EL5027
®
Data Sheet
May 4, 2007
Dual 2.5MHz Rail-to-Rail Input-Output
Buffer
Features
• 2.5MHz -3dB bandwidth
The EL5027 is a dual, low power, high voltage rail-to-rail
input-output buffer. Operating on supplies ranging from 5V to
15V, while consuming only 110µA per channel, the EL5027
has a bandwidth of 2.5MHz -(-3dB). The EL5027 also
provides rail-to-rail input and output ability, giving the
maximum dynamic range at any supply voltage.
The EL5027 also features fast slewing and settling times, as
well as a high output drive capability of 30mA (sink and
source). These features make the EL5027 ideal for use as
voltage reference buffers in Thin Film Transistor Liquid
Crystal Displays (TFT-LCD). Other applications include
battery power, portable devices, and anywhere low power
consumption is important.
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 110µA
• High slew rate = 1.2V/µs
• Rail-to-rail operation
• Pb-free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Electronics notebooks
The EL5027 is available in space-saving 6 Ld TSOT
package and operates over a temperature range of -40°C to
+85°C.
• Electronics games
Ordering Information
• Portable instrumentation
PART NUMBER
(Note)
EL5027IWTZ-T7
PART
MARKING
BVAA
EL5027IWTZ-T7A BVAA
FN7426.1
PACKAGE
(Pb-free)
TAPE &
REEL
PKG.
DWG. #
6 Ld TSOT-23
7” (3k pcs)
MDP0049
• Personal communication devices
• Personal Digital Assistants (PDA)
• Wireless LANs
• Office automation
• Active filters
6 Ld TSOT-23 7” (250 pcs) MDP0049
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020C.
• ADC/DAC buffer
Pinout
EL5027
(6 LD TSOT)
TOP VIEW
VINA 1
VS- 2
VINB 3
1
6 VOUTA
5 VS+
4 VOUTB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5027
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS+ +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
1
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 0V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
-4.5V ≤ VOUT ≤ 4.5V
0.995
µV/°C
50
nA
1.005
V/V
-4.85
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short-circuit Current
Short to GND
-4.92
4.85
4.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from ±2.25V to ±7.75V
IS
Supply Current (Per Buffer)
No load
55
110
160
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
tS
Settling to +0.1%
BW
CS
0.7
1.2
V/µs
VO = 2V step
900
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
2.5
MHz
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
2
FN7426.1
May 4, 2007
EL5027
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C Unless Otherwise Specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
1
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 2.5V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
0.5 ≤ VOUT ≤ 4.5V
0.995
µV/°C
50
nA
1.005
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short-circuit Current
Short to GND
80
4.85
4.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Buffer)
No load
55
110
160
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
1V ≤ VOUT ≤4V, 20% to 80%
tS
Settling to +0.1%
BW
CS
0.7
1.2
V/µs
VO = 2V Step
900
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
2.5
MHz
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
3
FN7426.1
May 4, 2007
EL5027
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = 25°C unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 7.5V
1
TCVOS
Average Offset Voltage Drift
(Note 1)
5
IB
Input Bias Current
VCM = 7.5V
2
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
1.35
pF
AV
Voltage Gain
0.5 ≤ VOUT ≤ 14.5V
0.995
µV/°C
50
nA
1.005
V/V
150
mV
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
Short-circuit Current
Short to GND
80
14.85
14.92
V
±120
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Buffer)
No load
55
110
160
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
1V ≤ VOUT ≤14V, 20% to 80%
tS
Settling to +0.1%
BW
CS
0.7
1.2
V/µs
VO = 2V Step
900
ns
-3dB Bandwidth
RL = 10kΩ, CL = 10pF
2.5
MHz
Channel Separation
f = 5MHz
75
dB
NOTES:
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
4
FN7426.1
May 4, 2007
EL5027
Typical Performance Curves
20
CL = 10pF
VS = ±5V
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
20
10
10kΩ
1kΩ
0
562Ω
-10
150Ω
-20
-30
1K
10K
100K
1M
RL = 10kΩ
VS = ±5V
10
100pF
-20
100K
1M
10M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL
MAXIMUM OUTPUT SWING (VP-P)
OUTPUT IMPEDANCE (Ω)
2000
TA = 25°C
VS = ±5V
1600
1200
800
400
100K
12
8
6
4
2
0
10K
1M
VS = ±5V
RL = 10kΩ
CL = 12pF
TA = 25°C
10
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 4. MAXIMUM OUTPUT SWING vs FREQUENCY
300
0.12
0.1
100
THD + NOISE (%)
VOLTAGE NOISE (nV/√Hz)
10K
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL
10K
1nF
-10
FREQUENCY (Hz)
0
1K
12pF
0
-30
1K
10M
47pF
0.06
0.04
0.02
10
1K
0.08
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 5. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
5
0
1K
10K
100K
FREQUENCY (Hz)
FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
FN7426.1
May 4, 2007
EL5027
Typical Performance Curves
(Continued)
100
16
14
70
60
50
40
12
10
8
6
30
4
20
2
0
10
FIGURE 7. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
10
8
6
4
2
0
-2
FIGURE 8. INPUT OFFSET VOLTAGE DISTRIBUTION
3.5
4.955
OUTPUT HIGH VOLTAGE (V)
VS = ±5V
3
2.5
2
1.5
VS = ±5V
IOUT = 5mA
4.95
4.945
4.94
4.935
4.93
4.925
1
-35
-15
5
25
45
65
85
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 10. OUTPUT HIGH VOLTAGE vs TEMPERATURE
-4.938
1.0045
VS = ±5V
IOUT = -5mA
VS = ±5V
1.004
-4.942
VOLTAGE GAIN (V/V)
OUTPUT LOW VOLTAGE (V)
-4
INPUT OFFSET VOLTAGE (mV)
CAPACITANCE (pF)
INPUT BIAS CURRENT (nA)
-6
1K
-8
0
100
-10
OVERSHOOT (%)
80
18
VS = ±5V
RL = 10kΩ
VIN = ±50mV
TA = 25°C
% OF BUFFERS
90
-4.946
-4.95
-4.954
1.0035
1.003
1.0025
1.002
1.0015
-4.958
1.001
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
FIGURE 11. OUTPUT LOW VOLTAGE vs TEMPERATURE
6
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
FIGURE 12. VOLTAGE GAIN vs TEMPERATURE
FN7426.1
May 4, 2007
EL5027
Typical Performance Curves
(Continued)
2.255
0.185
VS = ±5V
SUPPLY CURRENT (mA)
SLEW RATE (V/µs)
VS=±5V
2.245
2.235
2.225
2.215
-40
0.18
0.175
0.17
0.165
0.16
-20
0
20
40
80
60
-35
TEMPERATURE (°C)
-15
5
25
45
65
85
TEMPERATURE (°C)
FIGURE 13. SLEW RATE vs TEMPERATURE
FIGURE 14. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
0.195
SUPPLY CURRENT (mA)
TA = 25°C
0.19
0.185
0.18
1V/DIV
0.175
0.17
0.165
4
6
8
10
12
14
16
18
4µs/DIV
SUPPLY VOLTAGE (V)
FIGURE 15. SUPPLY CURRENT PER CHANNEL vs SUPPY
VOLTAGE
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
20mV/DIV
1µs/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
7
FN7426.1
May 4, 2007
EL5027
Pin Descriptions
6 LD TSOT
PIN NAME
1
VINA
FUNCTION
EQUIVALENT CIRCUIT
Buffer A Input
VS+
VSCIRCUIT 1
2
VS-
3
VINB
4
VOUTB
Negative Supply Voltage
Buffer B Input
(Reference Circuit 1)
Buffer B Output
VS+
VS-
GND
CIRCUIT 2
5
VS+
6
VOUTA
Positive Supply Voltage
Buffer A Output
(Reference Circuit 2)
Applications Information
The EL5027 unity gain buffer is fabricated using a high
voltage CMOS process. It exhibits rail-to-rail input and
output capability and has low power consumption (500µA
per buffer). These features make the EL5027 ideal for a wide
range of general-purpose applications. When driving a load
of 10kΩ and 12pF, the EL5027 has a -3dB bandwidth of
2.5MHz and exhibits 2.2V/µs slew rate.
Operating Voltage, Input, and Output
The EL5027 is specified with a single nominal supply voltage
from 5V to 15V or a split supply with its total range from 5V
to 15V. Correct operation is guaranteed for a supply range of
4.5V to 16.5V. Most EL5027 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
The output swings of the EL5027 typically extend to within
80mV of positive and negative supply rails with load currents
of 5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 1 shows
the input and output waveforms for the device. Operation is
from ±5V supply with a 10kΩ load connected to GND. The
input is a 10VP-P sinusoid. The output voltage is
approximately 9.985VP-P.
8
VS=±5V
TA=25°C
VIN=10VP-P
5V
INPUT
10µs
OUTPUT
5V
Product Description
FIGURE 18. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short-Circuit Current Limit
The EL5027 will limit the short-circuit current to ±120mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
Output Phase Reversal
The EL5027 is immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2
shows a photo of the output of the device with the input
voltage driven beyond the supply rails. Although the device's
FN7426.1
May 4, 2007
EL5027
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
1V
10µs
where:
i = 1 to 2 for dual buffer
VS = Total supply voltage
ISMAX = Maximum supply current per channel
VOUTi = Maximum output voltage of the application
ILOADi = Load current
VS=±2.5V
TA=25°C
VIN=6VP-P
1V
FIGURE 19. OPERATION WITH BEYOND-THE-RAILS INPUT
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figure 20
and Figure 21 provide a convenient way to see if the device
will overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves.
Unused Buffers
Power Dissipation
With the high-output drive capability of the EL5027 buffer, it
is possible to exceed the +125°C 'absolute-maximum
junction temperature' under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if load
conditions need to be modified for the buffer to remain in the
safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX - T AMAX
P DMAX = --------------------------------------------Θ JA
where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
ΘJA = Thermal resistance of the package
PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P DMAX = Σi [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ]
when sourcing, and:
P DMAX = Σi [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ]
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5027 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5Ω and 50Ω) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
"snubber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150Ω and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5027 can provide gain at high frequency. As with any
high frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1µF ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the buffer. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
when sinking.
9
FN7426.1
May 4, 2007
EL5027
TSOT Package Family
MDP0049
e1
D
TSOT PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
2X
1
5
2
(N/2)
0.25 C
2X N/2 TIPS
e
ddd M
B
C A-B D
b
NX
0.15 C A-B
1
3
D
2X
TSOT5
TSOT6
TSOT8
TOLERANCE
A
1.00
1.00
1.00
Max
A1
0.05
0.05
0.05
±0.05
A2
0.87
0.87
0.87
±0.03
b
0.38
0.38
0.29
±0.07
c
0.127
0.127
0.127
+0.07/-0.007
D
2.90
2.90
2.90
Basic
E
2.80
2.80
2.80
Basic
E1
1.60
1.60
1.60
Basic
e
0.95
0.95
0.65
Basic
e1
1.90
1.90
1.95
Basic
L
0.40
0.40
0.40
±0.10
L1
0.60
0.60
0.60
Reference
ddd
0.20
0.20
0.13
-
N
5
6
8
Reference
Rev. B 2/07
C
A2
SEATING
PLANE
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10 C
NOTES:
NX
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
(L1)
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
H
A
GAUGE
PLANE
c
L
6. TSOT5 version has no center lead (shown as a dashed line).
0.25
4° ±4°
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7426.1
May 4, 2007
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