EL5127CY-T13

EL5127, EL5227, EL5327, EL5427 ® Data Sheet May 4, 2007 2.5MHz 4-, 8-, 10- and 12-Channel Rail-toRail Buffers The EL5127, EL5227, EL5327, and EL5427 are low power, high voltage rail-to-rail input/output buffers designed for use in reference voltage buffering applications in small LCD displays. They are available in quad (EL5127), octal (EL5227), 10-Channel (EL5327), and 12-Channel (EL5427) topologies. All buffers feature a -3dB bandwidth of 2.5MHz and operate from just 133µA per buffer. This family also features a continuous output drive capability of 30mA (sink and source). The quad channel EL5127 is available in the 10 Ld MSOP package. The 8-Channel EL5227 is available in both the 20 Ld TSSOP and 24 Ld QFN packages, the 10-Channel EL5327 in the 24 Ld TSSOP and 24 Ld QFN packages, and the 12-Channel EL5427 in the 28 Ld TSSOP and 32 Ld QFN packages. All buffers are specified for operation over the full -40°C to +85°C temperature range. FN7111.4 Features • 2.5MHz -3dB bandwidth • Supply voltage = 4.5V to 16.5V • Low supply current (per buffer) = 133µA • High slew rate = 2.2V/µs • Rail-to-rail input/output swing • Ultra-small packages • Pb-free plus anneal available (RoHS compliant) Applications • TFT-LCD drive circuits • Electronic games • Touch-screen displays • Personal communication devices • Personal digital assistants (PDAs) • Portable instrumentation 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5127, EL5227, EL5327, EL5427 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5127CY R - 10 Ld MSOP (3.0mm) MDP0043 EL5127CY-T7 R 7” 10 Ld MSOP (3.0mm) MDP0043 EL5127CY-T13 R 13” 10 Ld MSOP (3.0mm) MDP0043 EL5127CYZ (Note) BAAAH - 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5127CYZ-T7 (Note) BAAAH 7” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5127CYZ-T13 (Note) BAAAH 13” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5227CL 5227CL - 24 Ld QFN (4mmx5mm) MDP0046 EL5227CL-T7 5227CL 7” 24 Ld QFN (4mmx5mm) MDP0046 EL5227CL-T13 5227CL 13” 24 Ld QFN (4mmx5mm) MDP0046 EL5227CLZ (Note) 5227CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5227CLZ-T7 (Note) 5227CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5227CLZ-T13 (Note) 5227CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5227CR 5227CR - 20 Ld TSSOP (4.4mm) MDP0044 EL5227CR-T7 5227CR 7” 20 Ld TSSOP (4.4mm) MDP0044 EL5227CR-T13 5227CR 13” 20 Ld TSSOP (4.4mm) MDP0044 EL5227CRZ (Note) 5227CRZ - 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5227CRZ-T7 (Note) 5227CRZ 7” 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5227CRZ-T13 (Note) 5227CRZ 13” 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5327CL 5327CL - 24 Ld QFN (4mmx5mm) MDP0046 EL5327CL-T7 5327CL 7” 24 Ld QFN (4mmx5mm) MDP0046 EL5327CL-T13 5327CL 13” 24 Ld QFN (4mmx5mm) MDP0046 EL5327CLZ (Note) 5327CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5327CLZ-T7 (Note) 5327CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5327CLZ-T13 (Note) 5327CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5327CR 5327CR - 24 Ld TSSOP (4.4mm) MDP0044 EL5327CR-T7 5327CR 7” 24 Ld TSSOP (4.4mm) MDP0044 EL5327CR-T13 5327CR 13” 24 Ld TSSOP (4.4mm) MDP0044 EL5327CRZ (Note) 5327CRZ - 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5327CRZ-T7 (Note) 5327CRZ 7” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5327CRZ-T13 (Note) 5327CRZ 13” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5427CL 5427CL - 32 Ld QFN (5mmx6mm) MDP0046 EL5427CL-T7 5427CL 7” 32 Ld QFN (5mmx6mm) MDP0046 EL5427CL-T13 5427CL 13” 32 Ld QFN (5mmx6mm) MDP0046 EL5427CLZ (Note) 5427CLZ - 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 EL5427CLZ-T7 (Note) 5427CLZ 7” 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 2 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Ordering Information (Continued) PART NUMBER PART MARKING TAPE & REEL EL5427CLZ-T13 (Note) 5427CLZ 13” EL5427CR 5427CR EL5427CR-T13 5427CR EL5427CRZ (Note) 5427CRZ EL5427CRZ-T7 (Note) EL5427CRZ-T13 (Note) PACKAGE PKG. DWG. # 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 - 28 Ld TSSOP (4.4mm) MDP0044 13” 28 Ld TSSOP (4.4mm) MDP0044 - 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 5427CRZ 7” 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 5427CRZ 13” 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Pinouts EL5427 (28 LD TSSOP) TOP VIEW EL5327 (24 LD TSSOP) TOP VIEW EL5227 (20 LD TSSOP) TOP VIEW EL5127 (10 LD MSOP) TOP VIEW VIN1 1 10 VOUT1 VIN1 1 20 VOUT1 VIN1 1 24 VOUT1 VIN1 1 28 VOUT1 VIN2 2 9 VOUT2 VIN2 2 19 VOUT2 VIN2 2 23 VOUT2 VIN2 2 27 VOUT2 8 VS- VIN3 3 18 VOUT3 VIN3 3 22 VOUT3 VIN3 3 26 VOUT3 VIN3 4 7 VOUT3 VIN4 4 17 VOUT4 VIN4 4 21 VOUT4 VIN4 4 25 VOUT4 VIN4 5 6 VOUT4 VS+ 5 16 VS- VIN5 5 20 VOUT5 VIN5 5 24 VOUT5 VS+ 6 15 VS- VS+ 6 19 VS- VIN6 6 23 VOUT6 VIN5 7 14 VOUT5 VS+ 7 18 VS- VS+ 7 22 VS- VIN6 8 13 VOUT6 VIN6 8 17 VOUT6 VS+ 8 21 VS- VIN7 9 12 VOUT7 VIN7 9 16 VOUT7 VIN7 9 20 VOUT7 VIN8 10 11 VOUT8 VIN8 10 15 VOUT8 VIN8 10 19 VOUT8 VIN9 11 14 VOUT9 VIN9 11 18 VOUT9 VIN10 12 13 VOUT10 VIN10 12 17 VOUT10 VIN11 13 16 VOUT11 VIN12 14 15 VOUT12 26 VOUT2 27 VOUT1 28 NC 31 VIN1 32 VIN2 20 VOUT2 21 VOUT1* 22 NC 23 VIN1* 24 VIN2 29 NC EL5427 (32 LD QFN) TOP VIEW EL5227, EL5327 (24 LD QFN) TOP VIEW 30 NC VS+ 3 VIN3 1 19 VOUT3 VIN3 1 25 VOUT3 VIN4 2 18 VOUT4 VIN4 2 24 VOUT4 17 VOUT5 VIN5 3 23 VOUT5 16 VS- VIN6 4 VIN5 3 THERMAL PAD VS+ 4 22 VOUT6 THERMAL PAD VIN8 7 19 VOUT8 VIN9 8 18 VOUT9 VIN10 9 17 VOUT10 4 VOUT11 16 21 VS- VOUT12 15 CVIN10* 9 * NOT AVAILABLE IN EL5227 NC 14 13 VOUT8 NC 13 VIN8 7 NC 12 20 VOUT7 VIN12 11 VIN7 6 VIN11 10 14 VOUT7 VOUT9 12 VIN7 6 VOUT10* 11 VS+ 5 NC 10 15 VOUT6 VIN9 8 VIN6 5 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage Between VS+ and VS-. . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ, CL = 10pF to 0V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 1 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain -4.5V ≤ VOUT ≤ 4.5V 0.99 µV/°C 50 nA 1.01 V/V -4.85 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA 4.85 4.95 V IOUT (max) Max Output Current (Note 2) RL = 10Ω 100 ±120 mA 55 80 dB -4.95 POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current No load (EL5127) 0.7 0.9 mA No load (EL5227) 1.2 1.4 mA No load (EL5327) 1.4 2 mA No load (EL5427) 1.6 2.2 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% tS Settling to +0.1% (AV = +1) BW CS 0.9 2.2 V/µs (AV = +1), VO = 2V step 900 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz Channel Separation f = 100kHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. 5 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 10kΩ, CL = 10pF to 2.5V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 1 TCVOS Average Offset Voltage Drift (Note 4) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5V ≤ VOUT ≤ 4.5V 0.99 µV/°C 50 nA 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA 4.85 4.95 V IOUT (max) Output Current (Note 5) RL = 10Ω 100 ±120 mA 55 80 dB 80 POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current No load (EL5127) 0.7 0.9 mA No load (EL5227) 1.1 1.35 mA No load (EL5327) 1.35 1.9 mA No load (EL5427) 1.5 2.05 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 6) 1V ≤ VOUT ≤ 4V, 20% to 80% tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step BW -3dB Bandwidth CS Channel Separation 0.9 1.5 V/µs 1000 ns RL = 10kΩ, CL = 10pF 2.5 MHz f = 5MHz 75 dB NOTES: 4. Measured over operating temperature range. 5. Instantaneous peak current. 6. Slew rate is measured on rising and falling edges. 6 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ, CL = 10pF to 7.5V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 18 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 1 TCVOS Average Offset Voltage Drift (Note 7) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5V ≤ VOUT ≤ 14.5V 0.99 µV/°C 50 nA 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA 14.85 14.95 V IOUT (max) Output Current (Note 8) RL = 10Ω 100 ±120 mA 55 80 dB 50 POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current No load (EL5127) 0.75 0.95 mA No load (EL5227) 1.3 1.55 mA No load (EL5327) 1.5 2.1 mA No load (EL5427) 1.6 2.4 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 9) 1V ≤ VOUT ≤ 14V, 20% to 80% tS Settling to +0.1% (AV = +1) BW CS 0.9 2.2 V/µs (AV = +1), VO = 2V step 900 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz Channel Separation f = 5MHz 75 dB NOTES: 7. Measured over operating temperature range. 8. Instantaneous peak current. 9. Slew rate is measured on rising and falling edges. 7 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves 20 CL=10pF VS=±5V NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) 20 10 10kΩ 1kΩ 0 562Ω -10 150Ω -20 -30 1K 10K 100K 1M RL=10kΩ VS=±5V 10 47pF 12pF 0 1nF -10 100pF -20 -30 1K 10M FREQUENCY (Hz) TA=25°C VS=±5V 10M 1600 1200 800 400 100K 12 10 8 6 4 2 VS=±5V RL=10kΩ CL=12pF TA=25°C 0 10K 1M 100K 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 4. MAXIMUM OUTPUT SWING vs FREQUENCY 300 0.12 0.1 100 THD + NOISE (%) VOLTAGE NOISE (nV/√Hz) 1M FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL MAXIMUM OUTPUT SWING (VP-P) OUTPUT IMPEDANCE (Ω) 2000 10K 100K FREQUENCY (Hz) FIGURE 1. FREQEUNCY RESPONSE FOR VARIOUS RL 0 1K 10K 0.06 0.04 0.02 10 1K 0.08 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 5. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 8 0 1K 10K 100K FREQUENCY (Hz) FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves 14 70 60 50 40 12 10 8 6 30 4 20 2 FIGURE 7. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE 10 8 6 4 2 FIGURE 8. INPUT OFFSET VOLTAGE DISTRIBUTION 3.5 4.955 OUTPUT HIGH VOLTAGE (V) VS=±5V INPUT BIAS CURRENT (nA) 0 INPUT OFFSET VOLTAGE (mV) CAPACITANCE (pF) 3 2.5 2 1.5 VS=±5V IOUT=5mA 4.95 4.945 4.94 4.935 4.93 4.925 1 -35 -15 5 25 45 65 -35 85 -15 5 25 45 65 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 10. OUTPUT HIGH VOLTAGE vs TEMPERATURE -4.938 1.0045 VS=±5V IOUT=-5mA VS=±5V 1.004 -4.942 VOLTAGE GAIN (V/V) OUTPUT LOW VOLTAGE (V) -2 1K -4 100 -6 0 0 10 -10 OVERSHOOT (%) 80 16 -8 90 18 VS=±5V RL=10kΩ VIN=±50mV TA=25°C % OF BUFFERS 100 -4.946 -4.95 -4.954 1.0035 1.003 1.0025 1.002 1.0015 -4.958 1.001 -35 -15 5 25 45 65 85 TEMPERATURE (°C) FIGURE 11. OUTPUT LOW VOLTAGE vs TEMPERATURE 9 -35 -15 5 25 45 65 85 TEMPERATURE (°C) FIGURE 12. VOLTAGE GAIN vs TEMPERATURE FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves 2.255 0.185 SUPPLY CURRENT (mA) SLEW RATE (V/µs) VS=±5V 2.245 2.235 2.225 VS=±5V 2.215 -40 -20 0.18 0.175 0.17 0.165 0.16 0 20 40 80 60 -35 -15 TEMPERATURE (°C) 5 25 45 65 85 TEMPERATURE (°C) FIGURE 13. SLEW RATE vs TEMPERATURE FIGURE 14. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE 0.195 SUPPLY CURRENT (mA) TA=25°C 0.19 0.185 0.18 1V/DIV 0.175 0.17 0.165 4 6 8 10 12 14 16 18 4µs/DIV SUPPLY VOLTAGE (V) FIGURE 15. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 3 POWER DISSIPATION (W) 2.857W 20mV/DIV 2.5 2.703W QFN32 θJA=35°C/W 2 QFN24 θJA=37°C/W 1.5 1 870mW 0.5 MSOP10 θJA=115°C/W 0 1µs/DIV 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE 10 FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.8 1.333W 1.2 758mW 1.176W 1 1.111W POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 TSSOP24 θJA=85°C/W 0.8 TSSOP28 θJA=75°C/W 0.6 TSSOP20 θJA=90°C/W 0.4 0.2 0.7 714mW QFN32 θJA=132°C/W 0.6 0.5 486mW 0.4 0.3 QFN24 θJA=140°C/W MSOP10 θJA=206°C/W 0.2 0.1 0 0 0 25 50 75 85 100 0 125 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 833mW POWER DISSIPATION (W) 0.8 781mW 0.7 714mW TSSOP28 θJA=120°C/W 0.6 0.5 TSSOP24 θJA=128°C/W 0.4 0.3 0.2 TSSOP20 θJA=140°C/W 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Applications Information Product Description The EL5127, EL5227, EL5327, and EL5427 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (120µA per buffer). These features make the EL5127, EL5227, EL5327, and EL5427 ideal for a wide range of general-purpose applications. When driving a load of 10kΩ and 12pF, the EL5127, EL5227, EL5327, and EL5427 have a -3dB bandwidth of 2.5MHz and exhibits 2.2V/µs slew rate. temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5127, EL5227, EL5327, and EL5427 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 22 shows the input and output waveforms for the device. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. Operating Voltage, Input, and Output The EL5127, EL5227, EL5327, and EL5427 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5127, EL5227, EL5327, and EL5427 specifications are stable over both the full supply range and operating 11 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 5V application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. 10µs VS=±5V TA=25°C VIN=10VP-P 5V OUTPUT INPUT The maximum power dissipation allowed in a package is determined according to: FIGURE 22. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT T JMAX - T AMAX P DMAX = --------------------------------------------Θ JA where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package Short Circuit Current Limit The EL5127, EL5227, EL5327, and EL5427 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: Output Phase Reversal when sourcing, and: The EL5127, EL5227, EL5327, and EL5427 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 23 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. P DMAX = Σi [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ] PDMAX = Maximum power dissipation in the package P DMAX = Σi [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ] when sinking. where: i = 1 to Total number of buffers VS = Total supply voltage ISMAX = Maximum quiescent current per channel 1V 10µs VOUTi = Maximum output voltage of the application ILOADi = Load current VS=±2.5V TA=25°C VIN=6VP-P 1V FIGURE 23. OPERATION WITH BEYOND-THE-RAILS INPUT If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. Power Dissipation Unused Buffers With the high-output drive capability of the EL5127, EL5227, EL5327, and EL5427 buffer, it is possible to exceed the +125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the It is recommended that any unused buffer have the input tied to the ground plane. 12 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Driving Capacitive Loads The EL5127, EL5227, EL5327, and EL5427 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ pin to VS- pin. A 4.7µF tantalum capacitor should then be connected from VS+ pin to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. 13 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 14 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN3 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN2 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 15 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X 16 FN7111.4 May 4, 2007 EL5127, EL5227, EL5327, EL5427 Thin Shrink Small Outline Plastic Packages (TSSOP) M20.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 0.25 0.010 SEATING PLANE L A D -C- α e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 20 0o 20 7 8o Rev. 1 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7111.4 May 4, 2007