EL5132IS-T13

EL5132, EL5133 ® Data Sheet May 4, 2007 670MHz Low Noise Amplifiers Features The EL5132 and EL5133 are ultra-low voltage noise, high speed voltage feedback amplifiers that are ideal for applications requiring low voltage noise, including communications and imaging. These devices offer extremely low power consumption for exceptional noise performance. Stable at gains as low as 10, these devices offer 120mA of drive performance. Not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. • 670MHz -3dB bandwidth These amplifiers are available in small package options (SOT-23) as well as the industry-standard SOIC packages. All parts are specified for operation over the -40°C to +85°C temperature range. FN7382.8 • Ultra low noise 0.9nV/√Hz • 1000V/µs slew rate • Low supply current = 12mA • Single supplies from 5V to 12V • Dual supplies from ±2.5V to ±6V • Fast disable on the EL5132 • Pb-free plus anneal available (RoHS compliant) Applications • Pre-amplifier Pinout • Receiver EL5132 (8 LD SOIC) TOP VIEW NC 1 IN- 2 IN+ 3 + • Filter • IF and baseband amplifier 8 CE • ADC drivers 7 VS+ • DAC buffers 6 OUT VS- 4 5 NC • Instrumentation • Communications devices EL5133 (5 LD SOT-23) TOP VIEW OUT 1 VS- 2 5 VS+ + - IN+ 3 4 IN- 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5132, EL5133 Ordering Information PART NUMBER part marking TAPE AND REEL PACKAGE PKG. DWG. # EL5132IS 5132IS - 8 Ld SOIC (150 mil) MDP0027 EL5132IS-T7 5132IS 7” 8 Ld SOIC (150 mil) MDP0027 EL5132IS-T13 5132IS 13” 8 Ld SOIC (150 mil) MDP0027 EL5132ISZ (Note) 5132ISZ - 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5132ISZ-T7 (Note) 5132ISZ 7” 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5132ISZ-T13 (Note) 5132ISZ 13” 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5133IW-T7 BCAA 7” (3k pcs) 5 Ld SOT-23 MDP0038 EL5133IW-T7A BCAA 7” (250 pcs) 5 Ld SOT-23 MDP0038 EL5133IWZ BSAA - 5 Ld SOT-23 (Pb-free) MDP0038 EL5133IWZ-T7 (Note) BSAA 7” (3k pcs) 5 Ld SOT-23 (Pb-free) MDP0038 EL5133IWZ-T7A (Note) BSAA 7” (250 pcs) 5 Ld SOT-23 (Pb-free) MDP0038 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7382.8 May 4, 2007 EL5132, EL5133 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . 13.2V Slewrate between VS+ and VS- . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs IIN-, IIN+, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS VS+ = +5V, VS- = -5V, RL = 500Ω, RF = 900Ω, RG = 100Ω, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS Offset Voltage MIN TYP MAX UNIT -1 0.5 1 mV TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V 8 12 20 IOS Input Offset Current VIN = 0V -1250 400 +1250 TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX PSRR Power Supply Rejection Ratio VS+ = ±4.75V to ±5.25V CMRR Common Mode Rejection Ratio VIN = ±3.0 V CMIR Common Mode Input Range Guaranteed by CMRR test RIN Input Resistance Common mode 2 CIN Input Capacitance IS Supply Current AVOL Open Loop Gain VO Output Voltage Swing RF = 900Ω, RG = 100Ω, RL = 150Ω ISC Short Circuit Current RL = 10Ω VOUT = ±2.5V, RL = 1kΩ to GND 0.8 µV/°C µA nA 3 nA/°C 87 dB 80 100 dB ±3 ±3.3 V 5 MΩ 2 pF 75 9.2 11 5 8.5 13 mA ±3.1 ±3.5 V 70 140 mA KV/V BW -3dB Bandwidth RF = 225Ω, AV = +10, RL = 1kΩ 670 MHz BW ±0.1dB Bandwidth RF = 225Ω, AV = +10, RL = 1kΩ 90 MHz GBWP Gain Bandwidth Product 3000 MHz PM Phase Margin RL = 1kΩ, CL = 6pF 55 ° 1000 V/µs 2.0 ns SR Slew Rate RL = 100Ω, VOUT = ±2.5V tR, tF Rise Time, Fall Time ±0.1VSTEP ±0.1VSTEP OS Overshoot tS 0.01% Settling Time 700 10 % 6.6 ns dG Differential Gain RF = 1kΩ, RLoad = 150Ω 0.01 % dP Differential Phase RF = 1kΩ, RLoad = 150Ω 0.01 ° eN Input Noise Voltage f = 10kHz 0.9 nV/√Hz iN Input Noise Current f = 10kHz 3.5 pA/√Hz 220 nS 175 nS ENABLE (EL5132 Only) tEN Enable Time tDIS Disable Time VIHCE CE Input High Voltage for Power-down VILCE CE Input Low Voltage for Power-up IS-OFF Supply Current - Disabled No Load, CE = 4V IIL-CE CE Pin Input Low Current CE = VS- IIH-CE CE Pin Input High Current CE = VS+ 3 VS+ - 1 V 13 -1 VS+ - 3 V 25 µA 0 1 µA 14 25 µA FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves NORMALIZED GAIN (dB) 3 2 300 5 240 4 NORMALIZED GAIN (dB) VS = ±5V AV = +10 RG = 25 RL = 500Ω CL = +1pF 4 180 120 GAIN 1 60 0 0 -60 -1 PHASE (°) 5 -120 -2 PHASE -3 -180 3 2 1 0 -1 -2 -3 -4 -240 -4 -5 100k -300 -5 100k 1M 10M 100M 1G -3dB BW @ 700MHz 1M FREQUENCY (Hz) 5 0.4 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0.5 0.3 0.1dB BW @ 30MHz 0.1 0 -0.1 -0.2 -0.3 2 0 -1 -2 AV = +30 -3 -0.5 100k -5 100k 100M VS = ±5V RL = 500Ω 60 50 40 FREQUENCY = 31.6MHz GAIN = 40dB or 100 GAIN BW PRODUCT = 31.6 x 100 = 3160MHz 30 20 1.0 10.0 100.0 FREQUENCY (MHz) FIGURE 5. GAIN BANDWIDTH PRODUCT 4 AV = +20 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS +AV GAIN-BANDWIDTH PRODUCT (MHz) 70 AV = +10 1 -4 FIGURE 3. 0.1dB BANDWIDTH GAIN (dB) 3 VS = ±5V RG = 25Ω RL = 500Ω CL = +1pF -0.4 10M FREQUENCY (Hz) 1G FIGURE 2. -3dB BANDWIDTH FIGURE 1. GAIN & PHASE vs FREQUENCY 0.2 10M 100M FREQUENCY (Hz) 4000 3500 VS = ±5V RL = 500Ω 3000 2500 2000 1500 1000 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (±V) FIGURE 6. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves (Continued) NORMALIZED GAIN (dB) 4 3 2 5 AV = +10 RG = 25Ω RL = 500Ω CL = +1pF 4 NORMALIZED GAIN (dB) 5 VS=±4 1 0 -1 VS = ±6 -2 VS = ±5V -3 VS = ±3V -4 -5 100k 10M 100M 2 0 -1 -2 RL=100Ω RL=150Ω -3 RL=500Ω -5 100k 1G 1M FREQUENCY (Hz) 3 2 4 RL=1kΩ 1 0 -1 RL=500Ω RL=150Ω -3 RL=100Ω -4 -5 100k 1M 10M 100M FREQUENCY (Hz) 1 CL= 23pF CL= 12pF 0 -1 -2 CL=1pF 0 -1 CL= 1pF -2 -3 4 3 2 100M 1G 0 -2 FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +20) RF = 90Ω -3 -5 100k 1G RF = 900Ω RF = 450Ω -1 -5 100k 5 10M 1 -4 10M 100M FREQUENCY (Hz) 1M VS = ±5V AV = +10 RL = 500Ω CL = +1pF -4 1M CL=6.8pF FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +10) CL=39pF -3 CL= 12pF 1 5 VS = ±5V AV = +20 RG = 25Ω RF = 475 RL = 500Ω CL=3.3pF FREQUENCY (Hz) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 2 -5 100k 1G 5 3 3 VS = ±5V AV = +10 RG = 25Ω RF = 225Ω RL = 500Ω -4 FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +20) 4 1G 5 VS = ±5V AV = +20 RG = 25Ω CL = +1pF -2 100M FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +10) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10M FREQUENCY (Hz) FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±VS 5 RL = 1kΩ 1 -4 VS = ±2.5V 1M 3 VS = ±5V AV = +10 RG = 25Ω CL = +1pF RF = 225Ω 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +10) FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves (Continued) 5 5 2 RF = 1.9kΩ 1 0 -1 -2 RF = 953Ω RF = 190Ω -3 RF = 475Ω -4 -5 100k VS = ±5V AV = +10 RG = 25Ω RL = 500Ω CL = +1pF 4 1M 10M 100M 3 2 0 -1 CIN = 2.2pF -2 CIN = 0pF -3 -4 -5 100k 1G FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +20) 1M 2 90 CIN = 22pF CIN = 15pF CIN = 12pF 1 0 -1 CIN = 8.2pF -2 -3 CIN = 0pF -4 -5 100k 300 240 70 180 60 120 50 60 OPEN LOOP PHASE 40 0 30 -60 OPEN LOOP GAIN 20 -120 10 -180 0 -240 -10 1M 10M 100M FREQUENCY (Hz) 1G -300 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS CIN (AV = +20) FIGURE 16. OPEN LOOP GAIN AND PHASE vs FREQUENCY 100 -10 VS = ±5V -20 -30 10 CMRR (dB) OUTPUT IMPEDANCE (Ω) 1G Vs = ±5V 80 OPEN LOOP GAIN (dB) NORMALIZED GAIN (dB) 3 10M 100M FREQUENCY (Hz) FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +10) 5 VS = ±5V AV = +20 RG = 25Ω RL = 500Ω CL = +1pF CIN = 3.9pF 1 FREQUENCY (Hz) 4 CIN = 6.8pF PHASE (°) 3 VS = ±5V AV = +20 RL = 500Ω CL = +1pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 1 AV = +10 VS = ±5V -40 -50 -60 -70 -80 0.10 -90 -100 0.01 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 17. OUTPUT IMPEDANCE vs FREQUENCY 6 -110 1k 10k 100k 1M 10M 100M 500M FREQUENCY (Hz) FIGURE 18. CMRR vs FREQUENCY FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves (Continued) 5 10 0 PSRR (dB) -10 OUTPUT SWING GAIN (dB) AV = +10 VS = ±5V -20 -30 -40 -50 VS- -60 -70 VS+ -80 -90 1k VS = ±5V AV = +10 RG = 25Ω RL = 500Ω CL = +1pF 4 3 2 1 0 -1 VOUT = 670mVP-P -2 VOUT = 2.1VP-P -3 VOUT = 3.8VP-P -4 VOUT = 6.6VP-P -5 10k 100k 1M 10M 1M 100M 500M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) VS = ±5V AV = +20 RG = 25 CHIP DISABLED -50 -60 ISOLATION (dB) GROUP DELAY (ns) -40 VS = ±5V AV = +10 RG = 25Ω RL = 500Ω -70 -80 INPUT TO OUTPUT -90 OUTPUT TO INPUT -100 -110 -120 -130 0 1M 10M 100M -140 100k 1G 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 21. GROUP DELAY vs FREQUENCY FIGURE 22. INPUT AND OUTPUT ISOLATION -20 VS = ±5V -40 AV = +10 RG = 25Ω -50 RL = 500Ω VOUT = 2VP-P THD -60 -70 -80 2nd HD 3rd HD -90 HARMONIC DISTORTION (dBc) -30 HARMONIC DISTORTION (dBc) 1G FIGURE 20. OUTPUT SWING vs FREQUENCY FIGURE 19. PSRR vs FREQUENCY 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 VOUT = 240mVP-P VS = ±5V AV = +10 RG = 25Ω RL = 500Ω -30 -40 -50 FIN = 10MHz -60 -70 -80 -90 FIN = 1MHz -100 -100 0M 5M 10M 15M 20M 25M 30M 35M 40M FUNDAMENTAL FREQUENCY (Hz) FIGURE 23. HARMONIC DISTORTION vs FREQUENCY 7 0 1 2 3 4 5 6 OUTPUT LEVEL (VP-P) 7 8 FIGURE 24. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves (Continued) 6 4 VS = ±5V RL = 500Ω VOUT = 2VP-P 5 ENABLE SIGNAL AMPLITUDE (V) AMPLITUDE (V) 6 VS = ±5V RL = 500Ω VOUT = 2VP-P 5 3 2 1 0 4 DISABLE SIGNAL 3 OUTPUT SIGNAL 2 1 0 -1 -1 OUTPUT SIGNAL -2 -3 -400 -200 0 200 400 600 800 -2 -1000 -800 -600 -400 -200 0 TIME (ns) 1000 1200 TIME (ns) CURRENT NOISE (pA/√Hz) 1.0 0.1 VS = ±5V 10.0 1.0 0.1 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 27. EQUIVALENT INPUT VOLTAGE NOISE vs FREQUENCY AMPLITUDE (V) 600 100.0 10 0.4 2.0 0.2 1.0 TFALL= 2.02ns 0.0 TRISE = 2.12ns -0.2 -0.4 -40 -20 0 VS = ±5V RL = 500Ω AV = +10 CL = +1pF RG = 25Ω VOUT = 500mV 20 40 60 80 100 120 140 160 180 TIME (ns) FIGURE 29. SMALL SIGNAL STEP RESPONSE_RISE AND FALL TIME 8 100 1k 10k 100k FREQUENCY (Hz) 1M FIGURE 28. EQUIVALENT INPUT CURRENT NOISE vs FREQUENCY AMPLITUDE (V) VOLTAGE NOISE (nV/√Hz) 1000.0 VS = ±5V 10.0 0.0 10 400 FIGURE 26. DISABLE TIME FIGURE 25. ENABLE TIME 100.0 200 TFALL = 2.05ns 0.0 TRISE = 2.02ns -1.0 -2.0 -40 -20 0 VS = ±5V RL = 500Ω AV = +10 CL = 1pF RG = 25Ω VOUT = 2.0V 20 40 60 80 100 120 140 160 180 TIME (ns) FIGURE 30. LARGE SIGNAL STEP RESPONSE_RISE AND FALL TIME FN7382.8 May 4, 2007 EL5132, EL5133 Typical Performance Curves (Continued) 1200 RG = 25Ω RL = 500Ω CL = +1pF 11.8 11.6 1000 11.4 11.2 11.0 10.8 10.6 Please note that the curve showed positive current. The negative current was almost the same. 10.4 10.2 10.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 700 6.0 500 300 2.0 0.6 SO8 θJA = +110°C/W 435mW 0.4 SOT23-5 θJA = +230°C/W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 9 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGES (±V) 5.5 6.0 FIGURE 32. SLEW RATE vs SUPPLY VOLTAGES 1 1.2 0.8 AV = +10 RG = 25Ω RL = 500Ω CL = +1pF VOUT = 4VP-P 600 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 909mW NEGATIVE SLEW RATE 800 POWER DISSIPATION (W) POWER DISSIPATION (W) 900 400 FIGURE 31. SUPPLY CURRENT vs SUPPLY VOLTAGE 1.4 POSITIVE SLEW RATE 1100 SLEW RATE (V/µs) SUPPLY CURRENT (mA) 12.0 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 0.7 625mW 0.6 SO8 θJA = +160°C/W 0.5 391mW 0.4 0.3 0.2 SOT23-5 θJA = +256°C/W 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7382.8 May 4, 2007 EL5132, EL5133 DIFFERENTIAL GAIN (%) Typical Performance Curves (Continued) 0.2 0.1 0.0 0 -0.05 -0.15 -0.20 0 10 20 30 40 50 60 70 80 90 100 DIFFERENTIAL PHASE (°) FIGURE 35. DIFFERENTIAL GAIN (%) 0.20 0.15 0.05 0 -0.05 -0.15 -0.20 0 10 20 30 40 50 60 70 80 90 100 FIGURE 36. DIFFERENTIAL PHASE (°) Applications Information Product Description The EL5132, EL5133 is a voltage feedback operational amplifier designed for communication and imaging applications requiring very low voltage and current noise. It also features low distortion while drawing moderately low supply current and is built on Intersil's proprietary high-speed complementary bipolar process. The EL5132, EL5133 uses a classical voltage-feedback topology which allows them to be used in a variety of applications where current-feedback amplifiers are not appropriate because of restrictions placed upon the feedback element used with the amplifier. Gain-Bandwidth Product and the -3dB Bandwidth The EL5132, EL5133 has a gain-bandwidth product of 3000MHz while using only 11mA of supply current. For gains greater than 10, their closed-loop -3dB bandwidth is approximately equal to the gain-bandwidth product divided by the noise gain of the circuit. For gains of 10, higher-order poles in the amplifiers' transfer function contribute to even higher closed loop bandwidths. For example, the EL5132, EL5133 have a -3dB bandwidth of 670MHz at a gain of 10, dropping to 150MHz at a gain of 30. It is important to note that the EL5132, EL5133 is designed so that this “extra” bandwidth in low-gain application does not come at the expense of stability. As seen in the typical performance curves, the EL5132, EL5133 in a gain of only 10 exhibited 0.5dB of peaking with a 500Ω load. 10 Output Drive Capability The EL5132 and EL5133 are is designed to drive a low impedance load. It can easily drive 6VP-P signal into a 500Ω load. This high output drive capability makes the EL5132, EL5133 an ideal choice for RF, IF, and video applications. Furthermore, the EL5132, EL5133 is current-limited at the output, allowing it to withstand momentary short to ground. However, the power dissipation with output-shorted cannot exceed the power dissipation capability of the package. Driving Cables and Capacitive Loads Although the EL5132, EL5133 is designed to drive low impedance load, capacitive loads will decreases the amplifier's phase margin. As shown in the performance curves, capacitive load can result in peaking, overshoot and possible oscillation. For optimum AC performance, capacitive loads should be reduced as much as possible or isolated with a series resistor between 5Ω to 20Ω. When driving coaxial cables, double termination is always recommended for reflection-free performance. When properly terminated, the capacitance of the coaxial cable will not add to the capacitive load seen by the amplifier. Disable/Power-Down The EL5132 amplifier can be disabled placing its output in a high impedance state. When disable, the amplifier current is reduced to 12µA. The EL5132 is disabled when it CE pin is pulled up to within 1V of the power supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least 3V below the positive supply. For ±5V supply, this means that an EL5132 amplifier will be enabled when CE is 2V or FN7382.8 May 4, 2007 EL5132, EL5133 less, and disabled when CE is above 4V. Although the logic levels are not standard TTL, this choice of logic voltages allows the EL5132 to be enabled by typing CE to ground, even in 5V single supply applications. The CE pin can be driving from CMOS outputs. where: Supply Voltage Range and Single-Supply Operation • VS = Supply voltage The EL5132 and EL5133 have been designed to operate with supply voltages having a span of greater than 5V and less than 12V. In practical terms, this means that they will operate on dual supplies ranging from ±2.5V to ±6V. With single-supply, the EL5132 and EL5133 will operate from 5V to 12V. To prevent internal circuit latch-up, the slew rate between the negative and positve supplies must be less than 1V/µs. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL5132 and EL5133 have an input range which extends to within 2V of either supply. So, for example, on ±5V supplies, the EL5132 and EL5133 have an input range which spans ±3V. The output range of the EL5132 and EL5133 are also quite large, extending to within 2V of the supply rail. On a ±5V supply, the output is therefore capable of swinging from -3.1V to +3.1V. Single-supply output range is larger because of the increased negative swing due to the external pulldown resistor to ground. Power Dissipation With the wide power supply range and large output drive capability of the EL5132 and EL5133, it is possible to exceed the 150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified for the EL5132 and EL5133 to remain in the safe operating area. These parameters are related as follows: T JMAX = T MAX + ( θ JA xPD MAXTOTAL ) • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • IMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Power Supply Bypassing And Printed Circuit Board Layout As with any high frequency devices, good printed circuit board layout is essential for optimum performance. Ground plane construction is highly recommended. Pin lengths should be kept as short as possible. The power supply pins must be closely bypassed to reduce the risk of oscillation. The combination of a 4.7µF tantalum capacitor in parallel with 0.1µF ceramic capacitor has been proven to work well when placed at each supply pin. For single supply operation, where pin 4 (VS-) is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor across pin 8 (VS+). For good AC performance, parasitic capacitance should be kept to a minimum. Ground plane construction again should be used. Small chip resistors are recommended to minimize series inductance. Use of sockets should be avoided since they add parasitic inductance and capacitance which will result in additional peaking and overshoot. (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated as follows: V OUTMAX PD MAX = 2*V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R (EQ. 2) L 11 FN7382.8 May 4, 2007 EL5132, EL5133 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 12 FN7382.8 May 4, 2007 EL5132, EL5133 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 0.25 0° +3° -0° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7382.8 May 4, 2007