EL5174ISZ-T13

DATASHEET EL5174, EL5374 FN7313 Rev 9.00 August 12, 2015 550MHz Differential Twisted-Pair Drivers The EL5174 and EL5374 are single and triple high bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs can be in either single-ended or differential form but the outputs are always in differential form. On the EL5174 and EL5374, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of one). For a fixed gain of two, please see the EL5173, EL5373 data sheet (FN7312). The output common mode level for each channel is set by the associated REF pin, which has a -3dB bandwidth of over 110MHz. Generally, these pins are grounded but can be tied to any voltage reference. All outputs are short circuit protected to withstand temporary overload condition. The EL5174 is available in a 8 Ld SOIC package and the EL5374 is available in a 28 Ld QSOP package. All are specified for operation over the full -40°C to +85°C temperature range. Features • Fully differential inputs, outputs, and feedback • Differential input range ±2.3V • 550MHz 3dB bandwidth • 1100V/µs slew rate • Low distortion at 5MHz • Single 5V or dual ±5V supplies • 60mA maximum output current • Low power - 12.5mA per channel • Pb-free (RoHS compliant) Applications • Twisted-pair driver • Differential line driver • VGA over twisted-pair • ADSL/HDSL driver • Single-ended to differential amplification • Transmission of analog signals in a noisy environment Pinouts EL5374 (28 LD QSOP) TOP VIEW EL5174 (8 LD SOIC) TOP VIEW FBP 1 IN+ 2 REF 3 FBN 4 8 OUT+ + - NC 1 7 VS- INP1 2 6 VS+ INN1 3 5 OUT- REF1 4 + - 27 FBP1 26 FBN1 25 OUT1B NC 5 24 VSP INP2 6 23 VSN INN2 7 22 OUT2 REF2 8 NC 9 + - 21 FBP2 20 FBN2 INP3 10 19 OUT2B INN3 11 18 OUT3 REF3 12 NC 13 EN 14 FN7313 Rev 9.00 August 12, 2015 28 OUT1 + - 17 FBP3 16 FBN3 15 OUT3B Page 1 of 15 EL5174, EL5374 Pin Descriptions EL5174 EL5374 PIN NAME 1 PIN FUNCTION FBP Feedback from non-inverting output 2 IN+ Non-inverting input 3 REF Inverting inputs, note that on EL5174, this pin is also the REF pin 4 FBN Feedback from inverting output 5 OUT- Inverting output 6 VS+ Positive supply 7 VS- Negative supply 8 OUT+ 17, 21, 27 Non-inverting output FBP3, FBP2, FBP1 Feedback from non-inverting outputs 2, 6, 10 INP1, INP2, INP3 Non-inverting inputs 3, 7, 11 INN1, INN2, INN3 Inverting inputs, note that on EL5174, this pin is also the REF pin 16, 20, 26 FBN3, FBN2, FBN1 Feedback from inverting outputs 15, 19, 25 OUT3B, OUT2B, OUT1B Inverting outputs 24 VSP Positive supply 23 VSN Negative supply 18, 22, 28 OUT3, OUT2, OUT1 1, 5, 9, 13 NC No connect; grounded for best crosstalk performance 4, 8, 12 REF1, REF2, REF3 Reference inputs, sets common-mode output voltage 14 EN Non-inverting outputs ENABLE Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # EL5174ISZ 5174ISZ -40 to +85 8 Ld SOIC M8.15E EL5374IUZ (No longer available, recommended replacement: EL5373IUZ) EL5374IUZ -40 to +85 28 Ld QSOP M28.15 NOTE: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL5174, EL5374. For more information on MSL please see tech brief TB363. FN7313 Rev 9.00 August 12, 2015 Page 2 of 15 EL5174, EL5374 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Input Voltage (IN+, IN- to VS+, VS-) . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Thermal Resistance (Typical, Note 4) JA (°C/W) 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120.40 28 Ld QSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.61 Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications specified. PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, unless otherwise DESCRIPTION CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNIT AC PERFORMANCE BW BW SR -3dB Bandwidth AV = 1, CLD = 2.7pF 550 MHz AV = 2, RF = 500, CLD = 2.7pF 130 MHz AV = 10, RF = 500, CLD = 2.7pF 20 MHz ±0.1dB Bandwidth AV = 1, CLD = 2.7pF 120 MHz Slew Rate (EL5174) VOUT = 3VP-P, 20% to 80% 800 1100 V/µs Slew Rate (EL5374) VOUT = 3VP-P, 20% to 80% 600 850 V/µs tSTL Settling Time to 0.1% VOUT = 2VP-P 10 ns tOVR Output Overdrive Recovery Time 20 ns GBWP Gain Bandwidth Product 200 MHz VREFBW (-3dB) VREF -3dB Bandwidth AV = 1, CLD = 2.7pF 110 MHz VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 134 V/µs VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 70 V/µs VN Input Voltage Noise at 10kHz 21 nV/Hz IN Input Current Noise at 10kHz 2.7 pA/Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz -95 dBc VOUT = 2VP-P, 20MHz -94 dBc HD3 Third Harmonic Distortion VOUT = 2VP-P, 5MHz -88 dBc -87 dBc dG Differential Gain at 3.58MHz RLD = 300, AV = 2 0.06 % d Differential Phase at 3.58MHz RLD = 300, AV = 2 0.13 ° eS Channel Separation - for EL5374 only at f = 1MHz 90 dB VOUT = 2VP-P, 20MHz INPUT CHARACTERISTICS VOS Input Referred Offset Voltage (EL5174) IIN Input Bias Current (VIN+, VIN-) -30 IREF Input Bias Current (VREF) 0.5 RIN Differential Input Resistance (EL5374) FN7313 Rev 9.00 August 12, 2015 ±1.4 ±25 mV ±2.2 ±25 mV -14 -7 µA 2.3 4 µA 150 k Page 3 of 15 EL5174, EL5374 Electrical Specifications specified. (Continued) PARAMETER CIN VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, unless otherwise DESCRIPTION CONDITIONS MIN (Note 5) Differential Input Capacitance DMIR Differential Mode Input Range CMIR+ Common Mode Positive Input Range at VIN+, VIN- TYP MAX (Note 5) 1 ±2.1 ±2.3 pF ±2.5 3.4 CMIR- Common Mode Negative Input Range at VIN+, VIN- VREFIN + Positive Reference Input Voltage Range (EL5374) VIN+ = VIN- = 0V VREFIN - Negative Reference Input Voltage Range (EL5374) VIN+ = VIN- = 0V VREFOS Output Offset Relative to VREF (EL5374) CMRR Input Common Mode Rejection Ratio (EL5374) VIN = ±2.5V Gain Gain Accuracy 3.4 UNIT V V -4.3 V 3.7 V -3.3 -3 V ±50 ±100 mV 65 78 dB VIN = 1V (EL5174) 0.980 0.995 1.010 V VIN = 1V (EL5374) 0.978 0.993 1.008 V OUTPUT CHARACTERISTICS VOUT Output Voltage Swing IOUT(Max) Maximum Output Current ROUT Output Impedance RL = 500 to GND (EL5174) ±3.4 RL = 500 to GND (EL5374) ±3.6 ±3.8 RL = 10, VIN+ = ±3.2V ±50 ±60 V V ±100 130 mA m SUPPLY VSUPPLY Supply Operating Range IS(ON) Power Supply Current - Per Channel IS(OFF)+ Positive Power Supply Current - Disabled (EL5374) IS(OFF)- Negative Power Supply Current - Disabled (EL5374) PSRR Power Supply Rejection Ratio VS+ to VS- 4.75 10 EN pin tied to 4.8V VS from ±4.5V to ±5.5V 11 V 12.5 14 mA 1.7 10 µA -200 -120 µA 60 75 dB ns ENABLE (EL5374 ONLY) tEN Enable Time 130 tDS Disable Time 1.2 VIH EN Pin Voltage for Power-Up VIL EN Pin Voltage for Shut-Down IIH-EN EN Pin Input Current High At VEN = 5V IIL-EN EN Pin Input Current Low At VEN = 0V µs VS+ -1.5 V 150 µA VS+ -0.5 V 123 -10 -8 µA NOTE: 5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN7313 Rev 9.00 August 12, 2015 Page 4 of 15 RF1 -5V 0 IN+ RG REF RS1 50 RS1 50 1 FBP OUT 8 2 INP VSN 7 3 REF VSP 6 4 FBN OUTB 5 RF2 EL5174, EL5374 FN7313 Rev 9.00 August 12, 2015 Connection Diagrams CL1 5pF OUT RLD 1k OUTB +5V CL2 5pF 0 FIGURE 1. EL5174 +5V INP1 INN1 REF1 INP2 INN2 REF2 INP3 INN3 REF3 Page 5 of 15 RSP1 50 RSN1 50 RSR1 50 RSP2 50 RSN2 50 RSR2 50 RSP3 50 RSN3 50 RSR3 50 1 NC OUT1 28 2 INP1 FBP1 27 3 INN1 FBN1 26 4 REF1 OUT1B 25 5 NC VSP 24 6 INP2 VSN 23 7 INN2 OUT2 22 8 REF2 FBP2 21 9 NC FBN2 20 10 INP3 OUT2B 19 11 INN3 OUT3 18 12 REF3 FBP3 17 13 NC FBN3 16 14 EN OUT3B 15 RF RG FIGURE 2. EL5374 RLD1 1k RF 0 RF RG RLD2 1k 0 RF 0 RF RG 0 RLD3 1k RF 0 -5V ENABLE 0 CL1 5pF CL1B 5pF CL2 5pF CL2B 5pF CL3 5pF CL3B 5pF EL5174, EL5374 Typical Performance Curves AV = 1, RLD = 1k, CLD = 2.7pF RLD = 1k, CLD = 2.7pF 4 4 MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) 3 2 VOP-P = 200mV 1 0 -1 -2 VOP-P = 1V -3 -4 -5 -6 1M 10M 100M 3 2 1 AV = 1 0 -1 -3 AV = 10 -5 FREQUENCY (Hz) AV = 1, CLD = 2.7pF 3 CLD = 23pF CLD = 34pF 4 2 0 CLD = 9pF -2 -4 2 MAGNITUDE (dB) MAGNITUDE (dB) 6 CLD = 2.7pF 0 -1 -3 -4 -8 -5 100M RLD = 500 -2 -6 10M RLD= 1k 1 RLD = 200 -6 1M 1G 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE vs CLD FIGURE 6. FREQUENCY RESPONSE vs RLD AV = 2, CLD = 2.7pF, RF = 750 AV = 2, RLD = 1k, CLD = 2.7pF 10 10 9 9 RF = 1k 8 8 7 MAGNITUDE (dB) MAGNITUDE (dB) 1G 4 CLD = 50pF -10 1M 100M FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS GAIN AV = 1, RLD = 1k 8 10M FREQUENCY (Hz) FIGURE 3. FREQUENCY RESPONSE 10 AV = 5 -4 -6 1M 1G AV = 2 -2 6 5 RF = 500 4 RF = 200 3 7 5 1 1 100M FREQUENCY (Hz) FIGURE 7. FREQUENCY RESPONSE FN7313 Rev 9.00 August 12, 2015 400M RLD = 200 3 2 10M RLD = 500 4 2 0 1M RLD = 1k 6 0 1M 10M 100M 400M FREQUENCY (Hz) FIGURE 8. FREQUENCY RESPONSE vs RLD Page 6 of 15 EL5174, EL5374 Typical Performance Curves (Continued) 5 0 4 -10 -20 2 -30 1 PSRR (dB) MAGNITUDE (dB) 3 0 -1 -40 -2 -60 -3 -70 -4 -80 -5 100k 1M 10M -90 10k 100M PSRR- -50 PSRR+ FIGURE 10. PSRR vs FREQUENCY 1k 100 VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz) 80 CMRR (dB) 100M 10M FREQUENCY (Hz) FIGURE 9. FREQUENCY RESPONSE - VREF 60 40 20 0 -20 1k 1M 100k FREQUENCY (Hz) 10k 100k 1M 10M 100M 100 EN 10 IN 1 10 1G 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY FIGURE 11. CMRR vs FREQUENCY 0 100 -10 -20 IMPEDANCE () GAIN (dB) -30 -40 -50 -60 CH1 CH2, CH2 CH3 -70 -80 10 1.0 CH1 CH3 -90 -100 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 13. CHANNEL ISOLATION (EL5374 ONLY) FN7313 Rev 9.00 August 12, 2015 1G 0.1 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 14. OUTPUT IMPEDANCE vs FREQUENCY Page 7 of 15 EL5174, EL5374 Typical Performance Curves (Continued) VS = ±5V, AV = 2, RLD = 1k VS = ±5V, AV = 1, RLD = 1k -40 -40 HD3 (f = 5MHz) -50 DISTORTION (dB) DISTORTION (dB) -50 -60 HD3 (f = 20MHz) -70 -80 -60 HD3 (f = 20MHz) -70 (f H D3 -80 -90 HD2 (f = 20MHz) HD2 (f = 5MHz) 1.5 2.0 2.5 3.0 3.5 4.5 4.0 5.0 -100 1 2 3 -55 -55 -60 -60 -65 -65 -70 -75 H D2 -90 HD2 -95 -100 100 (f = 20M (f = 5 200 HD3 (f Hz) HD3 = 5M (f = 2 Hz) 0MH z ) 400 500 600 RLD () -75 -80 DISTORTION (dB) HD2 (f = 20MHz) -85 -90 HD2 (f = 5MHz) 700 900 1000 800 -100 200 300 400 500 600 700 RLD () 800 900 1000 FIGURE 18. HARMONIC DISTORTION vs RLD VS = ±5V, RLD = 1k, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 -50 HD3 (AV = 2) -60 2 HD -70 (A V HD3 (AV -80 HD -90 -100 HD3 (f = 5MHz) -70 FIGURE 17. HARMONIC DISTORTION vs RLD -40 10 HD3 (f = 20MHz) -95 MHz) 300 9 VS = ±5V, AV = 2, VOP-P, DM = 2V -50 DISTORTION (dB) DISTORTION (dB) VS = ±5V, AV = 1, VOP-P, DM = 1V -85 8 FIGURE 16. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -50 -80 HD2 (f = 5MHz) 5 6 7 VOP-P, DM (V) 4 VOP-P, DM (V) FIGURE 15. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE Hz ) z) HD2 (f = 20MH -90 -100 1.0 = 5M 0 10 20 30 40 FREQUENCY (MHz) 2( AV =2 = 1) 50mV/DIV ) =1 50 FIGURE 19. HARMONIC DISTORTION vs FREQUENCY FN7313 Rev 9.00 August 12, 2015 ) 60 10ns/DIV FIGURE 20. SMALL SIGNAL TRANSIENT RESPONSE Page 8 of 15 EL5174, EL5374 Typical Performance Curves (Continued) M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV CH1 0.5V/DIV CH2 400ns/DIV 10ns/DIV FIGURE 22. ENABLED RESPONSE FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.2 CH1 CH2 1.010W 1.0 QSOP28 JA = +99°C/W 0.8 625mW 0.6 0.4 SO8 JA = +160°C/W 0.2 0 0 25 400ns/DIV 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 23. DISABLED RESPONSE FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.266W 1.0 909mW QSOP28 JA = +79°C/W 0.8 0.6 SO8 JA = +110°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7313 Rev 9.00 August 12, 2015 Page 9 of 15 EL5174, EL5374 Simplified Schematic VS+ R1 IN+ IN- R3 R2 FBP R4 R7 R8 FBN VB1 OUT+ RCD REF RCD VB2 CC OUT- R9 R10 CC R5 R6 VS- Description of Operation and Application Information Product Description The EL5174 and EL5374 are wide bandwidth, low power and single/differential ended to differential output amplifiers. The EL5174 is a single channel differential amplifier. Since the INpin and REF pin are tied together internally, the EL5174 can be used as a single-ended to differential converter. The EL5374 is a triple channel differential amplifier. The EL5374 has a separate IN- pin and REF pin for each channel. It can be used as single/differential ended to differential converter. The EL5174 and EL5374 are internally compensated for closed loop gain of +1 of greater. Connected in a gain of 1 and driving a 1k differential load, the EL5174 and EL5374 have a -3dB bandwidth of 550MHz. Driving a 200 differential load at gain of 2, the bandwidth is about 130MHz. The EL5374 is available with a power-down feature to reduce the power while the amplifier is disabled. Input, Output and Supply Voltage Range The EL5174 and EL5374 have been designed to operate with a single supply voltage of 5V to 10V or split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.3V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.7V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL5174 and EL5374 can swing from -3.8V to +3.8V at 1k differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings differential mode signal. For the true balance differential outputs, the REF pin must be tied to the same bias level as the IN+ pin. For a ±5V supply, just tie the REF pin to GND if the IN+ pin is biased at 0V with a 50 or 75 termination resistor. For a single supply application, if the IN+ is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL5174 is expressed in Equation 1: R F1 + R F2  V ODM = V IN +   1 + ---------------------------- RG   (EQ. 1) 2R F  V ODM = V IN + =  1 + ----------- RG   V OCM = V REF = 0V Where: VREF = 0V RF1 = RF2 = RF The EL5374 has a separate IN- pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one. The gain setting for EL5374 is expressed in Equation 2: R F1 + R F2  V ODM =  V IN + – V IN -    1 + ---------------------------- RG   2R F  V ODM =  V IN + – V IN -    1 + ----------- RG   (EQ. 2) V OCM = V REF Where: RF1 = RF2 = RF For EL5174, since the IN- pin and REF pin are bound together as the REF pin in an 8 Ld package, the signal at the REF pin is part of the common mode signal and also part of the FN7313 Rev 9.00 August 12, 2015 Page 10 of 15 EL5174, EL5374 resistor. Again, a small series resistor at the output can help to reduce peaking. RF1 Disable/Power-Down (for EL5374 only) FBP VIN+ VIN- RG VREF The EL5374 can be disabled and its outputs placed in a high impedance state. The turn-off time is about 1.2µs and the turn-on time is about 130ns. When disabled, the amplifier's supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the EN pin. The applied logic signal is relative to the VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at the EN pin is above VS+ - 0.5V. V O+ IN+ INREF V O- FBN RF2 FIGURE 26. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5174 and EL5374 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. The EL5174 and EL5374 have a gain bandwidth product of 200MHz for RLD = 1k. For gains 5, its bandwidth can be predicted by Equation 3: Gain  BW = 200MHz (EQ. 3) Driving Capacitive Loads and Cables The EL5174 and EL5374 can drive a 23pF differential capacitor in parallel with 1k differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss, which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination FN7313 Rev 9.00 August 12, 2015 Output Drive Capability The EL5174 and EL5374 have internal short circuit protection. Its typical short circuit current is ±60mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL5174 and EL5374, it is possible to exceed the +135°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 4: T JMAX – T AMAX PD MAX = -------------------------------------------- JA (EQ. 4) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or as expressed in Equation 5: V O  PD = i   V STOT  I SMAX +  V STOT – V O   ------------ R LD   (EQ. 5) Where: VSTOT = Total supply voltage = VS+ - VSISMAX = Maximum quiescent supply current per channel VO = Maximum differential output voltage of the application RLD = Differential load resistance Page 11 of 15 EL5174, EL5374 ILOAD = Load current i = Number of channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Typical Applications As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. RF FBP 50 TWISTED PAIR IN+ IN+ RT RG INREF EL5174/ EL5374 50 IN- ZO = 100 FBN EL5175/ EL5375 VO REF RF RFR RGR FIGURE 27. TWISTED PAIR CABLE RECEIVER RF GAIN (dB) FBP RT 75 RGC RG CL VO+ IN+ INREF VO- FBN fL RF 2R F DC Gain = 1 + ----------RG 1 f L  ------------------------2R G C C 2R F  HF Gain = 1 + -------------------------R G  R GC 1 f H  ----------------------------2R GC C C fH FREQUENCY FIGURE 28. TRANSMIT EQUALIZER FN7313 Rev 9.00 August 12, 2015 Page 12 of 15 EL5174, EL5374 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION August 12, 2015 FN7313.9 CHANGE Updated Ordering Information table on page 2. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7313 Rev 9.00 August 12, 2015 Page 13 of 15 EL5174, EL5374 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN7313 Rev 9.00 August 12, 2015 Page 14 of 15 EL5174, EL5374 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) M28.15 N INDEX AREA H 0.25(0.010) M E 2 SYMBOL 3 0.25 0.010 SEATING PLANE -A- INCHES GAUGE PLANE -B1 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) B M A D h x 45° -C- e 0.17(0.007) M  A2 A1 B L C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. MIN MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - A2 - 0.061 - 1.54 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.386 0.394 9.81 10.00 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 N  28 0° 1.27 28 8° 0° 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 6 7 8° Rev. 1 6/04 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7313 Rev 9.00 August 12, 2015 Page 15 of 15