EL5205IYZ

DATASHEET EL5104, EL5105, EL5204, EL5205, EL5304 FN7332 Rev 8.00 May 25, 2016 700MHz Slew-Enhanced VFAs The EL5104, EL5105, EL5204, EL5205, and EL5304 represent high speed voltage feedback amplifiers based on the current feedback amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. This family is available in single, dual, and triple versions, with 200MHz, 400MHz, and 700MHz versions. This family operates on single 5V or ±5V supplies from minimum supply current. The EL5104 and EL5204 also feature an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. Features • Specified for 5V or ±5V applications • Power-down to 17µA • -3dB bandwidth = 700MHz • ±0.1dB bandwidth = 45MHz • Low supply current = 9.5mA • Slew rate = 7000V/µs • Low offset voltage = 10mV max • Output current = 160mA • AVOL = 1400 • Diff gain/phase = 0.01%/0.02° • Pb-free plus anneal available (RoHS compliant) Applications • Video amplifiers • PCMCIA applications • A/D drivers • Line drivers • Portable computers • High speed communications • RGB applications • Broadcast equipment • Active filtering FN7332 Rev 8.00 May 25, 2016 Page 1 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Pinouts OUT 1 VS- 2 + - IN+ 3 6 VS+ NC 1 5 ENABLE IN- 2 4 IN- IN+ 3 VS- 4 R E NG LO NO OUT 1 10 VS+ OUTA 1 IN- 2 9 OUT INA- 2 8 IN- INA+ 3 + VS- 4 + CE 5 R O + LE B LA AI AV ED 8 ENABLE RT O P P SU 7 VS+ 6 OUT OUT 1 + + VS- 4 7 IN+ 5 VS+ VS- 2 + - IN+ 3 4 IN- 5 NC EL5304 (16 LD QSOP) TOP VIEW EL5205 (8 LD SOIC, MSOP) TOP VIEW EL5204 (10 LD MSOP) TOP VIEW IN+ 3 EL5105 (5 LD SOT-23, SC-70) TOP VIEW EL5104 (8 LD SOIC) TOP VIEW EL5104 (6 LD SOT-23) TOP VIEW 8 VS+ INA+ 1 7 OUTB CEA 2 6 INB- VS- 3 5 INB+ CEB 4 INB+ 5 ER NG LO6 NC O N 6 CE 16 INA+ E +BL LAI A AV CEC 7 INC+ 8 ED RT 15 OUTA PO UP S14 VS+ R O 13 OUTB 12 INB11 NC + - 10 OUTC 9 INC- Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5104ISZ (Note) (No longer available, recommended replacement: EL5104IWZ-T7) 5104ISZ - 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5104ISZ-T7 (Note) (No longer available, recommended replacement: EL5104IWZ-T7) 5104ISZ 7” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5104ISZ-T13 (Note) (No longer available, recommended replacement: EL5104IWZ-T7) 5104ISZ 13” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5104IWZ-T7 (Note) BAEA 7” (3k pcs) 6 Ld SOT-23 (Pb-Free) P5.064A EL5104IWZ-T7A (Note) BAEA 7” (250 pcs) 6 Ld SOT-23 (Pb-Free) P5.064A EL5105IC (No longer available or supported) C 5 Ld SC-70 (1.25mm) P5.049 EL5105IWZ-T7 (Note) BBMA 7” (3k pcs) 5 Ld SOT-23 (Pb-Free) P5.064A EL5105IWZ-T7A (Note) BBMA 7” (250 pcs) 5 Ld SOT-23 (Pb-Free) P5.064A EL5204IYZ (Note) BAAAF - 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5204IYZ-T7 (Note) BAAAF 7” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5204IYZ-T13 (Note) BAAAF 13” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 FN7332 Rev 8.00 May 25, 2016 - Page 2 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Ordering Information (Continued) PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5205ISZ (Note) 5205ISZ - 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5205ISZ-T7 (Note) 5205ISZ 7” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5205ISZ-T13 (Note) 5205ISZ 13” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5304IU (No longer available or supported) 5304IU - 16 Ld QSOP (150 mil) MDP0040 EL5304IU-T7 (No longer available or supported) 5304IU 7” 16 Ld QSOP (150 mil) MDP0040 EL5304IU-T13 (No longer available 5304IU or supported) 13” 16 Ld QSOP (150 mil) MDP0040 EL5304IUZ (Note) (No longer available or supported) 5304IUZ - 16 Ld QSOP (150 mil) (Pb-Free) MDP0040 EL5304IUZ-T7 (Note) (No longer available or supported) 5304IUZ 7” 16 Ld QSOP (150 mil) (Pb-Free) MDP0040 EL5304IUZ-T13 (Note) (No longer available or supported) 5304IUZ 13” 16 Ld QSOP (150 mil) (Pb-Free) MDP0040 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7332 Rev 8.00 May 25, 2016 Page 3 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and GND. . . . . . . . . . . . . . . . . . 13.2V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mA VS+ to VS- Maximum Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications VS = ±5V, GND = 0V, TA = +25°C, VCM = 0V, VOUT = 0V, VENABLE = GND or OPEN, Unless Otherwise Specified. PARAMETER VOS DESCRIPTION Offset Voltage CONDITIONS MIN TYP MAX UNIT EL5104, EL5105, EL5204, EL5205 -10 3 10 mV EL5304 -18 5 18 mV TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX 10 IB Input Bias Current VIN = 0V 8 30 µA IOS Input Offset Current VIN = 0V 4 15 µA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX 50 nA/°C PSRR Power Supply Rejection Ratio 60 70 dB CMRR Common Mode Rejection Ratio VCM from -3V to +3V 56 62 dB CMIR Common Mode Input Range Guaranteed by CMRR test -3 RIN Input Resistance Common mode 50 CIN Input Capacitance SO package IS,ON Supply Current - Enabled Per amplifier 8.5 9.5 11 mA IS,OFF Supply Current - Shut Down VS+, per amplifier +1 0 +25 µA VS-, per amplifier -25 17 -1 µA 13.2 V PSOR Power Supply Operating Range AVOL Open Loop Gain +3 55 RL = 150 to GND k 1 pF 65 dB 60 dB 3.8 V VOP Positive Output Voltage Swing RL = 150 to 0V VON Negative Output Voltage Swing RL = 150 to 0V IOUT Output Current RL = 10 to 0V VIH-EN ENABLE Pin Voltage for Power Up (VS+) -5 (VS+) -3 V VIL-EN ENABLE Pin Voltage for Shut Down (VS+) -1 VS+ V FN7332 Rev 8.00 May 25, 2016 3.6 V 120 4 RL = 1k to GND µV/°C -3.8 ±90 -3.6 ±160 V mA Page 4 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Closed Loop AC Electrical Specifications VS = +5V, GND = 0V, TA = +25°C, VCM = +1.5V, VOUT = +1.5V, VCLAMP = +5V, VENABLE = 0V, AV = +1, RF = 0, RL = 150 to GND pin, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT BW -3dB Bandwidth (VOUT = 200mVP-P) VS = ±5V, AV = 1, RF = 0 SR Slew Rate RL = 100, VOUT = -3V to +3V tR, tF Rise Time, Fall Time ±0.1V step 0.4 ns OS Overshoot ±0.1V step 10 % tPD Propagation Delay ±0.1V step 0.4 ns tS 0.1% Settling Time VS = ±5V, RL = 500, AV = 1, VOUT = ±2.5V 7 ns dG Differential Gain AV = 2, RL = 150, VINDC = -1 to +1V 0.01 % dP Differential Phase AV = 2, RL = 150, VINDC = -1 to +1V 0.02 ° eN Input Noise Voltage f = 10kHz 10 nV/Hz iN Input Noise Current f = 10kHz 54 pA/Hz tDIS Disable Time 180 ns tEN Enable Time 650 ns IEN Enable Pin Current FN7332 Rev 8.00 May 25, 2016 700 2000 3000 MHz 7000 V/µs Enabled, VEN = 0V -1 1 µA Disabled, VEN = 5V 1 25 µA Page 5 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves 5 3 2 120 1 0 -1 -2 VS=±5V AV=+1 RF=0 RL=500 180 PHASE (°) NORMALIZED GAIN (dB) 240 VS=±5V AV=+1 RF=0 RL=500 4 60 0 -60 -3dB BW @ 925MHz -120 -3 -180 -4 -5 100k 1M 10M 100M 1G -240 100k 10G 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH) FIGURE 2. PHASE vs FREQUENCY 70 0.5 VS=±5V AV=+1 RF=0 RL=500 0.3 0.2 GAIN=40dB or 100 FREQ.=2.64MHz GAIN BW PRODUCT=2.64x100=264MHz 60 0.1dB BW @ 39MHz 0.1 0 -0.1 GAIN (dB) NORMALIZED GAIN (dB) 0.4 50 40 -0.2 30 -0.3 VS=±5V RL=500 -0.4 -0.5 1 10 20 100 0 1 FREQUENCY (MHz) 100 FIGURE 4. GAIN BANDWIDTH PRODUCT 300 5 4 NORMALIZED GAIN (dB) 250 200 150 100 VS=±5V RL=500 50 2.0 10 FREQUENCY (MHz) FIGURE 3. 0.1dB BANDWIDTH GAIN-BANDWIDTH PRODUCT (MHz) 1G 2.5 AV=+1 RF=0 2 1 0 -1 -2 AV=+5 RF=1.6k, RG=402 -3 AV=+2 RF=RG=255 -4 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGES (±V) FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES FN7332 Rev 8.00 May 25, 2016 3 VS=±5V RL=500 6.0 -5 100k 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV Page 6 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves (Continued) 5 5 AV=+1 RF=0 RL=500 3 VS=±6V 2 VS=±5V 1 0 -1 VS=±4V -2 VS=±3V -3 -4 1M 10M 100M FREQUENCY (Hz) 1G -1 -2 RL=150 -3 RL=75 RL=50 1M 4 2 RL=500 1 RL=1k 0 -1 -2 RL=50 -3 RL=75 -4 1M 10M 3 2 100M RL=500 -1 -2 RL=50 -3 RL=75 RL=150 1M 1G FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RL (AV=+5) CL=22pF CL=12pF 4 CL=5.6pF CL=3.3pF 0 -1 CL=0pF -2 -3 -4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10M 100M FREQUENCY (Hz) 5 VS=±5 AV=+1 RF=0 RL=500 1 -5 100k 10G RL=1k 0 -5 100k 1G 5 2 1G 1 -4 RL=150 FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RL (AV=+2) 3 100M VS=±5 AV=+5 RF=1600 CL=12pF FREQUENCY (Hz) 4 10M FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RL (AV=+1) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL=500 0 5 VS=±5 AV=+2 RF=255 -5 100k 1 FREQUENCY (Hz) 5 3 RL=1k 2 -5 100k 10G FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±Vs 4 3 -4 VS=±2V -5 100k VS=±5 AV=+1 RF=0 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 3 2 VS=±5 AV=+2 RF=255 RL=500 CL=33pF CL=22pF CL=15pF 1 CL=8.2pF 0 -1 CL=0pF -2 -3 -4 1M 10M 100M FREQUENCY (Hz) 1G 10G FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CL (AV=+1) FN7332 Rev 8.00 May 25, 2016 -5 100k 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CL (AV=+2) Page 7 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves (Continued) 5 5 NORMALIZED GAIN (dB) 4 3 2 4 CL=100pF CL=68pF NORMALIZED GAIN (dB) VS=±5 AV=+5 RF=1600 RL=500 CL=39pF 1 0 CL=22pF -1 CL=0pF -2 -3 -4 1M 10M 100M FREQUENCY (Hz) RF=25 1 0 -1 RF=0 -2 -3 RF=604 RF=511 2 RF=402 1 0 -1 RF=255 -2 -3 10M 4 RF=50 -4 3 VS=±5 AV=+5 RL=500 1M 10M 100M RF=6k 2 1 RF=2k 0 -1 RF=1k -2 -3 RF=100 -5 100k 1G FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2) 1M 1 CIN=3.9pF CIN=2.7pF CIN=2.2pF 0 CIN=1pF -1 CIN=0pF -2 -3 -4 -5 100k 1G 3 2 1 VS=±5 AV=+5 RG=402 RL=1600 CL=15pF CIN=4.7pF CIN=3.3pF CIN=2.2pF 0 CIN=1.5pF -1 -2 CIN=0pF -3 -4 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2) FN7332 Rev 8.00 May 25, 2016 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 VS=±5 AV=+2 RF=RG=255 RL=500 10M 100M FREQUENCY (Hz) FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5) 5 2 10G RF=4k FREQUENCY (Hz) 3 1G -4 -5 100k 4 100M FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV=+1) 5 VS=±5 AV=+2 RL=500 1M FREQUENCY (Hz) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 3 2 -5 100k 1G FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CL (AV=+5) 4 RF=50 -4 -5 100k 5 3 RF=100 VS=±5 AV=+1 RL=500 -5 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5) Page 8 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves (Continued) 100 50 AV=+2 VS=±5V 10 30 ZOUT () OPEN LOOP GAIN (dB) 70 10 1 0.1 -10 -30 1k 10k 100k 1M 10M 100M 0.01 10k 1G 100k 100M FIGURE 20. ZOUT vs FREQUENCY 10 AV=+5 VS=±5V -30 -10 -50 -30 PSRR (dB) CMRR (dB) 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 1M -70 AV=+1 VS=±5V -50 VS+ -90 -70 -110 1k 10k 100k 1M 10M 100M -90 1k 1G VS- 10k 100k FREQUENCY (Hz) 1G 30 25 RL=500 9 20 8 GROUP DELAY (ns) MAX OUTPUT VOLTAGE SWING (VP-P) 100M FIGURE 22. PSRR vs FREQUENCY 10 7 6 RL=150 5 4 3 1 10M FREQUENCY (Hz) FIGURE 21. CMRR vs FREQUENCY 2 1M VS=±5V AV=+2 RF=RG=402 0 100k 1M 10 5 0 -5 -10 -15 -20 -25 10M 100M FREQUENCY (Hz) 1G FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY FN7332 Rev 8.00 May 25, 2016 15 VS=±5V AV=+1 RF=0 RL=500 -30 100k 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 24. GROUP DELAY vs FREQUENCY Page 9 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves -10 -20 0 -10 VS=±5V -20 AV=+1 -30 RF=0 -40 RL=500 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 100k 1M OUTPUT TO INPUT -40 GAIN (dB) ISOLATION (dB) -30 VS=±5V AV=+1 RF=0 CHIP DISABLED (Continued) -50 INPUT TO OUTPUT -60 -70 -80 -90 -100 100k 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 25. INPUT AND OUTPUT ISOLATION -50 -60 -20 VS =±5V AV=+1 RF=0 RL=500 VOUT=2VP-P VS =±5V AV=+5 RG=402 RF=1600 RL=500 CL=15pF -30 -40 T.H.D -70 2ndH.D. -80 -90 -50 NOTE: This was done on the EL5205 (dual op amp). 10M 100M FREQUENCY (Hz) 1G FIN = 10MHz -60 -70 3rd H.D. FIN = 1MHz -80 -100 -90 -100 -110 100k 1M 10M 100M 0 1 2 6 5 ENABLE SIGNAL 4 3 Vs =±5V AV=+1 RF=0 RL=500 VOUT=2VP-P 2 OUTPUT SIGNAL 1 0 Vs =±5V 5 AV=+1 RF=0 4 R =500 L 3 VOUT=2VP-P FIGURE 29. TURN-ON TIME FN7332 Rev 8.00 May 25, 2016 8 0 -2 TIME (ns) 7 OUTPUT SIGNAL 1 -1 200 400 600 800 1000 1200 1400 1600 6 DISABLE SIGNAL 2 -2 0 5 6 -1 -3 -600 -400 -200 4 FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES AMPLITUDE (V) FIGURE 27. HARMONIC DISTORTION vs FREQUENCY 3 OUTPUT VOLTAGES (VP-P) FUNDAMENTAL FREQUENCY (Hz) AMPLITUDE (V) B IN TO A OUT FIGURE 26. CHANNEL TO CHANNEL ISOLATION THD (dBc) HARMONIC DISTORTION (dBc) -40 A IN TO B OUT -3 -600 -400 -200 0 200 400 600 800 1000 1200 1400 1600 TIME (ns) FIGURE 30. TURN-OFF TIME Page 10 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves 1K (Continued) 0.5 VS=±5V Vs =±5V AV=+1 RF=0 0.3 RL=500 VOUT=400mV 100 AMPLITUDE (V) NOISE VOLTAGE (nV/Hz) 0.4 10 0.2 0.1 TFALL = 860ps 0.0 TRISE=852ps -0.1 -0.2 1 10 100 1k 10k -0.3 -20 100k 0 20 40 60 FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY 4 AMPLITUDE (V) 3 12 Vs =±5V AV=+1 RF=0 RL=500 VOUT=4.0VP-P 10 2 1 TFALL = 944ps 0 TRISE=958ps -1 -2 -3 -20 0 20 40 60 80 8 6 4 NOTE: The curve showed positive current. The negative current was the same. 2 0 1.0 100 120 140 160 180 AV=+1 RF=0 RL=500 1.5 2.0 2.5 TIME (ns) 4.0 4.5 5.0 5.5 6.0 10 NEGATIVE SLEW RATE AMPLITUDE (dBm) SLEW RATE (V/µs) 3.5 FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE 5000 3500 POSITIVE SLEW RATE 3000 3.0 SUPPLY VOLTAGE (V) FIGURE 33. LARGE SIGNAL STEP RESPONSE_RISE & FALL TIME AV=+2 4500 RF=RG=255 RL=500 4000 VOUT=4VP-P 100 120 140 160 180 FIGURE 32. SMALL SIGNAL STEP RESPONSE_RISE & FALL TIME SUPPLY CURRENT (mA) 5 80 TIME (ns) FREQUENCY (Hz) 2500 2000 Vs =±5V 0 AV=+5 -10 RF=1600 RL=100 -20 C =15pF L -30 f1=4dBm -40 @ 0.95MHz -50 2f1-f2=-72.7dBm -60 @ 0.85MHz -70 Delta IM=(4)-(-73)=77dB IP3=4+(77/2)=42.5dBm f2=4.1dBm @ 1.05MHz 2f2-f1=-73dBm @ 1.15MHz -80 1500 1000 2.0 -90 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGES (±V) 5.5 FIGURE 35. SLEW RATE vs SUPPLY VOLTAGES FN7332 Rev 8.00 May 25, 2016 6.0 -100 0.8 0.9 1.0 FREQUENCY (MHz) 1.1 1.2 FIGURE 36. THIRD ORDER IMD INTERCEPT (IP3) Page 11 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Typical Performance Curves (Continued) 60 55 50 IP3 (dBm) 45 40 35 30 Vs =±5V AV=+5 RF=1600 RL=100 CL=15pF 25 20 15 10 1 10 FREQUENCY (MHz) 100 FIGURE 37. THIRD ORDER IMD INTERCEPT vs FREQUENCY 1.2 1.136W 1.116W 1 1.087W 1 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD SO8 JA=110°C/W QSOP16 JA=112°C/W 0.8 0.6 543mW 0.4 SOT23-5/6 JA=230°C/W 0.2 0 0 25 50 MSOP8/10 JA=115°C/W 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7332 Rev 8.00 May 25, 2016 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 791mW 0.8 QSOP16 JA=158°C/W 781mW 0.6 MSOP8/10 JA=206°C/W 488mW 0.4 SOT23-5/6 JA=256°C/W 0.2 0 SO8 JA=160°C/W 607mW 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 12 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE May 25, 2016 FN7332.8 - Updated Ordering Information Table on page 2. October 20, 2015 FN7332.7 - Updated Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage. - POD MDP0038 obsoleted and replaced by P5.064A latest revision. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2004-2016. All Rights Reserved. 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No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7332 Rev 8.00 May 25, 2016 Page 13 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS 0.08 M C A B b SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE A1 L 0.25 3° ±3° DETAIL X FN7332 Rev 8.00 May 25, 2016 Page 14 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 NOTES: Rev. M 2/07 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN7332 Rev 8.00 May 25, 2016 Page 15 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 5 (0.60) 0.20 C 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 H 0.15 C A-B 2x C 1.45 MAX 1.14 ±0.15 0.10 C SIDE VIEW SEATING PLANE (0.25) GAUGE PLANE 0.45±0.1 0.05-0.15 4 DETAIL "X" (0.60) (1.20) NOTES: (2.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN FN7332 Rev 8.00 May 25, 2016 Page 16 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X FN7332 Rev 8.00 May 25, 2016 Page 17 of 18 EL5104, EL5105, EL5204, EL5205, EL5304 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- WITH PLATING b1 NOTES 0.031 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c1 MAX 0.000  c MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X 1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1  L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X 1 VIEW C FN7332 Rev 8.00 May 25, 2016 Page 18 of 18