DATASHEET
EL5220T
FN6892
Rev 0.00
May 4, 2010
12MHz Rail-to-Rail Input-Output Operational Amplifier
The EL5220T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5220T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
Features
The maximum operating voltage range is from 4.5V to
19V. It can be configured for single or dual supply
operation, and typically consumes only 550µA per
amplifier. The EL5220T has an output short circuit
capability of ±200mA and a continuous output current
capability of ±65mA.
• 550µA Supply Current (per Amplifier)
The EL5220T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond
the supply rails, rail-to-rail output capability, and a
bandwidth of 12MHz (-3dB). This enables the
amplifiers to offer maximum dynamic range at any
supply voltage. These features make the EL5220T an
ideal amplifier solution for use in TFT-LCD panels as a
VCOM or static gamma buffer, and in high speed
filtering and signal conditioning applications. Other
applications include battery power and portable
devices, especially where low power consumption is
important.
• Rail-to-rail Output Swing
The EL5220T is available in an 8 Ld MSOP package,
and a thermally enhanced 8 Ld DFN package. Both
feature a standard operational amplifier pinout. The
devices operate over an ambient temperature range of
-40°C to +85°C.
• Electronics Games
• 12MHz (-3dB) Bandwidth
• 4.5V to 19V Maximum Supply Voltage Range
• 12V/µs Slew Rate
• ±65mA Continuous Output Current
• ±200mA Output Short Circuit Current
• Unity-gain Stable
• Beyond the Rails Input Capability
• Built-in Thermal Protection
• -40°C to +85°C Ambient Temperature Range
• Pb-free (RoHS Compliant)
Applications*(see page 13)
• TFT-LCD Panels
• VCOM Amplifiers
• Static Gamma Buffers
• Electronics Notebooks
• Touch-screen Displays
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Sampling ADC Amplifiers
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffer
+15V
+15V
VOUTA
VINA0
VINA+
VS-
EL5220T
VS+
0.1µF
+
PANEL
CAPACITANCE
4.7µF
VOUTB
PANEL
CAPACITANCE
VINBVINB+
0
TFT-LCD
PANEL
NORMALIZED GAIN (dB)
5
10kΩ
0
1kΩ
-5
560Ω
150Ω
-10 VS = ±5V
AV = 1
CL = 8pF
-15
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. TYPICAL TFT-LCD VCOM APPLICATION
FN6892 Rev 0.00
May 4, 2010
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS RL
Page 1 of 15
EL5220T
Pin Configuration
EL5220T
(8 LD DFN)
TOP VIEW
EL5220T
(8 LD MSOP)
TOP VIEW
VOUTA 1
VINA- 2
8 VS+
VOUTA 1
7 VOUTB
+
VINA+ 3
+
VS- 4
VINA- 2
6 VINB-
VINA+ 3
8 VS+
7 VOUTB
PD
6 VINB-
VS- 4
5 VINB+
5 VINB+
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
Pin Descriptions
PIN NUMBER
(MSOP, DFN)
PIN
NAME
1
VOUTA
Amplifier A output
(Reference Circuit 1)
2
VINA-
Amplifier A inverting input
(Reference Circuit 2)
3
VINA+
Amplifier A non-inverting input
(Reference Circuit 2)
4
VS-
5
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
6
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
VOUTB
Amplifier B output
(Reference Circuit 1)
8
VS+
PD
EQUIVALENT
CIRCUIT
FUNCTION
Negative power supply
Positive power supply
Thermal Pad Functions as a heat sink. Electrically connected to VS-. Connect the thermal
pad to VS- plane on the PCB for optimum thermal performance.
VS+
VS+
VOUTx
VINx
VS-
GND
VS-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
EL5220TILZ-T13 (Note 1)
20T
EL5220TIYZ
EL5220TIYZ-T7 (Note 1)
EL5220TIYZ-T13 (Note 1)
PACKAGE
(Pb-Free)
PKG.
DWG. #
8 Ld DFN
L8.2x3
BBBMA
8 Ld MSOP
M8.118A
BBBMA
8 Ld MSOP
M8.118A
BBBMA
8 Ld MSOP
M8.118A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5220T. For more information on MSL please see
techbrief TB363.
FN6892 Rev 0.00
May 4, 2010
Page 2 of 15
EL5220T
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . .+19.8V
Input Voltage Range (VINx+, VINx-) . . . VS- - 0.5V, VS+ + 0.5V
Input Differential Voltage (VINx+ - VINx-) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . (VS+ + 0.5V)-(VS- - 0.5V)
Maximum Continuous Output Current . . . . . . . . . . . ±65mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld MSOP (Notes 6, 7) . . . . . . . .
170
60
8 Ld DFN (Notes 4, 5). . . . . . . . . .
58
8
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . -40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . . See Figures 32 and 33
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
7. For JC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
18
mV
INPUT CHARACTERISTICS
VOS
TCVOS
IB
Input Offset Voltage
VCM = 0V
3
Average Offset Voltage Drift (Note 8)
8 Ld MSOP package
5
µV/°C
8 Ld DFN package
3
µV/°C
VCM = 0V
2
Input Bias Current
50
nA
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
-5.5
+5.5
V
CMRR
Common-Mode Rejection Ratio
For VINx from -5.5V to +5.5V
50
75
dB
AVOL
Open Loop Gain
-4.5V VOUTx 4.5V
75
105
dB
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
Short Circuit Current
VCM = 0V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
4.85
Output Current
-4.94 -4.85
V
4.94
V
±200
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-) Supply Voltage Range
4.5
IS
Supply Current (Per Amplifier)
VCM = 0V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
FN6892 Rev 0.00
May 4, 2010
550
60
75
19
V
750
µA
dB
Page 3 of 15
EL5220T
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 9)
-4.0V VOUTx 4.0V, 20% to 80%
tS
Settling to +0.1% (Note 10)
AV = +1, VOUTx = 2V step,
RL = 10kΩ, CL = 8pF
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
Gain-Bandwidth Product
PM
CS
BW
GBWP
12
V/µs
500
ns
12
MHz
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
Channel Separation
f = 5MHz
85
dB
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10kΩ to 2.5V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX UNIT
INPUT CHARACTERISTICS
VOS
TCVOS
IB
Input Offset Voltage
VCM = 2.5V
3
Average Offset Voltage Drift (Note 8)
8 Ld MSOP package
5
µV/°C
8 Ld DFN package
3
µV/°C
VCM = 2.5V
2
Input Bias Current
18
50
mV
nA
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
-0.5
+5.5
V
CMRR
Common-Mode Rejection Ratio
For VINx from -0.5V to +5.5V
45
70
dB
AVOL
Open Loop Gain
0.5V VOUTx 4.5V
75
105
dB
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -2.5mA
VOH
Output Swing High
IL = +2.5mA
ISC
Short Circuit Current
VCM = 2.5V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
30
4.85
Output Current
150
mV
4.97
V
±125
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-)
Supply Voltage Range
4.5
IS
Supply Current (Per Amplifier)
VCM = 2.5V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
550
60
19
V
750
µA
75
dB
12
V/µs
500
ns
12
MHz
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 9)
1V VOUTx 4V, 20% to 80%
tS
Settling to +0.1% (Note 10)
AV = +1, VOUTx = 2V step,
RL = 10kΩ, CL = 8pF
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
Gain-Bandwidth Product
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
PM
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
CS
Channel Separation
f = 5MHz
85
dB
BW
GBWP
FN6892 Rev 0.00
May 4, 2010
Page 4 of 15
EL5220T
Electrical Specifications
PARAMETER
VS+ = +18V, VS- = 0V, RL = 10kΩ to 9V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
18
mV
INPUT CHARACTERISTICS
VOS
TCVOS
IB
Input Offset Voltage
VCM = 9V
5
Average Offset Voltage Drift (Note 8)
8 Ld MSOP package
6
µV/°C
8 Ld DFN package
4
µV/°C
VCM = 9V
2
Input Bias Current
50
nA
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
-0.5
+18.5
V
CMRR
Common-Mode Rejection Ratio
For VINx from -0.5V to +18.5V
53
78
dB
AVOL
Open Loop Gain
0.5V VOUTx 17.5V
75
90
dB
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -9mA
VOH
Output Swing High
IL = +9mA
ISC
Short Circuit Current
VCM = 9V, Source: VOUTx short to VS-,
Sink: VOUTx short to VS+
IOUT
120
150
mV
17.85 17.88
Output Current
V
±200
mA
±65
mA
POWER SUPPLY PERFORMANCE
(VS+) - (VS-) Supply Voltage Range
4.5
IS
Supply Current (Per Amplifier)
VCM = 9V, No load
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
650
60
19
V
850
µA
75
dB
12
V/µs
500
ns
12
MHz
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 9)
1V VOUTx 17V, 20% to 80%
tS
Settling to +0.1% (Note 10)
AV = +1, VOUTx = 2V step,
RL = 10kΩ, CL = 8pF
-3dB Bandwidth
RL = 10kΩ, CL = 8pF
Gain-Bandwidth Product
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
8
MHz
PM
Phase Margin
AV = -50, RF = 5kΩRG = 100Ω
RL = 10kΩ, CL = 8pF
50
°
CS
Channel Separation
f = 5MHz
85
dB
BW
GBWP
NOTES:
8. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in
the “Typical Performance Curves” on page 6.
9. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of
the output signal.
10. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output
level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]
FN6892 Rev 0.00
May 4, 2010
Page 5 of 15
EL5220T
Typical Performance Curves
VS = ±5V
TA = +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
400
300
200
100
0
-10
-8
-6
-4
-2
0
2
4
6
8
18
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
500
14
TYPICAL
PRODUCTION
DISTRIBUTION
12
10
8
6
4
2
0
10
VS = ±5V
-40°C TO +85°C
16
2
INPUT OFFSET VOLTAGE (mV)
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 4. INPUT OFFSET VOLTAGE DRIFT (MSOP)
10.0
VS = ±5V
-40°C TO +85°C
16
14
TYPICAL
PRODUCTION
DISTRIBUTION
12
10
8
6
4
2
1
3
5
7
9
11
13
15
INPUT OFFSET VOLTAGE (mV)
QUANTITY (AMPLIFIERS)
18
0
4 6 8 10 12 14 16 18 20 22 24 26 28
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
VS = ±5V
7.5
5.0
2.5
0.0
-50
17
0
INPUT OFFSET VOLTAGE DRIFT (mV)
FIGURE 5. INPUT OFFSET VOLTAGE DRIFT (DFN)
4.96
VS = ±5V
4
3
2
1
0
-1
-50
100
0
50
100
150
TEMPERATURE (°C)
FIGURE 7. INPUT BIAS CURRENT vs TEMPERATURE
FN6892 Rev 0.00
May 4, 2010
150
FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE
OUTPUT HIGH VOLTAGE (V)
INPUT BIAS CURRENT (nA)
5
50
TEMPERATURE (°C)
VS = ±5V
IOUT = 5mA
4.95
4.94
4.93
4.92
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 8. OUTPUT HIGH VOLTAGE vs TEMPERATURE
Page 6 of 15
EL5220T
Typical Performance Curves (Continued)
-4.92
140
VS = ±5V
IOUT = -5mA
OPEN LOOP GAIN (dB)
OUTPUT LOW VOLTAGE (V)
-4.91
-4.93
-4.94
-4.95
-4.96
-4.97
-50
0
50
100
VS = ±5V
RL = 10kΩ
120
100
80
60
40
-50
150
0
TEMPERATURE (°C)
FIGURE 9. OUTPUT LOW VOLTAGE vs TEMPERATURE
VS = ±5V
RL = 10kΩ
12.5
12.0
11.5
11.0
-50
0
50
100
590
VS = ±5V
570
550
530
0
TEMPERATURE (°C)
SLEW RATE (V/µs)
SUPPLY CURRENT (µA)
TA = +25°C
NO LOAD
INPUT AT GND
700
600
500
400
2
4
6
8
SUPPLY VOLTAGE (±V)
FIGURE 13. SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
FN6892 Rev 0.00
May 4, 2010
50
TEMPERATURE (°C)
100
150
FIGURE 12. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
16
800
150
NO LOAD
INPUT AT GND
510
-50
150
FIGURE 11. SLEW RATE vs TEMPERATURE
100
FIGURE 10. OPEN-LOOP GAIN vs TEMPERATURE
SUPPLY CURRENT (µA)
SLEW RATE (V/µs)
13.0
50
TEMPERATURE (°C)
10
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
14
12
10
8
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V)
FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE
Page 7 of 15
20
EL5220T
Typical Performance Curves (Continued)
250
200
80
GAIN
60
150
40
100
PHASE
50
20
VS = ±5V
TA = +25°C
0 R = 10kΩ
L
CL = 8pF
-20
10
100
1k
0
10k
100k
1M
10M
NORMALIZED GAIN (dB)
5
PHASE (°)
OPEN LOOP GAIN (dB)
100
-50
100M
10kΩ
0
1kΩ
-5
560Ω
150Ω
-10
VS = ±5V
AV = 1
CL = 8pF
-15
100k
1M
FIGURE 15. OPEN LOOP GAIN AND PHASE vs
FREQUENCY
1000
OUTPUT IMPEDANCE (Ω)
NORMALIZED GAIN (dB)
VS = ±5V
A =1
15 RV = 10kΩ
L
10
100pF
5
0
50pF
8pF
-5
1M
10M
FREQUENCY (Hz)
10
1
0.1
1k
100k
1M
100M
FREQUENCY (Hz)
FIGURE 18. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
12
0
-10
10
-20
8
CMRR (dB)
MAXIMUM OUTPUT SWING (VP-P)
100
0.01
10
100M
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS CL
6
2
VS = ±5V
RF = 2kVΩ
RG = 1kΩ
RL = 450Ω
SOURCE = 0dBm
1000pF
-15
100k
4
100M
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS RL
20
-10
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
0
10k
-30
-40
-50
-60
-70
100k
1M
FREQUENCY (Hz)
10M
FIGURE 19. MAXIMUM OUTPUT SWING vs FREQUENCY
FN6892 Rev 0.00
May 4, 2010
V S = ±5V
T A = +25°C
V INx = -10dBm
-80
10
1k
100k
FREQUENCY (Hz)
100M
FIGURE 20. CMRR vs FREQUENCY
Page 8 of 15
EL5220T
Typical Performance Curves (Continued)
0
1000
VS = ±5V
TA = +25°C
PSRR (dB)
-20
-30
-40
-50
-60
-70
-80
1k
TA = +25°C
VOLTAGE NOISE (nV/√Hz)
-10
10k
100k
1M
100
10
1
100
10M
1k
FREQUENCY (Hz)
-60
THD+N (%)
0.030
0.025
0.020
-70
XTALK (dB)
VS = ±5V
RL = 10kΩ
AV = 1
VIN = 1.4VRMS
0.035
1M
10M
100M
FIGURE 22. INPUT VOLTAGE NOISE SPECTRAL
DENSITY vs FREQUENCY
0.050
0.040
100k
FREQUENCY (Hz)
FIGURE 21. PSRR vs FREQUENCY
0.045
10k
VS = ±5V
AV = 1
VINx = 0dBm
-80
-90
0.015
0.010
0.005
100
1k
10k
FREQUENCY (Hz)
100k
FIGURE 23. TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
-100
10k
5
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
4
3
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
VINx = ±50mV
20
0
10
100
LOAD CAPACITANCE (pF)
FIGURE 25. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FN6892 Rev 0.00
May 4, 2010
1000
STEP SIZE (V)
OVERSHOOT (%)
80
40
10M
FIGURE 24. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
100
60
100k
1M
FREQUENCY (Hz)
2
0.1%
1
0
-1
-2
0.1%
-3
-4
-5
100
200
300
400
500
600
SETTLING TIME (ns)
FIGURE 26. STEP SIZE vs SETTLING TIME
Page 9 of 15
700
EL5220T
Typical Performance Curves (Continued)
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
1V/DIV
50mV/DIV
VS = ±5V
TA = +25°C
AV = 1
RL = 10kΩ
CL = 8pF
200ns/DIV
100mV STEP
6V STEP
1µs/DIV
FIGURE 27. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 28. SMALL SIGNAL TRANSIENT RESPONSE
EL5220T
(8LD MSOP/DFN SHOWN)
1
VOUTA
CLA
RLA
VOUTA
VS+
RFA
2 VINA-
VOUTB
8
0.1µF
VOUTB
RFB
3
VINA+
VINB-
VS+
4.7µF
7
RGA
VINA+
+
RLB
CLB
6
RGB
49.9
4
VS4.7µF +
VS-
VINB+
5
0.1µF
VINB+
49.9
THERMAL PAD
CONNECTED TO VS(DFN ONLY)
FIGURE 29. BASIC TEST CIRCUIT
FN6892 Rev 0.00
May 4, 2010
Page 10 of 15
EL5220T
Applications Information
VS = ±2.5V, TA = +25°C, AV = 1, VINx = 6VP-P, RL = 10kΩ TO GND
The EL5220T can operate on a single supply or dual
supply configuration. The EL5220T operating voltage
ranges from a minimum of 4.5V to a maximum of 19V.
This range allows for a standard 5V (or ±2.5V) supply
voltage to dip to -10%, or a standard 18V (or ±9V) to
rise by +5.5% without affecting performance or
reliability.
The input common-mode voltage range of the EL5220T
extends 500mV beyond the supply rails. Also, the
EL5220T is immune to phase reversal. However, if the
common mode input voltage exceeds the supply voltage
by more than 0.5V, electrostatic protection diodes in the
input stage of the device begin to conduct. Even though
phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage
conditions. Figure 30 shows the input voltage driven
500mV beyond the supply rails and the device output
swinging between the supply rails.
The EL5220T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 31
shows the input and output waveforms for the device in
a unity-gain configuration. Operation is from ±5V
supply with a 10kΩ load connected to GND. The input is
a 10VP-P sinusoid and the output voltage is
approximately 9.9VP-P.
Refer to the “Electrical Specifications” Table beginning
on page 3 for specific device parameters. Parameter
variations with operating voltage, loading and/or
temperature are shown in the “Typical Performance
Curves” on page 6.
INPUT
100µs/DIV
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS
INPUT
VS = ±5V, TA = +25°C, AV = 1, VINx = 10VP-P, RL = 10kΩ TO GND
INPUT
Operating Voltage, Input and Output
Capability
OUTPUT
OUTPUT
The EL5220T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond
the supply rails, rail-to-rail output capability, and a
bandwidth of 12MHz (-3dB). This enables the
amplifiers to offer maximum dynamic range at any
supply voltage.
5V/DIV
The EL5220T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5220T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability,
and is unity gain stable.
1V/DIV
Product Description
100µs/DIV
FIGURE 31. OPERATION WITH RAIL-TO-RAIL INPUT
AND OUTPUT
Output Current
The EL5220T is capable of output short circuit currents
of 200mA (source and sink), and the device has
built-in protection circuitry which limits the output
current to ±200mA (typical).
To maintain maximum reliability the continuous output
current should never exceed ±65mA. This ±65mA limit
is determined by the characteristics of the internal
metal interconnects. Also, see “Power Dissipation” on
page 12 for detailed information on ensuring proper
device operation and reliability for temperature and
load conditions.
Unused Amplifiers
It is recommended that any unused amplifiers be
configured as a unity gain follower. The inverting input
should be directly connected to the output and the
non-inverting input tied to the ground.
Thermal Shutdown
The EL5220T has a built-in thermal protection which
ensures safe operation and prevents internal damage
to the device due to overheating. When the die
temperature reaches +165°C (typical) the device
automatically shuts OFF the outputs by putting them in
a high impedance state. When the die cools by +15°C
FN6892 Rev 0.00
May 4, 2010
Page 11 of 15
EL5220T
(typical) the device automatically turns ON the outputs
by putting them in a low impedance (normal)
operating state.
• VS+ = Positive supply voltage
Driving Capacitive Loads
• VS- = Negative supply voltage
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5220T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
Another method to reduce peaking is to add a series
output resistor (typically between 1 to 10).
Depending on the capacitive loading, a small value
resistor may be the most appropriate choice to
minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5220T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5220T in the
application. Proper load conditions will ensure that the
EL5220T junction temperature stays within a safe
operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
• ISMAX = Maximum supply current per amplifier
(ISMAX = EL5220T quiescent current ÷ 2)
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in
the highest power dissipation. To find RLOAD set the
two PDMAX equations equal to each other and solve for
VOUT/ILOAD. Reference the package power dissipation
curves, Figures 32 and 33, for further information.
1.0
POWER DISSIPATION (W)
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability,
a snubber circuit or a series resistor may be added to
the output of the EL5220T.
• VS = Total supply voltage (VS+ - VS-)
DFN8
JA = +160°C/W
595mW
0.6
0.4
MSOP8
JA = +210°C/W
0.2
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
(EQ. 1)
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the
total quiescent supply current times the total power
supply voltage, plus the power dissipation in the IC
due to the loads, or:
(EQ. 2)
POWER DISSIPATION (W)
2.4
• TJMAX = Maximum junction temperature
2.16W
2.0
DFN8
JA = +58°C/W
1.6
1.2
MSOP8
JA = +170°C/W
740mW
0.8
0.4
0.0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
when sourcing, and:
P DMAX = i V S I SMAX + V OUT i – V S - I LOAD i
781mW
0.8
0.0
where:
P DMAX = i V S I SMAX + V S + – V OUT i I LOAD i
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
(EQ. 3)
FIGURE 33. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
when sinking, where:
• i = 1 to 2
(1, 2 corresponds to Channel A, B respectively)
FN6892 Rev 0.00
May 4, 2010
Page 12 of 15
EL5220T
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5220T can provide gain at high frequency, so
good printed circuit board layout is necessary for
optimum performance. Ground plane construction is
highly recommended, trace lengths should be as short
as possible and the power supply pins must be well
bypassed to reduce any risk of oscillation.
For normal single supply operation (the VS- pin is
connected to ground) a 4.7µF capacitor should be
placed from VS+ to ground, then a parallel 0.1µF
capacitor should be connected as close to the amplifier
as possible. One 4.7µF capacitor may be used for
multiple devices. For dual supply operation the same
capacitor combination should be placed at each supply
pin to ground.
It is highly recommended that EL5220T exposed
thermal pad packages should always have the pad
connected to the lowest potential, VS-, to optimize
thermal and operating performance. PCB vias should
be placed below the device’s exposed thermal pad to
transfer heat to the VS- plane and away from the
device.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
5/4/10
FN6892.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: EL5220T
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
© Copyright Intersil Americas LLC 2010. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6892 Rev 0.00
May 4, 2010
Page 13 of 15
EL5220T
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
3.0±0.1
8
A
0.25
CAB
3.0±0.1
4.9±0.15
DETAIL "X"
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
0.18 ± 0.05
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.33 +0.07/ -0.08
0.08 C A B
0.10 ± 0.05
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
4.40
3.00
1.
Dimensions are in millimeters.
2.
Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
4.
Plastic interlead protrusions of 0.25mm max per side are not
included.
5.
Dimensions “D” and “E1” are measured at Datum Plane “H”.
6.
This replaces existing drawing # MDP0043 MSOP 8L.
0.65
0.40
1.40
TYPICAL RECOMMENDED LAND PATTERN
FN6892 Rev 0.00
May 4, 2010
Page 14 of 15
EL5220T
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
2.00
A
2X 1.50
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
6X 0.50
1
1.80 +0.10/-0.15
3.00
B
(4X)
0.15
8
8X 0.40 ±0.10
TOP VIEW
1.65 +0.10/-0.15
8X 0.25 +0.07/-0.05 4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 ±0.10
0.10 C
(1.65)
(1.50)
(8X 0.60)
C
BASE PLANE
SEATING PLANE
0.08 C
0.05 MAX
SIDE VIEW
(2.80)(1.80)
0.20 REF
C
(6X 0.50)
0.05 MAX
(8X 0.25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compies to JEDEC MO-229 VCED-2.
either a mold or mark feature.
FN6892 Rev 0.00
May 4, 2010
Page 15 of 15
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