EL7232CS-T7

DATASHEET EL7232 FN7283 Rev 4.00 November 12, 2015 Dual Channel, High Speed, High Current Line Driver with 3-State The EL7232 3-state drivers are particularly well suited for ATE and microprocessor based applications. The low quiescent power dissipation makes this part attractive in battery applications. The 2A peak drive capability, makes the EL7232 an excellent choice when driving high speed capacitive lines, as well. The input circuitry provides level shifting from TTL levels to the supply rails. The EL7232 is available in 8 Ld PDIP and 8 Ld SO packages. Features Ordering Information • Low, matched output impedance 5 PART NUMBER PART MARKING PACKAGE 8 Ld PDIP PKG. DWG. # EL7232CN No longer available or supported, recommended replacement: EL7232CNZ EL7232CN E8.3 EL7232CNZ (Note) EL7232CN Z 8 Ld PDIP** E8.3 EL7232CSZ (Note) 7232CSZ 8 Ld SOIC (Pb-free) M8.15E EL7232CSZ-T7* (Note) 7232CSZ M8.15E 8 Ld SOIC (Pb-free) Tape and Reel EL7232CSZ-T13* (Note) 7232CSZ • 3-State output • 3V and 5V input compatible • Clocking speeds up to 10MHz • 20ns Switching/delay time • 2A Peak drive • Low quiescent current 2.5mA • Wide operating voltage 4.5V to 16V • Pb-free available (RoHS compliant) Applications • Parallel bus line drivers • EPROM and PROM programming • Motor controls M8.15E 8 Ld SOIC (Pb-free) Tape and Reel *-T7” suffix for 1k unit or “-T13” suffix for 2.5k unit Tape and Reel options. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Charge pumps • Sampling circuits • Pin drivers • Bridge circuits Pinout EL7232 (8 LD PDIP, SO) TOP VIEW 3-STATE V+ A IN A OUT 3-STATE B OUT B IN GND Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047 Truth Table FN7283 Rev 4.00 November 12, 2015 3-STATE INPUT OUTPUT 1 0 1 1 1 0 0 0 Open 0 1 Open Page 1 of 8 EL7232 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER TA = +25°C, V = 15V unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current VHVS Input Hysteresis 2.4 @V+ V 0.1 @0V 0.1 10 µA 0.8 V 10 µA 0.3 V OUTPUT ROH Pull-Up Resistance IOUT = -100mA 3 6  ROL Pull-Down Resistance IOUT = +100mA 4 6  IOFF 3-State Output Leakage VOUT = V+ VOUT = 0V 10 µA IPK Peak Output Current Source Sink IDC Continuous Output Current Source/Sink 0.2 2.0 2.0 A 100 mA POWER SUPPLY IS Power Supply Current VS Operating Voltage 1 4.5 AC Electrical Specifications PARAMETER Inputs High 2.5 mA 16 V MAX UNITS TA = +25°C, V = 15V unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP SWITCHING CHARACTERISTICS tR Rise Time CL = 500pF CL = 1000pF 7.5 10 tF Fall Time CL = 500pF CL = 1000pF 10 13 20 tD-ON Turn-On Delay Time 18 25 ns tD-OFF Turn-Off Delay Time 20 25 ns HIZ-ON Three-State Delay, Enable 22 ns HIZ-OFF Three-State Delay, Disable 22 ns FN7283 Rev 4.00 November 12, 2015 ns ns Page 2 of 8 EL7232 Timing Table Standard Test Configuration Simplified Schematic Typical Performance Curves FIGURE 1. MAX POWER/DERATING CURVES FN7283 Rev 4.00 November 12, 2015 FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE Page 3 of 8 EL7232 Typical Performance Curves (Continued) FIGURE 3. INPUT CURRENT vs VOLTAGE FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE FIGURE 5. QUIESCENT SUPPLY CURRENT FIGURE 6. ON-RESISTANCE vs SUPPLY VOLTAGE FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY FN7283 Rev 4.00 November 12, 2015 FIGURE 8. AVERAGE SUPPLY CURRENT vs CAPACITIVE LOAD Page 4 of 8 EL7232 Typical Performance Curves (Continued) FIGURE 9. RISE/FALL TIME vs LOAD FIGURE 10. RISE/FALL TIME vs SUPPLY VOLTAGE FIGURE 11. PROPAGATION DELAY vs SUPPLY VOLTAGE FIGURE 12. RISE/FALL TIME vs TEMPERATURE FIGURE 13. PROPAGATION DELAY vs TEMPERATURE FN7283 Rev 4.00 November 12, 2015 Page 5 of 8 EL7232 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION November 12, 2015 FN7283.4 CHANGE Added Rev History and About Intersil Verbiage. Updated Ordering Information on page 1 Updated POD MDP0031 to E8.3 Updated POD MDP0027 to M8.15E About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7283 Rev 4.00 November 12, 2015 Page 6 of 8 EL7232 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN7283 Rev 4.00 November 12, 2015 Page 7 of 8 EL7232 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7283 Rev 4.00 November 12, 2015 Page 8 of 8