EL7531IYZ-T7

DATASHEET EL7531 FN7428 Rev 10.00 December 10, 2015 Monolithic 1A Step-Down Regulator with Low Quiescent Current The EL7531 is a synchronous, integrated FET 1A step-down regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The EL7531 features automatic PFM/PWM mode control, or PWM mode only. The PWM frequency is typically 1.4MHz and can be synchronized up to 12MHz. The typical no load quiescent current is only 120µA. Additional features include a Power-Good output, 2.5V) forces the converter into PWM mode in the next switching cycle regardless of output current. The duration of the transition varies depending on the output current. Figures 22 and 23 (under two different loading conditions) show the device goes from PFM to PWM mode. Note: In forced PWM mode, the IC will continue to start-up in PFM mode to support pre-biased load applications. Start-Up and Shut-Down When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The inductor current limit is gradually increased to ensure proper soft-start operation. When the EN pin is connected to a logic low, the EL7531 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1µA. When the EN reaches logic HI, the regulator repeats the startup procedure, including the soft-start function. Current Limit and Short-Circuit Protection The current limit is set at about 2A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point. Thermal Shut-Down Once the junction reaches about 145°C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn FN7428 Rev 10.00 December 10, 2015 Page 9 of 12 EL7531 off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130°C, the regulator will restart again in the same manner as EN pin connects to logic HI. Thermal Performance The EL7531 is available in a fused-lead MSOP10 package. Compared with regular MSOP10 package, the fused- lead package provides lower thermal resistance. The JA is 100°C/W on a 4-layer board and 125°C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. Power Good Output The PG (pin 8) output is used to indicate when the output voltage is properly regulating at the desired set point. It is an open-drain output that should be tied to VIN or VCC through a 100k resistor. If no faults are detected, EN is high, and the output voltage is within ~5% of regulation, the PG pin will be allowed to go high. Otherwise, the open-drain NMOS will pull PG low. handle the 2A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the Typical Application Diagram). The phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow the equation below: 1 f Z = ---------------------2R 2 C 4 Over a normal range of R2 (~10-100k), C4 will range from ~470-4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set point. The equation below shows the pole frequency relationship: 1 f P = --------------------------------------2  R 1 R 2 C 4 Output Voltage Selection Layout Considerations Users can set the output voltage of the variable version with a resister divider, which can be chosen based on the following formula: The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: R 2  V O = 0.8   1 + ------- R 1  Component Selection 1. Separate the Power Ground ( ) and Signal Ground ( connect them only at one point right at the pins ); 2. Place the input capacitor as close to VIN and PGND pins as possible Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. We recommend 10µf to 22µF multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5 to 2.2µH for the inductor. 3. Make the following PC traces as small as possible: The RMS current present at the input capacitor is decided by the following formula: 8. Place several via holes under the chip to additional ground plane to improve heat dissipation V O   V IN – V O  I INRMS = -----------------------------------------------  I O V IN 4. from LX pin to L 5. from CO to PGND 6. If used, connect the trace from the FB pin to R1 and R2 as close as possible 7. Maximize the copper area around the PGND pin The demo board is a good example of layout based on this outline. Please refer to the EL7531 Application Brief. This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as:  V IN – V O   V O I IL = -------------------------------------------L  V IN  f S L is the inductance fS the switching frequency (nominally 1.4MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must FN7428 Rev 10.00 December 10, 2015 Page 10 of 12 EL7531 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 10, 2015 FN7428.10 CHANGE - Updated Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. - Replaced POD from MDP0043 to M10.118A. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2004-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN7428 Rev 10.00 December 10, 2015 Page 11 of 12 EL7531 Package Outline Drawing M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0 ± 0.1 A 0.25 10 DETAIL "X" CAB 0.18 ± 0.05 SIDE VIEW 2 4.9 ± 0.15 3.0 ± 0.1 1.10 Max B PIN# 1 ID 1 2 0.95 BSC 0.5 BSC TOP VIEW Gauge Plane 0.86 ± 0.09 H 0.25 C 3°±3° SEATING PLANE 0.10 ± 0.05 0.23 +0.07/ -0.08 0.08 C A B 0.55 ± 0.15 0.10 C DETAIL "X" SIDE VIEW 1 5.80 4.40 3.00 NOTES: 0.50 0.30 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. 4. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L. FN7428 Rev 10.00 December 10, 2015 Page 12 of 12