EL7551CUZ-T7

DATASHEET NOT RECOMMENDED FOR NEW DESIGNS SEE EL7531 OR EL7536 EL7551 FN7291 Rev 1.00 March 21, 2006 Monolithic 1Amp DC:DC Step-down Regulator The EL7551 is an integrated, synchronous step-down regulator with output voltage adjustable from 1.0V to 3.8V. It is capable of delivering 1A continuous current at up to 95% efficiency. The EL7551 operates at a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented on-chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. The EL7551 is available in a fused-lead 16-pin QSOP package. With proper external components, the whole converter fits into a less than 0.4 in2 area. The minimal external components and small size make this EL7551 ideal for desktop and portable applications. Features • Integrated synchronous MOSFETs and current mode controller • 1A continuous output current • Up to 95% efficiency • 4.5V to 5.5V input voltage • Adjustable output from 1V to 3.8V • Cycle-by-cycle current limit • Precision reference • ±0.5% load and line regulation • Adjustable switching frequency to 1.2MHz The EL7551 is specified for operation over the -40°C to +85°C temperature range. • Oscillator synchronization possible • Internal soft start Pinout • Over temperature protection EL7551 (16-PIN QSOP) TOP VIEW • Under voltage lockout • 16-pin QSOP package • Pb-free plus anneal available (RoHS compliant) C3 C4 0.1µF 270pF 1 SGND PGND 16 2 COSC VREF 15 Applications C5 0.1µF R3 3 VDD 39 FB 14 4 PGND VDRV 13 5 PGND LX 12 6 VIN LX 11 7 VIN VHI 10 8 EN PGND 9 • DSP, CPU Core and IO Supplies R2 R1 2.37k 1k • Logic/Bus Supplies L1 C1 10µF ceramic VIN (4.5V-5.5V) 10µH C6 0.1µF • Portable Equipment C7 VO 47µF (3.3V,1A) • DC:DC Converter Modules • GTL + Bus Power Supply Ordering Information PART PART NUMBER MARKING Manufactured under U.S. Patent No. 57,323,974 PACKAGE TAPE & REEL PKG. DWG. # EL7551CU 7551CU 16-Pin QSOP - MDP0040 EL7551CU-T7 7551CU 16-Pin QSOP 7” MDP0040 EL7551CU-T13 7551CU 16-Pin QSOP 13” MDP0040 EL7551CUZ (See Note) 7551CUZ 16-Pin QSOP (Pb-free) - MDP0040 EL7551CUZ-T7 (See Note) 7551CUZ 16-Pin QSOP (Pb-free) 7” MDP0040 EL7551CUZ-T13 7551CUZ (See Note) 16-Pin QSOP (Pb-free) 13” MDP0040 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7291 Rev 1.00 March 21, 2006 Page 1 of 9 EL7551 EL7551 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VIN or VDD and GND . . . . . . . . . . . . +6.5V VLX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN +0.3V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VDD +0.3V VHI Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VLX +6V Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +135° CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VDD = VIN = 5V, TA = TJ = 25°C, COSC = 1.2nF, unless otherwise specified. DESCRIPTION VREF Reference Accuracy VREFTC Reference Temperature Coefficient VREFLOAD Reference Load Regulation VRAMP Oscillator Ramp Amplitude IOSC_CHG Oscillator Charge Current IOSC_DIS CONDITIONS MIN TYP MAX UNIT 1.24 1.26 1.28 V 50 0 < IREF < 50µA ppm/°C -1 % 1.15 V 0.1V < VOSC < 1.25V 200 µA Oscillator Discharge Current 0.1V < VOSC < 1.25V 8 mA IVDD+VDRV VDD+VDRV Supply Current VEN = 4V, FOSC = 120kHz IVDD_OFF VDD Standby Current EN = 0 VDD_OFF VDD for Shutdown VDD_ON VDD for Startup TOT Over Temperature Threshold 135 °C THYS Over Temperature Hysteresis 20 °C ILEAK Internal FET Leakage Current ILMAX Peak Current Limit RDSON FET On Resistance RDSONTC RDSON Tempco VFB Output Initial Accuracy ILOAD = 0A VFB_LINE Output Line Regulation VIN = 5V, VIN = 10%, ILOAD = 0A 0.5 % VFB_LOAD Output Load Regulation 0.1A < ILOAD < 1A 0.5 % VFB_TC Output Temperature Stability -40°C < TA < 85°C, ILOAD = 0.5A ±1 % IFB Feedback Input Pull Up Current VFB = 0V 100 200 nA VEN_HI EN Input High Level 3.2 4 V VEN_LO EN Input Low Level IEN Enable Pull Up Current FN7291 Rev 1.00 March 21, 2006 3.5 5 mA 1 1.5 mA 3.5 4 V 3.95 4.45 V EN = 0, LX = 5V (low FET), LX = 0V (high FET) 10 2 Wafer level test only A 45 95 0.2 0.960 0.975 1 VEN = 0 -4 µA m m/°C 0.99 V V -2.5 µA Page 2 of 9 EL7551 EL7551 Closed-Loop AC Electrical Specifications PARAMETER VS = VIN = 5V, TA = TJ = 25°C, COSC = 1.2nF, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 105 117 130 kHz FOSC Oscillator Initial Accuracy tSYNC Minimum Oscillator Sync Width 25 ns MSS Soft Start Slope 0.5 V/ms tBRM FET Break Before Make Delay 15 ns tLEB High Side FET Minimum On Time 150 ns DMAX Maximum Duty Cycle 95 % Pin Descriptions PIN NUMBER PIN NAME 1 SGND Control circuit negative supply. 2 COSC Oscillator timing capacitor. FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in µF. 3 VDD 4 PGND Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET. 5 PGND Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET. 6 VIN Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET. 7 VIN Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET. 8 EN Chip Enable, active high. A 2µA internal pull-up current enables the device if the pin is left open. 9 PGND 10 VHI Positive supply of the high-side driver. 11 LX Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage. 12 LX Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage. 13 VDRV 14 FB 15 VREF Bandgap reference bypass capacitor. Typically 0.1µF to GND. 16 PGND Ground return of the regulator. FN7291 Rev 1.00 March 21, 2006 PIN FUNCTION Control circuit positive supply. Ground return of the regulator. Positive supply of the low-side driver and input voltage for the high-side boot strap. Voltage feedback input. Connected to an external resistor divider between VOUT and GND. A 125nA pull-up current forces VOUT to VS in the event that FB is floating. Page 3 of 9 EL7551 EL7551 Typical Performance Curves 100 Efficiency vs IO VIN=5V 0.25 VO=2.5V 95 VO=1.8V VO=1.5V 0.2 Power Loss (W) 90 Efficiency (%) Power Loss vs IO VIN=5V 85 80 VO=3.3V VO=1.2V VO=1V 75 70 VO=3.3V 0.1 0.05 FS=500kHz 65 0.15 VO=1V L=Coilcraft DO3316P-472 60 0.1 0 0.2 0.4 0.6 0.8 1 0 0.2 100 0.8 1 0.8 1 Output Current IO (A) Efficiency vs IO VO=3.3V 0.6 Load Regulation VO=3.3V VIN=4.5V 95 0.4 Output Voltage (%) 90 Efficiency (%) 0.6 0.4 Load Current IO (A) VIN=5V 85 VIN=5.5V 80 75 70 0.2 VIN=5V 0 VIN=4.5V -0.2 -0.4 FS=500kHz 65 VIN=5.5V L=Coilcraft DO3316P-472 60 -0.6 0 0.2 0.4 0.6 0.8 1 0 0.2 0.6 Load Current IO (A) Line Regulation VO=3.3V VREF vs Temperature 1.258 0.5 1.256 0.4 1.254 IO=0.1A 0.2 VREF (V) VO (%) 0.3 0.1 IO=1A 0 -0.1 1.25 1.248 1.244 -0.3 4.7 4.9 5.1 VIN (V) FN7291 Rev 1.00 March 21, 2006 1.252 1.246 -0.2 -0.4 4.5 0.6 0.4 Load Current IO (A) 5.3 5.5 1.242 -40 10 60 110 160 Temperature (°C) Page 4 of 9 EL7551 EL7551 Typical Performance Curves (Continued) Oscillator Frequency vs Temperature Input Current vs Temperature (Enable connected to GND) 0.96 VIN=5.5V 0.94 385 Input Current (mA) Oscillator Frequency (kHz) 390 380 375 370 365 0.92 VIN=5V 0.9 VIN=4.5V 0.88 0.86 0.84 0.82 360 -40 0 40 80 120 0.8 -40 10 60 110 160 Temperature (°C) Temperature (°C) Switching Waveforms VIN=5V, VO=3.8V, IO=1A Switching Frequency vs COSC 1400 VI 1200 VLX FS (kHz) 1000 800 600 VO 400 iL 200 0 0 200 400 600 800 1000 COSC (pF) Power-Up VIN=5V, VO=3.8V, IO=1A Transient Response VIN=5V, VO=3.8V, IO=0A-1A iO VIN VO VO FN7291 Rev 1.00 March 21, 2006 Page 5 of 9 EL7551 EL7551 Typical Performance Curves (Continued) Power-Down VIN=5V, VO=3.8V, IO=1A Releasing EN VIN=5V, VO=3.8V, IO=1A VIN VO VIN VO Short-Circuit Protection VIN=5V Shut-Down VIN=5V, VO=3.8V, IO=1A EN iO VO VO Block Diagram 0.1µF VREF Voltage Reference 270pF COSC Oscillator Thermal Shut-down VDRV VHI Controller Supply 39 VDD VIN Power 0.1µF PWM Controller 0.1µF FET 10µH Drivers VOUT Power 47µF FET PGND EN 2370 1k Current Sense SGND FN7291 Rev 1.00 March 21, 2006 FB Page 6 of 9 EL7551 EL7551 Applications Information Circuit Description General The EL7551 is a fixed frequency, current mode controlled DC:DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all the active circuitry required to implement a cost effective, userprogrammable 1A synchronous step-down regulator suitable for use in DSP core power supplies. Theory of Operation The EL7551 is composed of 5 major blocks: 1. PWM Controller 2. NMOS Power FETs and Drive Circuitry 3. Bandgap Reference 4. Oscillator 5. Thermal Shut-down PWM Controller The EL7551 regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-averaged of the modulator output, the relatively large LC time constant found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter and can react more quickly to changes in line and load conditions. This feedforward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the current-feedback to voltage-feedback ratio the overall loop response will approach a one-pole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. The heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles FN7291 Rev 1.00 March 21, 2006 greater than 50% and is also used to define the open-loop gain of the overall system. The slope compensation is fixed internally and optimized for 500mA inductor ripple current. The power tracking will not contribute any input to the comparator steady-state operation. Current feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on. The comparator inputs are gated off for a minimum period of time of about 150ns (LEB) after the highside switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. If the inductor current exceeds the maximum current limit (ILMAX) a secondary over-current comparator will terminate the high-side switch on time. If ILMAX has not been reached, the feedback voltage FB derived from the regulator output voltage VOUT is then compared to the internal feedback reference voltage. The resultant error voltage is summed with the current feedback and slope compensation ramp. The high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-before-make delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic control signal. Output Voltage Setting In general: R 2  V OUT = 0.975V   1 + ------- R 1  However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loopgain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating. NMOS Power FETs and Drive Circuitry The EL7551 integrates low on-resistance (60m) NMOS FETs to achieve high efficiency at 1A. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 5V. At the beginning of the next cycle the high-side switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 10V, for VDRV=VIN=5V. This voltage is Page 7 of 9 EL7551 EL7551 then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.1µF for CVHI is recommended. and temperature variations. Figure 1 shows a typical connection. Reference A 1.5% temperature compensated bandgap reference is integrated in the EL7551. The external VREF capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1µF is recommended. 100pF External Oscillator Oscillator The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommodate component 1 16 2 15 3 14 6 11 7 10 8 9 BAT54S EL7551 FIGURE 1. OSCILLATOR SYNCHRONIZATION Thermal Shut-down An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135°C and 115°C respectively. Start-up Delay A capacitor can be added to the EN pin to delay the converter start-up (Figure 2) by utilizing the pull-up current. The delay time is approximately: t d  ms  = 1200  C  F  1 16 2 15 3 14 6 11 7 10 8 9 VOUT VIN C VO td TIME EL7551 FIGURE 2. START-UP DELAY FN7291 Rev 1.00 March 21, 2006 Page 8 of 9 EL7551 EL7551 Layout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to pin 14 (FB) is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. The demo board is a good example of layout based on these principles. Please refer to the EL7551 Application Brief for the layout. © Copyright Intersil Americas LLC 2002-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7291 Rev 1.00 March 21, 2006 Page 9 of 9