EL8100IS-T13

DATASHEET EL8100, EL8101 FN7103 Rev 9.00 September 14, 2010 200MHz Rail-to-Rail Amplifiers The EL8100 and EL8101 represent single rail-to-rail amplifiers with a -3dB bandwidth of 200MHz and slew rate of 200V/µs. Running off a very low 2mA supply current, the EL8100 and EL8101 also feature inputs that go to 0.15V below the VS- rail. The EL8100 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8100 is ideal for multiplexing applications. The EL8100 and EL8101 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8100 is available in 8 Ld SO and 6 Ld SOT-23 packages and the EL8101 is available in a 5 Ld SOT-23 package. All are specified for operation over the -40°C to +85°C temperature range. Ordering Information PART NUMBER (Note 1) PART MARKING Features • 200MHz -3dB bandwidth • 200V/µs slew rate • Low supply current = 2mA • Supplies from 3V to 5.0V • Rail-to-rail output • Input to 0.15V below VS• Fast 25ns disable (EL8100 only) • Low cost • Pb-Free (RoHS compliant) Applications • Video amplifiers PKG. DWG. # PACKAGE EL8100ISZ 8100ISZ 8 Ld SOIC (Pb-Free) M8.15E EL8100ISZ-T7* 8100ISZ 8 Ld SOIC (Pb-Free) M8.15E EL8100ISZ-T13* 8100ISZ 8 Ld SOIC (Pb-Free) M8.15E EL8100IWZ-T7* BASA (Note 2) 6 Ld SOT-23 (Pb-free) P6.064A EL8100IWZ-T7A* BASA (Note 2) 6 Ld SOT-23 (Pb-free) P6.064A EL8101IWZ-T7* BATA (Note 2) 5 Ld SOT-23 (Pb-Free) P5.064A EL8101IWZ-T7A* BATA (Note 2) 5 Ld SOT-23 (Pb-Free) P5.064A • Portable/hand-held products • Communications devices Pinouts EL8100 (8 LD SOIC) TOP VIEW NC 1 IN- 2 IN+ 3 + VS- 4 NOTES: 6 OUT 5 NC OUT 1 VS- 2 6 VS+ + - IN+ 3 2. The part marking is located on the bottom of the part. 5 ENABLE 4 IN- EL8101 (5 LD SOT-23) TOP VIEW OUT 1 VS- 2 IN+ 3 FN7103 Rev 9.00 September 14, 2010 7 VS+ EL8100 (6 LD SOT-23) TOP VIEW *Please refer to TB347 for details on reel specifications. 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 8 ENABLE 5 VS+ + 4 IN- Page 1 of 14 EL8100, EL8101 EL8100, EL8101 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = +25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT -6 -0.8 +6 mV INPUT CHARACTERISTICS VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V IOS Input Offset Current VIN = 0V TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V CMIR Common Mode Input Range RIN Input Resistance CIN Input Capacitance AVOL Open Loop Gain -2.1 3 µV/°C -1.5 µA 0.2 70 µA 2 nA/°C 90 dB VS- -0.15 Common Mode 0.55 VS+ -1.5 V 16 M 0.5 pF 90 dB VOUT = +1.5V to +3.5V, RL = 150 to GND 80 dB 30 m VOUT = +1.5V to +3.5V, RL = 1k to GND 75 OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 VOP Positive Output Voltage Swing RL = 1k 4.85 4.9 V RL = 150 4.6 4.7 V VON Negative Output Voltage Swing RL = 150 100 150 mV RL = 1k 35 50 mV IOUT Linear Output Current 65 mA ISC (source) Short Circuit Current RL = 10 60 70 mA ISC (sink) Short Circuit Current RL = 10 120 140 mA VS+ = 4.5V to 5.5V 75 100 dB POWER SUPPLY PSRR Power Supply Rejection Ratio IS-ON Supply Current - Enabled 2 IS-OFF Supply Current - Disabled 30 µA 2.4 mA ENABLE (EL8100 ONLY) tEN Enable Time 200 ns tDS Disable Time 25 ns FN7103 Rev 9.00 September 14, 2010 Page 2 of 14 EL8100, EL8101 EL8100, EL8101 Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = +25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. (Continued) DESCRIPTION MIN (Note 3) CONDITIONS TYP MAX (Note 3) UNIT VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-down 2 V IIH-ENB ENABLE Pin Input Current High 8.6 µA IIL-ENB ENABLE Pin Input for Current Low 0.01 µA AV = +1, RF = 0, CL = 5pF 200 MHz AV = -1, RF = 1k, CL = 5pF 90 MHz AV = +2, RF = 1k, CL = 5pF 90 MHz AV = +10, RF = 1k, CL = 5pF 10 MHz AC PERFORMANCE BW -3dB Bandwidth BW ±0.1dB Bandwidth AV = +1, RF = 0, CL = 5pF 20 MHz Peak Peaking AV = +1, RF = 1k, CL = 5pF 1 dB GBWP Gain Bandwidth Product 100 MHz PM Phase Margin RL = 1k, CL = 5pF 55 ° SR Slew Rate AV = 2, RL = 100, VOUT = 0.5V to 4.5V 200 V/µs tR Rise Time 2.5VSTEP, 20% to 80% 8 ns tF Fall Time 2.5VSTEP, 20% to 80% 7 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 2 ns tS 0.1% Settling Time 200mV step 20 ns dG Differential Gain AV = +2, RF = 1k, RL = 150 0.035 % dP Differential Phase AV = +2, RF = 1k, RL = 150 0.05 ° eN Input Noise Voltage f = 10kHz 10 nV/Hz iN+ Positive Input Noise Current f = 10kHz 1 pA/Hz iN- Negative Input Noise Current f = 10kHz 0.8 pA/Hz 160 NOTE: 3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Pin Descriptions PIN NUMBER EL8100IS (8 Ld SOIC) EL8100IW (6 Ld SO- 23) EL8101IW 5 Ld SOT-23) 1, 5 PIN NAME DESCRIPTION NC Not connected 2 4 4 IN- Inverting input 3 3 3 IN+ Non-inverting input 4 2 2 VS- Negative power supply 6 1 1 OUT Amplifier output 7 6 5 VS+ Positive power supply 8 5 FN7103 Rev 9.00 September 14, 2010 ENABLE Enable and disable input Page 3 of 14 EL8100, EL8101 EL8100, EL8101 Simplified Schematic Diagram VS+ I1 I2 Q5 Q7 R2 Q1 IN+ R8 VBIAS1 Q6 R3 R1 R7 R6 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- Typical Performance Curves GAIN (dB) 2 4 VS = 5V AV = 1 RL = 1k CL = 5pF 2 VOP-P = 200mV GAIN (dB) 4 0 VOP-P = 1V -2 -6 100k 1M 10M RL = 330 0 RL = 1k -2 RL = 100 VOP-P = 2V -4 VS = 5V AV = 1 CL = 5pF -4 100M -6 100k 1G 1M FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS 4 AV = 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 AV = 1 0 -2 AV = 5 -4 -6 100k AV = 10 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS FN7103 Rev 9.00 September 14, 2010 100M 1G FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD 4 VS = 5V RL = 1k CL = 5pF 10M FREQUENCY (Hz) FREQUENCY (Hz) 2 VS = 5V RL = 1k CL = 5pF RF = 1k AV = -5 0 AV = -2 -2 AV = -10 -4 -6 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS Page 4 of 14 EL8100, EL8101 EL8100, EL8101 Typical Performance Curves (Continued) 10 CL = 15pF CL = 11.5pF 1 CL = 8.3pF CL = 56pF 8 CL = 5pF -1 VS = 5V -3 AV = 1 RL = 1k VOP-P = 200mV -5 100k 1M 6 CL = 15pF 4 CL = 1.5pF 10M CL = 35pF VS = 5V AV = 2 RL = 1k RF = RG = 1k 2 100M 0 100k 1G 1M FREQUENCY (Hz) 110 RF = RG = 500 VS = 5V AV = 2 RL = 1k CL = 5pF 0 100k 315 RL = 150 GAIN (dB) GAIN (dB) 2 30 225 RL = 150 -10 10M 100M 1G 135 RL = 1k -50 1M -90 1k 10k 45 100k FREQUENCY (Hz) 1M -45 1G 230 210 BANDWIDTH (MHz) -30 CMRR (dB) 100M FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 -50 -70 -90 1M 10M 100M FREQUENCY (Hz) FIGURE 9. COMMON-MODE REJECTION RATIO vs FREQUENCY AV = 1 190 170 150 130 110 90 70 FN7103 Rev 9.00 September 14, 2010 10M FREQUENCY (Hz) FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RF AND RG -110 100k 1G 405 RL = 1k 70 RF = RG = 1k 6 4 100M FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL 10 RF = RG = 2k 10M FREQUENCY (Hz) FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL 8 CL = 5pF PHASE (°) 3 GAIN (dB) GAIN (dB) 5 50 3.0 RL = 1k CL = 5pF 3.5 AV = 2 4.0 4.5 5.0 5.5 VS (V) FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE Page 5 of 14 EL8100, EL8101 EL8100, EL8101 Typical Performance Curves (Continued) 2.5 2.0 10 PEAKING (dB) IMPEDANCE () 100 1.0 0.1 1.5 1.0 0.5 0.01 10k 100k 1M 10M 0 3.0 100M AV = 1 RL = 1k CL = 5pF 4.0 3.5 4.5 FREQUENCY (Hz) -10 -45 -30 -55 PSRR- -70 5.5 FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE DISTORTION (dBc) PSRR (dB) FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY -50 5.0 VS (V) PSRR+ VS = 5V RL = 1k CL = 5pF AV = 2 @ HD2 -65 HD -75 z HD2@5MH MHz @10 HD3 3@5MHz 1 HD2@ -85 -90 z 10MH MHz HD3@1MHz -110 1k 10k 100k 1M 10M -95 100M 1 2 3 FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUENCY GAIN (dB) -30 -30 VS = 5V AV = 1 RL = 1k CL = 5pF VS = 5V RL = 1k VO = 1VP-P for AV = 1 VO = 2VP-P for AV = 2 -40 -50 -70 -90 -110 1k -50 -60 -70 2 HD -80 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 15. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE FN7103 Rev 9.00 September 14, 2010 -100 2@ HD =2 @A V 3@ HD -90 10k 5 FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE DISTORTION (dBc) -10 4 VOP-P (V) FREQUENCY (Hz) =1 AV 2 A V= HD3@AV=1 1 10 40 FREQUENCY (MHz) FIGURE 16. HARMONIC DISTORTION vs FREQUENCY Page 6 of 14 EL8100, EL8101 EL8100, EL8101 Typical Performance Curves (Continued) -60 1.0k DISTORTION (dBc) -65 HD 3@ -70 -75 HD -80 AV = -90 2 HD2@A =1 V 3@ A V= -85 AV =2 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz) HD2@ 1 VS = 5V VO = 1VP-P for AV = 1 VO = 2VP-P for AV = 2 -95 -100 100 1K 2K 100 IN0.1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY VS = 5V, AV = 5, RL = 1k TO 2.5V VS = 5V, AV = 1, RL = 1k TO 2.5V 5.0 5.0 2.5 2.5 0 0 10ns/DIV 2µs/DIV FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 20. OUTPUT SWING VS = 5V, AV = 1, RL = 1k TO 2.5V CL= 5pF VS = 5V, AV = 5, RL = 1k TO 2.5V 5.0 2.6 2.5 2.5 2.4 0 10ns/DIV FIGURE 21. SMALL SIGNAL TRANSIENT RESPONSE FN7103 Rev 9.00 September 14, 2010 IN+ 1.0 RLOAD () FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE eN 10 2µs/DIV FIGURE 22. OUTPUT SWING Page 7 of 14 EL8100, EL8101 EL8100, EL8101 Typical Performance Curves (Continued) VS = ±2.5V, AV = 1, RL = 1k VS = ±2.5V, AV = 1, RL = 1k CH1 CH1 CH2 ENABLE INPUT ENABLE INPUT CH2 VOUT OUTPUT CH1, CH2, 0.5V/DIV, M = 20ns CH1, CH2, 1V/DIV, M = 100ns FIGURE 23. DISABLED RESPONSE FIGURE 24. ENABLED RESPONSE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 0.9 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 1.0 909mW 0.8 SO8 JA = +110°C/W 0.6 435mW 0.4 SOT23-5/6 JA = +230°C/W 0.2 0 0 25 50 0.8 0.7 625mW 0.6 0.5 0.3 0.2 SOT23-5/6 JA = +256°C/W 0.1 75 85 100 125 150 AMBIENT TEMPERATURE (°C) SO8 JA = +160°C/W 391mW 0.4 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Description of Operation and Application Information The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. Product Description The EL8100, EL8101 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1k load, the EL8100, EL8101 have a -3dB bandwidth of 200MHz. Driving a 150 load, the bandwidth is about 130MHz while maintaining a 200V/µs slew rate. The EL8100 is available with a power-down pin to reduce power to 30µA typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8100, EL8101 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. FN7103 Rev 9.00 September 14, 2010 The output of the EL8100, EL8101 can swing rail-to-rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1k, the output swing is about 4.9V at a 5V supply. For the load resistor 150, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier’s phase margin is reduced. This causes ringing in the time domain Page 8 of 14 EL8100, EL8101 EL8100, EL8101 and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300 to 1k. The EL8100, EL8101 have a gain bandwidth product of 100MHz. For gains 5, its bandwidth can be predicted by Equation 1: Gain  BW = 100MHz (EQ. 1) turn-on time is about 200ns. When disabled, the amplifier’s supply current is reduced to 30µA typically, thereby effectively eliminating the power consumption. The amplifier’s power-down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at the ENABLE pin is 2V above VS-. Output Drive Capability The EL8100, EL8101 do not have internal short circuit protection circuitry. They have a typical short circuit current of 70mA sourcing and 140mA sinking for the output is connected to half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnections. Video Performance Power Dissipation For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because the change in output current with DC level. Special circuitry has been incorporated in the EL8100, EL8101 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.03% and 0.05, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. With the high output drive capability of the EL8100, EL8101, it is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. Driving Capacitive Loads and Cables The EL8100, EL8101 can drive 15pF loads in parallel with 1k with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier’s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL8100 can be disabled and placed its output in a high impedance state. The turn-off time is about 25ns and the FN7103 Rev 9.00 September 14, 2010 The maximum power dissipation allowed in a package is determined according to Equation 2: T JMAX – T AMAX PD MAX = -------------------------------------------- JA (EQ. 2) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing, Equation 3: V OUT PD MAX = V S  I SMAX +  V S – V OUT   ---------------R (EQ. 3) L For sinking, Equation 4: PD MAX = V S  I SMAX +  V OUT – V S -   I LOAD (EQ. 4) Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current Page 9 of 14 EL8100, EL8101 EL8100, EL8101 VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. and VIN2 is passed through to the output. The break-before-make operation ensures that more than one amplifier isn’t trying to drive the bus at the same time. 5V VIN - 1k 1K FIGURE 27. SYNC PULSE REMOVER 1.0V 0.5V VIN 0V 1.0V 0.5V VOUT 0V M = 10µs/DIV FIGURE 28. VIDEO SIGNAL +2.5V B 2MHz 1VP-P + 75 -2.5V Typical Applications 1k 1K Video Sync Pulse Remover Multiplexer VOUT 75 As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 27 shows a gain of 2 connections for EL8100, EL8101. Figure 28 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. 75 VS- 75 Power Supply Bypassing and Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier’s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. VS+ + 75 +2.5V A 2MHz 2VP-P 75 + - 75 -2.5V 1k 1K ENABLE FIGURE 29. TWO TO ONE MULTIPLEXER Besides the normal power-down usage, the ENABLE pin of the EL8100 can be used for multiplexing applications. Figure 29 shows two EL8100s with the outputs tied together, driving a back terminated 75 video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 30 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the break-before-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on FN7103 Rev 9.00 September 14, 2010 VOUT Page 10 of 14 EL8100, EL8101 EL8100, EL8101 RF 1k 0V -0.5V ENABLE VIN -1.5V C1 RG 47µF 500 - R3 C3 470µF 75 VOUT + 5V RT 75 -2.5V 5V R1 10k 1V 75 0V B A R2 10k -1V C2 220µF FIGURE 32. 5V SINGLE SUPPLY INVERTING VIDEO LINE DRIVER M = 50ns/DIV FIGURE 30. ENABLE SIGNAL Single Supply Video Line Driver 5V 5 4 NORMALIZED GAIN (dB) The EL8100, EL8101 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 31 is the single supply non-inverting video line driver configuration and Figure 32 is the inverting video ling driver configuration. The signal is AC-coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal. 3 2 1 AV = 2 0 AV = -2 -1 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 200M FIGURE 33. VIDEO LINE DRIVER FREQUENCY RESPONSE VIN C1 47µF R1 10k R3 C3 470µF 75 + RT 75 R2 10k VOUT - 75 RG 1k RF 1k C2 220µF FIGURE 31. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER © Copyright Intersil Americas LLC 2003-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7103 Rev 9.00 September 14, 2010 Page 11 of 14 EL8100, EL8101 EL8100, EL8101 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN7103 Rev 9.00 September 14, 2010 Page 12 of 14 EL8100, EL8101 EL8100, EL8101 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 5 (0.60) 0.20 C 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 H 0.15 C A-B 2x C 1.45 MAX 1.14 ±0.15 0.10 C SIDE VIEW SEATING PLANE (0.25) GAUGE PLANE 0.45±0.1 0.05-0.15 4 DETAIL "X" (0.60) (1.20) NOTES: (2.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN FN7103 Rev 9.00 September 14, 2010 Page 13 of 14 EL8100, EL8101 EL8100, EL8101 Package Outline Drawing P6.064A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° 0.95 D 0.08-0.20 A 5 6 4 PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 1 (0.60) 3 2 0.20 C 2x 0.40 ±0.05 B 5 SEE DETAIL X 3 0.20 M C A-B D TOP VIEW 2.90 5 END VIEW 10° TYP (2 PLCS) 0.15 C A-B 2x H 1.14 ±0.15 C SIDE VIEW 0.10 C 0.05-0.15 1.45 MAX SEATING PLANE DETAIL "X" (0.25) GAUGE PLANE 0.45±0.1 4 (0.60) (1.20) NOTES: (2.40) (0.95) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (1.90) TYPICAL RECOMMENDED LAND PATTERN FN7103 Rev 9.00 September 14, 2010 Page 14 of 14