DATASHEET
EL8176
FN7436
Rev 9.00
January 6, 2015
Micropower Single Supply Rail-to-Rail Input/Output Precision Op Amp
The EL8176 is a precision low power, operational amplifier.
The device is optimized for single supply operation between
2.4V to 5.5V.
Features
The EL8176 draws minimal supply current while meeting
excellent DC-accuracy noise and output drive specifications.
Competing devices seriously degrade these parameters to
achieve micropower supply current.
• 100µV max offset voltage (8 Ld SO)
The EL8176 can be operated from one lithium cell or two Ni-Cd
batteries. The input range includes both positive and negative
rail. The output swings to both rails.
• 55µA supply current
• 2nA input bias current
• 400kHz gain-bandwidth product
• Single supply operation down to 2.4V
• Rail-to-rail input and output
• Output sources 31mA and sinks 26mA load current
• Pb-free (RoHS compliant)
Applications
• Battery- or solar-powered systems
• 4mA to 20mA current loops
• Handheld consumer products
• Medical devices
• Thermocouple amplifiers
• Photodiode pre amps
• pH probe amplifiers
Pin Configurations
EL8176
(8 LD SO)
TOP VIEW
EL8176
(6 LD SOT-23)
TOP VIEW
OUT 1
V- 2
IN+ 3
+ -
6 V+
NC 1
5 EN
IN- 2
4 IN-
IN+ 3
V- 4
FN7436 Rev 9.00
January 6, 2015
8 EN
+
7 V+
6 OUT
5 NC
Page 1 of 16
EL8176
Pin Descriptions
SO PIN
NUMBER
SOT-23 PIN
NUMBER
PIN
NAME
1, 5
Equivalent
Circuit
DESCRIPTION
NC
No internal connection
2
4
IN-
Circuit 1
Amplifier’s inverting input
3
3
IN+
Circuit 1
Amplifier’s non-inverting input
4
2
V-
Circuit 4
Negative power supply
6
1
OUT
Circuit 3
Amplifier’s output
7
6
V+
Circuit 4
Positive power supply
8
5
EN
Circuit 2
Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled
state; Logic “0” selects the enabled state.
V+
IN-
IN+
V+
V+
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
EN
V-
V-
V-
VCIRCUIT 1
V+
CIRCUIT 2
CIRCUIT 3
CIRCUIT 4
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
EL8176FSZ
8176FSZ
8 Ld SO
M8.15E
EL8176FSZ-T7 (Note 1)
8176FSZ
8 Ld SO
M8.15E
EL8176FWZ-T7 (Note 1, 4)
BBVA
6 Ld SOT-23
P6.064A
EL8176FWZ-T7A (Note 1, 4)
BBVA
6 Ld SOT-23
P6.064A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for EL8176. For more information on MSL, please see tech brief TB363.
4. The part marking is located on the bottom of the parts.
FN7436 Rev 9.00
January 6, 2015
Page 2 of 16
EL8176
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS) and Power-up Ramp Rate . . . . . . . . . . . . 5.75V, 1V/µs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Current into IN+, IN-, and EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Resistance (Typical, Note 5)
JA (°C/W)
6 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Ambient Operating Temperature Range . . . . . . . . . . . . . -40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open,VEN = 0V, TA = +25°C, unless otherwise specified. Boldface limits
apply across the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 6)
TYP
-100
±25
MAX
(Note 6)
UNITS
DC SPECIFICATIONS
VOS
Input Offset Voltage
8 Ld SO
-220
6 Ld SOT-23
-350
±80
-350
100
µV
220
µV
350
µV
350
µV
V OS
------------------Time
Long Term Input Offset Voltage Stability
2.4
µV/Mo
V OS
----------------T
Input Offset Drift vs Temperature
0.7
µV/°C
IOS
Input Offset Current
IB
Input Bias Current
CMIR
CMRR
PSRR
AVOL
Input Voltage Range
Common-mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
-1
-2
Guaranteed by CMRR test
VCM = 0V to 5V
0
90
1
nA
4
nA
2
nA
5
nA
5
VS = 2.4V to 5.5V
VO = 0.5V to 4.5V, RL = 100kΩ
90
dB
110
dB
500
V/mV
dB
90
200
dB
200
V/mV
VO = 0.5V to 4.5V, RL = 1kΩ
25
VOL; Output low, RL = 100kΩ
3
VOH; Output high, RL = 100kΩ
130
VOH; Output high, RL = 1kΩ
IS, ON
Supply Current, Enabled
VEN = 5V
IS, OFF
Supply Current, Disabled
VEN = 0V
4.994
V
110
90
Maximum Output Voltage Swing
FN7436 Rev 9.00
January 6, 2015
±0.5
-5
VOL; Output low, RL = 1kΩ
VOUT
±0.4
-4
V/mV
8
mV
10
mV
200
mV
300
mV
4.997
V
4.992
4.750
V
4.867
V
4.7
35
V
55
30
3
75
µA
90
µA
10
µA
10
µA
Page 3 of 16
EL8176
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open,VEN = 0V, TA = +25°C, unless otherwise specified. Boldface limits
apply across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER
IO+
IOVS
DESCRIPTION
Short Circuit Output Sourcing Current
Short Circuit Output Sinking Current
Supply Voltage
VINH
Enable Pin High Level
VINL
Enable Pin Low Level
IENH
Enable Pin Input Current
IENL
Enable Pin Input Current
TEST CONDITIONS
RL = 10Ω
RL = 10Ω
Guaranteed by PSRR test
MIN
(Note 6)
TYP
18
31
mA
26
mA
MAX
(Note 6)
18
17
UNITS
mA
15
mA
2.4
5.5
V
2.4
5.5
V
2
VEN = 5V
VEN = 0V
0.25
-0.5
V
0.7
0
-1
0.8
V
2.0
µA
2.5
µA
+0.5
µA
+1
µA
AC SPECIFICATIONS
GBW
Unity Gain
Bandwidth
eN
Gain Bandwidth Product
AV = 100, Rf = 100kΩRL = 10kΩ
Rg = 1kΩto VCM
400
kHz
-3dB Bandwidth
AV = 1, Rf = 0ΩRL = 100kΩto VCM
VOUT = 10mVP-P
1
MHz
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz,RL = 10kΩto VCM
1.5
µVP-P
Input Noise Voltage Density
fO = 1kHz
28
nV/Hz
Input Noise Current Density
fO = 1kHz
0.16
pA/Hz
Off-State Input to Output Isolation
VEN = 5V, fO = 1kHz, AV = +1, VIN = 1VP-P
-73
dB
Input Common Mode Rejection Ratio
fO = 120Hz; VCM = 1VP-P
-70
dB
PSRR+
Power Supply Rejection Ratio (V+)
fO = 120Hz; V+, V- = ±2.5V, VSOURCE = 1VP-P
-90
dB
PSRR-
Power Supply Rejection Ratio (V-)
fO = 120Hz; V+, V- = ±2.5V, VSOURCE = 1VP-P
-70
dB
iN
ISO
CMRR
TRANSIENT RESPONSE
SR
tr, tf, Large
Signal
tr, tf, Small
Signal
tEN
±0.065
Slew Rate
±0.13
±0.3
V/µs
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10kΩto
VCM
18
µs
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10kΩto
VCM
19
µs
Rise Time, 10% to 90%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 10kΩto VCM
2.4
µs
Fall Time, 90% to 10%, VOUT
AV = +2, VOUT = 10mVP-P,
Rg = Rf = RL = 10kΩto VCM
2.4
µs
4
µs
0.1
µs
Enable to Output Turn-on Delay Time, 10% EN VEN = 5V to 0V, AV = +2,
to 10% VOUT
Rg = Rf = RL = 10kΩto VCM
Enable to Output Turn-off Delay Time, 10%
EN to 10% VOUT
VEN = 0V to 5V, AV = +2,
Rg = Rf = RL = 10kΩto VCM
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7436 Rev 9.00
January 6, 2015
Page 4 of 16
EL8176
Typical Performance Curves
100
200
80
150
PHASE
80
40
40
0
0
-40
-40
-80
-50
0
-100
10
100
1k
10k
FREQUENCY (Hz)
-150
1M
100M
-80
1
10
2
-1
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
0
-2
Rf = Rg= 10k
-4
-5
-6
V+ = 5V
RL = 10k
Rf = Rg = 100k
CL = 8.3pF
-7
AV = +2
-8
VOUT = 10mVP-P
-9
100
Rf = Rg= 1k
1k
1k
10k
100k
VOUT = 100mV
-4
-6
CL = 8.3pF
-7
AV = +1
-8
10
1M
VOUT = 1V
V+ = 5V
RL = 1k
-5
100
1k
1
NORMALIZED GAIN (dB)
2
1
0
-1
VOUT = 100mV
-5
-6
-7
-8
10
V+ = 5V
RL = 10k
VOUT = 1V
CL = 8.3pF
AV = +1
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs VOUT, RL = 10k
FN7436 Rev 9.00
January 6, 2015
100k
1M
10M
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 1k
3
-4
10k
FREQUENCY (Hz)
2
VOUT = 50mV
-120
10M
VOUT = 50mV
-3
3
-3
1M
VOUT = 10mV
-2
FIGURE 3. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES Rf/Rg
VOUT = 10mV
100k
0
-1
FREQUENCY (Hz)
-2
10k
FIGURE 2. AVOL vs FREQUENCY AT 100kΩ LOAD
1
-3
100
FREQUENCY (Hz)
FIGURE 1. AVOL vs FREQUENCY AT 1kΩ LOAD
NORMALIZED GAIN (dB)
PHASE (°)
0
GAIN
GAIN (dB)
40
PHASE (°)
GAIN (dB)
50
-20
80
100
60
20
120
10M
0
-1
-2
VOUT = 10mV
-3
VOUT = 50mV
-4
-5
V+ = 5V
RL = 100k
-6
CL = 8.3pF
-7
AV = +1
-8
10
100
VOUT = 100mV
VOUT = 1V
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 6. GAIN vs FREQUENCY vs VOUT, RL = 100k
Page 5 of 16
EL8176
Typical Performance Curves
(Continued)
70
3
2
1
RL = 10k
-1
RL = 100k
-2
-3
-4
V+ = 5V
RL = 1k
-5
CL = 8.3pF
-6
AV = +1
-7
VOUT = 10mVP-P
-8
10
10k
100k
1M
AV = 10
20
AV = 10, Rg = 1k, Rf = 9.09k
AV = 1
AV = 1, Rg = INF, Rf = 0
-10
10
10M
V+ = 5V
CL = 8.3pF
RL = 10k
VOUT = 10mVP-P
30
0
1k
AV = 101, Rg = 1k, Rf = 100k
AV = 101
40
10
100
AV = 1001, Rg = 1k, Rf = 1M
50
0
GAIN (dB)
NORMALIZED GAIN (dB)
AV = 1001
60
100
1k
1M
10M
45
2
V+ = 2.5V
1
40
0
V+ = 2.5V
RL = 10k
CL = 8.3pF
AV = 100
VOUT = 10mVP-P
Rf = 221kΩ
Rg = 2.23kΩ
35
-1
30
-2
V+ = 5V
-3
GAIN (dB)
GAIN (dB)
100k
FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 7. GAIN vs FREQUENCY vs RL
-4
-5
CL = 8.3pF
V+ = 2V
-7
AV = +1
-8
VOUT = 10mVP-P
-9
1k
25
20
V+ = 5V
15
RL = 10k
-6
10k
V+ = 2V
10
5
100k
1M
0
10M
100
1k
1M
20
CL = 64.3pF
0
CL = 47.3pF
CL = 35.3pF
CMRR (dB)
-20
CL = 26.3pF
CL = 8.3pF
-40
V+ = 5V
RL = OPEN
-60
CL = 8.3pF
-80
AV = +1
-100
100k
1M
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY vs CL
FN7436 Rev 9.00
January 6, 2015
100k
FIGURE 10. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 9. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
6
5
4
3
2
1
0
-1
-2
-3
-4
V+ = 5V
-5
RL = 10k
-6
AV = +1
-7
VOUT = 10mVP-P
-8
-9
1k
10k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
10M
-120
VCM = 1VP-P
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. CMRR vs FREQUENCY; V+, V- = ±2.5V
Page 6 of 16
1M
EL8176
Typical Performance Curves
(Continued)
10
0
0
V+ = 5V
RL = OPEN
-20
PSRR-
AV = +1
-40
PSRR (dB)
-20
CL = 8.3pF
-30
OFF ISOLATION (dB)
-10
-10
VCM = 1VP-P
-50
PSRR+
-60
-70
-80
-90
V+ = 5V
RL = OPEN
CL = 8.3pF
-30
AV = +1
-40
VIN = 1VP-P
-50
-60
-70
-80
-100
-110
-90
-120
-100
1
1
10
100
1k
10k
100k
1M
10
100
FREQUENCY (Hz)
FIGURE 13. PSRR vs FREQUENCY, V+, V- = ±2.5V
10M
10
INPUT CURRENT NOISE (pA√Hz)
V+ = 5V
RL = OPEN
INPUT VOLTAGE NOISE (nV√Hz)
1M
FIGURE 14. OFF ISOLATION vs FREQUENCY; V+, V- = ±2.5V
1000
CL = 8.3pF
AV = +1
100
10
0.1
1
10
100
1k
FREQUENCY (Hz)
V+ = 5V
RL = OPEN
CL = 8.3pF
AV = +1
1
0.1
0.1
10k
1
10
100
1k
10k
FREQUENCY (Hz)
FIGURE 15. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FIGURE 16. INPUT CURRENT NOISE DENSITY vs FREQUENCY
2.5
2.0
V+ = 5V
RL = OPEN
1.5
CL = 8.3pF
1.0 Rg = 10, Rf = 10k
AV = 1000
0.5
2.0
1.5
LARGE SIGNAL (V)
INPUT NOISE (µV)
1k
10k
100k
FREQUENCY (Hz)
0
-0.5
-1.0
-1.5
1.0
0.5
-0.5
V+, V- = ±2.5V
RL = 10k
CL = 8.3pF
Rg = 10k
-1.0
Rf = 30k
-1.5
AV = 4
VOUT = 4VP-P
0
-2.0
-2.0
0
1
2
3
4
5
6
7
8
TIME (s)
FIGURE 17. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
FN7436 Rev 9.00
January 6, 2015
9
10
-2.5
0
50
100
150
200
250
300
350
TIME (µs)
FIGURE 18. LARGE SIGNAL STEP RESPONSE
Page 7 of 16
400
EL8176
Typical Performance Curves
(Continued)
3.0
12
3.0
VENABLE
2.5
10
2.5
2.0
6
V- ENABLE (V)
8
V+, V- = ±2.5V
RL = 10k
CL = 8.3pF
Rg = Rf = 10k
AV = 2
VOUT = 10mVP-P
4
2
1.5
V+, V- = ±2.5V
Rg = Rf = RL = 10k
1.5
1.0
CL = 8.3pF
1.0
AV = +2
0.5
0
-2
2.0
50
100
150
200
250
TIME (µs)
300
350
400
0
-0.5
0
20
40
60
2.0
80
1.5
60
1.0
IBIAS (µA)
VIO (µV)
V+, V- = ±2.5V
Rg = 100
Rf = 10k
RL = INF
CL = 8.3pF
AV = +11
VOUT = 2VP-P
0
-40
-60
-80
-100
-0.5
0
0.5
1.0
1.5
2.0
2.5
0.5
0
140
160
180
-0.5
200
-0.5
-1.0
-1.5
3.0
3.5 4.0
4.5
5.0
-2.0
-0.5
5.5
0
0.5
1.0 1.5 2.0 2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCM (V)
VCM (V)
FIGURE 21. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT
VOLTAGE
FIGURE 22. INPUT OFFSET CURRENT vs COMMON-MODE INPUT
VOLTAGE
60
200
VCM = VDD/2
AV = -1
50
SUPPLY CURRENT (µA)
150
100
50
VDD = 5V
0
VDD = 2.5V
-50
-100
40
30
20
10
-150
-200
120
V+, V- = ±2.5V
Rg = 100
Rf = 10k
RL = INF
CL = 8.3pF
AV = +11
VOUT = 2VP-P
40
-20
100
TIME (µs)
100
20
80
FIGURE 20. ENABLE TO OUTPUT RESPONSE
FIGURE 19. SMALL SIGNAL STEP RESPONSE
INPUT OFFSET VOLTAGE (µV)
0.5
VOUT = 2VP-P
0
0
OUTPUT (V)
SMALL SIGNAL (mV)
VOUT
0
1
2
3
4
OUTPUT VOLTAGE (V)
FIGURE 23. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
FN7436 Rev 9.00
January 6, 2015
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
FIGURE 24. SUPPLY CURRENT vs SUPPLY VOLTAGE
Page 8 of 16
5.5
EL8176
Typical Performance Curves
(Continued)
75
7
DISABLED SUPPLY CURRENT (µA)
n = 12
SUPPLY CURRENT (µA)
70
65
MAX
60
MIN
55
MEDIAN
50
45
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
MAX
6
n = 12
5
4
MEDIAN
3
2
MIN
1
0
-40
120
0
20
60
80
100
120
FIGURE 26. DISABLED SUPPLY CURRENT vs TEMPERATURE
VS = ±2.5V RL= INF
3.0
2.5
n = 12
n = 12
2.5
2.0
2.0
CURRENT (nA)
1.5
MAX
1.0
0.5
MEDIAN
1.5
MAX
1.0
MEDIAN
0.5
0
0
MIN
MIN
-0.5
-40
-20
0
20
40
60
80
100
-0.5
-40
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 28. IBIAS (+) vs TEMPERATURE VS = ±1.2V
FIGURE 27. IBIAS (+) vs TEMPERATURE VS = ±2.5V
2.5
3.0
n = 12
1.5
n = 12
2.5
2.0
2.0
MAX
CURRENT (nA)
CURRENT (nA)
40
TEMPERATURE (°C)
FIGURE 25. SUPPLY CURRENT vs TEMPERATURE VS = ±2.5V
ENABLED. RL = INF
CURRENT (nA)
-20
1.0
MEDIAN
0.5
MAX
1.5
1.0
MEDIAN
0.5
0
0
MIN
-0.5
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 29. IBIAS (-) vs TEMPERATURE VS = ±2.5V
FN7436 Rev 9.00
January 6, 2015
120
MIN
-0.5
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 30. IBIAS (-) vs TEMPERATURE VS = ±1.2V
Page 9 of 16
EL8176
Typical Performance Curves
(Continued)
2.5
2.5
n = 12
n = 12
2.0
1.5
CURRENT (nA)
CURRENT (nA)
2.0
MAX
1.0
0.5
MEDIAN
1.5
MAX
1.0
0.5
MEDIAN
0
0
MIN
MIN
-0.5
-40
-20
0
20
40
60
80
100
-0.5
-40
120
-20
0
20
TEMPERATURE (°C)
200
SO PACKAGE
n = 12
80
100
120
SO PACKAGE
n = 12
150
150
100
MAX
50
VOS (µV)
VOS (µV)
60
FIGURE 32. INPUT OFFSET CURRENT vs TEMPERATURE
VS = ±1.2V
FIGURE 31. INPUT OFFSET CURRENT vs TEMPERATURE
VS = ±2.5V
200
40
TEMPERATURE (°C)
MEDIAN
MIN
0
MAX
100
MEDIAN
50
0
MIN
-50
-40
-20
0
20
40
60
80
100
-50
-40
120
-20
0
20
400
200
SOT-23 PACKAGE
80
100
120
n = 12
SOT-23 PACKAGE
150
300
MAX
MAX
100
VOS (µV)
200
VOS (µV)
60
FIGURE 34. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±1.2V
FIGURE 33. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±2.5V
n = 12
40
TEMPERATURE (°C)
TEMPERATURE (°C)
100
MEDIAN
0
50
0
MEDIAN
-50
-100
-100
-200
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 35. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±2.5V
FN7436 Rev 9.00
January 6, 2015
MIN
-150
MIN
120
-200
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 36. INPUT OFFSET VOLTAGE vs TEMPERATURE
VS = ±1.2V
Page 10 of 16
EL8176
Typical Performance Curves
(Continued)
140
125
n = 12
120
130
MAX
MAX
125
PSRR (dB)
115
CMRR (dB)
n = 12
135
110
105
120
115
MEDIAN
110
MEDIAN
105
100
95
-40
MIN
-20
0
20
40
100
60
80
100
MIN
95
-40
120
-20
0
TEMPERATURE (°C)
240
VOUT (mV)
VOUT (V)
MIN
4.85
n = 12
160
140
100
-20
0
20
40
60
80
100
80
-40
120
-20
0
TEMPERATURE (°C)
60
80
100
120
5.5
n = 12
MAX
5.0
4.9978
MEDIAN
4.5
4.9974
VOUT (mV)
VOUT (V)
40
FIGURE 40. NEGATIVE VOUT vs TEMPERATURE RL = 1k
VS = ±2.5V
n = 12
4.9980
4.9972
4.9970
MAX
4.0
3.5
MIN
4.9968
4.9966
MEDIAN
MIN
3.0
4.9964
4.9962
-40
20
TEMPERATURE (°C)
FIGURE 39. POSITIVE VOUT vs TEMPERATURE RL = 1k
VS = ±2.5V
4.9976
MEDIAN
MAX
180
MIN
4.83
4.9982
120
120
4.84
4.82
-40
100
200
MEDIAN
4.87
4.86
80
220
MAX
4.89
4.88
60
FIGURE 38. PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V
n = 12
4.90
40
TEMPERATURE (°C)
FIGURE 37. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
4.91
20
-20
0
20
40
60
80
TEMPERATURE (°C)
100
FIGURE 41. POSITIVE VOUT vs TEMPERATURE RL = 100k
VS = ±2.5V
FN7436 Rev 9.00
January 6, 2015
120
2.5
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 42. NEGATIVE VOUT vs TEMPERATURE RL = 100k
VS = ±2.5V
Page 11 of 16
EL8176
Typical Performance Curves
(Continued)
0.23
0.17
n = 12
n = 12
0.16
0.19
0.17
MEDIAN
0.15
0.13
0.14
MEDIAN
0.13
MIN
0.12
MIN
0.11
0.09
-40
MAX
0.15
MAX
CURRENT (pA)
SLEW RATE (V/µs)
0.21
0.11
-20
0
20
40
60
80
100
0.10
-40
120
-20
0
TEMPERATURE (°C)
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 43. ±SLEW RATE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V, AV = 2
900
FIGURE 44. ±SLEW RATE vs TEMPERATURE VS = ±2.5V
INPUT = ±0.75V, AV = 2
n = 12
800
MAX
AVOL (V/mV)
700
600
MEDIAN
500
MIN
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 45. AVOL, RL = 100k, VS ±2.5V, VO = ±2V
Applications Information
Introduction
The EL8176 is a rail-to-rail input and output micro-power
precision single supply operational amplifier with an enable
feature. The device achieves rail-to-rail input and output
operation and eliminates the concerns introduced by a
conventional rail-to-rail I/O operational amplifier as discussed
below.
Rail-to-Rail Input
the other causing drastic changes in input offset voltage and an
undesired change in magnitude and polarity of input offset
current.
The EL8176 achieves input rail-to-rail without sacrificing
important precision specifications and without degrading
distortion performance. The EL8176's input offset voltage
exhibits a smooth behavior throughout the entire common-mode
input range. The input bias current versus the common-mode
voltage range for the EL8176 gives us an undistorted behavior
from typically 10mV above the negative rail all the way up to the
positive rail.
The input common-mode voltage range of the EL8176 goes from
negative supply to positive supply without introducing offset errors
or degrading performance associated with a conventional
rail-to-rail input operational amplifier. Many rail-to-rail input stages
use two differential input pairs, a long-tail PNP (or PFET) and an
NPN (or NFET). Severe penalties have to be paid for this circuit
topology. As the input signal moves from one supply rail to
another, the operational amplifier switches from one input pair to
FN7436 Rev 9.00
January 6, 2015
Page 12 of 16
EL8176
Input Bias Current Compensation
The input bias currents as low as 500pA are achieved while
maintaining an excellent bandwidth for a micro-power
operational amplifier. Inside the EL8176 is an input bias
canceling circuit. The input stage transistors are still biased with
an adequate current for speed but the canceling circuit sinks
most of the base current, leaving a small fraction as input bias
current. The input bias current compensation/cancellation is
stable from -40°C to +125°C and operates from typically 10mV
to the positive supply rail.
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output
swing. The NMOS sinks current to swing the output in the negative
direction. The PMOS sources current to swing the output in the
positive direction. The EL8176 with a 100kΩ load will swing to within
3mV of the supply rails.
FIGURE 47.
Typical Applications
R4
Enable/Disable Feature
100kΩ
The EL8176 offers an EN pin. The active low EN pin disables the
device when pulled up to at least 2.0V. When disabled, the output
is in a high impedance state and the part consumes typically
3µA. When disabled, the high impedance output allows multiple
parts to be MUXed together. When configured as a MUX, the
outputs are tied together in parallel and a channel can be
selected by pulling the EN pin to 0.8V or lower. The EN pin has an
internal pull-down. If left open or floating, the EN pin will
internally be pulled low, enabling the part by default.
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage of the EL8176, care should be
taken in the circuit board layout. The PC board surface must
remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board will
reduce surface moisture and provide a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around
the amplifier inputs will further reduce leakage currents.
Figure 46 shows how the guard ring should be configured and
Figure 47 shows the top view of how a surface mount layout can
be arranged. The guard ring does not need to be a specific width,
but it should form a continuous loop around both inputs. By
setting the guard ring voltage equal to the voltage at the
non-inverting input, parasitic capacitance is minimized as well.
For further reduction of leakage currents, components can be
mounted to the PC board using Teflon standoff insulators.
3
10kΩ
R2
10kΩ
k TYPE
THERMOCOUPLE
V+
+
EL8176
V-
410µV/°C
+
5V
R1
100kΩ
FIGURE 48. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature-sensing
device because of their low cost, interchangeability and ability to
measure a wide range of temperatures. The EL8176 is used to
convert the differential thermocouple voltage into single-ended
signal with 10x gain. The EL8176's rail-to-rail input characteristic
allows the thermocouple to be biased at ground and the
converter to run from a single 5V supply.
V+
HIGH IMPEDANCE INPUT
IN
R3
6
EL8176
1
4
2
5
FIGURE 46.
FN7436 Rev 9.00
January 6, 2015
Page 13 of 16
EL8176
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
January 6, 2015
FN7436.9
CHANGE
- Updated entire datasheet to Intersil new standard.
- Removed WLCSP throughout the document.
- Ordering information table on page 2: Added MSL note.
- Added revision history and about Intersil verbiage
- Updated 8 Ld SO POD from “MDP0027” to “M8.15E”.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2004-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7436 Rev 9.00
January 6, 2015
Page 14 of 16
EL8176
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN7436 Rev 9.00
January 6, 2015
Page 15 of 16
EL8176
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.95
D
0.08-0.20
A
5
6
4
PIN 1
INDEX AREA
2.80
3
1.60
3
0.15 C D
2x
1
(0.60)
3
2
0.20 C
2x
0.40 ±0.05
B
5
SEE DETAIL X
3
0.20 M C A-B
D
TOP VIEW
2.90
5
END VIEW
10° TYP
(2 PLCS)
0.15 C A-B
2x
H
1.14 ±0.15
C
SIDE VIEW
0.10 C
0.05-0.15
1.45 MAX
SEATING PLANE
DETAIL "X"
(0.25) GAUGE
PLANE
0.45±0.1
4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
Dimension is exclusive of mold flash, protrusions or gate burrs.
4.
Foot length is measured at reference to guage plane.
5.
This dimension is measured at Datum “H”.
6.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN7436 Rev 9.00
January 6, 2015
Page 16 of 16
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