H7N1002LD-E

H7N1002LD, H7N1002LS, H7N1002LM Silicon N Channel MOS FET High Speed Power Switching REJ03G1131-0700 (Previous: ADE-208-1573E) Rev.7.00 Apr 07, 2006 Features • Low on-resistance RDS (on) = 8 mΩ typ. • Low drive current • Available for 4.5 V gate drive Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) 4 4 1. Gate 2. Drain 3. Source 4. Drain RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) 1 2 1 3 2 3 H7N1002LD H7N1002LS RENESAS Package code: PRSS0004AE-C (Package name: LDPAK (S)-(2) ) 4 G D 1 2 3 S H7N1002LM Rev.7.00 Apr 07, 2006 page 1 of 8 H7N1002LD, H7N1002LS, H7N1002LM Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Symbol VDSS VGSS ID ID (pulse) IDR Note 1 Value 100 ±20 75 300 75 50 166 100 150 –55 to +150 Unit V V A A A A mJ W °C °C IAP Note 3 EAR Pch Tch Note 2 Note 3 Tstg Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note: 4. Pulse test Symbol V (BR) DSS V (BR) GSS IGSS IDSS VGS (off) RDS (on) |yfs| Ciss Coss Crss Qg Qgs Qgd td (on) tr td (off) tf VDF trr Min 100 ±20 — — 1.0 — — 57 — — — — — — — — — — — — Typ — — — — — 8 10 95 9700 740 330 155 35 33 43 245 130 25 0.93 70 Max — — ±10 10 2.5 10 15 — — — — — — — — — — — — — Unit V V µA µA V mΩ mΩ S pF pF pF nC nC nC ns ns ns ns V ns Test Conditions ID = 10 mA, VGS = 0 IG = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 100 V, VGS = 0 ID = 1 mA, VDS = 10 V Note 4 ID = 37.5 A, VGS = 10 V ID = 37.5 A, VGS = 4.5 V Note 4 ID = 37.5 A, VDS = 10 V VDS = 10 V VGS = 0 f = 1 MHz VDD = 50 V VGS = 10 V ID = 75 A VGS = 10 V, ID = 37.5 A RL = 0.8 Ω Rg = 4.7 Ω IF = 75 A, VGS = 0 IF = 75 A, VGS = 0 diF/dt = 100 A/µs Note 4 Note 4 Rev.7.00 Apr 07, 2006 page 2 of 8 H7N1002LD, H7N1002LS, H7N1002LM Main Characteristics Power vs. Temperature Derating 200 1000 300 1 1 1 0 0 µs 0 m µs s Maximum Safe Operation Area Pch (W) ID (A) Drain Current 150 100 30 10 3 DC Operation (Tc = 25°C) Channel Dissipation 100 50 0 0 50 100 150 200 PW = 10 ms 1 Operation in (1shot) 0.3 this area is limited by RDS(on) 0.1 Ta = 25°C 0.03 0.1 0.3 1 3 10 30 100 300 Case Temperature Tc (°C) Drain to Source Voltage VDS (V) Typical Output Characteristics 50 10 V 4V 50 3.6 V Typical Transfer Characteristics VDS = 10 V Pulse Test ID (A) ID (A) Drain Current 40 Pulse Test 40 30 30 3.4 V Drain Current 20 20 Tc = 75°C 25°C 10 VGS = 3 V 10 –25°C 0 0 0 2 4 6 8 10 0 1 2 3 4 5 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Saturation Voltage VDS(on) (V) 1.0 Pulse Test 0.8 Static Drain to Source on State Resistance vs. Drain Current 50 Pulse Test 20 VGS = 4.5 V 10 5 10 V 0.6 ID = 50 A 0.4 2 1 0.5 2 0.2 20 A 10 A 0 5 10 15 20 0 5 10 20 50 100 200 Gate to Source Voltage VGS (V) Drain Current ID (A) Rev.7.00 Apr 07, 2006 page 3 of 8 H7N1002LD, H7N1002LS, H7N1002LM Static Drain to Source on State Resistance vs. Temperature Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Drain to Source on State Resistance RDS(on) (mΩ) 40 Pulse Test 32 50 A ID = 10 A, 20 A 16 VGS = 4.5 V 50 A 8 10 V 0 –40 0 40 10 A, 20 A 200 100 Tc = –25°C 10 25°C 1 75°C 0.1 0.02 0.01 24 VDS = 10 V Pulse Test 0.1 1 10 100 80 120 160 Case Temperature Tc (°C) Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 20000 10000 Ciss Body to Drain Diode Reverse Recovery Time Reverse Recovery Time trr (ns) 100 50 Capacitance C (pF) 5000 2000 1000 500 200 100 50 20 0 VGS = 0 f = 1 MHz 10 20 30 40 Coss 20 di / dt = 100 A / µs VGS = 0, Ta = 25°C 10 0.1 0.3 1 3 10 30 100 Crss 50 Reverse Drain Current IDR (A) Drain to Source Voltage VDS (V) Dynamic Input Characteristics Switching Characteristics VDS (V) ID = 75 A 160 VGS 16 VDD = 25 V 50 V 80 V VGS (V) 200 20 1000 300 100 td(on) 30 10 3 1 0.1 VGS = 10 V, VDD = 30 V PW = 5 µs, duty ≤ 1 % Rg = 4.7 Ω 0.3 1 3 10 30 100 tf td(off) tr Drain to Source Voltage 120 VDS 80 12 8 40 0 0 80 VDD = 80 V 50 V 25 V 160 240 320 4 0 400 Gate to Source Voltage Switching Time t (ns) Gate Charge Qg (nc) Drain Current ID (A) Rev.7.00 Apr 07, 2006 page 4 of 8 H7N1002LD, H7N1002LS, H7N1002LM Reverse Drain Current vs. Source to Drain Voltage Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) (A) 100 200 IAP = 50 A VDD = 25 V duty < 0.1 % Rg ≥ 50 Ω IDR 80 10 V 160 Reverse Drain Current 60 120 40 5V 20 VGS = 0, –5 V 80 40 0 0 0.4 0.8 1.2 Pulse Test 1.6 2.0 0 25 50 75 100 125 150 Source to Drain Voltage VSD (V) Channel Temperature Tch (°C) Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 θch – c (t) = γ s (t) • θch – c θch – c = 1.25°C/W, Tc = 25°C PDM uls e 0.05 0.03 0.02 D= PW T PW T 0.0 1 tp ho 1s 0.01 10 µ 100 µ 1m 10 m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit Avalanche Waveform 1 • L • IAP2 • 2 VDSS VDSS – VDD V(BR)DSS IAP VDD ID VDS VDS Monitor L IAP Monitor EAR = Rg D.U.T Vin 15 V 50 Ω VDD 0 Rev.7.00 Apr 07, 2006 page 5 of 8 H7N1002LD, H7N1002LS, H7N1002LM Switching Time Test Circuit Waveform Vin Monitor D.U.T. Rg RL Vout Monitor Vin Vout 10% 10% 90% 10% Vin 10 V VDS = 30 V td(on) 90% tr 90% td(off) tf Rev.7.00 Apr 07, 2006 page 6 of 8 H7N1002LD, H7N1002LS, H7N1002LM Package Dimensions Package Name LDPAK(L) JEITA Package Code  RENESAS Code PRSS0004AE-A Previous Code LDPAK(L) / LDPAK(L)V MASS[Typ.] 1.40g Unit: mm (1.4) 4.44 ± 0.2 10.2 ± 0.3 1.3 ± 0.15 11.3 ± 0.5 0.3 10.0 + 0.5 – 8.6 ± 0.3 1.3 ± 0.2 1.37 ± 0.2 0.76 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 11.0 ± 0.5 0.2 0.86 + 0.1 – 2.49 ± 0.2 0.4 ± 0.1 Package Name LDPAK(S)-(1) JEITA Package Code SC-83 RENESAS Code PRSS0004AE-B Previous Code LDPAK(S)-(1) / LDPAK(S)-(1)V MASS[Typ.] 1.30g Unit: mm 4.44 ± 0.2 10.2 ± 0.3 (1.4) 8.6 ± 0.3 + 0.3 – 0.5 10.0 (1.5) (1.5) 2.49 ± 0.2 0.2 0.1 + 0.1 – 7.8 7.0 2.2 1.37 ± 0.2 1.3 ± 0.2 2.54 ± 0.5 0.3 3.0 + 0.5 – 0.2 0.86 + 0.1 – 0.4 ± 0.1 2.54 ± 0.5 Rev.7.00 Apr 07, 2006 page 7 of 8 1.7 1.3 ± 0.15 7.8 6.6 H7N1002LD, H7N1002LS, H7N1002LM Package Name LDPAK(S)-(2) JEITA Package Code  RENESAS Code PRSS0004AE-C Previous Code LDPAK(S)-(2) / LDPAK(S)-(2)V MASS[Typ.] 1.35g Unit: mm 4.44 ± 0.2 10.2 ± 0.3 (1.4) 8.6 ± 0.3 + 0.3 – 0.5 2.49 ± 0.2 10.0 (1.5) (2.3) 0.2 0.1 + 0.1 – 7.8 7.0 2.2 1.37 ± 0.2 1.3 ± 0.2 2.54 ± 0.5 0.4 ± 0.1 0.3 5.0 + 0.5 – 0.2 0.86 + 0.1 – 2.54 ± 0.5 Ordering Information Part Name H7N1002LD-E H7N1002LSTL-E 500 pcs 1000 pcs Quantity Shipping Container Box (Conductive Sack) Taping H7N1002LMTL-E 1000 pcs Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.7.00 Apr 07, 2006 page 8 of 8 1.7 1.3 ± 0.15 7.8 6.6 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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