H8S2110B

REJ09B0299-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2110B Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2110B HD64F2110BV Rev. 2.00 Revision Date: Mar 21, 2006 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 2.00 Mar 21, 2006 page ii of xxxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. Rev. 2.00 Mar 21, 2006 page iii of xxxviii Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7. • • Description of Functional Modules CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. List of Registers 9. Electrical Characteristics 10. Appendix 11. Index Rev. 2.00 Mar 21, 2006 page iv of xxxviii Preface The H8S/2110B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technology original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. This LSI is equipped with ROM, RAM, a 14-bit PWM timer (PWMX), a 16-bit free-running timer (FRT), an 8-bit timer (TMR), a watchdog timer (WDT), a serial communication interface (SCI), a 2 keyboard buffer controller, a host interface LPC interface (LPC), an I C bus interface (IIC), and I/O ports as on-chip peripheral modules, required for system configuration. A flash memory (F-ZTAT *) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2110B in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2110B to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. TM Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. Rev. 2.00 Mar 21, 2006 page v of xxxviii • In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to a low-active signal: xxxx Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2110B manuals: Documenet Title H8S/2110B Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Documenet No. This manual REJ09B0139 User's manuals for development tools: Documenet Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Documenet No. REJ10B0058 ADE-702-282 ADE-702-231 ADE-702-201 Rev. 2.00 Mar 21, 2006 page vi of xxxviii Main Revisions for This Edition Item All Page  Revisions (See Manual for Details) • • 1.2 Block Diagram Figure 1.1 Internal Block Diagram of H8S/2110B 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement of H8S/2110B 2.4.3 Extended Control Register (EXR) 3.2.3 Serial Timer Control Register (STCR) 4.7 Usage Note Figure 4.7 Operation When SP Value Is Odd 5.3.7 Keyboard Matrix 72 Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB) 5.5 Interrupt Exception 76 Handling Vector Table Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities 22 R/W in bits 6 to 3 amended (Before) R → (After)  53 IICS description in bit 7 amended (Before) ... SLC and SDA. → (After) ... SCL and SDA. 62 Figure 4.7 amended (Before) SP set to H'FFFEFF → (After) SP set to H'FFEFFF Description amended (Before) If any of KMIMR15 to KMIMR8 or WUEMRB7 to WUEMRB0 is cleared to 0, ... → (After) If any of KMIMR15 to KMIMR8 or WUEMR7 to WUEMR0 is cleared to 0, ... 3 2 Nortification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Product naming convention amended (Before) H8S/2110B Series → (After) H8S/2110B Group Figure 1.1 amended P75* * 12 P74* * 12 P73* * 12 P72* * 12 P71* * 12 P70* * 12 Figure 1.2 amended (Before) P51/ExRDxD1* → (After) P51/ExRxD1* 1 1 Table 5.3 amended IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) Rev. 2.00 Mar 21, 2006 page vii of xxxviii Item Page Revisions (See Manual for Details) Figure 5.6 amended (Before) IFBFI3 → (After) IBFI3 5.6.2 Interrupt Control 81 Mode 1 Figure 5.6 Flowchart of Procedure Up to 6.1 Bus Control Register (BCR) 7.1 Overview 89 91 Initial value in bit 2 amended (Before) 0 → (After) 1 Description amended (Before) Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR and DR, to control ... → (After) Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR, to control ... 7.4.4 Pin Functions 100 • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 Note * amended Note: * The combination of bits not described ... m = 3 to 1: LPC input/output pins (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0) ... 7.9.3 Pin Functions 116 • P86/IRQ5/SCK1/SCL1 1 Table amended IRQ5 input pin* 8.1 Features Figure 8.1 PWM (D/A) Block Diagram 131 Figure 8.1 amended Internal clock φ φ/2 Select clock Clock Base cycle compare match A PWX0 PWX1 Fine–adjustment pulse addition A Comparator A Comparator B Base cycle compare match B Fine–adjustment pulse addition B Control logic Rev. 2.00 Mar 21, 2006 page viii of xxxviii Item 8.5 Operation Table 8.5 Position of Pulse to Be Added to Basic Pulse with 12-Bit Conversion Accuracy (CFS = 1) Table 8.6 Position of 145 Pulse to Be Added to Basic Pulse with 10-Bit Conversion Accuracy (CFS = 1) 144 Page 0 1 Basic Pulse No. 2 3 4 5 6 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 Basic Pulse No. 23456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Table 8.6 amended Table 8.5 amended 0 0 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Lower 6 bits 0000 1000 0000 1000 00 0 16 0 32 0 48 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Revisions (See Manual for Details) Lower 6 bits 0000 0010 0100 0110 1000 1010 1100 1110 0000 0010 0100 0110 1000 1010 1100 1110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYesYes Yes Yes Yes Yes Yes YesYes Yes YesYesYes Yes Yes Yes Yes YesYes Yes YesYesYes Yes YesYes Yes Yes YesYes Yes YesYesYes Yes YesYes YesYes Yes YesYes Yes Yes YesYes YesYesYesYes YesYes Yes Yes YesYes YesYesYesYes YesYes Yes YesYesYes Yes YesYes Yes YesYesYes YesYes Yes YesYes YesYesYesYes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYes Yes Yes Yes Yes Yes YesYes Yes YesYesYesYes Yes YesYesYesYes Yes Yes Rev. 2.00 Mar 21, 2006 page ix of xxxviii Item Page Revisions (See Manual for Details) Initial value in bit 0 amended (Before) 0 → (After) 1 ICFB description in bit 6 amended ... When BUFEB =1, ICRB indicates that the old ICRB value ... TCSR_Y Initial value in bit 4 amended (Before) 0 → (After) 1 Bit name in bits 6 to 0 amended (Before) (Blanc) → (After)  Table 10.3 amended TCNT_X Figure 10.11 amended TCNT_X 9.3.6 Timer Interrupt 153 Enable Register (TIER) 9.3.7 Timer 154 Control/Status Register (TCSR) 10.3.5 Timer 188 Control/Status Register (TCSR) 10.3.10 Timer 190 Connection Register S (TCONRS) Table 10.3 Registers 191 Accessible by TMR_X/TMR_Y 10.7.3 Input Capture 199 Operation Figure 10.11 Timing of Input Capture Operation 13.3.5 I C Bus Control Register (ICCR) 2 280 MST and TRS description in bits 5 and 4 amended .... In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition ... 2 283, 284 Table 13.5 Flags and 286 Transfer States Slave Mode) R/W in bit 1 amended R/(W)* Table 13.5 amended MST 0 0 0 0 TRS 1 1 1 1 BBSY ESTP 1 1 1 1 0 0 0 0 STOP IRTR 0 0 0 0 — — — AASX AL — — — 0↓ — 0 0 AAS 0↓ — 0 0 ADZ 0 0 0 0 ACKB ICDRF ICDRE State 0 0 0 0 — — — — 0↓ 1 0↓ 1↑ ICDR write with the above state Transmission nd e with ICDRE = 1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state 1↑/0*2 — 13.4.4 Master Receive Operation Figure 13.11 Example of Operation Timing master Receive Mode (MLS = WAIT = 0, HNDS = 1) 306 Figure 13.11 amended [2] ICDR read (Dummy read) Rev. 2.00 Mar 21, 2006 page x of xxxviii Item 13.4.4 Master Receive Operation Figure 13.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) Page 308 Revisions (See Manual for Details) Figure 13.14 amended Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Read IRIC flag in ICCR No IRIC = 1? Yes Set ACKB = 1 in ICSR [7] Set acknowledge data for 310 13.4.5 Slave Receive 313 Operation 317 Description amended 15. Clear the WAIT bit in ICMR to cancel the wait mode. ... Description amended 3. ... The master device ... and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. Description amended 3. ... The master device ... and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0. 13.4.6 Slave Transmit 320 Operation 13.6 Usage Notes 332 Description amended 2. ... If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, ... 8. Notes on start condition issuance for retransmission Note amended Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 11 in ICXR. 333, 334 Figure 13.34 ICDR Read and ICCR Access in Slave Transmit Mode 335 10. Notes on WAIT function Description added Figure 13.34 amended (Before) R/W → (After) R/W 336 13. Notes on TRS bit setting in slave mode Note amended Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 11 in ICXR. 336, 337 14. Notes on Arbitration Lost in master mode Description added Rev. 2.00 Mar 21, 2006 page xi of xxxviii Item 14.4.1 Receive Operation Figure 14.3 Sample Receive Processing Flowchart 14.4.2 transmit Operation Figure 14.5 (1) Sample Transmit Processing Flowchart Page 345 Revisions (See Manual for Details) Figure 14.3 amended [1] Set the KBIOE bit to 1 in KBCRH. 347 Figure 14.5 (1) amended [1] Set the KBIOE bit to 1 in KBCRH. 15.3.1 Host Interface 365 Control Registers 0 and 1 (HICR0, HICR1) 15.3.7 Status 378 Registers 1 to 3 (STR1 to STR3) 15.4.4 Host Interface 397 Shutdown Function (LPCPD) Table 15.5 Scope of Host Interface Pin Shutdown • HICR1 R/W in slave in bit 7 amended (Before) R/W → (After) R • STR3 (TWRE = 1 or SELSTR3 = 0) Bit name in bit 3 amended (Before) C/D3 → (After) C/D3 I/O description in CLKRUN amended (Before) I/O → (After) Input Rev. 2.00 Mar 21, 2006 page xii of xxxviii Item 17.8.1 Program/ProgramVerify Figure 17.9 Program/ProgramVerify Flowchart Page 426 Revisions (See Manual for Details) Figure 17.9 amended Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (x) µs Store 128-byte program data in program data area and reprogram data area *6 Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait (γ) µs Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR2 Wait (β) µs Disable WDT *6 *6 *5 *6 *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *4 n=1 m=0 Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call Apply write pulse z1 µs or z2 µs Set PV bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address See Note 7 for pulse width *6 *6 Wait (ε) µs Read verify data Increment address *6 n←n+1 End Sub *2 NG m=1 NG Note 7: Write Pulse Width Number of Writes n Write Time (z) µs*6 Write data = verify data? 1 2 3 4 5 6 7 8 9 10 11 12 13 z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 OK 6≥n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? NG 998 999 1000 z2 z2 z2 OK Clear PV bit in FLMCR1 Wait (η) µs 6 ≥ n? NG *6 Note: Use a z3 µs write pulse for additional programming. RAM Program data storage area (128 bytes) OK Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Apply write pulse (Additional programming) *3 µs n ≥ (N)? Reprogram data storage area (128 bytes) m=0? OK Clear SWE bit in FLMCR1 Wait (θ) µs End of programming NG NG Additional-programming data storage area (128 bytes) OK Clear SWE bit in FLMCR1 *6 Wait (θ) µs Programming failure *6 18.5 Subclock Input Circuit 19.1.1 Standby Control Register (SBYCR) 19.1.1 Standby Control Register (SBYCR) Table 19.1 Operating Frequency and Wait Time 20.1 Register Addresses (Address Order) 438, 439 443 Description of "When Subclock Is Not Needed" and " Note on Subclock Usage" added SCK2 to SCK0 description in bits 2 to 0 amended When …, SCK2 to SCK0 must be cleared to B'00. 443 Table amended STS2 0 STS1 0 STS0 0 Wait Time 8192 states 10 MHz 8 MHz 0.8 1.0 6 MHz 1.3 4 MHz 2.0 2 MHz 4.1 Unit ms 460 Address in P7ODA amended (Before) H'FE02 → (After) H'FE01 Rev. 2.00 Mar 21, 2006 page xiii of xxxviii Item 21.2.3 On-Chip Peripheral Module Timing Figure 21.19 A/D Converter External Trigger Input Timing Appendix C Package Dimensions Figure C.1 Package Dimensions (FP-100B) Figure C.2 Package Dimensions (TFP-100B) Page 506 Revisions (See Manual for Details) Figure 21.19 replaced 513 Figure replaced 514 Figure replaced Rev. 2.00 Mar 21, 2006 page xiv of xxxviii Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 Features ............................................................................................................................. Block Diagram .................................................................................................................. Pin Arrangement and Functions........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 1 1 2 3 3 4 9 Section 2 CPU ...................................................................................................................... 13 2.1 Features ............................................................................................................................. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 General Registers ................................................................................................. 2.4.2 Program Counter (PC) ......................................................................................... 2.4.3 Extended Control Register (EXR) ....................................................................... 2.4.4 Condition-Code Register (CCR) .......................................................................... 2.4.5 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Instructions Classified by Function...................................................................... 2.6.2 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Register Direct—Rn............................................................................................. 2.7.2 Register Indirect—@ERn .................................................................................... 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn . 2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 ................................................................. 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 13 14 15 15 16 16 17 19 20 21 22 22 22 24 24 24 26 26 28 37 38 39 39 39 39 39 40 40 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 2.00 Mar 21, 2006 page xv of xxxviii 2.8 2.9 2.7.8 Memory Indirect—@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Notes ...................................................................................................................... 2.9.1 Note on TAS Instruction Usage ........................................................................... 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 2.9.3 Bit Manipulation Instructions .............................................................................. 2.9.4 EEPMOV Instruction........................................................................................... 41 42 44 46 46 46 46 48 Section 3 MCU Operating Modes .................................................................................. 49 3.1 3.2 MCU Operating Mode Selection ...................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Serial Timer Control Register (STCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 2 ................................................................................................................. 3.3.2 Mode 3 ................................................................................................................. Address Map in Each Operating Mode ............................................................................. 49 49 50 51 53 54 54 54 55 3.3 3.4 Section 4 Exception Handling ......................................................................................... 57 4.1 4.2 4.3 Exception Handling Types and Priority ............................................................................ Exception Sources and Exception Vector Table ............................................................... Reset.................................................................................................................................. 4.3.1 Reset Exception Handling.................................................................................... 4.3.2 Interrupts after Reset............................................................................................ 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled ........................................ Interrupt Exception Handling............................................................................................ Trap Instruction Exception Handling................................................................................ Stack Status after Exception Handling.............................................................................. Usage Note........................................................................................................................ 57 58 59 59 60 60 60 60 61 62 4.4 4.5 4.6 4.7 Section 5 Interrupt Controller .......................................................................................... 63 5.1 5.2 5.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 5.3.2 Address Break Control Register (ABRKCR)....................................................... 5.3.3 Break Address Registers A to C (BARA to BARC) ............................................ 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 63 65 65 66 67 67 68 Rev. 2.00 Mar 21, 2006 page xvi of xxxviii 5.4 5.5 5.6 5.7 5.8 IRQ Enable Register (IER) .................................................................................. IRQ Status Register (ISR).................................................................................... Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... Interrupt Sources............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts................................................................................................. Interrupt Exception Handling Vector Table...................................................................... Interrupt Control Modes and Interrupt Operation ............................................................. 5.6.1 Interrupt Control Mode 0 ..................................................................................... 5.6.2 Interrupt Control Mode 1 ..................................................................................... 5.6.3 Interrupt Exception Handling Sequence .............................................................. 5.6.4 Interrupt Response Times .................................................................................... Address Break ................................................................................................................... 5.7.1 Features................................................................................................................ 5.7.2 Block Diagram ..................................................................................................... 5.7.3 Operation ............................................................................................................. 5.7.4 Usage Notes ......................................................................................................... Usage Notes ...................................................................................................................... 5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 5.8.2 Instructions that Disable Interrupts ...................................................................... 5.8.3 Interrupts during Execution of EEPMOV Instruction.......................................... 5.8.4 IRQ Status Register (ISR).................................................................................... 5.3.5 5.3.6 5.3.7 69 70 70 73 73 74 74 77 77 79 81 83 84 84 84 84 85 87 87 88 88 88 Section 6 Bus Controller (BSC) ...................................................................................... 89 6.1 Register Descriptions ........................................................................................................ 89 6.1.1 Bus Control Register (BCR) ................................................................................ 89 6.1.2 Wait State Control Register (WSCR) .................................................................. 90 Section 7 I/O Ports .............................................................................................................. 91 7.1 7.2 Overview........................................................................................................................... Port 1................................................................................................................................. 7.2.1 Port 1 Data Direction Register (P1DDR)............................................................. 7.2.2 Port 1 Data Register (P1DR)................................................................................ 7.2.3 Port 1 Pull-Up MOS Control Register (P1PCR) .................................................. 7.2.4 Pin Functions ....................................................................................................... 7.2.5 Port 1 Input Pull-Up MOS ................................................................................... Port 2................................................................................................................................. 7.3.1 Port 2 Data Direction Register (P2DDR)............................................................. 7.3.2 Port 2 Data Register (P2DR)................................................................................ 91 95 95 95 96 96 96 97 97 97 7.3 Rev. 2.00 Mar 21, 2006 page xvii of xxxviii 7.3.3 Port 2 Pull-Up MOS Control Register (P2PCR) .................................................. 7.3.4 Pin Functions ....................................................................................................... 7.3.5 Port 2 Input Pull-Up MOS ................................................................................... 7.4 Port 3................................................................................................................................. 7.4.1 Port 3 Data Direction Register (P3DDR)............................................................. 7.4.2 Port 3 Data Register (P3DR)................................................................................ 7.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) .................................................. 7.4.4 Pin Functions ....................................................................................................... 7.4.5 Port 3 Input Pull-Up MOS ................................................................................... 7.5 Port 4................................................................................................................................. 7.5.1 Port 4 Data Direction Register (P4DDR)............................................................. 7.5.2 Port 4 Data Register (P4DR)................................................................................ 7.5.3 Pin Functions ....................................................................................................... 7.6 Port 5................................................................................................................................. 7.6.1 Port 5 Data Direction Register (P5DDR)............................................................. 7.6.2 Port 5 Data Register (P5DR)................................................................................ 7.6.3 Pin Functions ....................................................................................................... 7.7 Port 6................................................................................................................................. 7.7.1 Port 6 Data Direction Register (P6DDR)............................................................. 7.7.2 Port 6 Data Register (P6DR)................................................................................ 7.7.3 Port 6 Pull-Up MOS Control Register (KMPCR)................................................ 7.7.4 System Control Register 2 (SYSCR2) ................................................................. 7.7.5 Pin Functions ....................................................................................................... 7.7.6 Port 6 Input Pull-Up MOS ................................................................................... 7.8 Port 7................................................................................................................................. 7.8.1 Port 7 Input Data Register (P7PIN) ..................................................................... 7.8.2 Port 7 Data Direction Register (P7DDR)............................................................. 7.8.3 Port 7 Output Data Register (P7ODR)................................................................. 7.8.4 Pin Functions ....................................................................................................... 7.9 Port 8................................................................................................................................. 7.9.1 Port 8 Data Direction Register (P8DDR)............................................................. 7.9.2 Port 8 Data Register (P8DR)................................................................................ 7.9.3 Pin Functions ....................................................................................................... 7.10 Port 9................................................................................................................................. 7.10.1 Port 9 Data Direction Register (P9DDR)............................................................. 7.10.2 Port 9 Data Register (P9DR)................................................................................ 7.10.3 Pin Functions ....................................................................................................... 7.11 Port A................................................................................................................................ 7.11.1 Port A Data Direction Register (PADDR) ........................................................... 7.11.2 Port A Output Data Register (PAODR) ............................................................... Rev. 2.00 Mar 21, 2006 page xviii of xxxviii 98 98 98 99 99 99 100 100 101 101 101 102 102 104 104 105 105 107 107 108 108 109 110 112 112 113 113 114 114 115 115 116 116 119 119 120 120 122 122 123 7.11.3 Port A Input Data Register (PAPIN).................................................................... 7.11.4 Pin Functions ....................................................................................................... 7.11.5 Port A Input Pull-Up MOS .................................................................................. 7.12 Port B ................................................................................................................................ 7.12.1 Port B Data Direction Register (PBDDR)............................................................ 7.12.2 Port B Output Data Register (PBODR) ............................................................... 7.12.3 Port B Input Data Register (PBPIN) .................................................................... 7.12.4 Pin Functions ....................................................................................................... 7.12.5 Port B Input Pull-Up MOS .................................................................................. 123 124 126 127 127 127 128 128 129 Section 8 14-Bit PWM Timer (PWMX) ....................................................................... 131 8.1 8.2 8.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 8.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL)...................................... 8.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) ................................. 8.3.3 PWM (D/A) Control Register (DACR) ............................................................... Bus Master Interface ......................................................................................................... Operation .......................................................................................................................... Usage Note........................................................................................................................ 8.6.1 Module Stop Mode Setting .................................................................................. 131 132 132 133 134 136 137 138 146 146 8.4 8.5 8.6 Section 9 16-Bit Free-Running Timer (FRT) .............................................................. 147 9.1 9.2 9.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 9.3.1 Free-Running Counter (FRC) .............................................................................. 9.3.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 9.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 9.3.5 Output Compare Register DM (OCRDM) ........................................................... 9.3.6 Timer Interrupt Enable Register (TIER) .............................................................. 9.3.7 Timer Control/Status Register (TCSR) ................................................................ 9.3.8 Timer Control Register (TCR) ............................................................................. 9.3.9 Timer Output Compare Control Register (TOCR) .............................................. Operation .......................................................................................................................... 9.4.1 Pulse Output......................................................................................................... Operation Timing.............................................................................................................. 9.5.1 FRC Increment Timing ........................................................................................ 9.5.2 Output Compare Output Timing .......................................................................... 147 149 149 150 150 150 151 151 152 153 156 157 159 159 159 159 160 9.4 9.5 Rev. 2.00 Mar 21, 2006 page xix of xxxviii 9.6 9.7 9.5.3 FRC Clear Timing................................................................................................ 9.5.4 Input Capture Input Timing ................................................................................. 9.5.5 Buffered Input Capture Input Timing .................................................................. 9.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 9.5.7 Timing of Output Compare Flag (OCF) setting................................................... 9.5.8 Timing of FRC Overflow Flag Setting ................................................................ 9.5.9 Automatic Addition Timing................................................................................. 9.5.10 Mask Signal Generation Timing .......................................................................... Interrupt Sources............................................................................................................... Usage Notes ...................................................................................................................... 9.7.1 Conflict between FRC Write and Clear ............................................................... 9.7.2 Conflict between FRC Write and Increment........................................................ 9.7.3 Conflict between OCR Write and Compare-Match ............................................. 9.7.4 Switching of Internal Clock and FRC Operation ................................................. 9.7.5 Module Stop Mode Setting .................................................................................. 161 161 162 163 164 164 165 165 166 167 167 168 169 170 172 Section 10 8-Bit Timer (TMR) ........................................................................................ 173 10.1 Features ............................................................................................................................. 10.2 Input/Output Pins .............................................................................................................. 10.3 Register Descriptions ........................................................................................................ 10.3.1 Timer Counter (TCNT)........................................................................................ 10.3.2 Time Constant Register A (TCORA)................................................................... 10.3.3 Time Constant Register B (TCORB) ................................................................... 10.3.4 Timer Control Register (TCR) ............................................................................. 10.3.5 Timer Control/Status Register (TCSR) ................................................................ 10.3.6 Time Constant Register (TCORC)....................................................................... 10.3.7 Input Capture Registers R and F (TICRR and TICRF)........................................ 10.3.8 Timer Input Select Register (TISR) ..................................................................... 10.3.9 Timer Connection Register I (TCONRI) ............................................................. 10.3.10 Timer Connection Register S (TCONRS)............................................................ 10.3.11 Timer XY Control Register (TCRXY) ................................................................ 10.4 Operation .......................................................................................................................... 10.4.1 Pulse Output......................................................................................................... 10.5 Operation Timing.............................................................................................................. 10.5.1 TCNT Count Timing............................................................................................ 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 10.5.3 Timing of Timer Output at Compare-Match........................................................ 10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 10.5.5 TCNT External Reset Timing .............................................................................. 10.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. Rev. 2.00 Mar 21, 2006 page xx of xxxviii 173 177 177 179 179 179 180 184 189 189 189 190 190 191 192 192 193 193 194 194 195 195 196 10.6 TMR_0 and TMR_1 Cascaded Connection ...................................................................... 10.6.1 16-Bit Count Mode .............................................................................................. 10.6.2 Compare-Match Count Mode .............................................................................. 10.7 TMR_Y and TMR_X Cascaded Connection .................................................................... 10.7.1 16-Bit Count Mode .............................................................................................. 10.7.2 Compare-Match Count Mode .............................................................................. 10.7.3 Input Capture Operation ...................................................................................... 10.8 Interrupt Sources............................................................................................................... 10.9 Usage Notes ...................................................................................................................... 10.9.1 Conflict between TCNT Write and Counter Clear............................................... 10.9.2 Conflict between TCNT Write and Count-Up ..................................................... 10.9.3 Conflict between TCOR Write and Compare-Match........................................... 10.9.4 Conflict between Compare-Matches A and B...................................................... 10.9.5 Switching of Internal Clocks and TCNT Operation............................................. 10.9.6 Mode Setting with Cascaded Connection ............................................................ 10.9.7 Module Stop Mode Setting .................................................................................. 197 197 197 198 198 198 199 201 201 201 202 203 203 204 206 206 Section 11 Watchdog Timer (WDT) .............................................................................. 207 11.1 Features ............................................................................................................................. 11.2 Input/Output Pins .............................................................................................................. 11.3 Register Descriptions ........................................................................................................ 11.3.1 Timer Counter (TCNT)........................................................................................ 11.3.2 Timer Control/Status Register (TCSR) ................................................................ 11.4 Operation .......................................................................................................................... 11.4.1 Watchdog Timer Mode ........................................................................................ 11.4.2 Interval Timer Mode ............................................................................................ 11.4.3 RESO Signal Output Timing ............................................................................... 11.5 Interrupt Sources............................................................................................................... 11.6 Usage Notes ...................................................................................................................... 11.6.1 Notes on Register Access..................................................................................... 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 11.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 11.6.5 System Reset by RESO Signal............................................................................. 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................ 207 209 209 209 210 214 214 216 217 217 218 218 219 219 219 220 220 Section 12 Serial Communication Interface (SCI) .................................................... 221 12.1 Features ............................................................................................................................. 221 12.2 Input/Output Pins .............................................................................................................. 223 Rev. 2.00 Mar 21, 2006 page xxi of xxxviii 12.3 Register Descriptions ........................................................................................................ 12.3.1 Receive Shift Register (RSR) .............................................................................. 12.3.2 Receive Data Register (RDR) .............................................................................. 12.3.3 Transmit Data Register (TDR)............................................................................. 12.3.4 Transmit Shift Register (TSR) ............................................................................. 12.3.5 Serial Mode Register (SMR)................................................................................ 12.3.6 Serial Control Register (SCR).............................................................................. 12.3.7 Serial Status Register (SSR) ................................................................................ 12.3.8 Serial Interface Mode Register (SCMR).............................................................. 12.3.9 Bit Rate Register (BRR) ...................................................................................... 12.3.10 Serial Pin Select Register (SPSR) ........................................................................ 12.4 Operation in Asynchronous Mode .................................................................................... 12.4.1 Data Transfer Format........................................................................................... 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 12.4.3 Clock.................................................................................................................... 12.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 12.4.5 Data Transmission (Asynchronous Mode)........................................................... 12.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 12.5 Multiprocessor Communication Function......................................................................... 12.5.1 Multiprocessor Serial Data Transmission ............................................................ 12.5.2 Multiprocessor Serial Data Reception ................................................................. 12.6 Operation in Clocked Synchronous Mode ........................................................................ 12.6.1 Clock.................................................................................................................... 12.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 12.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 12.7 Interrupt Sources............................................................................................................... 12.8 Usage Notes ...................................................................................................................... 12.8.1 Module Stop Mode Setting .................................................................................. 12.8.2 Break Detection and Processing .......................................................................... 12.8.3 Mark State and Break Detection .......................................................................... 12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 12.8.5 Relation between Writing to TDR and TDRE Flag ............................................. 12.8.6 SCI Operations during Mode Transitions ............................................................ 12.8.7 Switching from SCK Pins to Port Pins ................................................................ 223 223 224 224 224 225 227 229 231 232 237 237 238 239 240 241 242 244 248 250 251 254 254 255 256 258 260 262 263 263 263 263 263 263 264 267 Rev. 2.00 Mar 21, 2006 page xxii of xxxviii Section 13 I2C Bus Interface (IIC) .................................................................................. 269 13.1 Features ............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Descriptions ........................................................................................................ 2 13.3.1 I C Bus Data Register (ICDR) ............................................................................. 13.3.2 Slave Address Register (SAR) ............................................................................. 13.3.3 Second Slave Address Register (SARX) ............................................................. 2 13.3.4 I C Bus Mode Register (ICMR) ........................................................................... 2 13.3.5 I C Bus Control Register (ICCR) ......................................................................... 2 13.3.6 I C Bus Status Register (ICSR)............................................................................ 13.3.7 DDC Switch Register (DDCSWR) ...................................................................... 2 13.3.8 I C Bus Extended Control Register (ICXR)......................................................... 13.4 Operation .......................................................................................................................... 2 13.4.1 I C Bus Data Format ............................................................................................ 13.4.2 Initialization ......................................................................................................... 13.4.3 Master Transmit Operation .................................................................................. 13.4.4 Master Receive Operation.................................................................................... 13.4.5 Slave Receive Operation...................................................................................... 13.4.6 Slave Transmit Operation .................................................................................... 13.4.7 IRIC Setting Timing and SCL Control ................................................................ 13.4.8 Noise Canceler ..................................................................................................... 13.4.9 Initialization of Internal State .............................................................................. 13.5 Interrupt Sources............................................................................................................... 13.6 Usage Notes ...................................................................................................................... 13.6.1 Module Stop Mode Setting .................................................................................. 269 272 273 273 274 275 277 280 288 292 293 297 297 299 299 304 311 319 322 325 325 327 327 338 Section 14 Keyboard Buffer Controller ........................................................................ 339 14.1 Features ............................................................................................................................. 14.2 Input/Output Pins .............................................................................................................. 14.3 Register Descriptions ........................................................................................................ 14.3.1 Keyboard Control Register H (KBCRH) ............................................................. 14.3.2 Keyboard Control Register L (KBCRL) .............................................................. 14.3.3 Keyboard Data Buffer Register (KBBR) ............................................................. 14.4 Operation .......................................................................................................................... 14.4.1 Receive Operation................................................................................................ 14.4.2 Transmit Operation .............................................................................................. 14.4.3 Receive Abort ...................................................................................................... 14.4.4 KCLKI and KDI Read Timing............................................................................. 14.4.5 KCLKO and KDO Write Timing......................................................................... 339 340 341 341 343 344 345 345 346 349 351 352 Rev. 2.00 Mar 21, 2006 page xxiii of xxxviii 14.4.6 KBF Setting Timing and KCLK Control ............................................................. 14.4.7 Receive Timing.................................................................................................... 14.4.8 KCLK Fall Interrupt Operation............................................................................ 14.5 Usage Notes ...................................................................................................................... 14.5.1 KBIOE Setting and KCLK Falling Edge Detection............................................. 14.5.2 Module Stop Mode Setting .................................................................................. 353 354 355 356 356 356 357 357 359 360 361 368 371 372 373 373 374 381 389 390 390 391 393 396 400 402 403 403 403 405 405 405 Section 15 Host Interface LPC Interface (LPC) ......................................................... 15.1 Features ............................................................................................................................. 15.2 Input/Output Pins .............................................................................................................. 15.3 Register Descriptions ........................................................................................................ 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 15.3.3 LPC Channel 3 Address Register (LADR3) ........................................................ 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)................................................... 15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) .................................... 15.3.7 Status Registers 1 to 3 (STR1 to STR3)............................................................... 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 15.3.9 Host Interface Select Register (HISEL) ............................................................... 15.4 Operation .......................................................................................................................... 15.4.1 Host Interface Activation ..................................................................................... 15.4.2 LPC I/O Cycles .................................................................................................... 15.4.3 A20 Gate .............................................................................................................. 15.4.4 Host Interface Shutdown Function (LPCPD)....................................................... 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 15.4.6 Host Interface Clock Start Request (CLKRUN) .................................................. 15.5 Interrupt Sources............................................................................................................... 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12........................ 15.6 Usage Notes ...................................................................................................................... 15.6.1 Module Stop Mode Setting .................................................................................. 15.6.2 Notes on Using Host Interface ............................................................................. Section 16 RAM .................................................................................................................. 407 Section 17 ROM .................................................................................................................. 17.1 Features ............................................................................................................................. 17.2 Mode Transitions .............................................................................................................. 17.3 Block Configuration.......................................................................................................... Rev. 2.00 Mar 21, 2006 page xxiv of xxxviii 409 409 411 414 17.4 Input/Output Pins .............................................................................................................. 17.5 Register Descriptions ........................................................................................................ 17.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 17.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 17.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 17.6 Operating Modes............................................................................................................... 17.7 On-Board Programming Modes........................................................................................ 17.7.1 Boot Mode ........................................................................................................... 17.7.2 User Program Mode............................................................................................. 17.8 Flash Memory Programming/Erasing ............................................................................... 17.8.1 Program/Program-Verify ..................................................................................... 17.8.2 Erase/Erase-Verify............................................................................................... 17.9 Program/Erase Protection ................................................................................................. 17.9.1 Hardware Protection ............................................................................................ 17.9.2 Software Protection.............................................................................................. 17.9.3 Error Protection.................................................................................................... 17.10 Interrupts during Flash Memory Programming/Erasing ................................................... 17.11 Programmer Mode ............................................................................................................ 17.12 Usage Notes ...................................................................................................................... 415 415 416 417 418 419 419 420 424 425 425 427 429 429 429 429 430 431 431 433 434 434 435 437 437 438 438 439 439 439 439 440 Section 18 Clock Pulse Generator .................................................................................. 18.1 Oscillator........................................................................................................................... 18.1.1 Connecting Crystal Resonator ............................................................................. 18.1.2 External Clock Input Method............................................................................... 18.2 Duty Correction Circuit .................................................................................................... 18.3 Medium-Speed Clock Divider .......................................................................................... 18.4 Bus Master Clock Select Circuit ....................................................................................... 18.5 Subclock Input Circuit ...................................................................................................... 18.6 Waveform Forming Circuit............................................................................................... 18.7 Clock Select Circuit .......................................................................................................... 18.8 Usage Notes ...................................................................................................................... 18.8.1 Note on Resonator ............................................................................................... 18.8.2 Notes on Board Design ........................................................................................ Section 19 Power-Down Modes ...................................................................................... 441 19.1 Register Descriptions ........................................................................................................ 19.1.1 Standby Control Register (SBYCR) .................................................................... 19.1.2 Low-Power Control Register (LPWRCR) ........................................................... 19.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 19.2 Mode Transitions and LSI States ...................................................................................... 441 442 444 445 446 Rev. 2.00 Mar 21, 2006 page xxv of xxxviii 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 Medium-Speed Mode........................................................................................................ Sleep Mode ....................................................................................................................... Software Standby Mode.................................................................................................... Hardware Standby Mode .................................................................................................. Watch Mode...................................................................................................................... Subsleep Mode.................................................................................................................. Subactive Mode ................................................................................................................ Module Stop Mode ........................................................................................................... Direct Transitions.............................................................................................................. Usage Notes ...................................................................................................................... 19.12.1 I/O Port Status...................................................................................................... 19.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 449 450 451 452 453 454 455 456 456 457 457 457 Section 20 List of Registers .............................................................................................. 459 20.1 20.2 20.3 20.4 Register Addresses (Address Order) ................................................................................. Register Bits...................................................................................................................... Register States in Each Operating Mode........................................................................... Register Select Conditions ................................................................................................ 460 467 473 479 Section 21 Electrical Characteristics.............................................................................. 487 21.1 Electrical Characteristics................................................................................................... 21.1.1 Absolute Maximum Ratings ................................................................................ 21.1.2 DC Characteristics ............................................................................................... 21.1.3 AC Characteristics ............................................................................................... 21.1.4 Flash Memory Characteristics ............................................................................. 21.1.5 Usage Note........................................................................................................... 21.2 Timing Chart..................................................................................................................... 21.2.1 Clock Timing ....................................................................................................... 21.2.2 Control Signal Timing ......................................................................................... 21.2.3 On-Chip Peripheral Module Timing .................................................................... 487 487 488 494 499 501 501 501 503 504 Appendix A I/O Port States in Each Processing State .............................................. 511 Appendix B Product Codes .............................................................................................. 512 Appendix C Package Dimensions................................................................................... 513 Index ............................................................................................................................. 515 Rev. 2.00 Mar 21, 2006 page xxvi of xxxviii Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2110B .............................................................. Figure 1.2 Pin Arrangement of H8S/2110B......................................................................... Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ............................................................ Figure 2.2 Stack Structure in Normal Mode ........................................................................ Figure 2.3 Exception Vector Table (Advanced Mode) ........................................................ Figure 2.4 Stack Structure in Advanced Mode .................................................................... Figure 2.5 Memory Map ...................................................................................................... Figure 2.6 CPU Internal Registers ....................................................................................... Figure 2.7 Usage of General Registers................................................................................. Figure 2.8 Stack ................................................................................................................... Figure 2.9 General Register Data Formats (1) ..................................................................... Figure 2.9 General Register Data Formats (2) ..................................................................... Figure 2.10 Memory Data Formats........................................................................................ Figure 2.11 Instruction Formats (Examples).......................................................................... Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ............... Figure 2.13 State Transitions ................................................................................................. 2 3 17 17 18 19 19 20 21 22 24 25 26 38 41 45 Section 3 MCU Operating Modes Figure 3.1 Address Map for H8S/2110B (1)........................................................................ 55 Figure 3.2 Address Map for H8S/2110B (2)........................................................................ 56 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3) ................................................................................... 59 Figure 4.2 Stack Status after Exception Handling ............................................................... 61 Figure 4.3 Operation When SP Value Is Odd ...................................................................... 62 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ............................................................... 64 Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB 72 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 ....................................................... 73 Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 78 Figure 5.5 State Transition in Interrupt Control Mode 1 ..................................................... 79 Rev. 2.00 Mar 21, 2006 page xxvii of xxxviii Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1................................................................................................... Interrupt Exception Handling ............................................................................. Address Break Block Diagram ........................................................................... Address Break Timing Example......................................................................... Conflict between Interrupt Generation and Disabling ........................................ 81 82 84 86 87 Section 8 14-Bit PWM Timer (PWMX) Figure 8.1 PWM (D/A) Block Diagram............................................................................... Figure 8.2 PWM (D/A) Operation ....................................................................................... Figure 8.3 Output Waveform (OS = 0, DADR Corresponds to TL) ..................................... Figure 8.4 Output Waveform (OS = 1, DADR Corresponds to TH) ..................................... Figure 8.5 D/A Data Register Configuration when CFS = 1 ............................................... Figure 8.6 Output Waveform when DADR = H'0207 (OS = 1)........................................... Section 9 16-Bit Free-Running Timer (FRT) Figure 9.1 Block Diagram of 16-Bit Free-Running Timer................................................... Figure 9.2 Example of Pulse Output .................................................................................... Figure 9.3 Increment Timing with Internal Clock Source ................................................... Figure 9.4 Increment Timing with External Clock Source .................................................. Figure 9.5 Timing of Output Compare A Output................................................................. Figure 9.6 Clearing of FRC by Compare-Match A Signal................................................... Figure 9.7 Input Capture Input Signal Timing (Usual Case) ............................................... Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD Are Read)............... Figure 9.9 Buffered Input Capture Timing .......................................................................... Figure 9.10 Buffered Input Capture Timing (BUFEA = 1).................................................... Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ............... Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting .............................. Figure 9.13 Timing of Overflow Flag (OVF) Setting ............................................................ Figure 9.14 OCRA Automatic Addition Timing ................................................................... Figure 9.15 Timing of Input Capture Mask Signal Setting .................................................... Figure 9.16 Timing of Input Capture Mask Signal Clearing.................................................. Figure 9.17 FRC Write-Clear Conflict................................................................................... Figure 9.18 FRC Write-Increment Conflict ........................................................................... Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) ............................................ Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) ................................................... 131 138 140 141 141 142 148 159 159 160 160 161 161 162 162 163 163 164 164 165 165 166 167 168 169 170 Rev. 2.00 Mar 21, 2006 page xxviii of xxxviii Section 10 8-Bit Timer (TMR) Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ....................................... Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ..................................... Figure 10.3 Pulse Output Example ........................................................................................ Figure 10.4 Count Timing for Internal Clock Input............................................................... Figure 10.5 Count Timing for External Clock Input (Both Edges)........................................ Figure 10.6 Timing of CMF Setting at Compare-Match........................................................ Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal ........................ Figure 10.8 Timing of Counter Clear by Compare-Match..................................................... Figure 10.9 Timing of Counter Clear by External Reset Input .............................................. Figure 10.10 Timing of OVF Flag Setting............................................................................... Figure 10.11 Timing of Input Capture Operation .................................................................... Figure 10.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read)........................................................................ Figure 10.13 Conflict between TCNT Write and Clear ........................................................... Figure 10.14 Conflict between TCNT Write and Count-Up.................................................... Figure 10.15 Conflict between TCOR Write and Compare-Match.......................................... Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of WDT....................................................................................... Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation ............................................. Figure 11.3 Interval Timer Mode Operation ........................................................................... Figure 11.4 OVF Flag Set Timing........................................................................................... Figure 11.5 Output Timing of RESO signal............................................................................ Figure 11.6 Writing to TCNT and TCSR (WDT_0) ............................................................... Figure 11.7 Conflict between TCNT Write and Increment..................................................... Figure 11.8 Sample Circuit for Resetting System by RESO Signal........................................ 175 176 192 193 193 194 194 195 195 196 199 200 202 202 203 208 215 216 216 217 218 219 220 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI ......................................................................................... 222 Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).......................................................................................... 237 Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 239 Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ......................................................................................... 240 Figure 12.5 Sample SCI Initialization Flowchart.................................................................... 241 Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. 242 Figure 12.7 Sample Serial Transmission Flowchart................................................................ 243 Rev. 2.00 Mar 21, 2006 page xxix of xxxviii Figure 12.8 Figure 12.9 Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.13 Figure 12.14 Figure 12.15 Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Figure 12.20 Figure 12.21 Figure 12.22 Figure 12.23 Figure 12.24 Figure 12.25 Figure 12.26 2 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Sample Serial Reception Flowchart (1) ............................................................... Sample Serial Reception Flowchart (2) ............................................................... Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... Sample Multiprocessor Serial Transmission Flowchart....................................... Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ....................................................................... Sample Multiprocessor Serial Reception Flowchart (1) ...................................... Sample Multiprocessor Serial Reception Flowchart (2) ...................................... Data Format in Clocked Synchronous Communication (LSB-First) ................... Sample SCI Initialization Flowchart.................................................................... Example of SCI Transmit Operation in Clocked Synchronous Mode ................. Sample Serial Transmission Flowchart................................................................ Example of SCI Receive Operation in Clocked Synchronous Mode................... Sample Serial Reception Flowchart ..................................................................... Sample Flowchart of Simultaneous Serial Transmission and Reception ............. Sample Flowchart for Mode Transition during Transmission ............................. Pin States during Transmission in Asynchronous Mode (Internal Clock) ........... Pin States during Transmission in Clocked Synchronous Mode (Internal Clock).................................................................................................... Sample Flowchart for Mode Transition during Reception................................... Switching from SCK Pins to Port Pins ................................................................ Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ........ 244 246 247 249 250 251 252 253 254 255 256 257 258 259 261 265 265 266 266 267 267 Section 13 I C Bus Interface (IIC) 2 Figure 13.1 Block Diagram of I C Bus Interface .................................................................... 271 2 Figure 13.2 I C Bus Interface Connections (Example: This LSI as Master) ........................... 272 2 2 Figure 13.3 I C Bus Data Format (I C Bus Format) ................................................................ 297 2 Figure 13.4 I C Bus Data Format (Serial Format)................................................................... 297 2 Figure 13.5 I C Bus Timing .................................................................................................... 298 Figure 13.6 Sample Flowchart for IIC Initialization ............................................................... 299 Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode............................... 300 Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ... 302 Figure 13.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) .................................................................... 303 Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ........... 304 Figure 13.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ........................................................................................................... 306 Rev. 2.00 Mar 21, 2006 page xxx of xxxviii Figure 13.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)................................................... Figure 13.13 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1).............................................................. Figure 13.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) ................................................................ Figure 13.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) .......................................................................... Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) .......................................................................... Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1).............. Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS = 1). Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS = 1). Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0).............. Figure 13.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) .......................................................................... Figure 13.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) .......................................................................... Figure 13.23 Sample Flowchart for Slave Transmit Mode ....................................................... Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ........................ Figure 13.25 IRIC Setting Timing and SCL Control (1)........................................................... Figure 13.26 IRIC Setting Timing and SCL Control (2)........................................................... Figure 13.27 IRIC Setting Timing and SCL Control (3)........................................................... Figure 13.28 Block Diagram of Noise Canceler ....................................................................... Figure 13.29 Notes on Reading Master Receive Data............................................................... Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing........................................................................................................... Figure 13.31 Stop Condition Issuance Timing.......................................................................... Figure 13.32 IRIC Flag Clear Timing on WAIT Operation...................................................... Figure 13.33 IRIC Flag Clearing Timing When WAIT = 1 ...................................................... Figure 13.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode ......................... Figure 13.35 TRS Bit Set Timing in Slave Mode ..................................................................... Figure 13.36 Diagram of Erroneous Operation when Arbitration is Lost ................................. Section 14 Keyboard Buffer Controller Figure 14.1 Block Diagram of Keyboard Buffer Controller ................................................... Figure 14.2 Keyboard Buffer Controller Connection.............................................................. Figure 14.3 Sample Receive Processing Flowchart ................................................................ Figure 14.4 Receive Timing.................................................................................................... Figure 14.5 (1) Sample Transmit Processing Flowchart.............................................................. 306 307 308 310 311 312 314 315 316 318 318 319 321 322 323 324 325 331 332 333 334 334 335 336 337 339 340 345 346 347 Rev. 2.00 Mar 21, 2006 page xxxi of xxxviii Figure 14.5 (2) Sample Transmit Processing Flowchart.............................................................. Figure 14.6 Transmit Timing .................................................................................................. Figure 14.7 (1) Sample Receive Abort Processing Flowchart ..................................................... Figure 14.7 (2) Sample Receive Abort Processing Flowchart ..................................................... Figure 14.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing.................................................................................................................. Figure 14.9 KCLKI and KDI Read Timing............................................................................. Figure 14.10 KCLKO and KDO Write Timing......................................................................... Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing.................... Figure 14.12 Receive Counter and KBBR Data Load Timing.................................................. Figure 14.13 Example of KCLK Input Fall Interrupt Operation............................................... Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing................................ Section 15 Host Interface LPC Interface (LPC) Figure 15.1 Block Diagram of LPC ........................................................................................ Figure 15.2 Typical LFRAME Timing ................................................................................... Figure 15.3 Abort Mechanism ................................................................................................ Figure 15.4 GA20 Output........................................................................................................ Figure 15.5 Power-Down State Termination Timing.............................................................. Figure 15.6 SERIRQ Timing................................................................................................... Figure 15.7 Clock Start Request Timing................................................................................. Figure 15.8 HIRQ Flowchart (Example of Channel 1) ........................................................... Section 17 ROM Figure 17.1 Block Diagram of Flash Memory ........................................................................ Figure 17.2 Flash Memory State Transitions .......................................................................... Figure 17.3 Boot Mode ........................................................................................................... Figure 17.4 User Program Mode (Example) ........................................................................... Figure 17.5 Flash Memory Block Configuration .................................................................... Figure 17.6 On-Chip RAM Area in Boot Mode...................................................................... Figure 17.7 ID Code Area ....................................................................................................... Figure 17.8 Programming/Erasing Flowchart Example in User Program Mode..................... Figure 17.9 Program/Program-Verify Flowchart .................................................................... Figure 17.10 Erase/Erase-Verify Flowchart.............................................................................. Figure 17.11 Memory Map in Programmer Mode .................................................................... 348 348 349 350 350 351 352 353 354 355 356 358 392 392 394 399 400 402 405 410 411 412 413 414 423 423 424 426 428 431 Section 18 Clock Pulse Generator Figure 18.1 Block Diagram of Clock Pulse Generator............................................................ 433 Figure 18.2 Typical Connection to Crystal Resonator ............................................................ 434 Figure 18.3 Equivalent Circuit of Crystal Resonator .............................................................. 434 Rev. 2.00 Mar 21, 2006 page xxxii of xxxviii Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Example of External Clock Input......................................................................... External Clock Input Timing ............................................................................... Timing of External Clock Output Stabilization Delay Time ............................... Subclock Input Timing ........................................................................................ Note on Board Design of Oscillator Circuit Section............................................ 435 436 437 438 440 Section 19 Power-Down Modes Figure 19.1 Mode Transition Diagram.................................................................................... Figure 19.2 Medium-Speed Mode Timing.............................................................................. Figure 19.3 Application Example in Software Standby Mode................................................ Figure 19.4 Hardware Standby Mode Timing......................................................................... Section 21 Electrical Characteristics Figure 21.1 Darlington Pair Drive Circuit (Example)............................................................. Figure 21.2 LED Drive Circuit (Example).............................................................................. Figure 21.3 Output Load Circuit ............................................................................................. Figure 21.4 Connection of VCL Capacitor ............................................................................. Figure 21.5 System Clock Timing .......................................................................................... Figure 21.6 Oscillation Settling Timing.................................................................................. Figure 21.7 Oscillation Setting Timing (Exiting Software Standby Mode) ............................ Figure 21.8 Reset Input Timing .............................................................................................. Figure 21.9 Interrupt Input Timing ......................................................................................... Figure 21.10 I/O Port Input/Output Timing .............................................................................. Figure 21.11 FRT Input/Output Timing.................................................................................... Figure 21.12 FRT Clock Input Timing ..................................................................................... Figure 21.13 8-Bit Timer Output Timing.................................................................................. Figure 21.14 8-Bit Timer Clock Input Timing.......................................................................... Figure 21.15 8-Bit Timer Reset Input Timing........................................................................... Figure 21.16 PWMX Output Timing ........................................................................................ Figure 21.17 SCK Clock Input Timing ..................................................................................... Figure 21.18 SCI Input/Output Timing (Synchronous Mode) .................................................. Figure 21.19 A/D Converter External Trigger Input Timing .................................................... Figure 21.20 Keyboard Buffer Controller Timing .................................................................... 2 Figure 21.21 I C Bus Interface Input/Output Timing................................................................ Figure 21.22 Host Interface (LPC) Timing ............................................................................... Figure 21.23 Tester Measurement Condition............................................................................ 447 450 452 453 492 492 494 501 501 502 502 503 503 504 504 505 505 505 505 506 506 506 506 507 508 508 509 Appendix C Package Dimensions Figure C.1 Package Dimensions (FP-100B) .......................................................................... 513 Figure C.2 Package Dimensions (TFP-100B)........................................................................ 514 Rev. 2.00 Mar 21, 2006 page xxxiii of xxxviii Tables Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode.................................................................. Table 1.2 Pin Functions.......................................................................................................... Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation................................................................................................. Table 2.3 Data Transfer Instructions ...................................................................................... Table 2.4 Arithmetic Operations Instructions (1)................................................................... Table 2.4 Arithmetic Operations Instructions (2)................................................................... Table 2.5 Logic Operations Instructions ................................................................................ Table 2.6 Shift Instructions .................................................................................................... Table 2.7 Bit Manipulation Instructions (1) ........................................................................... Table 2.7 Bit Manipulation Instructions (2) ........................................................................... Table 2.8 Branch Instructions ................................................................................................ Table 2.9 System Control Instructions ................................................................................... Table 2.10 Block Data Transfer Instructions ........................................................................... Table 2.11 Addressing Modes.................................................................................................. Table 2.12 Absolute Address Access Ranges .......................................................................... Table 2.13 Effective Address Calculation (1) .......................................................................... Table 2.13 Effective Address Calculation (2) .......................................................................... 4 9 27 28 29 30 31 32 32 33 34 35 36 37 38 40 42 43 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................ 49 Section 4 Exception Handling Table 4.1 Exception Types and Priority ................................................................................. 57 Table 4.2 Exception Handling Vector Table .......................................................................... 58 Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 61 Section 5 Interrupt Controller Table 5.1 Pin Configuration ................................................................................................... 65 Table 5.2 Correspondence between Interrupt Source and ICR .............................................. 66 Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 75 Table 5.4 Interrupt Control Modes......................................................................................... 77 Table 5.5 Interrupt Response Times....................................................................................... 83 Table 5.6 Number of States in Interrupt Handling Routine Execution Status........................ 83 Rev. 2.00 Mar 21, 2006 page xxxiv of xxxviii Section 7 I/O Ports Table 7.1 Port Functions of H8S/2110B ................................................................................ Table 7.2 Input Pull-Up MOS States (Port 1) ........................................................................ Table 7.3 Input Pull-Up MOS States (Port 2) ........................................................................ Table 7.4 Input Pull-Up MOS States (Port 3) ........................................................................ Table 7.5 Input Pull-Up MOS States (Port 6) ........................................................................ Table 7.6 Input Pull-Up MOS States (Port A)........................................................................ Table 7.7 Input Pull-Up MOS States (Port B)........................................................................ Section 8 14-Bit PWM Timer (PWMX) Table 8.1 Pin Configuration ................................................................................................... Table 8.2 Read and Write Access Methods for 16-Bit Registers ........................................... Table 8.3 Settings and Operation (Examples When φ = 10 MHz) ......................................... Table 8.4 Position of Pulse to Be Added to Basic Pulse with 14-Bit Conversion Accuracy (CFS = 1)................................................................................................................ Table 8.5 Position of Pulse to Be Added to Basic Pulse with 12-Bit Conversion Accuracy (CFS = 1)................................................................................................................ Table 8.6 Position of Pulse to Be Added to Basic Pulse with 10-Bit Conversion Accuracy (CFS = 1)................................................................................................................ 92 96 98 101 112 126 129 132 137 139 143 144 145 Section 9 16-Bit Free-Running Timer (FRT) Table 9.1 Pin Configuration ................................................................................................... 149 Table 9.2 FRT Interrupt Sources............................................................................................ 166 Table 9.3 Switching of Internal Clock and FRC Operation ................................................... 171 Section 10 8-Bit Timer (TMR) Table 10.1 Pin Configuration ................................................................................................... Table 10.2 Clock Input to TCNT and Count Condition (1) ..................................................... Table 10.2 Clock Input to TCNT and Count Condition (2) ..................................................... Table 10.3 Registers Accessible by TMR_X/TMR_Y............................................................. Table 10.4 Input Capture Signal Selection............................................................................... Table 10.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X......... Table 10.6 Timer Output Priorities .......................................................................................... Table 10.7 Switching of Internal Clocks and TCNT Operation ............................................... 177 181 182 191 200 201 203 204 Section 11 Watchdog Timer (WDT) Table 11.1 Pin Configuration ................................................................................................... 209 Table 11.2 WDT Interrupt Source............................................................................................ 217 Rev. 2.00 Mar 21, 2006 page xxxv of xxxviii Section 12 Table 12.1 Table 12.2 Table 12.3 Table 12.3 Table 12.4 Table 12.5 Table 12.6 Table 12.7 Table 12.8 Table 12.9 Table 12.10 Section 13 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Serial Communication Interface (SCI) Pin Configuration ................................................................................................... Relationships between N Setting in BRR and Bit Rate B ...................................... BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Serial Transfer Formats (Asynchronous Mode) ..................................................... SSR Status Flags and Receive Data Handling........................................................ SCI Interrupt Sources ............................................................................................. I C Bus Interface (IIC) Pin Configuration ................................................................................................... Communication Format.......................................................................................... 2 I C Transfer Rate .................................................................................................... Flags and Transfer States (Master Mode) .............................................................. Flags and Transfer States (Slave Mode)................................................................. 2 I C Bus Data Format Symbols................................................................................ IIC Interrupt Sources.............................................................................................. 2 I C Bus Timing (SCL and SDA Outputs)............................................................... Permissible SCL Rise Time (tsr) Values ................................................................. 2 I C Bus Timing (with Maximum Influence of tSr/tSf)............................................... 2 223 232 233 234 235 235 236 236 238 245 262 272 276 279 285 286 298 327 328 328 330 Section 14 Keyboard Buffer Controller Table 14.1 Pin Configuration ................................................................................................... 340 Section 15 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 15.10 Host Interface LPC Interface (LPC) Pin Configuration ................................................................................................... Register Selection................................................................................................... GA20 (P81) Set/Clear Timing................................................................................ Fast A20 Gate Output Signals ............................................................................... Scope of Host Interface Pin Shutdown................................................................... Scope of Initialization in Each Host Interface Mode.............................................. Frame Configuration of Serial Interrupt Transfer Cycle ........................................ Receive Complete Interrupts and Error Interrupt ................................................... HIRQ Setting and Clearing Conditions.................................................................. Host Address Example ........................................................................................... 359 372 393 395 397 398 401 403 404 406 Rev. 2.00 Mar 21, 2006 page xxxvi of xxxviii Section 17 ROM Table 17.1 Differences between Boot Mode and User Program Mode.................................... Table 17.2 Pin Configuration ................................................................................................... Table 17.3 Operating Modes and ROM ................................................................................... Table 17.4 On-Board Programming Mode Settings................................................................. Table 17.5 Boot Mode Operation............................................................................................. Table 17.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible............................................................................................................... Section 18 Clock Pulse Generator Table 18.1 Damping Resistance Values ................................................................................... Table 18.2 Crystal Resonator Parameters ................................................................................ Table 18.3 External Clock Input Conditions ............................................................................ Table 18.4 External Clock Output Stabilization Delay Time................................................... Table 18.5 Subclock Input Conditions ..................................................................................... 411 415 419 419 422 423 434 435 436 437 438 Section 19 Power-Down Modes Table 19.1 Operating Frequency and Wait Time ..................................................................... 443 Table 19.2 LSI Internal States in Each Operating Mode.......................................................... 448 Section 21 Table 21.1 Table 21.2 Table 21.2 Table 21.2 Table 21.3 Table 21.4 Table 21.5 Table 21.6 Table 21.7 Table 21.8 Table 21.9 Table 21.10 Table 21.11 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics (1) ............................................................................................ DC Characteristics (2) ............................................................................................ DC Characteristics (3) When LPC Function Is Used ............................................. Permissible Output Currents .................................................................................. Bus Drive Characteristics ....................................................................................... Clock Timing ......................................................................................................... Control Signal Timing............................................................................................ Timing of On-Chip Peripheral Modules................................................................. Keyboard Buffer Controller Timing....................................................................... 2 I C Bus Timing....................................................................................................... LPC Module Timing .............................................................................................. Flash Memory Characteristics................................................................................ 487 488 490 491 491 493 494 495 496 497 497 498 499 Appendix A I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State ................................................................ 511 Rev. 2.00 Mar 21, 2006 page xxxvii of xxxviii Rev. 2.00 Mar 21, 2006 page xxxviii of xxxviii Section 1 Overview Section 1 Overview 1.1 Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral function 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) I C bus interface (IIC) Keyboard buffer controller Host interface LPC interface (LPC) Clock pulse generator • On-chip memory ROM F-ZTAT Version Model HD64F2110BV ROM 64 kbytes RAM 2 kbytes Remarks 2 • General I/O ports I/O pins: 82 • Supports various power-down states • Compact package Product H8S/2110B Package QFP-100B TQFP-100B Code FP-100B TFP-100B Body Size 16.0 × 16.0 mm Pin Pitch 0.5 mm Rev. 2.00 Mar 21, 2006 page 1 of 518 REJ09B0299-0200 Section 1 Overview 1.2 Block Diagram VCC VCL VSS VSS VSS VSS RES XTAL EXTAL VCCB MD1 MD0 NMI STBY RESO P97/SDA0 P96/φ/EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2 P67/TMOX/KIN7/IRQ7 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SDA1 P41/TMO0 P40/TMCI0 P52/ExSCK1*1/SCL0 P51/ExRxD1*1 P50/ExTxD1*1 Clock pulse generator Internal adderss bus Internal data bus H8S/2000 CPU Bus controller PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9 PA0/KIN8 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P37/SERIRQ P36/LCLK P35/LRESET P34/LFRAME P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0 PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3 PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI Interrup contoller Port 9 ROM (Flash memory) WDT × 2 channels Keyboard buffer controller × 3 channels Port 1 Port B Port 3 RAM Port 6 16-bit FRT 14-bit PWM Host interface (LPC) Port 4 8-bit timer × 4 channels SCI × 1 channel Port 5 IIC × 2 channles Port 8 Port 7 P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD P82/CLKRUN P81/GA20 P80/PME Notes: 1. The program development tool (emulator) does not support this function. 2. The program development tool (emulator) does not support the output. Figure 1.1 Internal Block Diagram of H8S/2110B Rev. 2.00 Mar 21, 2006 page 2 of 518 REJ09B0299-0200 P77*2/ExTMOX*1 P76*2/TMOY*1 P75*1*2 P74*1*2 P73*1*2 P72*1*2 P71*1*2 P70*1*2 VCC VCC VSS Port 2 Port A Section 1 Overview 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement P42/TMRI0/SDA1 P45/TMRI1 P13 P12 P11 P10 PB3/WUE3 PB2/WUE2 P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ PB1/WUE1/LSCI PB0/WUE0/LSMI VSS P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 RESO 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 RES P43/TMCI1 PB4/WUE4 PB5/WUE5 PB6/WUE6 PB7/WUE7 P47/PWX1 P46/PWX0 P44/TMO1 VCC VSS VSS P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P41/TMO0 P40/TMCI0 PA0/KIN8 PA1/KIN9 VSS P77*2/ExTMOX*1 P76*2/TMOY*1 P75*2 P74*2 P73*2 P72*2 P71*2 P70*2 VCC VCC P67/TMOX/KIN7/IRQ7 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 PA2/KIN10/PS2AC PA3/KIN11/PS2AD P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX 49 48 47 46 45 44 43 42 41 40 FP-100B TFP-100B (Top view) 39 38 37 36 35 34 33 32 31 30 29 28 27 2 XTAL 3 EXTAL 4 VCCB 5 MD1 6 MD0 7 NMI 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PA7/KIN15/PS2CD PA6/KIN14/PS2CC P97/SDA0 PA5/KIN13/PS2BD P52/ExSCK1*1/SCL0 PA4/KIN12/PS2BC STBY P96/φ/EXCL VCL VSS P94 P92/IRQ0 P91/IRQ1 P51/ExRxD1*1 P50/ExTxD1*1 P90/IRQ2 P95 P93 Notes: 1. The program development tool (emulator) does not support this function. 2. The program development tool (emulator) does not support the output. Figure 1.2 Pin Arrangement of H8S/2110B Rev. 2.00 Mar 21, 2006 page 3 of 518 REJ09B0299-0200 Section 1 Overview 1.3.2 Table 1.1 Pin Fuctions in Each Operating Mode Pin Functions in Each Operating Mode Pin Name Pin No. FP-100B TFP-100B 1 2 3 4 5 6 7 8 9 10 (B) 11 (B) 12 (N) 13 14 15 16 (N) 17 18 19 20 (B) 21 (B) Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL PA7/KIN15/PS2CD PA6/KIN14/PS2CC 1 P52/ExSCK1* /SCL0 1 P51/ExRxD1* 1 P50/ExTxD1* Flash Memory Programmer Mode RES XTAL EXTAL VCC VSS VSS FA9 VCC VCC NC NC NC FA17 NC VSS VCC NC FA16 FA15 NC NC VSS P97/SDA0 P96/φ/EXCL P95 P94 PA5/KIN13/PS2BD PA4/KIN12/PS2BC Rev. 2.00 Mar 21, 2006 page 4 of 518 REJ09B0299-0200 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 22 23 24 25 26 27 28 29 30 (B) 31 (B) 32 33 34 35 36 37 38 39 40 41 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P93 P92/IRQ0 P91/IRQ1 P90/IRQ2 P60/FTCI/KIN0/TMIX P61/FTOA/KIN1 P62/FTIA/KIN2/TMIY P63/FTIB/KIN3 PA3/KIN11/PS2AD PA2/KIN10/PS2AC P64/FTIC/KIN4 P65/FTID/KIN5 P66/FTOB/KIN6/IRQ6 P67/TMOX/KIN7/IRQ7 VCC VCC 2 P70* 2 P71* 2 P72* Flash Memory Programmer Mode WE VSS VCC VCC NC NC NC NC NC NC NC NC NC VSS VCC VCC NC NC NC NC P73* 2 Rev. 2.00 Mar 21, 2006 page 5 of 518 REJ09B0299-0200 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 42 43 44 45 46 47 (B) 48 (B) 49 50 51 (N) 52 53 54 55 56 57 58 59 60 61 62 63 64 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P74* P75* 2 2 2 1 Flash Memory Programmer Mode NC NC NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC VCC CE FA14 FA13 FA12 FA11 P76* /TMOY* 2 1 P77* /ExTMOX* VSS PA1/KIN9 PA0/KIN8 P40/TMCI0 P41/TMO0 P42/TMRI0/SDA1 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 PB7/WUE7 PB6/WUE6 VCC P27 P26 P25 P24 P23 Rev. 2.00 Mar 21, 2006 page 6 of 518 REJ09B0299-0200 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) P22 P21 P20 PB5/WUE5 PB4/WUE4 VSS VSS P17 P16 P15 P14 P13 P12 P11 P10 PB3/WUE3 PB2/WUE2 P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ PB1/WUE1/LSCI PB0/WUE0/LSMI Flash Memory Programmer Mode FA10 OE FA8 NC NC VSS VSS FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 NC NC FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 NC NC Rev. 2.00 Mar 21, 2006 page 7 of 518 REJ09B0299-0200 Section 1 Overview Pin Name Pin No. FP-100B TFP-100B 92 93 94 95 96 97 98 99 (N) 100 Single-Chip Modes Mode 2, Mode 3 (EXPE = 0) VSS P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 RESO Flash Memory Programmer Mode VSS NC NC NC NC NC NC NC NC Notes: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS pushpull/open-drain drive. 1. The program development tool (emulator) does not support this function. 2. The program development tool (emulator) does not support the output. Rev. 2.00 Mar 21, 2006 page 8 of 518 REJ09B0299-0200 Section 1 Overview 1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. Type Power Symbol VCC VCL VCCB VSS FP-100B, TFP-100B I/O 36, 37, 59 9 4 Input Input Input Name and Function Power supply pin. Connect the pin to the system power supply. Power supply pin. Connect the pin to VCC. The power supply for the port A input/output buffer. Ground pin. Connect to the system power supply (0 V). Pins for connection to crystal resonators. The EXTAL pin can also input an external clock. See section 18, Clock Pulse Generator, for typical connection diagrams. 15, 46, 70, Input 71, 92 2 3 Input Input Clock XTAL EXTAL φ EXCL Operating MD1 mode MD0 control System control RES RESO STBY Interrupt signals NMI IRQ0 to IRQ7 16-bit freerunning timer (FRT) FTCI FTOA FTOB FTIA 17 17 5 6 1 100 8 7 23 to 25, 97 to 99, 34, 35 26 27 34 28 Output Input Input Supplies the system clock to external devices. Input a 32.768 kHz external subclock. These pins set the operating mode. These pins should not be changed while the MCU is operating. Reset pin. When this pin becomes low, the chip is reset. Input Output Outputs a reset signal to external device. Input Input Input When this pin is driven low, a transition is made to hardware standby mode. Input pin for a nonmaskable interrupt request. These pins request a maskable interrupt. Input Output Output Input The counter clock input pin. The output compare A output pin. The output compare B output pin. The input capture A input pin. Rev. 2.00 Mar 21, 2006 page 9 of 518 REJ09B0299-0200 Section 1 Overview Pin No. Type 16-bit freerunning timer (FRT) 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) Symbol FTIB FTIC FTID TMO0 TMO1 TMOX 1 ExTMOX* *1 TMOY TMCI0 TMCI1 TMRI0 TMRI1 8-bit timer TMIX (TMR_X, TMIY TMR_Y) 14-bit PWM timer (PWMX) Serial communication interface (SCI_1) PWX0 PWX1 FP-100B, TFP-100B I/O 29 32 33 50 53 35 45 44 49 52 51 54 26 28 55 56 Input Input Input Name and Function The input capture B input pin. The input capture C input pin. The input capture D input pin. Output The waveform output pins for the output compare function. Input Input Input Input pins for the external clock input to counters. The counter reset input pins. The counter event input and counter reset input pins. Output PWM D/A pulse output pins. 1 ExTxD1* TxD1 1 ExRxD1* RxD1 14 97 13 98 12 99 31 21 11 30 20 10 Output Transmit data output pins. Input Receive data input pins. ExSCK1* SCK1 1 Input/ Clock input/output pins. Output The output type is NMOS push-pull. Input/ Output Keyboard buffer controller synchronization clock input/output pins. Keyboard PS2AC buffer PS2BC controller PS2CC PS2AD PS2BD PS2CD Input/ Keyboard buffer controller data input/output pins. Output Rev. 2.00 Mar 21, 2006 page 10 of 518 REJ09B0299-0200 Section 1 Overview Pin No. Type Host interface (LPC) Symbol LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ FP-100B, TFP-100B I/O 85 to 82 86 87 88 89 Name and Function Input/ LPC command, address, and data input/output pins. Output Input Input Input Input pin that indicates the start of an LPC cycle or forced termination of an abnormal LPC cycle. Input pin that indicates an LPC reset. The LPC clock input pin. Input/ Input/output pin for LPC serialized host interrupts Output (HIRQ1, SMI, HIRQ6, HIRQ9 to HIRQ12). Input/ LPC auxiliary output pins. Functionally, they are general Output I/O ports. Input/ A20 gate control signal output pin. Output state Output monitoring input is possible. Input/ Input/output pin that requests the start of LCLK Output operation when LCLK is stopped. Input Input pin that controls LPC module shutdown. Matrix keyboard input pins. KIN0 to KIN15 are used as key-scan inputs, and P10 to P17 and P20 to P27 are used as key-scan outputs. This allows a maximum 16output × 16-input, 256-key matrix to be configured. Wakeup event input pins. These pins allow the same kind of wakeup as key-wakeup from various sources. 2 LSCI, 90, 91, 93 LSMI, PME GA20 CLKRUN LPCPD Keyboard KIN0 to buffer KIN15 controller 94 95 96 26 to 29, Input 32 to 35, 48, 47, 31, 30, 21, 20, 11, 10 91, 90, 81, Input 80, 69, 68, 58, 57 12 99 16 51 WUE0 to WUE7 I C bus interface (IIC) 2 SCL0 SCL1 SDA0 SDA1 Input/ I C clock I/O pins. The output type is NMOS open-drain Output output. Input/ I C data I/O pins. The output type is NMOS open-drain Output output. 2 Rev. 2.00 Mar 21, 2006 page 11 of 518 REJ09B0299-0200 Section 1 Overview Pin No. Type I/O ports Symbol FP-100B, TFP-100B I/O Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Name and Function Eight input/output pins. Eight input/output pins. Eight input/output pins. Eight input/output pins. (The output type of P42 is NMOS push-pull.) Three input/output pins. (The output type of P52 is NMOS push-pull.) Eight input/output pins. P17 to P10 72 to 79 P27 to P20 60 to 67 P37 to P30 89 to 82 P47 to P40 56 to 49 P52 to P50 12 to 14 P67 to P60 35 to 32 29 to 26 P77 to P70 45 to 38 P86 to P80 99 to 93 P97 to P90 16 to 19 22 to 25 PA7 to PA0 PB7 to PB0 2 Input/ Eight input/output pins.* 2 Output* Input/ Output Input/ Output Seven input/output pins. (The output type of P86 is NMOS push-pull.) Eight input/output pins. (The output type of P97 is NMOS push-pull.) Eight input/output pins. 10, 11, 20, Input/ 21, 30, 31, Output 47, 48 57, 58, 68, Input/ 69, 80, 81, Output 90, 91 Eight input/output pins. Notes: 1. The program development tool (emulator) does not support this function. 2. The program development tool (emulator) does not support the output. Rev. 2.00 Mar 21, 2006 page 12 of 518 REJ09B0299-0200 Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features • Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs • General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers • Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions • Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] • 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes CPU210A_010020020800 Rev. 2.00 Mar 21, 2006 page 13 of 518 REJ09B0299-0200 Section 2 CPU • High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B) 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Rev. 2.00 Mar 21, 2006 page 14 of 518 REJ09B0299-0200 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register One 8-bit control register has been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. • Higher speed Basic instructions are executed twice as fast. Rev. 2.00 Mar 21, 2006 page 15 of 518 REJ09B0299-0200 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 kbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) • Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. • Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details on the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. • Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. Rev. 2.00 Mar 21, 2006 page 16 of 518 REJ09B0299-0200 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch Note: * Ignored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. Rev. 2.00 Mar 21, 2006 page 17 of 518 REJ09B0299-0200 Section 2 CPU • Instruction set All instructions and addressing modes can be used. • Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.3 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. • Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling. Rev. 2.00 Mar 21, 2006 page 18 of 518 REJ09B0299-0200 Section 2 CPU SP Reserved PC (24 bits) SP CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 64 kbytes H'FFFF 16 Mbytes Program area H'00000000 H'00FFFFFF Data area Not available in this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.5 Memory Map Rev. 2.00 Mar 21, 2006 page 19 of 518 REJ09B0299-0200 Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers 23 PC 0 EXR* T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: : Stack pointer SP : Program counter PC EXR : Extended control register : Trace bit T I2 to I0 : Interrupt mask bits CCR : Condition-code register : Interrupt mask bit I : User bit or interrupt mask bit UI Note: * Does not affect operation in this LSI. H : Half-carry flag U : User bit N : Negative flag Z : Zero flag V : Overflow flag C : Carry flag Figure 2.6 CPU Internal Registers Rev. 2.00 Mar 21, 2006 page 20 of 518 REJ09B0299-0200 Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. • Address registers • 32-bit registers • 16-bit registers • 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 2.00 Mar 21, 2006 page 21 of 518 REJ09B0299-0200 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI. Bit 7 6 to 3 2 to 0 Bit Name T — I2 I1 I0 Initial Value R/W 0 All 1 1 1 1 R/W — R/W R/W R/W Description Trace Bit Does not affect operation in this LSI. Reserved These bits are always read as 1. Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI. 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Rev. 2.00 Mar 21, 2006 page 22 of 518 REJ09B0299-0200 Section 2 CPU Bit 7 Bit Name I Initial Value 1 R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by • • • Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 2.00 Mar 21, 2006 page 23 of 518 REJ09B0299-0200 Section 2 CPU 2.4.5 Initial Register Values The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers. Data Type 1-bit data Register Number RnH Data Image 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 2.00 Mar 21, 2006 page 24 of 518 REJ09B0299-0200 Section 2 CPU Data Type Word data Register Number Rn 15 0 Data Image MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn : General register ER En : General register E Rn : General register R RnH : General register RH RnL : General register RL MSB: Most significant bit LSB : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 2.00 Mar 21, 2006 page 25 of 518 REJ09B0299-0200 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Image 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M + 1 MSB LSB Longword data Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3 MSB LSB Figure 2.10 Memory Data Formats 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Rev. 2.00 Mar 21, 2006 page 26 of 518 REJ09B0299-0200 Section 2 CPU Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* 5 5 LDM* , STM* 3 3 MOVFPE* , MOVTPE* Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 19 Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 4 8 14 5 9 1 Total: 65 BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B BIAND, BOR, BIOR, BXOR, BIXOR 2 BCC* , JMP, BSR, JSR, RTS — — — TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP Block data transfer EEPMOV Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. BCC is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5. 5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Rev. 2.00 Mar 21, 2006 page 27 of 518 REJ09B0299-0200 Section 2 CPU 2.6.1 Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ∼ :8/:16/:24/:32 Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 2.00 Mar 21, 2006 page 28 of 518 REJ09B0299-0200 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* 1 Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. B/W/L MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn → @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. 2 LDM* L L @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @-SP Pushes two or more general registers onto the stack. 2 STM* Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Rev. 2.00 Mar 21, 2006 page 29 of 518 REJ09B0299-0200 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 2.00 Mar 21, 2006 page 30 of 518 REJ09B0299-0200 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W 1 Function Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 TAS* B @ERd – 0, 1 → ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. Rev. 2.00 Mar 21, 2006 page 31 of 518 REJ09B0299-0200 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ∼ Rd → Rd Takes the one's complement (logical complement) of data in a general register. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Shift Instructions Size* B/W/L Function Rd (shift) → Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) → Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (rotate) → Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. B/W/L Rd (rotate) → Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 2.00 Mar 21, 2006 page 32 of 518 REJ09B0299-0200 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ∼ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ ( of ) → C Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ∧ ( of ) → C Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ ( of ) → C Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ (∼ of ) → C Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 2.00 Mar 21, 2006 page 33 of 518 REJ09B0299-0200 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ∼ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ∼ C → (. of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte Rev. 2.00 Mar 21, 2006 page 34 of 518 REJ09B0299-0200 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z ∨ (N ⊕ V ) = 0 Z ∨ (N ⊕ V ) = 1 Condition Always Never C∨Z=0 C∨Z=1 C=0 JMP BSR JSR RTS — — — — Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 2.00 Mar 21, 2006 page 35 of 518 REJ09B0299-0200 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* — — — B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC ORC XORC NOP B B B — CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word Rev. 2.00 Mar 21, 2006 page 36 of 518 REJ09B0299-0200 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size — Function if R4L ≠ 0 then Repeat @ER5 + → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5 + → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W — 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. • Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields, and some have no register field. • Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. • Condition field Specifies the branching condition of Bcc instructions. Rev. 2.00 Mar 21, 2006 page 37 of 518 REJ09B0299-0200 Section 2 CPU (1) Operation field only op NOP, RTS (2) Operation field and register fields op rn rm ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode 1 2 3 4 5 6 7 8 Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 Rev. 2.00 Mar 21, 2006 page 38 of 518 REJ09B0299-0200 Section 2 CPU 2.7.1 Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn Register Indirect with Post-Increment—@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Register Indirect with Pre-Decrement—@–ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). Rev. 2.00 Mar 21, 2006 page 39 of 518 REJ09B0299-0200 Section 2 CPU For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Rev. 2.00 Mar 21, 2006 page 40 of 518 REJ09B0299-0200 Section 2 CPU 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode Rev. 2.00 Mar 21, 2006 page 41 of 518 REJ09B0299-0200 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 0 Register indirect (@ERn) 31 24 23 0 General register contents op 3 r Don't care Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 0 General register contents op r disp 31 Sign extension 31 0 disp 24 23 0 Don't care 4 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 31 0 31 24 23 0 General register contents Don't care op r 31 1, 2, or 4 • Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 2.00 Mar 21, 2006 page 42 of 518 REJ09B0299-0200 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 • Normal mode 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care • Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Rev. 2.00 Mar 21, 2006 page 43 of 518 REJ09B0299-0200 Section 2 CPU 2.8 Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. • Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. • Program execution state In this state the CPU executes program instructions in sequence. • Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 44 of 518 REJ09B0299-0200 Section 2 CPU Program execution state SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 End of exception handling Request for exception handling SLEEP instruction with LSON = 0, SSBY = 0 Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Reset state *1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 19, Power-Down Modes. Figure 2.13 State Transitions Rev. 2.00 Mar 21, 2006 page 45 of 518 REJ09B0299-0200 Section 2 CPU 2.9 2.9.1 Usage Notes Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5. 2.9.2 Note on STM/LDM Instruction Usage ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by one STM/LDM instruction. The following ranges can be specified in the register list. Two registers: ER0–ER1, ER2–ER3, or ER4–ER5 Three registers: ER0–ER2 or ER4–ER6 Four registers: ER0–ER3 The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. 2.9.3 Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Example: The BCLR instruction is executed for DDR in port 4. P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at P46. P45 to P40 are output pins and output low-level signals. The following shows an example in which P40 is set to be an input pin with the BCLR instruction. Rev. 2.00 Mar 21, 2006 page 46 of 518 REJ09B0299-0200 Section 2 CPU Prior to executing BCLR: P47 Input/output Pin state DDR DR Input Low level 0 1 P46 Input High level 0 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Output Low level 1 0 BCLR instruction executed: BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4. After executing BCLR: P47 Input/output Pin state DDR DR Output Low level 1 1 P46 Output High level 1 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Input High level 0 0 Operation: 1. When the BCLR instruction is executed, first the CPU reads P4DDR. Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a value of H'3F, but the value read by the CPU is H'FF. 2. The CPU clears bit 0 of the read data to 0, changing data to H'FE. 3. The CPU writes H'FE to DDR, completing execution of BCLR. As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin. However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins. Rev. 2.00 Mar 21, 2006 page 47 of 518 REJ09B0299-0200 Section 2 CPU 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). R5 R6 R5 + R4L Invalid H'FFFF R6 + R4L Rev. 2.00 Mar 21, 2006 page 48 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MD1 1 MD0 0 1 CPU Operating Mode Advanced Normal Description Single-chip mode Single-chip mode On-Chip ROM Enabled MCU Operating Mode 2 3 Modes 2 and 3 set the operation in single-chip mode. Modes 0 and 1 cannot be used in this LSI. Thus, mode pins should be set to enable mode 2 or 3 in normal program execution state. Mode pins should not be changed during operation. 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) • Serial timer control register (STCR) Rev. 2.00 Mar 21, 2006 page 49 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode. Bit 7 6 to 2 1 0 Bit Name EXPE — Initial Value 0 All 0 R/W R/W Description Reserved The initial value should not be changed. Reserved These bits are always read as 0. These bits cannot be modified. R MDS1 MDS0 —* —* R R Mode Select 1 and 0 These bits indicate the input levels at mode pins (MD1 and MD0) (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and MD0, respectively. These bits are read-only bits and they cannot be written to. The mode pin (MD1 and MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * The initial values are determined by the settings of the MD1 and MD0 pins. Rev. 2.00 Mar 21, 2006 page 50 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit 7 and 6 5 4 Bit Name — Initial Value All 0 R/W R/W Description Reserved The initial value should not be changed. INTM1 INTM0 0 0 R R/W These bits select the control mode of the interrupt controller. For details on the interrupt control modes and interrupt control select modes 1 and 0, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset This bit indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows. 1: A reset is caused by an external reset. 2 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input Rev. 2.00 Mar 21, 2006 page 51 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes Bit 1 Bit Name HIE Initial Value 0 R/W R/W Description Host Interface Enable Controls CPU access to the keyboard matrix interrupt, input pull-up MOS control registers (KMIMR, KMPCR, and KMIMRA), and the 8-bit timer (TMR_X and TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and TCORB_X, TCONRI, and TCONRS). 0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X and TMR_Y) is permitted. 1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to keyboard matrix interrupt and input pull-up MOS control registers is permitted. 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 2.00 Mar 21, 2006 page 52 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit 7 Bit Name IICS Initial Value 0 R/W R/W Description I C Extra Buffer Select Specifies bits 7 to 4 of port A as output buffers similar to SCL and SDA. These pins are used to 2 implement an I C interface only by software. 0: PA7 to PA4 are normal input/output pins. 1: PA7 to PA4 are input/output pins enabling bus driving. 6 5 IICX1 IICX0 0 0 R/W R/W I C Transfer Rate Select 1 and 0 These bits control the IIC operation. These bits select a transfer rate in master mode together with 2 bits CKS2 to CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, refer to table 13.3. I C Master Enable Enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), and SCI registers (SMR, BRR, SCMR). 0: SCI_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. 1: IIC_1 registers are accessed in an area from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in an area from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in an area from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 2 2 2 4 IICE 0 R/W Rev. 2.00 Mar 21, 2006 page 53 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes Bit 3 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 1: Control registers of flash memory are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 2 1 0 — ICKS1 ICKS0 0 0 0 R/(W) R/W R/W Reserved The initial value should not be changed. Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, refer to section 10.3.4, Timer Control Register (TCR). 3.3 3.3.1 Operating Mode Descriptions Mode 2 The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM is enabled. 3.3.2 Mode 3 The CPU can access a 64-kbyte address space in normal single-chip mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. Rev. 2.00 Mar 21, 2006 page 54 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes 3.4 Address Map in Each Operating Mode Figures 3.1 and 3.2 show the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000 On-chip ROM H'00FFFF Reserved area H'01FFFF H'FFE080 H'FFE880 H'FFEFFF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Reserved area On-chip RAM Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Figure 3.1 Address Map for H8S/2110B (1) Rev. 2.00 Mar 21, 2006 page 55 of 518 REJ09B0299-0200 Section 3 MCU Operating Modes Mode 3 (EXPE = 0) Normal mode Single-chip mode H'0000 On-chip ROM H'DFFF H'E080 H'E880 Reserved area On-chip RAM H'EFFF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 Figure 3.2 Address Map for H8S/2110B (2) Rev. 2.00 Mar 21, 2006 page 56 of 518 REJ09B0299-0200 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direction transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in program execution state. Direct transition Trap instruction Low Rev. 2.00 Mar 21, 2006 page 57 of 518 REJ09B0299-0200 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Vector Address Exception Source Reset Reserved for system use Vector Number 0 1  5 6 7 8 9 10 11 Reserved for system use 12  15 16 17 18 19 20 21 22 23 24  111 Normal Mode H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031  H'00DE to H'00DF Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063  H'0001BC to H'0001BF Direct transition External interrupt (NMI) Trap instruction (four sources) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Rev. 2.00 Mar 21, 2006 page 58 of 518 REJ09B0299-0200 Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit is set to 1 in CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. Vector fetch Internal Prefetch of first program processing instruction φ RES Internal address bus (1) (3) Internal read signal Internal write signal High Internal data bus (2) (4) (1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction Figure 4.1 Reset Sequence (Mode 3) Rev. 2.00 Mar 21, 2006 page 59 of 518 REJ09B0299-0200 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all modules operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. 4.5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. Rev. 2.00 Mar 21, 2006 page 60 of 518 REJ09B0299-0200 Section 4 Exception Handling The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling. Table 4.3 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 Legend: 1: Set to 1 —: Retains value prior to execution I 1 1 UI — 1 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Note: Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 2.00 Mar 21, 2006 page 61 of 518 REJ09B0299-0200 Section 4 Exception Handling 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd. Address CCR SP PC SP R1L H'FFEFFA H'FFEFFB PC H'FFEFFC H'FFEFFD SP H'FFEFFF TRAPA instruction executed SP set to H'FFEFFF Legend: CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer MOV.B R1L, @-ER7 executed Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode. Figure 4.3 Operation When SP Value Is Odd Rev. 2.00 Mar 21, 2006 page 62 of 518 REJ09B0299-0200 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break. • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Thirty-one external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin and sixteen external interrupt inputs (KIN15 to KIN8 and WUE7 to WUE0). KIN15 to KIN0 and WUE7 to WUE0 can be masked individually by the user program. Rev. 2.00 Mar 21, 2006 page 63 of 518 REJ09B0299-0200 Section 5 Interrupt Controller INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR KMIMR KIN input WUE input Internal interrupt request WOVI0 to IBFI3 ICR Interrupt controller Legend: : Interrupt control register ICR : IRQ sense control register ISCR : IRQ enable register IER : IRQ status register ISR KMIMR : Keyboard matrix interrupt mask register WUEMR : Wake-up event interrupt mask register SYSCR : System control register IER WUEMR CPU Interrupt request Vector number Priority check KIN and WUE input I, UI CCR Figure 5.1 Block Diagram of Interrupt Controller Rev. 2.00 Mar 21, 2006 page 64 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Symbol NMI IRQ7 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, both edges, or level sensing, can be selected individually for each pin. KIN15 to KIN0 WUE7 to WUE0 Input Input Maskable external interrupts Falling edge or level sensing can be selected. Maskable external interrupts Falling edge or level sensing can be selected. 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). • Interrupt control registers A to C (ICRA to ICRC) • Address break control register (ABRKCR) • Break address registers A to C (BARA to BARC) • IRQ sense control registers (ISCRH, ISCRL) • IRQ enable register (IER) • IRQ status register (ISR) • Keyboard matrix interrupt mask registers (KMIMRA, KMIMR) • Wake-up event interrupt mask register (WUEMRB) Rev. 2.00 Mar 21, 2006 page 65 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2. Bit 7 to 0 Bit Name ICRn7 to IRCn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) Note: n: A to C Table 5.2 Correspondence between Interrupt Source and ICR Register Bit 7 6 5 4 3 2 1 0 Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 — WDT_0 WDT_1 ICRB — FRT — — TMR_0 TMR_1 TMR_X , TMR_Y Keyboard buffer controller ICRC — SCI_1 — IIC_0 IIC_1 — LPC — Legend: : Reserved. The write value should always be 0. Note: n: A to C Rev. 2.00 Mar 21, 2006 page 66 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested. Bit 7 Bit Name CMF Initial Value 0 R/W R Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1. [Clearing condition] When an exception handling is executed for an address break interrupt. 6 to 1 0 — All 0 R Reserved These bits are always read as 0 and cannot be modified. BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. • BARA Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus. Rev. 2.00 Mar 21, 2006 page 67 of 518 REJ09B0299-0200 Section 5 Interrupt Controller • BARB Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus. • BARC Bit 7 to 1 0 Bit Name A7 to A1 — Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 R Reserved This bit is always read as 0 and cannot be modified. 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. • ISCRH Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 7 to 4) Rev. 2.00 Mar 21, 2006 page 68 of 518 REJ09B0299-0200 Section 5 Interrupt Controller • ISCRL Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 3 to 0) 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. Rev. 2.00 Mar 21, 2006 page 69 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests. Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] When reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high (n = 7 to 0) When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set Note: * Only 0 can be written, for flag clearing. 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and Wake-Up Event Interrupt Mask Register (WUEMRB) The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0). • KMIMRA Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 15 to 8 These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request Rev. 2.00 Mar 21, 2006 page 70 of 518 REJ09B0299-0200 Section 5 Interrupt Controller • KMIMR Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial Value 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 7 to 0 These bits enable or disable a key-sensing input interrupt request (KIN7 to KIN0). KMIMR6 also performs interrupt request mask control for pin IRQ6. 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request • WUEMRB Bit 7 6 5 4 3 2 1 0 Bit Name WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask 7 to 0 These bits enable or disable a wake-up event input interrupt request (WUE7 to WUE0). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMRA, KMIMR, and WUEMRB. Rev. 2.00 Mar 21, 2006 page 71 of 518 REJ09B0299-0200 Section 5 Interrupt Controller KMIMR0 (initial value 1) P60/KIN0 KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7 IRQ6 internal signal Edge level selection enable/disable circuit IRQ6 interrupt IRQ6E IRQ6SC KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 WUEMR7 (initial value 1) PB7/WUE7 IRQ7 internal signal Edge level selection enable/disable circuit IRQ7 interrupt IRQ7E IRQ7SC Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB If any of bits KMIMR15 to KMIMR8 or WUEMR7 to WUEMR0 is cleared to 0, interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either lowlevel sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). Rev. 2.00 Mar 21, 2006 page 72 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an independent vector address. • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • Interrupt control levels can be specified by the ICR settings. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 to use the pin as an I/O pin for another function. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Note: n = 7 to 0 Clear signal S R Q IRQn interrupt request Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 Rev. 2.00 Mar 21, 2006 page 73 of 518 REJ09B0299-0200 Section 5 Interrupt Controller When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored. Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied, regardless of the IER setting, refer to a needed flag only. KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7 to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE7 to WUE0. When pins KIN15 to KIN0 and WUE7 to WUE0 are used for key-sense input or wakeup event, clear the corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8 generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin conditions for interrupt request generation, enable of interrupt requests, settings of interrupt control levels, and status display of interrupt requests depend on each setting and display of the IRQ7 or IRQ6 interrupt. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7). 5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2. The control level for each interrupt can be set by ICR. 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 2.00 Mar 21, 2006 page 74 of 518 REJ09B0299-0200 Section 5 Interrupt Controller An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to control level 0 (no priority). Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Vector Normal Number Mode 7 16 17 18 19 20 21 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 to H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 to H'007E H'0080 H'0082 H'0084 H'0086 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 to H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 to H'0000FC H'000100 H'000104 H'000108 H'00010C ICR — ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 Priority High Origin of Interrupt Name Source External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 22 IRQ7, KIN15 to KIN8, WUE7 to 23 WUE0 — WDT_0 WDT_1 — — Reserved for system use WOVI0 (Interval timer) WOVI1 (Interval timer) Address break Reserved for system use 24 25 26 27 28 to 47 48 49 50 51 52 53 54 55 56 to 63 64 65 66 67 — ICRA1 ICRA0 — — FRT ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use Reserved for system use ICRB6 — — TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use ICRB3 Low Rev. 2.00 Mar 21, 2006 page 75 of 518 REJ09B0299-0200 Section 5 Interrupt Controller Origin of Interrupt Name Source TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture X) Reserved for system use Vector Address Vector Normal Number Mode 68 69 70 71 72 73 74 75 76 to 83 84 85 86 87 88 to 91 92 93 94 95 96 97 98 99 100 to 107 108 109 110 111 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 to H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 to H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00C2 H'00C4 H'00C6 H'00C8 to H'00D6 H'00D8 H'00DA H'00DC H'00DE Advanced Mode H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 to H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 to H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'000184 H'000188 H'00018C H'000190 to H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC ICRB0 ICRC3 ICR ICRB2 Priority High TMR_X, TMR_Y ICRB1 — — SCI_1 ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) Reserved for system use ICRC6 — — IIC_0 IICI0 (1-byte transmission/ reception completion) Reserved for system use IICI1 (1-byte transmission/ reception completion) Reserved for system use ICRC4 IIC_1 Keyboard KBIA (Reception completion A) buffer KBIB (Reception completion B) controller KBIC (Reception completion C) Reserved for system use — Reserved for system use — LPC ERRI (Transfer error) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) ICRC1 Low Rev. 2.00 Mar 21, 2006 page 76 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes Priority Setting Registers ICR Interrupt Mask Bits I Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0 Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 1 1 ICR I, UI 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI and address breaks are masked by ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. Rev. 2.00 Mar 21, 2006 page 77 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program excution state Interrupt generated? Yes Yes No NMI No An interrupt with interrupt control level 1? No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 IBFI3 Yes Yes IBFI3 Yes No No I=0 Yes No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 2.00 Mar 21, 2006 page 78 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. • An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending • An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5 shows a state transition diagram. • All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 …) • Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI = 0. • Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1. I All interrupt requests are accepted I 0 0 1, UI Only NMI, address break, IRQ2, and IRQ3 interrupt requests are accepted UI 0 Exception handling execution or UI 1 I Exception handling execution or I 1, UI 1 0 Only NMI and address break interrupt requests are accepted Figure 5.5 State Transition in Interrupt Control Mode 1 Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an Rev. 2.00 Mar 21, 2006 page 79 of 518 REJ09B0299-0200 Section 5 Interrupt Controller interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When both the I and UI bits are set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit is not affected. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address break interrupt. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 2.00 Mar 21, 2006 page 80 of 518 REJ09B0299-0200 Section 5 Interrupt Controller Program excution state No Interrupt generated? Yes Yes NMI No An interrupt with interrupt control level 1? No Hold pending Yes No No IRQ1 Yes IBFI3 Yes No IRQ0 Yes IRQ1 Yes IBFI3 Yes No IRQ0 Yes I=0 Yes No I=0 No Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 2.00 Mar 21, 2006 page 81 of 518 REJ09B0299-0200 Interrupt is accepted Section 5 Interrupt Controller Interrupt level decision and wait for end of instruction Instruction prefetch Stack access Vector fetch Internal processing Internal processing Prefetch of instruction in interrupt-handling routine φ Rev. 2.00 Mar 21, 2006 page 82 of 518 REJ09B0299-0200 Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) (13) Internal read signal Internal write signal Figure 5.7 Interrupt Exception Handling Internal data bus (2) (4) (6) (8) (10) (12) (14) (1) (2) (4) (3) (5) (7) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.) SP – 2 SP – 4 (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and CCR Vector address Starting address of interrupt-handling routine (contents of vector address) Starting address of interrupt-handling routine ((13) = (10) (12)) First instruction in interrupt-handling routine Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times Normal Mode 3 1 to (19 + 2·SI) 2·SK SI 3 No. Execution Status 1 2 3 4 5 6 1 Interrupt priority determination* Advanced Mode 3 1 to (19 + 2·SI) 2·SK 2·SI 2·SI 2 12 to 32 Number of wait states until executing 2 instruction ends* PC, CCR stack save Vector fetch Instruction fetch* 4 Internal processing* 2·SI 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.6 Number of States in Interrupt Handling Routine Execution Status Object of Access Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK Internal Memory 1 Rev. 2.00 Mar 21, 2006 page 83 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.7 5.7.1 Address Break Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. 5.7.2 Block Diagram Figure 5.8 shows a block diagram of the address break. BAR ABRKCR Comparator Match signal Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.8 Address Break Block Diagram 5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the CPU is invalid to an address break interrupt. Rev. 2.00 Mar 21, 2006 page 84 of 518 REJ09B0299-0200 Section 5 Interrupt Controller To use the address break function, set each register as follows: 1. Set a break address in the A23 to A1 bits in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable the address break. When the BIE bit is cleared to 0, an address break is not requested. When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an interrupt. The interrupt source should be determined by the interrupt handling routine if necessary. 5.7.4 Usage Notes 1. In an address break, the break address should be an address where the first byte of the instruction exists. Otherwise, a break condition will not be satisfied. 2. In normal mode, addresses A23 to A16 are not compared. 3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and RTE instruction are placed immediately prior to the address specified by BAR, a prefetch signal to the address may be output to request an address break by executing these instruction. It is necessary to take countermeasures: do not set a break address to an address immediately after these instructions, or determine whether interrupt handling is performed by satisfaction of a normal condition. 4. An address break interrupt is generated by combining the internal prefetch signal and an address. Therefore, the timing to enter the interrupt exception handling differs according to the instructions at the specified and at prior addresses and execution cycles. Figure 5.9 shows an example of address timing. Rev. 2.00 Mar 21, 2006 page 85 of 518 REJ09B0299-0200 Section 5 Interrupt Controller (1) When a break address specified instruction is executed for one state in the program area and on-chip memory Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Save to stack Vector fetch Instruction Internal fetch operation φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP NOP execution execution NOP execution Interrupt exception handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Break point NOP instruction is executed at break point address H'0312 and following address H'0314. Fetching is performed from address H'0316 after exception handling ends. (2) When a break address specified instruction is executed for two states in the program area and on-chip memory Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Save to stack Vector fetch Internal operation Instruction fetch φ Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP execution MOV.W execution Interrupt exception handling Break request signal H'0310 H'0312 H'0316 H'0318 NOP MOV.W #xx:16,Rd NOP NOP Break point MOV instruction is executed at break point address H'0312, and NOP instruction is not executed at the following address H'0314. Fetching is performed from address H'0316 after exception handling ends. Figure 5.9 Address Break Timing Example Rev. 2.00 Mar 21, 2006 page 86 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10 shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TCR write cycle by CPU CMIA exception handling φ Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.10 Conflict between Interrupt Generation and Disabling Rev. 2.00 Mar 21, 2006 page 87 of 518 REJ09B0299-0200 Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.4 IRQ Status Register (ISR) According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset to write 0. (n = 7 to 0) Rev. 2.00 Mar 21, 2006 page 88 of 518 REJ09B0299-0200 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. 6.1 Register Descriptions The bus controller has the following registers. • Bus control register (BCR) • Wait state control register (WSCR) 6.1.1 Bit 7 6 5 4 3 2 1 0 Bus Control Register (BCR) Bit Name — ICIS0 BRSTRM BRSTS1 BRSTS0  IOS1 IOS0 Initial Value 1 1 0 1 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion The initial value should not be changed. Burst ROM Enable The initial value should not be changed. Burst Cycle Select 1 The initial value should not be changed. Burst Cycle Select 0 The initial value should not be changed. Reserved The initial value should not be changed. IOS Select 1, 0 The initial value should not be changed. BSCS20AA_010020020800 Rev. 2.00 Mar 21, 2006 page 89 of 518 REJ09B0299-0200 Section 6 Bus Controller (BSC) 6.1.2 Bit Wait State Control Register (WSCR) Bit Name Initial Value All 0 1 1 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed. Wait Mode Select 1, 0 The initial value should not be changed. Wait Count 1, 0 The initial value should not be changed. 7, 6 — 5 4 3 2 1 0 ABW AST WMS1 WMS0 WC1 WC0 Rev. 2.00 Mar 21, 2006 page 90 of 518 REJ09B0299-0200 Section 7 I/O Ports Section 7 I/O Ports 7.1 Overview This LSI has eleven I/O ports (ports 1 to 9*, A, and B). Table 7.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, A, and B have an on-chip input pull-up MOS function. For ports A and B, the on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR, to control the on/off status of the input pull-up MOS. Ports 1 to 9*, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1 to 3 can drive an LED (10 mA sink current). Port A input and output use by the VccB power supply, which is independent of the Vcc power supply. When the VccB voltage is 5V, the pins on port A will be 5-V tolerant. PA4 to PA7 of port A have bus-buffer drive capability. P52 in port 5, P97 in port 9, P86 in port 8 and P42 in port 4 are NMOS push-pull outputs. P52, P97, P86 and P42 are thus 5-V tolerant, with DC characteristics that are dependent on the Vcc voltage. For the P42, P52/ExSCK1, P86/SCK1, and P97 outputs, connect pull-up resistors to pins to raise output-high-level voltage. Note: * The program development tool (emulator) does not support the output of port 7. Rev. 2.00 Mar 21, 2006 page 91 of 518 REJ09B0299-0200 Section 7 I/O Ports Table 7.1 Port Port 1 Port Functions of H8S/2110B Description General I/O port Mode 2, 3 P17 P16 P15 P14 P13 P12 P11 P10 I/O Status On-chip input pull-up MOSs Port 2 General I/O port P27 P26 P25 P24 P23 P22 P21 P20 On-chip input pull-up MOSs Port 3 General I/O port also functioning as LPC input/output pins P37/SERIRQ P36/LCLK P35/LRESET P34/LFRAME P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0 On-chip input pull-up MOSs Rev. 2.00 Mar 21, 2006 page 92 of 518 REJ09B0299-0200 Section 7 I/O Ports Port Port 4 Description General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, and IIC_1 input/output pins Mode 2, 3 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SDA1 P41/TMO0 P40/TMCI0 Port 5 General I/O port also functioning as SCI_1 extended input/output and IIC_0 input/output pins General I/O port also functioning as interrupt input, FRT input/output, TMR_X input/output, TMR_Y output, and keysense interrupt input 1 P52/ExSCK1* /SCL0 1 P51/ExRxD1* I/O Status P50/ExTxD1* 1 Port 6 P67/TMOX/KIN7/IRQ7 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX On-chip input pull-up MOSs Port 7 General I/O port* also functioning as TMR_X extended output and TMR_Y output pins 2 P77* /ExTMOX* 2 1 P76* /TMOY* 2 1 P75* 2 P74* 2 P73* 2 P72* 2 P71* 2 P70* 2 Rev. 2.00 Mar 21, 2006 page 93 of 518 REJ09B0299-0200 Section 7 I/O Ports Port Port 8 Description General I/O port also functioning as interrupt input, SCI_1 input/output, LPC input/output, and IIC_1 input/output pins Mode 2, 3 P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD P82/CLKRUN P81/GA20 P80/PME Port 9 General I/O port also functioning as IIC_0 input/output, subclock input, φ output, and interrupt input P97/SDA0 P96/φ/EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2 Port A General I/O port also functioning as key-sense interrupt input, and keyboard buffer controller input/output pins PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9 PA0/KIN8 Port B General I/O port also functioning as wakeup event interrupt input, and LPC input/output pins PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3 PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI Notes: 1. The program development tool (emulator) does not support this function. 2. The program development tool (emulator) does not support the output. On-chip input pull-up MOSs On-chip input pull-up MOSs I/O Status Rev. 2.00 Mar 21, 2006 page 94 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.2 Port 1 Port 1 is an 8-bit I/O port. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 7.2.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 1 pins are output ports when the P1DDR bits are set to 1, and input ports when the P1DDR bits are cleared to 0. 7.2.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.00 Mar 21, 2006 page 95 of 518 REJ09B0299-0200 Description If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read. Section 7 I/O Ports 7.2.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off status of the port 1 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a P1PCR bit is set to 1 with the input port setting, the input pull-up MOS is turned on. 7.2.4 Pin Functions • P17 to P10 The pin function is switched as shown below according to the status of the P1nDDR bit. P1nDDR Pin Function Note: n = 7 to 0 0 P17 to P10 input pins 1 P17 to P10 output pins 7.2.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.2 summarizes the input pull-up MOS states. Table 7.2 Reset Off Input Pull-Up MOS States (Port 1) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P1DDR = 0, and P1PCR = 1; otherwise off. Rev. 2.00 Mar 21, 2006 page 96 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.3 Port 2 Port 2 is an 8-bit I/O port. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 pull-up MOS control register (P2PCR) 7.3.1 Port 2 Data Direction Register (P2DDR) P2DDR specifies input or output for the pins of port 2 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 2 pins are output ports when P2DDR bits are set to 1, and input ports when P2DDR bits are cleared to 0. 7.3.2 Port 2 Data Register (P2DR) P2DR stores output data for port 2. Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.00 Mar 21, 2006 page 97 of 518 REJ09B0299-0200 Description If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. Section 7 I/O Ports 7.3.3 Port 2 Pull-Up MOS Control Register (P2PCR) P2PCR controls the port 2 on-chip input pull-up MOSs. Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The input pull-up MOS is turned on when a P2PCR bit is set to 1 in the input port state. 7.3.4 Pin Functions • P27 to P20 The pin function is switched as shown below according to the status of the P2nDDR bit. P2nDDR Pin Function Note: n = 7 to 0 0 P27 to P20 input pins 1 P27 to P20 output pins 7.3.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.3 summarizes the input pull-up MOS states. Table 7.3 Reset Off Input Pull-Up MOS States (Port 2) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P2DDR = 0, and P2PCR = 1; otherwise off. Rev. 2.00 Mar 21, 2006 page 98 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.4 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as LPC input/output pins. Port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 pull-up MOS control register (P3PCR) 7.4.1 Port 3 Data Direction Register (P3DDR) P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when P3DDR bits are cleared to 0. 7.4.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.00 Mar 21, 2006 page 99 of 518 REJ09B0299-0200 Description If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. Section 7 I/O Ports 7.4.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The input pull-up MOS is turned on when a P3PCR bit is set to 1 in the input port state. The input pull-up MOS function cannot be used when the host interface is enabled. 7.4.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LPC3E to LPC1E bits in HICR0 of host interface (LPC), and the P3nDDR bit. LPCmE HI12E P3nDDR Pin Function 0 P37 to P30 input pins All 0 0 1 P37 to P30 output pins Not all 0 0 0 LPC input/output pins Note: * The combination of bits not described in the above table must not be used. m = 3 to 1: LPC input/output pins (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0) when at least one of LPC3E to LPC1E is set to 1. n = 7 to 0 Rev. 2.00 Mar 21, 2006 page 100 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.4.5 Port 3 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.4 summarizes the input pull-up MOS states. Table 7.4 Reset Off Input Pull-Up MOS States (Port 3) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P3DDR = 0, and P3PCR = 1; otherwise off. 7.5 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as PWMX output pins, TMR_0 and TMR_1 I/O pins, and the IIC_1 I/O pin. The output type of P42 is NMOS push-pull output. The output type of SDA1 is NMOS open-drain output. Port 4 has the following registers. • Port 4 data direction register (P4DDR) • Port 4 data register (P4DR) 7.5.1 Port 4 Data Direction Register (P4DDR) P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. As 14-bit PWM is initialized in software standby mode, the pin states are determined by the TMR_0, TMR_1, IIC_1, P4DDR, and P4DR specifications. Rev. 2.00 Mar 21, 2006 page 101 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.5.2 Port 4 Data Register (P4DR) P4DR stores output data for port 4. Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read. 7.5.3 Pin Functions • P47/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR of the 14-bit PWM and the P47DDR bit. OEB P47DDR Pin Function 0 P47 input pin 0 1 P47 output pin 1 — PWX1 output pin • P46/PWX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of the 14-bit PWM and the P46DDR bit. OEA P46DDR Pin Function 0 P46 input pin 0 1 P46 output pin 1 — PWX0 output pin Rev. 2.00 Mar 21, 2006 page 102 of 518 REJ09B0299-0200 Section 7 I/O Ports • P45/TMRI1 The pin function is switched as shown below according to the status of the P45DDR bit. P45DDR Pin Function 0 P45 input pin TMRI1 input pin Note: * When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. 1 P45 output pin • P44/TMO1 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_1 and the P44DDR bit. OS3 to OS0 P44DDR Pin Function 0 P44 input pin All 0 1 P44 output pin TMO1 output pin Not all 0 • P43/TMCI1 The pin function is switched as shown below according to the status of the P43DDR bit. P43DDR Pin Function 0 P43 input pin TMCI1 input pin* Note: * When the external clock is selected by bits CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin. 1 P43 output pin • P42/TMRI0/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P42DDR bit. ICE P42DDR Pin Function 0 P42 input pin 0 1 P42 output pin TMRI0 input pin* Note: * SDA1 is an NMOS-only output, and has direct bus drive capability. When bits CCLR1 and CCLR0 in TCR0 of TMR_0 are set to 1, this pin is used as the TMRI0 input pin. When the P42 output pin is set, the output type is NMOS push-pull output. SDA1 I/O pin 1 Rev. 2.00 Mar 21, 2006 page 103 of 518 REJ09B0299-0200 Section 7 I/O Ports • P41/TMO0 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_0 and the P41DDR bit. OS3 to OS0 P41DDR Pin Function 0 P41 input pin All 0 1 P41 output pin TMO0 output pin Not all 0 • P40/TMCI0 The pin function is switched as shown below according to the status of the P40DDR bit. P40DDR Pin Function 0 P40 input pin TMCI0 input pin* Note: * When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin is used as the TMCI0 input pin. 1 P40 output pin 7.6 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O pin. P52 and ExSCK1 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) 7.6.1 Port 5 Data Direction Register (P5DDR) P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis. Bit 7 to 3 2 1 0 P52DDR P51DDR P50DDR Bit Name Initial Value All 1 R/W Description Reserved The initial value should not be changed. 0 0 0 W W W The corresponding port 5 pins are output ports when P5DDR bits are set to 1, and input ports when cleared to 0. As SCI_1 is initialized in software standby mode, the pin states are determined by the IIC_0 ICCR, P5DDR, and P5DR specifications. Rev. 2.00 Mar 21, 2006 page 104 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.6.2 Port 5 Data Register (P5DR) P5DR stores output data for port 5 pins. Bit 7 to 3 2 1 0 P52DR P51DR P50DR Bit Name Initial Value All 1 R/W Description Reserved The initial value should not be changed. 0 0 0 R/W R/W R/W If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. 7.6.3 Pin Functions • P52/ExSCK1*/SCL0 The pin function is switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR, the C/A bit in SMR of SCI_1, the SPS1 bit* in SPSR, the ICE bit in ICCR of IIC_0, and the P52DDR bit. SPS1* ICE CKE1 C/A CKE0 P52DDR Pin Function 0 P52 input pin 1 P52 SCL0 output I/O pin pin 0 P52 input pin 0 1 P52 ExSCK1* ExSCK1* ExSCK1* SCL0 output output output input I/O pin pin pin pin pin 0 1 0 0 1 0 1 0 1 1 1 0 0 0 Note: * When this pin is used as the SCL0 I/O pin by setting 1 to the SPS1 bit of SPSR, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in SMR must all be cleared to 0. SCL0 is an NMOS open-drain output. When set as the P52 output pin or ExSCK1 output pin, this pin is an NMOS push-pull output. The program development tool (emulator) does not support this function. Rev. 2.00 Mar 21, 2006 page 105 of 518 REJ09B0299-0200 Section 7 I/O Ports • P51/ExRxD1* The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1, the SPS1 bit* in SPSR, and the P51DDR bit. SPS1* RE P51DDR Pin Function 0 P51 input pin 1 P51 output pin 0 P51 input pin 0 0 1 P51 output pin ExRxD1 input pin* 1 1 Note: * The program development tool (emulator) does not support this function. • P50/ExTxD1* The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SPS1 bit* in SPSR, and the P50DDR bit. SPS1* TE P50DDR Pin Function 0 P50 input pin 1 P50 output pin 0 P50 input pin 0 0 1 P50 output pin ExTxD1 output pin* 1 1 Note: * The program development tool (emulator) does not support this function. Rev. 2.00 Mar 21, 2006 page 106 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.7 Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, TMR_X I/O pins, TMR_Y input pin, key-sense interrupt input pins, and interrupt input pins. The port 6 input level can be switched in four stages. Port 6 has the following registers. • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 pull-up MOS control register (KMPCR) • System control register 2 (SYSCR2) 7.7.1 Port 6 Data Direction Register (P6DDR) P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0. Rev. 2.00 Mar 21, 2006 page 107 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.7.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. 7.7.3 Port 6 Pull-Up MOS Control Register (KMPCR) KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The input pull-up MOS is turned on when a KMPCR bit is set to 1 with the input port setting. Rev. 2.00 Mar 21, 2006 page 108 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.7.4 System Control Register 2 (SYSCR2) SYSCR2 controls the port 6 operations. Bit 7 6 Bit Name KWUL1 KWUL0 Initial Value 0 0 R/W R/W R/W Description Key wakeup levels 1 and 0 Sets the input level of port 6. The input level of pins functioning as port 6 is also changed. 00: Standard input level 01: Input level 1 10: Input level 2 11: Input level 3 5 P6PUE 0 R/W Port 6 input pull-up MOS extra Selects the power specifications of the input pullup MOS for port 6. 0: Standard power specifications 1: Restricted power specifications 4 3 to 1 0 HI12E 0 All 0 0 R/W R/W R/W Reserved The initial value should not be changed. Reserved The initial value should not be changed. Host interface enabled The initial value should not be changed. Rev. 2.00 Mar 21, 2006 page 109 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.7.5 Pin Functions • P67/TMOX/KIN7/IRQ7 The pin function is switched as shown below according to the combination of the OS3 to OS0 2 bits in TCSR of TMR_X, the OSX bit* in TCRXY, and the P67DDR bit. 2 OSX* 0 All 0 0 P67 input pin 1 P67 output pin Not all 0 0 1 OS3 to OS0 P67DDR Pin Function 1 P67 output pin TMOX output P67 input pin pin 1 IRQ7 input pin, KIN7 input pin* Notes: 1. This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER. It can always be used as the KIN7 input pin. 2. The program development tool (emulator) does not support this function. • P66/FTOB/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit. OEB P66DDR Pin Function 0 P66 input pin 0 1 P66 output pin IRQ6 input pin, KIN6 input pin* Note: * This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 input pin. FTOB output pin 1 • P65/FTID/KIN5 P65DDR Pin Function 0 P65 input pin X P65 output pin FTID input pin, KIN5 input pin* Note: * This pin can always be used as the FTID or KIN5 input pin. Rev. 2.00 Mar 21, 2006 page 110 of 518 REJ09B0299-0200 Section 7 I/O Ports • P64/FTIC/KIN4 The pin function is switched as shown below according to the status of the P64DDR bit. P64DDR Pin Function 0 P64 input pin FTIC input pin, KIN4 input pin* Note: * This pin can always be used as the FTIC or KIN4 input pin. 1 P64 output pin • P63/FTIB/KIN3 P63DDR Pin Function 0 P63 input pin 1 P63 output pin FTIB input pin, KIN3 input pin* Note: * This pin can always be used as the FTIB or KIN3 input pin. • P62/FTIA/KIN2/TMIY P62DDR Pin Function 0 P62 input pin 1 P62 output pin FTIA input pin, TMIY input pin, KIN2 input pin* Note: * This pin can always be used as the FTIA, TMIY, or KIN2 input pin. • P61/FTOA/KIN1 The pin function is switched as shown below according to the combination of the OEA bit in TOCR of the FRT, and the P61DDR bit. OEA P61DDR Pin Function 0 P61 input pin 0 1 P61 output pin KIN1 input pin* Note: * This pin can always be used as the KIN1 input pin. FTOA input pin 1 • P60/FTCI/KIN0/TMIX P60DDR Pin Function 0 P60 input pin 1 P60 output pin FTCI input pin, TMIX input pin, KIN0 input pin* Note: * This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the TMIX or KIN0 input pin. Rev. 2.00 Mar 21, 2006 page 111 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.7.6 Port 6 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 7.5 summarizes the input pull-up MOS states. Table 7.5 Reset Off Input Pull-Up MOS States (Port 6) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P6DDR = 0, and KMPCR = 1; otherwise off. 7.8 Port 7 1 Port 7 is an 8-bit I/O port* . Port 7 pins also function as the TMR_X extended output pins 2 2 (ExTMOX)* and TMR_Y output pins (TMOY)* . Port 7 has the following registers. • Port 7 input data register (P7PIN) • Port 7 data direction register (P7DDR)* 2 • Port 7 output data register (P7ODR)* 2 Notes: 1. The program development tool (emulator) does not support the output. 2. The program development tool (emulator) does not support this function. Rev. 2.00 Mar 21, 2006 page 112 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.8.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit 7 6 5 4 3 2 1 0 Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a P7PIN read is performed, the pin states are always read. P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR and the port B setting will be changed. Note: * Determined by the pin states of P77 to P70. 7.8.2 Port 7 Data Direction Register (P7DDR) P7DDR specifies input or output for the pins of port 7 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 7 pins are output ports when P7DDR bits are set to 1, and input ports when P7DDR bits are cleared to 0. Note: The program development tool (emulator) does not support this register. Rev. 2.00 Mar 21, 2006 page 113 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.8.3 Port 7 Output Data Register (P7ODR) P7ODR stores output for the pins of port 7. Bit 7 6 5 4 3 2 1 0 Bit Name P77ODR P76ODR P75ODR P74ODR P73ODR P72ODR P71ODR P70ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P7ODR can always be read or written to, regardless of the contents of P7DDR. Note: The program development tool (emulator) does not support this register. 7.8.4 Pin Functions • P77/ExTMOX* The pin function is switched as shown below according to the combination of the OSX bit* in TCRXY of TMR_X, OS3 to OS0 bits, and P77DDR*. OSX* OS3 to OS0 P77DDR* Pin Function 0 All 0 0 P77 input pin 1 P77 output pin* 0 P77 input pin 1 P77 output pin* ExTMOX output pin* 1 Not all 0 Note: * The program development tool (emulator) does not support this function. • P76/TMOY* The pin function is switched as shown below according to the combination of the OEY bit* in TCRXY of TMR_X, OS3 to OS0 bits, and P76DDR*. OEY* OS3 to OS0 P76DDR* Pin Function 0 All 0 0 P76 input pin 1 P76 output pin* 0 P76 input pin 1 P76 output pin* TMOY output pin* 1 Not all 0 Note: * The program development tool (emulator) does not support this function. Rev. 2.00 Mar 21, 2006 page 114 of 518 REJ09B0299-0200 Section 7 I/O Ports • P75 to P70 The pin function is switched as shown below according to the status of P7nDDR*. P7nDDR* Pin Function 0 P7n input pin 1 P7n output pin* Note: * The program development tool (emulator) does not support this function. (n = 5 to 0) 7.9 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pin, LPC I/O pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The output type of SCL1 is NMOS open-drain output and direct bus driving is enabled. Port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) 7.9.1 Port 8 Data Direction Register (P8DDR) P8DDR specifies input or output for the pins of port 8 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Bit Name Initial Value 1 0 0 0 0 0 0 0 W W W W W W W R/W Description Reserved The initial value should not be changed. P8DDR has the same address as PBPIN, and if read, the port B state will be returned. The corresponding port 8 pins are output ports when P8DDR bits are set to 1, and input ports when cleared to 0. Rev. 2.00 Mar 21, 2006 page 115 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.9.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins (P86 to P80). Bit 7 6 5 4 3 2 1 0 P86DR P85DR P84DR P83DR P82DR P81DR P80DR Bit Name Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read. 7.9.3 Pin Functions • P86/IRQ5/ SCK1/SCL1 The pin function is switched as shown below according to the combination of the CKE1 and 2 CKE0 bits in SCR of SCI_1, the C/A bit in SMR of SCI_1, the SPS1 bit* in SPSR, the ICE bit in ICCR of IIC_1, and the P86DDR bit. SPS1* ICE CKE1 C/A CKE0 P86DDR Pin Function 0 0 1 SCK1 output pin 0 1 0 1 2 0 0 1 1 0 0 0 0 0 1 1 1 SCL1 I/O pin P86 P86 input pin output pin SCK1 SCK1 SCL1 P86 P86 output input pin I/O pin input pin output pin pin *1 IRQ5 input pin Notes: 1. When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in SMR of SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin are set, the output type is NMOS push-pull output. SCL1 is an NMOS-only output, and has direct bus drive capability. 2. The program development tool (emulator) does not support this function. Rev. 2.00 Mar 21, 2006 page 116 of 518 REJ09B0299-0200 Section 7 I/O Ports • P85/IRQ4/RxD1 The pin function is switched as shown below according to the combination of the RE bit in 2 SCR of SCI_1, the SPS1 bit* in SPSR, and the P85DDR bit. SPS1* RE P85DDR Pin Function 0 P85 input pin 2 0 0 1 P85 output pin RxD1 input pin IRQ4 input pin* 1 1 1 0 P85 input pin 1 P85 output pin Notes: 1. When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin. 2. The program development tool (emulator) does not support this function. • P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in 2 SCR of SCI_1, the SPS1 bit* in SPSR, and the P84DDR bit. SPS1* TE P84DDR Pin Function 0 P84 input pin 2 0 0 1 P84 output pin TxD1 output pin IRQ3 input pin* 1 1 1 0 P84 input pin 1 P84 output pin Notes: 1. When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 2. The program development tool (emulator) does not support this function. • P83/LPCPD The pin function is switched as shown below according to the status of the P83DDR bit. P83DDR Pin Function 0 P83 input pin LPCPD input pin* Note: * When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, this pin is used as the LPCPD input pin. 1 P83 output pin Rev. 2.00 Mar 21, 2006 page 117 of 518 REJ09B0299-0200 Section 7 I/O Ports • P82/CLKRUN The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPC3E to LPC1E HI12E P82DDR Pin Function 0 P82 input pin All 0 0 1 P82 output pin Not all 0 0* 0* CLKRUN I/O pin Note: * When at least one of bits LPC3E to LPC1E is set to 1, bits HI12E and P82DDR should be cleared to 0. • P81/GA20 The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the FGA20E bit in HICR0, and the P81DDR bit. FGA20E HI12E P81DDR Pin Function 0 P81 input pin 0 0 1 P81 output pin GA20 input pin Note: * When bit FGA20E is set to 1 in HICR0, bits HI12E and P81DDR should be cleared to 0. 1 0* 0* GA20 output pin • P80/PME The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the PMEE bit in HICR0, and the P80DDR bit. PMEE HI12E P80DDR Pin Function 0 P80 input pin 0 0 1 P80 output pin PME input pin Note: * When bit PMEE is set to 1 in HICR0, bits HI12E and P80DDR should be cleared to 0. 1 0* 0* PME output pin Rev. 2.00 Mar 21, 2006 page 118 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.10 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin, subclock input pin, and system clock (φ) output pin. P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following registers. • Port 9 data direction register (P9DDR) • Port 9 data register (P9DR) 7.10.1 Port 9 Data Direction Register (P9DDR) P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Rev. 2.00 Mar 21, 2006 page 119 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.10.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read. For P96, the pin state is always read. Note: * The initial value of bit 6 is determined according to the P96 pin state. 7.10.3 Pin Functions • P97/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P97DDR bit. ICE P97DDR Pin Function 0 P97 input pin 0 1 P97 output pin SDA0 I/O pin 1 Note: * When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. • P96/φ/EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR EXCLE Pin Function 0 P96 input pin 0 1 EXCL input pin 1 0 φ output pin Note: * When this pin is used as the EXCL input pin, P96DDR should be cleared to 0. Rev. 2.00 Mar 21, 2006 page 120 of 518 REJ09B0299-0200 Section 7 I/O Ports • P95 The pin function is switched as shown below according to the status of the P95DDR bit. P95DDR Pin Function 0 P95 input pin 1 P95 output pin • P94 The pin function is switched as shown below according to the status of the P94DDR bit. P94DDR Pin Function 0 P94 input pin 1 P94 output pin • P93 The pin function is switched as shown below according to the status of the P93DDR bit. P93DDR Pin Function 0 P93 input pin 1 P93 output pin • P92/IRQ0 The pin function is switched as shown below according to the status of the P92DDR bit. P92DDR Pin Function 0 P92 input pin IRQ0 input pin* Note: * When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. 1 P92 output pin • P91/IRQ1 The pin function is switched as shown below according to the status of the P91DDR bit. P91DDR Pin Function 0 P91 input pin IRQ1 input pin* Note: * When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin. 1 P91 output pin Rev. 2.00 Mar 21, 2006 page 121 of 518 REJ09B0299-0200 Section 7 I/O Ports • P90/IRQ2 The pin function is switched as shown below according to the status of the P90DDR bit. P90DDR Pin Function 0 P90 input pin IRQ2 input pin* Note: * When the IRQ2E bit in IER is set to 1, this pin is used as the IRQ2 input pin. 1 P90 output pin 7.11 Port A Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and key-sense interrupt input pins. Port A input/output operates by VccB power independent from the Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the following registers. PADDR and PAPIN have the same address. • Port A data direction register (PADDR) • Port A output data register (PAODR) • Port A input data register (PAPIN) 7.11.1 Port A Data Direction Register (PADDR) PADDR specifies input or output for the pins of port A on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port A pins are output ports when PADDR bits are set to 1, and input ports when cleared to 0. PA7 to PA2 pins are used as the keyboard buffer controller I/O pins by setting the KBIOE bit to 1, while the I/O direction according to PA7DDR to PA2DDR is ignored. PADDR has the same address as PAPIN, if read, port A status is returned. Rev. 2.00 Mar 21, 2006 page 122 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.11.2 Port A Output Data Register (PAODR) PAODR stores output data for port A. Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR can always be read or written to, regardless of the contents of PADDR. 7.11.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit 7 6 5 4 3 2 1 0 Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PAPIN always returns the pin states. PAPIN has the same address as PADDR. If a write is performed, the port A settings will change. Note: * The initial value is determined according to the PA7 to PA0 pin states. Rev. 2.00 Mar 21, 2006 page 123 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.11.4 Pin Functions • PA7/KIN15/PS2CD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_2 of the keyboard buffer controller, and the PA7DDR bit. KBIOE PA7DDR Pin Function 0 PA7 input pin 0 1 PS2CD output pin KIN15 input pin, PS2CD input pin* PA7 output pin 1 Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2CD or KIN15 input pin. • PA6/KIN14/PS2CC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_2 of the keyboard buffer controller, and the PA6DDR bit. KBIOE PA6DDR Pin Function 0 PA6 input pin 0 1 PS2CC output pin KIN14 input pin, PS2CC input pin* PA6 output pin 1 Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2CC or KIN14 input pin. • PA5/KIN13/PS2BD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA5DDR bit. KBIOE PA5DDR Pin Function 0 PA5 input pin 0 1 PA5 output pin PS2BD output pin KIN13 input pin, PS2BD input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2BD or KIN13 input pin. 1 Rev. 2.00 Mar 21, 2006 page 124 of 518 REJ09B0299-0200 Section 7 I/O Ports • PA4/KIN12/PS2BC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA4DDR bit. KBIOE PA4DDR Pin Function 0 PA4 input pin 0 1 PA4 output pin PS2BC output pin KIN12 input pin, PS2BC input pin* Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2BC or KIN12 input pin. 1 • PA3/KIN11/PS2AD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_0 of the keyboard buffer controller, and the PA3DDR bit. KBIOE PA3DDR Pin Function 0 PA3 input pin 0 1 PA3 output pin PS2AD output pin KIN11 input pin, PS2AD input pin* Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2AD or KIN11 input pin. 1 • PA2/KIN10/PS2AC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_0 of the keyboard buffer controller, and the PA2DDR bit. KBIOE PA2DDR Pin Function 0 PA2 input pin 0 1 PA2 output pin PS2AC output pin KIN10 input pin, PS2AC input pin* Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2AC or KIN10 input pin. 1 Rev. 2.00 Mar 21, 2006 page 125 of 518 REJ09B0299-0200 Section 7 I/O Ports • PA1/KIN9, PA0/KIN8 The pin function is switched as shown below according to the status of the PAnDDR bit. PAnDDR Pin Function 0 PAn input pin KINm input pin* Note: * This pin can always be used as the KINm input pin. (n = 1 or 0, m = 9 or 8) 1 PAn output pin 7.11.5 Port A Input Pull-Up MOS Port A has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS for pins PA7 to PA4 is always off when IICS is set to 1. When the keyboard buffer control pin function is selected for pins PA7 to PA2, the input pull-up MOS is always off. Table 7.6 summarizes the input pull-up MOS states. Table 7.6 Reset Off Input Pull-Up MOS States (Port A) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PADDR = 0, and PAODR = 1; otherwise off. Rev. 2.00 Mar 21, 2006 page 126 of 518 REJ09B0299-0200 Section 7 I/O Ports 7.12 Port B Port B is an 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event interrupt input pins function. Port B has the following registers. • Port B data direction register (PBDDR) • Port B output data register (PBODR) • Port B input data register (PBPIN) 7.12.1 Port B Data Direction Register (PBDDR) PBDDR specifies input or output for the pins of port B on a bit-by-bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be returned. A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. 7.12.2 Port B Output Data Register (PBODR) PBODR stores output data for port B. Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 2.00 Mar 21, 2006 page 127 of 518 REJ09B0299-0200 Description PBODR can always be read or written to, regardless of the contents of PBDDR. Section 7 I/O Ports 7.12.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Bit 7 6 5 4 3 2 1 0 Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change. Note: * The initial value is determined according to the PB7 to PB0 pin states. 7.12.4 Pin Functions • PB7/WUE7, PB6/WUE6, PB5/WUE5, PB4/WUE4, PB3/WUE3, PB2/WUE2 The pin function is switched as shown below according to the status of the PBnDDR bit. PBnDDR Pin Function 0 PBn input pin WUEn input pin* Note: * This pin can always be used as the WUEn input pin. (n = 7 to 2) 1 PBn output pin • PB1/WUE1/LSCI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LSCIE bits in HICR0 of host interface (LPC), and the PB1DDR bit. LSCIE HI12E PB1DDR Pin Function 0 PB1input pin 0 0 1 1 1 0* 0* 1 PB1 output pin LSCI output pin *2, LSCI input pin*2 WUE1 input pin Notes: 1. When bit LSCIE is set to 1 in HICR0, bits HI12E and PB1DDR should be cleared to 0. 2. This pin can always be used as the WUE1 or LSCI input pin. Rev. 2.00 Mar 21, 2006 page 128 of 518 REJ09B0299-0200 Section 7 I/O Ports • PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the HI12E bit in SYSCR2, the LSMIE bits in HICR0 of host interface (LPC), and the PB0DDR bit. LSMIE HI12E PB0DDR Pin Function 0 PB0 input pin 0 0 1 PB0 output pin WUE0 input pin* , LSMI input pin* 2 2 1 1 0* 0* 1 LSMI output pin Notes: 1. When bit LSMIE is set to 1 in HICR0, bits HI12E and PB0DDR should be cleared to 0. 2. This pin can always be used as the WUE0 or LSMI input pin. 7.12.5 Port B Input Pull-Up MOS Port B has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 7.7 summarizes the input pull-up MOS states. Table 7.7 Reset Off Input Pull-Up MOS States (Port B) Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off Legend: Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PBDDR = 0, and PBODR = 1; otherwise off. Rev. 2.00 Mar 21, 2006 page 129 of 518 REJ09B0299-0200 Section 7 I/O Ports Rev. 2.00 Mar 21, 2006 page 130 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) Section 8 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 8.1 Features • Division of pulse into multiple base cycles to reduce ripple • Two resolution settings The resolution can be set equal to one or two system clock cycles. • Two base cycle settings The base cycle can be set equal to T × 64 or T × 256, where T is the resolution. • Four operating speeds • Four operation clocks (by combination of two resolution settings and two base cycle settings) Figure 8.1 shows a block diagram of the PWM (D/A) module. Internal clock φ φ/2 Select clock Clock Base cycle compare match A PWX0 PWX1 Fine–adjustment pulse addition A Internal data bus Bus interface Comparator A Comparator B DADRA DADRB Base cycle compare match B Fine–adjustment pulse addition B Control logic Base cycle overflow DACNT DACR Module data bus Legend: DACR : PWM D/A control register DADRA : PWM D/A data register A DADRB : PWM D/A data register B DACNT : PWM D/A counter Figure 8.1 PWM (D/A) Block Diagram DTCH80BA_010020020900 Rev. 2.00 Mar 21, 2006 page 131 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.2 Input/Output Pins Table 8.1 lists the PWM (D/A) module input and output pins. Table 8.1 Name PWM output pin X0 PWM output pin X1 Pin Configuration Abbreviation I/O PWX0 PWX1 Output Output Function PWM output of PWMX channel A PWM output of PWMX channel B 8.3 Register Descriptions The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). • PWM (D/A) counter H (DACNTH) • PWM (D/A) counter L (DACNTL) • PWM (D/A) data register AH (DADRAH) • PWM (D/A) data register AL (DADRAL) • PWM (D/A) data register BH (DADRBH) • PWM (D/A) data register BL (DADRBL) • PWM (D/A) control register (DACR) Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. Rev. 2.00 Mar 21, 2006 page 132 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of 16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details, refer to section 8.4, Bus Master Interface. DACNTH Bit (CPU) Bit (Counter) : : 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 0 REGS • DACNTH Bit 7 to 0 Bit Name UC7 to UC0 Initial Value All 0 R/W R/W Description Upper Up-Counter • DACNTL Bit 7 to 2 1 0 Bit Name UC8 to UC13 — REGS Initial Value All 0 R/W R/W Description Lower Up-Counter 1 1 R R/W Reserved This bit is always read as 1 and cannot be modified. Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Rev. 2.00 Mar 21, 2006 page 133 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register (TEMP). For details, refer to section 8.4, Bus Master Interface. • DADRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) × 256 DADR range = H'0103 to H'FFFF 0 — 1 R Reserved This bit is always read as 1 and cannot be modified. Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT. Rev. 2.00 Mar 21, 2006 page 134 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) • DADRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) × 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) × 256 DADR range = H'0103 to H'FFFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT. Rev. 2.00 Mar 21, 2006 page 135 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.3.3 PWM (D/A) Control Register (DACR) DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed. Bit 7 Bit Name TEST Initial Value 0 R/W R/W Description Test Mode Selects test mode, which is used in testing this LSI. Normally this bit should be cleared to 0. 0: PWM (D/A) in user state: Normal operation 1: PWM (D/A) in test state: Correct conversion results unobtainable 6 PWME 0 R/W PWM Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 — 3 OEB All 1 0 R R/W Reserved These bits are always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWM (D/A) channel B. 0: PWM (D/A) channel B output (at the PWX1 pin) is disabled 1: PWM (D/A) channel B output (at the PWX1 pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWM (D/A) channel A. 0: PWM (D/A) channel A output (at the PWX0 pin) is disabled 1: PWM (D/A) channel A output (at the PWX0 pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWM (D/A) output. 0: Direct PWM (D/A) output 1: Inverted PWM (D/A) output 0 CKS 0 R/W Clock Select Selects the PWM (D/A) resolution. If the system clock (φ) frequency is 10 MHz, resolutions of 100 ns and 200 ns, can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) × 2 Rev. 2.00 Mar 21, 2006 page 136 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. Write: When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. Read: When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Table 8.2 Read and Write Access Methods for 16-Bit Registers Read Write Word Yes Yes Byte × × Register Name DADRA and DADRB DACNT Word Yes Yes Byte Yes × Legend: Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). ×: This type of access may give incorrect results. Rev. 2.00 Mar 21, 2006 page 137 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.5 Operation A PWM waveform like the one shown in figure 8.2 is output from the PWX pin. The value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 8.3 and 8.4 show the types of waveform output available. 1 conversion cycle (T × 214 (= 16384)) tf Base cycle (T × 64 or T × 256) tL T: Resolution TL = ∑ tLn (OS = 0) n=1 m (When CFS = 0, m = 256 When CFS = 1, m = 64) Figure 8.2 PWM (D/A) Operation Rev. 2.00 Mar 21, 2006 page 138 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) Table 8.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Table 8.3 Settings and Operation (Examples When φ = 10 MHz) Fixed DADR Bits Resolu Base Conversion TL (if OS = 0) CKS tion T (µs) CFS Cycle (µs) Cycle (µs) TH (if OS = 1) 0 0.1 0 6.4 1638.4 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) × T (DADR = H'0401 to H'FFFD) 1 25.6 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) × T (DADR = H'0103 to H'FFFF) 1 0.2 0 12.8 3276.8 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) × T (DADR = H'0401 to H'FFFD) 1 51.2 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) × T (DADR = H'0103 to H'FFFF) 14 12 10 3276.8 0 0 819.2 0 0 0 0 204.8 10 0 0 0 0 204.8 14 12 3276.8 0 0 819.2 10 0 0 0 0 102.4 14 12 1638.4 0 0 409.6 10 0 0 0 0 102.4 Bit Data Accuracy Conversion 3 2 1 0 Cycle* (µs) (Bits) 14 12 1638.4 0 0 409.6 Note: * This column indicates the conversion cycle when specific DADR bits are fixed. Rev. 2.00 Mar 21, 2006 page 139 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) × 256] Figure 8.3 Output Waveform (OS = 0, DADR Corresponds to TL) Rev. 2.00 Mar 21, 2006 page 140 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) × 256] Figure 8.4 Output Waveform (OS = 1, DADR Corresponds to TH) An example of setting CFS to 1 (basic cycle = resolution (T) × 256) and OS to 1 (PWMX inverted output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional pulse is determined by the following six bits (DA5 to DA0) as shown in figure 8.5. Tables 8.4 to 8.6 show the position of the additional pulse. DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Basic pulse duty ratio Additional pulse position Figure 8.5 D/A Data Register Configuration when CFS = 1 Here, the case of DADR = H'0207 (B'0000 0010 0000 0111) is considered. Figure 8.6 shows an output waveform. Because CFS = 1 and the value of upper eight bits is B'0000 0010, the duty ratio of the basic pulse is 2/256 × (T) of high width. Rev. 2.00 Mar 21, 2006 page 141 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) Since the value of the following six bits is B'0000 01, the additional pulse is output at the position of basic pulse No. 63 as shown in table 8.4. Only 1/256 × (T) of the additional pulse is added to the basic pulse. One conversion cycle Basic cycle No.0 Basic cycle No.1 Basic cycle No.63 Basic pulse High width: 2/256 × (T) Additional pulse output position Basic pulse 2/256 × (T) Additional pulse 1/256 × (T) Figure 8.6 Output Waveform when DADR = H'0207 (OS = 1) Note that the case of CFS = 0 (basic cycle = resolution (T) × 64) is similar other than the duty ratio of the basic pulse is determined by the upper six bits, and the position of the additional pulse is determined by the following eight bits. Rev. 2.00 Mar 21, 2006 page 142 of 518 REJ09B0299-0200 Table 8.4 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 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1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 1 2 3 4 5 6 7 8 Basic Pulse No. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Position of Pulse to Be Added to Basic Pulse with 14-Bit Conversion Accuracy (CFS = 1) Section 8 14-Bit PWM Timer (PWMX) Rev. 2.00 Mar 21, 2006 page 143 of 518 REJ09B0299-0200 Table 8.5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYesYes Yes Yes Yes Yes Yes YesYes Yes YesYesYes Yes Yes Yes Yes YesYes Yes YesYesYes Yes YesYes Yes Yes YesYes Yes YesYesYes Yes YesYes YesYes Yes YesYes Yes Yes YesYes YesYesYesYes YesYes Yes Yes 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No. 23456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Section 8 14-Bit PWM Timer (PWMX) Rev. 2.00 Mar 21, 2006 page 144 of 518 REJ09B0299-0200 Lower 6 bits 0000 0010 0100 0110 1000 1010 1100 1110 0000 0010 0100 0110 1000 1010 1100 1110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYesYes YesYes Yes Yes Yes Yes Yes YesYesYes YesYes Yes Yes Yes Yes YesYes YesYesYes YesYes Yes Yes Yes Yes Yes YesYes YesYesYes YesYes Yes Yes Yes Yes Yes YesYes YesYesYesYes Yes Yes YesYes YesYes Yes Yes YesYes YesYesYesYes Yes Yes YesYes YesYes YesYesYes YesYes YesYesYesYes Position of Pulse to Be Added to Basic Pulse with 12-Bit Conversion Accuracy (CFS = 1) 0 1 Basic Pulse No. 23456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Table 8.6 0 0 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesYesYes Yes Yes Yes Yes Yes YesYes Yes Yes Yes YesYes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Lower 6 bits 0000 1000 0000 1000 00 0 16 0 32 0 48 Yes Yes Yes Yes Yes Yes Position of Pulse to Be Added to Basic Pulse with 10-Bit Conversion Accuracy (CFS = 1) Section 8 14-Bit PWM Timer (PWMX) Rev. 2.00 Mar 21, 2006 page 145 of 518 REJ09B0299-0200 Section 8 14-Bit PWM Timer (PWMX) 8.6 8.6.1 Usage Note Module Stop Mode Setting PWMX operation can be enabled or disabled using the module stop control register. The initial setting is for PWMX operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 146 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Section 9 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 9.1 Features • Selection of four clock sources One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be selected (enabling use as an external event counter). • Two independent comparators Two independent waveforms can be output. • Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. • Counter clearing The free-running counters can be cleared on compare-match A. • Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. • Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling input capture operations in this interval to be restricted. TIM8FR1A_010020020800 Rev. 2.00 Mar 21, 2006 page 147 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Figure 9.1 shows a block diagram of the FRT. External clock Internal clock FTCI Clock selector φ/2 φ/8 φ/32 Clock OCRAR/F (H/L) OCRA (H/L) Compare-match A Bus interface FTOA FTOB FTIA FTIB FTIC FTID Input capture Overflow Module data bus Comparator A Internal data bus FRC (H/L) Clear Compare-match B Control logic Comparator B OCRB (H/L) ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L) Comparator M Compare-match M ×1 ×2 OCRDM L TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt signal Legend: OCRA, OCRB : Output compare register A, B (16-bit) OCRAR,OCRAF : Output compare register AR, AF (16-bit) OCRDM : Output compare register DM (16-bit) FRC : Free-running counter (16-bit) ICRA to D : Input capture registers A to D (16-bit) TCSR : Timer control/status register (8-bit) TIER : Timer interrupt enable register (8-bit) TCR : Timer control register (8-bit) TOCR : Timer output compare control register (8-bit) Figure 9.1 Block Diagram of 16-Bit Free-Running Timer Rev. 2.00 Mar 21, 2006 page 148 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.2 Input/Output Pins Table 9.1 lists the FRT input and output pins. Table 9.1 Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Pin Configuration Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input 9.3 Register Descriptions The FRT has the following registers. • Free-running counter (FRC) • Output compare register A (OCRA) • Output compare register B (OCRB) • Input capture register A (ICRA) • Input capture register B (ICRB) • Input capture register C (ICRC) • Input capture register D (ICRD) • Output compare register AR (OCRAR) • Output compare register AF (OCRAF) • Output compare register DM (OCRDM) • Timer interrupt enable register (TIER) • Timer control/status register (TCSR) • Timer control register (TCR) • Timer output compare control register (TOCR) Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA to ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR. Rev. 2.00 Mar 21, 2006 page 149 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 9.3.2 Output Compare Registers A and B (OCRA, OCRB) The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 9.3.3 Input Capture Registers A to D (ICRA to ICRD) The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (φ) for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (φ). ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. Rev. 2.00 Mar 21, 2006 page 150 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 9.3.5 Output Compare Register DM (OCRDM) OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000. Rev. 2.00 Mar 21, 2006 page 151 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled Rev. 2.00 Mar 21, 2006 page 152 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Bit 2 Bit Name OCIBE Initial Value 0 R/W R/W Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled 0 — 1 R Reserved This bit is always read as 1 and cannot be modified. 9.3.7 Timer Control/Status Register (TCSR) TCSR is used for counter clear selection and control of interrupt request signals. Bit 7 Bit Name ICFA Initial Value 0 R/W Description R/(W)* Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA Rev. 2.00 Mar 21, 2006 page 153 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Bit 6 Bit Name ICFB Initial Value 0 R/W Description R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICRB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFB when ICFB = 1, then write 0 to ICFB 5 ICFC 0 R/(W)* Input Capture Flag C This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC 4 ICFD 0 R/(W)* Input Capture Flag D This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD Rev. 2.00 Mar 21, 2006 page 154 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Bit 3 Bit Name OCFA Initial Value 0 R/W Description R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB 1 OVF 0 R/(W)* Timer Overflow This status flag indicates that the FRC has overflowed. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF 0 CCLRA 0 R/W Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A Note: * Only 0 can be written to clear the flag. Rev. 2.00 Mar 21, 2006 page 155 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB Rev. 2.00 Mar 21, 2006 page 156 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W Description Clock Select 1, 0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 9.3.9 Timer Output Compare Control Register (TOCR) TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C. Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected Rev. 2.00 Mar 21, 2006 page 157 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Bit 4 Bit Name OCRS Initial Value 0 R/W R/W Description Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled 2 OEB 0 R/W Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled 1 OLVLA 0 R/W Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A 0 OLVLB 0 R/W Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B Rev. 2.00 Mar 21, 2006 page 158 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.4 9.4.1 Operation Pulse Output Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 9.2 Example of Pulse Output 9.5 9.5.1 Operation Timing FRC Increment Timing Figure 9.3 shows the FRC increment timing with an internal clock source. Figure 9.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ). φ Internal clock FRC input clock FRC N–1 N N+1 Figure 9.3 Increment Timing with Internal Clock Source Rev. 2.00 Mar 21, 2006 page 159 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) φ External clock input pin FRC input clock FRC N N+1 Figure 9.4 Increment Timing with External Clock Source 9.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 9.5 shows the timing of this operation for compare-match A. φ FRC N N+1 N N+1 OCRA N N Compare-match A signal Clear* OLVLA Output compare A output pin FTOA Note : * Indicates instruction execution by software. Figure 9.5 Timing of Output Compare A Output Rev. 2.00 Mar 21, 2006 page 160 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.5.3 FRC Clear Timing FRC can be cleared when compare-match A occurs. Figure 9.6 shows the timing of this operation. φ Compare-match A signal FRC N H'0000 Figure 9.6 Clearing of FRC by Compare-Match A Signal 9.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is selected. φ Input capture input pin Input capture signal Figure 9.7 Input Capture Input Signal Timing (Usual Case) Rev. 2.00 Mar 21, 2006 page 161 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (φ). Figure 9.8 shows the timing for this case. Read cycle of ICRA to ICRD T1 φ T2 Input capture input pin Input capture signal Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD Are Read) 9.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. φ FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 9.9 Buffered Input Capture Timing Rev. 2.00 Mar 21, 2006 page 162 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (φ). Figure 9.10 shows the timing when BUFEA = 1. CPU read cycle of ICRA or ICRC T1 φ T2 FTIA Input capture signal Figure 9.10 Buffered Input Capture Timing (BUFEA = 1) 9.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag. φ Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting Rev. 2.00 Mar 21, 2006 page 163 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 9.12 shows the timing of setting the OCFA or OCFB flag. φ FRC N N+1 OCRA, OCRB N Compare-match signal OCFA, OCFB Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 9.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 9.13 shows the timing of setting the OVF flag. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 9.13 Timing of Overflow Flag (OVF) Setting Rev. 2.00 Mar 21, 2006 page 164 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 9.14 shows the OCRA write timing. φ FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 9.14 OCRA Automatic Addition Timing 9.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask signal. Figure 9.16 shows the timing of clearing the mask signal. φ Input capture signal Input capture mask signal Figure 9.15 Timing of Input Capture Mask Signal Setting Rev. 2.00 Mar 21, 2006 page 165 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) φ FRC N N+1 ICRD + OCRDM × 2 N Compare-match signal Input capture mask signal Figure 9.16 Timing of Input Capture Mask Signal Clearing 9.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts. Table 9.2 Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI FRT Interrupt Sources Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag ICFA ICFB ICFC ICFD OCFA OCFB OVF Low Priority High Rev. 2.00 Mar 21, 2006 page 166 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.7 9.7.1 Usage Notes Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 9.17 shows the timing for this type of conflict. Write cycle of FRC T1 φ T2 Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 9.17 FRC Write-Clear Conflict Rev. 2.00 Mar 21, 2006 page 167 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 9.18 shows the timing for this type of conflict. Write cycle of FRC T1 φ T2 Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 9.18 FRC Write-Increment Conflict Rev. 2.00 Mar 21, 2006 page 168 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) 9.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 9.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 9.20 shows the timing for this type of conflict. Write cycle of OCR T1 φ T2 Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare-match signal Disabled Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used) Rev. 2.00 Mar 21, 2006 page 169 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Write cycle of OCRAR/OCRAF T1 φ T2 Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Old data New data Compare-match signal Disabled FRC N N+1 OCRA N Automatic addition is not performed because compare-match signals are disabled. Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used) 9.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 9.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also cause FRC to increment. Rev. 2.00 Mar 21, 2006 page 170 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Table 9.3 Switching of Internal Clock and FRC Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Rev. 2.00 Mar 21, 2006 page 171 of 518 REJ09B0299-0200 Section 9 16-Bit Free-Running Timer (FRT) Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low No. 3 FRC Operation Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 9.7.5 Module Stop Mode Setting FRT operation can be enabled or disabled using the module stop control register. The initial setting is for FRT operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 172 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Section 10 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels. 10.1 Features • Selection of clock sources  TMR_0, TMR_1: The counter input clock can be selected from six internal clocks and an external clock 1  TMR_Y, TMR_X: The counter input clock can be selected from six internal clocks* and an external clock • Selection of three ways to clear the counters  The counters can be cleared on compare-match A or compare-match B, or by an external reset signal. • Timer output controlled by two compare-match signals  The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. • Cascading of two channels  Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). 2  Cascading of TMR_Y and TMR_X* Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X as the lower half (16-bit count mode). TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count mode). TIMH265A_000020020800 Rev. 2.00 Mar 21, 2006 page 173 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) • Multiple interrupt sources for each channel  TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, compare-match B, and overflow  TMR_X: One type of interrupt: Input capture Notes: 1. The program development tool (emulator) supports three internal clocks. 2. The program development tool (emulator) does not support this function. Figures 10.1 and 10.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. Rev. 2.00 Mar 21, 2006 page 174 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) External clock sources TMCI0 TMCI1 Internal clock sources TMR_0 φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024 TMR_1 φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048 Clock 1 Clock 0 Clock select TCORA_0 Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 TMRI1 Control logic TCORB_0 TCORB_1 Comparator B_1 TCORA_1 Comparator A_1 TMO0 TMRI0 TCNT_0 TCNT_1 Internal bus TCSR_0 TCSR_1 TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Legend: TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 TCR_1 : Time constant register A_0 : Time constant register B_0 : Timer counter_0 : Timer control/status register_0 : Timer control register_0 TCORA_1 TCORB_1 TCNT_1 TCSR_1 TCR_1 : Time constant register A_1 : Time constant register B_1 : Timer counter_1 : Timer control/status register_1 : Timer control register_1 Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) Rev. 2.00 Mar 21, 2006 page 175 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) External clock sources TMCIY TMCIX Internal clock sources TMR_X φ, φ/2, φ/4, φ/2048*, φ/4096*, φ/8192* TMR_Y φ/4, φ/256, φ/2048, φ/4096*, φ/8192*, φ/16384* Clock X Clock Y Clock select * * Compare-match AX Compare-match AY TCORA_Y TCORA_X Comparator A_Y Comparator A_X Overflow X Overflow Y Clear Y TCNT_Y Clear X TCNT_X TMOY* TMRIY Comparator B_Y Comparator B_X Compare-match BY TCORB_Y Control logic TCORB_X ExTMOX*/TMOX TMRIX Input capture TICRR TICRF TICR Compare-match C Comparator C + TCORC TCSR_Y TCR_Y TISR Interrupt signals CMIAY CMIBY OVIY ICIX Legend: TCORA_Y: Time constant register A_Y TCORB_Y: Time constant register B_Y TCNT_Y: Timer counter_Y TCSR_Y: Timer control/status register_Y TCR_Y: Timer control register_Y TISR: Timer input select register TCSR_X TCR_X TCORA_X: Time constant register A_X TCORB_X: Time constant register B_X TCNT_X: Timer counter_X TCSR_X: Timer control/status register_X TCR_X: Timer control register_X TICR: Input capture register TCORC: Time constant register C TICRR: Input capture register R TICRF: Input capture register F Note: * The program development tool (emulator) does not support this function. Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) Rev. 2.00 Mar 21, 2006 page 176 of 518 REJ09B0299-0200 Internal bus Compare- match BX Section 10 8-Bit Timer (TMR) 10.2 Input/Output Pins Table 10.1 summarizes the input and output pins of the TMR. Table 10.1 Pin Configuration Channel TMR_0 Name Timer output Timer clock input Timer reset input TMR_1 Timer output Timer clock input Timer reset input TMR_Y TMR_Y TMR_X Timer clock/reset input Timer output Timer output Timer clock/reset input Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare-match External clock input for the counter External reset input for the counter External clock input/external reset input for the counter Output controlled by compare-match Output controlled by compare-match External clock input/external reset input for the counter TMIY Input (TMCIY/TMRIY) TMOY* Output TMOX/ ExTMOX* Output TMIX Input (TMCIX/TMRIX) Note: * The program development tool (emulator) does not support this pin. 10.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). TMR_0 • Timer counter_0 (TCNT_0) • Time constant register A_0 (TCORA_0) • Time constant register B_0 (TCORB_0) • Timer control register_0 (TCR_0) • Timer control/status register_0 (TCSR_0) Rev. 2.00 Mar 21, 2006 page 177 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TMR_1 • Timer counter_1 (TCNT_1) • Time constant register A_1 (TCORA_1) • Time constant register B_1 (TCORB_1) • Timer control register_1 (TCR_1) • Timer control/status register_1 (TCSR_1) TMR_Y • Timer counter_Y (TCNT_Y) • Time constant register A_Y (TCORA_Y) • Time constant register B_Y (TCORB_Y) • Timer control register_Y (TCR_Y) • Timer control/status register_Y (TCSR_Y) • Timer input select register (TISR) • Timer connection register S (TCONRS) TMR_X • Timer counter_X (TCNT_X) • Time constant register A_X (TCORA_X) • Time constant register B_X (TCORB_X) • Timer control register_X (TCR_X) • Timer control/status register_X (TCSR_X) • Input capture register (TICR) • Time constant register (TCORC) • Input capture register R (TICRR) • Input capture register F (TICRF) • Timer connection register I (TCONRI) For both TMR_Y and TMR_X • Timer XY control register (TCRXY) Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS. Rev. 2.00 Mar 21, 2006 page 178 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. TCNT_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCNT_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0. 10.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. TCORA_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCORA_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0. 10.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. TCORB_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCORB_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0. Rev. 2.00 Mar 21, 2006 page 179 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0. Bit 7 Bit Name Initial Value R/W CMIEB 0 R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. For TMR_X, a CMIB interrupt does not occur irrespective of the value of this bit. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. For TMR_X, a CMIA interrupt does not occur irrespective of the value of this bit. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. For TMR_X, an OVI interrupt does not occur irrespective of the value of this bit. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1, 0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 10.2. Rev. 2.00 Mar 21, 2006 page 180 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Table 10.2 Clock Input to TCNT and Count Condition (1) TCR Channel CKS2 TMR_0 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 STCR ICKS1 — — — — — — — — — 0 1 0 1 0 1 — ICKS0 — 0 1 0 1 0 1 — — — — — — — — — Description Disables clock input Increments at falling edge of internal clock φ/8 Increments at falling edge of internal clock φ/2 Increments at falling edge of internal clock φ/64 Increments at falling edge of internal clock φ/32 Increments at falling edge of internal clock φ/1024 Increments at falling edge of internal clock φ/256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock φ/8 Increments at falling edge of internal clock φ/2 Increments at falling edge of internal clock φ/64 Increments at falling edge of internal clock φ/128 Increments at falling edge of internal clock φ/1024 Increments at falling edge of internal clock φ/2048 Increments at compare-match A from TCNT_0* Rev. 2.00 Mar 21, 2006 page 181 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TCR Channel CKS2 Common 1 1 1 CKS1 0 1 1 CKS0 1 0 1 STCR ICKS1 — — — ICKS0 — — — Description Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. Table 10.2 Clock Input to TCNT and Count Condition (2) TCR Channel CKS2 TMR_Y 0 0 0 0 1 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 2 TCRXY* CKSX — — — — — — — — — — — — — CKSY 0 0 0 0 0 1 1 1 1 1 — — — Description Disables clock input Increments at φ/4 Increments at φ/256 Increments at φ/2048 Disables clock input Disables clock input Increments at φ/4096 Increments at φ/8192 Increments at φ/16384 Increments at overflow signal from 1 TCNT_X* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock Rev. 2.00 Mar 21, 2006 page 182 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TCR Channel CKS2 TMR_X 0 0 0 0 1 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 2 TCRXY* CKSX 0 0 0 0 0 1 1 1 1 1 — — — CKSY — — — — — — — — — — — — — Description Disables clock input Increments at φ Increments at φ/2 Increments at φ/4 Disables clock input Disables clock input Increments at φ/2048 Increments at φ/4096 Increments at φ/8192 Increments at compare-match A from 1 TCNT_Y* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock Notes: 1. If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. 2. The program development tool (emulator) does not support TCRXY. Selection of the internal clock is only available when CKSX = 0 and CKSY = 0. Rev. 2.00 Mar 21, 2006 page 183 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. TCSR_0 Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA * Timer Overflow Flag R/(W) [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 5 OVF 0 4 ADTE 0 R/W A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Rev. 2.00 Mar 21, 2006 page 184 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Bit 1 0 Bit Name Initial Value R/W OS1 OS0 0 0 R/W R/W Description Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. TCSR_1 Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB * Compare-Match Flag A R/(W) [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA * Timer Overflow Flag R/(W) [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 CMFA 0 5 OVF 0 4 — 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 2.00 Mar 21, 2006 page 185 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Bit 3 2 Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W Description Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. TCSR_X Bit 7 Bit Name Initial Value R/W CMFB 0 Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA Rev. 2.00 Mar 21, 2006 page 186 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Bit 5 Bit Name Initial Value R/W OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF * Input Capture Flag R/(W) [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order. [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF 4 ICF 0 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. Rev. 2.00 Mar 21, 2006 page 187 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TCSR_Y Bit 7 Bit Name Initial Value R/W CMFB 0 Description 1 R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 1 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] 5 OVF 0 Read CMFA when CMFA = 1, then write 0 in CMFA *1 Timer Overflow Flag R/(W) [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICIE 1 R/W Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3, 2 These bits specify how the TMOY pin* output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 2 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Rev. 2.00 Mar 21, 2006 page 188 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Bit 1 0 Bit Name Initial Value R/W OS1 OS0 0 0 R/W R/W Description Output Select 1, 0 2 These bits specify how the TMOY pin* output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Notes: 1. Only 0 can be written, for flag clearing. 2. The program development tool (emulator) does not support this pin. 10.3.6 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. 10.3.7 Input Capture Registers R and F (TICRR and TICRF) TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset input (TMRIX) in that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00. 10.3.8 Timer Input Select Register (TISR) TISR permits or prohibits a signal source of external clock/reset input for the counter. Bit 7 to 1 0 Bit Name Initial Value R/W — All 1 Description R/(W) Reserved The initial value should not be changed. R/W Input Select Selects a timer clock/reset input pin (TMIY) as the signal source of external clock/reset input for the TMR_Y counter. 0: Input is prohibited 1: TMIY (TMCIY/TMRIY) is permitted for input Rev. 2.00 Mar 21, 2006 page 189 of 518 REJ09B0299-0200 IS 0 Section 10 8-Bit Timer (TMR) 10.3.9 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit 7 to 5 4 Bit Name — ICST Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX [Setting condition] When 1 is written in ICST after reading ICST = 0 3 to 0 — All 0 R/W Reserved The initial values should not be modified. 10.3.10 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit 7 Bit Name TMR_X/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 10.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 to 0 — All 0 R/W Reserved The initial values should not be modified. Rev. 2.00 Mar 21, 2006 page 190 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Table 10.3 Registers Accessible by TMR_X/TMR_Y TMRX/Y 0 1 H'FFF0 TMR_X TCR_X TMR_Y TCR_Y H'FFF1 TMR_X TMR_Y H'FFF2 TMR_X TMR_Y H'FFF3 TMR_X TICRF TMR_Y H'FFF4 TMR_X TCNT_X TMR_Y H'FFF5 TMR_X TCORC TMR_Y TISR H'FFF6 TMR_X H'FFF7 TMR_X TCSR_X TICRR TCORA_X TCORB_X TCSR_Y TCORA_Y TCORB_Y TCNT_Y 10.3.11 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock. Bit 7 Bit Name OSX Initial Value 0 R/W R/W Description TMR_X Output Select 0: Output to P67/TMOX 1: Output to P77/ExTMOX 6 OEY 0 R/W TMR_Y Output Enable 0: Output to P76/TMOY is prohibited 1: Output to P76/TMOY is permitted 5 CKSX 0 R/W TMR_X Clock Select For details about selection, see the clock conditions in table 10.2. 4 CKSY 0 R/W TMR_Y Clock Select For details about selection, see the clock conditions in table 10.2. 3 to 0 — All 0 R/W Reserved The initial value should not be changed. Note: * The program development tool (emulator) does not support TCRXY. Rev. 2.00 Mar 21, 2006 page 191 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.4 10.4.1 Operation Pulse Output Figure 10.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 10.3 Pulse Output Example Rev. 2.00 Mar 21, 2006 page 192 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.5 10.5.1 Operation Timing TCNT Count Timing Figure 10.4 shows the TCNT count timing with an internal clock source. Figure 10.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges. The counter will not increment correctly if the pulse width is less than these values. φ Internal clock TCNT input clock TCNT N–1 N N+1 Figure 10.4 Count Timing for Internal Clock Input φ External clock input pin TCNT input clock TCNT N–1 N N+1 Figure 10.5 Count Timing for External Clock Input (Both Edges) Rev. 2.00 Mar 21, 2006 page 193 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 10.6 shows the timing of CMF flag setting. φ TCNT N N+1 TCOR Compare-match signal N CMF Figure 10.6 Timing of CMF Setting at Compare-Match 10.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 10.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. φ Compare-match A signal Timer output pin Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal Rev. 2.00 Mar 21, 2006 page 194 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.8 shows the timing of clearing the counter by a compare-match. φ Compare-match signal TCNT N H'00 Figure 10.8 Timing of Counter Clear by Compare-Match 10.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 10.9 shows the timing of clearing the counter by an external reset input. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 10.9 Timing of Counter Clear by External Reset Input Rev. 2.00 Mar 21, 2006 page 195 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 10.10 shows the timing of OVF flag setting. φ TCNT H'FF H'00 Overflow signal OVF Figure 10.10 Timing of OVF Flag Setting Rev. 2.00 Mar 21, 2006 page 196 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 10.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits. • Setting of compare-match flags  The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.  The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. • Counter clear specification  If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set.  The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. • Pin output  Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions.  Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 10.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each or TMR_0 and TMR_1. Rev. 2.00 Mar 21, 2006 page 197 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 10.7.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X occupying the lower 8 bits. • Setting of compare-match flags  The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs.  The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs. • Counter clear specification  If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at comparematch, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y are also cleared when counter clear by the TMRIY pin has been set.  The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of TCNT_X can be cleared by the counter. • Pin output  Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance with the upper 8-bit compare-match conditions.  Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance with the lower 8-bit compare-match conditions. Note: The program development tool (emulator) does not support 16-bit count mode. 10.7.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1, TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Note: The program development tool (emulator) does not support compare-match count mode. Rev. 2.00 Mar 21, 2006 page 198 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. Input Capture Signal Input Timing: Figure 10.11 shows the timing of the input capture operation. φ TMRIX Input capture signal TCNT_X TICRR TICRF M m n n n+1 n m N N N+1 Figure 10.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock (φ) cycle. Figure 10.12 shows the timing of this operation. Rev. 2.00 Mar 21, 2006 page 199 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TICRR, TICRF read cycle T1 T2 φ TMRIX Input capture signal Figure 10.12 Timing of Input Capture Signal (Input Capture Signal Is Input during TICRR and TICRF Read) Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI of the timer connection. The input capture signal selection is shown in table 10.4. Table 10.4 Input Capture Signal Selection TCONRI Bit 4 ICST 0 1 Description Input capture function not used TMIX pin input selection Rev. 2.00 Mar 21, 2006 page 200 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate an ICIX interrupt. Table 10.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 10.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Channel Name TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY TMR_X ICIX Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Input capture Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF ICF Low Interrupt Priority High 10.9 10.9.1 Usage Notes Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 10.13, clearing takes priority and the counter write is not performed. Rev. 2.00 Mar 21, 2006 page 201 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 10.13 Conflict between TCNT Write and Clear 10.9.2 Conflict between TCNT Write and Count-Up If a count-up occurs during the T2 state of a TCNT write cycle as shown in figure 10.14, the counter write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 10.14 Conflict between TCNT Write and Count-Up Rev. 2.00 Mar 21, 2006 page 202 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 10.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match signal Disabled Figure 10.15 Conflict between TCOR Write and Compare-Match 10.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the operation follows the output status that is defined for compare-match A or B, according to the priority of the timer output shown in table 10.6. Table 10.6 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Rev. 2.00 Mar 21, 2006 page 203 of 518 REJ09B0299-0200 Priority High Section 10 8-Bit Timer (TMR) 10.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 10.7 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 10.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Table 10.7 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low to 1 low level* No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Clock switching from low to 2 high level∗ Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Rev. 2.00 Mar 21, 2006 page 204 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high 3 to low level∗ No. 3 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. Rev. 2.00 Mar 21, 2006 page 205 of 518 REJ09B0299-0200 Section 10 8-Bit Timer (TMR) 10.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 10.9.7 Module Stop Mode Setting TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 206 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 is shown in figure 11.1. 11.1 Features • Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. • Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: • If the counter overflows, an internal reset or an internal NMI interrupt is generated. • When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. Interval Timer Mode: • If the counter overflows, an interval timer interrupt (WOVI) is generated. WDT0102B_000020020800 Rev. 2.00 Mar 21, 2006 page 207 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1 Interrupt control Reset control Overflow Clock Clock selection φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock TCNT_0 TCSR_0 Module bus Bus interface WDT_0 WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Reset control Overflow Clock Clock selection φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal reset signal*1 φSUB/2 φSUB/4 φSUB/8 φSUB/16 φSUB/32 φSUB/64 φSUB/128 φSUB/256 TCNT_1 TCSR_1 Module bus Bus interface WDT_1 Legend: TCSR_0: Timer control/status register_0 TCNT_0: Timer counter_0 TCSR_1: Timer control/status register_1 TCNT_1: Timer counter_1 Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1. Figure 11.1 Block Diagram of WDT Rev. 2.00 Mar 21, 2006 page 208 of 518 REJ09B0299-0200 Internal bus Internal bus Section 11 Watchdog Timer (WDT) 11.2 Input/Output Pins The WDT has the pins listed in table 11.1. Table 11.1 Pin Configuration Name Reset output pin Symbol RESO I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin 11.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, refer to section 11.6.1, Notes on Register Access. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). • Timer counter (TCNT) • Timer control/status register (TCSR) 11.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is cleared to 0. Rev. 2.00 Mar 21, 2006 page 209 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit 7 Bit Name Initial Value R/W OVF 0 1 Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] • • When TCSR is read when OVF = 1* , then 0 is written to OVF 2 When 0 is written to TME 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 3 — 0 R/(W) R/W Reserved The initial value should not be changed. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested RST/NMI 0 Rev. 2.00 Mar 21, 2006 page 210 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) Bit 2 1 0 Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to. The overflow frequency for φ = 10 MHz is enclosed in parentheses. 000: φ/2 (frequency: 51.2 µs) 001: φ/64 (frequency: 1.64 ms) 010: φ/128 (frequency: 3.28 ms) 011: φ/512 (frequency: 13.1 ms) 100: φ/2048 (frequency: 52.4 ms) 101: φ/8192 (frequency: 209.7 ms) 110: φ/32768 (frequency: 0.84 s) 111: φ/131072 (frequency: 3.36 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 2.00 Mar 21, 2006 page 211 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) • TCSR_1 Bit 7 Bit Name Initial Value R/W OVF 0 R/(W)*1 Description Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] • • When TCSR is read when OVF = 1* , then 0 is written to OVF 2 When 0 is written to TME 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. Rev. 2.00 Mar 21, 2006 page 212 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) Bit 4 Bit Name Initial Value R/W PSS 0 R/W Description Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of φ—based prescaler (PSM) 1: Counts the divided cycle of φSUB—based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for φ = 10 MHz and φSUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 51.2 µs) 001: φ/64 (frequency: 1.64 ms) 010: φ/128 (frequency: 3.28 ms) 011: φ/512 (frequency: 13.1 ms) 100: φ/2048 (frequency: 52.4 ms) 101: φ/8192 (frequency: 209.7 ms) 110: φ/32768 (frequency: 0.84 s) 111: φ/131072 (frequency: 3.36 s) When PSS = 1: 000: φSUB/2 (cycle: 15.6 ms) 001: φSUB/4 (cycle: 31.3 ms) 010: φSUB/8 (cycle: 62.5 ms) 011: φSUB/16 (cycle: 125 ms) 100: φSUB/32 (cycle: 250 ms) 101: φSUB/64 (cycle: 500 ms) 110: φSUB/128 (cycle: 1 s) 111: φ/256 (cycle: 2 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 2.00 Mar 21, 2006 page 213 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.4 11.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 11.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. Rev. 2.00 Mar 21, 2006 page 214 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT OVF = 1* RESO and internal reset signals generated Time WT/IT = 1 Write H'00 to TME = 1 TCNT RESO signal 132 system clocks Internal reset signal 518 system clocks Legend: WT/IT : Timer mode select bit TME : Timer enable bit OVF : Overflow flag Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation Rev. 2.00 Mar 21, 2006 page 215 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 11.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown in figure 11.4. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time Legend: WOVI : Internal timer interrupt request occurrence Figure 11.3 Interval Timer Mode Operation φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 11.4 OVF Flag Set Timing Rev. 2.00 Mar 21, 2006 page 216 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.4.3 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 11.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal 132 states Internal reset signal 518 states Figure 11.5 Output Timing of RESO signal RESO 11.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow. Table 11.2 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF Rev. 2.00 Mar 21, 2006 page 217 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.6 11.6.1 Usage Notes Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 11.6 to write to TCNT or TCSR. To write to TCNT, the upper bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the upper bytes must contain the value H'A5 and the lower bytes must contain the write data. 15 Address : H'FFA8 0 H'5A 87 Write data 0 15 Address : H'FFA8 0 H'A5 87 Write data 0 Figure 11.6 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. Rev. 2.00 Mar 21, 2006 page 218 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.7 Conflict between TCNT Write and Increment 11.6.3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 2.00 Mar 21, 2006 page 219 of 518 REJ09B0299-0200 Section 11 Watchdog Timer (WDT) 11.6.5 System Reset by RESO Signal RESO Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 11.8. This LSI Reset input RES Reset signal for entire system RESO Figure 11.8 Sample Circuit for Resetting System by RESO Signal RESO 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and sub-active or watch mode, the counter does not display the correct value due to internal clock switching. Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing timing is delayed for approximately two to three clock cycles. Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not supplied until stabilized internal oscillation is available because the main clock oscillator is halted in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value differences for this time. Special care must be taken when using WDT_1 as a clock counter. Note that no counter value difference is produced while operated in the same mode. Rev. 2.00 Mar 21, 2006 page 220 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has a serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. 12.1 Features • Choice of asynchronous or clocked synchronous serial communication mode • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. • The on-chip baud rate generator allows any bit rate to be selected An external clock can be selected as a transfer clock source. • Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) • Four interrupt sources Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive error — that can issue requests. Asynchronous Mode: • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCI0022C_000020020800 Rev. 2.00 Mar 21, 2006 page 221 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Clocked Synchronous Mode: • Data length: 8 bits • Receive error detection: Overrun errors • Serial data communication with other LSIs that have the clock synchronized communication function A block diagram of the SCI is shown in figure 12.1. Internal data bus Bus interface Module data bus RDR TDR SCMR SSR SCR BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock External clock TEI TXI RXI ERI ExRxD*/RxD RSR TSR SMR Transmission/ reception control ExTxD*/TxD Parity check ExSCK*/SCK Parity generation Legend: RSR RDR TSR TDR SMR : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register SCR SSR SCMR BRR : Serial control register : Serial status register : Smart card mode register : Bit rate register Note:* The program development tool (emulator) does not support this function. Figure 12.1 Block Diagram of SCI Rev. 2.00 Mar 21, 2006 page 222 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins Table 12.1 shows the input/output pins for each SCI channel. Table 12.1 Pin Configuration Channel 1 1 Symbol* 2 SCK1/ExSCK1* 2 RxD1/ExRxD1* 2 TxD1/ExTxD1* Input/Output Input/Output Input Output Function Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Notes: 1. Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 2. The program development tool (emulator) does not support this function. 12.3 Register Descriptions The SCI has the following registers. • Receive shift register (RSR) • Receive data register (RDR) • Transmit data register (TDR) • Transmit shift register (TSR) • Serial mode register (SMR) • Serial control register (SCR) • Serial status register (SSR) • Serial interface mode register (SCMR) • Bit rate register (BRR) • Serial pin select register (SPSR)* Note: * The program development tool (emulator) does not support this function. 12.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. Rev. 2.00 Mar 21, 2006 page 223 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 12.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 2.00 Mar 21, 2006 page 224 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock source. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. Rev. 2.00 Mar 21, 2006 page 225 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1, 0 These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR. Rev. 2.00 Mar 21, 2006 page 226 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 12.7, Interrupt Sources. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 12.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. Rev. 2.00 Mar 21, 2006 page 227 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1, 0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) Legend: X: Don’t care Rev. 2.00 Mar 21, 2006 page 228 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • • When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition] When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next data is received while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 Rev. 2.00 Mar 21, 2006 page 229 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial Value 0 R/W Description R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. * Parity Error R/(W) [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 3 PER 0 2 TEND 1 R Transmit End [Setting conditions] • • When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev. 2.00 Mar 21, 2006 page 230 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Bit 7 to 4 Bit Name — Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 — 1 R Reserved This bit is always read as 1 and cannot be modified. 0 SMIF 0 R/W Serial Communication Interface Mode Select: 0: Normal asynchronous or clocked synchronous mode 1: Reserved mode Rev. 2.00 Mar 21, 2006 page 231 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.2 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode B= 64 × 2 Bit Rate φ × 10 2n-1 6 Error × (N+1) Error (%) = { φ × 106 B × 64 × 2 2n-1 × (N+1) - 1 } × 100 Clocked synchronous mode B= 64 × 2 φ × 106 2n-1 — × (N+1) Legend: B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 0 1 2 3 n Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate settable for each frequency. Table 12.6 shows sample N settings in BRR in clocked synchronous mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock input. Rev. 2.00 Mar 21, 2006 page 232 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 — — 0 — N 141 103 207 103 51 25 12 — — 1 — Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 — — 0.00 — n 1 1 0 0 0 0 0 0 — — — 2.097152 N 148 108 217 108 54 26 13 6 — — — Error (%) –0.04 0.21 0.21 0.21 –0.70 1.14 –2.48 –2.48 — — — n 1 1 0 0 0 0 0 0 0 — 0 2.4576 N 174 127 255 127 63 31 15 7 3 — 1 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 1 1 1 0 0 0 0 0 0 0 — N 212 155 77 155 77 38 19 9 4 2 — 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 — Operating Frequency φ (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 1 1 0 0 0 0 0 — 0 — N 70 207 103 207 103 51 25 12 — 3 — 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 — 0.00 — n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 Legend: —: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 2.00 Mar 21, 2006 page 233 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0.00 –2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 — 0 7.3728 N 130 95 191 95 191 95 47 23 11 — 5 Error (%) –0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 n 2 2 1 1 0 0 0 0 0 0 — N 141 103 207 103 207 103 51 25 12 7 — 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 — Operating Frequency φ (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) –0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 –1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0.00 1.73 Legend: —: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 2.00 Mar 21, 2006 page 234 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 n 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 φ (MHz) 9.8304 10 Maximum Bit Rate (bit/s) 307200 312500 n 0 0 N 0 0 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 φ (MHz) 9.8304 10 External Input Clock (MHz) 2.4576 2.5000 Maximum Bit Rate (bit/s) 153600 156250 Rev. 2.00 Mar 21, 2006 page 235 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M Legend: Blank: Cannot be set. —: Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 3 2 1 1 0 0 0 0 0 0 0 0 2 n N 70 124 249 124 199 99 49 19 9 4 1 0* n — 2 2 1 1 0 0 0 0 0 0 0 0 4 N — 249 124 249 99 199 99 39 19 9 3 1* 0 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* — — — 1 1 0 0 0 0 0 0 — — — 249 124 249 99 49 24 9 4 n 8 N n 10 N Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) 2 4 6 8 10 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 Rev. 2.00 Mar 21, 2006 page 236 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.3.10 Serial Pin Select Register (SPSR) SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during communication. Bit 7 Bit Name SPS1 Initial Value 0 R/W R/W Description Serial Port Select Selects the serial I/O pins. 0: P86/SCK1, P85/RxD1, P84/TxD1 1: P52/ExSCK1, P51/ExRxD1, P50/ExTxD1 6 to 0 — All 0 R/W Reserved The initial value should not be changed. Note: The program development tool (emulator) does not support SPSR. 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 2.00 Mar 21, 2006 page 237 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function. Table 12.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 — 1 0 S 8-bit data MPB STOP 0 — 1 1 S 8-bit data MPB STOP STOP 1 — 1 0 S 7-bit data MPB STOP 1 — 1 1 S 7-bit data MPB STOP STOP Rev. 2.00 Mar 21, 2006 page 238 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 – 1 2N )– D – 0.5 (1 + F) – (L – 0.5) F } × 100 N [%] ... Formula (1) M: Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0.5 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875 % However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 2.00 Mar 21, 2006 page 239 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 2.00 Mar 21, 2006 page 240 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer/receive format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 12.5 Sample SCI Initialization Flowchart Rev. 2.00 Mar 21, 2006 page 241 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.5 Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8Bit Data, Parity, One Stop Bit) Rev. 2.00 Mar 21, 2006 page 242 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: No All data transmitted? Yes [3] Read TEND flag in SSR Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 12.7 Sample Serial Transmission Flowchart Rev. 2.00 Mar 21, 2006 page 243 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 2.00 Mar 21, 2006 page 244 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Table 12.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flow chart for serial data reception. Table 12.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Rev. 2.00 Mar 21, 2006 page 245 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and [2] If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. No All data received? Yes Clear RE bit in SCR to 0 [5] Legend: ∨ : Logical OR Figure 12.9 Sample Serial Reception Flowchart (1) Rev. 2.00 Mar 21, 2006 page 246 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.9 Sample Serial Reception Flowchart (2) Rev. 2.00 Mar 21, 2006 page 247 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 2.00 Mar 21, 2006 page 248 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) ID transmission cycle = receiving station specification Receiving station C (ID = 03) H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Receiving station D (ID = 04) Legend: MPB: Multiprocessor bit Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 2.00 Mar 21, 2006 page 249 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 2.00 Mar 21, 2006 page 250 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station’s ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID2 Matches this station’s ID, so reception continues, and data is received in RXI interrupt service routine Data 2 MPIE bit set to 1 again (b) Data matches station’s ID Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 2.00 Mar 21, 2006 page 251 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value. Legend: ∨ : Logical OR Initialization Start reception [1] Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR [2] FER ∨ ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station’s ID? Yes Read ORER and FER flags in SSR Yes [3] FER ∨ ORER = 1 No Read RDRF flag in SSR Yes No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 2.00 Mar 21, 2006 page 252 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Mar 21, 2006 page 253 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don’t care Note:* High except in continuous transfer/reception Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don’t care * Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First) 12.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 2.00 Mar 21, 2006 page 254 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. [2] Set the data transfer/receive format in SMR and SCMR. [1] Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer/receive format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.15 Sample SCI Initialization Flowchart Rev. 2.00 Mar 21, 2006 page 255 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode Rev. 2.00 Mar 21, 2006 page 256 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [3] Initialization Start transmission [1] Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 12.17 Sample Serial Transmission Flowchart Rev. 2.00 Mar 21, 2006 page 257 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode Rev. 2.00 Mar 21, 2006 page 258 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. Initialization Start reception [1] Read ORER flag in SSR [2] Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 12.19 Sample Serial Reception Flowchart Rev. 2.00 Mar 21, 2006 page 259 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and RE bits to 1 simultaneously with a single instruction. Rev. 2.00 Mar 21, 2006 page 260 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Initialization Start transmission/reception [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] [3] Read ORER flag in SSR Yes [3] Error processing ORER = 1 No [4] Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] No All data received? Yes [5] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Clear TE and RE bits in SCR to 0 Note: * When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 2.00 Mar 21, 2006 page 261 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.7 Interrupt Sources Table 12.10 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 12.10 SCI Interrupt Sources Channel 1 Name ERI1 RXI1 TXI1 TEI1 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND Low Priority High Rev. 2.00 Mar 21, 2006 page 262 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.8 12.8.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 12.8.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 12.8.3 Mark State and Break Detection When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 12.8.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. Rev. 2.00 Mar 21, 2006 page 263 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.8.6 SCI Operations during Mode Transitions Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If a transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 12.21 shows a sample flowchart for mode transition during transmission. Figures 12.22 and 12.23 show the pin states during transmission. Reception: Before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 12.24 shows a sample flowchart for mode transition during reception. Rev. 2.00 Mar 21, 2006 page 264 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Transmission All data transmitted? Yes Read TEND flag in SSR No [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation. [2] Also clear TIE and TEIE to 0 when they are 1. [3] Module stop, watch, sub-active, and sub-sleep modes are included. TEND = 1 Yes TE = 0 [2] No Make transition to software standby mode etc. Cancel software standby mode etc. [3] Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 12.21 Sample Flowchart for Mode Transition during Transmission Transition to Software standby Transmission end software standby mode cancelled mode Transmission start TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) Rev. 2.00 Mar 21, 2006 page 265 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Transition to Software standby software standby mode cancelled mode Transmission start Transmission end TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note:* Initialized in software standby mode Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop, watch, sub-active, and subsleep modes are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 12.24 Sample Flowchart for Mode Transition during Reception Rev. 2.00 Mar 21, 2006 page 266 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) 12.8.7 Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 12.25. Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output Figure 12.25 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. End serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 (switch to port output) 5. CKE1 bit = 0 High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 2.00 Mar 21, 2006 page 267 of 518 REJ09B0299-0200 Section 12 Serial Communication Interface (SCI) Rev. 2.00 Mar 21, 2006 page 268 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Section 13 I C Bus Interface (IIC) The I C bus interface is provided as an optional function. Note the following point when using this optional function. • Although the product type name is identical, please contact Renesas before using this optional function on an F-ZTAT version product. This LSI has a two-channel I C bus interface. The I C bus interface conforms to and provides a 2 subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that 2 controls the I C bus differs partly from the Philips configuration, however. 2 2 2 2 13.1 2 Features • Selection of addressing format or non-addressing format  I C bus format: addressing format with an acknowledge bit, for master/slave operation  Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only • Conforms to Philips I C bus interface (I C bus format) 2 2 • Two ways of setting slave address (I C bus format) 2 • Start and stop conditions generated automatically in master mode (I C bus format) 2 • Selection of the acknowledge output level in reception (I C bus format) 2 • Automatic loading of an acknowledge bit in transmission (I C bus format) 2 • Wait function in master mode (I C bus format) 2  A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement.  The wait can be cleared by clearing the interrupt flag. • Wait function (I C bus format) 2  A wait request can be generated by driving the SCL pin low after data transfer.  The wait request is cleared when the next transfer becomes possible. • Interrupt sources  Data transfer end (including when a transition to transmit mode with I C bus format occurs, when ICDR data is transferred, or during a wait state) 2  Address match: When any slave address matches or the general call address is received in 2 slave receive mode with I C bus format (including address reception after loss of master arbitration)  Start condition detection (in master mode) IFIIC60B_000020020800 Rev. 2.00 Mar 21, 2006 page 269 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2  Stop condition detection (in slave mode) • Selection of 16 internal clocks (in master mode) • Direct bus drive (SCL/SDA pin)  Four pins—P52/SCL0, P97/SDA0, P86/SCL1, and P42/SDA1 —(normally NMOS pushpull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Rev. 2.00 Mar 21, 2006 page 270 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Figure 13.1 shows a block diagram of the I C bus interface. Figure 13.2 shows an example of I/O 2 pin connections to external circuits. Since I C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 21, Electrical Characteristics. 2 ICXR φ SCL PS Clock control ICCR Noise canceler ICMR Bus state decision circuit Arbitration decision circuit SDA Output data control circuit ICSR ICDRT ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: ICMR: ICSR: ICDR: ICXR: SAR: SARX: PS: I2C bus control register I2C bus mode register I2C bus status register I2C bus data register I2C bus extended control register Slave address register Slave address register X Prescaler 2 Interrupt generator Figure 13.1 Block Diagram of I C Bus Interface Rev. 2.00 Mar 21, 2006 page 271 of 518 REJ09B0299-0200 Internal data bus Interrupt request Section 13 I C Bus Interface (IIC) VDD VCC 2 VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) This LSI SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) 2 SDA in SDA out (Slave 2) Figure 13.2 I C Bus Interface Connections (Example: This LSI as Master) 13.2 Input/Output Pins 2 Table 13.1 summarizes the input/output pins used by the I C bus interface. Table 13.1 Pin Configuration Channel 0 Symbol* SCL0 SDA0 1 SCL1 SDA1 Input/Output Input/Output Input/Output Input/Output Input/Output Function Serial clock input/output pin of IIC_0 Serial data input/output pin of IIC_0 Serial clock input/output pin of IIC_1 Serial data input/output pin of IIC_1 Note: * In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 2.00 Mar 21, 2006 page 272 of 518 REJ09B0299-0200 SCL SDA Section 13 I C Bus Interface (IIC) 2 13.3 2 Register Descriptions The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). • I C bus control register (ICCR) 2 2 2 2 • I C bus status register (ICSR) • I C bus data register (ICDR) • I C bus mode register (ICMR) • Slave address register (SAR) • Second slave address register (SARX) • I C bus extended control register (ICXR) 2 • DDC switch register (DDCSWR) 13.3.1 I C Bus Data Register (ICDR) 2 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag is 0) after successful transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is 2 transferred automatically from ICDRT to ICDRS by writing to ICDR. If I C is in receive mode (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to ICDR in receive mode. Rev. 2.00 Mar 21, 2006 page 273 of 518 REJ09B0299-0200 2 Section 13 I C Bus Interface (IIC) 2 Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR. If I C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from 2 ICDRS to ICDRR. Always set I C to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. 13.3.2 Slave Address Register (SAR) 2 SAR sets the slave address and selects the communication format. If the LSI is in slave mode with 2 the I C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Format Select Selects the communication format together with the FSX bit in SARX. Refer to table 13.2. This bit should be set to 0 when general call address recognition is performed. Description Slave Address 6 to 0 Set a slave address. Rev. 2.00 Mar 21, 2006 page 274 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave 2 mode with the I C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value R/W 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR. Refer to table 13.2. Description Second Slave Address 6 to 0 Set the second slave address. Rev. 2.00 Mar 21, 2006 page 275 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.2 Communication Format SAR FS 0 SARX FSX 0 Operating Mode I C bus format • • 1 2 2 SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored I C bus format • • • 1 0 I C bus format • • • 2 1 Clocked synchronous serial format • • SAR and SARX slave addresses ignored General call address ignored • I C bus format: addressing format with an acknowledge bit 2 • Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only Rev. 2.00 Mar 21, 2006 page 276 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.3.4 I C Bus Mode Register (ICMR) 2 ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value R/W 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8 clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, refer to section 13.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. Refer to table 13.3. th 2 2 Rev. 2.00 Mar 21, 2006 page 277 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected. The value returns to 000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 2.00 Mar 21, 2006 page 278 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.3 I C Transfer Rate STCR Bits 5 and 6 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ICMR Bit 5 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock φ/28 φ/40 φ/48 φ/64 φ/80 φ/100 φ/112 φ/128 φ/56 φ/80 φ/96 φ/128 φ/160 φ/200 φ/224 φ/256 Transfer Rate φ = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz φ = 8 MHz φ = 10 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 2 Rev. 2.00 Mar 21, 2006 page 279 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 2 13.3.5 I C Bus Control Register (ICCR) 2 ICCR controls the I C bus interface and performs interrupt flag confirmation. Bit 7 Bit Name ICE Initial Value R/W 0 R/W Description I C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they lose 2 in a bus contention in master mode with the I C bus format. 2 In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. 2 2 2 2 2 2 2 Rev. 2.00 Mar 21, 2006 page 280 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 5 4 Bit Name MST TRS Initial Value R/W 0 0 R/W Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3. When lost in bus contention in I C bus format master mode [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing condition 3) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing condition 3) 3. When 1 is received as the R/W bit after the first frame 2 address matching in I C bus format slave mode 3 ACKE 0 R/W Acknowledge Bit Decision and Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. 2 2 2 Rev. 2.00 Mar 21, 2006 page 281 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 2 0 Bit Name BBSY SCP Initial Value R/W 0 1 R/W W Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: • • Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled. 2 In slave mode: • [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored. 2 2 Rev. 2.00 Mar 21, 2006 page 282 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 1 Bit Name Initianl Value R/W IRIC 0 Description 2 2 2 R/(W)* I C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 13.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode: • When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock while no wait is inserted) When a slave address is received after bus arbitration is lost (the first frame after the start condition) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 2 • • • • When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 I C bus format slave mode: • When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) When the general call address is detected (when 0 is received as the R/W bit and the ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) while the ACKE bit is 1 When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) while the STOPIM bit is 0 2 • • • Rev. 2.00 Mar 21, 2006 page 283 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 1 Bit Name IRIC Initial Value R/W 0 Description • • 2 R/(W)* Clocked synchronous serial format mode: At the end of data transfer (rise of the 8th transmit/receive) When a start condition is detected When the ICDRE or ICDRF flag is set to 1 in any operating mode: • When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) When data is transferred among the ICDR register and buffer (when data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1, or when data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1) • [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 Note: * Only 0 can be written, to clear the flag. When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition 2 after a slave address (SVA) or general call address match in I C bus format slave mode. Tables 13.4 and 13.5 show the relationship between the flags and the transfer states. 2 Rev. 2.00 Mar 21, 2006 page 284 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.4 Flags and Transfer States (Master Mode) MST 1 1 1 1 TRS 1 1 — 1 BBSY ESTP 0 1↑ 1 1 0 0 0 0 STOP IRTR 0 0 0 0 0 1↑ — — AASX AL 0↓ 0 0 0 0 0 0 0 AAS 0↓ 0 0 0 ADZ 0↓ 0 0 0 ACKB ICDRF ICDRE State 0 0 — 1↑ — — — — 0 1↑ — — Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE = 1 and ACKB = 1) Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF = 0 ICDR read with the above state Reception end with ICDRF = 1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Arbitration lost Stop condition detected 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1↑ — — — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — — — — 1↑ 0↓ 1 0↓ 1 1 1 0 0 1↑ 0 0 0 0 0 — 1↑ 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1↑ — — — 1↑ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — — — — — 1↑ 0↓ 1 0↓ 1↑ — — — — — 0↓ 1 0↓ — 1 0↓ 0 0 0 0 — — 0 0 1↑ 0 0 0 0 0 — — — — — 0↓ Legend: 0: 1: —: 0 ↓: 1 ↑: 0-state retained 1-state retained Previous state retained Cleared to 0 Set to 1 Rev. 2.00 Mar 21, 2006 page 285 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.5 Flags and Transfer States (Slave Mode) MST 0 0 0 0 TRS 0 0 BBSY ESTP 0 1↑ 0 0 0 0 STOP IRTR 0 0 0 0 0 0 0 0 AASX AL 0 0↓ 0 0 0 0 — — AAS 0 0 1↑ 1↑ ADZ 0 0 0 1↑ ACKB ICDRF ICDRE State 0 0 0 0 — — 1↑ 1↑ 0 1↑ 1 1 Idle state (flag clearing required) Start condition detected SAR match in first frame (SARX ≠ SAR) General call address match in first frame (SARX ≠ H'00) SARS match in first frame (SAR ≠ SARX) Transmission end (ACKE = 1 and ACKB = 1) Transmission end with ICDRE = 0 ICDR write with the above state Transmission end with ICDRE = 1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF = 0 ICDR read with the above state Reception end with ICDRF = 1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected 1 1↑/0* 1 0 1 0 0 1↑/0* 1 1 1 1 0 0 0 0 1↑ — 1↑ — — — 0 — 0 0 0 1↑ 1↑ — 1 — 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1↑/0*1 — — — — — — — — 0↓ — 0↓ 0 — 0↓ — 0↓ 0 0 0 0 0 0 0 0 0 0 0 — — — — — 1↑ 0↓ 1 0↓ 1↑ 1↑/0*2 — 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1↑/0*2 — — — — — — — — 0↓ — 0↓ 0 — 0↓ — 0↓ 0 — 0↓ — 0↓ 0 — — — — — 1↑ 0↓ 1 0↓ 1↑ — — — — — 2 1↑/0* — 0 — 0↓ 1↑/0*3 0/1↑*3 — — — — — — — 0↓ Legend: 0: 0-state retained 1: 1-state retained —: Previous state retained Rev. 2.00 Mar 21, 2006 page 286 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 0 ↓: Cleared to 0 Set to 1 1 ↑: Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP = 1, STOP is 0, or when STOP = 1, ESTP is 0. 2 Rev. 2.00 Mar 21, 2006 page 287 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 2 13.3.6 I C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 13.4 and 13.5. Bit 7 Bit Name ESTP Initial Value R/W 0 Description 2 R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] • When 0 is written in ESTP after reading ESTP = 1 • When the IRIC flag in ICCR is cleared to 0 * Normal Stop Condition Detection Flag R/(W) This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] • • When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0 2 6 STOP 0 5 IRTR 0 R/(W)* I C Bus Interface Continuous Transfer Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I C bus format slave mode: • When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1 2 2 Master mode or clocked synchronous serial format mode 2 with I C bus format: • • • Rev. 2.00 Mar 21, 2006 page 288 of 518 REJ09B0299-0200 When the ICDRE or ICDRF flag is set to 1 When 0 is written after reading IRTR = 1 When the IRIC flag is cleared to 0 while ICE is 1 [Clearing conditions] Section 13 I C Bus Interface (IIC) Bit 4 Bit Name AASX Initial Value R/W 0 Description 2 2 R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] • • • When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode 3 AL 0 R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL = 0 • • If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before 2 the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1 When ALSL = 1 • • [Clearing conditions] • • Rev. 2.00 Mar 21, 2006 page 289 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 2 Bit Name AAS Initial Value R/W 0 Description 2 2 R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] • • • When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode 2 1 ADZ 0 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] • • • When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode If a general call address is detected while FS = 1 and FSX = 0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1). Rev. 2.00 Mar 21, 2006 page 290 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 0 Bit Name ACKB Initial Value R/W 0 R/W Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode [Clearing conditions] • • When 0 is received as the acknowledge bit when ACKE = 1 in transmit mode When 0 is written to the ACKE bit 2 Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If the ICSR register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write the ACKE bit to 0 to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written to clear the flag. Rev. 2.00 Mar 21, 2006 page 291 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Bit Bit Name Initial Value R/W All 0 0 1 1 1 1 R/W R W* W* W* W* Description Reserved The initial value should not be changed. Reserved IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Note: * This bit is always read as 1. 7 to — 5 4 3 2 1 0 — CLR3 CLR2 CLR1 CLR0 Rev. 2.00 Mar 21, 2006 page 292 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 2 13.3.8 I C Bus Extended Control Register (ICXR) 2 ICXR enables or disables the I C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit 7 Bit Name STOPIM Initial Value R/W 0 R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Handshake Receive Operation Select Enables or disables continuous receive operation in receive mode. 0: Enables continuous receive operation 1: Disables continuous receive operation When the HNDS bit is cleared to 0, receive operation is performed continuously after data has been received successfully while ICDRF flag is 0. When the HNDS bit is set to 1, SCL is fixed to the low level and the next data transfer is disabled after data has been received successfully while the ICDRF flag is 0. The bus line is released and next receive operation is enabled by reading the receive data in ICDR. Rev. 2.00 Mar 21, 2006 page 293 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 5 Bit Name ICDRF Initial Value R/W 0 R Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR. (1) When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). (2) When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] • • • When ICDR (ICDRR) is read. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. 2 When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0). Rev. 2.00 Mar 21, 2006 page 294 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 4 Bit Name ICDRE Initial Value R/W 0 R Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [Setting conditions] • • When the start condition is detected from the bus line 2 state with I C bus format or serial format. When data is transferred from ICDRT to ICDRS. (1) When data transmission completed while ICDRE = 0 (at the rise of the 9th clock pulse). (2) When data is written to ICDR in transmit mode after data transmission was completed while ICDRE = 1. [Clearing conditions] • • • • When data is written to ICDR (ICDRT). When the stop condition is detected with I C bus format or serial format. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. 2 2 2 Note that if the ACKE bit is set to 1 with I C bus format thus enabling acknowledge bit decision, ICDRE is not set when data transmission is completed while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRE is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time. Rev. 2.00 Mar 21, 2006 page 295 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Bit 3 Bit Name ALIE Initial Value R/W 0 R/W Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SCL pin is driven low by another device. 1: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SDA line is driven low by another device in idle state or after the start condition instruction was executed. 1 0 FNC1 FNC0 0 0 R/W R/W Function Bit 1, 0 Cancels some restrictions on usage. For details, refer to section 13.6, Usage Notes. 00: Restrictions on operation remaining in effect 01: Setting prohibited 10: Setting prohibited 11: Restrictions on operation canceled 2 Rev. 2.00 Mar 21, 2006 page 296 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4 2 Operation 2 The I C bus interface has an I C bus format and a serial format. 13.4.1 2 I C Bus Data Format 2 The I C bus format is an addressing format with an acknowledge bit. This is shown in figure 13.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 13.4. Figure 13.5 shows the I C bus timing. The symbols used in figures 13.3 to 13.5 are explained in table 13.6. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) 2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) Figure 13.3 I C Bus Data Format (I C Bus Format) FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) 2 2 Figure 13.4 I C Bus Data Format (Serial Format) 2 Rev. 2.00 Mar 21, 2006 page 297 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) SDA 2 SCL 1–7 S SLA 8 R/W 9 A 1–7 DATA 2 8 9 A 1–7 DATA 8 9 A/A P Figure 13.5 I C Bus Timing Table 13.6 I C Bus Data Format Symbols Legend S SLA R/W A Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high 2 DATA P Rev. 2.00 Mar 21, 2006 page 298 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4.2 Initialization Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRL) Set IICE = 1 in STCR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR Set ICMR Set ICXR Set ICCR Cancel module stop mode Enable the CPU accessing to the IIC control register and data register Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE) > Figure 13.6 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 13.4.3 2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 13.7 shows the sample flowchart for the operations in master transmit mode. Rev. 2.00 Mar 21, 2006 page 299 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Start Initialize IIC [1] Initialization 2 Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC flag in ICCR [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.) [7] Wait for 1 byte to be transmitted. [3] Select master transmit mode. [4] Start condition issuance Read IRIC flag in ICCR No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No No [8] Test the acknowledge bit transferred from the slave device. Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC flag continuously.) [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB bit in ICSR [11] Determine end of tranfer No End of transmission? or ACKB = 1? Yes Clear IRIC flag in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode Rev. 2.00 Mar 21, 2006 page 300 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. 2. Read the BBSY flag in ICCR to confirm that the bus is free. 3. Set bits MST and TRS to 1 in ICCR to select master transmit mode. 4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. 2 Rev. 2.00 Mar 21, 2006 page 301 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 IRIC Interrupt request Interrupt request IRTR ICDRT Address + R/W Address + R/W Data 1 ICDRS Data 1 Note:* Data write in ICDR prohibited User processing [4] BBSY set to 1 [6] ICDR write SCP cleared to 0 (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 2.00 Mar 21, 2006 page 302 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Start condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9 2 SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE Data 2 IRIC IRTR ICDR Data 1 Data 2 User processing [9] ICDR write [9] IRIC clear [11] ACKB read [12] Set BBSY = 1and SCP = 0 (Stop condition issuance) [12] IRIC clear Figure 13.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 2.00 Mar 21, 2006 page 303 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4.4 2 Master Receive Operation In I C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Receive Operation Using the HNDS Function (HNDS = 1): Figure 13.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1). Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 1 in ICXR Clear IRIC flag in ICCR [1] Select receive mode. Last receive? No Read ICDR Yes [2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read) Read IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR [3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame) [4] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? [6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received. Yes Clear IRIC flag in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End [9] Clear IRIC flag. [10] Read the receive data. [11] Set stop condition issuance. Generate stop condition. Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) Rev. 2.00 Mar 21, 2006 page 304 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to clear the wait state. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 2.00 Mar 21, 2006 page 305 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Master transmit mode Master receive mode SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Undefined value Data 1 9 A 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A SCL is fixed low until ICDR is read 9 1 Bit 7 2 Bit 6 2 Data 1 Data 2 User processing [1] TRS = 0 clear [1] IRIC clear [2] ICDR read (Dummy read) [4] IRIC clear [5] ICDR read (Data 1) Figure 13.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) SCL is fixed low until stop condition is issued 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9 SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Stop condition generation Data 2 Data 3 Data 3 [10] ICDR read (Data 3) [11] Set BBSY = 0 and SCP = 0 (Stop condition instruction issuance) User processing [4] IRIC clear [7] ICDR read (Data 2) [6] Set ACKB = 1 [9] IRIC clear Figure 13.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) Receive Operation Using the Wait Function: Figures 13.13 and 13.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Rev. 2.00 Mar 21, 2006 page 306 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [4] Determine end of reception IRTR = 1? Yes Last receive? No Read ICDR Clear IRIC flag in ICCR [5] Read the receive data. [6] Clear IRIC flag. (to end the wait insertion) Yes [1] Select receive mode. 2 Read IRIC flag in ICCR No IRIC = 1? Yes No Set ACKB = 1 in ICSR Wait for one clock pulse Set TRS = 1 in ICCR Read ICDR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [8] Wait for TRS setting [9] Set TRS for stop condition issuance [10] Read the receive data. [11] Clear IRIC flag. (to end the wait insertion) Read IRIC flag in ICCR No IRIC = 1? Yes IRTR = 1? No Clear IRIC flag in ICCR Yes [12] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [13] Determine end of reception [14] Clear IRIC. (to end the wait insertion) Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data. [17] Generate stop condition Figure 13.13 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1) Rev. 2.00 Mar 21, 2006 page 307 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR [1] Select receive mode. Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Read IRIC flag in ICCR No IRIC = 1? Yes Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance [11] Clear IRIC flag. (to end the wait insertion) [12] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock) Read IRIC flag in ICCR No IRIC = 1? Yes Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data [17] Generate stop condition End Figure 13.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1) Rev. 2.00 Mar 21, 2006 page 308 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 13.14. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. 3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU.  At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing.  At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 4. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. If IRTR flag is 1, read ICDR receive data. 6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [3] to [6]. 7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. 8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. Read the ICDR receive data. 11. Clear the IRIC flag to 0. Rev. 2.00 Mar 21, 2006 page 309 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 12. The IRIC flag is set to 1 in either of the following cases.  At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared.  At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. 15. Clear the WAIT bit in ICMR to cancel the wait mode. Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. Read the last ICDR receive data. 17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master tansmit mode Master receive mode SCL (master output) 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 SDA (slave output) SDA (master output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Data 2 Bit 4 Bit 3 IRIC IRTR [4]IRTR=0 [4] IRTR=1 ICDR Data 1 User processing [1] TRS cleared to 0 IRIC cleard to 0 [2] ICDR read (dummy read) [6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1) Figure 13.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Rev. 2.00 Mar 21, 2006 page 310 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) [8] Wait for one clock pulse 2 Stop condition generation SCL (master output) 8 9 1 Bit 7 [3] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [12] A [12] 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR Data 3 [4] IRTR = 0 [4] IRTR = 1 [13] IRTR = 0 [13] IRTR = 1 Data 1 Data 2 Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear [17] Stop condition issuance [16] ICDR read (Data 3) User processing [6] IRIC clear [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS = 1 [7] Set ACKB = 1 Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) 13.4.5 2 Slave Receive Operation In I C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. Receive Operation Using the HNDS Function (HNDS = 1): Figure 13.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1). Rev. 2.00 Mar 21, 2006 page 311 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR 2 [1] Initialization. Select slave receive mode. Read IRIC flag in ICCR ICDRF = 1? Yes No [2] Read the receive data remaining unread. Read ICDR, clear IRIC flag Read IRIC flag in ICCR No IRIC = 1? Yes [3] to [7] Wait for one byte to be received (slave address + R/W) Clear IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Yes [8] Clear IRIC General call address processing * Description omitted Read TRS in ICCR TRS = 1? No Yes Yes Slave transmit mode Last reception? No Read ICDR [10] Read the receive data. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? Yes [5] to [7] Wait for the reception to end. Clear IRIC flag in ICCR [8] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? Yes [9] Set acknowledge data for the last reception. [10] Read the receive data. [11] Detect stop condition [12] Clear IRIC flag. Clear IRIC in ICCR End Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) Rev. 2.00 Mar 21, 2006 page 312 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0. Rev. 2.00 Mar 21, 2006 page 313 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) IRIC 1 1 2 2 3 3 4 4 5 5 6 6 7 7 2 [7] SCL is fixed low until ICDR is read 8 8 9 9 1 1 2 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 Slave address [6] A Interrupt request occurrence ICDRF ICDRS Address+R/W Address+R/W ICDRR Undefined value User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read) Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS = 1) Rev. 2.00 Mar 21, 2006 page 314 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Stop condition generation [7] SCL is fixed low until ICDR is read 4 5 6 7 8 9 2 [7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n - 1) SDA (slave output) IRIC Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 8 9 1 2 3 Bit 3 Bit 2 Bit 1 Bit 0 [6] Data (n) [6] [11] A A ICDRF ICDRS Data (n - 1) Data (n) Data (n - 1) Data (n) ICDRR Data (n - 2) User processing [8] IRIC clear [5] ICDR read (Data (n - 1)) [9] Set ACKB = 1 [8] IRIC clear [10] ICDR read (Data (n)) [12] IRIC clear Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS = 1) Rev. 2.00 Mar 21, 2006 page 315 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Continuous Receive Operation: Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No No Yes Yes No [1] Select slave receive mode. [2] Read the receive data remaining unread. [3] to [7] Wait for one byte to be received (slave address + R/W) (Set IRIC at the rise of the 9th clock) [8] Clear IRIC General call address processing * Description omitted Slave transmit mode * n: Address + total number of bytes received (n-2)th-byte reception? Wait for one frame Set ACKB = 1 in ICSR [9] Wait for ACKB setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n - 1)th byte data) No ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? Yes ESTP = 1 or STOP = 1? No Clear IRIC in ICCR [10] Read the receive data. The first read is a dummy read. [11] Wait for one byte to be received (Set IRIC at the rise of the 9th clock) Yes [12] Detect stop condition [13] Clear IRIC ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR End No [14] Read the last receive data [15] Clear IRIC Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) Rev. 2.00 Mar 21, 2006 page 316 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W) in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, the IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. 8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0. 9. If the next read data is the third last receive frame, wait for at least one frame time to set the ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive frame. 10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0. 11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1. 12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive data. 13. Clear the IRIC flag to 0. Receive operations can be performed continuously by repeating steps [9] to [13]. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag. Rev. 2.00 Mar 21, 2006 page 317 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) Start condition issuance SCL (master output) SDA (master output) SDA (slave output) IRIC 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [6] A 9 1 Bit 7 2 Bit 6 Data 1 3 Bit 5 4 Bit 4 2 Slave address ICDRF ICDRS Address + R/W [7] Data 1 Address + R/W ICDRR User processing [8] IRIC clear [10] ICDR read Figure 13.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0) Start condition detection SCL (master output) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA (master output) Bit 0 Data n - 2 SDA (slave output) IRIC ICDRF ICDRS ICDRR User processing Data n - 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] A Data n - 1 [11] A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n [11] A [11] Data n - 1 Data n - 2 [9] Wait for one frame [13] IRIC clear Data n - 1 Data n Data n [13] IRIC clear [10] ICDR read [10] ICDR read (Data n - 1) (Data n - 2) [9] Set ACKB = 1 [13] IRIC clear [14] ICDR read (Data n) [15] IRIC clear Figure 13.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0) Rev. 2.00 Mar 21, 2006 page 318 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 13.23 shows the sample flowchart for the operations in slave transmit mode. Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR [1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes. [3], [4] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB in ICSR [4] Determine end of transfer. No End of transmission (ACKB = 1)? Yes Clear IRIC in ICCR [6] Read IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition Clear ACKE to 0 in ICCR (ACKB = 0 clear) Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR End Figure 13.23 Sample Flowchart for Slave Transmit Mode Rev. 2.00 Mar 21, 2006 page 319 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS, transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps [4] and [5]. 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SDA on the slave side. Rev. 2.00 Mar 21, 2006 page 320 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0. Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 [2] Data 1 [4] Data 2 SDA (master output) R/W IRIC A ICDRE ICDR User processing [3] IRIC clear [3] ICDR write [3] IRIC clear Data 1 Data 2 [5] IRIC clear [5] ICDR write Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 2.00 Mar 21, 2006 page 321 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control. When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 2 3 SDA 7 8 A 1 2 3 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 7 8 9 1 SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 13.25 IRIC Setting Timing and SCL Control (1) Rev. 2.00 Mar 21, 2006 page 322 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 2 3 2 SDA 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 8 9 1 SDA 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 13.26 IRIC Setting Timing and SCL Control (2) Rev. 2.00 Mar 21, 2006 page 323 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL 7 8 1 2 3 4 2 SDA 7 8 1 2 3 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception Figure 13.27 IRIC Setting Timing and SCL Control (3) Rev. 2.00 Mar 21, 2006 page 324 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 13.28 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 13.28 Block Diagram of Noise Canceler 13.4.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: • ICDRE and ICDRF internal flags • Transmit/receive sequencer and internal operating clock counter • Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) Rev. 2.00 Mar 21, 2006 page 325 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) • Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR • The value of the ICMR bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. • When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. • Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. • If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. Rev. 2.00 Mar 21, 2006 page 326 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 13.5 Interrupt Sources The IIC has interrupt source IICI. Table 13.7 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently. Table 13.7 IIC Interrupt Sources Channel 0 1 Name IICI0 IICI1 Enable Bit IEIC IEIC Interrupt Source I C bus interface interrupt request I C bus interface interrupt request 2 2 Interrupt Flag IRIC IRIC Priority High Low 13.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction 2 to generate a stop condition is issued before the start condition is output to the I C bus, neither condition will be output correctly. To output the start condition followed by the stop condition, 2 after issuing the instruction that generates the start condition, read DR in each I C bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR.  Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS)  Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Rev. 2.00 Mar 21, 2006 page 327 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.8 I C Bus Timing (SCL and SDA Outputs) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * 6tcyc when IICX is 0, 12tcyc when 1. tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO – 1tcyc 0.5tSCLO – 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO – 3tcyc 1tSCLL – (6tcyc or 12tcyc*) 3tcyc Unit ns Notes See figure 21.21. 2 4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 21, Electrical 2 Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 5. The I C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high2 speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds 2 the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 13.9. Table 13.9 Permissible SCL Rise Time (tsr) Values Time Indication [ns] IICX 0 tcyc Indication 7.5 tcyc Standard mode High-speed mode 1 17.5 tcyc Standard mode High-speed mode I C Bus Specification (Max.) 1000 300 1000 300 2 2 φ= 5 MHz 1000 300 1000 300 φ= 8 MHz 937 300 1000 300 φ= 10 MHz 750 300 1000 300 Rev. 2.00 Mar 21, 2006 page 328 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 6. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns 2 and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in 2 table 13.8. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 13.10 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing 2 permits this output timing for use as slave devices connected to the I C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input 2 timing permits this output timing for use as slave devices connected to the I C bus. 2 2 2 Rev. 2.00 Mar 21, 2006 page 329 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Table 13.10 I C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I C Bus tSr/tSf Influence Specifiφ= cation (Min.) 5 MHz (Max.) Standard mode –1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 0 0 4000 950 2 2 Item tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tcyc Indication 0.5 tSCLO (–tSr) 0.5 tSCLO (–tSf) 0.5 tSCLO – 1 tcyc (–tSr) 0.5 tSCLO – 1 tcyc (–tSf) 1 tSCLO (–tSr) 0.5 tSCLO + 2 tcyc (–tSr) 3 φ= 8 MHz 4000 950 φ= 10 MHz 4000 950 High-speed mode –300 Standard mode –250 High-speed mode –250 Standard mode –1000 High-speed mode –300 Standard mode –250 4750 4750 4750 1 1 1 1000* 1000* 1000* 1 1 1 3800* 3875* 3900* 1 1 1 750* 825* 850* 4550 800 9000 2200 4400 1350 3100 400 1300 4625 875 9000 2200 4250 1200 3325 625 4650 900 9000 2200 4200 1150 3400 700 High-speed mode –250 Standard mode –1000 High-speed mode –300 Standard mode –1000 High-speed mode –300 Standard mode 2 tSDASO 1 tSCLLO* – 3 tcyc (master) (–tSr) 1 tSCLL* – 12 tcyc* tSDASO (slave) (–tSr) 3 –1000 High-speed mode –300 Standard mode –1000 High-speed mode –300 Standard mode 2 2200 2500 *1 –500*1 –200*1 –1400 600 600 375 375 300 300 tSDAHO 3 tcyc 0 High-speed mode 0 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL – 6tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). Rev. 2.00 Mar 21, 2006 page 330 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR (ICDRR), and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 13.29 (after confirming that the BBSY bit in ICCR has been cleared to 0). Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9 Start condition Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confirmation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 13.29 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. Rev. 2.00 Mar 21, 2006 page 331 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 8. Notes on start condition issuance for retransmission Figure 13.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated. IRIC = 1? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICSR) No [1] [1] Wait for end of 1-byte transfer [2] Determine whether SCL is low No Other processing [3] Issue start condition instruction for retransmission [4] Determine whether start condition is generated or not [5] Set transmit data (slave address + R/W) [2] Note:* Program so that processing from [3] to [5] is executed continuously. No [3] IRIC = 1? Yes Write transmit data to ICDR No [4] [5] Start condition generation (retransmission) SCL 9 SDA ACK bit7 IRIC [5] ICDR write (transmit data) [4] IRIC determination [1] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 11 in ICXR. Rev. 2.00 Mar 21, 2006 page 332 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 9. Note on when I C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low. 9th clock VIH Secures a high period 2 SCL SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low determination [2] Stop condition instruction issuance Figure 13.31 Stop Condition Issuance Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. 10. Notes on WAIT function  Conditions to cause this phenomenon When both of the following conditions are satisfied, the clock pulse of the 9th clock could be outputted continuously in master mode using the WAIT function due to the failure of the WAIT insertion after the 8th clock fall. (1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode (2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock.  Error phenomenon Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the 7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally. Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.  Restrictions Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2 through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th clock. Rev. 2.00 Mar 21, 2006 page 333 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.) Transmit/receive data 9 1 7 2 6 3 5 When BC2-0 ≥ 2 IRIC clear ASD SCL BC2–BC0 IRIC (operation example) A 9 0 1 7 2 6 Transmit/receive data A 7 2 1 8 SCL = ‘L’ confirm 0 IRIC clear 3 5 4 4 5 3 6 IRIC flag clear available IRIC flag clear available IRIC flag clear unavailable Figure 13.32 IRIC Flag Clear Timing on WAIT Operation 11. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be 2 inserted by driving the SCL pin low is used when the wait function is used in I C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously. Secures a high period SCL VIH SCL = low detected SDA IRIC [1] SCL = low determination [2] IRIC clear Figure 13.33 IRIC Flag Clearing Timing When WAIT = 1 Rev. 2.00 Mar 21, 2006 page 334 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. 12. Note on ICDR read and ICCR access in slave transmit mode In I C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 13.34. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions.  Read ICDR data that has been received so far or read/write from/to ICCR before starting the receive operation of the next slave address.  Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to ICCR during the time other than the shaded time. Waveform at problem occurrence ICDR write SDA R/W A Bit 7 2 SCL 8 9 TRS bit Address reception Data transmission ICDR read and ICCR read/write are disabled (6 system clock period) The rise of the 9th clock is detected Figure 13.34 ICDR Read and ICCR Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in ICXR. 13. Note on TRS bit setting in slave mode In I C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 13.35), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 13.35), the bit value is suspended and remains invalid until the rising edge of the 9th Rev. 2.00 Mar 21, 2006 page 335 of 518 REJ09B0299-0200 2 Section 13 I C Bus Interface (IIC) 2 clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 13.35. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR. Restart condition (a) SDA (b) A SCL 8 9 1 2 3 4 5 6 7 8 9 TRS Data transmission Address reception TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected The rise of the 9th clock is detected Figure 13.35 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 11 in ICXR. 14. Notes on Arbitration Lost in master mode The I C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX 2 register, the I C bus interface erroneously recognizes that the address call has occurred. (See figure 13.36.) In multi-master mode, a bus conflict could happen. When The I C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. 2 2 Rev. 2.00 Mar 21, 2006 page 336 of 518 REJ09B0299-0200 Section 13 I C Bus Interface (IIC) 2 When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. • Arbitration is lost • The AL flag in ICSR is set to 1 I2 C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data does not match DATA2 A DATA3 A Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Data contention I bus interface (Slave receive mode) 2C S SLA R/W A SLA R/W A DATA4 A • Receive address is ignored • Automatically transferred to slave receive mode • Receive data is recognized as an address • When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device Figure 13.36 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. 15. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 16. Note on ACKE and TRS bits in slave mode In the I C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the Rev. 2.00 Mar 21, 2006 page 337 of 518 REJ09B0299-0200 2 2 Section 13 I C Bus Interface (IIC) 2 address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt source even when the address does not match. To use the I C bus interface module in slave mode, be sure to follow the procedures below. A. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. B. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 13.23, in order to switch from slave transmit mode to slave receive mode. 13.6.1 Module Stop Mode Setting 2 The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 338 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Section 14 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 14.1 shows a block diagram of the keyboard buffer controller. 14.1 Features • Conforms to PS/2 interface specifications • Direct bus drive (via the KCLK and KD pins) • Interrupt sources: on completion of data reception and on detection of clock edge • Error detection: parity error and stop bit monitoring Internal data bus KBBR KDI Control logic KCLKI Parity KDO KCLKO KBCRL KBCRH KCLK (PS2AC, PS2BC, PS2CC) Register counter value KBI interrupt Legend: KD: KCLK: KBBR: KBCRH: KBCRL: KBC data I/O pin KBC clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L Figure 14.1 Block Diagram of Keyboard Buffer Controller IFKEY10A_000020020800 Rev. 2.00 Mar 21, 2006 page 339 of 518 REJ09B0299-0200 Module data bus Bus interface KD (PS2AD, PS2BD, PS2CD) Section 14 Keyboard Buffer Controller Figure 14.2 shows how the keyboard buffer controller is connected. Vcc Vcc System side KCLK in Clock KCLK out Keyboard side KCLK in KCLK out KD in KD out Data KD in KD out Keyboard buffer controller (This LSI) I/F Figure 14.2 Keyboard Buffer Controller Connection 14.2 Input/Output Pins Table 14.1 lists the input/output pins used by the keyboard buffer controller. Table 14.1 Pin Configuration Channel 0 Name KBC clock I/O pin (KCLK0) KBC data I/O pin (KD0) 1 KBC clock I/O pin (KCLK1) KBC data I/O pin (KD1) 2 KBC clock I/O pin (KCLK2) KBC data I/O pin (KD2) Abbreviation* PS2AC PS2AD PS2BC PS2BD PS2CC PS2CD I/O I/O I/O I/O I/O I/O I/O Function KBC clock input/output KBC data input/output KBC clock input/output KBC data input/output KBC clock input/output KBC data input/output Note:* These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK and data I/O pins as KD, omitting the channel designations. Rev. 2.00 Mar 21, 2006 page 340 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) • Keyboard data buffer register (KBBR) 14.3.1 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer controller. Bit 7 Bit Name KBIOE Initial Value 0 R/W R/W Description Keyboard In/Out Enable Selects whether or not the keyboard buffer controller is used. 0: The keyboard buffer controller is non-operational (KCLK and KD signal pins have port functions) 1: The keyboard buffer controller is enabled for transmission and reception (KCLK and KD signal pins are in the bus drive state) 6 KCLKI 1 R Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In: Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 4 KBFSEL 1 R/W Keyboard Buffer Register Full Select Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag. When KBFSEL is cleared to 0, the KBE bit in KBCRL should be cleared to 0 to disable reception. 0: KBF bit is used as KCLK fall interrupt flag 1: KBF bit is used as keyboard buffer register full flag Rev. 2.00 Mar 21, 2006 page 341 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Bit 3 Bit Name KBIE Initial Value 0 R/W R/W Description Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer controller to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled 2 KBF 0 R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR. 0: [Clearing condition] Read KBF when KBF = 1, then write 0 in KBF 1: [Setting conditions] • When data has been received normally and has been transferred to KBBR while KBFSEL = 1 (keyboard buffer register full flag) When a KCLK falling edge is detected while KBFSEL = 0 (KCLK interrupt flag) • 1 PER 0 R/(W)* Parity Error Indicates that an odd parity error has occurred. 0: [Clearing condition] Read PER when PER = 1, then write 0 in PER 1: [Setting condition] When an odd parity error occurs 0 KBS 0 R Keyboard Stop Indicates the receive data stop bit. Valid only when KBF = 1. 0: 0 stop bit received 1: 1 stop bit received Note: Only 0 can be written for clearing the flag. Rev. 2.00 Mar 21, 2006 page 342 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer controller pin output. Bit 7 Bit Name KBE Initial Value 0 R/W R/W Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls KBC clock I/O pin output. 0: KBC clock I/O pin is low 1: KBC clock I/O pin is high 5 KDO 1 R/W Keyboard Data Out Controls KBC data I/O pin output. 0: KBC data I/O pin is low 1: KBC data I/O pin is high 4 — 1 — Reserved This bit is always read as 1 and cannot be modified. Rev. 2.00 Mar 21, 2006 page 343 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Bit 3 2 1 0 Bit Name RXCR3 RXCR2 RXCR1 RXCR0 Initial Value 0 0 0 0 R/W R R R R Description Receive Counter These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received. 0000: — 0001: Start bit 0010: KB0 0011: KB1 0100: KB2 0101: KB3 0110: KB4 0111: KB5 1000: KB6 1001: KB7 1010: Parity bit 1011: — 11- - : — 14.3.3 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit 7 6 5 4 3 2 1 0 Bit Name KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0. Rev. 2.00 Mar 21, 2006 page 344 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4 14.4.1 Operation Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 14.3, and the receive timing in figure 14.4. Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set KBE bit Receive enabled state [1] [2] No [1] Set the KBIOE bit to 1 in KBCRH. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK. [4] When a stop bit is received, the keyboard buffer controller drives KCLK low to disable keyboard transmission (automatic I/O inhibit). If the KBIE bit is set to 1 in KBCRH, an interrupt request is sent to the CPU at the same time. [5] Perform receive data processing. [6] Clear the KBF flag to 0 in KBCRL. At the same time, the system automatically drives KCLK high, setting the receive enabled state. The receive operation can be continued by repeating steps [3] to [6]. Keyboard side in data transmission state. [3] Execute receive abort processing. KBF = 1? Yes PER = 0? Yes KBS = 1? Yes Read KBBR Receive data processing No [4] No No Error handling [5] Clear KBF flag (receive enabled state) [6] Figure 14.3 Sample Receive Processing Flowchart Rev. 2.00 Mar 21, 2006 page 345 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Flag cleared Receive processing/ error handling KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 Previous data PER KBS KBF 1 2 0 3 1 9 7 10 11 Start bit Parity bit Stop bit Automatic I/O inhibit KB0 KB1 Receive data [1] [2] [3] [4] [5] [6] Figure 14.4 Receive Timing 14.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 14.5, and the transmit timing in figure 14.6. Rev. 2.00 Mar 21, 2006 page 346 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set I/O inhibit (KCLKO = 0) KBE = 0 (KBBR reception prohibited) Wait [4] KCLKO remains at 0 [5] Clear I/O inhibit (KCLKO = 1) KDO remains at 0 Set start bit (KDO = 0) i=0 [6] No [1] [2] No [3] Write 0 in the KBE bit (prohibit KBBR receive operation). 2 KDO remains at 1 (Continued on [4] Write 0 in the KDO bit (set start bit). next page) [1] Set the KBIOE bit to 1 in KBCRH. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). [3] [5] Write 1 in the KCLKO bit (clear I/O inhibit). [6] Read KBCRH, and when KCLKI = 0, set the transmit data in the KDO bit (LSB-first). Next, set the parity bit and stop bit in the KDO bit. [7] After transmitting the stop bit, read KBCRL and confirm that KDI = 0 (receive completed notification from the keyboard). [8] Read KBCRH. Confirm that the KCLKI and KDI bits are both 1. The transmit operation can be continued by repeating steps [2] to [8]. Read KBCRH KCLKI = 0? Yes Set transmit data (KDO = D(i)) Read KBCRH KCLKI = 1? Yes i=i+1 i > 9? Yes Read KBCRH KCLKI = 1? No Note: i = 0 to 7: Transmit data i = 8: Parity bit i = 9: Stop bit No No Yes 1 (Continued on next page) Figure 14.5 (1) Sample Transmit Processing Flowchart Rev. 2.00 Mar 21, 2006 page 347 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 1 Read KBCRH KCLKI = 0? Yes KDI = 0? * Yes No No 2 [7] Keyboard side in data transmission state. Execute receive abort processing. Error handling [8] Read KBCRH KCLK = 1? Yes Transmit end state (KCLK = high, KD = high) No To receive operation or transmit operation Note:* To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 14.5 (2) Sample Transmit Processing Flowchart KCLK (pin state) KD (pin state) KCLK (output) KD (output) KCLK (input) KD (input) Receive completed notification 1 2 8 9 10 11 Start bit 0 1 7 Parity bit Stop bit I/O inhibit Start bit 0 1 7 Parity bit Stop bit [1] [2] [3] [4] [5] [6] [7] [8] Figure 14.6 Transmit Timing Rev. 2.00 Mar 21, 2006 page 348 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain period. A sample receive abort processing flowchart is shown in figure 14.7, and the receive abort timing in figure 14.8. Start [1] Read KBCRL, and if KBF = 1, perform processing 1. [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, the parity bit is being received. With the PS2 interface, a receive abort request following parity bit reception is disabled. Wait until stop bit reception is completed, perform receive data processing and clear the KBF flag, then proceed to the next operation. No Receive state Read KBCRL No KBF = 0? Yes Read KBCRH [1] Processing 1 RXCR3 to RXCR0 ≥ B'1001? Yes Disable receive abort requests [3] No [2] KCLKO = 0 (receive abort request) Retransmit command transmission (data)? Yes KBE = 0 (disable KBBR reception and clear receive counter) Set start bit (KDO = 0) Clear I/O inhibit (KCLKO = 1) Transmit data KBE = 0 (disable KBBR reception and clear receive counter) KBE = 1 (enable KB operation) Clear I/O inhibit (KCLKO = 1) To transmit operation To receive operation Figure 14.7 (1) Sample Receive Abort Processing Flowchart Rev. 2.00 Mar 21, 2006 page 349 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller Processing 1 Receive operation ends normally [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 14.7 (2) Sample Receive Abort Processing Flowchart Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. Reception in progress KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KD (input) KD (output) Receive abort request Start bit Transmit operation Figure 14.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing Rev. 2.00 Mar 21, 2006 page 350 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.4 KCLKI and KDI Read Timing Figure 14.9 shows the KCLKI and KDI read timing. T1 φ* T2 Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note:* The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.9 KCLKI and KDI Read Timing Rev. 2.00 Mar 21, 2006 page 351 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.5 KCLKO and KDO Write Timing Figure 14.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 φ* T2 Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note:* The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.10 KCLKO and KDO Write Timing Rev. 2.00 Mar 21, 2006 page 352 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.6 KBF Setting Timing and KCLK Control Figure 14.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK (pin) Internal KCLK Falling edge signal RXCR3 to RXCR0 KBF KCLK (output) 11th fall B'1010 B'0000 Automatic I/O inhibit Note:* The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 2.00 Mar 21, 2006 page 353 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.7 Receive Timing Figure 14.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 N N+1 N+2 Note:* The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.12 Receive Counter and KBBR Data Load Timing Rev. 2.00 Mar 21, 2006 page 354 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 14.13 shows the setting method and an example of operation. Start Set KBIOE KBE = 0 (KBBR reception disabled) KBFSEL = 0 KBIE = 1 (KCLK falling edge interrupts enabled) KCLK (pin state) KBF bit KCLK pin fall detected? Yes KBF = 1 (interrupt generated) Interrupt handling Clear KBF No Interrupt generated Cleared by software Interrupt generated Note:* The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in figure 14.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does not operate. Figure 14.13 Example of KCLK Input Fall Interrupt Operation Rev. 2.00 Mar 21, 2006 page 355 of 518 REJ09B0299-0200 Section 14 Keyboard Buffer Controller 14.5 14.5.1 Usage Notes KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 14.14 shows the timing of KBIOE setting and KCLK falling edge detection. T1 φ T2 KCLK (pin) Internal KCLK (KCLKI) KBIOE Falling edge signal KBFSEL KBE KBF Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing 14.5.2 Module Stop Mode Setting Keyboard buffer controller operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer controller operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 19, Power-Down Modes. Rev. 2.00 Mar 21, 2006 page 356 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Section 15 Host Interface LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33-MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports only I/O read cycle and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the host interface. 15.1 Features • Supports LPC interface I/O read cycles and I/O write cycles  Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.  Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). • Has three register sets comprising data and status registers  The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR).  Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively. A fast A20 gate function is also provided.  The I/O address can be set for channel 3. Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. • Supports SERIRQ  Host interrupt requests are transferred serially on a single signal line (SERIRQ).  On channel 1, HIRQ1 and HIRQ12 can be generated.  On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.  Operation can be switched between quiet mode and continuous mode.  The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). • Eleven interrupt sources  The LPC module can be shut down by inputting the LPCPD signal.  Three pins, PME, LSMI, and LSCI, are provided for general input/output. IFHSTL0A_010020020800 Rev. 2.00 Mar 21, 2006 page 357 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Figure 15.1 shows a block diagram of the LPC. Module data bus TWR0MW TWR1–15 IDR3 IDR2 IDR1 SIRQCR0 Cycle detection SIRQCR1 CLKRUN Parallel → serial conversion SERIRQ Serial → parallel conversion Control logic HISEL LPCPD LFRAME Address match LRESET LCLK LAD0– LAD3 H'0060/64 H'0062/66 LADR3 LSCIE LSCIB LSCI input PB1 I/O LSMIE LSMIB LSMI input PB0 I/O PMEE PMEB PME input P80 I/O HICR0 LSCI Serial ← parallel conversion LSMI SYNC output TWR0SW TWR1–15 ODR3 ODR2 ODR1 STR3 STR2 STR1 PME HICR1 HICR2 HICR3 GA20 Internal interrupt control IBFI1 IBFI2 IBFI3 ERRI Legend: HICR0 to HICR3: Host interface control registers 0 to 3 LADR3H, 3L: LPC channel 3 address register 3H and 3L IDR1 to IDR3: Input data registers 1 to 3 ODR1 to DOR3: Output data registers 1 to 3 STR1 to STR3: Status registers 1 to 3 TWR0MW: Two-way register 0MW TWR0SW: Two-way register 0SW TWR1 to TWR15: Two-way data registers 1 to 15 SERIRQ0, 1: SERIEQ control registers 0 and 1 HISEL: Host interface select register Figure 15.1 Block Diagram of LPC Rev. 2.00 Mar 21, 2006 page 358 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.2 Input/Output Pins Table 15.1 lists the input and output pins of the LPC module. Table 15.1 Pin Configuration Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Abbreviation Port I/O Function Serial (4-signal-line) transfer cycle type/address/data signals, synchronized with LCLK Transfer cycle start and forced termination signal LPC interface reset signal 33 MHz PCI clock signal Serialized host interrupt request signal, synchronized with LCLK (SMI, IRQ1, IRQ6, IRQ9 to IRQ12) General output General output General output A20 gate control signal output LCLK restart request signal in case of serial host interrupt request LPC module shutdown signal LAD3 to LAD0 P33 to P30 Input/ output LFRAME LRESET LCLK P34 P35 P36 P37 1 Input* 1 Input* Input Input/ 1 output* Output* * Output* * Output* * 12 Serialized interrupt SERIRQ request LSCI general output LSMI general output PME general output GATE A20 LPC clock run LPC power-down LSCI LSMI PME GA20 CLKRUN LPCPD PB1 PB0 P80 P81 P82 P83 12 12 12 Output* * Input/ 12 output* * 1 Input* Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an external resistor is necessary to pull the signal up to VCC. Rev. 2.00 Mar 21, 2006 page 359 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3 Register Descriptions The LPC has the following registers. The settings of the HI12E bit in SYSCR2 do not affect the operation of the LPC. For reasons relating to the configuration of the program development tool (emulator), when the LPC is used, the HI12E bit in SYSCR2 should not be set to 1. For details, see section 3.2.2, System Control Register (SYSCR), and section 7.7.4, System Control Register 2 (SYSCR2). • Host interface control register 0 (HICR0) • Host interface control register 1 (HICR1) • Host interface control register 2 (HICR2) • Host interface control register 3 (HICR3) • LPC channel 3 address registers (LADR3H, LADR3L) • Input data register 1 (IDR1) • Output data register 1 (ODR1) • Status register 1 (STR1) • Input data register 2 (IDR2) • Output data register 2 (ODR2) • Status register 2 (STR2) • Input data register 3 (IDR3) • Output data register 3 (ODR3) • Status register 3 (STR3) • Bidirectional data registers 0 to 15 (TWR0 to TWR15) • SERIRQ control register 0 (SIRQCR0) • SERIRQ control register 1 (SIRQCR1) • Host interface select register (HISEL) Rev. 2.00 Mar 21, 2006 page 360 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface. • HICR0 R/W Bit 7 6 5 Bit Name Initial Value Slave Host Description LPC3E LPC2E LPC1E 0 0 0 R/W R/W R/W — — — LPC Enable 3 to 1 Enable or disable the host interface function in single-chip mode. When the host interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave processor (this LSI) and the host processor is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. • LPC3E 0: LPC channel 3 operation is disabled No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15 1: LPC channel 3 operation is enabled • LPC2E 0: LPC channel 2 operation is disabled No address (H'0062, 66) matches for IDR2, ODR2, or STR2 1: LPC channel 2 operation is enabled • LPC1E 0: LPC channel 1 operation is disabled No address (H'0060, 64) matches for IDR1, ODR1, or STR1 1: LPC channel 1 operation is enabled Rev. 2.00 Mar 21, 2006 page 361 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description FGA20E 0 R/W — Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output. When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1. 0: Fast A20 gate function disabled • • • 3 SDWNE 0 R/W — Other function of pin P81 is enabled GA20 output internal state is initialized to 1 GA20 pin output is open-drain (external VCC pullup resistor required) 1: Fast A20 gate function enabled LPC Software Shutdown Enable Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 15.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state, LPC software shutdown setting enabled [Clearing conditions] • • • Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown release (rising edge of LPCPD signal) Hardware shutdown state when LPCPD signal is low 1: LPC hardware shutdown state setting enabled • [Setting condition] Writing 1 after reading SDWNE = 0 Rev. 2.00 Mar 21, 2006 page 362 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description PMEE 0 R/W — PME output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC. When the PME output function is used, the DDR bit for P80 must not be set to 1. PMEE 0 1 1 1 LSMIE 0 R/W — PMEB x: PME output disabled, other function of pin is enabled 0: PME output enabled, PME pin output goes to 0 level 1: PME output enabled, PME pin output is high-impedance LSMI output Enable Controls LSMI output in combination with the LSMIB bit in HICR1. LSMI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC. When the LSMI output function is used, the DDR bit for PB0 must not be set to 1. LSMIE LSMIB 0 1 1 x: LSMI output disabled, other function of pin is enabled 0: LSMI output enabled, LSMI pin output goes to 0 level 1: LSMI output enabled, LSMI pin output is high-impedance Rev. 2.00 Mar 21, 2006 page 363 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description LSCIE 0 R/W — LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the LSCI output function is used, the DDR bit for PB1 must not be set to 1. LSCIE 0 1 1 Legend: X: Don't care LSCIB x: LSCI output disabled, other function of pin is enabled 0: LSCI output enabled, LSCI pin output goes to 0 level 1: LSCI output enabled, LSCI pin output is high-impedance Rev. 2.00 Mar 21, 2006 page 364 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) • HICR1 R/W Bit 7 Bit Name Initial Value Slave Host Description LPCBSY 0 R — LPC Busy Indicates that the host interface is processing a transfer cycle. 0: Host interface is in transfer cycle wait state • • Bus idle, or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown Forced termination (abort) of transfer cycle subject to processing Normal termination of transfer cycle subject to processing [Clearing conditions] • • • • 1: Host interface is performing transfer cycle processing [Setting condition] Match of cycle type and address Rev. 2.00 Mar 21, 2006 page 365 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 6 Bit Name Initial Value Slave Host Description CLKREQ 0 R — LCLK Request Indicates that the host interface’s SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] • • • • LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown SERIRQ is set to continuous mode There are no further interrupts for transfer to the host in quiet mode 1: LCLK restart request issued [Setting condition] In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped 5 IRQBSY 0 R — SERIRQ Busy Indicates that the host interface’s SERIRQ signal is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] • • • LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame 1: SERIRQ transfer processing in progress [Setting condition] Start of SERIRQ transfer frame Rev. 2.00 Mar 21, 2006 page 366 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description LRSTB 0 — — LPC Software Reset Bit Resets the host interface. For the scope of initialization by an LPC reset, see section 15.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] • • Writing 0 LPC hardware reset 1: LPC software reset state [Setting condition] Writing 1 after reading LRSTB = 0 3 SDWNB 0 R/W — LPC Software Shutdown Bit Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 15.4.4, Host Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] • • • • Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1: LPC software shutdown state [Setting condition] Writing 1 after reading SDWNB = 0 2 PMEB 0 R/W — PME Output Bit Controls PME output in combination with the PMEE bit. For details, refer to description on the PMEE bit in HICR0. 1 LSMIB 0 R/W — LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0. Rev. 2.00 Mar 21, 2006 page 367 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description LSCIB 0 R/W — LSCI output Bit Controls LSCI output in combination with the LSCIE bit in HICR1. For details, refer to description on the LSCIE bit. 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states. The pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing. • HICR2 R/W Bit 7 6 Bit Name Initial Value Slave Host Description GA20 LRST Undefined 0 R — GA20 Pin Monitor LPC Reset Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware reset occurs. 0: [Clearing condition] Writing 0 after reading LRST = 1 1: [Setting condition] LRESET pin falling edge detection 5 SDWN 0 R/(W)* — LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] • • Writing 0 after reading SDWN = 1 LPC hardware reset and LPC software reset R/(W)* — 1: [Setting condition] LPCPD pin falling edge detection Rev. 2.00 Mar 21, 2006 page 368 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description ABRT 0 R/(W)* — LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] • • • Writing 0 after reading ABRT = 1 LPC hardware reset and LPC software reset LPC hardware shutdown and LPC software shutdown 1: [Setting condition] LFRAME pin falling edge detection during LPC transfer cycle 3 IBFIE3 0 R/W — IDR3 and TWR Receive Completion Interrupt Enable Enables or disables IBFI3 interrupt to the slave processor (this LSI). 0: Input data register IDR3 and TWR receive completed interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive completed interrupt requests enabled [When TWRIE = 1 in LADR3] Input data register (IDR3) and TWR receive completed interrupt requests enabled 2 IBFIE2 0 R/W — IDR2 Receive Completion Interrupt Enable Enables or disables IBFI2 interrupt to the slave processor (this LSI). 0: Input data register (IDR2) receive completed interrupt requests disabled 1: Input data register (IDR2) receive completed interrupt requests enabled Rev. 2.00 Mar 21, 2006 page 369 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description IBFIE1 0 R/W — IDR1 Receive Completion Interrupt Enable Enables or disables IBFI1 interrupt to the slave processor (this LSI). 0: Input data register (IDR1) receive completed interrupt requests disabled 1: Input data register (IDR1) receive completed interrupt requests enabled 0 ERRIE 0 R/W — Error Interrupt Enable Enables or disables ERRI interrupt to the slave processor (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled Note: * Only 0 can be written to bits 6 to 4, to clear the flag. • HICR3 R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ LRESET LPCPD PME LSMI LSCI Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R — — — — — — — — LFRAME Pin Monitor CLKRUN Pin Monitor SERIRQ Pin Monitor LRESET Pin Monitor LPCPD Pin Monitor PME Pin Monitor LSMI Pin Monitor LSCI Pin Monitor Rev. 2.00 Mar 21, 2006 page 370 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). • LADR3H Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Channel 3 Address Bits 15 to 8: When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 of LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored. Register selection according to the bits ignored in address match determination is as shown in table 15.2. • LADR3L Bit 7 6 5 4 3 2 Bit Name Initial Value R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3  0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Reserved This bit is readable/writable, however, only 0 should be written to this bit. 1 0 Bit 1 TWRE 0 0 R/W R/W Channel 3 Address Bit 1 Bidirectional Data Register Enable Enables or disables bidirectional data register operation. 0: TWR operation is disabled TWR-related I/O address match determination is halted 1: TWR operation is enabled Description Channel 3 Address Bits 7 to 3 Rev. 2.00 Mar 21, 2006 page 371 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Table 15.2 Register Selection I/O Address Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 0 0 1 0 0 1 Bit 2 0 1 0 1 0 0 1 0 0 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 0 1 0 0 1 Bit 0 0 0 0 0 0 1 1 0 1 1 I/O read I/O read TWR0SW read TWR1 to TWR15 read Transfer Cycle I/O write I/O write I/O read I/O read I/O write I/O write Host Register Selection IDR3 write, C/D3 ← 0 IDR3 write, C/D3 ← 1 ODR3 read STR3 read TWR0MW write TWR1 to TWR15 write 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit writeonly registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on IDR3 selection, see section 15.3.3, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of IDR1 to IDR3 are undefined. I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 0000 0000 0110 0000 0000 0110 Bit 3 0 0 0 0 Bit 2 0 1 0 1 Bit 1 0 0 1 1 Bit 0 0 0 0 0 Transfer Cycle I/O write I/O write I/O write I/O write Host Register Selection IDR1 write, C/D1 ← 0 IDR1 write, C/D1 ← 1 IDR2 write, C/D2 ← 0 IDR2 write, C/D2 ← 1 Rev. 2.00 Mar 21, 2006 page 372 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit read-only registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 selection, see section 15.3.3, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of ODR1 to ODR3 are undefined. I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 Bit 3 0 0 Bit 2 0 0 Bit 1 0 1 Bit 0 0 0 Transfer Cycle I/O read I/O read Host Register Selection ODR1 read ODR2 read 15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) The TWR registers are sixteen 8-bit readable/writable registers to both the slave processor (this LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address. TWR0MW is a write-only register for the host processor, and a read-only register for the slave processor, while TWR0SW is a write-only register for the slave processor and a read-only register for the host processor. When the host and slave processors begin a write, after the respective TWR0 registers have been written to, access right arbitration for simultaneous access is performed by checking the status flags to see if those writes were valid. For the registers selected from the host according to the I/O address, see section 15.3.3, LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 are undefined. Rev. 2.00 Mar 21, 2006 page 373 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3.7 Status Registers 1 to 3 (STR1 to STR3) The STR registers are 8-bit registers that indicate status information during host interface processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits for both the host processor and the slave processor (this LSI). However, only 0 can be written to bit 0 of STR1 to STR3 and bits 6 and 4 of STR3, from the slave processor (this LSI), in order to clear the flags to 0. The registers selected from the host processor according to the I/O address are shown in the following table. For information on STR3 selection, see section 15.3.3, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host processor. The initial values of STR1 to STR3 are H'00. I/O Address Bits 15 to 4 0000 0000 0110 0000 0000 0110 Bit 3 0 0 Bit 2 1 1 Bit 1 0 1 Bit 0 0 0 Transfer Cycle I/O read I/O read Host Register Selection STR1 read STR2 read Rev. 2.00 Mar 21, 2006 page 374 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) • STR1 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU17 DBU16 DBU15 DBU14 C/D1 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU12 IBF1 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details, see table 15.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF1 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. Cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. Defined by User The user can use these bits as necessary. Rev. 2.00 Mar 21, 2006 page 375 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) • STR2 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU27 DBU26 DBU25 DBU24 C/D2 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU22 IBF2 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details, see table 15.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF2 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. Cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. Defined by User The user can use these bits as necessary. Rev. 2.00 Mar 21, 2006 page 376 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit 7 Bit Name Initial Value Slave Host Description IBF3B 0 R R Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor (this LSI). IBF3B is cleared to 0 when the slave processor reads TWR15. 0: [Clearing condition] When the slave processor reads TWR15 1: [Setting condition] When the host processor writes to TWR15 using I/O write cycle 6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full Set to 1 when the slave processor (this LSI) writes to TWR15. OBF3B is cleared to 0 when the host processor reads TWR15. 0: [Clearing condition] When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 to the OBF3B bit 1: [Setting condition] When the slave processor writes to TWR15 5 MWMF 0 R R Master Write Mode Flag Set to 1 when the host processor writes to TWR0. MWMF is cleared to 0 when the slave processor (this LSI) reads TWR15. 0: [Clearing condition] When the slave processor reads TWR15 1: [Setting condition] When the host processor writes to TWR0 using I/O write cycle while SWMF = 0 Rev. 2.00 Mar 21, 2006 page 377 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description SWMF 0 R/(W)* R Slave Write Mode Flag Set to 1 when the slave processor (this LSI) writes to TWR0. In the event of simultaneous writes by the master and the slave, the master write has priority. SWMF is cleared to 0 when the host reads TWR15 0: [Clearing condition] When the host processor reads TWR15 using I/O read cycle, or the slave processor writes 0 to the SWMF bit 1: [Setting condition] When the slave processor writes to TWR0 while MWMF = 0 3 C/D3 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details, see table 15.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle Rev. 2.00 Mar 21, 2006 page 378 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description OBF3A 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. OBF is cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. Rev. 2.00 Mar 21, 2006 page 379 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) • STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU37 DBU36 DBU35 DBU34 C/D3 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full Set to 1 when the host processor writes to IDR. This bit is an internal interrupt source to the slave processor (this LSI). IBF is cleared to 0 when the slave processor reads IDR. The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details, see table 15.3. 0: [Clearing condition] When the slave processor reads IDR 1: [Setting condition] When the host processor writes to IDR using I/O write cycle 0 OBF3A 0 R/(W)* R Output Buffer Full Set to 1 when the slave processor (this LSI) writes to ODR. OBF is cleared to 0 when the host processor reads ODR. 0: [Clearing condition] When the host processor reads ODR using I/O read cycle, or the slave processor writes 0 to the OBF bit 1: [Setting condition] When the slave processor writes to ODR Note: * Only 0 can be written to clear the flag. Rev. 2.00 Mar 21, 2006 page 380 of 518 REJ09B0299-0200 Defined by User The user can use these bits as necessary. Section 15 Host Interface LPC Interface (LPC) 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. • SIRQCR0 R/W Bit 7 Bit Name Initial Value Slave Host Description Q/C 0 R — Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] • • LPC hardware reset, LPC software reset Specification by SERIRQ transfer cycle stop frame 1: Quiet mode [Setting condition] Specification by SERIRQ transfer cycle stop frame. 6 SELREQ 0 R/W — Start Frame Initiation Request Select Selects whether start frame initiation is requested when one or more interrupt requests are cleared, or when all interrupt requests are cleared, in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared in quiet mode. 1: Start frame initiation is requested when one or more interrupt requests are cleared in quiet mode. 5 IEDIR 0 R/W — Interrupt Enable Direct Mode Specifies whether LPC channel 2 and channel 3 SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11) generation is conditional upon OBF, or is controlled only by the host interrupt enable bit. 0: Host interrupt is requested when host interrupt enable bit and corresponding OBF are both set to 1 1: Host interrupt is requested when host interrupt enable bit is set to 1 Rev. 2.00 Mar 21, 2006 page 381 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description SMIE3B 0 R/W — Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] • • • Writing 0 to SMIE3B LPC hardware reset, LPC software reset Clearing OBF3B to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3B = 0 3 SMIE3A 0 R/W — Host SMI Interrupt Enable 3A Enables or disables a host SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] • • • Writing 0 to SMIE3A LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3A = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 2.00 Mar 21, 2006 page 382 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description SMIE2 0 R/W — Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] • • • Writing 0 to SMIE2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE2 = 0 1 IRQ12E1 0 R/W — Host IRQ12 Interrupt Enable 1 Enables or disables a host IRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: Host IRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] • • • Writing 0 to IRQ12E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: [When IEDIR = 0] 1: Host IRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ12E1 = 0 Rev. 2.00 Mar 21, 2006 page 383 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ1E1 0 R/W — Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: Host IRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] • • • Writing 0 to IRQ1E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: Host IRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ1E1 = 0 • SIRQCR1 R/W Bit 7 Bit Name Initial Value Slave Host Description IRQ11E3 0 R/W — Host IRQ11 Interrupt Enable 3 Enables or disables a host IRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ11 interrupt request by OBF3A and IRQ11E3 is disabled [Clearing conditions] • • • Writing 0 to IRQ11E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ11 interrupt is requested. [Setting condition] Writing 1 after reading IRQ11E3 = 0 1: [When IEDIR = 0] Rev. 2.00 Mar 21, 2006 page 384 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 6 Bit Name Initial Value Slave Host Description IRQ10E3 0 R/W — Host IRQ10 Interrupt Enable 3 Enables or disables a host IRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ10 interrupt request by OBF3A and IRQ10E3 is disabled [Clearing conditions] • • • Writing 0 to IRQ10E3 LPC hardware reset, LPC software reset Clearing OB3FA to 0 (when IEDIR = 0) Host IRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ10 interrupt is requested. [Setting condition] Writing 1 after reading IRQ10E3 = 0 5 IRQ9E3 0 R/W — Host IRQ9 Interrupt Enable 3 Enables or disables a host IRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ9 interrupt request by OBF3A and IRQ9E3 is disabled [Clearing conditions] • • • Writing 0 to IRQ9E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ9 interrupt is requested. [Setting condition] Writing 1 after reading IRQ9E3 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 2.00 Mar 21, 2006 page 385 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description IRQ6E3 0 R/W — Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: Host IRQ6 interrupt request by OBF3A and IRQ6E3 is disabled [Clearing conditions] • • • Writing 0 to IRQ6E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR = 0) Host IRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR = 1] Host IRQ6 interrupt is requested. [Setting condition] Writing 1 after reading IRQ6E3 = 0 3 IRQ11E2 0 R/W — Host IRQ11 Interrupt Enable 2 Enables or disables a host IRQ11 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ11 interrupt request by OBF2 and IRQ11E2 is disabled [Clearing conditions] • • • Writing 0 to IRQ11E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ11 interrupt is requested. [Setting condition] Writing 1 after reading IRQ11E2 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 2.00 Mar 21, 2006 page 386 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description IRQ10E2 0 R/W — Host IRQ10 Interrupt Enable 2 Enables or disables a host IRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ10 interrupt request by OBF2 and IRQ10E2 is disabled [Clearing conditions] • • • Writing 0 to IRQ10E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ10 interrupt is requested. [Setting condition] Writing 1 after reading IRQ10E2 = 0 1 IRQ9E2 0 R/W — Host IRQ9 Interrupt Enable 2 Enables or disables a host IRQ9 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ9 interrupt request by OBF2 and IRQ9E2 is disabled [Clearing conditions] • • • Writing 0 to IRQ9E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) Host IRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ9 interrupt is requested. [Setting condition] Writing 1 after reading IRQ9E2 = 0 1: [When IEDIR = 0] 1: [When IEDIR = 0] Rev. 2.00 Mar 21, 2006 page 387 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ6E2 0 R/W — Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request when OBF2 is set by an ODR2 write. 0: Host IRQ6 interrupt request by OBF2 and IRQ6E2 is disabled [Clearing conditions] • • • Writing 0 to IRQ6E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR = 0) 1: [When IEDIR = 0] Host IRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] Host IRQ6 interrupt is requested. [Setting condition] Writing 1 after reading IRQ6E2 = 0 Rev. 2.00 Mar 21, 2006 page 388 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt request signal of each frame. R/W Bit 7 Bit Name Initial Value Slave Host Description SELSTR3 0 W — STR3 Register Function Select 3 Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. See description on STR3 in section 15.3.7, Status Registers 1 to 3 (STR1 to STR3), for details. 0: Bits 7 to 4 in STR3 are status bits of the host interface. 1: [When TWRE = 1] Bits 7 to 4 in STR3 are status bits of the host interface. [When TWRE = 0] Bits 7 to 4 in STR3 are user bits. 6 5 4 3 2 1 0 SELIRQ11 0 SELIRQ10 0 SELIRQ9 0 SELIRQ6 0 SELSMI 0 SELIRQ12 1 SELIRQ1 1 W W W W W W W — — — — — — — SERIRQ Output Select Selects the pin output status of host interrupt requests (HIRQ11, HIRQ10, HIRQ9, HIRQ6, SMI, HIRQ12, and HIRQ1) of the LPC. 0: [When host interrupt request is cleared] SERIRQ pin output is in the high-impedance state. [When host interrupt request is set] SERIRQ pin output is 0. 1: [When host interrupt request is cleared] SERIRQ pin output is 0. [When host interrupt request is set] SERIRQ pin output is in the high-impedance state. Rev. 2.00 Mar 21, 2006 page 389 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.4 15.4.1 Operation Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in singlechip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports PB0 and PB1) to the host interface’s input/output pins. Use the following procedure to activate the host interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether bidirectional data registers are to be used. 3. Set the enable bit (LPC3E to LPC1E) for the channel to be used. 4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 5. Set the selection bits for other functions (SDWNE, IEDIR). 6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15 to clear IBF. 7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary. Rev. 2.00 Mar 21, 2006 page 390 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.4.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B′0000 in the slave’s synchronization return cycle, but with the chip’s LPC a value of B′0000 is always returned. If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the host interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed. I/O Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Contents Start Address 1 Address 2 Address 3 Address 4 Turnaround (recovery) Turnaround Synchronization Data 1 Data 2 Turnaround (recovery) Turnaround Drive Source Host Host Host Host Host Host None Slave Slave Slave Slave None Value (3 to 0) 0000 0000 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 Turnaround (recovery) Turnaround Synchronization Turnaround (recovery) Turnaround I/O Write Cycle Drive Source Host Host Host Host Host Host Host Host None Slave Slave None Value (3 to 0) 0000 0010 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ Cycle type/direction Host Cycle type/direction Host Rev. 2.00 Mar 21, 2006 page 391 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3. LCLK LFRAME LAD3–LAD0 Start Cycle type, direction, and size ADDR TAR Sync Data TAR Start Number of clocks 1 1 4 2 1 2 2 1 Figure 15.2 Typical LFRAME Timing LFRAME LCLK LFRAME LAD3–LAD0 Start Cycle type, direction, and size ADDR TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 15.3 Abort Mechanism Rev. 2.00 Mar 21, 2006 page 392 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.4.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it at the gate A20 pin. Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E = 0. When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. The state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2. The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1 register. The host interface decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 15.3 shows the conditions that set and clear GA20 (P81). Figure 15.4 shows the GA20 output in flowchart form. Table 15.4 indicates the GA20 output signal values. Table 15.3 GA20 (P81) Set/Clear Timing Pin Name GA20 (P81) Setting Condition When bit 1 of the data that follows an H'D1 host command is 1 Clearing Condition When bit 1 of the data that follows an H'D1 host command is 0 Rev. 2.00 Mar 21, 2006 page 393 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 15.4 GA20 Output Rev. 2.00 Mar 21, 2006 page 394 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Table 15.4 Fast A20 Gate Output Signals Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Turn-off sequence (abbreviated form) Turn-on sequence (abbreviated form) Turn-off sequence HA0 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 Data/Command H'D1 command 1 1 data* H'FF command H'D1 command 2 0 data* H'FF command H'D1 command 1 data* 1 Remarks Turn-on sequence Command other than H'FF and H'D1 H'D1 command 0 data* 2 Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command Notes: 1. Arbitrary data with bit 1 set to 1. 2. Arbitrary data with bit 1 cleared to 0. Rev. 2.00 Mar 21, 2006 page 395 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave processor in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. Place the slave processor in sleep mode or software standby mode as necessary. 8. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means. Rev. 2.00 Mar 21, 2006 page 396 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Table 15.5 shows the scope of the host interface pin shutdown. Table 15.5 Scope of Host Interface Pin Shutdown Abbreviation LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD Port P33 to P30 P34 P35 P36 P37 PB1 PB0 P80 P81 P82 P83 Scope of Shutdown O O × O O ∆ ∆ ∆ ∆ O × I/O I/O Input Input Input I/O I/O I/O I/O I/O Input Input Notes Hi-Z Hi-Z LPC hardware reset function is active Hi-Z Hi-Z Hi-Z, only when LSCIE = 1 Hi-Z, only when LSMIE = 1 Hi-Z, only when PMEE = 1 Hi-Z, only when FGA20E = 1 Hi-Z Needed to clear shutdown state Legend: O: Pin that is shutdown by the shutdown function ∆: Pin that is shutdown only when the LPC function is selected by register setting ×: Pin that is not shutdown In the LPC shutdown state, the LPC’s internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by STBY or RES pin input, or WDT0 overflow)  All register bits, including bits LPC3E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input)  LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB)  SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown  SDWNB bit is cleared to 0. 5. LPC software shutdown Rev. 2.00 Mar 21, 2006 page 397 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) The scope of the initialization in each mode is shown in table 15.6. Table 15.6 Scope of Initialization in Each Host Interface Mode Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags Host interface flags (IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1, OBF2, OBF3A, OBF3B, SWMF, DBU), GA20 (internal state) System Reset Initialized Initialized Initialized LPC Reset Initialized Initialized Initialized LPC Shutdown Initialized Initialized Retained Host interrupt enable bits Initialized (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3), Q/C flag, SELREQ bit LRST flag SDWN flag LRSTB bit SDWNB bit SDWNE bit Initialized (0) Initialized (0) Initialized (0) Initialized (0) Initialized (0) Initialized Retained Can be set/cleared Initialized (0) HR: 0 SR: 1 Initialized (0) Initialized (0) Retained Can be set/cleared Can be set/cleared 0 (can be set) HS: 0 SS: 1 HS: 1 SS: 0 or 1 Retained Host interface operation control bits Initialized (LPC3E to LPC1E, FGA20E, LADR3, IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6, SELIRQ9, SELIRQ10, SELIRQ11, SELIRQ12) LRESET signal LPCPD signal LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals PME, LSMI, LSCI, GA20 signals (when function is selected) PME, LSMI, LSCI, GA20 signals (when function is not selected) Rev. 2.00 Mar 21, 2006 page 398 of 518 REJ09B0299-0200 Input (port Input function Input Input Output Input Input Hi-Z Hi-Z Port function Port function Section 15 Host Interface LPC Interface (LPC) Note: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS) Figure 15.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3–LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 15.5 Power-Down State Termination Timing Rev. 2.00 Mar 21, 2006 page 399 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 15.6. SL or H LCLK SERIRQ Drive source IRQ1 START Host controller None IRQ1 None Start frame H R T IRQ0 frame S R T IRQ1 frame S R T IRQ2 frame S R T IRQ14 frame S LCLK SERIRQ Driver Legend: H: Host control SL: Slave control R: Recovery None R T IRQ15 frame S R T IOCHCK frame S R T I Stop frame H R T Next cycle STOP IRQ15 None Host controller START T: Turnaround S: Sample I: Idle Figure 15.6 SERIRQ Timing The frame configuration of the serialized interrupt transfer cycle is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave processor that was driving the preceding state. Rev. 2.00 Mar 21, 2006 page 400 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Table 15.7 Frame Configuration of Serial Interrupt Transfer Cycle Serial Interrupt Transfer Cycle Frame Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK Stop Drive Source Slave Host Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Host Number of States 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Undefined First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next Drive possible in LPC channels 2 and 3 Drive possible in LPC channels 2 and 3 Drive possible in LPC channels 2 and 3 Drive possible in LPC channel 1 Drive possible in LPC channels 2 and 3 Drive possible in LPC channel 1 Drive possible in LPC channels 2 and 3 Notes In quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host There are two modes—continuous mode and quiet mode—for serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the powerRev. 2.00 Mar 21, 2006 page 401 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) down state. In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. For details, see section 15.4.6, Host Interface Clock Start Request (CLKRUN). 15.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 15.7. CLK 1 CLKRUN 2 3 4 5 6 Pull-up enable Drive by the slave processor Drive by the host processor Figure 15.7 Clock Start Request Timing Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. Rev. 2.00 Mar 21, 2006 page 402 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) 15.5 15.5.1 Interrupt Sources IBFI1, IBFI2, IBFI3, and ERRI The host interface has four interrupt requests for the slave processor (this LSI): IBF1 to IBF3, and ERRI. IBFI1 to IBFI3 are IDR receive complete interrupts for IDR1 to IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding enable bit. Table 15.8 Receive Complete Interrupts and Error Interrupt Interrupt IBFI1 IBFI2 IBFI3 ERRI Description When IBFIE1 is set to 1 and IDR1 reception is completed When IBFIE2 is set to 1 and IDR2 reception is completed When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1 15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9 to HIRQ11 can be requested from LPC channel 2 or 3. There are two ways of clearing a host interrupt request. When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3, IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective functional differences. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. Rev. 2.00 Mar 21, 2006 page 403 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Table 15.9 summarizes the methods of setting and clearing these bits, and Figure 15.8 shows the processing flowchart. Table 15.9 HIRQ Setting and Clearing Conditions Host Interrupt HIRQ1 (independent from IEDIR) HIRQ12 (independent from IEDIR) SMI (IEDIR = 0) Setting Condition Clearing Condition Internal CPU writes to ODR1, then reads Internal CPU writes 0 to bit IRQ1E1, 0 from bit IRQ1E1 and writes 1 or host reads ODR1 Internal CPU writes to ODR1, then reads Internal CPU writes 0 to bit IRQ12E1, 0 from bit IRQ12E1 and writes 1 or host reads ODR1 Internal CPU • • • Internal CPU writes 0 to bit SMIE2, or host reads ODR2 writes 0 to bit SMIE3A, or host reads ODR3 writes 0 to bit SMIE3B, or host reads TWR15 writes 0 to bit SMIE2 writes 0 to bit SMIE3A writes 0 to bit SMIE3B writes to ODR2, then reads 0 from bit • SMIE2 and writes 1 writes to ODR3, then reads 0 from bit • SMIE3A and writes 1 writes to TWR15, then reads 0 from bit SMIE3B and writes 1 • SMI (IEDIR = 1) Internal CPU • • • reads 0 from bit SMIE3A, then writes 1 reads 0 from bit SMIE3B, then writes 1 Internal CPU • • reads 0 from bit SMIE2, then writes 1 • HIRQi (i = 6, 9 to 11) (IEDIR = 0) Internal CPU • • Internal CPU writes 0 to bit IRQiE2, or host reads ODR2 CPU writes 0 to bit IRQiE3, or host reads ODR3 writes 0 to bit IRQiE2 writes 0 to bit IRQiE3 writes to ODR2, then reads 0 from bit • IRQiE2 and writes 1 writes to ODR3, then reads 0 from bit • IRQiE3 and writes 1 reads 0 from bit IRQiE2, then writes 1 • reads 0 from bit IRQiE3, then writes 1 • HIRQi (i = 6, 9 to 11) (IEDIR = 1) Internal CPU • • Internal CPU Rev. 2.00 Mar 21, 2006 page 404 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Slave CPU Master CPU ODR1 write Interrupt initiation ODR1 read Write 1 to IRQ1E1 SERIRQ IRQ1 output SERIRQ IRQ1 source clearance No OBF1 = 0? Yes All bytes transferred? Hardware operation Yes Software operation No Figure 15.8 HIRQ Flowchart (Example of Channel 1) 15.6 15.6.1 Usage Notes Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop control register. The initial setting is for LPC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 19, Power-Down Modes. 15.6.2 Notes on Using Host Interface The host interface provides buffering of asynchronous data from the host processor and slave processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data contention. For example, if the host and slave processor both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. Rev. 2.00 Mar 21, 2006 page 405 of 518 REJ09B0299-0200 Section 15 Host Interface LPC Interface (LPC) Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 15.10 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15 when LADR3 = H'A24F and LADR3 = H'3FD0. Table 15.10 Host Address Example Register IDR3 ODR3 STR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Host Address when LADR3 = H'A24F H'A24A and H'A24E H'A24A H'A24E H'A250 H'A250 H'A251 H'A252 H'A253 H'A254 H'A255 H'A256 H'A257 H'A258 H'A259 H'A25A H'A25B H'A25C H'A25D H'A25E H'A25F Host Address when LADR3 = H'3FD0 H'3FD0 and H'3FD4 H'3FD0 H'3FD4 H'3FC0 H'3FC0 H'3FC1 H'3FC2 H'3FC3 H'3FC4 H'3FC5 H'3FC6 H'3FC7 H'3FC8 H'3FC9 H'3FCA H'3FCB H'3FCC H'3FCD H'3FCE H'3FCF Rev. 2.00 Mar 21, 2006 page 406 of 518 REJ09B0299-0200 Section 16 RAM Section 16 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version H8S/2110B RAM Capacitance 2 kbytes RAM Address H'E880 to H'EFFF, H'FF00 to H'FF7F Rev. 2.00 Mar 21, 2006 page 407 of 518 REJ09B0299-0200 Section 16 RAM Rev. 2.00 Mar 21, 2006 page 408 of 518 REJ09B0299-0200 Section 17 ROM Section 17 ROM This LSI has an on-chip ROM (flash memory or masked ROM). The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 17.1. 17.1 • Size Features ROM Capacitance 64 kbytes ROM Address H'000000 to H'00FFFF (mode 2) H'0000 to H'DFFF (mode 3) Product Classification H8S/2110B • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows:  8 k6bytes × 2 blocks, 16 kbytes × 1 block, 28 kbytes × 1 block, and 1 kbyte × 4 blocks To erase the entire flash memory, each block must be erased in turn. • Programming/erase time It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 µs (typ.) per 1 byte. Erasing one block takes 100 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • Two flash memory on-board programming modes  Boot mode  User program mode On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erase or programming of the entire flash memory. In user program mode, individual blocks can be erased or programmed. • Automatic bit rate adjustment With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. • Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. Rev. 2.00 Mar 21, 2006 page 409 of 518 REJ09B0299-0200 Section 17 ROM • Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer. Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Module bus EBR1 EBR2 Bus interface/controller Operating mode Mode pin Flash memory (64 kbytes) Legend: FLMCR1 FLMCR2 EBR1 EBR2 : Flash memory control register 1 : Flash memory control register 2 : Erase block register 1 : Erase block register 2 Figure 17.1 Block Diagram of Flash Memory Rev. 2.00 Mar 21, 2006 page 410 of 518 REJ09B0299-0200 Section 17 ROM 17.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 17.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 17.1. Figure 17.3 shows the boot mode and figure 17.4 shows the user program mode. MD1 =1 Reset state 0 User mode (on-chip ROM enabled) FLSHE = 0 SWE = 0 = RES RES = 0 *2 = 0 FLSHE = 1 SWE = 1 RE *1 RES = 0 S Programmer mode User program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD1 = MD0 = 0, P92 = P91 = P90 = 1 2. MD1 = MD0 = 0, P92 = 0, P91 = P90 = 1 Boot mode On-board programming mode Figure 17.2 Flash Memory State Transitions Table 17.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Program/program-verify Erase/erase-verify Note: * Should be provided by the user, in accordance with the recommended algorithm. Rev. 2.00 Mar 21, 2006 page 411 of 518 REJ09B0299-0200 Section 17 ROM 1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Programming control program New application program Boot program SCI 2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked. Then the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. New application program Boot program SCI Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. 4. Writing new application program The programming control program transferred from the host to RAM via SCI communication is executed, and the new application program in the host is written into the flash memory. New application program Boot program SCI Boot program New application program SCI Boot program area Flash memory erase Programming control program Boot program area Programming control program Program execution state Figure 17.3 Boot Mode Rev. 2.00 Mar 21, 2006 page 412 of 518 REJ09B0299-0200 Section 17 ROM 1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Programming/ erase control program New application program Boot program Transfer program SCI Boot program Transfer program Programming/ erase control program Application program (old version) Application program (old version) SCI New application program 2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM. 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. New application program Boot program Transfer program Programming/ erase control program Flash memory erase New application program SCI Boot program Transfer program Programming/ erase control program SCI Program execution state Figure 17.4 User Program Mode (Example) Rev. 2.00 Mar 21, 2006 page 413 of 518 REJ09B0299-0200 Section 17 ROM 17.3 Block Configuration Figure 17.5 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80. EB0 Erase unit: 1 kbyte H'000000 H'000380 H'000001 H'000381 H'000401 H'000002 H'000382 H'000402 Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– Programming unit: 128 bytes –––––––––––––– H'00007F H'0003FF H'00047F H'0007FF H'00087F EB1 Erase unit: 1 kbyte H'000400 H'000780 EB2 Erase unit: 1 kbyte H'000800 H'000781 H'000801 H'000782 H'000802 H'000B80 EB3 Erase unit: 1 kbyte H'000F80 EB4 Erase unit: 28 kbytes H'007F80 EB5 Erase unit: 16 kbytes H'00BF80 EB6 Erase unit: 8 kbytes H'00DF80 EB7 Erase unit: 8 kbytes H'00FF80 H'00E000 H'00C000 H'008000 H'001000 H'000C00 H'000B81 H'000C01 H'000B82 H'000C02 H'000BFF H'000C7F H'000FFF H'00107F H'007FFF H'00807F H'00BFFF H'00C07F H'00DFFF H'00E07F H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001 H'00DF81 H'00E001 H'00FF81 H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002 H'00DF82 H'00E002 H'00FF82 H'00FFFF Figure 17.5 Flash Memory Block Configuration Rev. 2.00 Mar 21, 2006 page 414 of 518 REJ09B0299-0200 Section 17 ROM 17.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 17.2. Table 17.2 Pin Configuration Pin Name RES MD1 MD0 P92 P91 P90 TxD1 RxD1 I/O Input Input Input Input Input Input Output Input Function Reset Sets this LSI’s operating mode Sets this LSI’s operating mode Sets this LSI’s operating mode Sets this LSI’s operating mode Sets this LSI’s operating mode Serial transmit data output Serial receive data input 17.5 Register Descriptions The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2, the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the serial/timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Erase block register 2 (EBR2) Rev. 2.00 Mar 21, 2006 page 415 of 518 REJ09B0299-0200 Section 17 ROM 17.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 17.8, Flash Memory Programming/Erasing.FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode. Bit 7 Bit Name FWE Initial Value 1 R/W R Description Flash Write Enable Controls programming/erasing of on-chip flash memory. This bit is always read as 0, and cannot be modified. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, the EV, PV, E, and P bits in this register, the ESU and PSU bits in FLMCR2, and all EBR1 and EBR2 bits cannot be set to 1. Do not clear these bits and SWE to 0 simultaneously. 5, 4 — All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 EV 0 R/W Erase-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1 while SWE = 1, the flash memory transits to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. Rev. 2.00 Mar 21, 2006 page 416 of 518 REJ09B0299-0200 Section 17 ROM 17.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash memory error Indicates that an error has occurred during flash memory programming/erasing. When this bit is set to 1, flash memory goes to the error-protection state. For details, see section 17.9.3, Error Protection. 6 to 2 1 — ESU All 0 0 R/(W) R/W Reserved The initial values should not be modified. Erase Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit in FLMCR1 to 1. 0 PSU 0 R/W Program Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1 to 1. Rev. 2.00 Mar 21, 2006 page 417 of 518 REJ09B0299-0200 Section 17 ROM 17.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0. • EBR1 Bit 7 to 0 Bit Name — Initial Value All 0 R/W R/(W) Description Reserved The initial values should not be modified. • EBR2 Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) are to be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) are to be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) are to be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) are to be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) is to be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) is to be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) is to be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) is to be erased. Note: * In normal mode, this bit is always read as 0 and cannot be modified. Rev. 2.00 Mar 21, 2006 page 418 of 518 REJ09B0299-0200 Section 17 ROM 17.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. In normal mode (mode 3), up to 56 kbytes of ROM can be used. Table 17.3 Operating Modes and ROM Operating Modes MCU Operating Mode Mode 2 Mode 3 CPU Operating Mode Advanced Normal Mode Single-chip mode Single-chip mode Mode Pins MD1 1 1 MD0 0 1 On-Chip ROM Enabled (64 kbytes) Enabled (56 kbytes) 17.7 On-Board Programming Modes An on-board programming mode is used to perform on-chip flash memory programming, erasing, and verification. This LSI has two on-board programming modes: boot mode and user program mode. Table 17.4 shows pin settings for boot mode. In user program mode, operation by software is enabled by setting control bits. For details on flash memory mode transitions, see figure 17.2. Table 17.4 On-Board Programming Mode Settings Mode Setting Boot mode User program mode Mode 2 (advanced mode) Mode 3 (normal mode) MD1 0 1 1 MD0 0 0 1 P92 1*   P91 1*   P90 1*   Note: * Can be used as an I/O port after the boot mode activation. Rev. 2.00 Mar 21, 2006 page 419 of 518 REJ09B0299-0200 Section 17 ROM 17.7.1 Boot Mode Table 17.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 17.8, Flash Memory Programming/Erasing. In boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery when user program mode cannot be executed because the program to be initiated in user program mode was mistakenly erased. 2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, this LSI measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins should be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states before this LSI is ready to measure the low-level period. 4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to this LSI. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and this LSI. To operate the SCI properly, set the host’s transfer bit rate and system clock frequency of this LSI within the ranges listed in table 17.6. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses 1 H'FFE080 to H'FFE87F* is the area to which the programming control program is transferred from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to H'FFE087. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. Figure 17.6 shows the on-chip RAM area in boot mode. 6. Before branching to the programming control program (H'FFE088 in the RAM area), this LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD1 pin is in highlevel output state. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. Rev. 2.00 Mar 21, 2006 page 420 of 518 REJ09B0299-0200 Section 17 ROM 7. Boot mode can be cleared by a reset. Cancel the reset* after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. 9. All interrupts are disabled during programming or erasing of the flash memory. Notes: 1. This area is reserved for boot mode. Do not use this area for any other purpose. 2. After reset is cancelled, mode pin input settings must satisfy the mode programming setup time (tMDS = 4 states). 2 Rev. 2.00 Mar 21, 2006 page 421 of 518 REJ09B0299-0200 Section 17 ROM Table 17.5 Boot Mode Operation Item Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot mode start Boot program start Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. H'00 H'55 • Measures low-level period of receive data H'00. • Calculates bit rate and sets it in BRR of SCI_1. • Transmits data H'00 to host as adjustment end indication. Receives data H'AA. Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte). H'AA After receiving data H'55, transmits data H'AA to host. Transfer of programming control program High-order byte and low-order byte Echoback H'XX Echobacks the 2-byte data received to host. Transmits 1-byte of programming control program (repeated for N times). Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times). Flash memory erase Boot program erase error H'FF Receives data H'AA. H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 2.00 Mar 21, 2006 page 422 of 518 REJ09B0299-0200 Section 17 ROM Table 17.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible Host Bit Rate 19200 bps 9600 bps 4800 bps System Clock Frequency Range of LSI 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz H'FFE080 H'FFE088 ID code area *1 Programming control program area*1 (2040 bytes) H'FFE880 Boot program area*2 (1920 bytes) H'FFEFFF H'FFFF00 Boot program area*2 (128 bytes) H'FFFF7F Notes: 1. This area is reserved for boot mode. Do not use this area for any other purpose. 2. The boot program area and area which is not used cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the contents of the boot program area in RAM are remained after a branch is made to the programming control program. Figure 17.6 On-Chip RAM Area in Boot Mode In boot mode, this LSI checks the contents of the 8-byte ID code area as shown below to confirm that the programming control program corresponds with this LSI. To originally write a programming control program to be used in boot mode, the above 8-byte ID code must be added at the beginning of the program. H'FFE080 40 FE 64 66 32 31 31 30 ← H'FFE088 (Product ID) Instruction codes of the programming control program Figure 17.7 ID Code Area Rev. 2.00 Mar 21, 2006 page 423 of 518 REJ09B0299-0200 Section 17 ROM 17.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory. Because the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as like in boot mode. Figure 17.8 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 17.8, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/ erase control program to RAM Branch to flash memory application program Branch to user program/ erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 17.8 Programming/Erasing Flowchart Example in User Program Mode Rev. 2.00 Mar 21, 2006 page 424 of 518 REJ09B0299-0200 Section 17 ROM 17.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 17.8.1, Program/Program-Verify and section 17.8.2, Erase/Erase-Verify, respectively. 17.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 17.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 17.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 17.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. The overflow cycle should be longer than (y + z2 + α + β) µs. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. Rev. 2.00 Mar 21, 2006 page 425 of 518 REJ09B0299-0200 Section 17 ROM 8. The maximum number of repetitions of the program/program-verify sequence to the same bit is (N). Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (x) µs Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR2 Wait (γ) µs Set P bit in FLMCR1 Wait (z1) µs, (z2) µs or (z3) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR2 Wait (β) µs Disable WDT *6 *6 *5 *6 *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *6 *4 n=1 m=0 Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call Apply write pulse z1 µs or z2 µs Set PV bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address See Note 7 for pulse width *6 *6 Wait (ε) µs Read verify data Increment address *6 n←n+1 End Sub *2 NG m=1 NG Note 7: Write Pulse Width Number of Writes n Write Time (z) µs*6 Write data = verify data? 1 2 3 4 5 6 7 8 9 10 11 12 13 z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2 OK 6≥n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? NG 998 999 1000 z2 z2 z2 OK Clear PV bit in FLMCR1 Wait (η) µs 6 ≥ n? NG *6 Note: Use a z3 µs write pulse for additional programming. RAM Program data storage area (128 bytes) OK Successively write 128-byte data from additional1 programming data area in RAM to flash memory * Apply write pulse (Additional programming) *3 µs n ≥ (N)? Reprogram data storage area (128 bytes) m=0? OK Clear SWE bit in FLMCR1 Wait (θ) µs End of programming NG NG Additional-programming data storage area (128 bytes) OK Clear SWE bit in FLMCR1 *6 Wait (θ) µs Programming failure *6 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of z1 µs or z2 µs is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of additional-programming data is executed, a z3 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in section 21.1.4, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Additional-Programming Data Computation Table (X) 1 0 1 1 Still in erased state; no action Comments Programming completed Programming incomplete; reprogram (D) 0 0 1 1 (V) 0 1 0 1 Reprogram Data (X') 0 0 1 1 Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Figure 17.9 Program/Program-Verify Flowchart Rev. 2.00 Mar 21, 2006 page 426 of 518 REJ09B0299-0200 Section 17 ROM 17.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 17.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately (y + z + α + β) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is N. Rev. 2.00 Mar 21, 2006 page 427 of 518 REJ09B0299-0200 Section 17 ROM START *1 Set SWE bit in FLMCR1 Wait (x) µs n=1 Set EBR1 and EBR2 *2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs Set E bit in FLMCR1 *2 Start of erasing Wait (z) ms Clear E bit in FLMCR1 *2 End of erasing Wait (α) µs Clear ESU bit in FLMCR2 *2 Wait (β) µs Disable WDT Set EV bit in FLMCR1 *2 Wait (γ) µs Set block start address as verify address H'FF dummy write to verify address *2 n←n+1 Wait (ε) µs Read verify data Increment address Verify data = all "1"? *2 *3 NG OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait (η) µs Clear EV bit in FLMCR1 Wait (η) µs *2 NG *2 n≥ (N) ? *5 All erase blocks erased? *2 NG OK Clear SWE bit in FLMCR1 OK Clear SWE bit in FLMCR1 Wait (θ) µs Erase failure Wait (θ) µs End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (writing 0 to all data in erased block) is not necessary. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 21.1.4, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. Set only a single bit in EBR1 and EBR2. Do not set more than one bit. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 17.10 Erase/Erase-Verify Flowchart Rev. 2.00 Mar 21, 2006 page 428 of 518 REJ09B0299-0200 Section 17 ROM 17.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 17.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 17.9.3 Error Protection In error protection, an error is detected when the CPU’s runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. • When the flash memory of is read during programming/erasing (including vector read and instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction is executed (transits to software standby mode, sleep mode, subactive mode, sub-sleep mode, or watch mode) during programming/erasing Rev. 2.00 Mar 21, 2006 page 429 of 518 REJ09B0299-0200 Section 17 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode. 17.10 Interrupts during Flash Memory Programming/Erasing In order to give the highest priority to programming/erasing operations, disable all interrupts including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set 1 to 1) or boot program execution* . 1. If an interrupt is generated during programming/erasing, operation in accordance with the program/erase algorithm is not guaranteed. 2. CPU runaway may occur because normal vector reading cannot be performed in interrupt 2 exception handling during programming/erasing* . 3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot be executed. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly for the following two reasons: If flash memory is read while being programmed or erased (while the P or E bit in FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 2.00 Mar 21, 2006 page 430 of 518 REJ09B0299-0200 Section 17 ROM 17.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 64-kbyte flash memory on-chip MCU device*. Figure 17.11 shows a memory map in programmer mode. Note: * Set the programming voltage of the PROM programmer to 3.3V. MCU mode H'000000 Programmer mode H'00000 On-chip ROM area H'00FFFF H'0FFFF Undefined value output H'1FFFF Figure 17.11 Memory Map in Programmer Mode 17.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the Renesas 64-kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. 2. Notes on power on/off At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 3. Perform flash memory programming/erasing in accordance with the recommended algorithm In the recommended algorithm, flash memory programming/erasing can be performed without subjecting this LSI to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1 to 1, set the watchdog timer against program runaway. Rev. 2.00 Mar 21, 2006 page 431 of 518 REJ09B0299-0200 Section 17 ROM 4. Do not set/clear the SWE bit during program execution in the flash memory. Do not set/clear the SWE bit during program execution in the flash memory. An interval of at least 100 µs is necessary between program execution or data reading in flash memory and SWE bit clearing. When the SWE bit is set to 1, flash memory data can be modified, however, flash memory data can be read only in program-verify or erase-verify mode. Do not access the flash memory for a purpose other than verification during programming/erasing. Do not clear the SWE bit during programming, erasing, or verifying. 5. Do not use interrupts during flash memory programming/erasing In order to give the highest priority to programming/erasing operation, disable all interrupts including NMI input when the flash memory is programmed or erased. 6. Do not perform additional programming. Programming must be performed in the erased state. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 7. Ensure that the PROM programmer is correctly attached before programming. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 8. Do not touch the socket adapter or LSI while programming. Touching either of these can cause contact faults and write errors. Rev. 2.00 Mar 21, 2006 page 432 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator Section 18 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 18.1 shows a block diagram of the clock pulse generator. EXTAL Oscillator XTAL Duty correction circuit Clock select circuit φSUB Mediumspeed clock divider φ/2 to φ/32 φ Bus master clock select circuit EXCL Subclock input circuit Waveform forming circuit System clock to φ pin WDT_1 count clock Internal clock to peripheral modules Bus master clock to CPU Figure 18.1 Block Diagram of Clock Pulse Generator The bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on the standby control register, refer to section 19.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, refer to section 19.1.2, Low Power Control Register (LPWRCR). Rev. 2.00 Mar 21, 2006 page 433 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator 18.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 18.1.1 Connecting Crystal Resonator Figure 18.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 18.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 18.3 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 18.2 should be used. A crystal resonator with frequency identical to that of the system clock (φ) should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 18.2 Typical Connection to Crystal Resonator Table 18.1 Damping Resistance Values Frequency (MHz) Rd (Ω) 2 1k 4 500 8 200 10 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator C0 Figure 18.3 Equivalent Circuit of Crystal Resonator Rev. 2.00 Mar 21, 2006 page 434 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator Table 18.2 Crystal Resonator Parameters Frequency (MHz) RS (max) (Ω) C0 (max) (pF) 2 500 7 4 120 7 8 80 7 10 70 7 18.1.2 External Clock Input Method Figure 18.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 18.3. The frequency of the external clock should be the same as that of the system clock (φ). EXTAL XTAL Open External clock input (a) Example of external clock input when XTAL pin left open EXTAL XTAL External clock input (b) Example of external clock input when an inverted clock is input to XTAL pin Figure 18.4 Example of External Clock Input Rev. 2.00 Mar 21, 2006 page 435 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator Table 18.3 External Clock Input Conditions VCC = 2.7 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level Symbol tEXL tEXH tEXr tEXf tCL tCH Min 40 40 — — 0.4 80 Clock pulse width high level 0.4 80 Max — — 10 10 0.6 — 0.6 — Unit ns ns ns ns tcyc ns tcyc ns φ ≥ 5 MHz φ < 5 MHz φ ≥ 5 MHz φ < 5 MHz Figure 21.5 Test Conditions Figure 18.5 tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 18.5 External Clock Input Timing The oscillator and duty correction circuit have a function to adjust the waveform of the external clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to hold it in reset state. Table 18.4 shows the external clock output stabilization delay time. Figure 18.6 shows the timing of the external clock output stabilization delay time. Rev. 2.00 Mar 21, 2006 page 436 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator Table 18.4 External Clock Output Stabilization Delay Time Condition: VCC = 2.7 V to 3.6 V, VSS = 0 V Item Symbol * Min. 500 Max. — Unit µs Remarks Figure 18.6 External clock output stabilization delay tDEXT time Note: * tDEXT includes a RES pulse width (tRESW). VCC 2.7 V STBY VIH EXTAL φ (Internal and external) RES tDEXT* Note:* The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 18.6 Timing of External Clock Output Stabilization Delay Time 18.2 Duty Correction Circuit The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock (φ). 18.3 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16, and φ/32 clocks. Rev. 2.00 Mar 21, 2006 page 437 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator 18.4 Bus Master Clock Select Circuit The bus master clock select circuit selects a clock to supply the bus master with either the system clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in SBYCR. 18.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 18.5. When the subclock is not used, subclock input should not be enabled. Table 18.5 Subclock Input Conditions Vcc = 2.7 to 3.6 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min — — — — Typ 15.26 15.26 — — Max — — 10 10 Unit µs µs ns ns Measurement Condition Figure 18.7 tEXCLH tEXCLL EXCL VCC × 0.5 tEXCLr tEXCLf Figure 18.7 Subclock Input Timing When Subclock Is Not Needed: Do not enable subclock input when the subclock is not needed. Note on Subclock Usage: In transiting to power-down mode, if at least two cycles of the 32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the Rev. 2.00 Mar 21, 2006 page 438 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator SLEEP instruction is executed (power-down mode transition), the subclock input circuit is not initialized and an error may occur in the microcomputer. Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz clock should be input after the 32-kHz clock input is enabled (EXCLE = 1). As described in the hardware manual (clock pulse generator/subclock input circuit), when the subclock is not used, the subclock input should not be enabled (EXCLE = 0). 18.6 Waveform Forming Circuit To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode. 18.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, ports, and interrupt controller and their functions operate depending on the φSUB. The count clock and sampling clock for each timer are divided φSUB clocks. 18.8 18.8.1 Usage Notes Note on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillator pins does not exceed the maximum rating. Rev. 2.00 Mar 21, 2006 page 439 of 518 REJ09B0299-0200 Section 18 Clock Pulse Generator 18.8.2 Notes on Board Design When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit to prevent inductive interference with the correct oscillation as shown in figure 18.8. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 18.8 Note on Board Design of Oscillator Circuit Section Rev. 2.00 Mar 21, 2006 page 440 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Section 19 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. • Medium-speed mode System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16, or φ/32. • Subactive mode The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. • Sleep mode The CPU stops but on-chip peripheral modules continue operating. • Subsleep mode The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. • Watch mode The CPU and on-chip peripheral modules other than WDT_1 stop operating. • Software standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating. • Hardware standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state. • Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. 19.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). • Standby control register (SBYCR) • Low power control register (LPWRCR) • Module stop control register H (MSTPCRH) • Module stop control register L (MSTPCRL) Rev. 2.00 Mar 21, 2006 page 441 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit 7 Bit Name Initial Value R/W SSBY 0 R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Selects the wait time for clock stabilization from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 19.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, there are no specific wait requirements. Normally the minimum value is recommended. 3  0 R Reserved This bit is always read as 0, and cannot be modified. Rev. 2.00 Mar 21, 2006 page 442 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Bit 2 1 0 Bit Name Initial Value R/W SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W Description System Clock Select 2 to 0 Selects a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, SCK2 to SCK0 must be cleared to B'00. 000: High-speed mode 001: Medium-speed clock: φ/2 010: Medium-speed clock: φ/4 011: Medium-speed clock: φ/8 100: Medium-speed clock: φ/16 101: Medium-speed clock: φ/32 11X: — Legend: X: Don't care Table 19.1 Operating Frequency and Wait Time STS2 0 0 0 0 1 1 1 1 STS1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 Wait Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved Reserved 10 MHz 8 MHz 0.8 1.6 3.3 6.6 13.1 26.2   1.0 2.0 4.1 8.2 16.4 32.8   6 MHz 1.3 2.7 5.5 10.9 21.8 43.6   4 MHz 2.0 4.1 8.2 16.4 32.8 65.6   2 MHz 4.1 8.2 16.4 32.8 65.5 131.2     Unit ms Note: Shaded cells indicate the recommended specification. Rev. 2.00 Mar 21, 2006 page 443 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 Bit Name Initial Value R/W DTON 0 R/W Description Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is cancelled: 0: Shifts to high-speed mode 1: Shifts to subactive mode Rev. 2.00 Mar 21, 2006 page 444 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Bit 5 Bit Name Initial Value R/W NESEL 0 R/W Description Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (φSUB) input from the EXCL pin is sampled using the clock (φ) generated by the system clock pulse generator. Clear this bit to 0 when φ is 5 MHz or more. 0: Sampling using φ/32 clock 1: Sampling using φ/4 clock 4 EXCLE 0 R/W Subclock Input Enable Enables/disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin 3  0 R/W Reserved An undefined value is read from this bit. This bit should not be set to 1. 2 to 0  All 0 R Reserved These bits are always read as 0 and cannot be modified. 19.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. • MSTPCRH Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 1 0* 1 0* Corresponding Module   16-bit free-running timer (FRT) 8-bit timers (TMR_0, TMR_1) 14-bit PWM timer (PWMX)   8-bit timers (TMR_X, TMR_Y) R/W R/W R/W R/W R/W 1 1 1 1* 2 1* 2 R/W R/W R/W 1 Notes: 1. Do not set this bit to 1. 2. Do not clear this bit to 0. Rev. 2.00 Mar 21, 2006 page 445 of 518 REJ09B0299-0200 Section 19 Power-Down Modes • MSTPCRL Bit 7 6 5 4 3 2 Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 1 1* Corresponding Module  Serial communication interface_1 (SCI_1)  I C bus interface_0 (IIC_0) I C bus interface_1 (IIC_1) Keyboard buffer controller, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask register A (KMIMRA), port 6 pull-up MOS control register (KMPCR)  Host interface (LPC), wake-up event interrupt mask register B (WUEMRB) 2 2 R/W R/W R/W R/W R/W R/W 1 1 1* 1 1 1 1 0 MSTP1 MSTP0 1* 1 2 R/W R/W Notes: 1. Do not clear this bit to 0. 2. This bit can be read from or written to, however, operation is not affected. 19.2 Mode Transitions and LSI States Figure 19.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 19.2 shows the LSI internal states in each operating mode. Rev. 2.00 Mar 21, 2006 page 446 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0, LSON = 0 SLEEP instruction High-speed mode (main clock) Any interrupt SLEEP instruction External interrupt *3 SLEEP instruction Interrupt *1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception handling SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception handling SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode Sleep mode (main clock) Hardware standby mode SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 Medium-speed mode (main clock) SLEEP instruction Interrupt *1 LSON bit = 1 SLEEP instruction Interrupt *2 SSBY = 0, PSS = 1, LSON = 1 Subsleep mode (subclock) Subactive mode (subclock) : Transition after exception processing Notes: 1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts 2. NMI, IRQ0 to IRQ7, WDT0, WDT1, TMR0, and TMR1 interrupts 3. NMI, IRQ0 to IRQ2, IRQ6, and IRQ7 interrupts : Power-down mode • When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. • Always select high-speed mode before making a transition to watch mode or sub-active mode. Figure 19.1 Mode Transition Diagram Rev. 2.00 Mar 21, 2006 page 447 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Table 19.2 LSI Internal States in Each Operating Mode Function System clock pulse generator Subclock pulse generator CPU Instruction execution Registers External interrupts NMI IRQ0 to IRQ7 KIN0 to KIN15 WUE0 to WUE7 Peripheral WDT_1 modules WDT_0 TMR_0, TMR_1 FRT TMR_X, TMR_Y IIC_0 IIC_1 LPC SCI_1 Function- Halted ing/Halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) Functioning/Halted (retained) Functioning Function- Functioning ing Functioning Subclock operation Halted (retained) Subclock operation Subclock operation Halted (retained) Halted (reset) Functioning HighSpeed Functioning Functioning Functioning MediumSpeed Sleep Function- Functioning ing Function- Functioning ing Medium- Halted speed operation Retained Function- Functioning ing Module Stop Functioning Functioning Functioning Watch Halted SubActive Halted SubSleep Halted Software Hardware Standby Standby Halted Halted Functioning Halted Functioning Subclock operation Functioning Halted Halted Halted Halted Halted Retained Functioning Functioning Functioning Retained Functioning Retained Functioning Undefined Halted Halted (retained) Halted (retained) Rev. 2.00 Mar 21, 2006 page 448 of 518 REJ09B0299-0200 Section 19 Power-Down Modes HighSpeed Functioning Function Peripheral PWMX modules Keyboard buffer controller RAM MediumSpeed Sleep Function- Functioning ing Module Stop Watch SubActive Halted (reset) SubSleep Halted (reset) Software Hardware Standby Standby Halted (reset) Halted (reset) Function- Halted ing/Halted (reset) (reset) Functioning Functioning Retained Functioning Functioning Retained Retained Retained I/O Retained Functioning Retained High impedance Notes: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.” “Halted (reset)” means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 19.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32). On-chip peripheral modules other than the bus masters always operate on the system clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, operation shifts to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, medium-speed mode is cancelled and a transition is made to hardware standby mode. Rev. 2.00 Mar 21, 2006 page 449 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Figure 19.2 shows an example of medium-speed mode timing. Medium-speed mode φ, peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 19.2 Medium-Speed Mode Timing 19.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU’s internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation stabilization time has passed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin level is driven low, sleep mode is cancelled and a transition is made to hardware standby mode. Rev. 2.00 Mar 21, 2006 page 450 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT_1) is cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU’s internal registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the SCI and PWMX, are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), the RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side. When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. Figure 19.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin. Rev. 2.00 Mar 21, 2006 page 451 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 19.3 Application Example in Software Standby Mode 19.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has passed, reset exception handling starts. Rev. 2.00 Mar 21, 2006 page 452 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Figure 19.4 shows an example of hardware standby mode timing. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 19.4 Hardware Standby Mode Timing 19.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped. The contents of the CPU’s internal registers, several on-chip peripheral module registers, and onchip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is exited by an interrupt (WOVI1, NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), RES pin input, or STBY pin input. When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, watch mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the onchip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. Rev. 2.00 Mar 21, 2006 page 453 of 518 REJ09B0299-0200 Section 19 Power-Down Modes When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. 19.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU’s internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to IRQ7), the RES pin input, or the STBY pin input. When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts. In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. Rev. 2.00 Mar 21, 2006 page 454 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to 0. Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details of direct transitions, see section 19.11, Direct Transitions. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode. Rev. 2.00 Mar 21, 2006 page 455 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and PWMX are retained. After the reset state is cancelled, all modules are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. 19.11 Direct Transitions The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode, there is no interruption of program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and then executing the SLEEP instruction. After a transition, direct transition exception handling starts. The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 11, and the PSS bit in TSCR (WDT_1) set to 1. To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR (WDT_1) set to 1. Rev. 2.00 Mar 21, 2006 page 456 of 518 REJ09B0299-0200 Section 19 Power-Down Modes 19.12 Usage Notes 19.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 19.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. Rev. 2.00 Mar 21, 2006 page 457 of 518 REJ09B0299-0200 Section 19 Power-Down Modes Rev. 2.00 Mar 21, 2006 page 458 of 518 REJ09B0299-0200 Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order)  Registers are listed from the lower allocation addresses.  The MSB-side address is indicated for 16-bit addresses.  Registers are classified by functional modules.  The access size is indicated. 2. Register Bits  Bit configurations of the registers are described in the same order as the Register Addresses (address order) above.  Reserved bits are indicated by  in the bit name column.  The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data.  16-bit registers are indicated from the bit on the MSB side. 3. Register States in Each Operating Mode  Register states are described in the same order as the Register Addresses (address order) above.  The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 4. Register Select Conditions  Register states are described in the same order as the Register Addresses (address order) above.  For details on the register select conditions, refer to section 3.2.2, System Control Register (SYSCR), 3.2.3, Serial Timer Control Register (STCR), 19.1.3, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL), and the register descriptions for each module. Rev. 2.00 Mar 21, 2006 page 459 of 518 REJ09B0299-0200 Section 20 List of Registers 20.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Register Name Timer XY control register* Port 7 output data register* Port 7 data direction register* Serial pin select register* Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 Input data register 3 Output data register 3 Status register 3 Abbreviation TCRXY P7ODR P7DDR SPSR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FE00 H'FE01 H'FE03 H'FE0F H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 Module TMR_X, TMR_Y PORT PORT SCI_1 LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC Rev. 2.00 Mar 21, 2006 page 460 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 Register Name LPC channel address register H LPC channel address register L SERIRQ control register 0 SERIRQ control register 1 Input data register 1 Output data register 1 Status register 1 Input data register 2 Output data register 2 Status register 2 Host interface select register Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3 Wakeup event interrupt mask register B I2C bus extended control register_0 I2C bus extended control register_1 Keyboard control register H_0 Keyboard control register L_0 Keyboard data buffer register_0 Keyboard control register H_1 Keyboard control register L_1 Keyboard data buffer register_1 Abbreviation LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FEDC H'FEDD H'FEDE Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC INT IIC_0 IIC_1 Keyboard buffer 8 controller_0 Keyboard buffer 8 controller_0 Keyboard buffer 8 controller_0 Keyboard buffer 8 controller_1 Keyboard buffer 8 controller_1 Keyboard buffer 8 controller_1 Rev. 2.00 Mar 21, 2006 page 461 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Keyboard control register H_2 Keyboard control register L_2 Keyboard data buffer register_2 DDC switch register Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L Address break control register Break address register A Break address register B Break address register C Flash memory control register 1 Flash memory control register 2 Erase block register 1 System control register 2 Erase block register 2 Standby control register Low power control register Module stop control register H Module stop control register L Serial mode register_1 I C bus control register_1 Bit rate register_1 I C bus status register_1 Serial control register_1 2 2 Abbreviation KBCRH_2 KBCRL_2 KBBR_2 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FEE0 H'FEE1 H'FEE2 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 H'FF83 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF88 H'FF89 H'FF89 H'FF8A Module Keyboard buffer 8 controller_2 Keyboard buffer 8 controller_2 Keyboard buffer 8 controller_2 IIC_0 INT INT INT INT INT INT INT INT INT INT FLASH FLASH FLASH SYSTEM FLASH SYSTEM SYSTEM SYSTEM SYSTEM SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 2.00 Mar 21, 2006 page 462 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 I C bus data register_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 Timer interrupt enable register Timer control/status register Free running counter H Free running counter L Output control register AH Output control register BH Output control register AL Output control register BL Timer control register Timer output compare control register Input capture register AH Output control register ARH Input capture register AL Output control register ARL Input capture register BH Output control register AFH Input capture register BL Output control register AFL Input capture register CH Output compare register DMH Input capture register CL Output compare register DML 2 2 Abbreviation TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF8B H'FF8C H'FF8D H'FF8E H'FF8E H'FF8E H'FF8F H'FF8F H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF94 H'FF95 H'FF95 H'FF96 H'FF97 H'FF98 H'FF98 H'FF99 H'FF99 H'FF9A H'FF9A H'FF9B H'FF9B H'FF9C H'FF9C H'FF9D H'FF9D Module SCI_1 SCI_1 SCI_1 SCI_1 IIC_1 IIC_1 IIC_1 IIC_1 FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT Rev. 2.00 Mar 21, 2006 page 463 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Input capture register DH Input capture register DL PWM (D/A) control register PWM (D/A) data register AH PWM (D/A) data register AL PWM (D/A) counter H PWM (D/A) data register BH PWM (D/A) counter L PWM (D/A) data register BL Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register Abbreviation ICRDH ICRDL DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FF9E H'FF9F H'FFA0 H'FFA0 H'FFA1 H'FFA6 H'FFA6 H'FFA7 H'FFA7 H'FFA8 H'FFA8 (write) H'FFA9 (read) H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA Module FRT FRT PWMX PWMX PWMX PWMX PWMX PWMX PWMX WDT_0 WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Port 1 pull-up MOS control register P1PCR Port 2 pull-up MOS control register P2PCR Port 3 pull-up MOS control register P3PCR Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR Rev. 2.00 Mar 21, 2006 page 464 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 6 data register Port B output data register Port B input data register Port 8 data direction register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 I2C bus control register_0 I2C bus status register_0 I C bus data register_0 2 Abbreviation P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFBB H'FFBC H'FFBD (read) H'FFBD (write) H'FFBE (read) H'FFBE (write) H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDE Module PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM SYSTEM SYSTEM BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 IIC_0 IIC_0 IIC_0 Rev. 2.00 Mar 21, 2006 page 465 of 518 REJ09B0299-0200 Section 20 List of Registers Data Bus Width 8 8 8 8 8 8 16 16 8 16 16 8 16 16 8 16 16 16 16 16 16 16 16 8 8 Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Second slave address register_0 I2C bus mode register_0 Slave address register_0 Timer control/status register_1 Timer counter_1 Timer counter_1 Timer control register_X Timer control register_Y Keyboard matrix interrupt register 6 Timer control/status register_X Timer control/status register_Y Pull-up MOS control register Input capture register R Time constant register A_Y Keyboard matrix interrupt register A Input capture register F Time constant register B_Y Timer counter_X Timer counter_Y Timer constant register C Timer input select register Timer constant register A_X Timer constant register B_X Timer connection register I Timer connection register S Abbreviation SARX_0 ICMR_0 SAR_0 TCSR_1 TCNT_1 TCNT_1 TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y KMIMRA TICRF TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X TCONRI TCONRS Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFDE H'FFDF H'FFDF H'FFEA H'FFEA (write) H'FFEB (read) H'FFF0 H'FFF0 H'FFF1 H'FFF1 H'FFF1 H'FFF2 H'FFF2 H'FFF2 H'FFF3 H'FFF3 H'FFF3 H'FFF4 H'FFF4 H'FFF5 H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FFFE Module IIC_0 IIC_0 IIC_0 WDT_1 WDT_1 WDT_1 TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y INT TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_X TMR_X TMR_Y Note: * The program development tool (emulator) does not support this register. Rev. 2.00 Mar 21, 2006 page 466 of 518 REJ09B0299-0200 Section 20 List of Registers 20.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. 16-bit registers are shown as 2 lines. Register Abbreviation TCRXY*3 P7ODR* P7DDR* SPSR* 3 3 Bit 7 OSX Bit 6 OEY Bit 5 CKSX Bit 4 CKSY Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module TMR_X, TMR_Y PORT P77ODR P77DDR SPS1 P76ODR P76DDR — Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 OBF3B DBU36 Bit 14 Bit 6 P75ODR P75DDR — Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 MWMF DBU35 Bit 13 Bit 5 P74ODR P74DDR — Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 SWMF DBU34 Bit 12 Bit 4 P73ODR P73DDR — Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 C/D3 C/D3 Bit 11 Bit 3 P72ODR P72DDR — Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 DBU32 DBU32 Bit 10  P71ODR P71DDR — Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 IBF3A IBF3A Bit 9 Bit 1 P70ODR P70DDR — Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 OBF3A OBF3A Bit 8 TWRE 3 SCI_1 LPC TWR0MW Bit 7 TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3*1 STR3* 2 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 IBF3B DBU37 Bit 15 Bit 7 LADR3H LADR3L Rev. 2.00 Mar 21, 2006 page 467 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB ICXR_0 ICXR_1 Bit 7 Q/C IRQ11E3 Bit 7 Bit 7 DBU17 Bit 7 Bit 7 DBU27 SELSTR3 LPC3E LPCBSY GA20 LFRAME WUEMR7 STOPIM STOPIM Bit 6 SELREQ IRQ10E3 Bit 6 Bit 6 DBU16 Bit 6 Bit 6 DBU26 Bit 5 IEDIR IRQ9E3 Bit 5 Bit 5 DBU15 Bit 5 Bit 5 DBU25 Bit 4 SMIE3B IRQ6E3 Bit 4 Bit 4 DBU14 Bit 4 Bit 4 DBU24 Bit 3 SMIE3A IRQ11E2 Bit 3 Bit 3 C/D1 Bit 3 Bit 3 C/D2 SELIRQ6 SDWNE SDWNB IBFIE3 LPCPD WUEMR3 ALIE ALIE KBIE RXCR3 KB3 KBIE RXCR3 KB3 KBIE RXCR3 KB3 CLR3 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB — A19 Bit 2 SMIE2 IRQ10E2 Bit 2 Bit 2 DBU12 Bit 2 Bit 2 DBU22 SELSMI PMEE PMEB IBFIE2 PME WUEMR2 ALSL ALSL KBF RXCR2 KB2 KBF RXCR2 KB2 KBF RXCR2 KB2 CLR2 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA — A18 Bit 1 IRQ12E1 IRQ9E2 Bit 1 Bit 1 IBF1 Bit 1 Bit 1 IBF2 Bit 0 IRQ1E1 IRQ6E2 Bit 0 Bit 0 OBF1 Bit 0 Bit 0 OBF2 Module LPC SELIRQ11 SELIRQ10 SELIRQ9 LPC2E CLKREQ LRST CLKRUN WUEMR6 HNDS HNDS KCLKI KCLKO KB6 KCLKI KCLKO KB6 KCLKI KCLKO KB6 — ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA — A22 LPC1E IRQBSY SDWN SERIRQ WUEMR5 ICDRF ICDRF KDI KDO KB5 KDI KDO KB5 KDI KDO KB5 — ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB — A21 FGA20E LRSTB ABRT LRESET WUEMR4 ICDRE ICDRE KBFSEL — KB4 KBFSEL — KB4 KBFSEL — KB4 — ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA — A20 SELIRQ12 SELIRQ1 LSMIE LSMIB IBFIE1 LSMI WUEMR1 FNC1 FNC1 PER RXCR1 KB1 PER RXCR1 KB1 PER RXCR1 KB1 CLR1 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB — A17 LSCIE LSCIB ERRIE LSCI WUEMR0 FNC0 FNC0 KBS RXCR0 KB0 KBS RXCR0 KB0 KBS RXCR0 KB0 CLR0 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA BIE A16 INT IIC_0 IIC_1 Keyboard buffer controller _0 Keyboard buffer controller _1 Keyboard buffer controller _2 IIC_0 INT KBCRH_0 KBIOE KBCRL_0 KBBR_0 KBE KB7 KBCRH_1 KBIOE KBCRL_1 KBBR_1 KBE KB7 KBCRH_2 KBIOE KBCRL_2 KBBR_2 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA KBE KB7 — ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB CMF A23 Rev. 2.00 Mar 21, 2006 page 468 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR Bit 7 A15 A7 FWE FLER — KWUL1 EB7 SSBY DTON Bit 6 A14 A6 SWE — — KWUL0 EB6 STS2 LSON MSTP14 MSTP6 CHR IEIC Bit 6 STOP RIE Bit 6 RDRF Bit 6 — ICDR6 SVAX5 WAIT SVA5 ICIBE ICFB Bit 14 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 IEDGB OCRAMS Bit 5 A13 A5 — — — P6PUE EB5 STS1 NESEL MSTP13 MSTP5 PE MST Bit 5 IRTR TE Bit 5 ORER Bit 5 — ICDR5 SVAX4 CKS2 SVA4 ICICE ICFC Bit 13 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 IEDGC ICRS Bit 4 A12 A4 — — — — EB4 STS0 EXCLE MSTP12 MSTP4 O/E TRS Bit 4 AASX RE Bit 4 FER Bit 4 — ICDR4 SVAX3 CKS1 SVA3 ICIDE ICFD Bit 12 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 IEDGD OCRS Bit 3 A11 A3 EV — — SDE EB3 — — MSTP11 MSTP3 STOP ACKE Bit 3 AL MPIE Bit 3 PER Bit 3 SDIR ICDR3 SVAX2 CKS0 SVA2 OCIAE OCFA Bit 11 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 BUFEA OEA Bit 2 A10 A2 PV — — CS4E EB2 SCK2 — MSTP10 MSTP2 MP BBSY Bit 2 AAS TEIE Bit 2 TEND Bit 2 SINV ICDR2 SVAX1 BC2 SVA1 OCIBE OCFB Bit 10 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 BUFEB OEB Bit 1 A9 A1 E ESU — CS3E EB1 SCK1 — MSTP9 MSTP1 CKS1 IRIC Bit 1 ADZ CKE1 Bit 1 MPB Bit 1 — ICDR1 SVAX0 BC1 SVA0 OVIE OVF Bit 9 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 CKS1 OLVLA Bit 0 A8 — P PSU — HI12E EB0 SCK0 — MSTP8 MSTP0 CKS0 SCP Bit 0 ACKB CKE0 Bit 0 MPBT Bit 0 SMIF ICDR0 FSX BC0 FS — CCLRA Bit 8 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 CKS0 OLVLB Module INT FLASH SYSTEM FLASH SYSTEM MSTPCRH MSTP15 MSTPCRL MSTP7 SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR C/A ICE Bit 7 ESTP TIE Bit 7 TDRE Bit 7 — ICDR7 SVAX6 MLS SVA6 ICIAE ICFA Bit 15 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 IEDGA ICRDMS SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 FRT Rev. 2.00 Mar 21, 2006 page 469 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 7 TEST DA13 DA5 UC7 DA13 UC8 DA5 OVF Bit 7 PA7ODR PA7PIN PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 6 PWME DA12 DA4 UC6 DA12 UC9 DA4 WT/IT Bit 6 PA6ODR PA6PIN PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 5 — DA11 DA3 UC5 DA11 UC10 DA3 TME Bit 5 PA5ODR PA5PIN PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 4 — DA10 DA2 UC4 DA10 UC11 DA2 — Bit 4 PA4ODR PA4PIN PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 3 OEB DA9 DA1 UC3 DA9 UC12 DA1 RST/NMI Bit 3 PA3ODR PA3PIN PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 2 OEA DA8 DA0 UC2 DA8 UC13 DA0 CKS2 Bit 2 PA2ODR PA2PIN PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 1 OS DA7 CFS UC1 DA7 — CFS CKS1 Bit 1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 0 CKS DA6 — UC0 DA6 REGS REGS CKS0 Bit 0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR Module FRT PWMX WDT_0 PORT Rev. 2.00 Mar 21, 2006 page 470 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 Bit 7 P47DDR P37DR P47DR — P67DDR — P67DR PB7ODR PB7PIN — P77PIN PB7DDR — P97DDR P97DR IRQ7E IICS — EXPE — — CMIEB CMIEB CMFB CMFB Bit 6 P46DDR P36DR P46DR — P66DDR — P66DR PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E IICX1 — — ICIS0 — CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 IEIC STOP ICDR6 Bit 5 P45DDR P35DR P45DR — P65DDR — P65DR PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E IICX0 INTM1 — BRSTRM ABW OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 MST IRTR ICDR5 Bit 4 P44DDR P34DR P44DR — P64DDR — P64DR PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E IICE INTM0 — BRSTS1 AST CCLR1 CCLR1 ADTE — Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 TRS AASX ICDR4 Bit 3 P43DDR P33DR P43DR — P63DDR — P63DR PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST — BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 ACKE AL ICDR3 Bit 2 P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E — NMIEG — — WMS0 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 BBSY AAS ICDR2 Bit 1 P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 HIE MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 IRIC ADZ ICDR1 Bit 0 P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 SCP ACKB ICDR0 Module PORT INT SYSTEM BSC TMR_0, TMR_1 TCORA_0 Bit 7 TCORA_1 Bit 7 TCORB_0 Bit 7 TCORB_1 Bit 7 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 Bit 7 Bit 7 ICE ESTP ICDR7 IIC_0 Rev. 2.00 Mar 21, 2006 page 471 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation SARX_0 ICMR_0 SAR_0 TCSR_1 TCNT_1 TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR Bit 7 SVAX6 MLS SVA6 OVF Bit 7 CMIEB CMIEB KMIMR7 CMFB CMFB KMIMR7 Bit 7 Bit 6 SVAX5 WAIT SVA5 WT/IT Bit 6 CMIEA CMIEA KMIMR6 CMFA CMFA KMIMR6 Bit 6 Bit 6 KMIMR14 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 — Bit 6 Bit 6 — — Bit 5 SVAX4 CKS2 SVA4 TME Bit 5 OVIE OVIE KMIMR5 OVF OVF KMIMR5 Bit 5 Bit 5 KMIMR13 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 — Bit 5 Bit 5 — — Bit 4 SVAX3 CKS1 SVA3 PSS Bit 4 CCLR1 CCLR1 KMIMR4 ICF ICIE KMIMR4 Bit 4 Bit 4 KMIMR12 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 — Bit 4 Bit 4 ICST — Bit 3 SVAX2 CKS0 SVA2 RST/NMI Bit 3 CCLR0 CCLR0 KMIMR3 OS3 OS3 KMIMR3 Bit 3 Bit 3 KMIMR11 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 — Bit 3 Bit 3 — — Bit 2 SVAX1 BC2 SVA1 CKS2 Bit 2 CKS2 CKS2 KMIMR2 OS2 OS2 KMIMR2 Bit 2 Bit 2 KMIMR10 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 — Bit 2 Bit 2 — — Bit 1 SVAX0 BC1 SVA0 CKS1 Bit 1 CKS1 CKS1 KMIMR1 OS1 OS1 KMIMR1 Bit 1 Bit 1 KMIMR9 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 — Bit 1 Bit 1 — — Bit 0 FSX BC0 FS CKS0 Bit 0 CKS0 CKS0 KMIMR0 OS0 OS0 KMIMR0 Bit 0 Bit 0 KMIMR8 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 IS Bit 0 Bit 0 — — Module IIC_0 WDT_1 TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y INT TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X TCORA_Y Bit 7 KMIMRA TICRF KMIMR15 Bit 7 TCORB_Y Bit 7 TCNT_X TCNT_Y TCORC TISR Bit 7 Bit 7 Bit 7 — TCORA_X Bit 7 TCORB_X Bit 7 TCONRI TCONRS — TMRX/Y TMR_Y Notes: 1. When TWRE = 1 or SELSTR3 = 0 in LADR3L 2. When TWRE = 0 and SELSTR3 = 1 in LADR3L 3. The program development tool (emulator) does not support this register. Rev. 2.00 Mar 21, 2006 page 472 of 518 REJ09B0299-0200 Section 20 List of Registers 20.3 Register Abbreviation TCRXY* Register States in Each Operating Mode High-Speed/ MediumReset Initialized Speed — Watch — Sleep — Sub-Active Sub-Sleep — — Module Stop — Software Standby — Hardware Standby Initialized Module TMR_X, TMR_Y P7ODR* P7DDR* SPSR* TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized — — PORT SCI_1 LPC Rev. 2.00 Mar 21, 2006 page 473 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 KBCRH_2 KBCRL_2 KBBR_2 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC Reset Initialized — — Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Watch — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Sub-Active Sub-Sleep — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — Module Stop — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — Software Standby — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — Hardware Standby Initialized — — Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC_0 INT Keyboard buffer controller_2 Keyboard buffer controller_1 INT IIC_0 IIC_1 Keyboard buffer controller_0 Module LPC Rev. 2.00 Mar 21, 2006 page 474 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Watch Sleep Sub-Active Sub-Sleep Initialized Initialized Initialized — Initialized — — — — Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — Initialized Initialized Initialized — Initialized — — — — Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — Module Stop — — — — — — — — — Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — Software Standby Initialized Initialized Initialized — Initialized — — — — Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized FRT IIC_1 SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 FLASH SYSTEM FLASH SYSTEM Module FLASH Initialized — Initialized — Initialized — — — Initialized — — — — — — — — — Initialized — — — Initialized — — — Initialized — Initialized — Initialized — Initialized — Initialized — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Rev. 2.00 Mar 21, 2006 page 475 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Watch — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Sub-Active Sub-Sleep — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — Module Stop — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — Software Standby — — — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — — Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT PORT WDT_0 PWMX Module FRT Rev. 2.00 Mar 21, 2006 page 476 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Watch — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Sub-Active Sub-Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Module Stop — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Software Standby — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0, TMR_1 TMR_0, TMR_1 BSC INT SYSTEM Module PORT Rev. 2.00 Mar 21, 2006 page 477 of 518 REJ09B0299-0200 Section 20 List of Registers Register Abbreviation ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 TCSR_1 TCNT_1 TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y KMIMRA TICRF TCORB_Y TCNT_X TCNT_Y TCORC TISR TCORA_X TCORB_X TCONRI TCONRS Reset Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High-Speed/ MediumSpeed — — — — — — — — — — — — — — — — — — — — — — — — — — — Watch — — — — — — — — — — — — — — — — — — — — — — — — — — — Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — Sub-Active Sub-Sleep — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Module Stop — — — — — — — — — — — — — — — — — — — — — — — — — — — Software Standby — — — — — — — — — — — — — — — — — — — — — — — — — — — Hardware Standby Initialized Initialized — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_Y TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y INT TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_Y TMR_X WDT_1 Module IIC_0 Note: * The program development tool (emulator) does not support this register. Rev. 2.00 Mar 21, 2006 page 478 of 518 REJ09B0299-0200 Section 20 List of Registers 20.4 H'FE00* 2 H'FE02* 2 Register Select Conditions Register Name TCRXY P7ODR P7DDR SPSR TWR0MW TWR0SW No condition 1 MSTP = 0, (HI12E = 0)* Lower Address Register Select Condition No condition No condition Module Name TMR_X, TMR_Y PORT H'FE03* 2 H'FE0F* 2 SCI_1 LPC H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 Rev. 2.00 Mar 21, 2006 page 479 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FEDC H'FEDD H'FEDE H'FEE0 H'FEE1 H'FEE2 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 Register Name STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCRH_1 KBCRL_1 KBBR_1 KBCRH_2 KBCRL_2 KBBR_2 DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC MSTP4 = 0 No condition IIC_0 INT MSTP2 = 0 No condition No condition INT IIC_0 IIC_1 Keyboard buffer controller Register Select Condition MSTP = 0, (HI12E = 0)* 1 Module Name LPC Rev. 2.00 Mar 21, 2006 page 480 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FF80 H'FF81 H'FF82 H'FF83 Register Name FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 H'FF89 BRR_1 ICSR_1 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 H'FF8F ICMR_1 SAR_1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 TIER TCSR FRCH FRCL OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 TCR TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR MSTP13 = 0 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR ICE = 1 in ICCR1 ICE = 0 in ICCR1 ICE = 1 in ICCR1 ICE = 0 in ICCR1 FRT IIC_1 MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0, IICE = 0 in STCR MSTP3 = 0, IICE = 1 in STCR MSTP6 = 0 SCI_1 IIC_1 SCI_1 IIC_1 SCI_1 FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR SYSTEM FLASH SYSTEM Register Select Condition FLSHE = 1 in STCR Module Name FLASH Rev. 2.00 Mar 21, 2006 page 481 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FF98 Register Name ICRAH OCRARH H'FF99 ICRAL OCRARL H'FF9A ICRBH OCRAFH H'FF9B ICRBL OCRAFL H'FF9C ICRCH OCRDMH H'FF9D ICRCL OCRDML H'FF9E H'FF9F H'FFA0 ICRDH ICRDL DACR DADRAH H'FFA1 DADRAL MSTP11 = 0, IICE = 1 in STCR REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB REGS = 1 in DACNT/ DADRB REGS = 0 in DACNT/ DADRB No condition WDT_0 PWMX PWMX Register Select Condition MSTP13 = 0 ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR Module Name FRT MSTP11 = 0, IICE = 1 in STCR MSTP11 = 0, IICE = 1 in STCR H'FFA6 DACNTH DADRBH H'FFA7 DACNTL DADRBL H'FFA8 TCSR_0 TCNT_0 (write) H'FFA9 TCNT_0 (read) Rev. 2.00 Mar 21, 2006 page 482 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FFAA H'FFAB Register Name PAODR PAPIN (read) PADDR (write) H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN (read) P8DDR (write) H'FFBE P7PIN (read) PBDDR (write) H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR No condition BSC No condition No condition INT SYSTEM Register Select Condition No condition Module Name PORT Rev. 2.00 Mar 21, 2006 page 483 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDE Register Name TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 H'FFDF ICMR_0 SAR_0 H'FFEA TCSR_1 TCNT_1 (write) H'FFEB H'FFF0 TCNT_1 (read) TCR_X TCR_Y H'FFF1 KMIMR TCSR_X TCSR_Y H'FFF2 KMPCR TICRR TCORA_Y MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y INT No condition MSTP4 = 0, IICE = 1 in STCR ICE = 1 in ICCR0 ICE = 0 in ICCR0 ICE = 1 in ICCR0 ICE = 0 in ICCR0 WDT_1 MSTP4 = 0, IICE = 1 in STCR IIC_0 Register Select Condition MSTP12 = 0 Module Name TMR_0, TMR_1 MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y PORT MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y Rev. 2.00 Mar 21, 2006 page 484 of 518 REJ09B0299-0200 Section 20 List of Registers Lower Address H'FFF3 Register Name KMIMRA TICRF TCORB_Y H'FFF4 TCNT_X TCNT_Y H'FFF5 TCORC TISR H'FFF6 H'FFF7 H'FFFC H'FFFE TCORA_X TCORB_X TCONRI TCONRS Register Select Condition MSTP2 = 0, HIE = 1 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR Module Name INT TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y TMRX/Y = 0 in TCONRS TMR_X TMRX/Y = 1 in TCONRS TMR_Y TMRX/Y = 0 in TCONRS TMR_X MSTP8 = 0, HIE = 0 in SYSCR MSTP8 = 0, HIE = 0 in SYSCR TMR_X TMR_Y Notes: 1. Although the settings of the HI12E bit in SYSCR2 do not affect the LPC operation, this bit must not be set to 1 according to the limitation depending on the program development tool (emulator) configuration. 2. The program development tool (emulator) does not support this register. Rev. 2.00 Mar 21, 2006 page 485 of 518 REJ09B0299-0200 Section 20 List of Registers Rev. 2.00 Mar 21, 2006 page 486 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 21.1.1 Electrical Characteristics Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Power supply voltage I/O buffer power supply voltage Input voltage (except ports A, P97, P86, P52, and P42) Input voltage (Port A) Input voltage (P97, P86, P52, P42) Operating temperature Operating temperature (flash memory programming/erasing) Storage temperature Symbol VCC, VCL VCCB Vin Vin Vin Topr Topr Tstg Value –0.3 to +4.3 –0.3 to +7.0 –0.3 to VCC + 0.3 –0.3 to VCCB + 0.3 –0.3 to +7.0 –20 to +75 –20 to +75 –55 to +125 Unit V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Ensure so that the impressed voltage does not exceed 4.3 V for pins for which the maximum rating is determined by the voltage on the VCC and VCL pins, or 7.0 V for pins for which the maximum rating is determined by VCCB. The VCC and VCL pins must be connected to the VCC power supply. Rev. 2.00 Mar 21, 2006 page 487 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.1.2 DC Characteristics Table 21.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 21.3 and 21.4, respectively. Table 21.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Schmitt 1 P67 to P60* , trigger input KIN15 to KIN8, voltage IRQ2 to IRQ0, IRQ5 to IRQ3 4 Symbol (1)* VT VT – Min VCC × 0.2 VCCB × 0.2 — Typ Max — — — — — — — — — — — — — — — — — — — VCC × 0.7 VCCB × 0.7 — — VCC × 0.7 — — VCC × 0.7 — — VCC × 0.8 — — VCC × 0.9 — VCC + 0.3 VCC + 0.3 VCCB + 0.3 Unit V Test Conditions + VT – VT Schmitt P67 to P60 trigger input (KWUL = 00) voltage (in level 6 switching)* P67 to P60 (KWUL = 01) VT VT VT VT VT VT VT VT – + + – + + – + + – + + + – VCC × 0.05 VCCB × 0.05 VCC × 0.2 — V VT – VT – VCC × 0.05 VCC × 0.3 — VT – VT P67 to P60 (KWUL = 10) – VCC × 0.05 VCC × 0.4 — VT – VT P67 to P60 (KWUL = 11) – VCC × 0.03 VCC × 0.45 — VT – VT Input high voltage RES, STBY, (2) NMI, MD1, MD0 EXTAL PA7 to PA0 VIH – 0.05 VCC × 0.9 VCC × 0.7 VCCB × 0.7 V Rev. 2.00 Mar 21, 2006 page 488 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Test Conditions Item Input high voltage P97, P86, P52, P42 (2) Symbol VIH Min VCC × 0.7 VCC × 0.7 Typ — — — — Max 5.5 VCC + 0.3 VCC × 0.1 VCCB × 0.2 0.8 Unit V Input pins except (1) and (2) above Input low voltage RES, STBY, MD1, MD0 PA7 to PA0 (3) VIL –0.3 –0.3 V VCCB = 3.0 V to 4.0 V VCCB = 4.0 V to 5.5 V VCC = 3.0 V to 3.6 V V IOH = –200 µA IOH = –1 mA, (VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 4.5 V) IOH = –200 µA V IOL = 1.6 mA IOL = 5 mA IOL = 1.6 mA NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (except P97, P86, P52, and 234 P42)* * * VOH –0.3 — VCC × 0.2 VCC – 0.5 — VCCB – 0.5 VCC – 1.0 — VCCB – 1.0 — — P97, P86, P52, and 2 P42* Output low voltage All output pins 3 (except RESO)* Ports 1 to 3 RESO VOL 0.5 — — — — — — — — 0.4 1.0 0.4 Notes: 1. P67 to P60 include peripheral module inputs multiplexed on those pins. 2. P52/ExSCK1/SCL0, P97/SDA0, P86/SCK1/SCL1, and P42/SDA1 are NMOS push-pull outputs. When the SCL0, SDA0, SCL1, or SDA1 (ICE = 1) pin is used as an output, it is NMOS open-drain output. Therefore, an external pull-up resistor must be connected in order to output high level. P52/ExSCK1, P97, P86/SCK1, and P42 (ICE = 0) high levels are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from SCK1 and ExSCK1. 3. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function is selected is determined separately. 4. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. Rev. 2.00 Mar 21, 2006 page 489 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Input leakage current RES Symbol Iin Min — — — Typ — — — Max 10.0 1.0 1.0 µA Unit µA Test Conditions Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to VCC – 0.5 V, Vin = 0.5 to VCCB – 0.5 V Vin = 0 V, VCC = 3.0 V to 3.6 V VCCB = 3.0 V to 5.5 V Vin = 0 V, f = 1 MHz, Ta = 25°C STBY, NMI, MD1, MD0 3 Three-state Ports 1 to 9, A* , and B ITSI leakage current (off state) Input pull-up MOS current Ports 1 to 3 Ports 6 (P6PUE = 0) and B 3 Port A* Port 6 (P6PUE = 1) Input RES capacitance NMI P52, P97, P42, P86, PA7 to PA2 Input pins except (4) above Current Normal operation 1 dissipation* Sleep mode 2 Standby mode* ICC (4) Cin –IP 5 30 30 3 — — — — — — — — — — — — — — 8 — 30 20 1 — — 150 300 600 100 80 50 20 15 40 32 5.0 20.0 — µA pF mA f = 10 MHz f = 10 MHz Ta ≤ 50°C 50°C < Ta µA RAM standby voltage VRAM 2.0 V Notes: 1. Current dissipation values are for VIH min = VCC – 0.2 V, VCCB – 0.2 V, and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. 2. The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC – 0.2 V, VCCB – 0.2 V, and VIL max = 0.2 V. 3. The port A characteristics depend on VCCB, and the other pins characteristics depend on VCC. Rev. 2.00 Mar 21, 2006 page 490 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (3) When LPC Function Is Used Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Input high voltage Input low voltage Symbol P37 to P30, VIH P83 to P80, PB1, PB0 P37 to P30, VIL P83 to P80, PB1, PB0 VOH VOL Min VCC × 0.5 — VCC × 0.9 — Max — VCC × 0.3 — VCC × 0.1 Unit V V V V IOH = –0.5 mA IOL = 1.5 mA Test Conditions Output high P37, P33 to P30, voltage P82 to P80, PB1, PB0 Output low voltage P37, P33 to P30, P82 to P80, PB1, PB0 Table 21.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Permissible output low current (per pin) SCL1, SCL0, SDA1, SDA0, PS2AC to PS2CC, PS2AD to PS2CD, PA7 to PA4 (bus drive function selected) Ports 1 to 3 RESO Other output pins Permissible output low current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins –IOH ∑ –IOH ∑ IOL Symbol IOL Min — Typ — Max 10 Unit mA — — — — — — — — — — — — — — 2 1 1 40 60 2 30 mA mA mA Permissible output high current (per pin) Permissible output high current (total) Notes: 1. To protect chip reliability, do not exceed the output current values in table 21.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as show in figures 21.1 and 21.2. Rev. 2.00 Mar 21, 2006 page 491 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics This LSI 2 kΩ Port Darlington pair Figure 21.1 Darlington Pair Drive Circuit (Example) This LSI 600 Ω Ports 1 to 3 LED Figure 21.2 LED Drive Circuit (Example) Rev. 2.00 Mar 21, 2006 page 492 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Schmitt trigger input voltage Symbol VT VT – + + – Min VCC × 0.3 — VCC × 0.05 VCC × 0.7 –0.5 — — Typ — — — — — — — — — Max — VCC × 0.7 — 5.5 VCC × 0.3 0.5 0.4 20 1.0 250 Unit V Test Conditions VCC = 3.0 V to 3.6 V VCC = 3.0 V to 3.6 V VCC = 3.0 V to 3.6 V VT – VT Input high voltage Input low voltage Output low voltage VIH VIL VOL Cin V VCC = 3.0 V to 3.6 V VCC = 3.0 V to 3.6 V IOL = 8 mA IOL = 3 mA Vin = 0 V, f = 1 MHz, Ta = 25°C Vin = 0.5 to VCC – 0.5 V VCC = 3.0 V to 3.6 V V Input capacitance — — pF µA ns Three-state leakage | ITSI | current (off state) SCL, SDA output fall time tOf 20 + 0.1Cb — Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Output low voltage Symbol VOL Min — — — Typ — — — Max 0.8 0.5 0.4 Unit V Test Conditions IOL = 16 mA, VCCB = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA Rev. 2.00 Mar 21, 2006 page 493 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.1.3 AC Characteristics Figure 21.3 shows the test conditions for the AC characteristics. VCC RL Chip output pin C = 30 pF: All output ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V C RH Figure 21.3 Output Load Circuit Clock Timing: Table 21.5 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section 18, Clock Pulse Generator. Table 21.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation settling time at reset (crystal) Oscillation settling time in software standby (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 100 30 30 — — 20 8 500 Max 500 — — 20 20 — — — Unit ns ns ns ns ns ms ms µs Figure 21.6 Figure 21.7 Reference Figure 21.5 Rev. 2.00 Mar 21, 2006 page 494 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Control Signal Timing: Table 21.6 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 21.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item RES setup time RES pulse width NMI setup time (NMI) NMI hold time (NMI) Symbol tRESS tRESW tNMIS tNMIH Min 300 20 250 10 200 250 10 200 Max — — — — — — — — Unit ns tcyc ns ns ns ns ns ns Figure 21.9 Test Conditions Figure 21.8 NMI pulse width (exiting software standby tNMIW mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time(IRQ7 to IRQ0) IRQ pulse width (IRQ7, IRQ6, IRQ2 to IRQ0) (exiting software standby mode) tIRQS tIRQH tIRQW Timing of On-Chip Peripheral Modules: Tables 21.7 to 21.10 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Rev. 2.00 Mar 21, 2006 page 495 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.7 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*, 2 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Single edge Both edges Symbol tPWD tPRS tPRH tFTOD tFTIS tFTCS tFTCWH tFTCWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tPWOD tScyc tSCKW tSCKr tSCKf tTXD tRXS tRXH tRESD tRESOW Min — 50 50 — 50 50 1.5 2.5 — 50 50 1.5 2.5 — 4 6 0.4 — — — 100 100 — 132 Max 100 — — 100 — — — — 100 — — — — 100 — — 0.6 1.5 1.5 100 — — 200 — ns tcyc Figure 21.19 ns Figure 21.18 tScyc tcyc ns tcyc Figure 21.16 Figure 21.17 tcyc ns Figure 21.13 Figure 21.15 Figure 21.14 tcyc Figure 21.12 ns Figure 21.11 Unit ns Test Conditions Figure 21.10 Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges PWMX SCI Pulse output delay time Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) WDT RESO output delay time RESO output pulse width Note: * Only peripheral modules that can be used in subclock operation Rev. 2.00 Mar 21, 2006 page 496 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.8 Keyboard Buffer Controller Timing Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item KCLK, KD output fall time KCLK, KD input data hold time KCLK, KD input data setup time KCLK, KD output delay time KCLK, KD capacitive load 2 Symbol Min tKBF tKBIH tKBIS tKBOD Cb Typ Max 250 — — 450 400 Unit ns ns ns ns pF Test Conditions Notes Figure 21.20 20 + 0.1 Cb — 150 150 — — — — — — Table 21.9 I C Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min 12 3 5 — — — 5 3 3 3 0.5 0 — Typ — — — — — — — — — — — — — Max — — — 7.5* 300 1 — — — — — — 400 Unit tcyc tcyc tcyc tcyc ns tcyc tcyc tcyc tcyc tcyc tcyc ns pF 2 Test Conditions Notes Figure 21.21 Note: * 17.5 tcyc can be set according to the clock selected for use by the I C module. For details, see section 13.6, Usage Notes. Rev. 2.00 Mar 21, 2006 page 497 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Table 21.10 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C Item Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Transmit signal floating delay time Receive signal setup time Receive signal hold time Symbol tLcyc tLCKH tLCKL tTXD tOFF tRXS tRXH Min 30 11 11 2 — 7 0 Typ — — — — — — — Max — — — 11 28 — — Unit ns Test Conditions Figure 21.22 Rev. 2.00 Mar 21, 2006 page 498 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.1.4 Flash Memory Characteristics Table 21.11 shows the flash memory characteristics. Table 21.11 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Item Programming time* * * Erase time* * * 136 124 Symbol tP tE NWEC x y z1 z2 z3 Wait time after 1 P-bit clear* Wait time after 1 PSU-bit clear* Wait time after 1 PV-bit setting* Wait time after 1 dummy write* Wait time after 1 PV-bit clear* Wait time after 1 SWE-bit clear* Maximum programming 145 count* * * α β γ ε η θ N Min — — — 1 50 28 198 8 5 5 4 2 2 100 — Typ 10 100 — — — 30 200 10 — — — — — — — Max 200 1200 100 — — 32 202 12 — — — — — — 1000 Unit ms/ 128 bytes ms/ block times µs µs µs µs µs µs µs µs µs µs µs times Test Condition Reprogramming count Programming Wait time after 1 SWE-bit setting* Wait time after 1 PSU-bit setting* Wait time after 14 P-bit setting* * 1≤n≤6 7 ≤ n ≤ 1000 Additional write Rev. 2.00 Mar 21, 2006 page 499 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Test Conditions Item Erase Wait time after 1 SWE-bit setting* Wait time after 1 ESU-bit setting* Wait time after 16 E-bit setting* * Wait time after 1 E-bit clear* Wait time after 1 ESU-bit clear* Wait time after 1 EV-bit setting* Wait time after 1 dummy write* Wait time after 1 EV-bit clear* Wait time after 1 SWE-bit clear* Maximum erase 167 count* * * Symbol x y z α β γ ε η θ N Min 1 100 10 10 10 20 2 4 100 — Typ — — — — — — — — — — Max — — 100 — — — — — — 120 Unit µs µs ms µs µs µs µs µs µs times Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tP (max)) tP (max) = (wait time after P-bit setting (z1) + (z3)) × 6 + wait time after P-bit setting (z2) × ((N) – 6) 5. The maximum number of writes (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max)). The wait time after P-bit setting (z1, z2, and z3) should be alternated according to the number of writes (n) as follows: 1≤n≤6 z1 = 30µs, z3 = 10µs 7 ≤ n ≤ 1000 z2 = 200µs 6. Maximum erase time (tE (max)) tE (max) = Wait time after E-bit setting (z) × maximum erase count (N) 7. The maximum number of erases (N) should be set according to the actual set value of z to allow erasing within the maximum erase time (tE (max)). Rev. 2.00 Mar 21, 2006 page 500 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.1.5 Usage Note The method of connecting an external capacitor is shown in figure 21.4. Connect the system power supply to the VCL pin together with the VCC pins. Vcc power supply Bypass capacitor 10 µF 0.01 µF VCL VSS < Vcc = 3.0 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins. It is recommended that a bypass capacitor be connected to the power supply pins. (Values are reference values.) Figure 21.4 Connection of VCL Capacitor 21.2 21.2.1 Timing Chart Clock Timing The clock timings are shown below. tcyc tCH φ tCf tCL tCr Figure 21.5 System Clock Timing Rev. 2.00 Mar 21, 2006 page 501 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 φ Figure 21.6 Oscillation Settling Timing φ NMI IRQi tOSC2 Note: i = 0, 1, 2, 6, 7 Figure 21.7 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 2.00 Mar 21, 2006 page 502 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.2.2 Control Signal Timing The control signal timings are shown below. φ tRESS RES tRESW tRESS Figure 21.8 Reset Input Timing φ tNMIS NMI tNMIW tNMIH IRQi (i = 7 to 0) tIRQS IRQi Edge input tIRQS IRQi Level input tIRQW tIRQH Note: i = 7 to 0 Figure 21.9 Interrupt Input Timing Rev. 2.00 Mar 21, 2006 page 503 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 21.2.3 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. T1 φ tPRS tPRH T2 Ports 1 to 9, A, and B (read) tPWD Ports 1 to 9, A, and B (write) Figure 21.10 I/O Port Input/Output Timing φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 21.11 FRT Input/Output Timing Rev. 2.00 Mar 21, 2006 page 504 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics φ tFTCS FTCI tFTCWL tFTCWH Figure 21.12 FRT Clock Input Timing φ tTMOD TMO0, TMO1 TMOX, ExTMOX TMOY Figure 21.13 8-Bit Timer Output Timing φ tTMCS TMCI0, TMCI1 TMIX, TMIY tTMCWL tTMCWH tTMCS Figure 21.14 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 TMIX, TMIY Figure 21.15 8-Bit Timer Reset Input Timing Rev. 2.00 Mar 21, 2006 page 505 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics φ tPWOD PWX1, PWX0 Figure 21.16 PWMX Output Timing tSCKW SCK1, ExSCK1 tScyc tSCKr tSCKf Figure 21.17 SCK Clock Input Timing SCK1, ExSCK1 tTXD TxD1, ExTxD1 (transmit data) tRXS RxD1, ExRxD1 (receive data) tRXH Figure 21.18 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 21.19 A/D Converter External Trigger Input Timing Rev. 2.00 Mar 21, 2006 page 506 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics 1. Reception φ tKBIS KCLK/ KD 2. Transmission (a) tKBIH T1 φ T2 tKBOD KCLK/ KD Transmission (b) KCLK/ KD tKBF Legend: KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Note: φ shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. Figure 21.20 Keyboard Buffer Controller Timing Rev. 2.00 Mar 21, 2006 page 507 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics SDA0, SDA1 tBUF VIH VIL tSTAH tSCLH tSP tSTOS tSTAS SCL0, SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 21.21 I C Bus Interface Input/Output Timing tLCKH tLcyc 2 LCLK tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXS LAD3 to LAD0, SERIRQ, CLKRUN LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXH Figure 21.22 Host Interface (LPC) Timing Rev. 2.00 Mar 21, 2006 page 508 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Testing voltage: 0.4 Vcc 50pF Figure 21.23 Tester Measurement Condition Rev. 2.00 Mar 21, 2006 page 509 of 518 REJ09B0299-0200 Section 21 Electrical Characteristics Rev. 2.00 Mar 21, 2006 page 510 of 518 REJ09B0299-0200 Appendix A I/O Port States in Each Processing State Appendix A I/O Port States in Each Processing State Table A.1 Port Name Pin Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 97 Port 96 φ EXCL Ports 95 to 90 Port A Port B I/O Port States in Each Processing State Hardware Software Standby Standby Reset Mode Mode T T T T T T T T T T T T T T T T T T T T keep keep keep keep keep keep keep keep keep Sub-sleep Watch Mode Sleep Mode Mode keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep keep [DDR = 1] clock output [DDR = 0] T T T T T T T keep keep keep keep keep keep keep keep keep keep keep keep I/O port I/O port I/O port keep keep keep keep keep keep keep keep keep EXCL input Subactive Mode I/O port I/O port I/O port I/O port I/O port I/O port I/O port* I/O port I/O port EXCL input Program Execution State I/O port I/O port I/O port I/O port I/O port I/O port I/O port* I/O port I/O port Clock output/ EXCL input/ input port I/O port I/O port I/O port [DDR = 1] H EXCL input [DDR = 0] T Legend: H: High L: Low T: High-impedance state keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up MOSs remain on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR used. DDR: Data direction register Note: * The program development tool (emulator) does not support the output. Rev. 2.00 Mar 21, 2006 page 511 of 518 REJ09B0299-0200 Appendix B Product Codes Appendix B Product Codes Product Type Product Code Mark Code F2110BVFA10 F2110BVTE10 Package (Package Code) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) H8S/2110B Flash memory version HD64F2110BV (3-V version) Rev. 2.00 Mar 21, 2006 page 512 of 518 REJ09B0299-0200 Appendix C Package Dimensions Appendix C Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section ZE 100 26 Reference Symbol Dimension in Millimeters 1 ZD 25 F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0˚ 8˚ 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Min A A2 Figure C.1 Package Dimensions (FP-100B) Rev. 2.00 Mar 21, 2006 page 513 of 518 REJ09B0299-0200 c Appendix C Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 51 75 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 HE E c Terminal cross section ZE Reference Symbol Dimension in Millimeters 100 26 A2 1 ZD Index mark 25 θ F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0˚ 8˚ 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0 Min Figure C.2 Package Dimensions (TFP-100B) Rev. 2.00 Mar 21, 2006 page 514 of 518 REJ09B0299-0200 A c Index 14-Bit PWM Timer (PWMX)................. 131 16-Bit Count Mode ................................. 197 16-Bit Free-Running Timer (FRT) ......... 147 8-Bit Timer (TMR) ................................. 173 A20 Gate................................................. 393 ABRKCR.................. 67, 462, 468, 474, 480 Absolute Address...................................... 39 Address Map............................................. 55 Address Space........................................... 19 Addressing Modes .................................... 38 Arithmetic Operations Instructions........... 30 Asynchronous Mode............................... 237 BAR .......................... 67, 462, 468, 474, 480 Bcc ............................................................ 35 BCR .......................... 89, 465, 471, 477, 483 Bit Manipulation Instructions ................... 33 bit rate ..................................................... 232 Block Data Transfer Instructions.............. 37 Boot Mode .............................................. 420 Branch Instructions................................... 35 Break....................................................... 263 BRR ........................................................ 232 Buffered Input Capture Input.................. 162 Cascaded Connection.............................. 197 Clear Timing........................................... 161 Clock Pulse Generator ............................ 433 Clocked Synchronous Mode................... 254 CMI......................................................... 201 CMIA...................................................... 201 CMIAY................................................... 201 CMIB ...................................................... 201 CMIBY ................................................... 201 Compare-Match Count Mode ................. 197 Condition field .......................................... 37 Condition-Code Register (CCR) ...............22 Crystal Resonator....................................434 DACNT................... 133, 464, 470, 476, 482 DACR ..................... 136, 464, 470, 476, 482 Data Transfer Instructions.........................29 DDCSWR ............... 292, 462, 468, 474, 480 Direct Transitions....................................456 EBR1....................... 418, 462, 469, 475, 481 EBR2....................... 418, 462, 469, 475, 481 EEPMOV Instruction................................48 Effective Address......................................42 Effective address extension.......................37 Erase/Erase-Verify ..................................427 erasing units ............................................414 ERRI .......................................................403 Error Protection.......................................429 Exception Handling ..................................57 Exception Vector Table ............................58 Extended Control Register (EXR) ............22 flash memory ..........................................409 FLMCR1 ................. 416, 462, 469, 475, 481 FLMCR2 ................. 417, 462, 469, 475, 481 FOV ........................................................166 framing error ...........................................244 FRC......................... 150, 463, 469, 475, 481 General Registers ......................................21 Hardware Protection ...............................429 Hardware Standby Mode ........................452 HICR0 ..................... 361, 461, 468, 474, 480 HICR1 ..................... 361, 461, 468, 474, 480 HICR2 ..................... 368, 461, 468, 474, 480 HICR3 ..................... 368, 461, 468, 474, 480 HISEL ..................... 389, 461, 468, 474, 480 Rev. 2.00 Mar 21, 2006 page 515 of 518 Host Interface LPC Interface (LPC) ....... 357 I C Bus Data Format ............................... 297 2 I C Bus Interface (IIC) ............................ 269 ICCR....................... 280, 465, 471, 478, 484 ICDR....................... 273, 465, 471, 478, 484 ICI........................................................... 166 ICIX ........................................................ 201 ICMR ...................... 277, 466, 472, 478, 484 ICR................... 66, 150, 462, 463, 468, 470, ....................................... 474, 475, 480, 482 ICSR ....................... 288, 465, 471, 478, 484 ICXR....................... 293, 461, 468, 474, 480 IDR ......................... 372, 461, 468, 473, 479 IER............................ 69, 465, 471, 477, 483 IICI ......................................................... 327 Immediate ................................................. 40 Increment Timing ................................... 159 Input Capture Input................................. 161 Input Capture Operation ......................... 199 Instruction Set........................................... 26 Interrupt Control Modes ........................... 77 Interrupt Controller................................... 63 Interrupt Exception Handling ................... 60 Interrupt Exception Handling Vector Table .................................................................. 74 Interrupt Mask Bit..................................... 23 Interval Timer Mode............................... 216 ISCR ......................... 68, 462, 468, 474, 480 ISR ............................ 70, 462, 468, 474, 480 KBBR ..................... 344, 461, 468, 474, 480 KBCR ..................... 341, 461, 468, 474, 480 Keyboard Buffer Controller.................... 339 KMIMR .................... 70, 466, 472, 478, 484 KMIMRA ................. 70, 466, 472, 478, 485 KMPCR .................. 108, 466, 472, 478, 484 LADR3 ................... 371, 461, 467, 473, 479 Logic Operations Instructions................... 32 Rev. 2.00 Mar 21, 2006 page 516 of 518 2 LPWRCR ................ 444, 462, 469, 475, 481 Mark State...............................................263 MCU Operating Mode Selection ..............49 MDCR....................... 50, 465, 471, 477, 483 Medium-Speed Mode..............................449 Memory Indirect .......................................41 Module Stop Mode .................................456 MSTPCR................. 445, 462, 469, 475, 481 Multiprocessor Communication Function ................................................................248 NMI interrupt ............................................73 Noise Canceler ........................................325 OCI..........................................................166 OCR ........................ 150, 463, 470, 476, 481 OCRDM..................................................151 ODR ........................ 373, 461, 468, 473, 479 On-Board Programming Modes..............419 Operation field ..........................................37 Output Compare Output..........................160 overrun error ...........................................244 OVI .........................................................201 OVIY ......................................................201 P1DDR...................... 95, 464, 470, 476, 483 P1DR......................... 95, 464, 470, 476, 483 P1PCR....................... 96, 464, 470, 476, 483 P2DDR...................... 97, 464, 470, 476, 483 P2DR......................... 97, 464, 470, 476, 483 P2PCR....................... 98, 464, 470, 476, 483 P3DDR...................... 99, 464, 470, 477, 483 P3DR......................... 99, 464, 471, 477, 483 P3PCR..................... 100, 464, 470, 476, 483 P4DDR.................... 101, 464, 471, 477, 483 P4DR....................... 102, 464, 471, 477, 483 P5DDR.................... 104, 464, 471, 477, 483 P5DR....................... 105, 464, 471, 477, 483 P6DDR.................... 107, 464, 471, 477, 483 P6DR ...................... 108, 465, 471, 477, 483 P7DDR............................ 113, 460, 467, 479 P7ODR.................... 114, 460, 467, 473, 479 P7PIN...................... 113, 465, 471, 477, 483 P8DDR.................... 115, 465, 471, 477, 483 P8DR ...................... 116, 465, 471, 477, 483 P9DDR.................... 119, 465, 471, 477, 483 P9DR ...................... 120, 465, 471, 477, 483 PADDR................... 122, 464, 470, 476, 483 PAODR................... 123, 464, 470, 476, 483 PAPIN..................... 123, 464, 470, 476, 483 parity error .............................................. 244 PBDDR................... 127, 465, 471, 477, 483 PBODR................... 127, 465, 471, 477, 483 PBPIN..................... 128, 465, 471, 477, 483 Power-Down Modes ............................... 441 Program Counter (PC) .............................. 22 Program/Erase Protection ....................... 429 Program/Program-Verify ........................ 425 Program-Counter Relative ........................ 40 Programmer Mode .................................. 431 Pulse Output ........................................... 159 RDR ........................................................ 224 Register Direct .......................................... 39 Register field............................................. 37 Register Indirect........................................ 39 Register Indirect with Displacement......... 39 Register Indirect with Post-Increment ...... 39 Register Indirect with Pre-Decrement ...... 39 Reset ......................................................... 59 Reset Exception Handling ........................ 59 RSR......................................................... 223 SAR ........................ 274, 466, 472, 478, 484 SARX...................... 275, 466, 472, 478, 484 SBYCR ................... 442, 462, 469, 475, 481 SCMR ..................... 231, 463, 469, 475, 481 SCR......................................................... 227 Serial Communication Interface (SCI) ... 221 Serial Formats .........................................297 Shift Instructions.......................................32 SIRQCR .................. 381, 461, 468, 473, 479 Sleep Mode .............................................450 SMI .........................................................404 SMR ........................ 225, 462, 469, 475, 481 Software Protection.................................429 Software Standby Mode..........................451 SPSR ............................... 237, 460, 467, 479 SSR ......................... 229, 463, 469, 475, 481 stack pointer (SP) ......................................21 Stack Status...............................................61 STCR......................... 53, 465, 471, 477, 483 STR ......................... 374, 461, 468, 474, 480 Subactive Mode ......................................455 Subsleep Mode........................................454 SYSCR...................... 51, 465, 471, 477, 483 SYSCR2.................. 109, 462, 469, 475, 481 System Control Instructions......................36 TCNT ..................... 179, 209, 464, 465, 470, ............................... 471, 476, 477, 482, 484 TCONRI.................. 190, 466, 472, 478, 485 TCONRS................. 190, 466, 472, 478, 485 TCOR.............................. 465, 471, 477, 484 TCORA ...................................................179 TCORB ...................................................179 TCORC ................... 189, 466, 472, 478, 485 TCR........................ 156, 180, 463, 465, 469, ............................... 471, 475, 477, 481, 484 TCRXY ................... 191, 460, 467, 473, 479 TCSR...................... 153, 184, 210, 463, 464, .............................. 465, 469, 470, 471, 475, ............................... 476, 477, 481, 482, 484 TDR ........................................................224 TICRF ..................... 189, 466, 472, 478, 485 TICRR..................... 189, 466, 472, 478, 484 TIER........................ 152, 463, 469, 475, 481 TISR........................ 189, 466, 472, 478, 485 TOCR...................... 157, 463, 469, 475, 481 Rev. 2.00 Mar 21, 2006 page 517 of 518 Trap Instruction Exception Handling........ 60 TSR......................................................... 224 TWR ....................... 373, 460, 467, 473, 479 User Program Mode................................ 424 Watch Mode............................................453 Watchdog Timer (WDT).........................207 Watchdog Timer Mode ...........................214 WOVI......................................................217 WSCR ....................... 90, 465, 471, 477, 483 WUEMRB................. 70, 461, 468, 474, 480 Rev. 2.00 Mar 21, 2006 page 518 of 518 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2110B Group Publication Date: 1st Edition, Septemer 2002 Rev.2.00, March 21, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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