H8S29

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. 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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. H8S/2329 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2329 HD64F2329B HD64F2329E H8S/2328 HD6432328 HD64F2328B H8S/2327 HD6432327 H8S/2326 HD64F2326 H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320 HD6412324S HD6432323 HD6412322R HD6412321 HD6412320 User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Rev.6.00 2007.09 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.6.00 Sep. 27, 2007 Page ii of xxx REJ09B0220-0600 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.6.00 Sep. 27, 2007 Page iii of xxx REJ09B0220-0600 Rev.6.00 Sep. 27, 2007 Page iv of xxx REJ09B0220-0600 Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), DMA controller (DMAC), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM are flash memory (F-ZTAT™*) and mask ROM that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2329 Group, H8S/2328 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2329 Group, H8S/2328 Group to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. • In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Example: Related Manuals: Bit order: The MSB is on the left and the LSB is on the right. The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/) Rev.6.00 Sep. 27, 2007 Page v of xxx REJ09B0220-0600 H8S/2329 Group, H8S/2328 Group Manuals: Document Title H8S/2329 Group, H8S/2328 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual Document No. This manual REJ09B0139 User’s Manuals for Development Tools: Document Title H8S, H8S/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.01 User's Manual H8S, H8S/300 Series Simulator/Debugger (for Windows) User’s Manual Document No. REJ10B0161 ADE-702-037 High-performance Embedded Workshop (for Windows 95/98 and Windows ADE-702-201 NT 4.0) User’s Manual Application Notes: Document Title H8S Series Technical Q & A Application Note Document No. REJ05B0397 Rev.6.00 Sep. 27, 2007 Page vi of xxx REJ09B0220-0600 Main Revisions for This Edition Item Page Revision (See Manual for Details) Figure amended )* 1.3.1 Pin Arrangement 10 Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP120: Top View) Note amended Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the FZTAT versions. Figure 1.4 Mask ROM 11 Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (FP128B: Top View) Figure amended Note amended Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the FZTAT versions. Figure 1.7 HD64F2329B Pin Arrangement (TFP120: Top View) 14 Figure added Rev.6.00 Sep. 27, 2007 Page vii of xxx REJ09B0220-0600 81 80 79 RES WDTOVF (FWE )* P20 / PO0 / TIOCA3 73 72 71 RES WDTOVF (FWE P20 / PO0 / TIOCA3 Item Page Revision (See Manual for Details) Figure added 1.3.1 Pin Arrangement 15 Figure 1.8 HD64F2329B Pin Arrangement (FP128B: Top View) 1.3.3 Pin Functions Table 1.3 Pin Functions 26 Table amended Operating Mode — Mode 2* 1 Mode 3* Mode 4* 2 Mode 5* Mode 6 Mode 7 2 1 MD2 0 MD1 0 1 MD0 1 0 1 0 1 0 1 1 0 1 6.3.5 Chip Select Signals 169 Description amended Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or the CS25 enable bit (CS25E). In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS0 to CS7. Rev.6.00 Sep. 27, 2007 Page viii of xxx REJ09B0220-0600 Item 14.2.8 Bit Rate Register (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Page 618 Revision (See Manual for Details) Table amended φ = 25 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 Error (%) –0.02 0.47 –0.15 0.47 –0.15 0.47 –0.15 0.47 –0.76 1.00 1.73 19.4.1 Features 19.13.1 Features 19.22.1 Features 22.2.6 Flash Memory Characteristics Table 22.22 Flash Memory Characteristics 740 791 849 977 Description amended The flash memory can be reprogrammed minimum 100 times. Description amended The flash memory can be reprogrammed minimum 100 times. Description amended The flash memory can be reprogrammed minimum 100 times. Table amended Item 124 Programming time* * * 136 Erase time* * * Symbol tP tE NWEC tDRP* 1 9 Min — — 10 1 50 Typ 10 50 — — — Max 200 1000 — — — Unit ms/ 128 bytes ms/block Times year s s Test Conditions Rewrite times Data hold time Programming Wait time after SWE bit setting* Wait time after PSU bit setting* 1 7 8 100* 10000* — x y Rev.6.00 Sep. 27, 2007 Page ix of xxx REJ09B0220-0600 Item 22.2.6 Flash Memory Characteristics Table 22.22 Flash Memory Characteristics Page 978 Revision (See Manual for Details) Notes added 7. The minimum number of rewrites after which all characteristics are guaranteed. (The guaranteed range is one to min. rewrites.) 8. Reference value at 25°C. (This is a general indication of the number of rewrites possible under normal conditions.) 9. The data retention characteristics within the specified range, including min. rewrites. Appendix F Package Dimensions Figure F.1 TFP-120 Package Dimensions Figure F.2 FP-128B Package Dimensions 1267 Figure replaced 1268 Figure replaced All trademarks and registered trademarks are the property of their respective owners. Rev.6.00 Sep. 27, 2007 Page x of xxx REJ09B0220-0600 Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 8 Pin Description.................................................................................................................. 10 1.3.1 Pin Arrangement .................................................................................................. 10 1.3.2 Pin Functions in Each Operating Mode ............................................................... 18 1.3.3 Pin Functions ....................................................................................................... 24 Section 2 CPU....................................................................................................33 2.1 Overview........................................................................................................................... 33 2.1.1 Features................................................................................................................ 33 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 34 2.1.3 Differences from H8/300 CPU ............................................................................ 35 2.1.4 Differences from H8/300H CPU.......................................................................... 35 CPU Operating Modes ...................................................................................................... 36 Address Space ................................................................................................................... 39 Register Configuration ...................................................................................................... 40 2.4.1 Overview.............................................................................................................. 40 2.4.2 General Registers ................................................................................................. 41 2.4.3 Control Registers ................................................................................................. 42 2.4.4 Initial Register Values.......................................................................................... 44 Data Formats ..................................................................................................................... 44 2.5.1 General Register Data Formats ............................................................................ 45 2.5.2 Memory Data Formats ......................................................................................... 47 Instruction Set ................................................................................................................... 48 2.6.1 Overview.............................................................................................................. 48 2.6.2 Instructions and Addressing Modes ..................................................................... 49 2.6.3 Table of Instructions Classified by Function ....................................................... 50 2.6.4 Basic Instruction Formats .................................................................................... 60 Addressing Modes and Effective Address Calculation ..................................................... 61 2.7.1 Addressing Mode ................................................................................................. 61 2.7.2 Effective Address Calculation ............................................................................. 64 Processing States............................................................................................................... 68 2.8.1 Overview.............................................................................................................. 68 2.8.2 Reset State............................................................................................................ 69 2.8.3 Exception-Handling State .................................................................................... 70 2.8.4 Program Execution State...................................................................................... 72 Rev.6.00 Sep. 27, 2007 Page xi of xxx REJ09B0220-0600 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.5 Bus-Released State............................................................................................... 72 2.8.6 Power-Down State ............................................................................................... 73 2.9 Basic Timing ..................................................................................................................... 73 2.9.1 Overview.............................................................................................................. 73 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 73 2.9.3 On-Chip Supporting Module Access Timing....................................................... 75 2.9.4 External Address Space Access Timing .............................................................. 76 2.10 Usage Note........................................................................................................................ 76 2.10.1 TAS Instruction.................................................................................................... 76 Section 3 MCU Operating Modes .....................................................................77 3.1 Overview........................................................................................................................... 77 3.1.1 Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT).............. 77 3.1.2 Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT)........................................................................................... 78 3.1.3 Register Configuration......................................................................................... 80 Register Descriptions ........................................................................................................ 80 3.2.1 Mode Control Register (MDCR) ......................................................................... 80 3.2.2 System Control Register (SYSCR) ...................................................................... 81 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) ......................... 82 Operating Mode Descriptions ........................................................................................... 83 3.3.1 Mode 1 ................................................................................................................. 83 3.3.2 Mode 2 (H8S/2329B F-ZTAT Only) ................................................................... 83 3.3.3 Mode 3 (H8S/2329B F-ZTAT Only) ................................................................... 83 3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled) ................................... 83 3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled) ................................... 84 3.3.6 Mode 6 (Expanded Mode with On-Chip ROM Enabled) .................................... 84 3.3.7 Mode 7 (Single-Chip Mode) ................................................................................ 84 3.3.8 Modes 8 and 9 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) ................. 84 3.3.9 Mode 10 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)........................... 84 3.3.10 Mode 11 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)........................... 85 3.3.11 Modes 12 and 13.................................................................................................. 85 3.3.12 Mode 14 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)........................... 85 3.3.13 Mode 15 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only)........................... 85 Pin Functions in Each Operating Mode ............................................................................ 85 Memory Map in Each Operating Mode ............................................................................ 86 3.2 3.3 3.4 3.5 Section 4 Exception Handling ...........................................................................101 4.1 Overview........................................................................................................................... 101 4.1.1 Exception Handling Types and Priority............................................................... 101 Rev.6.00 Sep. 27, 2007 Page xii of xxx REJ09B0220-0600 4.2 4.3 4.4 4.5 4.6 4.7 4.1.2 Exception Handling Operation............................................................................. 102 4.1.3 Exception Vector Table ....................................................................................... 102 Reset.................................................................................................................................. 104 4.2.1 Overview.............................................................................................................. 104 4.2.2 Reset Sequence .................................................................................................... 104 4.2.3 Interrupts after Reset............................................................................................ 105 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 105 Traces................................................................................................................................ 106 Interrupts ........................................................................................................................... 107 Trap Instruction................................................................................................................. 108 Stack Status after Exception Handling.............................................................................. 108 Notes on Use of the Stack ................................................................................................. 109 Section 5 Interrupt Controller ............................................................................111 5.1 Overview........................................................................................................................... 111 5.1.1 Features................................................................................................................ 111 5.1.2 Block Diagram ..................................................................................................... 112 5.1.3 Pin Configuration................................................................................................. 113 5.1.4 Register Configuration......................................................................................... 113 Register Descriptions ........................................................................................................ 114 5.2.1 System Control Register (SYSCR) ...................................................................... 114 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 115 5.2.3 IRQ Enable Register (IER) .................................................................................. 116 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 117 5.2.5 IRQ Status Register (ISR).................................................................................... 118 Interrupt Sources ............................................................................................................... 119 5.3.1 External Interrupts ............................................................................................... 119 5.3.2 Internal Interrupts................................................................................................. 121 5.3.3 Interrupt Exception Vector Table ........................................................................ 121 Interrupt Operation............................................................................................................ 127 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 127 5.4.2 Interrupt Control Mode 0 ..................................................................................... 130 5.4.3 Interrupt Control Mode 2 ..................................................................................... 132 5.4.4 Interrupt Exception Handling Sequence .............................................................. 134 5.4.5 Interrupt Response Times .................................................................................... 136 Usage Notes ...................................................................................................................... 137 5.5.1 Contention between Interrupt Generation and Disabling..................................... 137 5.5.2 Instructions that Disable Interrupts ...................................................................... 138 5.5.3 Times when Interrupts Are Disabled ................................................................... 138 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 138 Rev.6.00 Sep. 27, 2007 Page xiii of xxx REJ09B0220-0600 5.2 5.3 5.4 5.5 5.6 DTC and DMAC Activation by Interrupt ......................................................................... 139 5.6.1 Overview.............................................................................................................. 139 5.6.2 Block Diagram ..................................................................................................... 140 5.6.3 Operation ............................................................................................................. 141 Section 6 Bus Controller....................................................................................143 6.1 Overview........................................................................................................................... 143 6.1.1 Features................................................................................................................ 143 6.1.2 Block Diagram ..................................................................................................... 145 6.1.3 Pin Configuration................................................................................................. 146 6.1.4 Register Configuration......................................................................................... 148 Register Descriptions ........................................................................................................ 149 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 149 6.2.2 Access State Control Register (ASTCR) ............................................................. 150 6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 151 6.2.4 Bus Control Register H (BCRH) ......................................................................... 154 6.2.5 Bus Control Register L (BCRL) .......................................................................... 157 6.2.6 Memory Control Register (MCR)........................................................................ 159 6.2.7 DRAM Control Register (DRAMCR) ................................................................. 162 6.2.8 Refresh Timer Counter (RTCNT)........................................................................ 164 6.2.9 Refresh Time Constant Register (RTCOR) ......................................................... 164 Overview of Bus Control .................................................................................................. 165 6.3.1 Area Partitioning.................................................................................................. 165 6.3.2 Bus Specifications................................................................................................ 166 6.3.3 Memory Interfaces ............................................................................................... 167 6.3.4 Advanced Mode ................................................................................................... 168 6.3.5 Chip Select Signals .............................................................................................. 169 Basic Bus Interface ........................................................................................................... 170 6.4.1 Overview.............................................................................................................. 170 6.4.2 Data Size and Data Alignment............................................................................. 170 6.4.3 Valid Strobes........................................................................................................ 172 6.4.4 Basic Timing........................................................................................................ 173 6.4.5 Wait Control ........................................................................................................ 181 DRAM Interface (Not supported in the H8S/2321) .......................................................... 183 6.5.1 Overview.............................................................................................................. 183 6.5.2 Setting DRAM Space........................................................................................... 183 6.5.3 Address Multiplexing........................................................................................... 184 6.5.4 Data Bus............................................................................................................... 184 6.5.5 Pins Used for DRAM Interface............................................................................ 185 6.5.6 Basic Timing........................................................................................................ 186 6.2 6.3 6.4 6.5 Rev.6.00 Sep. 27, 2007 Page xiv of xxx REJ09B0220-0600 6.5.7 Precharge State Control ....................................................................................... 187 6.5.8 Wait Control ........................................................................................................ 188 6.5.9 Byte Access Control ............................................................................................ 190 6.5.10 Burst Operation.................................................................................................... 192 6.5.11 Refresh Control.................................................................................................... 195 6.6 DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) ... 198 6.6.1 When DDS = 1..................................................................................................... 198 6.6.2 When DDS = 0..................................................................................................... 199 6.7 Burst ROM Interface......................................................................................................... 200 6.7.1 Overview.............................................................................................................. 200 6.7.2 Basic Timing........................................................................................................ 200 6.7.3 Wait Control ........................................................................................................ 202 6.8 Idle Cycle .......................................................................................................................... 203 6.8.1 Operation ............................................................................................................. 203 6.8.2 Pin States in Idle Cycle ........................................................................................ 208 6.9 Write Data Buffer Function .............................................................................................. 209 6.10 Bus Release....................................................................................................................... 210 6.10.1 Overview.............................................................................................................. 210 6.10.2 Operation ............................................................................................................. 210 6.10.3 Pin States in External Bus Released State............................................................ 211 6.10.4 Transition Timing ................................................................................................ 212 6.10.5 Usage Note........................................................................................................... 213 6.11 Bus Arbitration.................................................................................................................. 213 6.11.1 Overview.............................................................................................................. 213 6.11.2 Operation ............................................................................................................. 213 6.11.3 Bus Transfer Timing ............................................................................................ 214 6.11.4 External Bus Release Usage Note........................................................................ 215 6.12 Resets and the Bus Controller ........................................................................................... 215 Section 7 DMA Controller (Not Supported in the H8S/2321) ..........................217 7.1 Overview........................................................................................................................... 217 7.1.1 Features................................................................................................................ 217 7.1.2 Block Diagram ..................................................................................................... 218 7.1.3 Overview of Functions......................................................................................... 219 7.1.4 Pin Configuration................................................................................................. 221 7.1.5 Register Configuration......................................................................................... 222 Register Descriptions (1) (Short Address Mode) .............................................................. 223 7.2.1 Memory Address Registers (MAR) ..................................................................... 224 7.2.2 I/O Address Register (IOAR) .............................................................................. 225 7.2.3 Execute Transfer Count Register (ETCR) ........................................................... 225 Rev.6.00 Sep. 27, 2007 Page xv of xxx REJ09B0220-0600 7.2 7.3 7.4 7.5 7.6 7.7 7.2.4 DMA Control Register (DMACR) ...................................................................... 227 7.2.5 DMA Band Control Register (DMABCR) .......................................................... 231 Register Descriptions (2) (Full Address Mode) ................................................................ 237 7.3.1 Memory Address Register (MAR)....................................................................... 237 7.3.2 I/O Address Register (IOAR) .............................................................................. 237 7.3.3 Execute Transfer Count Register (ETCR) ........................................................... 238 7.3.4 DMA Control Register (DMACR) ...................................................................... 240 7.3.5 DMA Band Control Register (DMABCR) .......................................................... 244 Register Descriptions (3) .................................................................................................. 250 7.4.1 DMA Write Enable Register (DMAWER) .......................................................... 250 7.4.2 DMA Terminal Control Register (DMATCR)..................................................... 253 7.4.3 Module Stop Control Register (MSTPCR) .......................................................... 254 Operation........................................................................................................................... 255 7.5.1 Transfer Modes .................................................................................................... 255 7.5.2 Sequential Mode .................................................................................................. 257 7.5.3 Idle Mode............................................................................................................. 260 7.5.4 Repeat Mode ........................................................................................................ 263 7.5.5 Single Address Mode........................................................................................... 267 7.5.6 Normal Mode ....................................................................................................... 270 7.5.7 Block Transfer Mode ........................................................................................... 273 7.5.8 DMAC Activation Sources .................................................................................. 279 7.5.9 Basic DMAC Bus Cycles..................................................................................... 282 7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 283 7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 291 7.5.12 Write Data Buffer Function ................................................................................. 297 7.5.13 DMAC Multi-Channel Operation ........................................................................ 298 7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles, and the DTC......................................................................................................... 300 7.5.15 NMI Interrupts and DMAC.................................................................................. 301 7.5.16 Forced Termination of DMAC Operation............................................................ 302 7.5.17 Clearing Full Address Mode ................................................................................ 303 Interrupts ........................................................................................................................... 304 Usage Notes ...................................................................................................................... 305 Section 8 Data Transfer Controller....................................................................311 8.1 Overview........................................................................................................................... 311 8.1.1 Features................................................................................................................ 311 8.1.2 Block Diagram ..................................................................................................... 312 8.1.3 Register Configuration......................................................................................... 313 Register Descriptions ........................................................................................................ 314 8.2 Rev.6.00 Sep. 27, 2007 Page xvi of xxx REJ09B0220-0600 8.3 8.4 8.5 8.2.1 DTC Mode Register A (MRA) ............................................................................ 314 8.2.2 DTC Mode Register B (MRB)............................................................................. 315 8.2.3 DTC Source Address Register (SAR).................................................................. 317 8.2.4 DTC Destination Address Register (DAR).......................................................... 317 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 318 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 318 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 319 8.2.8 DTC Vector Register (DTVECR)........................................................................ 320 8.2.9 Module Stop Control Register (MSTPCR) .......................................................... 321 Operation........................................................................................................................... 321 8.3.1 Overview.............................................................................................................. 321 8.3.2 Activation Sources ............................................................................................... 325 8.3.3 DTC Vector Table................................................................................................ 326 8.3.4 Location of Register Information in Address Space ............................................ 330 8.3.5 Normal Mode ....................................................................................................... 331 8.3.6 Repeat Mode ........................................................................................................ 332 8.3.7 Block Transfer Mode ........................................................................................... 333 8.3.8 Chain Transfer ..................................................................................................... 335 8.3.9 Operation Timing................................................................................................. 336 8.3.10 Number of DTC Execution States ....................................................................... 337 8.3.11 Procedures for Using DTC................................................................................... 339 8.3.12 Examples of Use of the DTC ............................................................................... 340 Interrupts ........................................................................................................................... 344 Usage Notes ...................................................................................................................... 345 Section 9 I/O Ports .............................................................................................347 9.1 9.2 Overview........................................................................................................................... 347 Port 1................................................................................................................................. 352 9.2.1 Overview.............................................................................................................. 352 9.2.2 Register Configuration......................................................................................... 353 9.2.3 Pin Functions ....................................................................................................... 355 Port 2................................................................................................................................. 363 9.3.1 Overview.............................................................................................................. 363 9.3.2 Register Configuration......................................................................................... 364 9.3.3 Pin Functions ....................................................................................................... 366 Port 3................................................................................................................................. 374 9.4.1 Overview.............................................................................................................. 374 9.4.2 Register Configuration......................................................................................... 374 9.4.3 Pin Functions ....................................................................................................... 377 Port 4................................................................................................................................. 379 Rev.6.00 Sep. 27, 2007 Page xvii of xxx REJ09B0220-0600 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.5.1 Overview.............................................................................................................. 379 9.5.2 Register Configuration......................................................................................... 380 9.5.3 Pin Functions ....................................................................................................... 380 Port 5................................................................................................................................. 381 9.6.1 Overview.............................................................................................................. 381 9.6.2 Register Configuration......................................................................................... 382 9.6.3 Pin Functions ....................................................................................................... 386 Port 6................................................................................................................................. 388 9.7.1 Overview.............................................................................................................. 388 9.7.2 Register Configuration......................................................................................... 389 9.7.3 Pin Functions ....................................................................................................... 392 Port A................................................................................................................................ 394 9.8.1 Overview.............................................................................................................. 394 9.8.2 Register Configuration......................................................................................... 395 9.8.3 Pin Functions ....................................................................................................... 400 9.8.4 MOS Input Pull-Up Function............................................................................... 403 Port B ................................................................................................................................ 404 9.9.1 Overview.............................................................................................................. 404 9.9.2 Register Configuration......................................................................................... 405 9.9.3 Pin Functions ....................................................................................................... 407 9.9.4 MOS Input Pull-Up Function............................................................................... 409 Port C ................................................................................................................................ 410 9.10.1 Overview.............................................................................................................. 410 9.10.2 Register Configuration......................................................................................... 411 9.10.3 Pin Functions ....................................................................................................... 413 9.10.4 MOS Input Pull-Up Function............................................................................... 415 Port D................................................................................................................................ 416 9.11.1 Overview.............................................................................................................. 416 9.11.2 Register Configuration......................................................................................... 417 9.11.3 Pin Functions ....................................................................................................... 420 9.11.4 MOS Input Pull-Up Function............................................................................... 421 Port E ................................................................................................................................ 422 9.12.1 Overview.............................................................................................................. 422 9.12.2 Register Configuration......................................................................................... 423 9.12.3 Pin Functions ....................................................................................................... 425 9.12.4 MOS Input Pull-Up Function............................................................................... 427 Port F................................................................................................................................. 428 9.13.1 Overview.............................................................................................................. 428 9.13.2 Register Configuration......................................................................................... 429 9.13.3 Pin Functions ....................................................................................................... 433 Rev.6.00 Sep. 27, 2007 Page xviii of xxx REJ09B0220-0600 9.14 Port G................................................................................................................................ 435 9.14.1 Overview.............................................................................................................. 435 9.14.2 Register Configuration......................................................................................... 436 9.14.3 Pin Functions ....................................................................................................... 439 Section 10 16-Bit Timer Pulse Unit (TPU)........................................................441 10.1 Overview........................................................................................................................... 441 10.1.1 Features................................................................................................................ 441 10.1.2 Block Diagram ..................................................................................................... 445 10.1.3 Pin Configuration................................................................................................. 446 10.1.4 Register Configuration......................................................................................... 448 10.2 Register Descriptions ........................................................................................................ 450 10.2.1 Timer Control Registers (TCR) ........................................................................... 450 10.2.2 Timer Mode Registers (TMDR) .......................................................................... 455 10.2.3 Timer I/O Control Registers (TIOR).................................................................... 457 10.2.4 Timer Interrupt Enable Registers (TIER) ............................................................ 470 10.2.5 Timer Status Registers (TSR) .............................................................................. 472 10.2.6 Timer Counters (TCNT) ...................................................................................... 476 10.2.7 Timer General Registers (TGR)........................................................................... 477 10.2.8 Timer Start Register (TSTR)................................................................................ 478 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 479 10.2.10 Module Stop Control Register (MSTPCR) .......................................................... 480 10.3 Interface to Bus Master ..................................................................................................... 481 10.3.1 16-Bit Registers ................................................................................................... 481 10.3.2 8-Bit Registers ..................................................................................................... 481 10.4 Operation........................................................................................................................... 483 10.4.1 Overview.............................................................................................................. 483 10.4.2 Basic Functions.................................................................................................... 484 10.4.3 Synchronous Operation........................................................................................ 490 10.4.4 Buffer Operation .................................................................................................. 492 10.4.5 Cascaded Operation ............................................................................................. 496 10.4.6 PWM Modes ........................................................................................................ 498 10.4.7 Phase Counting Mode .......................................................................................... 504 10.5 Interrupts ........................................................................................................................... 510 10.5.1 Interrupt Sources and Priorities............................................................................ 510 10.5.2 DTC/DMAC Activation....................................................................................... 512 10.5.3 A/D Converter Activation.................................................................................... 512 10.6 Operation Timing.............................................................................................................. 513 10.6.1 Input/Output Timing ............................................................................................ 513 10.6.2 Interrupt Signal Timing........................................................................................ 517 Rev.6.00 Sep. 27, 2007 Page xix of xxx REJ09B0220-0600 10.7 Usage Notes ...................................................................................................................... 521 Section 11 Programmable Pulse Generator (PPG) ............................................531 11.1 Overview........................................................................................................................... 531 11.1.1 Features................................................................................................................ 531 11.1.2 Block Diagram ..................................................................................................... 532 11.1.3 Pin Configuration................................................................................................. 533 11.1.4 Registers............................................................................................................... 534 11.2 Register Descriptions ........................................................................................................ 535 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 535 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 536 11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 537 11.2.4 Notes on NDR Access ......................................................................................... 537 11.2.5 PPG Output Control Register (PCR).................................................................... 539 11.2.6 PPG Output Mode Register (PMR)...................................................................... 541 11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 543 11.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 544 11.2.9 Module Stop Control Register (MSTPCR) .......................................................... 544 11.3 Operation........................................................................................................................... 545 11.3.1 Overview.............................................................................................................. 545 11.3.2 Output Timing...................................................................................................... 546 11.3.3 Normal Pulse Output............................................................................................ 547 11.3.4 Non-Overlapping Pulse Output............................................................................ 549 11.3.5 Inverted Pulse Output .......................................................................................... 552 11.3.6 Pulse Output Triggered by Input Capture ............................................................ 553 11.4 Usage Notes ...................................................................................................................... 554 11.4.1 Operation of Pulse Output Pins............................................................................ 554 11.4.2 Note on Non-Overlapping Output........................................................................ 554 Section 12 8-Bit Timers.....................................................................................557 12.1 Overview........................................................................................................................... 557 12.1.1 Features................................................................................................................ 557 12.1.2 Block Diagram ..................................................................................................... 558 12.1.3 Pin Configuration................................................................................................. 559 12.1.4 Register Configuration......................................................................................... 559 12.2 Register Descriptions ........................................................................................................ 560 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 560 12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 560 12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 561 12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 561 Rev.6.00 Sep. 27, 2007 Page xx of xxx REJ09B0220-0600 12.3 12.4 12.5 12.6 12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 563 12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 566 Operation........................................................................................................................... 567 12.3.1 TCNT Incrementation Timing ............................................................................. 567 12.3.2 Compare Match Timing ....................................................................................... 568 12.3.3 Timing of TCNT External Reset.......................................................................... 570 12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 570 12.3.5 Operation with Cascaded Connection .................................................................. 571 Interrupts ........................................................................................................................... 572 12.4.1 Interrupt Sources and DTC Activation ................................................................ 572 12.4.2 A/D Converter Activation.................................................................................... 572 Sample Application........................................................................................................... 573 Usage Notes ...................................................................................................................... 574 12.6.1 Contention between TCNT Write and Clear........................................................ 574 12.6.2 Contention between TCNT Write and Increment ................................................ 575 12.6.3 Contention between TCOR Write and Compare Match ...................................... 576 12.6.4 Contention between Compare Matches A and B ................................................. 577 12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 577 12.6.6 Interrupts and Module Stop Mode ....................................................................... 579 Section 13 Watchdog Timer ..............................................................................581 13.1 Overview........................................................................................................................... 581 13.1.1 Features................................................................................................................ 581 13.1.2 Block Diagram ..................................................................................................... 582 13.1.3 Pin Configuration................................................................................................. 583 13.1.4 Register Configuration......................................................................................... 583 13.2 Register Descriptions ........................................................................................................ 584 13.2.1 Timer Counter (TCNT)........................................................................................ 584 13.2.2 Timer Control/Status Register (TCSR) ................................................................ 585 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 587 13.2.4 Notes on Register Access..................................................................................... 588 13.3 Operation........................................................................................................................... 589 13.3.1 Operation in Watchdog Timer Mode ................................................................... 589 13.3.2 Operation in Interval Timer Mode ....................................................................... 591 13.3.3 Timing of Overflow Flag (OVF) Setting ............................................................. 592 13.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 593 13.4 Interrupts ........................................................................................................................... 594 13.5 Usage Notes ...................................................................................................................... 594 13.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 594 13.5.2 Changing Value of CKS2 to CKS0...................................................................... 595 Rev.6.00 Sep. 27, 2007 Page xxi of xxx REJ09B0220-0600 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 595 13.5.4 System Reset by WDTOVF Signal...................................................................... 595 13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 596 Section 14 Serial Communication Interface (SCI) ............................................597 14.1 Overview........................................................................................................................... 597 14.1.1 Features................................................................................................................ 597 14.1.2 Block Diagram ..................................................................................................... 599 14.1.3 Pin Configuration................................................................................................. 600 14.1.4 Register Configuration......................................................................................... 601 14.2 Register Descriptions ........................................................................................................ 602 14.2.1 Receive Shift Register (RSR) .............................................................................. 602 14.2.2 Receive Data Register (RDR) .............................................................................. 602 14.2.3 Transmit Shift Register (TSR) ............................................................................. 603 14.2.4 Transmit Data Register (TDR)............................................................................. 603 14.2.5 Serial Mode Register (SMR)................................................................................ 604 14.2.6 Serial Control Register (SCR).............................................................................. 607 14.2.7 Serial Status Register (SSR) ................................................................................ 611 14.2.8 Bit Rate Register (BRR) ...................................................................................... 615 14.2.9 Smart Card Mode Register (SCMR) .................................................................... 623 14.2.10 Module Stop Control Register (MSTPCR) .......................................................... 625 14.3 Operation........................................................................................................................... 626 14.3.1 Overview.............................................................................................................. 626 14.3.2 Operation in Asynchronous Mode ....................................................................... 628 14.3.3 Multiprocessor Communication Function............................................................ 639 14.3.4 Operation in Synchronous Mode ......................................................................... 647 14.4 SCI Interrupts.................................................................................................................... 656 14.5 Usage Notes ...................................................................................................................... 658 Section 15 Smart Card Interface........................................................................667 15.1 Overview........................................................................................................................... 667 15.1.1 Features................................................................................................................ 667 15.1.2 Block Diagram ..................................................................................................... 668 15.1.3 Pin Configuration................................................................................................. 669 15.1.4 Register Configuration......................................................................................... 670 15.2 Register Descriptions ........................................................................................................ 671 15.2.1 Smart Card Mode Register (SCMR) .................................................................... 671 15.2.2 Serial Status Register (SSR) ................................................................................ 673 15.2.3 Serial Mode Register (SMR)................................................................................ 675 15.2.4 Serial Control Register (SCR).............................................................................. 677 Rev.6.00 Sep. 27, 2007 Page xxii of xxx REJ09B0220-0600 15.3 Operation........................................................................................................................... 678 15.3.1 Overview.............................................................................................................. 678 15.3.2 Pin Connections ................................................................................................... 678 15.3.3 Data Format ......................................................................................................... 680 15.3.4 Register Settings .................................................................................................. 682 15.3.5 Clock.................................................................................................................... 684 15.3.6 Data Transfer Operations ..................................................................................... 686 15.3.7 Operation in GSM Mode ..................................................................................... 694 15.3.8 Operation in Block Transfer Mode ...................................................................... 695 15.4 Usage Notes ...................................................................................................................... 696 Section 16 A/D Converter (8 Analog Input Channel Version)..........................701 16.1 Overview........................................................................................................................... 701 16.1.1 Features................................................................................................................ 701 16.1.2 Block Diagram ..................................................................................................... 702 16.1.3 Pin Configuration................................................................................................. 703 16.1.4 Register Configuration......................................................................................... 704 16.2 Register Descriptions ........................................................................................................ 705 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 705 16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 706 16.2.3 A/D Control Register (ADCR) ............................................................................ 708 16.2.4 Module Stop Control Register (MSTPCR) .......................................................... 709 16.3 Interface to Bus Master ..................................................................................................... 710 16.4 Operation........................................................................................................................... 711 16.4.1 Single Mode (SCAN = 0) .................................................................................... 711 16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 713 16.4.3 Input Sampling and A/D Conversion Time.......................................................... 715 16.4.4 External Trigger Input Timing ............................................................................. 716 16.5 Interrupts ........................................................................................................................... 717 16.6 Usage Notes ...................................................................................................................... 718 Section 17 D/A Converter..................................................................................723 17.1 Overview........................................................................................................................... 723 17.1.1 Features................................................................................................................ 723 17.1.2 Block Diagram ..................................................................................................... 724 17.1.3 Pin Configuration................................................................................................. 725 17.1.4 Register Configuration......................................................................................... 725 17.2 Register Descriptions ........................................................................................................ 726 17.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ....................................................... 726 17.2.2 D/A Control Registers 01 (DACR01) .................................................................. 726 Rev.6.00 Sep. 27, 2007 Page xxiii of xxx REJ09B0220-0600 17.2.3 Module Stop Control Register (MSTPCR) .......................................................... 728 17.3 Operation........................................................................................................................... 728 Section 18 RAM ................................................................................................731 18.1 Overview........................................................................................................................... 731 18.1.1 Block Diagram ..................................................................................................... 731 18.1.2 Register Configuration......................................................................................... 732 18.2 Register Descriptions ........................................................................................................ 732 18.2.1 System Control Register (SYSCR) ...................................................................... 732 18.3 Operation........................................................................................................................... 733 18.4 Usage Note........................................................................................................................ 733 Section 19 ROM ................................................................................................735 19.1 Overview........................................................................................................................... 735 19.1.1 Block Diagram ..................................................................................................... 735 19.1.2 Register Configuration......................................................................................... 736 19.2 Register Descriptions ........................................................................................................ 736 19.2.1 Mode Control Register (MDCR) ......................................................................... 736 19.2.2 Bus Control Register L (BCRL) .......................................................................... 737 19.3 Operation........................................................................................................................... 737 19.4 Overview of Flash Memory (H8S/2329B F-ZTAT) ......................................................... 740 19.4.1 Features................................................................................................................ 740 19.4.2 Overview.............................................................................................................. 741 19.4.3 Flash Memory Operating Modes ......................................................................... 742 19.4.4 On-Board Programming Modes........................................................................... 743 19.4.5 Flash Memory Emulation in RAM ...................................................................... 745 19.4.6 Differences between Boot Mode and User Program Mode ................................. 746 19.4.7 Block Configuration............................................................................................. 747 19.4.8 Pin Configuration................................................................................................. 748 19.4.9 Register Configuration......................................................................................... 749 19.5 Register Descriptions ........................................................................................................ 750 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 750 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 753 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 754 19.5.4 Erase Block Registers 2 (EBR2) .......................................................................... 754 19.5.5 System Control Register 2 (SYSCR2) ................................................................. 755 19.5.6 RAM Emulation Register (RAMER)................................................................... 756 19.6 On-Board Programming Modes........................................................................................ 758 19.6.1 Boot Mode ........................................................................................................... 759 19.6.2 User Program Mode............................................................................................. 763 Rev.6.00 Sep. 27, 2007 Page xxiv of xxx REJ09B0220-0600 19.7 Programming/Erasing Flash Memory ............................................................................... 765 19.7.1 Program Mode ..................................................................................................... 765 19.7.2 Program-Verify Mode.......................................................................................... 766 19.7.3 Erase Mode .......................................................................................................... 768 19.7.4 Erase-Verify Mode............................................................................................... 768 19.8 Flash Memory Protection.................................................................................................. 770 19.8.1 Hardware Protection ............................................................................................ 770 19.8.2 Software Protection.............................................................................................. 770 19.8.3 Error Protection.................................................................................................... 771 19.9 Flash Memory Emulation in RAM ................................................................................... 773 19.9.1 Emulation in RAM............................................................................................... 773 19.9.2 RAM Overlap ...................................................................................................... 774 19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 775 19.11 Flash Memory PROM Mode............................................................................................. 776 19.11.1 PROM Mode Setting............................................................................................ 776 19.11.2 Socket Adapters and Memory Map...................................................................... 776 19.11.3 PROM Mode Operation....................................................................................... 778 19.11.4 Memory Read Mode ............................................................................................ 779 19.11.5 Auto-Program Mode ............................................................................................ 783 19.11.6 Auto-Erase Mode ................................................................................................. 785 19.11.7 Status Read Mode ................................................................................................ 786 19.11.8 Status Polling ....................................................................................................... 788 19.11.9 PROM Mode Transition Time ............................................................................. 788 19.11.10 Notes on Memory Programming........................................................................ 789 19.12 Flash Memory Programming and Erasing Precautions ..................................................... 789 19.13 Overview of Flash Memory (H8S/2328B F-ZTAT) ......................................................... 791 19.13.1 Features................................................................................................................ 791 19.13.2 Overview.............................................................................................................. 792 19.13.3 Flash Memory Operating Modes ......................................................................... 793 19.13.4 On-Board Programming Modes........................................................................... 794 19.13.5 Flash Memory Emulation in RAM ...................................................................... 796 19.13.6 Differences between Boot Mode and User Program Mode ................................. 797 19.13.7 Block Configuration............................................................................................. 798 19.13.8 Pin Configuration................................................................................................. 799 19.13.9 Register Configuration......................................................................................... 800 19.14 Register Descriptions ........................................................................................................ 801 19.14.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 801 19.14.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 804 19.14.3 Erase Block Register 1 (EBR1) ........................................................................... 805 19.14.4 Erase Block Registers 2 (EBR2) .......................................................................... 805 Rev.6.00 Sep. 27, 2007 Page xxv of xxx REJ09B0220-0600 19.15 19.16 19.17 19.18 19.19 19.20 19.21 19.22 19.14.5 System Control Register 2 (SYSCR2) ................................................................. 806 19.14.6 RAM Emulation Register (RAMER)................................................................... 807 On-Board Programming Modes........................................................................................ 809 19.15.1 Boot Mode ........................................................................................................... 809 19.15.2 User Program Mode............................................................................................. 815 Programming/Erasing Flash Memory ............................................................................... 817 19.16.1 Program Mode ..................................................................................................... 817 19.16.2 Program-Verify Mode.......................................................................................... 818 19.16.3 Erase Mode .......................................................................................................... 820 19.16.4 Erase-Verify Mode............................................................................................... 820 Flash Memory Protection.................................................................................................. 822 19.17.1 Hardware Protection ............................................................................................ 822 19.17.2 Software Protection.............................................................................................. 822 19.17.3 Error Protection.................................................................................................... 823 Flash Memory Emulation in RAM ................................................................................... 825 19.18.1 Emulation in RAM............................................................................................... 825 19.18.2 RAM Overlap ...................................................................................................... 826 Interrupt Handling when Programming/Erasing Flash Memory....................................... 827 Flash Memory PROM Mode............................................................................................. 828 19.20.1 PROM Mode Setting............................................................................................ 828 19.20.2 Socket Adapters and Memory Map...................................................................... 829 19.20.3 PROM Mode Operation....................................................................................... 831 19.20.4 Memory Read Mode ............................................................................................ 832 19.20.5 Auto-Program Mode ............................................................................................ 836 19.20.6 Auto-Erase Mode ................................................................................................. 838 19.20.7 Status Read Mode ................................................................................................ 840 19.20.8 Status Polling ....................................................................................................... 841 19.20.9 PROM Mode Transition Time ............................................................................. 842 19.20.10 Notes on Memory Programming........................................................................ 843 Flash Memory Programming and Erasing Precautions ..................................................... 843 Overview of Flash Memory (H8S/2326 F-ZTAT)............................................................ 849 19.22.1 Features................................................................................................................ 849 19.22.2 Overview.............................................................................................................. 850 19.22.3 Flash Memory Operating Modes ......................................................................... 851 19.22.4 On-Board Programming Modes........................................................................... 852 19.22.5 Flash Memory Emulation in RAM ...................................................................... 854 19.22.6 Differences between Boot Mode and User Program Mode ................................. 855 19.22.7 Block Configuration............................................................................................. 856 19.22.8 Pin Configuration................................................................................................. 857 19.22.9 Register Configuration......................................................................................... 858 Rev.6.00 Sep. 27, 2007 Page xxvi of xxx REJ09B0220-0600 19.23 Register Descriptions ........................................................................................................ 859 19.23.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 859 19.23.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 862 19.23.3 Erase Block Register 1 (EBR1) ........................................................................... 865 19.23.4 Erase Block Registers 2 (EBR2) .......................................................................... 866 19.23.5 System Control Register 2 (SYSCR2) ................................................................. 867 19.23.6 RAM Emulation Register (RAMER)................................................................... 868 19.24 On-Board Programming Modes........................................................................................ 870 19.24.1 Boot Mode ........................................................................................................... 870 19.24.2 User Program Mode............................................................................................. 876 19.25 Programming/Erasing Flash Memory ............................................................................... 878 19.25.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) ................................................. 878 19.25.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) ........................................................ 879 19.25.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) ................................................. 881 19.25.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) ........................................................ 882 19.26 Flash Memory Protection.................................................................................................. 884 19.26.1 Hardware Protection ............................................................................................ 884 19.26.2 Software Protection.............................................................................................. 884 19.26.3 Error Protection.................................................................................................... 885 19.27 Flash Memory Emulation in RAM ................................................................................... 887 19.27.1 Emulation in RAM............................................................................................... 887 19.27.2 RAM Overlap ...................................................................................................... 888 19.28 Interrupt Handling when Programming/Erasing Flash Memory....................................... 889 19.29 Flash Memory PROM Mode............................................................................................. 890 19.29.1 PROM Mode Setting............................................................................................ 890 19.29.2 Socket Adapters and Memory Map...................................................................... 891 19.29.3 PROM Mode Operation....................................................................................... 893 19.29.4 Memory Read Mode ............................................................................................ 894 19.29.5 Auto-Program Mode ............................................................................................ 898 19.29.6 Auto-Erase Mode ................................................................................................. 900 19.29.7 Status Read Mode ................................................................................................ 902 19.29.8 Status Polling ....................................................................................................... 904 19.29.9 PROM Mode Transition Time ............................................................................. 904 19.29.10 Notes on Memory Programming........................................................................ 905 19.30 Flash Memory Programming and Erasing Precautions ..................................................... 906 Rev.6.00 Sep. 27, 2007 Page xxvii of xxx REJ09B0220-0600 Section 20 Clock Pulse Generator .....................................................................911 20.1 Overview........................................................................................................................... 911 20.1.1 Block Diagram ..................................................................................................... 911 20.1.2 Register Configuration......................................................................................... 912 20.2 Register Descriptions ........................................................................................................ 912 20.2.1 System Clock Control Register (SCKCR) ........................................................... 912 20.3 Oscillator........................................................................................................................... 914 20.3.1 Connecting a Crystal Resonator........................................................................... 914 20.3.2 External Clock Input ............................................................................................ 916 20.4 Duty Adjustment Circuit ................................................................................................... 918 20.5 Medium-Speed Clock Divider .......................................................................................... 918 20.6 Bus Master Clock Selection Circuit .................................................................................. 918 Section 21 Power-Down Modes ........................................................................919 21.1 Overview........................................................................................................................... 919 21.1.1 Register Configuration......................................................................................... 920 21.2 Register Descriptions ........................................................................................................ 921 21.2.1 Standby Control Register (SBYCR) .................................................................... 921 21.2.2 System Clock Control Register (SCKCR) ........................................................... 923 21.2.3 Module Stop Control Register (MSTPCR) .......................................................... 925 21.3 Medium-Speed Mode........................................................................................................ 925 21.4 Sleep Mode ....................................................................................................................... 926 21.5 Module Stop Mode............................................................................................................ 927 21.5.1 Module Stop Mode .............................................................................................. 927 21.5.2 Usage Notes ......................................................................................................... 928 21.6 Software Standby Mode.................................................................................................... 929 21.6.1 Software Standby Mode....................................................................................... 929 21.6.2 Clearing Software Standby Mode ........................................................................ 929 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 930 21.6.4 Software Standby Mode Application Example.................................................... 930 21.6.5 Usage Notes ......................................................................................................... 931 21.7 Hardware Standby Mode .................................................................................................. 932 21.7.1 Hardware Standby Mode ..................................................................................... 932 21.7.2 Hardware Standby Mode Timing......................................................................... 932 21.8 φ Clock Output Disabling Function .................................................................................. 933 Section 22 Electrical Characteristics .................................................................935 22.1 Electrical Characteristics of Mask ROM Version (H8S/2328, H8S/2327, H8S/2323) and ROMless Version (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) ........................ 935 22.1.1 Absolute Maximum Ratings ................................................................................ 935 Rev.6.00 Sep. 27, 2007 Page xxviii of xxx REJ09B0220-0600 22.1.2 DC Characteristics ............................................................................................... 936 22.1.3 AC Characteristics ............................................................................................... 940 22.1.4 A/D Conversion Characteristics........................................................................... 964 22.1.5 D/A Conversion Characteristics........................................................................... 965 22.2 Electrical Characteristics of F-ZTAT (H8S/2329B F-ZTAT, H8S/2329E F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) ....................................................................... 966 22.2.1 Absolute Maximum Ratings ................................................................................ 966 22.2.2 DC Characteristics ............................................................................................... 967 22.2.3 AC Characteristics ............................................................................................... 970 22.2.4 A/D Conversion Characteristics........................................................................... 975 22.2.5 D/A Conversion Characteristics........................................................................... 976 22.2.6 Flash Memory Characteristics ............................................................................. 977 22.3 Usage Note........................................................................................................................ 978 Appendix A Instruction Set ...............................................................................979 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .................................................................................................................. 979 Instruction Codes .............................................................................................................. 1003 Operation Code Map......................................................................................................... 1018 Number of States Required for Instruction Execution ...................................................... 1022 Bus States during Instruction Execution ........................................................................... 1036 Condition Code Modification ........................................................................................... 1050 Appendix B Internal I/O Registers ....................................................................1056 B.1 B.2 B.3 List of Registers (Address Order) ..................................................................................... 1056 List of Registers (By Module)........................................................................................... 1066 Functions........................................................................................................................... 1077 Appendix C I/O Port Block Diagrams ...............................................................1219 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Port 1................................................................................................................................. 1219 Port 2................................................................................................................................. 1222 Port 3................................................................................................................................. 1226 Port 4................................................................................................................................. 1229 Port 5................................................................................................................................. 1230 Port 6................................................................................................................................. 1234 Port A................................................................................................................................ 1240 Port B ................................................................................................................................ 1243 Port C ................................................................................................................................ 1244 Port D................................................................................................................................ 1245 Port E ................................................................................................................................ 1246 Port F................................................................................................................................. 1247 Rev.6.00 Sep. 27, 2007 Page xxix of xxx REJ09B0220-0600 C.13 Port G................................................................................................................................ 1255 Appendix D Pin States.......................................................................................1259 D.1 Port States in Each Mode .................................................................................................. 1259 Appendix E Product Lineup ..............................................................................1266 Appendix F Package Dimensions......................................................................1267 Rev.6.00 Sep. 27, 2007 Page xxx of xxx REJ09B0220-0600 Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2329 Group and H8S/2328 Group are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip supporting functions required for system configuration include DMA controller (DMAC)*1 and data transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM and other kinds of memory. Single-power-supply flash memory (F-ZTAT™*2) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The features of the H8S/2329 Group is shown in table 1.1. Notes: 1. The DMAC is not supported in the H8S/2321. 2. F-ZTAT is a trademark of Renesas Technology Corp. Rev.6.00 Sep. 27, 2007 Page 1 of 1268 REJ09B0220-0600 Section 1 Overview Table 1.1 Item CPU Overview Specification • General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate: 25 MHz ⎯ High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 40 ns (at 25-MHz operation) 16 × 16-bit register-register multiply: 800 ns (at 25-MHz operation) 32 ÷ 16-bit register-register divide: 800 ns (at 25-MHz operation) • Instruction set suitable for high-speed operation ⎯ Sixty-five basic instructions ⎯ 8/16/32-bit move/arithmetic and logic instructions ⎯ Unsigned/signed multiply and divide instructions ⎯ Powerful bit-manipulation instructions • CPU operating mode ⎯ Advanced mode: 16-Mbyte address space Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable Maximum 8-Mbyte DRAM* directly connectable (or use of interval timer possible) • External bus release function Choice of short address mode or full address mode 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible Can be activated by internal interrupt Bus controller • • • • • • • DMA controller* (DMAC) • • • • • • Rev.6.00 Sep. 27, 2007 Page 2 of 1268 REJ09B0220-0600 Section 1 Overview Item Data transfer controller (DTC) Specification • • • • 16-bit timer-pulse unit (TPU) • • • Programmable pulse generator (PPG) • • • • 8-bit timer, 2 channels • • • Watchdog timer (WDT) Serial communication interface (SCI), 3 channels A/D converter • • • • • • • • • • D/A converter I/O ports • • • Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channel High-speed conversion: 6.7 µs minimum conversion time (at 20-MHz operation) Single or scan mode selectable Sample-and-hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 86 input/output pins, 9 input pins Rev.6.00 Sep. 27, 2007 Page 3 of 1268 REJ09B0220-0600 Section 1 Overview Item Memory Specification • • Flash memory, mask ROM High-speed static RAM ROM *1 384 kbytes 256 kbytes 128 kbytes 512 kbytes — 32 kbytes — — — RAM 32 kbytes 8 kbytes 8 kbytes 8 kbytes 32 kbytes 8 kbytes 8 kbytes 4 kbytes 4 kbytes Product Code H8S/2329B, H8S/2329E 2 H8S/2328* , H8S/2328B H8S/2327 H8S/2326 H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320 Notes: 1. The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions are unavailable when the on-chip debug function is in use. Refer to figures 1.7 and 1.8, Pin Arrangement. For specifications, refer to the item for the H8S/2329B F-ZTAT. 2. Mask ROM version only. Interrupt controller • • • Power-down state • • • • • • 39 external interrupt pins (NMI, IRQ0 to IRQ7) 52 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Variable clock division ratio Rev.6.00 Sep. 27, 2007 Page 4 of 1268 REJ09B0220-0600 Section 1 Overview Item Operating modes Specification • Eight MCU operating modes (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) External Data Bus On-Chip Initial ROM Value — — Maximum Value — CPU Operating Description Mode Mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Advanced User program mode — — Advanced Boot mode — Advanced On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode — — — Disabled 16 bits 8 bits Enabled 8 bits — — Enabled — Enabled — 8 bits — — 8 bits — 16 bits 16 bits 16 bits — — 16 bits — — 16 bits — Rev.6.00 Sep. 27, 2007 Page 5 of 1268 REJ09B0220-0600 Section 1 Overview Item Operating modes Specification • Four MCU operating modes (ROMless, mask ROM versions, H8S/2329B F-ZTAT) External Data Bus On-Chip Initial ROM Value — — Maximum Value — CPU Operating Description Mode Mode 1 1 2* 1 3* 2 4* — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 2 5* On-chip ROM disabled Disabled 8 bits 16 bits expansion mode 6 On-chip ROM enabled Enabled 8 bits 16 bits expansion mode 7 Single-chip mode Enabled — — Notes: 1. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes. 2. The ROMless versions can use only modes 4 and 5. Clock pulse generator • Built-in duty correction circuit Rev.6.00 Sep. 27, 2007 Page 6 of 1268 REJ09B0220-0600 Section 1 Overview Item Product lineup Operating power supply voltage Operating frequency Model HD64F2329B HD64F2329E* HD6432328 HD64F2328B HD6432327 HD64F2326 HD6412324S HD6432323 HD6412322R HD6412321 HD6412320 Specification Condition A 2.7 to 3.6 V 2 to 20 MHz — — O — O — O O O O Condition B 3.0 to 3.6 V 2 to 25 MHz O O O O O O O O O O O O O: Products in the current lineup Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions are unavailable when the on-chip debug function is in use. Refer to figures 1.7 and 1.8, Pin Arrangement. For specifications, refer to the item for the H8S/2329B F-ZTAT. Note: * Not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 7 of 1268 REJ09B0220-0600 Section 1 Overview 1.2 Block Diagram PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Port D Port E Internal data bus H8S/2000 CPU Internal address bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF (FWE, EMLE)*1 NMI Port A Clock pulse generator PA7 /A23 / IRQ7 PA6 /A22 / IRQ6 PA5 /A21 / IRQ5 PA4 /A20 / IRQ4 PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16 PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8 PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 Interrupt controller PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 / LCAS / WAIT / BREQO PF1 / BACK PF0 / BREQ PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS P67 / CS7 / IRQ3 P66 / CS6 / IRQ2 P65 / IRQ1 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 P60 / DREQ0 / CS4 DTC Port B Peripheral address bus Peripheral data bus ROM*2 Port F DMAC Port C WDT RAM Port G 8-bit timer P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 P53 / ADTRG/IRQ7/WAIT/BREQO P52 /SCK2/IRQ6 P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 SCI TPU D/A converter Port 6 Port 3 PPG A/D converter Port 5 Port 1 Port 2 Port 4 Vref AVCC AVSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 / TCLKB P12 /PO10 /TIOCC0 / TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 Notes: 1. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The EMLE pin applies to the H8S/2329B F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. 2. ROM is not supported in the ROMless versions. Figure 1.1 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Internal Block Diagram Rev.6.00 Sep. 27, 2007 Page 8 of 1268 REJ09B0220-0600 P27 /PO7 /TIOCB5 /TMO1 P26 /PO6 /TIOCA5 /TMO0 P25 /PO5 /TIOCB4 / TMCI1 P24 /PO4 /TIOCA4 / TMRI1 P23 /PO3 /TIOCD3 / TMCI0 P22 /PO2 /TIOCC3 / TMRI0 P21 /PO1 / TIOCB3 P20 /PO0 / TIOCA3 P47 /AN7 /DA1 P46 /AN6 /DA0 P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40 /AN0 Section 1 Overview PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Port D PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Port E Internal data bus H8S/2000 CPU Internal address bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI Port A Clock pulse generator PA7 / A23 / IRQ7 PA6 / A22 / IRQ6 PA5 / A21 / IRQ5 PA4 / A20 / IRQ4 PA3 / A19 PA2 / A18 PA1 / A17 PA0 / A16 PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Interrupt controller PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 / WAIT / BREQO PF1 / BACK PF0 / BREQ PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 P67 / CS7 / IRQ3 P66 / CS6 / IRQ2 P65 / IRQ1 P64 / IRQ0 P63 P62 P61 / CS5 P60 / CS4 DTC Port B Peripheral address bus Peripheral data bus Port F Port C WDT RAM Port G 8-bit timer P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 /TxD1 P30 /TxD0 P53 / ADTRG/IRQ7/WAIT/BREQO P52 / SCK2/IRQ6 P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 SCI TPU D/A converter Port 6 Port 3 PPG A/D converter Port 5 Port 1 Port 2 Port 4 Vref AVCC AVSS P17 / PO15 /TIOCB2 /TCLKD P16 / PO14 /TIOCA2 P15 / PO13 /TIOCB1 /TCLKC P14 / PO12 /TIOCA1 P13 / PO11 /TIOCD0 /TCLKB P12 / PO10 /TIOCC0 /TCLKA P11 / PO9 /TIOCB0 P10 / PO8 /TIOCA0 Figure 1.2 H8S/2321 Internal Block Diagram P27 / PO7 /TIOCB5 /TMO1 P26 / PO6 /TIOCA5 /TMO0 P25 / PO5 /TIOCB4 /TMCI1 P24 / PO4 /TIOCA4 /TMRI1 P23 / PO3 /TIOCD3 /TMCI0 P22 / PO2 /TIOCC3 /TMRI0 P21 / PO1 /TIOCB3 P20 / PO0 /TIOCA3 P47 / AN7 / DA1 P46 / AN6 / DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Rev.6.00 Sep. 27, 2007 Page 9 of 1268 REJ09B0220-0600 Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE)* P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP-120: Top View) Rev.6.00 Sep. 27, 2007 Page 10 of 1268 REJ09B0220-0600 VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P52 /SCK2 / IRQ6 P53 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /DA0 /AN6 P47 /DA1 /AN7 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 / TCLKB P12 /PO10 /TIOCC0 / TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 PG3 / CS1 PG4 / CS0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0 / CS4 VSS P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC P64 / IRQ0 P65 / IRQ1 Section 1 Overview Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. Figure 1.4 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (FP-128B: Top View) PG3 / CS1 PG4 / CS0 VSS VSSNC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6 /DA0 P47 /AN7 /DA1 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 /TCLKB P12 /PO10 /TIOCC0 /TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P53 / ADTRG/IRQ7/WAIT/BREQO P52 /SCK2 /IRQ6 VSS VSS P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE)* P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 VSS VSS P60 / DREQ0 / CS4 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 /SCK1 P34 /SCK0 P33 / RxD1 P32 / RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC Rev.6.00 Sep. 27, 2007 Page 11 of 1268 REJ09B0220-0600 Section 1 Overview Figure 1.5 H8S/2321 Pin Arrangement (TFP-120: Top View) Rev.6.00 Sep. 27, 2007 Page 12 of 1268 REJ09B0220-0600 VCC PC0 / A0 PC1 / A1 PC2 / A2 PC3 / A3 VSS PC4 / A4 PC5 / A5 PC6 / A6 PC7 / A7 PB0 / A8 PB1 / A9 PB2 / A10 PB3 / A11 VSS PB4 / A12 PB5 / A13 PB6 / A14 PB7 / A15 PA0 / A16 PA1 /A17 PA2 / A18 PA3 / A19 VSS PA4 / A20 / IRQ4 PA5 / A21 / IRQ5 PA6 / A22 / IRQ6 PA7 / A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P52 /SCK2 / IRQ6 P53 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40 /AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / DA0 / AN6 P47 / DA1 / AN7 AVSS VSS P17 / PO15 /TIOCB2 /TCLKD P16 / PO14 /TIOCA2 P15 / PO13 /TIOCB1 /TCLKC P14 / PO12 /TIOCA1 P13 / PO11 /TIOCD0 /TCLKB P12 / PO10 /TIOCC0 /TCLKA P11 / PO9 /TIOCB0 P10 / PO8 /TIOCA0 MD0 MD1 MD2 PG0 PG1 / CS3 PG2 / CS2 PG3 / CS1 PG4 / CS0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF 6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 / PO0 /TIOCA3 P21 / PO1 /TIOCB3 P22 / PO2 /TIOCC3 /TMRI0 P23 / PO3 /TIOCD3 /TMCI0 P24 / PO4 /TIOCA4 /TMRI1 P25 / PO5 /TIOCB4 /TMCI1 P26 / PO6 /TIOCA5 /TMO0 P27 / PO7 /TIOCB5 /TMO1 P63 P62 P61 / CS5 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / CS4 VSS P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P64 / IRQ0 P65 / IRQ1 AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6 / DA0 P47 / AN7 / DA1 AVSS VSS P17 / PO15 / TIOCB2 / TCLKD P16 / PO14 / TIOCA2 P15 / PO13 / TIOCB1 / TCLKC P14 / PO12 / TIOCA1 P13 / PO11 / TIOCD0 / TCLKB P12 / PO10 / TIOCC0 / TCLKA P11 / PO9 / TIOCB0 P10 / PO8 / TIOCA0 MD0 MD1 MD2 PG0 PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Figure 1.6 H8S/2321 Pin Arrangement (FP-128B: Top View) PG3 / CS1 PG4 / CS0 VSS VSSNC VCC PC0 / A0 PC1 / A1 PC2 / A2 PC3 / A3 VSS PC4 / A4 PC5 / A5 PC6 / A6 PC7 / A7 PB0 / A8 PB1 / A9 PB2 / A10 PB3 / A11 VSS PB4 / A12 PB5 / A13 PB6 / A14 PB7 / A15 PA0 / A16 PA1 / A17 PA2 / A18 PA3 / A19 VSS PA4 / A20 / IRQ4 PA5 / A21 / IRQ5 PA6 / A22 / IRQ6 PA7 / A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P53 / ADTRG/IRQ7/WAIT/BREQO P52 / SCK2 /IRQ6 VSS VSS P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 / PO0 /TIOCA3 P21 / PO1 /TIOCB3 P22 / PO2 /TIOCC3 /TMRI0 P23 / PO3 /TIOCD3 /TMCI0 P24 / PO4 /TIOCA4 /TMRI1 P25 / PO5 /TIOCB4 /TMCI1 P26 / PO6 /TIOCA5 /TMO0 P27 / PO7 /TIOCB5 /TMO1 P63 P62 P61 / CS5 VSS VSS P60 / CS4 VSS Rev.6.00 Sep. 27, 2007 Page 13 of 1268 REJ09B0220-0600 Section 1 Overview Section 1 Overview P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES EMLE P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 Figure 1.7 HD64F2329B Pin Arrangement (TFP-120: Top View) Rev.6.00 Sep. 27, 2007 Page 14 of 1268 REJ09B0220-0600 VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P52 /SCK2 / IRQ6 P53 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /DA0 /AN6 P47 /DA1 /AN7 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 / TCLKB P12 /PO10 /TIOCC0 / TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 PG3 / CS1 PG4 / CS0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0 / CS4 VSS P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC P64 / IRQ0 P65 / IRQ1 AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6 /DA0 P47 /AN7 /DA1 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 /TCLKB P12 /PO10 /TIOCC0 /TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Figure 1.8 HD64F2329B Pin Arrangement (FP-128B: Top View) PG3 / CS1 PG4 / CS0 VSS VSSNC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 /SCK1 P34 /SCK0 P33 / RxD1 P32 / RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P53 / ADTRG/IRQ7/WAIT/BREQO P52 /SCK2 /IRQ6 VSS VSS P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /φ VSS EXTAL XTAL VCC STBY NMI RES EMLE P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 VSS VSS P60 / DREQ0 / CS4 VSS Rev.6.00 Sep. 27, 2007 Page 15 of 1268 REJ09B0220-0600 Section 1 Overview Section 1 Overview E10A compatible version P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES EMLE* P52 /SCK2 / IRQ6 P53 /ADTRG/IRQ7/WAIT/BREQO AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /DA0 /AN6 P47 /DA1 /AN7 AVSS VSS P17 /PO15 /TIOCB2 /TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 /TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 / TCLKB P12 /PO10 /TIOCC0 / TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 PG3 / CS1 PG4 / CS0 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1/TDO * P62 / DREQ1/TDI * P61 / TEND0 / CS5/TCK * Note: * If an E10A emulator is used, the TDO, TDI, TDK, TMS, and TRST pins are used exclusively for the H-UDI and the functions and function modules associated with these pins are not available. SCI channel 0 is not available. Also, the watchdog timer continues to operate during break states and, if the settings specify that an internal reset is to be performed, a reset is generated if an overflow occurs. Refer to the E10A Emulator User's Manual for E10A emulator connection examples. Figure 1.9 HD64F2329E Pin Arrangement (TFP-120: Top View) Rev.6.00 Sep. 27, 2007 Page 16 of 1268 REJ09B0220-0600 VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0 / CS4/TMS * VSS P35 /SCK1 P34 /SCK0*/ TRST* P33 / RxD1 P32 / RxD0* P31 / TxD1 P30 / TxD0* VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC P64 / IRQ0 P65 / IRQ1 Section 1 Overview E10A compatible version P53 / ADTRG/IRQ7/WAIT/BREQO P52 /SCK2 /IRQ6 VSS VSS P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /φ VSS EXTAL XTAL VCC STBY NMI RES EMLE* P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1/TDO * P62 / DREQ1/ T D I * P61 / TEND0 / CS5/TCK * VSS VSS P60 / DREQ0 / CS4/TMS * VSS Note: * If an E10A emulator is used, the TDO, TDI, TDK, TMS, and TRST pins are used exclusively for the H-UDI and the functions and function modules associated with these pins are not available. SCI channel 0 is not available. Also, the watchdog timer continues to operate during break states and, if the settings specify that an internal reset is to be performed, a reset is generated if an overflow occurs. Refer to the E10A Emulator User's Manual for E10A emulator connection examples. Figure 1.10 HD64F2329E Pin Arrangement (FP-128B: Top View) PG3 / CS1 PG4 / CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6 /DA0 P47 /AN7 /DA1 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12 /TIOCA1 P13 /PO11 /TIOCD0 /TCLKB P12 /PO10 /TIOCC0 /TCLKA P11 /PO9 /TIOCB0 / DACK1 P10 /PO8 /TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 /SCK1 P34 /SCK0*/ TRST* P33 /RxD1 P32 /RxD0* P31 /TxD1 P30 /TxD0* VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC Rev.6.00 Sep. 27, 2007 Page 17 of 1268 REJ09B0220-0600 Section 1 Overview 1.3.2 Table 1.2 Pin Functions in Each Operating Mode Pin Functions in Each Operating Mode Pin Name Flash Memory Programmer Mode VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 NC VSS NC NC NC Pin No. TFP-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FP-128B 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mode 4* VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 1 Mode 5* VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 1 Mode 6 VCC PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 VSS PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 VSS PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 Mode 7 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 VSS PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 VSS PA4/IRQ4 PA5/IRQ5 PA6/IRQ6 PA5/A21/IRQ5 PA6/A22/IRQ6 PA5/A21/IRQ5 PA6/A22/IRQ6 Rev.6.00 Sep. 27, 2007 Page 18 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode NC NC VCC VSS VSS VSS VSS VCC NC NC NC NC VSS NC NC NC NC I/O0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 VCC NC NC NC TFP-120 28 29 30 — — 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 FP-128B 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Mode 4* 1 Mode 5* 1 Mode 6 PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 7 PA7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0 PE1 PE2 PE3 VSS PE4 PE5 PE6 PE7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 P32/RxD0 PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 PA7/A23/IRQ7 P67/IRQ3/CS7 P66/IRQ2/CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Rev.6.00 Sep. 27, 2007 Page 19 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode NC NC NC VSS NC VSS VSS NC NC NC NC NC VSS WE TFP-120 56 57 58 59 60 — — 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 FP-128B 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Mode 4* 1 Mode 5* 1 Mode 6 P33/RxD1 P34/SCK0 P35/SCK1 VSS 2 P60/DREQ0* / Mode 7 P33/RxD1 P34/SCK0 P35/SCK1 VSS 2 P60/DREQ0* P33/RxD1 P34/SCK0 P35/SCK1 VSS 2 P60/DREQ0* / P33/RxD1 P34/SCK0 P35/SCK1 VSS 2 P60/DREQ0* / CS4 VSS VSS 2 P61/TEND0* / CS4 VSS VSS 2 P61/TEND0* / CS4 VSS VSS 2 P61/TEND0* / VSS VSS 2 P61/TEND0* CS5 P62/DREQ1* P63/TEND1 2 CS5 P62/DREQ1* P63/TEND1 2 CS5 P62/DREQ1* P63/TEND1 2 P62/DREQ1* P63/TEND1 2 *2 *2 *2 *2 P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0 P25/PO5/ TIOCB4/TMCI1 P24/PO4/ TIOCA4/TMRI1 P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0 P25/PO5/ TIOCB4/TMCI1 P24/PO4/ TIOCA4/TMRI1 P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0 P25/PO5/ TIOCB4/TMCI1 P24/PO4/ TIOCA4/TMRI1 P27/PO7/ TIOCB5/TMO1 P26/PO6/ TIOCA5/TMO0 P25/PO5/ TIOCB4/TMCI1 P24/PO4/ TIOCA4/TMRI1 P23/PO3/ P23/PO3/ P23/PO3/ P23/PO3/ CE TIOCD3/TMCI0 TIOCD3/TMCI0 TIOCD3/TMCI0 TIOCD3/TMCI0 P22/PO2/ P22/PO2/ P22/PO2/ P22/PO2/ OE TIOCC3/TMRI0 TIOCC3/TMRI0 TIOCC3/TMRI0 TIOCC3/TMRI0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 NC NC 3 WDTOVF WDTOVF WDTOVF WDTOVF FWE, EMLE* 3 3 3 3 (FWE, EMLE)* (FWE, EMLE)* (FWE, EMLE)* (FWE, EMLE)* RES NMI STBY RES NMI STBY RES NMI STBY RES NMI STBY RES VCC VCC Rev.6.00 Sep. 27, 2007 Page 20 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode VCC XTAL EXTAL VSS NC VCC NC NC NC NC NC NC NC NC TFP-120 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 — — 91 92 FP-128B 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Mode 4* VCC XTAL EXTAL VSS PF7/φ VCC PF6/AS RD HWR 1 Mode 5* VCC XTAL EXTAL VSS PF7/φ VCC PF6/AS RD HWR 1 Mode 6 VCC XTAL EXTAL VSS PF7/φ VCC PF6/AS RD HWR PF3/LWR 4 PF2/LCAS* / Mode 7 VCC XTAL EXTAL VSS PF7/φ VCC P F6 PF5 P F4 P F3 P F2 P F1 P F0 P50/TxD2/IRQ4 PF3/LWR 4 PF2/LCAS* / PF3/LWR 4 PF2/LCAS* / WAIT/BREQO PF1/BACK PF0/BREQ P50/TxD2/IRQ4 WAIT/BREQO PF1/BACK PF0/BREQ P50/TxD2/IRQ4 WAIT/BREQO PF1/BACK PF0/BREQ P50/TxD2/IRQ4 P51/RxD2/IRQ5 P51/RxD2/IRQ5 P51/RxD2/IRQ5 P51/RxD2/IRQ5 VCC VSS VSS P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 VSS VSS P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 VSS VSS P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7/WAIT/ BREQO AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 VSS VSS P52/SCK2/ IRQ6 P53/ADTRG/ IRQ7 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 VSS VSS NC NC 93 94 95 96 97 98 99 100 103 104 105 106 107 108 109 110 VCC VCC NC NC NC NC NC NC Rev.6.00 Sep. 27, 2007 Page 21 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode NC NC VSS VSS NC TFP-120 101 102 103 104 105 FP-128B 111 112 113 114 115 Mode 4* 1 Mode 5* 1 Mode 6 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ 5 DACK1* P10/PO8/ TIOCA0/ 6 DACK0* MD0 MD1 MD2 Mode 7 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ 5 DACK1* P10/PO8/ TIOCA0/ 6 DACK0* MD0 MD1 MD2 P46/AN6/DA0 P47/AN7/ DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ 5 DACK1* P10/PO8/ TIOCA0/ 6 DACK0* MD0 MD1 MD2 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ 5 DACK1* P10/PO8/ TIOCA0/ 6 DACK0* MD0 MD1 MD2 106 107 116 117 NC NC 108 109 118 119 NC NC 110 120 NC 111 121 NC 112 122 NC 113 114 115 116 117 118 119 120 123 124 125 126 127 128 1 2 VSS VSS VSS NC NC NC NC NC *6 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 *6 PG0/CAS PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 *6 PG0 PG1 PG2 PG3 PG4 Rev.6.00 Sep. 27, 2007 Page 22 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Pin Name Flash Memory Programmer Mode VSS TFP-120 — — FP-128B 3 4 Mode 4* VSS VSSNC 1 Mode 5* VSS 1 Mode 6 VSS Mode 7 VSS *7 VSSNC *7 VSSNC *7 VSSNC *7 NC Notes: 1. Only modes 4 and 5 are provided in the ROMless version. 2. The DREQ0, TEND0, DREQ1, and TEND1 pin functions are not supported in the H8S/2321. 3. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The EMLE pin applies to the H8S/2329B F-ZTAT only. The WDTOVF pin function is not available in the F-ZTAT versions. 4. The LCAS pin function is not supported in the H8S/2321. 5. The DACK1 pin function is not supported in the H8S/2321. 6. The DACK0 and CAS pin functions are not supported in the H8S/2321. 7. The VSSNC pin is connected to the VSS pin or released. Rev.6.00 Sep. 27, 2007 Page 23 of 1268 REJ09B0220-0600 Section 1 Overview 1.3.3 Table 1.3 Pin Functions Pin Functions Pin No. Type Power Symbol VCC TFP-120 1, 33, 52, 76, 81 6, 15, 24, 38, 47, 59, 79, 104 FP-128B I/O 5, 39, 58, 84, 89 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 85 Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). VSS Input Clock XTAL 77 Input Connects to a crystal resonator. See section 20, Clock Pulse Generator for typical connection diagrams for a crystal resonator and external clock input. Connects to a crystal resonator. The EXTAL pin can also input an external clock. See section 20, Clock Pulse Generator for typical connection diagrams for a crystal resonator and external clock input. EXTAL 78 86 Input φ 80 88 Output System clock: Supplies the system clock to an external device. Rev.6.00 Sep. 27, 2007 Page 24 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type Symbol TFP-120 115 to 113 FP-128B 125 to 123 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the chip is operating. H8S/2328B F-ZTAT, H8S/2326 F-ZTAT: Operating FWE MD2 MD1 MD0 Mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 — — — Mode 4 Mode 5 Mode 6 Mode 7 — — Mode 10 Mode 11 — — Mode 14 Mode 15 Operating mode MD2 to control MD0 Rev.6.00 Sep. 27, 2007 Page 25 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type Symbol TFP-120 115 to 113 FP-128B 125 to 123 I/O Input Name and Function Mask ROM and ROMless versions, H8S/2329B F-ZTAT: MD2 0 MD1 0 1 1 0 1 MD0 1 0 1 0 1 0 1 Operating Mode — Mode 2* 1 Mode 3* Mode 4* 2 Mode 5* Mode 6 Mode 7 2 1 Operating mode MD2 to control MD0 Notes: 1. Applies to the H8S/2329B F-ZTAT only. 2. The ROMless versions can use only modes 4 and 5. System control RES STBY 73 75 81 83 Input Input Reset input: W hen this pin is driven low, the chip is reset. Standby: W hen this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the chip. BREQ 88 96 Input BREQO 86, 92 94, 102 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. BACK 87 95 Rev.6.00 Sep. 27, 2007 Page 26 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type System control Symbol 1 FWE* TFP-120 72 FP-128B 80 80 82 I/O Input Input Input Name and Function Flash write enable: Enables/ disables flash memory programming. Emulator enable: For connection to the power supply (0 V) Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. EMLE* Interrupts NMI 2 72 74 IRQ7 to IRQ0 28 to 25, 29 to 32, 89 to 92 32 to 29, Input 33, 34, 37, 38, 97, 98, 101, 102 32 to 29, 27 to 20, 18 to 11, 9 to 6 57 to 54, 52 to 45, 43 to 40 Address bus A23 to A0 28 to 25, 23 to 16, 14 to 7, 5 to 2 51 to 48, 46 to 39, 37 to 34 Output Address bus: These pins output an address. Data bus D15 to D0 CS7 to CS0 I/O Data bus: These pins constitute a bidirectional data bus. Bus control 29, 30, 33, 34, Output Chip select: Signals for selecting 61, 60, 69, 66, areas 7 to 0. 117 to 120 127, 128, 1, 2 82 90 Output Address strobe: W hen this pin is low, it indicates that address output on the address bus is enabled. Output Read: W hen this pin is low, it indicates that the external address space can be read. Output High write/write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2-CAS type DRAM write enable signal. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. AS RD 83 91 HWR 84 92 LWR 85 93 Rev.6.00 Sep. 27, 2007 Page 27 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type Bus control Symbol 4 CAS* TFP-120 116 FP-128B 126 I/O Name and Function Output Upper column address strobe/ column address strobe: The 2-CAS type DRAM upper column address strobe signal. Output Lower column address strobe: The 2-CAS type DRAM lower column address strobe signal. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state access space. DMA request 1 and 0: These pins request DMAC activation. LCAS* 4 86 94 WAIT 86, 92 94, 102 DMA controller 3 (DMAC) * DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0 62, 60 63, 61 70, 66 71, 69 Input Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins. Clock input D to A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. 111, 112 121, 122 16-bit timer pulse unit (TPU) TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 105, 107, 115, 117, Input 109, 110 119, 120 112 to 109 122 to 119 I/O 108, 107 118, 117 I/O TIOCA2, TIOCB2 106, 105 116, 115 I/O TIOCA3, TIOCB3, TIOCC3, TIOCD3 71 to 68 79 to 76 I/O Rev.6.00 Sep. 27, 2007 Page 28 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type 16-bit timer pulse unit (TPU) Symbol TIOCA4, TIOCB4 TFP-120 67, 66 FP-128B 75, 74 I/O I/O Name and Function Input capture/output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. TIOCA5, TIOCB5 65, 64 73, 72 I/O Programmable PO15 to pulse generator PO0 (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Watchdog timer (WDT) Serial communication interface (SCI)/ smart card interface 5 105 to 112, 64 to 71 65, 64 68, 66 115 to 122, 72 to 79 73, 72 76, 74 Output Pulse output 15 to 0: Pulse output pins. Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins. 69, 67 77, 75 80 Input WDTOVF* 72 Output Watchdog timer overflow: The counter overflow signal output pin in watchdog timer mode. Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. Serial clock (channel 0, 1, 2): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 89, 54, 53 90, 56, 55 91, 58, 57 102 to 95 92 97, 60, 59 98, 62, 61 101, 64, 63I/O A/D converter AN7 to AN0 ADTRG 112 to 105 102 Input Input D/A converter DA1, DA0 102, 101 112, 111 Output Analog output: D/A converter analog output pins. Rev.6.00 Sep. 27, 2007 Page 29 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type A/D converter and D/A converter Symbol AVCC TFP-120 93 FP-128B 103 I/O Input Name and Function This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). AVSS 103 113 Input Vref 94 104 Input I/O ports P17 to P10 105 to 112 115 to 122 I/O P27 to P20 64 to 71 72 to 79 I/O P35 to P30 58 to 53 64 to 59 I/O P47 to P40 P53 to P50 102 to 95 92 to 89 112 to 105 Input 102, 101, I/O 98, 97 Rev.6.00 Sep. 27, 2007 Page 30 of 1268 REJ09B0220-0600 Section 1 Overview Pin No. Type I/O ports Symbol P67 to P60 TFP-120 29 to 32, 63 to 60 FP-128B 33, 34, 37, 38, 71 to 69, 66 32 to 29, 27 to 24 I/O I/O Name and Function Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). 5 Port B* : An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). 5 Port C* : An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). 5 Port D* : An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). PA7 to PA0 28 to 25, 23 to 20 I/O PB7 to PB0 19 to 16, 14 to 11 23 to 20, 18 to 15 I/O PC7 to PC0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O PD7 to PD0 51 to 48, 46 to 43 57 to 54, 52 to 49 I/O PE7 to PE0 42 to 39, 37 to 34 48 to 45, 43 to 40 I/O PF7 to PF0 80, 82 to 88 88, 90 to 96 I/O PG4 to PG0 120 to 116 2, 1, 128 to 126 I/O Notes: 1. 2. 3. 4. 5. Applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. Applies to the H8S/2329B F-ZTAT only. Not supported in the H8S/2321. Not available in the F-ZTAT versions. Cannot be used as an I/O port in the ROMless versions. Rev.6.00 Sep. 27, 2007 Page 31 of 1268 REJ09B0220-0600 Section 1 Overview Rev.6.00 Sep. 27, 2007 Page 32 of 1268 REJ09B0220-0600 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs ⎯ Can execute H8/300 and H8/300H object programs • General-register architecture ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-five basic instructions ⎯ 8/16/32-bit arithmetic and logic instructions ⎯ Multiply and divide instructions ⎯ Powerful bit-manipulation instructions • Eight addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@ERn] ⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] ⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] ⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ⎯ Immediate [#xx:8, #xx:16, or #xx:32] ⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)] ⎯ Memory indirect [@@aa:8] • 16-Mbyte address space ⎯ Program: 16 Mbytes ⎯ Data: 16 Mbytes (4 Gbytes architecturally) Rev.6.00 Sep. 27, 2007 Page 33 of 1268 REJ09B0220-0600 Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: ⎯ 8 × 8-bit register-register multiply: ⎯ 16 ÷ 8-bit register-register divide: ⎯ 16 × 16-bit register-register multiply: ⎯ 32 ÷ 16-bit register-register divide: • CPU operating mode ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU 25 MHz 480 ns 480 ns 800 ns 800 ns ⎯ 8/16/32-bit register-register add/subtract: 40 ns The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the product. Rev.6.00 Sep. 27, 2007 Page 34 of 1268 REJ09B0220-0600 Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space ⎯ Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing ⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced. ⎯ Signed multiply and divide instructions have been added. ⎯ Two-bit shift instructions have been added. ⎯ Instructions for saving and restoring multiple registers have been added. ⎯ A test and set instruction has been added. • Higher speed ⎯ Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register ⎯ One 8-bit control register has been added. • Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced. ⎯ Two-bit shift instructions have been added. ⎯ Instructions for saving and restoring multiple registers have been added. ⎯ A test and set instruction has been added. • Higher speed ⎯ Basic instructions execute twice as fast. Rev.6.00 Sep. 27, 2007 Page 35 of 1268 REJ09B0220-0600 Section 2 CPU 2.2 CPU Operating Modes The H8S/2329 and H8S/2328 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev.6.00 Sep. 27, 2007 Page 36 of 1268 REJ09B0220-0600 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.1). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.1 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev.6.00 Sep. 27, 2007 Page 37 of 1268 REJ09B0220-0600 Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.2 Stack Structure in Advanced Mode Rev.6.00 Sep. 27, 2007 Page 38 of 1268 REJ09B0220-0600 Section 2 CPU 2.3 Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2329 and H8S/2328 Group H'FFFFFFFF Advanced Mode Figure 2.3 Memory Map Rev.6.00 Sep. 27, 2007 Page 39 of 1268 REJ09B0220-0600 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag 0 Note: * In the H8S/2329 Group and H8S/2328 Group, this bit cannot be used as an interrupt mask. Figure 2.4 CPU Registers Rev.6.00 Sep. 27, 2007 Page 40 of 1268 REJ09B0220-0600 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.5 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) (E0 to E7) • 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.5 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.6 shows the stack. Rev.6.00 Sep. 27, 2007 Page 41 of 1268 REJ09B0220-0600 Section 2 CPU Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. Rev.6.00 Sep. 27, 2007 Page 42 of 1268 REJ09B0220-0600 Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2329 Group and H8S/2328 Group, this bit cannot be used as an interrupt mask bit. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Rev.6.00 Sep. 27, 2007 Page 43 of 1268 REJ09B0220-0600 Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. Rev.6.00 Sep. 27, 2007 Page 44 of 1268 REJ09B0220-0600 Section 2 CPU 2.5.1 General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don’t care 1-bit data RnL Don’t care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don’t care 4-bit BCD data RnL Don’t care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don’t care LSB 7 Don’t care Byte data RnL 0 LSB MSB Figure 2.7 General Register Data Formats Rev.6.00 Sep. 27, 2007 Page 45 of 1268 REJ09B0220-0600 Section 2 CPU Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.7 General Register Data Formats (cont) Rev.6.00 Sep. 27, 2007 Page 46 of 1268 REJ09B0220-0600 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.8 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev.6.00 Sep. 27, 2007 Page 47 of 1268 REJ09B0220-0600 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* LDM, STM 3 MOVFPE, MOVTPE* Size BWL WL L B BWL B BWL L BW WL B BWL BWL B — — Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* 19 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS EEPMOV 4 8 14 5 9 1 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — Total: 65 Legend: B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2329 Group and H8S/2328 Group. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Sep. 27, 2007 Page 48 of 1268 REJ09B0220-0600 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @@aa:8 — — — — — — — — — — — — — — — — — — — — Function Instruction @(d:16,PC) @(d:8,PC) @aa:16 @aa:24 @aa:32 @aa:8 @ERn #xx Rn Data transfer MOV POP, PUSH LDM, STM MOVFPE, MOVTPE*1 BWL — — — BWL WL B — — — — — — — — BWL — — — — — — — — — B — B — — BWL — — — BWL BWL B L BWL B BW BW BWL WL — BWL BWL BWL B — — — — — — B B — — — BWL — — — — — — — — — — — — — B — — — B — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — B — — — — — — — — — — — — — — — — — B — — — — — — — — — — — BWL — — B — — — — — — — — — — — — — — B — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWL — — — — — — — — — — — — — — — — — B — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — WL L — — — — — — — — — — — — — — — — — — Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 Logic operations Shift AND, OR, XOR NOT Bit manipulation Branch Bcc, BSR JMP, JSR RTS System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer — — — — — — — — — BW — — — Legend: B: Byte W: Word L: Longword Notes: 1. Cannot be used in the H8S/2329 Group and H8S/2328 Group. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Sep. 27, 2007 Page 49 of 1268 REJ09B0220-0600 — Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.6.00 Sep. 27, 2007 Page 50 of 1268 REJ09B0220-0600 Section 2 CPU Table 2.3 Type Data transfer Instructions Classified by Function Instruction MOV Size* 1 Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2329 Group and H8S/2328 Group. Cannot be used in the H8S/2329 Group and H8S/2328 Group. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. B/W/L MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM L L Rev.6.00 Sep. 27, 2007 Page 51 of 1268 REJ09B0220-0600 Section 2 CPU Type Arithmetic operations Instruction ADD SUB Size* 1 Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W Rev.6.00 Sep. 27, 2007 Page 52 of 1268 REJ09B0220-0600 Section 2 CPU Type Arithmetic operations Instruction DIVXS Size* B/W 1 Function Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 @ERd – 0, 1 → ( of @Erd)* Tests memory contents, and sets the most significant bit (bit 7) to 1. CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B Rev.6.00 Sep. 27, 2007 Page 53 of 1268 REJ09B0220-0600 Section 2 CPU Type Logic operations Instruction AND Size* 1 Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. B/W/L OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Rev.6.00 Sep. 27, 2007 Page 54 of 1268 REJ09B0220-0600 Section 2 CPU Type Bitmanipulation instructions Instruction BSET Size* B 1 Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Rev.6.00 Sep. 27, 2007 Page 55 of 1268 REJ09B0220-0600 Section 2 CPU Type Bitmanipulation instructions Instruction BXOR Size* B 1 Function C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. BIXOR B BLD B BILD B BST B BIST B Rev.6.00 Sep. 27, 2007 Page 56 of 1268 REJ09B0220-0600 Section 2 CPU Type Branch instructions Instruction Bcc Size* — 1 Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z∨(N ⊕ V) = 0 Z∨(N ⊕ V) = 1 JMP BSR JSR RTS — — — — Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Rev.6.00 Sep. 27, 2007 Page 57 of 1268 REJ09B0220-0600 Section 2 CPU Type Instruction Size* — — — B/W 1 Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC STC B/W ANDC B ORC B XORC B NOP — Rev.6.00 Sep. 27, 2007 Page 58 of 1268 REJ09B0220-0600 Section 2 CPU Type Block data transfer instruction Instruction EEPMOV.B Size* — 1 Function if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W — Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Sep. 27, 2007 Page 59 of 1268 REJ09B0220-0600 Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.9 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. Rev.6.00 Sep. 27, 2007 Page 60 of 1268 REJ09B0220-0600 Section 2 CPU 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev.6.00 Sep. 27, 2007 Page 61 of 1268 REJ09B0220-0600 Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Advanced Mode 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Rev.6.00 Sep. 27, 2007 Page 62 of 1268 REJ09B0220-0600 Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF). In advanced mode the memory operand is a long word operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified by @aa:8 Reserved Branch address Advanced Mode Figure 2.10 Branch Address Specification in Memory Indirect Mode Rev.6.00 Sep. 27, 2007 Page 63 of 1268 REJ09B0220-0600 Section 2 CPU If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. Rev.6.00 Sep. 27, 2007 Page 64 of 1268 REJ09B0220-0600 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 Operand is general register contents. Table 2.6 Register direct (Rn) op rm rn 2 31 General register contents Don't care 0 31 24 23 0 Register indirect (@ERn) op r 3 31 General register contents 31 disp 31 Sign extension disp 0 Don't care 24 23 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 0 Effective Address Calculation op r 4 31 General register contents 0 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 31 24 23 Don't care 0 op r 1, 2, or 4 31 General register contents 31 24 23 Don't care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 • Register indirect with pre-decrement @-DERn Rev.6.00 Sep. 27, 2007 Page 65 of 1268 REJ09B0220-0600 op r Section 2 CPU No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 5 31 24 23 H'FFFF Don't care Absolute address 87 0 @aa:8 Section 2 CPU op abs @aa:16 31 24 23 Sign extension abs Don't care 16 15 0 op @aa:24 31 24 23 abs Don't care 0 Rev.6.00 Sep. 27, 2007 Page 66 of 1268 REJ09B0220-0600 31 abs 24 23 Don't care op @aa:32 0 op 6 IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. op No. Effective Address Calculation 23 PC contents 0 Addressing Mode and Instruction Format Effective Address (EA) 7 Program-counter relative @(d:8, PC)/@(d:16, PC) op 23 Sign extension disp 31 24 23 Don’t care disp 0 0 8 Memory indirect @@aa:8 • Advanced mode abs 31 0 abs 0 Memory contents 31 24 23 Don’t care op 87 H'000000 31 0 Rev.6.00 Sep. 27, 2007 Page 67 of 1268 REJ09B0220-0600 Section 2 CPU Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2.11 Processing States Rev.6.00 Sep. 27, 2007 Page 68 of 1268 REJ09B0220-0600 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with SSBY = 1 SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.12 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13, Watchdog Timer. Rev.6.00 Sep. 27, 2007 Page 69 of 1268 REJ09B0220-0600 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 3 executed* Trace End of instruction execution or end of exception-handling 1 sequence* End of instruction execution or end of exception-handling 2 sequence* When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev.6.00 Sep. 27, 2007 Page 70 of 1268 REJ09B0220-0600 Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.13 shows the stack after exception handling ends. Rev.6.00 Sep. 27, 2007 Page 71 of 1268 REJ09B0220-0600 Section 2 CPU Advanced mode SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (c) Interrupt control mode 0 Note: * Ignored when returning. (d) Interrupt control mode 2 Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There is one other bus master in addition to the CPU: the DMA controller (DMAC)* and data transfer controller (DTC). For further details, refer to section 6, Bus Controller. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 72 of 1268 REJ09B0220-0600 Section 2 CPU 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.14 shows the on-chip memory access cycle. Figure 2.15 shows the pin states. Rev.6.00 Sep. 27, 2007 Page 73 of 1268 REJ09B0220-0600 Section 2 CPU Bus cycle T1 φ Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.14 On-Chip Memory Access Cycle Bus cycle T1 φ Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.15 Pin States during On-Chip Memory Access Rev.6.00 Sep. 27, 2007 Page 74 of 1268 REJ09B0220-0600 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access timing for the on-chip supporting modules. Figure 2.17 shows the pin states. Bus cycle T1 T2 φ Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.16 On-Chip Supporting Module Access Cycle Rev.6.00 Sep. 27, 2007 Page 75 of 1268 REJ09B0220-0600 Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 2.10.1 Usage Note TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev.6.00 Sep. 27, 2007 Page 76 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT have eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3.1. Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) External Data Bus On-Chip Initial ROM Value — — Max Value — MCU CPU Operating Operating Mode FWE MD2 MD1 MD0 Mode Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Advanced User program mode — — Advanced Boot mode — Advanced Expanded mode with on-chip ROM disabled — — Disabled 16 bits 16 bits 8 bits 16 bits 16 bits — — 16 bits — — 16 bits — Expanded mode with on- Enabled 8 bits chip ROM enabled Single-chip mode — — — — Enabled 8 bits — — — Enabled 8 bits — Rev.6.00 Sep. 27, 2007 Page 77 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. Modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. For details, see section 19, ROM. The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT) The ROMless and mask ROM versions have four operating modes (modes 4 to 7). H8S/2329B F-ZTAT has six operating modes (modes 2 to 7). The operating mode is determined by the mode pins (MD2 to MD0). The CPU operating mode, enabling or disabling of on-chip ROM, and the initial bus width setting can be selected as shown in table 3.2. Table 3.2 lists the MCU operating modes. Rev.6.00 Sep. 27, 2007 Page 78 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Table 3.2 MCU Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT) External Data Bus On-Chip Initial ROM Value — — Max. Value — MCU CPU Operating Operating MD2 MD1 MD0 Mode Description Mode 1 1 2* 1 3* 2 4* 0 0 1 1 0 1 0 1 0 1 — — 1 0 1 5* 6 7 2 Advanced Expanded mode with Disabled 16 bits on-chip ROM disabled 8 bits Expanded mode with on-chip ROM enabled Single-chip mode Enabled 8 bits — 16 bits 16 bits 16 bits — Notes: 1. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes. 2. The ROMless versions can use only modes 4 and 5. The CPU's architecture allows for 4 Gbytes of address space, but the mask ROM and ROMless versions, and H8S/2329B F-ZTAT actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The ROMless and mask ROM versions can only be used in modes 4 to 7. This means that the mode pins must be set to select one of these modes. However, note that only mode 4 or 5 can be set for the ROMless version. H8S/2329B F-ZTAT can only be used in modes 2 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. Rev.6.00 Sep. 27, 2007 Page 79 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes 3.1.3 Register Configuration The H8S/2329 Group and H8S/2328 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 (SYSCR2)*2 that control the operation of the chip. Table 3.3 summarizes these registers. Table 3.3 Name Mode control register System control register 2 System control register 2* Registers Abbreviation MDCR SYSCR SYSCR2 R/W R R/W R/W Initial Value Undefined H'01 H'00 Address* H'FF3B H'FF39 H'FF42 1 Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM and ROMless versions this register will return an undefined value if read, and cannot be modified. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2329 Group and H8S/2328 Group chip. Bit 7—Reserved: This bit is always read as 1, and cannot be modified. Bits 6 to 3—Reserved: These bits are always read as 0, and cannot be modified. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Rev.6.00 Sep. 27, 2007 Page 80 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes 3.2.2 Bit System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 R/W 1 0 R/W 0 RAME 1 R/W LWROD IRQPAS Initial value : R/W : Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode Description 0 — 2 — Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD 0 1 Description PF3 is designated as LWR output pin PF3 is designated as I/O port, and does not function as LWR output pin (Initial value) Rev.6.00 Sep. 27, 2007 Page 81 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Bit 1 IRQPAS 0 1 Description PA4 to PA7 are used for IRQ4 to IRQ7 input P50 to P53 are used for IRQ4 to IRQ7 input (Initial value) Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 3.2.3 Bit System Control Register 2 (SYSCR2) (F-ZTAT Version Only) : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — (R/W)* Initial value : R/W : Note: * R/W in the H8S/2329B F-ZTAT. SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified. Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Rev.6.00 Sep. 27, 2007 Page 82 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 and 1—Reserved: These bits are always read as 0. Only 0 should be written to these bits. Bit 0—Reserved: In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, this bit is always read as 0 and should only be written with 0. In the H8S/2329B F-ZTAT, this bit is reserved and should only be written with 0. 3.3 3.3.1 Operating Mode Descriptions Mode 1 The H8S/2329 does not support mode 1. Do not select the mode 1 setting. 3.3.2 Mode 2 (H8S/2329B F-ZTAT Only) This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced on-chip ROM enabled expansion mode, except when erasing and reprogramming flash memory. 3.3.3 Mode 3 (H8S/2329B F-ZTAT Only) This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced single-chip ROM mode, except when erasing and reprogramming flash memory. 3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. Rev.6.00 Sep. 27, 2007 Page 83 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes 3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6 (Expanded Mode with On-Chip ROM Enabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B, and C function as input ports immediately after a reset. These pins can be set to output addresses by setting the corresponding bits to 1 in pin function control register 1 (PFCR1) in the case of ports A and B, or in the data direction register (DDR) for port C. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.7 Mode 7 (Single-Chip Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input/output ports. 3.3.8 Modes 8 and 9 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) Modes 8 and 9 are not supported and must not be set. 3.3.9 Mode 10 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled. Rev.6.00 Sep. 27, 2007 Page 84 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes 3.3.10 Mode 11 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode. 3.3.11 Modes 12 and 13 Modes 12 and 13 are not supported and must not be set. 3.3.12 Mode 14 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory user program mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled. 3.3.13 Mode 15 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory user program mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode. 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Rev.6.00 Sep. 27, 2007 Page 85 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Table 3.4 Port Port A Pin Functions in Each Mode Mode 4 2* Mode 4 3* P Mode 4 P* /A A P* /A 1 P* /A D 1 P* /D 1 1 Mode 5 P* /A A A A D 1 P* /D P/C* C 1 1 Mode 2 6* P* /A 1 Mode 2 7* P Mode 3 10 * P* /A 1 Mode 3 11 * P Mode 3 14 * P* /A 1 Mode 3 15 * P PA7 to P* /A PA5 PA4 to PA0 1 Port B Port C Port D Port E Port F PF7 PF6 P P P P P* /C P 1 A A D 1 P/D* P* /A 1 P* /A D 1 P* /D P/C* C 1 1 1 P P P P P* /C P 1 P* /A 1 P* /A D 1 P* /D P/C* C 1 1 P P P P P* /C P 1 P* /A 1 P* /A D 1 P* /D P/C* C 1 1 P P P P P* /C P 1 P/C* 1 P/C* C 1 PF5 to C PF4 P/C* 1 PF2 to P* /C PF0 PF3 1 P/C* 1 P* /C 1 P/C* 1 P* /C P/C* 1 P* /C 1 P/C* 1 P* /C 1 P/C* 1 P* /C 1 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. After reset. 2. Setting is prohibited in the ROMless versions. 3. Setting prohibited except in case of the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT. 4. Valid only in the H8S/2329B F-ZTAT. 3.5 Memory Map in Each Operating Mode Figures 3.1 to 3.9 show memory maps for each of the operating modes. The address space is 16 Mbytes. The address space is divided into eight areas. Rev.6.00 Sep. 27, 2007 Page 86 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM Mode 3 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *5 H'060000 H'080000 H'FF7400 H'FF7C00 Reseved area*4 External address space Reseved area*4 On-chip RAM*3 H'060000 H'07FFFF Reseved area*4 H'FF7400 H'FF7C00 Reseved area*4 On-chip RAM H'FFFBFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Notes: 1. 2. 3. 4. 5. External address space Internal I/O registers External address space Internal I/O registers H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Access to the reserved areas H'060000 to H'07FFFF and H'FF7400 to H'FF7BFF is prohibited. Do not access a reserved area. Figure 3.1 (a) H8S/2329B Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 87 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'010000 External address space On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *5 H'060000 H'080000 H'FF7400 H'FF7C00 Reseved area*4 External address space Reseved area*4 On-chip RAM*3 H'060000 H'080000 H'FF7400 H'FF7C00 Reseved area*4 External address space Reseved area*4 On-chip RAM*3 H'060000 H'07FFFF Reseved area*4 H'FF7400 H'FF7C00 Reseved area*4 On-chip RAM H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. 5. H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Access to the reserved areas H'060000 to H'07FFFF and H'FF7400 to H'FF7BFF is prohibited. Do not access a reserved area. Figure 3.1 (b) H8S/2329B Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 88 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.2 (a) H8S/2328 Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 89 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space H'FFDC00 On-chip RAM*3 H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.2 (b) H8S/2328 Memory Map in Each Operating Mode (F-ZTAT Only) Rev.6.00 Sep. 27, 2007 Page 90 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space H'FFDC00 On-chip RAM*3 H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.2 (c) H8S/2328 Memory Map in Each Operating Mode (F-ZTAT Only) Rev.6.00 Sep. 27, 2007 Page 91 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 External address space/on-chip ROM*1 H'020000 External address space/reserved area*2 *5 H'010000 Reserved area*5/ on-chip ROM*3 H'020000 Reserved area*5 H'03FFFF H'040000 H'FFDC00 On-chip RAM*4 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*4 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. 5. External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.3 H8S/2327 Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 92 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 H'FFDC00 On-chip RAM*3 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.4 (a) H8S/2326 F-ZTAT Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 93 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space H'FFDC00 On-chip RAM*3 H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.4 (b) H8S/2326 F-ZTAT Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 94 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. 2. 3. 4. External address space H'FFDC00 On-chip RAM*3 H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access a reserved area. Figure 3.4 (c) H8S/2326 F-ZTAT Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 95 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7C00 On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2324S Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 96 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'008000 Reserved area*3 H'008000 Reserved area*3 External address space H'010000 H'010000 External address space/reserved area*1 *3 Reserved area*3 H'03FFFF H'040000 H'FFDC00 On-chip RAM*2 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*2 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE50 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 3. Do not access a reserved area. Figure 3.6 H8S/2323 Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 97 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.7 H8S/2322R Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 98 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 H'FFEC00 Reserved area On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.8 H8S/2320 and H8S/2321 Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 99 of 1268 REJ09B0220-0600 Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 100 of 1268 REJ09B0220-0600 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Trace* 1 Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been 2 issued* 3 Interrupt Low Trap instruction (TRAPA) * Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. Rev.6.00 Sep. 27, 2007 Page 101 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset • Trace Exception sources External interrupts: NMI, IRQ7 to IRQ0 • Interrupts Internal interrupts: interrupts from on-chip supporting modules • Trap instruction Figure 4.1 Exception Sources In modes 6 and 7, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 256-kbyte (128 kbytes/384 kbytes/512 kbytes)* area comprising addresses H'000000 to H'03FFFF (to H'01FFFF/H'05FFFF/H'07FFFF) to be used. For details, see section 6.2.5, Bus Control Register L (BCRL). Note: * The amount of on-chip ROM differs depending on the product. Rev.6.00 Sep. 27, 2007 Page 102 of 1268 REJ09B0220-0600 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Reset Reserved Reserved for system use Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 ⎜ H'016C to H'016F Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) 5 6 7 8 9 10 11 Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24 ⎜ 91 2 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector Table. Rev.6.00 Sep. 27, 2007 Page 103 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. A reset can also be caused by watchdog timer overflow. For details see section 13, Watchdog Timer. 4.2.2 Reset Sequence The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.2 shows an example of the reset sequence. Rev.6.00 Sep. 27, 2007 Page 104 of 1268 REJ09B0220-0600 Section 4 Exception Handling Vector fetch Internal Prefetch of first processing program instruction * * φ RES Address bus RD HWR, LWR D15 to D0 * (1) (3) (5) High (2) (4) (6) (1), (3) (2), (4) (5) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception vector address) Start address ((5) = (2), (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.2 Reset Sequence (Mode 4) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC* and DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 105 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR I 1 UI — I2 to I0 — EXR T 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Trace exception handling cannot be used. Rev.6.00 Sep. 27, 2007 Page 106 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer*, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC)*, and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. Note: * The refresh timer and DMAC are not supported in the H8S/2321. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) Internal interrupts WDT*1 (1) Refresh timer*2 *3 (1) TPU (26) 8-bit timer (6) SCI (12) DTC (1) DMAC (4)*3 A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match. 3. The refresh timer and DMAC are not supported in the H8S/2321. Figure 4.3 Interrupt Sources and Number of Interrupts Rev.6.00 Sep. 27, 2007 Page 107 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR I 1 1 UI — — I2 to I0 — — EXR T — 0 Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. 4.6 Stack Status after Exception Handling Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.4 Stack Status after Exception Handling (Advanced Modes) Rev.6.00 Sep. 27, 2007 Page 108 of 1268 REJ09B0220-0600 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.5 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD SP TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Data saved above SP Contents of CCR lost Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.5 Operation when SP Value is Odd Rev.6.00 Sep. 27, 2007 Page 109 of 1268 REJ09B0220-0600 Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 110 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts and 52 internal interrupts. • Two interrupt control modes ⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR) • Priorities settable with IPRs ⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI ⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times • Independent vector addresses ⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine • Nine external interrupt pins ⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI ⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0 • DTC and DMAC* control ⎯ DTC and DMAC* activation is controlled by means of interrupts Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 111 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to TEI CCR EXR IPR Interrupt controller Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev.6.00 Sep. 27, 2007 Page 112 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ7 to IRQ0 Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W) * R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE 1 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 113 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 R/W 1 0 R/W 0 RAME 1 R/W LWROD IRQPAS Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating Modes. SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Bit 1—IRQ Input Pin Select (IRQPAS): Selects switching of the pins that can be used for input of IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Rev.6.00 Sep. 27, 2007 Page 114 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : R/W : The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer 1 —* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 2 DMAC* SCI channel 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 Notes: 1. Reserved bits. 2. The refresh timer and DMAC are not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 115 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) Rev.6.00 Sep. 27, 2007 Page 116 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W ISCRL Bit : : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : ISCR (composed of ISCRH and ISCRL) is a 16-bit readable/writable register that selects rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. ISCR is initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0—IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input Rev.6.00 Sep. 27, 2007 Page 117 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] • • • • 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) [Setting conditions] • • • • Rev.6.00 Sep. 27, 2007 Page 118 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.) NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. Rev.6.00 Sep. 27, 2007 Page 119 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input IRQn interrupt S R Q request Clear signal Note: n = 7 to 0 Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR bit to 0 and use the pin as an I/O pin for another function. The pins that can be used for IRQ4 to IRQ7 interrupt input can be switched by means of the IRQPAS bit in SYSCR. Rev.6.00 Sep. 27, 2007 Page 120 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DMAC* and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC* or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. Note: * The DMAC is not supported in the H8S/2321. 5.3.3 Interrupt Exception Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Interrupt sources can also be used to activate the DTC and DMAC*. Priorities among modules can be set by means of IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 121 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Vector Number 0 1 2 3 4 5 6 External pin 7 8 9 10 11 Vector 1 Address* IPR H'0000 H'0004 H'0008 H'000C H'0010 H'0014 H'0018 H'001C H'0020 H'0024 H'0028 H'002C H'0030 H'0034 H'0038 H'003C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC6 to IPRC4 Low — — — — — — — — — DMAC* DTC Activa- ActivaPriority tion tion High — — 2 Interrupt Source Power-on reset Reserved Reserved for system use Trace Reserved for system use NMI Trap instruction (4 sources) Reserved for system use 12 13 14 15 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 External pin 16 17 18 19 20 21 22 23 Rev.6.00 Sep. 27, 2007 Page 122 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Origin of Interrupt Source DTC DMAC* DTC Activa- ActivaPriority tion tion — 2 Interrupt Source SWDTEND (softwareactivated data transfer end) WOVI (interval timer) CMI (compare match)* Reserved ADI (A/D conversion end) Reserved 3 Vector Vector 1 Number Address* IPR 24 H'0060 IPRC2 to High IPRC0 IPRD6 to IPRD4 IPRD2 to IPRD0 IPRE6 to IPRE4 IPRE2 to IPRE0 — — — — Watchdog 25 timer Refresh controller — A/D — 26 27 28 29 30 31 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 — — — — TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved TPU channel 0 32 IPRF6 to IPRF4 — 33 H'0084 34 H'0088 — 35 H'008C — 36 — 37 38 39 H'0090 H'0094 H'0098 H'009C Low — — — — Rev.6.00 Sep. 27, 2007 Page 123 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Origin of Interrupt Source TPU channel 1 DMAC* DTC Activa- ActivaPriority tion tion High 2 Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved Vector Vector 1 Number Address* IPR 40 H'00A0 IPRF2 to IPRF0 41 H'00A4 — 42 43 TPU channel 2 44 H'00A8 H'00AC H'00B0 IPRG6 to IPRG4 — — — — 45 H'00B4 — 46 47 TPU channel 3 48 H'00B8 H'00BC H'00C0 IPRG2 to IPRG0 — — — — 49 H'00C4 — 50 H'00C8 — 51 H'00CC — 52 — 53 54 55 H'00D0 H'00D4 H'00D8 H'00DC Low — — — — Rev.6.00 Sep. 27, 2007 Page 124 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Origin of Interrupt Source TPU channel 4 DMAC* DTC Activa- ActivaPriority tion tion 2 Interrupt Source TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) CMIA0 (compare match A) CMIB0 (compare match B) OVI0 (overflow 0) Reserved CMIA1 (compare match A) CMIB1 (compare match B) OVI1 (overflow 1) Reserved Vector Vector 1 Number Address* IPR 56 H'00E0 IPRH6 to High IPRH4 — 57 H'00E4 58 59 TPU channel 5 60 H'00E8 H'00EC H'00F0 IPRH2 to IPRH0 — — — — 61 H'00F4 — 62 63 8-bit timer channel 0 64 65 66 — 8-bit timer channel 1 67 68 69 70 — 71 H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C Low IPRI2 to IPRI0 IPRI6 to IPRI4 — — — — — — — — — — — — — — — — Rev.6.00 Sep. 27, 2007 Page 125 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Origin of Interrupt Source DMAC DMAC* DTC Activa- ActivaPriority tion tion High — 2 Interrupt Source DEND0A (channel 0/channel 0A transfer 3 end)* DEND0B (channel 0B 3 transfer end) * DEND1A (channel 1/channel 1A transfer 3 end) * DEND1B (channel 1B 3 transfer end) * Reserved Vector Vector 1 Number Address* IPR 72 H'0120 IPRJ6 to IPRJ4 73 74 H'0124 H'0128 — — 75 — 76 77 78 79 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C Low — IPRK2 to IPRK0 — — IPRK6 to IPRK4 — — IPRJ2 to IPRJ0 — — — — ERI0 (receive error 0) RXI0 (reception data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (reception data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) ERI2 (receive error 2) RXI2 (reception data full 2) TXI2 (transmit data empty 2) TEI2 (transmit end 2) SCI channel 0 80 81 82 83 — — — SCI channel 1 84 85 86 87 — — — — — SCI channel 2 88 89 90 91 Notes: 1. Lower 16 bits of the start address. 2. The DMAC is not supported in the H8S/2321. 3. Reserved in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 126 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I bit in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes SYSCR INTM1 INTM0 0 0 1 1 0 Priority Setting Registers — — IPR Interrupt Mask Bits I — I2 to I0 Interrupt Control Mode 0 — 2 Description Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited — 1 — — Rev.6.00 Sep. 27, 2007 Page 127 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 2 I 0 1 * Selected Interrupts All interrupts NMI interrupts All interrupts *: Don't care Rev.6.00 Sep. 27, 2007 Page 128 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0) Interrupt Control Mode 0 2 Default Priority Determination: When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Interrupt Control Mode 0 2 Operations and Control Signal Functions in Each Interrupt Control Mode Setting INTM1 INTM0 0 1 0 0 X Interrupt Acceptance Control I IM 1 —* X 8-Level Control I2 to I0 — IM IPR 2 —* PR Default Priority Determination T (Trace) — T Legend: : Interrupt operation control performed X: No operation (All interrupts enabled) IM: Used as interrupt mask bit PR: Sets priority —: Not used Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. Rev.6.00 Sep. 27, 2007 Page 129 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.6.00 Sep. 27, 2007 Page 130 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Program execution state Interrupt generated? Yes Yes No NMI? No No I = 0? Yes Hold pending No IRQ0? Yes No IRQ1? Yes TEI2? Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Sep. 27, 2007 Page 131 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.6.00 Sep. 27, 2007 Page 132 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Program execution state Interrupt generated? Yes Yes NMI? No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Sep. 27, 2007 Page 133 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.6.00 Sep. 27, 2007 Page 134 of 1268 REJ09B0220-0600 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt level determination Wait for end of instruction Interrupt handling routine instruction prefetch φ Interrupt request signal Internal address bus (1) (7) (9) (3) (5) (11) (13) Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) (14) Figure 5.7 Interrupt Exception Handling Internal data bus Rev.6.00 Sep. 27, 2007 Page 135 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2), (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6), (8) Saved PC and saved CCR (9), (11) Vector address (10), (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10), (12)) (14) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Advanced Mode No. 1 2 3 4 5 6 Item Interrupt priority determination *1 Number of wait states until executing 2 instruction ends* PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 Internal processing* INTM1 = 0 3 1 to (19 + 2·SI) 2·SK 2·SI 2·SI 2 12 to 32 INTM1 = 1 3 1 to (19 + 2·SI) 3·SK 2·SI 2·SI 2 13 to 33 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5.10 Number of States in Interrupt Handling Routine Execution Object of Access External Device 8-Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m Legend: m: Number of wait states in an external device access. Rev.6.00 Sep. 27, 2007 Page 136 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5.8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0. TIER0 write cycle by CPU TGI0A exception handling φ Internal address bus TIER0 address Internal write signal TGIEA TGFA TGI0A interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Rev.6.00 Sep. 27, 2007 Page 137 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 Rev.6.00 Sep. 27, 2007 Page 138 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.6 5.6.1 DTC and DMAC Activation by Interrupt Overview The DTC and DMAC* can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Activation request to DMAC* 4. Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC*, see section 8, Data Transfer Controller, and section 7, DMA Controller. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 139 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC, DMAC*, and interrupt controller. Note: * The DMAC is not supported in the H8S/2321. DMAC* Disable signal Clear signal Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Note: * The DMAC is not supported in the H8S/2321. Figure 5.9 Interrupt Control for DTC and DMAC* Rev.6.00 Sep. 27, 2007 Page 140 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC* control. Selection of Interrupt Source: With the DMAC*, the activation source is input directly to each channel. The activation source for each DMAC* channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC* can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC* activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC*, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC*, the activation source is input directly to each channel. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DMAC* activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC*, the DTCE bit of DTCERA to DTCERF in the DTC, and the DISEL bit of MRB in the DTC. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 141 of 1268 REJ09B0220-0600 Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTCE 0 1 1 * DTC DISEL * 0 1 * X Interrupt Source Selection/Clearing Control DMAC* 1 DTC X CPU X X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X: The relevant interrupt cannot be used. *: Don't care Note: 1. The DMAC is not supported in the H8S/2321. Usage Note: SCI and A/D converter interrupt sources are cleared when the DMAC* or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 142 of 1268 REJ09B0220-0600 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC). Note: * The DMAC is not supported in the H8S/2321. 6.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units ⎯ In advanced mode, manages the external space as 8 areas of 2 Mbytes ⎯ Bus specifications can be set independently for each area ⎯ DRAM*/burst ROM interfaces can be set • Basic bus interface ⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7 ⎯ 8-bit access or 16-bit access can be selected for each area ⎯ 2-state access or 3-state access can be selected for each area ⎯ Program wait states can be inserted for each area • DRAM interface* ⎯ DRAM interface can be set for areas 2 to 5 (in advanced mode) ⎯ Row address/column address multiplexed output (8/9/10 bits) ⎯ 2-CAS access method ⎯ Burst operation (fast page mode) ⎯ TP cycle insertion to secure RAS precharging time ⎯ Choice of CAS-before-RAS refreshing or self-refreshing • Burst ROM interface ⎯ Burst ROM interface can be set for area 0 ⎯ Choice of 1- or 2-state burst access Rev.6.00 Sep. 27, 2007 Page 143 of 1268 REJ09B0220-0600 Section 6 Bus Controller • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle • Write buffer functions ⎯ External write cycle and internal access can be executed in parallel ⎯ DMAC* single address mode and internal access can be executed in parallel • Bus arbitration function ⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC • Other features ⎯ Refresh counter (refresh timer)* can be used as an interval timer ⎯ External bus release function Note: * The DRAM interface, DMAC, and refresh counter are not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 144 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal control signals Bus mode signal WAIT WCRH WCRL External DRAM signals* DRAM controller* MCR DRAMCR RTCNT RTCOR CPU bus request signal DTC bus request signal DMAC bus request signal* CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal* Bus arbiter Note: * Not supported in the H8S/2321. Figure 6.1 Block Diagram of Bus Controller Rev.6.00 Sep. 27, 2007 Page 145 of 1268 REJ09B0220-0600 Internal data bus Wait controller Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Name Address strobe Read High write/write enable Bus Controller Pins Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal*. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space*. Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space*. Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space*. Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space*. Low write LWR Output Chip select 0 Chip select 1 Chip select 2/row address strobe 2 CS0 CS1 CS2 Output Output Output Chip select 3/row address strobe 3 CS3 Output Chip select 4/row address strobe 4 CS4 Output Chip select 5/row address strobe 5 CS5 Output Rev.6.00 Sep. 27, 2007 Page 146 of 1268 REJ09B0220-0600 Section 6 Bus Controller Name Chip select 6 Chip select 7 Upper column address strobe Lower column strobe Wait Bus request Bus request acknowledge Bus request output Symbol CS6 CS7 CAS* LCAS* WAIT BREQ BACK BREQO I/O Output Output Output Output Input Input Output Output Function Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. 2-CAS DRAM upper column address strobe signal. DRAM lower column address strobe signal. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. Note: * The DRAM interface and the CAS and LCAS pin functions are not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 147 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Memory control register DRAM control register Refresh timer counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL 3 MCR* 3 DRAMCR* 3 RTCNT* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF 2 Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 1 RTCOR* 3 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. 3. In the H8S/2321 this register is reserved and must not be accessed. Rev.6.00 Sep. 27, 2007 Page 148 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 5 ABW5 1 R/W 4 ABW4 1 R/W 3 ABW3 1 R/W 2 ABW2 1 R/W 1 ABW1 1 R/W 0 ABW0 1 R/W Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7,* and to H'00 in mode 4. It is not initialized in software standby mode. Note: * Modes 6 and 7 are not provided in the ROMless version. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev.6.00 Sep. 27, 2007 Page 149 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev.6.00 Sep. 27, 2007 Page 150 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev.6.00 Sep. 27, 2007 Page 151 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev.6.00 Sep. 27, 2007 Page 152 of 1268 REJ09B0220-0600 Section 6 Bus Controller WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev.6.00 Sep. 27, 2007 Page 153 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2* RMTS1 * RMTS0 * Initial value : R/W : Note: * This bit is reserved in the H8S/2321. BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev.6.00 Sep. 27, 2007 Page 154 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface area. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface area Area 0 is burst ROM interface area (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Rev.6.00 Sep. 27, 2007 Page 155 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as a DRAM interface area. In the H8S/2321 these bits are reserved and should only be written with 0. Bit 2 RMTS2 0 Bit 1 RMTS1 0 1 1 — Bit 0 RMTS0 0 1 0 1 — Description Area 5 Normal space Normal space Normal space DRAM space — DRAM space DRAM space Area 4 Area 3 Area 2 The LCAS pin is used for the LCAS signal on the 2-CAS DRAM interface. If it is wished to use BREQO output and WAIT input when using the LCAS signal, it is possible to switch to the P53 pin by means of the BREQOPS bit in PFCR2. For details, see section 9.6, Port 5 and section 9.13, Port F. Note: This note applies to the H8S/2323 only. If all areas selected as DRAM space are 8-bit space, the PF2 pin can be used as an I/O port, or as the BREQ0 or WAIT pin. However, if PF2 is used as the WAIT pin on the H8S/2323 only, normal space other than DRAM space should be designated as 16-bit bus space. The RAS down mode cannot be used in this case. Sample settings are shown below. RMTS2 0 RMTS1 0 RMTS0 0 1 1 0 1 Area 5 Normal space Normal space (16-bit bus) Normal space (16-bit bus) DRAM space (8-bit bus) DRAM space (8-bit bus) DRAM space (8-bit bus) Area 4 Area 3 Area 2 Rev.6.00 Sep. 27, 2007 Page 156 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 — 1 R/W 3 DDS* 1 R/W 2 — 1 R/W 1 WDBE* 0 R/W 0 WAITE 0 R/W Initial value : R/W : Note: * This bit is reserved in the H8S/2321. BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O ports (Initial value) External bus release is enabled Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO pin can be used as I/O port BREQO output enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 157 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*2 are to be internal addresses or external addresses. Description Bit 5 0 3 H8S/2329B, H8S/2328* , H8S/2326 H8S/2327 H8S/2323 1 1 Addresses H'010000 to Reserved area* H'01FFFF are on-chip ROM or address H'020000 to H'03FFFF are reserved 1 area* 2 Addresses H'010000 to H'03FFFF* are external addresses in external expanded mode 1 or reserved area* in single-chip mode (Initial value) On-chip ROM Notes: 1. Do not access a reserved area. 2. Addresses H'010000 to H'05FFFF in the H8S/2329B. Addresses H'010000 to H'07FFFF in the H8S/2326. 3. H8S/2328B in F-ZTAT version. Bit 4—Reserved: Only 1 should be written to this bit. Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. In the H8S/2321 this bit is reserved and should only be written with 1. Bit 3 DDS 0 Description When DMAC single address transfer is performed in DRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle 1 Burst access is possible when DMAC single address transfer is performed in DRAM space DACK signal goes low from Tc1 or T2 cycle (Initial value) Bit 2—Reserved: Only 1 should be written to this bit. Rev.6.00 Sep. 27, 2007 Page 158 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. In the H8S/2321 this bit is reserved and should only be written with 0. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port Wait input by WAIT pin enabled (Initial value) 6.2.6 Bit Memory Control Register (MCR) : 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 — 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Initial value : R/W : MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface areas. MCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed. Rev.6.00 Sep. 27, 2007 Page 159 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC 0 1 Description 1-state precharge cycle is inserted 2-state precharge cycle is inserted (Initial value) Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode. Bit 6 BE 0 1 Description Burst disabled (always full access) For DRAM space access, access in fast page mode (Initial value) Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). Bit 5 RCDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value) Bit 4—Reserved: Only 0 should be written to this bit. Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison. Rev.6.00 Sep. 27, 2007 Page 160 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 3 MXC1 0 Bit 2 MXC0 0 Description 8-bit shift • • (Initial value) When 8-bit access space is designated: Row address A23 to A8 used for comparison When 16-bit access space is designated: Row address A23 to A9 used for comparison When 8-bit access space is designated: Row address A23 to A9 used for comparison When 16-bit access space is designated: Row address A23 to A10 used for comparison When 8-bit access space is designated: Row address A23 to A10 used for comparison When 16-bit access space is designated: Row address A23 to A11 used for comparison 1 9-bit shift • • 1 0 10-bit shift • • 1 — Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled. Bit 1 RLW1 0 1 Bit 0 RLW0 0 1 0 1 Description No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted (Initial value) Rev.6.00 Sep. 27, 2007 Page 161 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2.7 Bit DRAM Control Register (DRAMCR) : 7 RFSHE 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed. Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Bit 7 RFSHE 0 1 Description Refresh control is not performed Refresh control is performed (Initial value) Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-beforeRAS refreshing. Bit 6 RCW 0 1 Description Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle (Initial value) Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), selects whether or not self-refresh control is performed in software standby mode. Bit 5 RMODE 0 1 Description Self-refreshing is not performed in software standby mode Self-refreshing is performed in software standby mode (Initial value) Rev.6.00 Sep. 27, 2007 Page 162 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 CMF 0 Description [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) [Setting condition] Set when RTCNT = RTCOR 1 Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE 0 1 Description Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled (Initial value) Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (φ). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Description Count operation disabled Count uses φ/2 Count uses φ/8 Count uses φ/32 Count uses φ/128 Count uses φ/512 Count uses φ/2048 Count uses φ/4096 (Initial value) Rev.6.00 Sep. 27, 2007 Page 163 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.2.8 Bit Refresh Timer Counter (RTCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed. 6.2.9 Bit Refresh Time Constant Register (RTCOR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: In the H8S/2321 this register is reserved and must not be accessed. Rev.6.00 Sep. 27, 2007 Page 164 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.3 6.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Advanced mode Figure 6.2 Overview of Area Partitioning Rev.6.00 Sep. 27, 2007 Page 165 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM interface* and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. Note: * The DRAM interface is not supported in the H8S/2321. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area. Rev.6.00 Sep. 27, 2007 Page 166 of 1268 REJ09B0220-0600 Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 8 2 3 0 0 1 2 3 ABWCR ABWn 0 ASTCR ASTn 0 1 Wn1 — 0 1 Wn0 — 0 1 0 1 — 0 1 0 1 1 0 1 — 0 1 6.3.3 Memory Interfaces The chip’s memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface* that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface* is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. Note: * The DRAM interface is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 167 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, Basic Bus Interface, 6.5, DRAM Interface (Not supported in the H8S/2321), and 6.7, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM*1, and in ROM-disabled expansion mode, all of area 0 is external space. In the ROM-enabled expansion mode, the space excluding on-chip ROM*1 is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 and 6: In external expansion mode, all of area 1 and area 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. Areas 2 to 5: In external expansion mode, all of area 2 to area 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface*2 can be selected for areas 2 to 5. With the DRAM interface*2, signals CS2 to CS5 are used as RAS signals. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. Notes: 1. Only applies to versions with ROM. 2. The DRAM interface is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 168 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.3.5 Chip Select Signals The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or the CS25 enable bit (CS25E). In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a poweron reset, so the corresponding DDR bits, and CS167E or CS25E, should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space*, outputs CS2 to CS5 are used as RAS signals. Note: * The DRAM interface is not supported in the H8S/2321. Bus cycle T1 φ T2 T3 Address bus Area n external address CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 7) Rev.6.00 Sep. 27, 2007 Page 169 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. (See table 6.3.) 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev.6.00 Sep. 27, 2007 Page 170 of 1268 REJ09B0220-0600 Section 6 Bus Controller 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev.6.00 Sep. 27, 2007 Page 171 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Write Word Read Write Address — — Even Odd Even Odd — — HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower Data Bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Notes: Hi-Z: High impedance Invalid: Input state; input value is ignored. Rev.6.00 Sep. 27, 2007 Page 172 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6.6 Bus Timing for 8-Bit 2-State Access Space Rev.6.00 Sep. 27, 2007 Page 173 of 1268 REJ09B0220-0600 Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space Rev.6.00 Sep. 27, 2007 Page 174 of 1268 REJ09B0220-0600 Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev.6.00 Sep. 27, 2007 Page 175 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 7 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Sep. 27, 2007 Page 176 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Sep. 27, 2007 Page 177 of 1268 REJ09B0220-0600 Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev.6.00 Sep. 27, 2007 Page 178 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 7 Valid Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Sep. 27, 2007 Page 179 of 1268 REJ09B0220-0600 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.6.00 Sep. 27, 2007 Page 180 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the chip can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion: Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. The WAITPS bit can be used to change the WAIT input pin from PF2 to P53. To make this change, select the input pin with the WAITPS bit, then set the WAITE bit. Rev.6.00 Sep. 27, 2007 Page 181 of 1268 REJ09B0220-0600 Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. By program wait T1 φ T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. Rev.6.00 Sep. 27, 2007 Page 182 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5 6.5.1 DRAM Interface (Not supported in the H8S/2321) Overview When the chip is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6.5 RMTS2 0 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space DRAM space Area 4 Area 3 Area 2 DRAM space Rev.6.00 Sep. 27, 2007 Page 183 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6.6 Address Multiplexing Settings by Bits MXC1 and MXC0 Address Pins A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 ————————————— MCR Shift MXC1 MXC0 Size 0 Row address 1 0 1 0 1 Column — address — 8 bits 9 bits 10 bits — Setting prohibited — A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 6.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface. For details, see section 6.4.2, Data Size and Data Alignment. Rev.6.00 Sep. 27, 2007 Page 184 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 Pin HWR DRAM Interface Pins With DRAM Setting WE Name Write enable I/O Output Function When 2-CAS system is set, write enable for DRAM space access Lower column address strobe for 16-bit DRAM space access Row address strobe when area 2 is designated as DRAM space Row address strobe when area 3 is designated as DRAM space Row address strobe when area 4 is designated as DRAM space Row address strobe when area 5 is designated as DRAM space Upper column address strobe for DRAM space access Wait request signal Row address/column address multiplexed output Data input/output pins LCAS CS2 CS3 CS4 CS5 CAS WAIT A12 to A0 D15 to D0 LCAS RAS2 RAS3 RAS4 RAS5 UCAS WAIT A12 to A0 D15 to D0 Lower column address strobe Row address strobe 2 Row address strobe 3 Row address strobe 4 Row address strobe 5 Upper column address strobe Wait Address pins Data pins Output Output Output Output Output Output Input Output I/O Rev.6.00 Sep. 27, 2007 Page 185 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.6 Basic Timing Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and Tc2. Tp φ A23 to A0 Row Column Tr Tc1 Tc2 CSn (RAS) CAS, LCAS HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 Note: n = 2 to 5 Figure 6.15 Basic Access Timing Rev.6.00 Sep. 27, 2007 Page 186 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.7 Precharge State Control When DRAM is accessed, an RAS precharging time must be secured. With the chip, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the DRAM connected and the operating frequency of the chip. Figure 6.16 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for refresh cycles. Tp1 φ A23 to A0 Row Column Tp2 Tr Tc1 Tc2 CSn (RAS) CAS, LCAS HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 Note: n = 2 to 5 Figure 6.16 Timing with 2-State Precharge Cycle Rev.6.00 Sep. 27, 2007 Page 187 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6.17 shows an example of wait state insertion timing. Rev.6.00 Sep. 27, 2007 Page 188 of 1268 REJ09B0220-0600 Section 6 Bus Controller By program wait Tp φ Tr Tc1 Tw By WAIT pin Tw Tc2 WAIT* Address bus CSn (RAS) CAS Read Data bus Read data CAS Write Data bus Write data Notes: indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6.17 Example of Wait State Insertion Timing Rev.6.00 Sep. 27, 2007 Page 189 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. Figure 6.18 shows the control timing in the 2-CAS system, and figure 6.19 shows an example of 2-CAS type DRAM connection. Tp Tr Tc1 Tc2 φ A23 to A0 Row Column CSn (RAS) CAS Byte control LCAS HWR (WE) Note: n = 2 to 5 Figure 6.18 2-CAS System Control Timing (Upper Byte Write Access) Rev.6.00 Sep. 27, 2007 Page 190 of 1268 REJ09B0220-0600 Section 6 Bus Controller Chip (Address shift size set to 9 bits) CS (RAS) CAS LCAS HWR (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Row address input: A8 to A0 Column address input: A8 to A0 Figure 6.19 Example of 2-CAS DRAM Connection Rev.6.00 Sep. 27, 2007 Page 191 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR. Tp φ Tr Tc1 Tc2 Tc1 Tc2 A23 to A0 CSn (RAS) Row Column 1 Column 2 CAS, LCAS HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 Note: n = 2 to 5 Figure 6.20 Operation Timing in Fast Page Mode The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control. Rev.6.00 Sep. 27, 2007 Page 192 of 1268 REJ09B0220-0600 Section 6 Bus Controller RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. • RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6.21 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode. DRAM access Tp φ Tr Tc1 Tc2 External space access T1 T2 DRAM access Tc1 Tc2 A23 to A0 CSn (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6.21 Example of Operation Timing in RAS Down Mode Rev.6.00 Sep. 27, 2007 Page 193 of 1268 REJ09B0220-0600 Section 6 Bus Controller • RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level. DRAM access Tp φ DRAM access Tc2 Tc1 Tc2 Tr Tc1 External space access T1 T2 A23 to A0 CSn (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6.22 Example of Operation Timing in RAS Up Mode Rev.6.00 Sep. 27, 2007 Page 194 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.5.11 Refresh Control The chip is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6.23, compare match timing in figure 6.24, and CBR refresh timing in figure 6.25. Access to other normal space can be performed during the CBR refresh interval. RTCNT RTCOR H'00 Refresh request Figure 6.23 RTCNT Operation Rev.6.00 Sep. 27, 2007 Page 195 of 1268 REJ09B0220-0600 Section 6 Bus Controller φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.24 Compare Match Timing TRp φ TRr TRc1 TRc2 CS (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6.25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6.26 shows the timing when the RCW bit is set to 1. Rev.6.00 Sep. 27, 2007 Page 196 of 1268 REJ09B0220-0600 Section 6 Bus Controller TRp TRr TRc1 TRw TRc2 φ CSn (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6.26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.27. When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-refresh mode is entered. Software standby TRp TRcr TRc3 φ CSn (RAS) CAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6.27 Self-Refresh Timing Rev.6.00 Sep. 27, 2007 Page 197 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.6 DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, this bit selects whether or not burst access is to be performed. 6.6.1 When DDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the TC1 state in the case of the DRAM interface. Figure 6.28 shows the DACK output timing for the DRAM interface when DDS = 1. Tp φ A23 to A0 CSn (RAS) CAS (UCAS) LCAS (LCAS) HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 DACK Note: n = 2 to 5 Row Column Tr Tc1 Tc2 Figure 6.28 DACK Output Timing when DDS = 1 (Example of DRAM Access) Rev.6.00 Sep. 27, 2007 Page 198 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0. Tp φ A23 to A0 CSn (RAS) CAS (UCAS) LCAS (LCAS) HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 DACK Row Column Tr Tc1 Tc2 Note: n = 2 to 5 Figure 6.29 DACK Output Timing when DDS = 0 (Example of DRAM Access) Rev.6.00 Sep. 27, 2007 Page 199 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.7 6.7.1 Burst ROM Interface Overview With the chip, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.7.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.30 (a) and (b). The timing shown in figure 6.30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.30 (b) is for the case where both these bits are cleared to 0. Rev.6.00 Sep. 27, 2007 Page 200 of 1268 REJ09B0220-0600 Section 6 Bus Controller Full access T1 φ T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.6.00 Sep. 27, 2007 Page 201 of 1268 REJ09B0220-0600 Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 φ Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev.6.00 Sep. 27, 2007 Page 202 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.8 6.8.1 Idle Cycle Operation When the chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and highspeed memory, I/O interfaces, and so on. Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6.31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (ICIS1 = 1 (initial value)) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.31 Example of Idle Cycle Operation (1) Rev.6.00 Sep. 27, 2007 Page 203 of 1268 REJ09B0220-0600 Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (ICIS0 = 1 (initial value)) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS0 = 0) Figure 6.32 Example of Idle Cycle Operation (2) Rev.6.00 Sep. 27, 2007 Page 204 of 1268 REJ09B0220-0600 Section 6 Bus Controller Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.33. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A φ Address bus CS (area A) CS (area B) RD T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (ICIS1 = 1 (initial value)) Figure 6.33 Relationship between Chip Select (CS) and Read (RD) Rev.6.00 Sep. 27, 2007 Page 205 of 1268 REJ09B0220-0600 Section 6 Bus Controller Usage Notes: When DRAM space* is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access*, only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6.34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6.35 (a) and (b). Note: * The DRAM interface is not supported in the H8S/2321. External read T1 φ Address bus RD Data bus T2 T3 Tp DRAM space read Tr Tc1 Tc2 Figure 6.34 Example of DRAM Access after External Read Rev.6.00 Sep. 27, 2007 Page 206 of 1268 REJ09B0220-0600 Section 6 Bus Controller DRAM space read Tp EXTAL Address RD RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space read Tc1 Tc1 Tc2 Idle cycle Figure 6.35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) DRAM space read Tp EXTAL Address RD HWR RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space write Tc1 Tc1 Tc2 Idle cycle Figure 6.35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) Rev.6.00 Sep. 27, 2007 Page 207 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.8.2 Pin States in Idle Cycle Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pins A23 to A0 D15 to D0 2 CSn* CAS* AS RD HWR LWR 34 DACKm* * 4 Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance 1 High* High High High High High High Remains low in DRAM space RAS down mode or a refresh cycle. n = 0 to 7 m = 0 and 1 The CAS and DACKm pin functions are not supported in the H8S/2321. Notes: 1. 2. 3. 4. Rev.6.00 Sep. 27, 2007 Page 208 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.9 Write Data Buffer Function The chip has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6.36 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer* continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. Note: * The DMAC is not supported in the H8S/2321. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address External space write CSn HWR, LWR D15 to D0 Note: n = 0 to 7 Figure 6.36 Example of Timing when Write Data Buffer Function is Used Rev.6.00 Sep. 27, 2007 Page 209 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.10 6.10.1 Bus Release Overview The chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request* is generated, it can issue a bus request off-chip. The BREQOPS bit can be used to change the BREQO output pin from PF2 to P53. Note: * The DRAM interface is not supported in the H8S/2321. 6.10.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the chip. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request* is generated in the external bus released state, refresh control* is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request* is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev.6.00 Sep. 27, 2007 Page 210 of 1268 REJ09B0220-0600 Section 6 Bus Controller If a refresh request* and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh* > External bus release (Low) As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DRAM interface is not supported in the H8S/2321. 6.10.3 Pin States in External Bus Released State Table 6.9 shows the pin states in the external bus released state. Table 6.9 Pins A23 to A0 D15 to D0 1 CSn* 3 CAS* Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High AS RD HWR LWR 23 DACKm* * Notes: 1. n = 0 to 7 2. m = 0 or 1 3. The CAS and DACKm pin functions are not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 211 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.10.4 Transition Timing Figure 6.37 shows the timing for transition to the bus released state. CPU cycle CPU cycle T0 φ T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [5] [6] [1] Low level of BREQ pin is sampled at rise of T2 state. [2] BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. [3] BREQ pin state is still sampled in external bus released state. [4] High level of BREQ pin is sampled. [5] BACK pin is driven high, ending bus release cycle. [6] BREQO signal goes high 1.5 clocks after BACK signal goes high. Note: * Output only when BREQOE is set to 1. Figure 6.37 Bus Released State Transition Timing Rev.6.00 Sep. 27, 2007 Page 212 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.10.5 Usage Note Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a transition is made to sleep mode when either of these settings has been made. 6.11 6.11.1 Bus Arbitration Overview The chip has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC*, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. Note: * The DMAC is not supported in the H8S/2321. 6.11.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC* > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refreshing*, can be executed in parallel. In the event of simultaneous external bus release request, refresh request*, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh* > External bus release (Low) (High) External bus release > Internal bus master external access (Low) Rev.6.00 Sep. 27, 2007 Page 213 of 1268 REJ09B0220-0600 Section 6 Bus Controller As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DMAC and DRAM interface are not supported in the H8S/2321. 6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC*: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 214 of 1268 REJ09B0220-0600 Section 6 Bus Controller 6.11.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal and the DRAM interface* RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change from the low level to the high-impedance state. Note: * The DRAM interface is not supported in the H8S/2321. 6.12 Resets and the Bus Controller In a reset, the chip, including the bus controller, enters the reset state at that point, and any executing bus cycle is discontinued. Rev.6.00 Sep. 27, 2007 Page 215 of 1268 REJ09B0220-0600 Section 6 Bus Controller Rev.6.00 Sep. 27, 2007 Page 216 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1 Overview The chip has a built-in DMA controller* (DMAC) which can carry out data transfer on up to 4 channels. Note: * The DMAC is not supported in the H8S/2321. 7.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode ⎯ Maximum of 4 channels can be used ⎯ Choice of dual address mode or single address mode ⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits ⎯ In single address mode, transfer source or transfer destination address only is specified as 24 bits ⎯ In single address mode, transfer can be performed in one bus cycle ⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode ⎯ Maximum of 2 channels can be used ⎯ Transfer source and transfer destination address specified as 24 bits ⎯ Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ⎯ Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts ⎯ Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception data full interrupt ⎯ A/D converter conversion end interrupt Rev.6.00 Sep. 27, 2007 Page 217 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) ⎯ External request ⎯ Auto-request • Module stop mode can be set ⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Channel 0 Control logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Internal data bus Legend: DMAWER: DMA write enable register DMATCR: DMA terminal control register DMABCR: DMA band control register (for all channels) DMACR: DMA control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Figure 7.1 Block Diagram of DMAC Rev.6.00 Sep. 27, 2007 Page 218 of 1268 REJ09B0220-0600 Channel 1 Module data bus IOAR0A Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.3 Overview of Functions Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7.1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Dual address mode • Sequential mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/decremented by 1 or 2 ⎯ 1 to 65,536 transfers • Idle mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address fixed ⎯ 1 to 65,536 transfers • Repeat mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/ decremented by 1 or 2 ⎯ After specified number of transfers (1 to 256), initial state is restored and operation continues • • • • Single address mode 1-byte or 1-word transfer executed for one transfer request Transfer in 1 bus cycle using DACK pin in place of address specifying I/O Specifiable for sequential, idle, and repeat modes • External request 24/DACK DACK/24 • • • • Transfer Source • Source Destination 16/24 TPU channel 0 to 24/16 5 compare match/input capture A interrupt SCI transmitdata-empty interrupt SCI receivedata-full interrupt A/D converter conversion end interrupt External request Rev.6.00 Sep. 27, 2007 Page 219 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Table 7.1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode • Normal mode Auto-request ⎯ Transfer request retained internally ⎯ Transfers continue for the specified number of times (1 to 65,536) ⎯ Choice of burst or cycle steal transfer External request ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ 1 to 65,536 transfers • Block transfer mode ⎯ Specified block size transfer executed for one transfer request ⎯ 1 to 65,536 transfers ⎯ Either source or destination specifiable as block area ⎯ Block size: 1 to 256 bytes or words • • • • • TPU channel 0 to 24 5 compare match/input capture A interrupt SCI transmitdata-empty interrupt SCI receivedata-full interrupt External request A/D converter conversion end interrupt 24 • External request Transfer Source • Auto-request Source 24 Destination 24 Rev.6.00 Sep. 27, 2007 Page 220 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.4 Pin Configuration Table 7.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7.2 Channel 0 DMAC Pins Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function DMAC channel 0 external request DMAC channel 0 single address transfer acknowledge DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 single address transfer acknowledge DMAC channel 1 transfer end 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 Rev.6.00 Sep. 27, 2007 Page 221 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.5 Register Configuration Table 7.3 summarizes the DMAC registers. Table 7.3 DMAC Registers Abbreviation R/W MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR MSTPCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bus Width Address* 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 1 Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B 0, 1 DMA write enable register DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Module stop control register Note: * Lower 16 bits of the address. Undefined H'FEE0 Undefined H'FEE4 Undefined H'FEE6 Undefined H'FEE8 Undefined H'FEEC Undefined H'FEEE Undefined H'FEF0 Undefined H'FEF4 Undefined H'FEF6 Undefined H'FEF8 Undefined H'FEFC Undefined H'FEFE H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3FFF H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF3C DMA terminal control register DMATCR Rev.6.00 Sep. 27, 2007 Page 222 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.4 FAE0 0 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) Description Short address mode specified (channels A and B operate independently) Channel 0A MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. 1 Full address mode specified (channels A and B operate in combination) MAR0A MAR0B Channel 0 Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B Rev.6.00 Sep. 27, 2007 Page 223 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.1 Bit MAR R/W Bit MAR R/W Memory Address Registers (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. Rev.6.00 Sep. 27, 2007 Page 224 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.2 Bit IOAR R/W I/O Address Register (IOAR) : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. Sequential Mode and Idle Mode Transfer Counter (ETCR) Bit : : Initial value : R/W * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rev.6.00 Sep. 27, 2007 Page 225 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. Repeat Mode Transfer Number Storage (ETCRH) Bit : 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 * R/W Initial value : R/W : Transfer Counter (ETCRL) Bit : 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W *: Undefined Initial value : R/W : In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. Rev.6.00 Sep. 27, 2007 Page 226 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.4 Bit DMA Control Register (DMACR) : 7 DTSZ 0 R/W 6 DTID5 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : R/W : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID 0 Description MAR is incremented after a data transfer • • 1 • • When DTSZ = 0, MAR is incremented by 1 after a transfer When DTSZ = 1, MAR is incremented by 2 after a transfer When DTSZ = 0, MAR is decremented by 1 after a transfer When DTSZ = 1, MAR is decremented by 2 after a transfer (Initial value) MAR is decremented after a data transfer Rev.6.00 Sep. 27, 2007 Page 227 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE 0 1 DMABCR DTIE 0 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value) For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE 0 Bit 4 DTDIR 0 1 1 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address Rev.6.00 Sep. 27, 2007 Page 228 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. Channel A Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — — — Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 receive-data-full interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 receive-data-full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — (Initial value) Activated by A/D converter conversion end interrupt Rev.6.00 Sep. 27, 2007 Page 229 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Channel B Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 receive-data-full interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 receive-data-full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. Rev.6.00 Sep. 27, 2007 Page 230 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.5 DMA Band Control Register (DMABCR) DMABCRH Bit : 15 FAE1 Initial value : R/W : 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRL Bit : 7 DTE1B Initial value : R/W : 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 DTIE1B 0 R/W 2 DTIE1A 0 R/W 1 DTIE0B 0 R/W 0 DTIE0A 0 R/W DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B can be used as independent channels. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Rev.6.00 Sep. 27, 2007 Page 231 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. Bit 13 SAE1 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. Bit 12 SAE0 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. Rev.6.00 Sep. 27, 2007 Page 232 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev.6.00 Sep. 27, 2007 Page 233 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 234 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 235 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 236 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7.4. 7.3.1 Bit Memory Address Register (MAR) : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 * 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * 23 22 21 20 19 18 17 16 Initial value : R/W Bit : : Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.3.2 I/O Address Register (IOAR) IOAR is not used in full address transfer. Rev.6.00 Sep. 27, 2007 Page 237 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. Normal Mode ETCRA Transfer Counter Bit : 15 * 14 * 13 * 12 * 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. Rev.6.00 Sep. 27, 2007 Page 238 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Block Transfer Mode ETCRA Block Size Storage (ETCRAH) Bit : 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 10 * R/W 9 * R/W 8 * R/W Initial value : R/W : Block Size Counter (ETCRAL) Bit : 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W *: Undefined Initial value : R/W : ETCRB Block Transfer Counter Bit : 15 * 14 * 13 * 12 * 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev.6.00 Sep. 27, 2007 Page 239 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode. DMACRA Bit : 15 DTSZ Initial value : R/W : 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W DMACRB Bit : 7 — Initial value : R/W : 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Rev.6.00 Sep. 27, 2007 Page 240 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARA is incremented by 1 after a transfer When DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value) MARA is fixed MARA is decremented after a data transfer • • When DTSZ = 0, MARA is decremented by 1 after a transfer When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR 0 1 Bit 11 BLKE 0 1 0 1 Description Transfer in normal mode Transfer in normal mode Transfer in block transfer mode, source side is block area (Initial value) Transfer in block transfer mode, destination side is block area For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Can be read or written to. Only 0 should be written to these bits. Rev.6.00 Sep. 27, 2007 Page 241 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARB is incremented by 1 after a transfer When DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value) MARB is fixed MARB is decremented after a data transfer • • When DTSZ = 0, MARB is decremented by 1 after a transfer When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Can be read or written to. Only 0 should be written to this bit. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 * * Bit 0 DTF0 0 1 0 1 * 0 1 * Description — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — Auto-request (cycle steal) Auto-request (burst) — *: Don't care (Initial value) Rev.6.00 Sep. 27, 2007 Page 242 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) • Block Transfer Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 receive-data-full interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 receive-data-full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. Rev.6.00 Sep. 27, 2007 Page 243 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.5 DMA Band Control Register (DMABCR) DMABCRH: Bit : 15 FAE1 Initial value : R/W : 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W DMABCRL: Bit : : Initial value : R/W : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 DTIE1B 0 R/W 2 DTIE1A 0 R/W 1 DTIE0B 0 R/W 0 DTIE0A 0 R/W DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Rev.6.00 Sep. 27, 2007 Page 244 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Bits 13 and 12—Reserved: Can be read or written to. Only 0 should be written to these bits. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev.6.00 Sep. 27, 2007 Page 245 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 10 and 8—Reserved: Can be read or written to. Only 0 should be written to these bits. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 246 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 247 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Rev.6.00 Sep. 27, 2007 Page 248 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 249 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4 7.4.1 Register Descriptions (3) DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. First transfer area MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B DMABCR Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A) Rev.6.00 Sep. 27, 2007 Page 250 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR, by the DTC. Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR, by the DTC. Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Rev.6.00 Sep. 27, 2007 Page 251 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR, by the DTC. Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR, by the DTC. Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. Rev.6.00 Sep. 27, 2007 Page 252 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4.2 Bit DMA Terminal Control Register (DMATCR) : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1 0 1 Description TEND1 pin output disabled TEND1 pin output enabled (Initial value) Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 0 1 Description TEND0 pin output disabled TEND0 pin output enabled (Initial value) The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: Read-only bits, always read as 0. Rev.6.00 Sep. 27, 2007 Page 253 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15—Module Stop (MSTP15): Specifies the DMAC module stop mode. Bits 15 MSTP15 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value) Rev.6.00 Sep. 27, 2007 Page 254 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5 7.5.1 Operation Transfer Modes Table 7.5 lists the DMAC modes. Table 7.5 DMAC Transfer Modes Transfer Source • TPU channel 0 to 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI receive-data-full interrupt A/D converter conversion end interrupt External request • Remarks • • Up to 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes (1), (2), and (3) can also be specified for single address mode Max. 2-channel operation, combining channels A and B With auto-request, burst mode transfer or cycle steal transfer can be selected Transfer Mode Short address mode Dual (1) Sequential address mode mode (2) Idle mode (3) Repeat mode • • • • • (4) Single address mode Full address mode (5) Normal mode • • (6) Block transfer mode • External request Auto-request TPU channel 0 to 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI receive-data-full interrupt A/D converter conversion end interrupt External request • • • • • • Rev.6.00 Sep. 27, 2007 Page 255 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Operation in each mode is summarized below. Sequential Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. Idle Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. Repeat Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. Single Address Mode: In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Sequential mode, idle mode, and repeat mode can also be specified for single address mode. Normal Mode • Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. ⎯ Cycle steal mode The bus is released to another bus master after each byte or word transfer. ⎯ Burst mode ⎯ The bus is held and transfer continued until the specified number of transfers have been completed. Rev.6.00 Sep. 27, 2007 Page 256 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. Block Transfer Mode: In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits. 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in sequential mode. Table 7.6 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Incremented/ Destination Start address of transfer destination decremented every address transfer or transfer source register address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: IOAR: ETCR: DTDIR: Memory address register I/O address register Execute transfer count register Data transfer direction bit Rev.6.00 Sep. 27, 2007 Page 257 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Rev.6.00 Sep. 27, 2007 Page 258 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty/reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Sequential mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7.4 Example of Sequential Mode Setting Procedure Rev.6.00 Sep. 27, 2007 Page 259 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in idle mode. Table 7.7 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation Fixed address register address register Destination Start address of address transfer destination register or transfer source address register Start address of transfer source or transfer destination 0 Destination Source Fixed 0 Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register DTDIR: Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev.6.00 Sep. 27, 2007 Page 260 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Rev.6.00 Sep. 27, 2007 Page 261 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7.6 Example of Idle Mode Setting Procedure Rev.6.00 Sep. 27, 2007 Page 262 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in repeat mode. Table 7.8 Register Functions in Repeat Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when value reaches H'0000 address register Fixed Start address of transfer source or transfer destination Number of transfers Fixed 23 H'FF 15 IOAR 7 ETCRH 0 Destination Source address register transfers 0 Holds number of 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register DTDIR: Data transfer direction bit Rev.6.00 Sep. 27, 2007 Page 263 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Rev.6.00 Sep. 27, 2007 Page 264 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N –1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Rev.6.00 Sep. 27, 2007 Page 265 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer. Repeat mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7.8 Example of Repeat Mode Setting Procedure Rev.6.00 Sep. 27, 2007 Page 266 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.9 summarizes register functions in single address mode. Table 7.9 Register Functions in Single Address Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation * address register Write strobe Destination Start address of address transfer destination register or transfer source Read strobe DACK pin 15 ETCR 0 Transfer counter (Set automatically Strobe for external by SAE bit; IOAR is device invalid) Number of transfers * Legend: MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer register DTDIR: Data transfer direction bit DACK: Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. Rev.6.00 Sep. 27, 2007 Page 267 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) Rev.6.00 Sep. 27, 2007 Page 268 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Single address mode setting Set DMABCRH [1] Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Set DMABCRL [6] Single address mode Figure 7.10 Example of Single Address Mode Setting Procedure (When Sequential Mode is Specified) Rev.6.00 Sep. 27, 2007 Page 269 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.10 summarizes register functions in normal mode. Table 7.10 Register Functions in Normal Mode Register 23 MARA 23 MARB 15 ETCRA Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Transfer counter Start address of Incremented/decremented transfer destination every transfer, or fixed Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev.6.00 Sep. 27, 2007 Page 270 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.11 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend: Address Address Address Address Where : Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev.6.00 Sep. 27, 2007 Page 271 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) For setting details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Set DMABCRL [6] Normal mode Figure 7.12 Example of Normal Mode Setting Procedure Rev.6.00 Sep. 27, 2007 Page 272 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.11 summarizes register functions in block transfer mode. Table 7.11 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Holds block ETCRAH Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed size Block size Block size Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 7 ETCRAL 0 counter 15 ETCRB 0 Block transfer counter Number of block transfers Legend: MARA: MARB: ETCRA: ETCRB: Memory address register A Memory address register B Execute transfer count register A Execute transfer count register B Rev.6.00 Sep. 27, 2007 Page 273 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area. Rev.6.00 Sep. 27, 2007 Page 274 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area. Rev.6.00 Sep. 27, 2007 Page 275 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. Rev.6.00 Sep. 27, 2007 Page 276 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ ETCRAL = ETCRAL – 1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7.15 Operation Flow in Block Transfer Mode Rev.6.00 Sep. 27, 2007 Page 277 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Block transfer mode setting Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Block transfer mode Figure 7.16 Example of Block Transfer Mode Setting Procedure Rev.6.00 Sep. 27, 2007 Page 278 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7.12. Table 7.12 DMAC Activation Sources Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode X X X X X X X X X X X X X X X X Block Transfer Mode Activation Source Internal Interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External Requests DREQ pin falling edge input DREQ pin low-level input Auto-request Legend: : Can be specified X : Cannot be specified Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared Rev.6.00 Sep. 27, 2007 Page 279 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. Rev.6.00 Sep. 27, 2007 Page 280 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7.16 shows the data bus in single address mode. RD HWR, LWR A23 to A0 Address bus (Read) Chip External memory D15 to D0 (high impedance) Data bus (Write) External device DACK Figure 7.17 Data Bus in Single Address Mode When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode. Rev.6.00 Sep. 27, 2007 Page 281 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. CPU cycle T1 φ Source address Address bus RD HWR LWR Destination address DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Figure 7.18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. Rev.6.00 Sep. 27, 2007 Page 282 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0. Rev.6.00 Sep. 27, 2007 Page 283 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Cycle Steal Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.6.00 Sep. 27, 2007 Page 284 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Burst Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release DMA write DMA read DMA write DMA read DMA write DMA dead Figure 7.21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev.6.00 Sep. 27, 2007 Page 285 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Block Transfer Mode): Figure 7.22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release Figure 7.22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. Rev.6.00 Sep. 27, 2007 Page 286 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.23 shows an example of DREQ pin falling edge activated normal mode transfer. DMA read DMA write Bus release DMA read DMA write Bus release Bus release φ DREQ Address bus DMA control Channel Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Sep. 27, 2007 Page 287 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer Bus release φ DREQ Address bus DMA control Channel DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Request clear period Request Minimum of 2 cycles Request clear period Minimum of 2 cycles [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Sep. 27, 2007 Page 288 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.25 shows an example of DREQ level activated normal mode transfer. Bus release DMA read DMA write Bus release DMA read DMA write Bus release φ DREQ Address bus DMA control Channel Idle Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Read Write Idle Request Minimum of 2 cycles [1] [2] Request clear period Request Minimum of 2 cycles Request clear period [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.25 Example of DREQ Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Sep. 27, 2007 Page 289 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer Bus release DMA read DMA write DMA Bus dead release DMA read 1 block transfer DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle Request Minimum of 2 cycles [1] [2] [3] Request clear period Request Minimum of 2 cycles [4] [5] [6] Request clear period [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.26 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Sep. 27, 2007 Page 290 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA DMA read dead DMA read φ Address bus RD DACK TEND DMA read DMA read Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.27 Example of Single Address Mode (Byte Read) Transfer Rev.6.00 Sep. 27, 2007 Page 291 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA dead DMA read DMA read DMA read φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.6.00 Sep. 27, 2007 Page 292 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Single Address Mode (Write): Figure 7.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA DMA write dead DMA write φ Address bus HWR LWR DACK TEND DMA write DMA write Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.29 Example of Single Address Mode (Byte Write) Transfer Rev.6.00 Sep. 27, 2007 Page 293 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA dead DMA write DMA write DMA write φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.30 Example of Single Address Mode (Word Write) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are executed by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.6.00 Sep. 27, 2007 Page 294 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer. Bus release φ DREQ Address bus DACK Transfer source/ destination Transfer source/ destination DMA single Bus release DMA single Bus release DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes Acceptance resumes [1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance Rev.6.00 Sep. 27, 2007 Page 295 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.32 shows an example of DREQ pin low level activated single address mode transfer. Bus release Bus release φ DREQ DMA single Bus release DMA single Address bus DACK Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. Rev.6.00 Sep. 27, 2007 Page 296 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7.33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Internal address Internal read signal External address HWR, LWR TEND Figure 7.33 Example of Dual Address Transfer Using Write Data Buffer Function Rev.6.00 Sep. 27, 2007 Page 297 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.13 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.13 summarizes the priority order for DMAC channels. Table 7.13 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High Rev.6.00 Sep. 27, 2007 Page 298 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA DMA write read DMA read DMA write DMA read DMA write DMA read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7.35 Example of Multi-Channel Transfer Rev.6.00 Sep. 27, 2007 Page 299 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles, and the DTC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. Rev.6.00 Sep. 27, 2007 Page 300 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. Resumption of transfer on interrupted channel DTE = 1 DTME = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev.6.00 Sep. 27, 2007 Page 301 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7.37 shows the procedure for forcibly terminating DMAC operation by software. [1] Clear the DTE bit in DMABCRL to 0. To prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Forced termination of DMAC Clear DTE bit to 0 [1] Forced termination Figure 7.37 Example of Procedure for Forcibly Terminating DMAC Operation Rev.6.00 Sep. 27, 2007 Page 302 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.17 Clearing Full Address Mode Figure 7.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2] Clearing full address mode Stop the channel [1] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7.38 Example of Procedure for Clearing Full Address Mode Rev.6.00 Sep. 27, 2007 Page 303 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14 shows the interrupt sources and their priority order. Table 7.14 Interrupt Source Priority Order Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.14. Figure 7.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while the DTE bit is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7.39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while the DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev.6.00 Sep. 27, 2007 Page 304 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) 7.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, MAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. (a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMAC transfer. Figure 7.40 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read DMA write DMA read DMA write φ DMA Internal address DMA control DMA register operation Idle Transfer source Read Transfer destination Write Idle Transfer source Read Transfer destination Write Dead Idle [1] [2] [1] [2'] [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Notes: 1. In single address transfer mode, the update timing is the same as [1]. 2. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7.40 DMAC Register Update Timing Rev.6.00 Sep. 27, 2007 Page 305 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.41. CPU longword read MAR upper word read MAR lower word read DMA transfer cycle DMA read DMA write φ DMA internal address DMA control DMA register operation Idle Transfe source Read Transfer destination Write Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.41 Contention between DMAC Register Update and CPU Read Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/break interrupt (DTE = 0 and DTIE = 1) • TEND pin enable (TEE = 1) • DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock. Rev.6.00 Sep. 27, 2007 Page 306 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. • Write Data Buffer Function and DMAC Register Setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. • Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. • Write Data Buffer Function and TEND Output A low level is not output at the TEND pin if the bus cycle in which a low level is to be output at the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output at the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output at the TEND pin. Figure 7.42 shows an example in which a low level is not output at the TEND pin. Rev.6.00 Sep. 27, 2007 Page 307 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) DMA read φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write Figure 7.42 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Rev.6.00 Sep. 27, 2007 Page 308 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or a forcible termination should be handled by the CPU as necessary. Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them. Rev.6.00 Sep. 27, 2007 Page 309 of 1268 REJ09B0220-0600 Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 310 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller Section 8 Data Transfer Controller 8.1 Overview The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software. 8.1.1 Features The features of the DTC are: • Transfer possible over any number of channels ⎯ Transfer information is stored in memory ⎯ One activation source can trigger a number of data transfers (chain transfer) ⎯ Chain transfer execution can be set after data transfer (when counter = 0) • Selection of transfer modes ⎯ Normal, repeat, and block transfer modes available ⎯ Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible ⎯ 24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC ⎯ An interrupt request can be issued to the CPU after one data transfer ends ⎯ An interrupt request can be issued to the CPU after all the specified data transfers have ended • Activation by software is possible • Module stop mode can be set ⎯ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode Rev.6.00 Sep. 27, 2007 Page 311 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR DTC activation request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 8.1 Block Diagram of DTC Rev.6.00 Sep. 27, 2007 Page 312 of 1268 REJ09B0220-0600 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERF DTVECR Section 8 Data Transfer Controller 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W —* 2 —* —* 2 —* 2 —* 2 2 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF Address* —* 3 —* —* 3 —* —* 3 —* 3 3 3 1 —* 2 R/W R/W R/W H'FF30 to H'FF35 H'FF37 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev.6.00 Sep. 27, 2007 Page 313 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined — Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev.6.00 Sep. 27, 2007 Page 314 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined — 6 DISEL Undefined — 5 CHNS Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined — Initial value : R/W : MRB is an 8-bit register that controls the DTC operating mode. Rev.6.00 Sep. 27, 2007 Page 315 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state) DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bit 5—DTC Chain Transfer Select (CHNS): Specifies the chain transfer condition when CHNE is 1. Bit 7 CHNE 0 1 1 Bit 5 CHNS – 0 1 Description No chain transfer (DTC data transfer end, activation waiting state entered) DTC chain transfer Chain transfer only when transfer counter = 0 Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the chip and should always be written with 0. Rev.6.00 Sep. 27, 2007 Page 316 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 ––– ––– 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 ––– ––– 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev.6.00 Sep. 27, 2007 Page 317 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — ←⎯⎯⎯⎯⎯⎯⎯ CRAH ⎯⎯⎯⎯⎯⎯→ ←⎯⎯⎯⎯⎯⎯⎯ CRAL ⎯⎯⎯⎯⎯⎯→ CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA register is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev.6.00 Sep. 27, 2007 Page 318 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value : R/W : The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.5, together with the vector numbers generated by the interrupt controller. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. Rev.6.00 Sep. 27, 2007 Page 319 of 1268 REJ09B0220-0600 Section 8 Data Transfer Controller 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W) 6 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* 3 0 R/(W)* 2 0 R/(W)* 1 0 R/(W)* 0 0 R/(W)* SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] • • 1 When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written after a software activation data-transfer-complete interrupt is issued to the CPU (Initial value) DTC software activation is enabled [Holding conditions] • • • When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs. Bit 3 OS3 0 1 Bit 2 OS2 0 1 0 1 Bit 1 OS1 0 1 Bit 0 OS0 0 1 0 1 Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) (Initial value) Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value) Rev.6.00 Sep. 27, 2007 Page 565 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12—Module Stop (MSTP12): Specifies the 8-bit timer module stop mode. Bit 12 MSTP12 0 1 Description 8-bit timer module stop mode cleared 8-bit timer module stop mode set (Initial value) Rev.6.00 Sep. 27, 2007 Page 566 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.3 12.3.1 Operation TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 12.2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 12.3 shows the timing of incrementation at both edges of an external clock signal. Rev.6.00 Sep. 27, 2007 Page 567 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers φ External clock input pin Clock input to TCNT TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 12.4 shows this timing. φ TCNT N N+1 TCOR Compare match signal N CMF Figure 12.4 Timing of CMF Setting Rev.6.00 Sep. 27, 2007 Page 568 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers Timer Output Timing: When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 12.5 Timing of Timer Output Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation. φ Compare match signal TCNT N H'00 Figure 12.6 Timing of Compare Match Clear Rev.6.00 Sep. 27, 2007 Page 569 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.3.3 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.7 Timing of Clearance by External Reset 12.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.8 shows the timing of this operation. φ TCNT H'FF H'00 Overflow signal OVF Figure 12.8 Timing of OVF Setting Rev.6.00 Sep. 27, 2007 Page 570 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. • Setting of compare match flags ⎯ The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs. ⎯ The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. • Counter clear specification ⎯ If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set. ⎯ The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. • Pin output ⎯ Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions. ⎯ Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Usage Note: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes. Rev.6.00 Sep. 27, 2007 Page 571 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.4 12.4.1 Interrupts Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12.3 8-Bit Timer Interrupt Sources Channel 0 Interrupt Source CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 12.4.2 A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev.6.00 Sep. 27, 2007 Page 572 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 12.9 Example of Pulse Output Rev.6.00 Sep. 27, 2007 Page 573 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.6 Usage Notes Note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12.10 Contention between TCNT Write and Clear Rev.6.00 Sep. 27, 2007 Page 574 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.11 Contention between TCNT Write and Increment Rev.6.00 Sep. 27, 2007 Page 575 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 12.12 shows this operation. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 12.12 Contention between TCOR Write and Compare Match Rev.6.00 Sep. 27, 2007 Page 576 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers 12.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.4. Table 12.4 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High 12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 12.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks. Rev.6.00 Sep. 27, 2007 Page 577 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers Table 12.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from 1 low to low* Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from 2 low to high* Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from 3 high to low* Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev.6.00 Sep. 27, 2007 Page 578 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from high to high Clock before switchover Clock after switchover TCNT clock No. 4 TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 12.6.6 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 579 of 1268 REJ09B0220-0600 Section 12 8-Bit Timers Rev.6.00 Sep. 27, 2007 Page 580 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer Section 13 Watchdog Timer 13.1 Overview The chip has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF)* if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 13.1.1 Features WDT features are listed below. • Switchable between watchdog timer mode and interval timer mode • WDTOVF output when in watchdog timer mode* If the counter overflows, the WDT outputs WDTOVF*. It is possible to select whether or not the entire chip is reset at the same time • Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt • Choice of eight counter clock sources Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Rev.6.00 Sep. 27, 2007 Page 581 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the WDT. Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select WDTOVF*1 Internal reset signal*2 Reset control φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. Internal reset signal generation is specified by means of a register setting. Figure 13.1 Block Diagram of WDT Rev.6.00 Sep. 27, 2007 Page 582 of 1268 REJ09B0220-0600 Internal bus Section 13 Watchdog Timer 13.1.3 Pin Configuration Table 13.1 describes the WDT output pin. Table 13.1 WDT Pin Name Watchdog timer overflow Symbol WDTOVF* I/O Output Function Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. 13.1.4 Register Configuration The WDT has three registers, as summarized in table 13.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13.2 WDT Registers Address* Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W 3 R/(W)* 1 Initial Value H'18 H'00 *3 H'1F Write *2 Read H'FFBC H'FFBD H'FFBF H'FFBC H'FFBC H'FFBE R/W R/(W) Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 13.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. Rev.6.00 Sep. 27, 2007 Page 583 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.2 13.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)*2 or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Notes: 1. TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. 2. The WDTOVF pin function cannot be used in the F-ZTAT versions. Rev.6.00 Sep. 27, 2007 Page 584 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.2.2 Bit Timer Control/Status Register (TCSR) : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading TCSR when OVF = 1*, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Note: * When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at least twice. (Initial value) Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal*1 when TCNT overflows. Rev.6.00 Sep. 27, 2007 Page 585 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer Bit 6 WT/IT 0 1 Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) 1 2 Watchdog timer: Generates the WDTOVF signal* when TCNT overflows* Notes: 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (φ), for input to TCNT. Description Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Clock φ/2 (Initial value) φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Overflow Period (when φ = 20 MHz)* 25.6 µs 819.2 µs 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Rev.6.00 Sep. 27, 2007 Page 586 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 — 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : Note: * Only 0 can be written, to clear the flag. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 1 Description [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer operation (Initial value) Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Description Reset signal is not generated if TCNT overflows * Reset signal is generated if TCNT overflows (Initial value) Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset. Rev.6.00 Sep. 27, 2007 Page 587 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer Bit 5—Reserved: This bit should be written with 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. 13.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 13.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FFBC H'5A 87 Write data 0 TCSR write 15 Address: H'FFBC H'A5 87 Write data 0 Figure 13.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by a word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 13.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE bit. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the WOVF bit. Rev.6.00 Sep. 27, 2007 Page 588 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0 Writing to RSTE bit 15 Address: H'FFBE H'5A 87 Write data 0 Figure 13.3 Writing to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. 13.3 13.3.1 Operation Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal* is output. This is shown in figure 13.4. This WDTOVF signal* can be used to reset the system. The WDTOVF signal* is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip internally is generated at the same time as the WDTOVF signal*. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Rev.6.00 Sep. 27, 2007 Page 589 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF *3 and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal*3 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF pin function cannot be used in the F-ZTAT versions. Figure 13.4 Operation in Watchdog Timer Mode Rev.6.00 Sep. 27, 2007 Page 590 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13.5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 13.5 Operation in Interval Timer Mode Rev.6.00 Sep. 27, 2007 Page 591 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.3.3 Timing of Overflow Flag (OVF) Setting The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 13.6. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of OVF Setting Rev.6.00 Sep. 27, 2007 Page 592 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 13.7 shows the timing in this case. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. φ TCNT Overflow signal (internal signal) WOVF H'FF H'00 WDTOVF signal* Internal reset signal 132 states 518 states Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Figure 13.7 Timing of WOVF Setting Rev.6.00 Sep. 27, 2007 Page 593 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 13.5 13.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.8 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.8 Contention between TCNT Write and Increment Rev.6.00 Sep. 27, 2007 Page 594 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 13.5.4 System Reset by WDTOVF Signal* If the WDTOVF output signal* is input to the RES pin of the chip, the chip will not be initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal*, use the circuit shown in figure 13.9. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Chip Reset input RES Reset signal to entire system WDTOVF* Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Figure 13.9 Circuit for System Reset by WDTOVF Signal (Example) Rev.6.00 Sep. 27, 2007 Page 595 of 1268 REJ09B0220-0600 Section 13 Watchdog Timer 13.5.5 Internal Reset in Watchdog Timer Mode The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. Rev.6.00 Sep. 27, 2007 Page 596 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Section 14 Serial Communication Interface (SCI) 14.1 Overview The chip is equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 14.1.1 Features SCI features are listed below. • Choice of asynchronous or synchronous serial communication mode Asynchronous mode ⎯ Serial data communication executed using an asynchronous system in which synchronization is achieved character by character ⎯ Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) ⎯ A multiprocessor communication function is provided that enables serial data communication with a number of processors ⎯ Choice of 12 serial data transfer formats Data length: Stop bit length: Parity: 7 or 8 bits 1 or 2 bits Even, odd, or none Multiprocessor bit: 1 or 0 ⎯ Receive error detection: Parity, overrun, and framing errors ⎯ Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error Synchronous mode ⎯ Serial data communication synchronized with a clock ⎯ Serial data communication can be carried out with other chips that have a synchronous communication function ⎯ One serial data transfer format Data length: 8 bits ⎯ Receive error detection: Overrun errors detected Rev.6.00 Sep. 27, 2007 Page 597 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) • Full-duplex communication capability ⎯ The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • Choice of LSB-first or MSB-first transfer ⎯ Can be selected regardless of the communication mode*1 (except in the case of asynchronous mode 7-bit data) • Built-in baud rate generator allows any bit rate to be selected • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin • Four interrupt sources ⎯ Four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive error—that can issue requests independently ⎯ The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC)*2 or data transfer controller (DTC) to execute data transfer • Module stop mode can be set ⎯ As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode Notes: 1. Descriptions in this section refer to LSB-first transfer. 2. The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 598 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: SCMR: Smart card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 14.1 Block Diagram of SCI Rev.6.00 Sep. 27, 2007 Page 599 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.1.3 Pin Configuration Table 14.1 shows the serial pins for each SCI channel. Table 14.1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev.6.00 Sep. 27, 2007 Page 600 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.1.4 Register Configuration The SCI has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 14.2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W 2 R/(W)* Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF 2 Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C 1 R R/W R/W R/W R/W R/W 2 R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W H'84 H'00 H'F2 H'3FFF Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 601 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2 14.2.1 Bit Register Descriptions Receive Shift Register (RSR) : : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — R/W RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 14.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode. Rev.6.00 Sep. 27, 2007 Page 602 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.3 Bit Transmit Shift Register (TSR) : : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — R/W TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 14.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. Rev.6.00 Sep. 27, 2007 Page 603 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * W hen 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Rev.6.00 Sep. 27, 2007 Page 604 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E 0 1 Description Even parity* 2 Odd parity* 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Rev.6.00 Sep. 27, 2007 Page 605 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 14.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 1 Bit 0 CKS0 0 1 0 1 Description φ clock φ/4 clock φ/16 clock φ/64 clock (Initial value) Rev.6.00 Sep. 27, 2007 Page 606 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit-data-empty interrupt (TXI) requests disabled* Transmit-data-empty interrupt (TXI) requests enabled (Initial value) Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Rev.6.00 Sep. 27, 2007 Page 607 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* 2 Transmission enabled* 1 (Initial value) Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* 2 Reception enabled* 1 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Rev.6.00 Sep. 27, 2007 Page 608 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • • 1 When the MPIE bit is cleared to 0 When data with MPB = 1 is received Multiprocessor interrupts enabled* Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. (Initial value) Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). Set CKE1 and CKE0 before determining the SCI operating mode with SMR. Rev.6.00 Sep. 27, 2007 Page 609 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) For details of clock source selection, see table 14.9. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output* Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 2 External clock/SCK pin functions as serial clock input 3 External clock/SCK pin functions as clock input* External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev.6.00 Sep. 27, 2007 Page 610 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC* or DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 611 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC* or DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Notes: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. * The DMAC is not supported in the H8S/2321. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 1 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1* 2 (Initial value)* 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Rev.6.00 Sep. 27, 2007 Page 612 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 1 Description [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, 2 and the stop bit is 0 * Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. (Initial value)* 1 Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not 2 match the parity setting (even or odd) specified by the O/E bit in SMR* (Initial value)* 1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Rev.6.00 Sep. 27, 2007 Page 613 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC* or DTC is activated by a TXI interrupt and writes data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Note: * The DMAC is not supported in the H8S/2321. Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 Description [Clearing condition] (Initial value)* When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) Rev.6.00 Sep. 27, 2007 Page 614 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 14.3 shows sample BRR settings in asynchronous mode, and table 14.4 shows sample BRR settings in synchronous mode. Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ = 2 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 — — 0.00 — φ = 2.097152 MHz Error (%) φ = 2.4576 MHz Error (%) φ = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 — n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 n 1 1 0 0 0 0 0 0 0 0 0 N 148 108 217 108 54 26 13 6 2 1 1 n N 174 127 255 127 63 31 15 7 3 1 1 n N 212 155 77 155 77 38 19 9 4 2 — –0.04 1 0.21 0.21 0.21 1 0 0 –0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 1 1 0 0 0 0 0 0 0 — –0.70 0 1.14 0 –2.48 0 –2.48 0 — — — 0 0 0 Rev.6.00 Sep. 27, 2007 Page 615 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) φ = 3.6864 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 φ = 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 — 0.00 — φ = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 φ = 5 MHz Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 –1.70 0 0.00 0 φ = 6 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) φ = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 φ = 7.3728 MHz Error (%) φ = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 — n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 — 0 N 130 95 191 95 191 95 47 23 11 — 5 n N 141 103 207 103 207 103 51 25 12 7 — –0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 –0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 2 1 1 0 0 0 0 0 0 — –2.34 0 –2.34 0 0.00 0 –2.34 0 Rev.6.00 Sep. 27, 2007 Page 616 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) φ = 9.8304 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) φ = 10 MHz Error (%) φ = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 φ = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n N 177 129 64 129 64 129 64 32 15 9 7 n N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 –0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 –0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –1.36 0 1.73 0.00 1.73 0 0 0 –2.34 0 0.00 0 –1.70 0 0.00 0 –2.34 0 φ = 14 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) φ = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 φ = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 φ = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 10 n N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 –0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –0.93 0 –0.93 0 0.00 — 0 0 –1.70 0 0.00 0 Rev.6.00 Sep. 27, 2007 Page 617 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) φ = 18 MHz Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) φ = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 φ = 20 MHz Error (%) φ = 25 MHz Error (%) –0.02 0.47 –0.15 0.47 –0.15 0.47 –0.15 0.47 –0.76 1.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 n N 110 80 162 80 162 80 162 80 40 24 19 –0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –0.25 3 0.16 0.16 0.16 0.16 0.16 0.16 0.16 3 2 2 1 1 0 0 –0.69 0 1.02 0.00 0 0 –1.36 0 0.00 1.73 0 0 –1.70 0 0.00 0 –2.34 0 Rev.6.00 Sep. 27, 2007 Page 618 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.4 BRR Settings for Various Bit Rates (Synchronous Mode) Bit Rate φ = 2 MHz (bits/s) n 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* 2 2 1 1 0 0 0 0 0 0 0 0 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* — — — 1 1 0 0 0 0 0 0 — — — 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 — — 2 1 1 0 0 0 0 0 0 0 0 — — 124 249 124 199 99 49 19 9 4 1 0* 3 2 2 1 0 0 0 0 — — — — 97 155 77 155 249 124 62 24 — — — — φ = 4 MHz n N n φ = 8 MHz N n φ = 10 MHz N n φ = 16 MHz N n φ = 20 MHz N n φ = 25 MHz N Note: Blank: —: *: As far as possible, the setting should be made so that the error is no more than 1%. Cannot be set. Can be set, but there will be a degree of error. Continuous transfer is not possible. Rev.6.00 Sep. 27, 2007 Page 619 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= φ 64 × 2 2n–1 ×B × 10 6 – 1 Synchronous mode: N= Where B: N: φ: n: φ 8×2 2n–1 ×B × 10 6 – 1 Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock φ φ/4 φ/16 φ/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { φ × 106 (N + 1) × B × 64 × 22n–1 – 1} × 100 Rev.6.00 Sep. 27, 2007 Page 620 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14.6 and 14.7 show the maximum bit rates with external clock input. Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 781250 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.6.00 Sep. 27, 2007 Page 621 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.2500 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 390625 Rev.6.00 Sep. 27, 2007 Page 622 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) 2 4 6 8 10 12 14 16 18 20 25 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 4.1667 Maximum Bit Rate (bits/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 4166666.7 14.2.9 Bit Smart Card Mode Register (SCMR) : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first transfer by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first transfer can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 15.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Rev.6.00 Sep. 27, 2007 Page 623 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in SMR. Bit 2 SINV 0 1 Description TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form (Initial value) Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written to this bit. Bit 0 SMIF 0 1 Description Operates as normal SCI (smart card interface function disabled) Smart card interface function enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 624 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the SCI channel 2 module stop mode. Bit 7 MSTP7 0 1 Description SCI channel 2 module stop mode cleared SCI channel 2 module stop mode set (Initial value) Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value) Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) Rev.6.00 Sep. 27, 2007 Page 625 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.3 14.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 14.8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 14.9. Asynchronous Mode • Data length: Choice of 7 or 8 bits • Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing, parity, and overrun errors, and breaks, during reception • Choice of internal or external clock as SCI clock source ⎯ When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ⎯ When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) Synchronous Mode • Transfer format: Fixed 8-bit data • Detection of overrun errors during reception • Choice of internal or external clock as SCI clock source ⎯ When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip ⎯ When external clock is selected: The built-in baud rate generator is not used, and the SCI operates on the input serial clock Rev.6.00 Sep. 27, 2007 Page 626 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 — — 1 — — 1 — — — 0 1 0 1 — Synchronous mode 8-bit data No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data SCI Transfer Format Multiprocessor Bit No Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 14.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 1 0 1 0 1 0 1 0 1 Synchronous mode Internal External Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock Inputs serial clock Rev.6.00 Sep. 27, 2007 Page 627 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 1 1 1 Transmit/receive data 7 or 8 bits Parity Stop bit(s) bit 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev.6.00 Sep. 27, 2007 Page 628 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Data Transfer Format Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 14.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 ⎯ ⎯ ⎯ ⎯ MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.6.00 Sep. 27, 2007 Page 629 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 14.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI initialization (asynchronous mode): Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Rev.6.00 Sep. 27, 2007 Page 630 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Figure 14.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the TxD or RxD pin to be used. [4] Start of initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits as necessary Figure 14.4 Sample SCI Initialization Flowchart Rev.6.00 Sep. 27, 2007 Page 631 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Serial data transmission (asynchronous mode): Figure 14.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit-dataempty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Initialization Start of transmission [1] Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Note: * The DMAC is not supported in the H8S/2321. Figure 14.5 Sample Serial Transmission Flowchart Rev.6.00 Sep. 27, 2007 Page 632 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Rev.6.00 Sep. 27, 2007 Page 633 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Figure 14.6 shows an example of the operation for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 14.6 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.6.00 Sep. 27, 2007 Page 634 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Serial data reception (asynchronous mode): Figure 14.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start of reception [1] [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER ∨ FER ∨ ORER = 1? ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error handling be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 Note: * The DMAC is not supported in the H8S/2321. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC* or DTC is activated by an RXI interrupt and the RDR value is read. Figure 14.7 Sample Serial Reception Flowchart Rev.6.00 Sep. 27, 2007 Page 635 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 14.7 Sample Serial Reception Flowchart (cont) Rev.6.00 Sep. 27, 2007 Page 636 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 14.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. Rev.6.00 Sep. 27, 2007 Page 637 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.11 Receive Error Conditions Receive Error Overrun error Abbreviation ORER Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to RDR in SSR is set to 1 When the stop bit is 0 Receive data is transferred from RSR to RDR Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR in SMR Figure 14.8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 14.8 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) Rev.6.00 Sep. 27, 2007 Page 638 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 14.9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 14.10. Rev.6.00 Sep. 27, 2007 Page 639 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Clock See section 14.3.2, Operation in Asynchronous Mode. Transmitting station Serial communication line Receiving station A (ID= 01) Serial data Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) H'01 (MPB= 1) ID transmission cycle= receiving station specification H'AA (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 14.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations Multiprocessor serial data transmission: Figure 14.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev.6.00 Sep. 27, 2007 Page 640 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Initialization Start of transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Note: * The DMAC is not supported in the H8S/2321. Figure 14.10 Sample Multiprocessor Serial Transmission Flowchart Rev.6.00 Sep. 27, 2007 Page 641 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. Rev.6.00 Sep. 27, 2007 Page 642 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Figure 14.11 shows an example of SCI operation for transmission using the multiprocessor format. MultiprocesStop sor bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14.11 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor serial data reception: Figure 14.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev.6.00 Sep. 27, 2007 Page 643 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER ∨ ORER = 1? No Read RDRF flag in SSR Yes [4] No RDRF = 1? Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error handling (Continued on next page) Figure 14.12 Sample Multiprocessor Serial Reception Flowchart Rev.6.00 Sep. 27, 2007 Page 644 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.6.00 Sep. 27, 2007 Page 645 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Figure 14.13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine ID1 If not this station's ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station's ID 1 Start bit Data (ID2) MPB D0 D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 0 1 Idle state (mark state) MPIE RDRF RDR value ID1 ID2 Data2 MPIE bit set to 1 again MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine (b) Data matches station's ID Figure 14.13 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.6.00 Sep. 27, 2007 Page 646 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.14 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care * MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Bit 0 Note: * High except in continuous transfer Figure 14.14 Data Format in Synchronous Communication In synchronous serial communication, data on the communication line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the communication line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Rev.6.00 Sep. 27, 2007 Page 647 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, an external clock should be selected as the clock source. Data Transfer Operations SCI initialization (synchronous mode): Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 14.15 shows a sample SCI initialization flowchart. Rev.6.00 Sep. 27, 2007 Page 648 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Start of initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the TxD or RxD pin to be used. [2] Set value in BRR Wait [3] No 1-bit interval elapsed? Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits as necessary [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 14.15 Sample SCI Initialization Flowchart Rev.6.00 Sep. 27, 2007 Page 649 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Serial data transmission (synchronous mode): Figure 14.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmit-dataempty interrupt (TXI) request and data is written to TDR. Initialization Start of transmission [1] Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1? Yes Clear TE bit in SCR to 0 Note: * The DMAC is not supported in the H8S/2321. Figure 14.16 Sample Serial Transmission Flowchart Rev.6.00 Sep. 27, 2007 Page 650 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 14.17 shows an example of SCI operation in transmission. Rev.6.00 Sep. 27, 2007 Page 651 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine 1 frame TEI interrupt request generated Figure 14.17 Example of SCI Transmit Operation Serial data reception (synchronous mode): Figure 14.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev.6.00 Sep. 27, 2007 Page 652 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Initialization Start of reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1? No [2] [3] Error processing (Continued below) [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC* or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] [5] Error handling Overrun error handling Clear ORER flag in SSR to 0 Note: * The DMAC is not supported in the H8S/2321. Figure 14.18 Sample Serial Reception Flowchart Rev.6.00 Sep. 27, 2007 Page 653 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 14.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 14.19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 14.19 Example of SCI Receive Operation Simultaneous serial data transmission and reception (synchronous mode): Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev.6.00 Sep. 27, 2007 Page 654 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Initialization Start of transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read ORER flag in SSR Yes [3] Error handling ORER = 1? No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC* or DTC is activated by a transmitdata-empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC* or DTC is activated by a receive-data-full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Notes: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE and RE bits to 0, then set both these bits to 1 simultaneously. * The DMAC is not supported in the H8S/2321. Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.6.00 Sep. 27, 2007 Page 655 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC* or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. The DMAC* and DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC* or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. The DMAC* and DTC cannot be activated by an ERI interrupt request. Also note that the DMAC* cannot be activated by an SCI channel 2 interrupt. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 656 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Table 14.12 SCI Interrupt Sources Channel 0 Interrupt Source Description ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible DMAC* Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Not possible Not possible Not possible Low 2 1 Priority* High Notes: 1. This table shows the initial state immediate after a reset. Relative priorities among channels can be changed by the interrupt controller. 2. The DMAC is not supported in the H8S/2321. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. Rev.6.00 Sep. 27, 2007 Page 657 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 14.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously: If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 14.13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 14.13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer from RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. X : Receive data is not transferred from RSR to RDR. Rev.6.00 Sep. 27, 2007 Page 658 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Therefore, DDR and DR for the port corresponding to the TxD pin should first be set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 14.21. Rev.6.00 Sep. 27, 2007 Page 659 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. M = | (0.5 – Where M N D L F 1 2N ) – (L – 0.5) F – | D – 0.5 | N (1 + F) | × 100% ... Formula (1) : Receive margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a receive margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% ... Formula (2) = 46.875% However, this is a theoretical value, and a margin of 20% to 30% should be allowed in system design. Rev.6.00 Sep. 27, 2007 Page 660 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Restrictions on Use of DMAC* or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DMAC* or DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 14.22) • When RDR is read by the DMAC* or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI). Note: * The DMAC is not supported in the H8S/2321. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4 clocks. Figure 14.22 Example of Synchronous Transmission Using DTC Rev.6.00 Sep. 27, 2007 Page 661 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 14.23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 14.24 and 14.25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 14.26 shows a sample flowchart for mode transition during reception. Rev.6.00 Sep. 27, 2007 Page 662 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1? Yes TE = 0 No [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [3] Includes module stop mode. [2] Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [3] No TE = 1 Figure 14.23 Sample Flowchart for Mode Transition during Transmission Rev.6.00 Sep. 27, 2007 Page 663 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Start of transmission End of transmission Transition to software standby Exit from software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 14.24 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 14.25 Synchronous Transmission Using Internal Clock Rev.6.00 Sep. 27, 2007 Page 664 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Read RDRF flag in SSR No [1] [1] Receive data being received becomes invalid. RDRF = 1? Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [2] [2] Includes module stop mode. No RE = 1 Figure 14.26 Sample Flowchart for Mode Transition during Reception Rev.6.00 Sep. 27, 2007 Page 665 of 1268 REJ09B0220-0600 Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep. 27, 2007 Page 666 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Section 15 Smart Card Interface 15.1 Overview The SCI supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (identification card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 15.1.1 Features Features of the smart card interface supported by the chip is as follows. • Asynchronous mode ⎯ Data length: 8 bits ⎯ Parity bit generation and checking ⎯ Transmission of error signal (parity error) in receive mode ⎯ Error signal detection and automatic data retransmission in transmit mode ⎯ Direct convention and inverse convention both supported • Built-in baud rate generator allows any bit rate to be selected • Three interrupt sources ⎯ Three interrupt sources (transmit-data-empty, receive-data-full, and transmit/receive-error) that can issue requests independently ⎯ The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC)* or data transfer controller (DTC) to execute data transfer Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 667 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the smart card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend: SCMR: Smart card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 15.1 Block Diagram of Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 668 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.1.3 Pin Configuration Table 15.1 shows the smart card interface pin configuration. Table 15.1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev.6.00 Sep. 27, 2007 Page 669 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.1.4 Register Configuration Table 15.2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI). Table 15.2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W) R R/W R/W R/W R/W R/W 2 R/(W) * 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF *2 H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C 1 R R/W R/W Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 670 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.2 Register Descriptions Registers added with the smart card interface and bits for which the function changes are described here. 15.2.1 Bit Smart Card Mode Register (SCMR) : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : SCMR is an 8-bit readable/writable register that selects the smart card interface function. SCMR is initialized to H'F2 by a reset and in hardware standby mode. In software standby mode and module stop mode it retains its previous state. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev.6.00 Sep. 27, 2007 Page 671 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 15.3.4, Register Settings. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0 SMIF 0 1 Description Smart card interface function is disabled Smart card interface function is enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 672 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.2.2 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in smart card interface mode. Bit 4 ERS 0 Description Indicates data received normally with no error signal [Clearing conditions] • • 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) Indicates an error signal was sent showing detection of a parity error at the receiving side [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Rev.6.00 Sep. 27, 2007 Page 673 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description Indicates transfer in progress [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When the DMAC* or DTC is activated by a TXI interrupt and writes data to TDR (Initial value) Indicates transfer complete [Setting conditions] • • • • • • Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Notes: etu: Elementary time unit (time for transfer of 1 bit) * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 674 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.2.3 Bit Serial Mode Register (SMR) : 7 GM 0 R/W 6 BLK 0 R/W 5 PE* 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * The DMAC is not supported in the H8S/2321. The function of bits 7, 6, 3, and 2 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced, and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation • • 1 • • (Initial value) TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit Clock output on/off control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output on/off control (set by SCR) GSM mode smart card interface mode operation Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Sep. 27, 2007 Page 675 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK 0 Description Normal smart card interface mode operation • • • 1 • • • TXI interrupt generated by TEND flag TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Error signal transmission/detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) (Initial value) Error signal transmission/detection and automatic data retransmission performed Block transfer mode operation Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 3 and 2—Base Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of base clock periods in a 1-bit transfer interval on the smart card interface. Bit 3 BCP1 0 1 Bit 2 BCP0 0 1 0 1 Description 32 clock periods 64 clock periods 372 clock periods 256 clock periods (Initial value) Bits 5, 4, 1, and 0—Operate in the same way as for the normal SCI. For details, see section 14.2.5, Serial Mode Register (SMR). Rev.6.00 Sep. 27, 2007 Page 676 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.2.4 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as being fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 GM SMR SCR Setting CKE1 CKE0 SCK Pin Function See the SCI specification 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin Rev.6.00 Sep. 27, 2007 Page 677 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3 15.3.1 Operation Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. (This does not apply to block transfer mode.) • If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (This does not apply to block transfer mode.) • Only asynchronous communication is supported; there is no synchronous communication function. 15.3.2 Pin Connections Figure 15.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data communication line, the chip’s TxD pin and RxD pin should both be connected to the line, as shown in the figure. The data communication line should be pulled up to the VCC power supply with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Rev.6.00 Sep. 27, 2007 Page 678 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface VCC TxD I/O RxD SCK Rx (port) Chip Connected equipment Data line Clock line Reset line CLK RST IC card Figure 15.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev.6.00 Sep. 27, 2007 Page 679 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3.3 Data Format Normal Transfer Mode: Figure 15.3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Legend: Ds: D0 to D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 15.3 Smart Card Interface Data Format Rev.6.00 Sep. 27, 2007 Page 680 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the data in which the error occurred. Block Transfer Mode: The operation sequence in block transfer mode is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check, but does not output an error signal even if an error has occurred. Since subsequent receive operations cannot be carried out if an error occurs, the error flag must be cleared to 0 before the parity bit for the next frame is received. [5] The transmitting station proceeds to transmit the next data frame. Rev.6.00 Sep. 27, 2007 Page 681 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3.4 Register Settings Table 15.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15.3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 — Bit 6 BLK BRR6 RIE TDR6 RDRF RDR6 — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — Bit 4 O/E BRR4 RE TDR4 ERS RDR4 — Bit 3 BCP1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 BCP0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: — : Unused bit. * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Settings: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator, and bits BCP1 and BCP0 select the number of base clock cycles during transfer of one bit. For details, see section 15.3.5, Clock. The BLK bit is cleared to 0 when using the normal smart card interface mode, and set to 1 when using block transfer mode. BRR Setting: BRR is used to set the bit rate. See section 15.3.5, Clock, for the method of calculating the value to be set. SCR Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 14, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Rev.6.00 Sep. 27, 2007 Page 682 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). • Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. • Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. With the chip, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR should be set to odd parity mode (the same applies to both transmission and reception). Rev.6.00 Sep. 27, 2007 Page 683 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3.5 Clock Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 15.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, the clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B= φ S×2 2n+1 × (N + 1) × 10 6 Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bits/s) φ = Operating frequency (MHz) n = See table 15.4 S = Number of internal clock cycles in 1-bit period set by bits BCP1 and BCP0 Table 15.4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 15.5 Examples of Bit Rate B (bits/s) for Various BRR Settings (When n = 0 and S = 372) φ (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 16.00 19200 9600 6400 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 25.00 33602 16801 11201 Note: Bit rates are rounded to the nearest whole number. Rev.6.00 Sep. 27, 2007 Page 684 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 2n+1 ×B × 10 6 – 1 Table 15.6 Examples of BRR Settings for Bit Rate B (bits/s) (When n = 0 and S = 372) φ (MHz) 7.1424 Bits/s 9600 N 0 Error N 0.00 1 10.00 10.7136 Error N 25 1 13.00 14.2848 Error N 0.00 1 16.00 Error N 12.01 2 18.00 Error N 15.99 2 20.00 Error N 6.60 3 25.00 Error 12.49 Error N 30 1 Error N 8.99 1 Table 15.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (When S = 372) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 Maximum Bit Rate (bits/s) 9600 13441 14400 17473 19200 21505 24194 26882 33602 N 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( φ S×2 2n+1 × B × (N + 1) × 106 – 1) × 100 Rev.6.00 Sep. 27, 2007 Page 685 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3.6 Data Transfer Operations Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE1 and CKE0 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev.6.00 Sep. 27, 2007 Page 686 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 15.4 shows a flowchart for transmitting, and figure 15.5 shows the relation between a transmit operation and the internal registers. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt handling or data transfer by the DMAC* or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag setting timing is shown in figure 15.6. If the DMAC* or DTC is activated by a TXI request, the number of bytes set in the DMAC* or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC* or DTC below. Notes: For details of operation in block transfer mode, see section 14.3.2, Operation in Asynchronous Mode. * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 687 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Start Initialization Start of transmission ERS = 0? Yes No Error handling No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit to 0 End Figure 15.4 Sample Transmission Flowchart Rev.6.00 Sep. 27, 2007 Page 688 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 15.5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu When GM = 1 11.0 etu Legend: Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Note: etu: Elementary time unit (time for transfer of 1 bit) Figure 15.6 TEND Flag Generation Timing in Transmission Rev.6.00 Sep. 27, 2007 Page 689 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 15.7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start of reception ORER = 0 and PER = 0? Yes No Error handling No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.7 Sample Reception Flowchart Rev.6.00 Sep. 27, 2007 Page 690 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface With the above processing, interrupt handling or data transfer by the DMAC* or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. If the DMAC* or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC* or DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DMAC* or DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Notes: For details of operation in block transfer mode, see section 14.3.2, Operation in Asynchronous Mode. * The DMAC is not supported in the H8S/2321. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GSM bit in SMR is set to 1, the clock output can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.8 shows the timing for fixing the clock output. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Rev.6.00 Sep. 27, 2007 Page 691 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 15.8 Timing for Fixing Clock Output Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 15.8. Note: For details of operation in block transfer mode, see section 14.4, SCI Interrupts. Table 15.8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Receive Mode Normal operation Error Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt DTC Source Activation TXI ERI RXI ERI Possible DMAC* Activation Possible Not possible Not possible Possible Possible Not possible Not possible Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 692 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Data Transfer Operation by DMAC* or DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC* or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC* or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC* is not activated. Thus, the number of bytes specified by the SCI and DMAC* are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC* or DTC, it is essential to set and enable the DMAC* or DTC before carrying out SCI setting. For details of the DMAC* and DTC setting procedures, see section 7, DMA Controller*, and section 8, Data Transfer Controller. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC* or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC* or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Notes: For details of operation in block transfer mode, see section 14.4, SCI Interrupts. * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 693 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt the transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state. • When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 15.9 Clock Halt and Restart Procedure Rev.6.00 Sep. 27, 2007 Page 694 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 15.3.8 Operation in Block Transfer Mode Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 14.3.2, Operation in Asynchronous Mode. Data Format: The data format is 8 bits with parity. There is no stop bit, but there is a guard time of 2 or more bits (1 or more bits in reception). Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. Transmit/Receive Clock: Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 15.3.5, Clock. ERS (FER) Flag: As with the normal smart card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0. Rev.6.00 Sep. 27, 2007 Page 695 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface 15.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256 times the transfer rate (determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the base clock. Use of a 372-times clock is illustrated in figure 15.10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.10 Receive Data Sampling Timing in Smart Card Mode (When Using 372-Times Clock) Rev.6.00 Sep. 27, 2007 Page 696 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Thus the receive margin in asynchronous mode is given by the following formula. M =⎥ (0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F – ⎥ D – 0.5⎥ N (1 + F)⎥ × 100% Receive margin (%) Ratio of bit rate to clock (N = 32, 64, 372, 256) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N=372 in the above formula, the receive margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% Rev.6.00 Sep. 27, 2007 Page 697 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 15.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC* or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC* or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Note: * The DMAC is not supported in the H8S/2321. Transfer frame n+1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame (DE) Ds D0 D1 D2 D3 D4 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 15.11 Retransfer Operation in SCI Receive Mode Rev.6.00 Sep. 27, 2007 Page 698 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 15.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DMAC* or DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DMAC* or DTC, the TDRE bit is automatically cleared to 0. Note: * The DMAC is not supported in the H8S/2321. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 15.12 Retransfer Operation in SCI Transmit Mode Rev.6.00 Sep. 27, 2007 Page 699 of 1268 REJ09B0220-0600 Section 15 Smart Card Interface Rev.6.00 Sep. 27, 2007 Page 700 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Section 16 A/D Converter (8 Analog Input Channel Version) 16.1 Overview The chip incorporates a successive-approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected. 16.1.1 Features A/D converter features are listed below • 10-bit resolution • Eight input channels • Settable analog conversion voltage range ⎯ Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage • High-speed conversion ⎯ Minimum conversion time: 6.7 µs per channel (at 20-MHz operation) • Choice of single mode or scan mode ⎯ Single mode: Single-channel A/D conversion ⎯ Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers ⎯ Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start ⎯ Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin • A/D conversion end interrupt generation ⎯ A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion ⎯ The DMA controller (DMAC)* or data transfer controller (DTC) can be activated for data transfer by an interrupt Note: * The DMAC is not supported in the H8S/2321. • Module stop mode can be set ⎯ As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Rev.6.00 Sep. 27, 2007 Page 701 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter. Module data bus Bus interface Internal data bus AVCC Vref AVSS 10-bit D/A converter Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 Multiplexer AN1 AN2 AN3 AN4 AN5 AN6 AN7 + − Comparator Sample-andhold circuit ADI interrupt signal Control circuit ADTRG Conversion start trigger from 8-bit timer or TPU A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Figure 16.1 Block Diagram of A/D Converter Rev.6.00 Sep. 27, 2007 Page 702 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.3 Pin Configuration Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 16.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Group 0 analog inputs Rev.6.00 Sep. 27, 2007 Page 703 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.4 Register Configuration Table 16.2 summarizes the registers of the A/D converter. Table 16.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R 2 R/(W)* Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF Address* H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C 1 R/W R/W Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 704 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.2 16.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 16.3. The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 16.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.6.00 Sep. 27, 2007 Page 705 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] • • 1 • • (Initial value) When 0 is written to the ADF flag after reading ADF = 1 When the DMAC* or DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels [Setting conditions] Note: * The DMAC is not supported in the H8S/2321. Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 706 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description A/D conversion stopped • • (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 16.4, Operation, for details of single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3—Clock Select (CKS): Used together with the CKS1 bit in ADCR to set the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). ADCR3 CKS1 0 1 Bit 3 CKS 0 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 68 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits are used together with the SCAN bit to select the analog input channels. Only set the input channel(s) while conversion is stopped (ADST = 0). Rev.6.00 Sep. 27, 2007 Page 707 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Group Selection CH2 0 Channel Selection CH1 0 1 CH0 0 1 0 1 0 1 1 0 1 Description Single Mode (SCAN = 0) Scan Mode (SCAN = 1) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 16.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — 3 CKS1 1 R/W 2 CH3 1 R/W 1 — 1 — 0 — 1 — Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 1 Bit 6 TRGS0 0 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 708 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. Bit 2—Channel Select 3 (CH3): Reserved. A value of 1 must be written to this bit. 16.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 MSTPCRL 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev.6.00 Sep. 27, 2007 Page 709 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 16.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 16.2 ADDR Access Operation (Reading H'AA40) Rev.6.00 Sep. 27, 2007 Page 710 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 to it after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 16.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the conversion result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev.6.00 Sep. 27, 2007 Page 711 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Set* ADIE A/D conversion starts Set* Set* ADST Clear* ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) ADDRA Read conversion result A/D conversion result 1 Clear* Idle Idle A/D conversion 1 Idle A/D conversion 2 Idle Idle Idle ADDRB Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.6.00 Sep. 27, 2007 Page 712 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 16.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev.6.00 Sep. 27, 2007 Page 713 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Continuous A/D conversion Set*1 ADST Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA A/D conversion result 1 A/D conversion result 4 A/D conversion time Idle A/D conversion 1 Clear*1 Idle A/D conversion 4 Idle Idle A/D conversion 2 Idle A/D conversion 5 *2 Idle Idle A/D conversion 3 Idle Idle ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 16.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev.6.00 Sep. 27, 2007 Page 714 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D conversion timing. Table 16.4 indicates the A/D conversion time. As indicated in figure 16.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16.4. In scan mode, the values given in table 16.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is as shown in table 16.5. (1) φ Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 16.5 A/D Conversion Timing Rev.6.00 Sep. 27, 2007 Page 715 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Table 16.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV Min Typ Max 18 — — 33 CKS = 1 Min Typ Max 4 — 67 — 15 — 5 — 68 CKS1 = 1 CKS = 0 Min Typ Max 10 — — 63 17 — 266 CKS = 1 Min Typ Max 6 — — 31 9 — 134 127 — 530 515 — 259 — 131 — Note: Values in the table are the number of states. Table 16.5 A/D Conversion Time (Scan Mode) CKS1 0 1 CKS 0 1 0 1 Conversion Time (States) 512 (Fixed) 64 (Fixed) 256 (Fixed) 128 (Fixed) 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.6 shows the timing. Rev.6.00 Sep. 27, 2007 Page 716 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) φ ADTRG Internal trigger signal ADST A/D conversion Figure 16.6 External Trigger Input Timing 16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC* can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC* in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16.6. Note: * The DMAC is not supported in the H8S/2321. Table 16.6 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC Activation Possible DMAC Activation* Possible Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 717 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) 16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. 2. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must not be left open. 3. Vref input range The analog reference voltage input at the Vref pin should be set in the range Vref ≤ AVCC. The Vref pin should be set as Vref = VCC when the A/D converter is not used. Do not leave the Vref pin open. If conditions 1, 2, and 3 above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 16.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 16.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed Rev.6.00 Sep. 27, 2007 Page 718 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 μF 100 Ω AN0 to AN7 AVSS Notes: Values are reference values. 1. 10 μF 0.01 μF 2. Rin: Input impedance Figure 16.7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: The chip’s A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 to B'0000000001. (See figure 16.9.) Rev.6.00 Sep. 27, 2007 Page 719 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 to B'1111111111. (See figure 16.9.) • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB. (See figure 16.8.) • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 16.8 A/D Conversion Precision Definitions (1) Rev.6.00 Sep. 27, 2007 Page 720 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16.9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: The chip’s analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. If a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Rev.6.00 Sep. 27, 2007 Page 721 of 1268 REJ09B0220-0600 Section 16 A/D Converter (8 Analog Input Channel Version) Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. Chip Sensor output impedance Max. 5 kΩ Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF A/D converter equivalent circuit 10 kΩ 20 pF Note: Values are reference values. Figure 16.10 Example of Analog Input Circuit Rev.6.00 Sep. 27, 2007 Page 722 of 1268 REJ09B0220-0600 Section 17 D/A Converter Section 17 D/A Converter 17.1 Overview The chip includes an 8-bit resolution D/A converter with from two analog signal output channels. 17.1.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode • Module stop mode can be set ⎯ As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode. Rev.6.00 Sep. 27, 2007 Page 723 of 1268 REJ09B0220-0600 Section 17 D/A Converter 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the D/A converter. Module data bus Internal data bus Vref AVCC DADR0 DA1 DA0 AVSS 8-bit D/A converter DADR1 Control circuit Legend: DACR: D/A control register DADR0, 1: D/A data registers 0, 1 Figure 17.1 Block Diagram of D/A Converter Rev.6.00 Sep. 27, 2007 Page 724 of 1268 REJ09B0220-0600 DACR Bus interface Section 17 D/A Converter 17.1.3 Pin Configuration Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage 17.1.4 Register Configuration Table 17.2 summarizes the registers of the D/A converter. Table 17.2 D/A Converter Registers Channels 0, 1 Name D/A data register 0 D/A data register 1 D/A control register 01 Common Module stop control register Note: * Lower 16 bits of the address. Abbreviation DADR0 DADR1 DACR01 MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C Rev.6.00 Sep. 27, 2007 Page 725 of 1268 REJ09B0220-0600 Section 17 D/A Converter 17.2 17.2.1 Bit Register Descriptions D/A Data Registers 0, 1 (DADR0, DADR1) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : DADR0, DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 17.2.2 Bit D/A Control Registers 01 (DACR01) : 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : DACR01 is a 8-bit readable/writable register that controls the operation of the D/A converter. DACR01 is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 726 of 1268 REJ09B0220-0600 Section 17 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 0 and 1 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 * Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled *: Don’t care If the chip enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. Rev.6.00 Sep. 27, 2007 Page 727 of 1268 REJ09B0220-0600 Section 17 D/A Converter 17.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter channel 0 and 1module stop mode. Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value) 17.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 17.2 shows the timing of this operation. [1] Write the conversion data to DADR0. Rev.6.00 Sep. 27, 2007 Page 728 of 1268 REJ09B0220-0600 Section 17 D/A Converter [2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 × Vref The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin. DADR0 write cycle DACR01 write cycle DADR0 write cycle DACR01 write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 17.2 Example of D/A Converter Operation Rev.6.00 Sep. 27, 2007 Page 729 of 1268 REJ09B0220-0600 Section 17 D/A Converter Rev.6.00 Sep. 27, 2007 Page 730 of 1268 REJ09B0220-0600 Section 18 RAM Section 18 RAM 18.1 Overview The H8S/2329B and H8S/2324S have 32 kbytes of on-chip high-speed static RAM, the H8S/2328 (H8S/2328B in flash memory version), H8S/2327, H8S/2326, H8S/2323, and H8S/2322R have 8 kbytes, and the H8S/2321 and H8S/2320 have 4 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 18.1.1 Block Diagram Figure 18.1 shows a block diagram of 32 kbytes of on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FF7C00 H'FF7C02 H'FF7C04 H'FF7C01 H'FF7C03 H'FF7C05 H'FFFBFE H'FFFBFF Figure 18.1 Block Diagram of RAM (32 kbytes) Rev.6.00 Sep. 27, 2007 Page 731 of 1268 REJ09B0220-0600 Section 18 RAM 18.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of SYSCR. Table 18.1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FF39 Note: * Lower 16 bits of the address. 18.2 18.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 R/W 1 0 R/W 0 RAME 1 R/W LWROD IRQPAS Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 5.2.1, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 732 of 1268 REJ09B0220-0600 Section 18 RAM 18.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. Note: The amount of on-chip RAM differs depending on the product. Refer to section 3.5, Memory Map in Each Operation Mode, for details. 18.4 Usage Note DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0. Rev.6.00 Sep. 27, 2007 Page 733 of 1268 REJ09B0220-0600 Section 18 RAM Rev.6.00 Sep. 27, 2007 Page 734 of 1268 REJ09B0220-0600 Section 19 ROM Section 19 ROM 19.1 Overview The Series has 512, 384, or 256 kbytes of on-chip flash memory, or 256, 128, or 32 kbytes of onchip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the EAE bit in BCRL. The flash memory version of the chip can be erased and programmed with a PROM programmer, as well as on-board. 19.1.1 Block Diagram Figure 19.1 shows a block diagram of 256 kbytes of on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'03FFFE H'03FFFF Figure 19.1 Block Diagram of ROM (256 kbytes) Rev.6.00 Sep. 27, 2007 Page 735 of 1268 REJ09B0220-0600 Section 19 ROM 19.1.2 Register Configuration The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROMrelated registers are shown in table 19.1. Table 19.1 ROM Registers Register Name Mode control register Bus controller register Abbreviation MDCR BCRL R/W R/W R/W Initial Value Undefined Undefined Address* H'FF3B H'FED5 Note: * Lower 16 bits of the address. 19.2 19.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register used to monitor the current operating mode of the chip. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. Rev.6.00 Sep. 27, 2007 Page 736 of 1268 REJ09B0220-0600 Section 19 ROM 19.2.2 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 — 1 R/W 3 DDS 1 R/W 2 — 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*2 are to be internal addresses or external addresses. Description Bit 5 0 H8S/2329B, H8S/2328 , H8S/2326 On-chip ROM *3 H8S/2327 H8S/2323 1 1 Addresses H'010000 to Reserved area* H'01FFFF are on-chip ROM or address H'020000 to H'03FFFF are reserved 1 area* 2 Addresses H'010000 to H'03FFFF* are external addresses in external expanded mode *1 in single-chip mode or reserved area (Initial value) Notes: 1. Do not access a reserved area. 2. Addresses H'010000 to H'05FFFF in the H8S/2329B. Addresses H'010000 to H'07FFFF in the H8S/2326. 3. H8S/2328B in flash memory version. 19.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE bit in BCRL. These settings are shown in tables 19.2 and 19.3. Rev.6.00 Sep. 27, 2007 Page 737 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.2 Operating Modes and ROM (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) Mode Pins Mode 1 2 3 4 5 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled 1 1 0 Operating Mode — FWE 0 MD2 0 MD1 0 1 MD0 1 0 1 0 1 0 0 1 7 Advanced single-chip mode 1 0 1 8 9 10 Boot mode (advanced expanded mode with on-chip 3 ROM enabled)* Boot mode (advanced 4 single-chip mode) * 1 — 1 0 0 0 1 0 0 1 1 0 1 12 13 14 User program mode (advanced expanded mode 3 with on-chip ROM enabled)* User program mode (advanced single-chip 4 mode)* 1 — 1 0 0 1 0 0 1 1 0 1 Enabled 15 (256 kbytes) * * Enabled (64 kbytes) Enabled 15 (256 kbytes) * * Enabled (64 kbytes) — Enabled 25 (256 kbytes) * * Enabled (64 kbytes) Enabled 25 (256 kbytes) * * Enabled (64 kbytes) — — Enabled 15 (256 kbytes)* * Enabled (64 kbytes) Enabled 15 (256 kbytes) * * Enabled (64 kbytes) — — Disabled BCRL EAE — On-Chip ROM — 11 15 Notes: 1. Note that in modes 6, 7, 14, and 15, the on-chip ROM that can be used after a reset is the 64-kbyte area from H'000000 to H'00FFFF. Rev.6.00 Sep. 27, 2007 Page 738 of 1268 REJ09B0220-0600 Section 19 ROM 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. 5. The capacity of on-chip ROM in the H8S/2328B F-ZTAT is 256 kbytes. The capacity of on-chip ROM in the H8S/2326 F-ZTAT is 512 kbytes. Table 19.3 Operating Modes and ROM (H8S/2329B F-ZTAT and Mask ROM Version) Mode Pins Mode 1 3 2* 3 3* BCRL EAE — On-Chip ROM — Operating Mode — MD2 0 MD1 0 1 MD0 1 0 1 0 1 4 5 6 7 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 0 — Disabled 1 0 1 0 1 0 1 12 Enabled (256 kbytes)* * Enabled (64 kbytes) 12 Enabled (256 kbytes)* * Enabled (64 kbytes) Notes: 1. Note that in modes 6 and 7, the on-chip ROM that can be used after a reset is the 64kbyte area from H'000000 to H'00FFFF. 2. The amount of on-chip RAM differs depending on the product. Refer to section 3.5, Memory Map in Each Operation Mode, for details. 3. Boot mode in the H8S/2329B F-ZTAT. See table 19.9, for information on H8S/2329B F-ZTAT user boot modes. See table 19.9, for information on H8S/2329B F-ZTAT user program modes. Rev.6.00 Sep. 27, 2007 Page 739 of 1268 REJ09B0220-0600 Section 19 ROM 19.4 19.4.1 Overview of Flash Memory (H8S/2329B F-ZTAT) Features The H8S/2329B F-ZTAT has 384 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. • Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 50 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed minimum 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. Rev.6.00 Sep. 27, 2007 Page 740 of 1268 REJ09B0220-0600 Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.4.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Flash memory (384 kbytes) Bus interface/controller Operating mode Mode pins Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Figure 19.2 Block Diagram of Flash Memory Rev.6.00 Sep. 27, 2007 Page 741 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. MD1 = 1, MD2 = 1 User mode (on-chip ROM enabled) RES = 0 Reset state RES = 0 RES = 0 MD1 = 1, MD2 = 0 * RES = 0 PROM mode SWE = 1 SWE = 0 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 Figure 19.3 Flash Memory Mode Transitions Rev.6.00 Sep. 27, 2007 Page 742 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory prewrite-erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 19.4 Boot Mode Rev.6.00 Sep. 27, 2007 Page 743 of 1268 REJ09B0220-0600 Section 19 ROM • User program mode 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory Transfer program RAM SCI Chip Boot program Flash memory Transfer program Programming/ erase control program SCI RAM Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory Transfer program Programming/ erase control program Chip SCI RAM Boot program Flash memory Transfer program Programming/ erase control program SCI RAM Flash memory erase New application program Program execution state Figure 19.5 User Program Mode (Example) Rev.6.00 Sep. 27, 2007 Page 744 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.6 Reading Overlap RAM Data in User Mode and User Program Mode Rev.6.00 Sep. 27, 2007 Page 745 of 1268 REJ09B0220-0600 Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program Execution state Application program Figure 19.7 Writing Overlap RAM Data in User Program Mode 19.4.6 Differences between Boot Mode and User Program Mode Table 19.4 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.6.00 Sep. 27, 2007 Page 746 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.7 Block Configuration The flash memory is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes 384 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'5FFFF Figure 19.8 Flash Memory Block Configuration Rev.6.00 Sep. 27, 2007 Page 747 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 19.5. Table 19.5 Flash Memory Pins Pin Name Reset Mode 2 Mode 1 Mode 0 Port 64 Port 65 Port 66 Transmit data Receive data Abbreviation RES MD2 MD1 MD0 P64 P65 P66 TxD1 RxD1 I/O Input Input Input Input Input Input Input Output Input Function Reset Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Serial transmit data output Serial receive data input Rev.6.00 Sep. 27, 2007 Page 748 of 1268 REJ09B0220-0600 Section 19 ROM 19.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.6. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.6 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register 2 RAM emulation register Abbreviation R/W FLMCR1 * 5 FLMCR2 * EBR1* 5 EBR2* SYSCR2 * RAMER 6 5 5 Initial Value 3 Address* H'FFC8* 2 H'FFC9* 2 1 R/W * 3 R/W * R/W * 3 R/W * R/W R/W 3 H'80 H'00 H'00* 4 H'00* H'00 H'00 4 H'FFCA* 2 H'FFCB* H'FF42 H'FEDB 2 Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. 4. If a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 6. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified. Rev.6.00 Sep. 27, 2007 Page 749 of 1268 REJ09B0220-0600 Section 19 ROM 19.5 19.5.1 Bit Register Descriptions Flash Memory Control Register 1 (FLMCR1) : 7 FWE 1 R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Initial value : R/W : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writing to bits ESU, PSU, EV, and PV in FLMCR1 is enabled only when SWE = 1; writing to the E bit is enabled only when SWE = 1, and ESU = 1; and writing to the P bit is enabled only when SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. These bits cannot be modified and are always read as 1 in this model. Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 5 to 0. When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode. Bit 6 SWE 0 1 Description Writes disabled Writes enabled (Initial value) Rev.6.00 Sep. 27, 2007 Page 750 of 1268 REJ09B0220-0600 Section 19 ROM Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When SWE = 1 (Initial value) Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When SWE = 1 (Initial value) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 751 of 1268 REJ09B0220-0600 Section 19 ROM Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE = 1 (Initial value) Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 (Initial value) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 752 of 1268 REJ09B0220-0600 Section 19 ROM 19.5.2 Bit Flash Memory Control Register 2 (FLMCR2) : 7 FLER 0 R 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection (Initial value) Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 753 of 1268 REJ09B0220-0600 Section 19 ROM 19.5.3 Bit EBR1 Erase Block Register 1 (EBR1) : 7 EB7 0 R/W : 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Initial value : R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.7. 19.5.4 Bit EBR2 Initial value : R/W : Erase Block Registers 2 (EBR2) : 7 — 0 — 6 — 0 — 5 EB13 0 R/W 4 EB12 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 and 6 are reserved: they are always read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.7. Rev.6.00 Sep. 27, 2007 Page 754 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.7 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes) EB13 (64 kbytes) Address H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF 19.5.5 Bit System Control Register 2 (SYSCR2) : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 R/W Initial value : R/W : SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 755 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0. Bit 0—Reserved: This bit should not be written with 0. 19.5.6 Bit RAM Emulation Register (RAMER) : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Initial value : R/W : RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 756 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19.8.) Table 19.8 Flash Memory Area Divisions RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don’t care Rev.6.00 Sep. 27, 2007 Page 757 of 1268 REJ09B0220-0600 Section 19 ROM 19.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.9. For a diagram of the transitions to the various flash memory modes, see figure 19.3. Table 19.9 Setting On-Board Programming Modes Mode MCU Mode Boot mode CPU Operating Mode Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode User program mode* Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 MD2 0 Pins MD1 1 MD0 0 1 0 1 Note: * Normally, user mode should be used. Set the SWE bit to 1 to make a transition to user program mode before performing a program/erase/verify operation. Rev.6.00 Sep. 27, 2007 Page 758 of 1268 REJ09B0220-0600 Section 19 ROM 19.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2329B F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in onchip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.9, and the boot program mode execution procedure in figure 19.10. Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 19.9 System Configuration in Boot Mode Rev.6.00 Sep. 27, 2007 Page 759 of 1268 REJ09B0220-0600 Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19.10 Boot Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 760 of 1268 REJ09B0220-0600 Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2329B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.10 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.11 Automatic SCI Bit Rate Adjustment Table 19.10 System Clock Frequencies for which Automatic Adjustment of H8S/2329B F-ZTAT Bit Rate is Possible Host Bit Rate 19,200 bps 9,600 bps System Clock Frequency for which Automatic Adjustment of H8S/2329B F-ZTAT Bit Rate is Possible 16 MHz to 25 MHz 8 MHz to 25 MHz On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FF7C00 to H'FF83FF is reserved for use by the boot program, as shown in figure 19.12. The area to which the programming control program is transferred is H'FF8400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. Rev.6.00 Sep. 27, 2007 Page 761 of 1268 REJ09B0220-0600 Section 19 ROM H'FF7C00 H'FF83FF Boot program area* (2 kbytes) Programming control program area (30 kbytes) H'FFFBFF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.12 RAM Areas in Boot Mode Notes on Use of Boot Mode • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FF8400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1). Rev.6.00 Sep. 27, 2007 Page 762 of 1268 REJ09B0220-0600 Section 19 ROM • The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. • Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19.9 and executing a reset-start. • Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. • Do not change the mode pin input levels in boot mode. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*2. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins input must satisfy the mode programming setup time (tMDS = 200 ns) with respect to the reset release timing. 2. See section 9, I/O Ports. 19.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means supply of programming data, and storing a program/erase control program in part of the program area if necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7). In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Rev.6.00 Sep. 27, 2007 Page 763 of 1268 REJ09B0220-0600 Section 19 ROM Figure 19.13 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area Execute program/erase control program (flash memory rewriting) Branch to flash memory application program Note: The watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Figure 19.13 User Program Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 764 of 1268 REJ09B0220-0600 Section 19 ROM 19.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 19.7.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 19.14 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β ) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the Rev.6.00 Sep. 27, 2007 Page 765 of 1268 REJ09B0220-0600 Section 19 ROM elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 19.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.14) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode in FLMCR1 to 0, and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev.6.00 Sep. 27, 2007 Page 766 of 1268 REJ09B0220-0600 Section 19 ROM Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU bit in FLMCR1 Wait (y) μs Set P bit in FLMCR1 n=1 Wait (z1) μs or (z2) μs or (z3) μs Clear P bit in FLMCR1 Wait (α) μs Clear PSU bit in FLMCR1 Wait (β) μs Disable WDT End sub Note 7: Write Pulse Width Number of Writes (n) Write Time (z) μs 1 z1 2 z1 3 z1 4 z1 5 z1 6 z1 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 . . . . . . 998 z2 999 z2 1000 z2 Note: Use a (z3) µs write pulse for additional programming. RAM Program data area (128 bytes) NG 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait (η) μs 6≥n? NG *6 *6 *6 *6 *5 *6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call Write pulse (z1) μs or (z2) μs Set PV bit in FLMCR1 Wait (γ) μs H'FF dummy write to verify address Increment address Wait (ε) μs Read verify data *6 *2 n←n+1 *6 See Note 7 for pulse width *6 *6 Start of programming Start Set SWE bit in FLMCR1 Wait (x) μs Store 128-byte program data in program data area and reprogram data area *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Read data = verify data? OK 6≥n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area *4 *3 *4 Reprogram data area (128 bytes) Additional program data area (128 bytes) OK Sequentially write 128-byte data in additional program data area in RAM to flash memory *1 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must Write Pulse *6 be performed even if writing fewer than 128 bytes; in this case, H'FF (z3 µs additional write pulse) data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. *6 3. Even bits for which programming has been completed in the 128-byte NG NG m = 0? n ≥ N? programming loop will be subjected to additional programming if they fail the subsequent verify operation. OK OK 4. A 128-byte area for storing program data, a 128-byte area for storing Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and Wait (θ) μs *6 Wait (θ) μs additional program data areas are modified as programming proceeds. 5. A write pulse of (z1) or (z2) μs should be applied according to the progress End of programming Programming failure of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Program Data Operation Chart Original Data Verify Data Reprogram Data Comments (D) (V) (X) 0 0 1 Programming completed 1 0 Programming incomplete; reprogram 1 0 1 1 Still in erased state; no action Additional Program Data Operation Chart Reprogram Data (X') 0 1 Verify Data Additional (V) Program Data (Y) 0 0 1 1 0 1 Comments *6 Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Figure 19.14 Program/Program-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 767 of 1268 REJ09B0220-0600 Section 19 ROM 19.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.15. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 19.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR1 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.6.00 Sep. 27, 2007 Page 768 of 1268 REJ09B0220-0600 Section 19 ROM Start *1 Set SWE bit in FLMCR1 Wait (x) μs n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) μs Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait (α) μs Clear ESU bit in FLMCR1 Wait (β) μs Disable WDT Set EV bit in FLMCR1 Wait (γ) μs Set block start address to verify address *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 n←n+1 H'FF dummy write to verify address Wait (ε) μs Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait (η) μs *2 *2 *3 NG Clear EV bit in FLMCR1 Wait (η) μs *2 *2 NG *5 End of erasing of all erase blocks? OK n ≥ N? OK Clear SWE bit in FLMCR1 Wait (θ) μs Erase failure NG Clear SWE bit in FLMCR1 Wait (θ) μs End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0) is not necessary. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19.15 Erase/Erase-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 769 of 1268 REJ09B0220-0600 Section 19 ROM 19.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.11). Table 19.11 Hardware Protection Functions Item Reset/standby protection Description • In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Program Yes Erase Yes • 19.8.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode (see table 19.12). Rev.6.00 Sep. 27, 2007 Page 770 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.12 Software Protection Functions Item SWE bit protection Description • • Block specification protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation Yes register (RAMER) places all blocks in the program/erase-protected state. Yes — Yes Program Yes Erase Yes • Emulation protection • 19.8.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: • When flash memory is read during programming/erasing (including a vector read or instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction (including software standby) is executed during programming/erasing • When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing Rev.6.00 Sep. 27, 2007 Page 771 of 1268 REJ09B0220-0600 Section 19 ROM Error protection is released only by a reset and in hardware standby mode. Figure 19.16 shows the flash memory state transition diagram. Normal operating mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or STBY = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19.16 Flash Memory State Transitions Rev.6.00 Sep. 27, 2007 Page 772 of 1268 REJ09B0220-0600 Section 19 ROM 19.9 19.9.1 Flash Memory Emulation in RAM Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.17 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.17 Flowchart for Flash Memory Emulation in RAM Rev.6.00 Sep. 27, 2007 Page 773 of 1268 REJ09B0220-0600 Section 19 ROM 19.9.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 Flash memory EB8 to EB13 On-chip RAM H'FFFBFF H'5FFFF H'FFEBFF Figure 19.18 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause Rev.6.00 Sep. 27, 2007 Page 774 of 1268 REJ09B0220-0600 Section 19 ROM a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. • Rev.6.00 Sep. 27, 2007 Page 775 of 1268 REJ09B0220-0600 Section 19 ROM 19.11 Flash Memory PROM Mode 19.11.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.13 shows PROM mode pin settings. Table 19.13 PROM Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: P66, P65, P64 STBY pin RES pin XTAL, EXTAL pins Other pins requiring setting: P32, P25 Settings/External Circuit Connection Low-level input High-level input to P66, low-level input to P65 and P64 High-level input (do not select hardware standby mode) Reset circuit Oscillator circuit High-level input to P32, low-level input to P25 19.11.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figure 19.20. Figure 19.19 shows the on-chip ROM memory map and figure 19.20 shows the socket adapter pin assignments. MCU mode address H'00000000 On-chip ROM space (384 kbytes) H'0005FFFF H'5FFFF PROM mode address H'00000 Figure 19.19 Memory Map in PROM Mode Rev.6.00 Sep. 27, 2007 Page 776 of 1268 REJ09B0220-0600 Section 19 ROM H8S/2329B F-ZTAT TFP-120 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 43 44 45 46 48 49 50 51 68 69 67 72 FP-128B 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 49 50 51 52 54 55 56 57 76 77 75 80 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D8 D9 D10 D11 D12 D13 D14 D15 CE OE WE EMLE*3 VCC Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1, 40 11, 30 5, 6, 7 8 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 Emulation enable Data input/output Address input Chip enable Output enable Write enable 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 6, 15, 24, 31, 32, 38, 3, 10, 19, 28, 35, 36, 47, 59, 66, 79, 103, 37, 38, 44, 53, 65, 104, 113, 114, 115 67, 68, 74, 87, 99, 100, 113, 114, 123, 124, 125 73 81 77 78 Other pins 85 86 VSS *1 RES XTAL EXTAL NC (OPEN) Reset circuit Oscillation circuit *2 9 Legend: EMLE: I/O7 to I/O0: A18 to A0: CE: OE: WE: Notes: 1. A reset oscillation stabilization time (tosc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. 3. As the FWE pin becomes VCC in the H8S/2329B F-ZTAT, the EMLE pin is ignored in PROM mode. This figure shows pin assignments, and does not show the entire socket adapter circuit. Figure 19.20 H8S/2329B F-ZTAT Socket Adapter Pin Assignments Rev.6.00 Sep. 27, 2007 Page 777 of 1268 REJ09B0220-0600 Section 19 ROM 19.11.3 PROM Mode Operation Table 19.14 shows how the different operating modes are set when using PROM mode, and table 19.15 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.14 Settings for Each Operating Mode in PROM Mode Pin Names Mode Read Output disable Command write 1 Chip disable* CE L L L H OE L H H X WE H H L X I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain X Ain* X 2 Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. Rev.6.00 Sep. 27, 2007 Page 778 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.15 PROM Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA PA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.11.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Rev.6.00 Sep. 27, 2007 Page 779 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.16 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Command write A18 to A0 Memory read mode Address stable CE OE WE Data twep tceh tnxtc tces tf tr H'00 tdh tds Data Note: Data is latched at the rising edge of WE. Figure 19.21 Memory Read Mode Timing Waveforms after Command Write Rev.6.00 Sep. 27, 2007 Page 780 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.17 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Memory read mode A18 to A0 CE OE WE Address stable tnxtc Other mode command write tces tceh tf twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 19.22 Timing Waveforms when Entering Another Mode from Memory Read Mode Rev.6.00 Sep. 27, 2007 Page 781 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.18 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns A18 to A0 CE OE WE I/O7 to I/O0 Address stable Address stable VIL VIL VIH tacc tacc toh toh Figure 19.23 Timing Waveforms for CE/OE Enable State Read A18 to A0 CE Address stable tce Address stable tce toe OE WE VIH I/O7 to I/O0 tacc toh tacc tdf toe toh tdf Figure 19.24 Timing Waveforms for CE/OE Clocked Read Rev.6.00 Sep. 27, 2007 Page 782 of 1268 REJ09B0220-0600 Section 19 ROM 19.11.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur. • Memory address transfer is executed in the second cycle (figure 19.25). Do not perform transfer later than the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed. • Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation). • Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev.6.00 Sep. 27, 2007 Page 783 of 1268 REJ09B0220-0600 Section 19 ROM AC Characteristics Table 19.19 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf Min 20 0 0 50 50 70 1 — 0 60 1 — — Max — — — — — — — 150 — — 3000 30 30 Unit µs ns ns ns ns ns ms ns ns ns ms ns ns A18 to A0 tces CE OE tf WE tds I/O7 tdh twep tceh tnxtc Address stable tnxtc tr tas tah Data transfer 1 byte to 128 bytes twsts tspa twrite Programming operation end identification signal I/O6 Programming normal end identification signal I/O5 to I/O0 H'40 H'00 Figure 19.25 Auto-Program Mode Timing Waveforms Rev.6.00 Sep. 27, 2007 Page 784 of 1268 REJ09B0220-0600 Section 19 ROM 19.11.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE . AC Characteristics Table 19.20 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf Min 20 0 0 50 50 70 1 — 100 — — Max — — — — — — — 150 40000 30 30 Unit µs ns ns ns ns ns ms ns ms ns ns Rev.6.00 Sep. 27, 2007 Page 785 of 1268 REJ09B0220-0600 Section 19 ROM A18 to A0 tces CE OE WE tf twep tr tdh tests tspa terase Erase end identification signal Erase normal end confirmation signal tceh tnxtc tnxtc tds I/O7 I/O6 I/O5 to I/O0 H'20 H'20 H'00 Figure 19.26 Auto-Erase Mode Timing Waveforms 19.11.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19.21 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns Rev.6.00 Sep. 27, 2007 Page 786 of 1268 REJ09B0220-0600 Section 19 ROM A18 to A0 tces CE tce OE WE tf twep tr tdh H'71 tf twep tr tdh H'71 toe tdf tceh tnxtc tces tceh tnxtc tnxtc tds I/O7 to I/O0 tds Note: I/O3 and I/O2 are undefined. Figure 19.27 Status Read Mode Timing Waveforms Table 19.22 Status Read Mode Return Commands Pin Name I/O7 Attribute I/O6 I/O5 Programming error I/O4 Erase error I/O3 — I/O2 — I/O1 I/O0 Normal Command end error identification 0 Command error: 1 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 0 — ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O3 and I/O2 are undefined. Rev.6.00 Sep. 27, 2007 Page 787 of 1268 REJ09B0220-0600 Section 19 ROM 19.11.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.23 Status Polling Output Truth Table Pin Names I/O7 I/O6 I/O0 to I/O5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 19.11.9 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 19.24 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 30 10 0 Max — — — Unit ms ms ms tosc1 VCC RES tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/ abnormal end identification tdwn Command acceptance Figure 19.28 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence Rev.6.00 Sep. 27, 2007 Page 788 of 1268 REJ09B0220-0600 Section 19 ROM 19.11.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed. 19.12 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off: When applying or disconnecting VCC power, fix the RES pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Rev.6.00 Sep. 27, 2007 Page 789 of 1268 REJ09B0220-0600 Section 19 ROM Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: When flash memory is programmed or erased, all interrupt requests, including NMI, should be disabled to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev.6.00 Sep. 27, 2007 Page 790 of 1268 REJ09B0220-0600 Section 19 ROM 19.13 Overview of Flash Memory (H8S/2328B F-ZTAT) 19.13.1 Features The H8S/2328B F-ZTAT has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. • Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 50 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed minimum 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. Rev.6.00 Sep. 27, 2007 Page 791 of 1268 REJ09B0220-0600 Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.13.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Flash memory (256 kbytes) Bus interface/controller Operating mode FWE pin Mode pins Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Figure 19.29 Block Diagram of Flash Memory Rev.6.00 Sep. 27, 2007 Page 792 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a resetstart is executed, the chip enters one of the operating modes shown in figure 19.30. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. MD1 = 1, MD2 = 1, FWE = 0 User mode (on-chip ROM enabled) FWE = 0 or SWE = 0 RES = 0 RES = 0 RES = 0 FWE = 1, MD1 = 1, MD2 = 0 * RES = 0 Reset state FWE = 1, SWE = 1 PROM mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 Figure 19.30 Flash Memory Mode Transitions Rev.6.00 Sep. 27, 2007 Page 793 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory prewrite-erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 19.31 Boot Mode Rev.6.00 Sep. 27, 2007 Page 794 of 1268 REJ09B0220-0600 Section 19 ROM • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Figure 19.32 User Program Mode (Example) Rev.6.00 Sep. 27, 2007 Page 795 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.33 Reading Overlap RAM Data in User Mode and User Program Mode Rev.6.00 Sep. 27, 2007 Page 796 of 1268 REJ09B0220-0600 Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program Execution state Application program Figure 19.34 Writing Overlap RAM Data in User Program Mode 19.13.6 Differences between Boot Mode and User Program Mode Table 19.25 Differnces between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.6.00 Sep. 27, 2007 Page 797 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.7 Block Configuration On-chip 256-kbyte flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 64 kbytes 256 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 19.35 Flash Memory Block Configuration Rev.6.00 Sep. 27, 2007 Page 798 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.8 Pin Configuration The flash memory is controlled by means of the pins shown in tables 19.26. Table 19.26 Flash Memory Pins Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port 64 Port 65 Port 66 Transmit data Receive data Abbreviation RES FWE MD2 MD1 MD0 P64 P65 P66 TxD1 RxD1 I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Serial transmit data output Serial receive data input Rev.6.00 Sep. 27, 2007 Page 799 of 1268 REJ09B0220-0600 Section 19 ROM 19.13.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.27. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.27 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register 2 RAM emulation register Abbreviation R/W FLMCR1 * 6 FLMCR2 * EBR1* 6 EBR2* SYSCR2 * RAMER 7 6 6 Initial Value 3 Address* H'FFC8* 2 H'FFC9* H'FFCA* 2 H'FFCB* H'FF42 H'FEDB 2 2 1 R/W * 3 R/W * R/W * 3 R/W * R/W R/W 3 H'00/H'80* H'00 H'00* 5 H'00* H'00 H'00 5 4 Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in FLMCR1. 4. When a high level is input to the FWE pin, the initial value is H'80. 5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 7. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be modified. Rev.6.00 Sep. 27, 2007 Page 800 of 1268 REJ09B0220-0600 Section 19 ROM 19.14 Register Descriptions 19.14.1 Flash Memory Control Register 1 (FLMCR1) Bit : 7 FWE Initial value : R/W : 1/0 R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to bits ESU, PSU, EV, and PV only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 3 to 0. When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode. Rev.6.00 Sep. 27, 2007 Page 801 of 1268 REJ09B0220-0600 Section 19 ROM Bit 6 SWE 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 802 of 1268 REJ09B0220-0600 Section 19 ROM Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 803 of 1268 REJ09B0220-0600 Section 19 ROM 19.14.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 FLER Initial value : R/W : 0 R 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.17.3, Error Protection (Initial value) Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 804 of 1268 REJ09B0220-0600 Section 19 ROM 19.14.3 Erase Block Register 1 (EBR1) Bit EBR1 Initial value : R/W : : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.28. 19.14.4 Erase Block Registers 2 (EBR2) Bit EBR2 Initial value : R/W : : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 to 4 are reserved: they are always read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.28. Rev.6.00 Sep. 27, 2007 Page 805 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.28 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) Address H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF 19.14.5 System Control Register 2 (SYSCR2) Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 806 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. 19.14.6 RAM Emulation Register (RAMER) Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.29. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 807 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (see table 19.29). Table 19.29 Flash Memory Area Divisions RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don’t care Rev.6.00 Sep. 27, 2007 Page 808 of 1268 REJ09B0220-0600 Section 19 ROM 19.15 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.30. For a diagram of the transitions to the various flash memory modes, see figure 19.31. Table 19.30 Setting On-Board Programming Modes Mode MCU Mode Boot mode CPU Operating Mode Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode User program mode* Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 1 FWE 1 MD2 0 Pins MD1 1 MD0 0 1 0 1 Note: * Normally, user mode should be used. Set the FWE pin to 1 to make a transition to user program mode before performing a program/erase/verify operation. 19.15.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2328B F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in onchip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.36, and the boot program mode execution procedure in figure 19.37. Rev.6.00 Sep. 27, 2007 Page 809 of 1268 REJ09B0220-0600 Section 19 ROM Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 19.36 System Configuration in Boot Mode Rev.6.00 Sep. 27, 2007 Page 810 of 1268 REJ09B0220-0600 Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19.37 Boot Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 811 of 1268 REJ09B0220-0600 Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2328B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.31 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.38 Automatic SCI Bit Rate Adjustment Table 19.31 System Clock Frequencies for which Automatic Adjustment of H8S/2328B F-ZTAT Bit Rate is Possible Host Bit Rate 19,200 bps 9,600 bps System Clock Frequencies for which Automatic Adjustment of H8S/2328B F-ZTAT Bit Rate is Possible 16 MHz to 25 MHz 8 MHz to 25 MHz Rev.6.00 Sep. 27, 2007 Page 812 of 1268 REJ09B0220-0600 Section 19 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.39. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFDC00 H'FFE3FF Boot program area* (2 kbytes) Programming control program area (6 kbytes) H'FFFBFF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.39 RAM Areas in Boot Mode Notes on Use of Boot Mode • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board. Rev.6.00 Sep. 27, 2007 Page 813 of 1268 REJ09B0220-0600 Section 19 ROM • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1). • The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. • Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19.30 and executing a reset-start. • Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. • Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins and FWE pin input must satisfy the mode programming setup time (tMDS = 200 ns) with respect to the reset release timing, as shown in figures 19.56 to 19.58. 2. For further information on FWE application and disconnection, see section 19.21, Flash Memory Programming and Erasing Precautions. 3. See section 9, I/O Ports. Rev.6.00 Sep. 27, 2007 Page 814 of 1268 REJ09B0220-0600 Section 19 ROM 19.15.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 19.40 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Rev.6.00 Sep. 27, 2007 Page 815 of 1268 REJ09B0220-0600 Section 19 ROM Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 19.21, Flash Memory Programming and Erasing Precautions. Figure 19.40 User Program Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 816 of 1268 REJ09B0220-0600 Section 19 ROM 19.16 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for the on-chip ROM area by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 19.16.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 19.42 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Rev.6.00 Sep. 27, 2007 Page 817 of 1268 REJ09B0220-0600 Section 19 ROM Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β ) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 19.16.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.41) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0, and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev.6.00 Sep. 27, 2007 Page 818 of 1268 REJ09B0220-0600 Section 19 ROM Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU bit in FLMCR1 Wait (y) μs Set P bit in FLMCR1 n=1 Wait (z1) μs or (z2) μs or (z3) μs Clear P bit in FLMCR1 Wait (α) μs Clear PSU bit in FLMCR1 Wait (β) μs Disable WDT End sub Note 7: Write Pulse Width *6 Number of Writes (n) Write Time (z) μs 1 z1 2 z1 3 z1 4 z1 5 z1 6 z1 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 . . . . . . 998 z2 999 z2 1000 z2 Note: Use a (z3) µs write pulse for additional programming. RAM Program data area (128 bytes) 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait (η) μs 6≥n? NG *6 *6 *6 *5 *6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call Write pulse (z1) μs or (z2) μs Set PV bit in FLMCR1 Wait (γ) μs H'FF dummy write to verify address Increment address Wait (ε) μs Read verify data *6 *2 n←n+1 *6 See Note 7 for pulse width *6 *6 Start of programming Start Set SWE bit in FLMCR1 Wait (x) μs Store 128-byte program data in program data area and reprogram data area *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Read data = verify data? OK 6≥n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area *4 *3 *4 NG Reprogram data area (128 bytes) Additional program data area (128 bytes) OK Sequentially write 128-byte data in additional program data area in RAM to flash memory *1 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must Write Pulse *6 be performed even if writing fewer than 128 bytes; in this case, H'FF (z3) µs additional write pulse data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. *6 NG NG 3. Even bits for which programming has been completed in the 128-byte m = 0? n ≥ N? programming loop will be subjected to additional programming if they fail OK OK the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 reprogram data, and a 128-byte area for storing additional program data Wait (θ) μs Wait (θ) μs should be provided in RAM. The contents of the reprogram data and *6 additional program data areas are modified as programming proceeds. End of programming Programming failure 5. A write pulse of (z1) or (z2) μs should be applied according to the progress of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Program Data Operation Chart Original Data Verify Data Reprogram Data (D) (V) (X) 0 1 0 1 0 1 1 0 1 Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Additional Program Data Operation Chart Reprogram Data (X') 0 1 Verify Data Additional (V) Program Data (Y) 0 0 1 1 0 1 Comments *6 Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Figure 19.41 Program/Program-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 819 of 1268 REJ09B0220-0600 Section 19 ROM 19.16.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.43. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 19.16.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR1 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.6.00 Sep. 27, 2007 Page 820 of 1268 REJ09B0220-0600 Section 19 ROM Start *1 Set SWE bit in FLMCR1 Wait (x) μs n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) μs Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait (α) μs Clear ESU bit in FLMCR1 Wait (β) μs Disable WDT Set EV bit in FLMCR1 Wait (γ) μs Set block start address to verify address *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 n←n+1 H'FF dummy write to verify address Wait (ε) μs Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait (η) μs *2 *2 *3 NG Clear EV bit in FLMCR1 Wait (η) μs *2 *2 NG *5 End of erasing of all erase blocks? OK n ≥ N? OK Clear SWE bit in FLMCR1 Wait (θ) μs Erase failure NG Clear SWE bit in FLMCR1 Wait (θ) μs End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0) is not necessary. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19.42 Erase/Erase-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 821 of 1268 REJ09B0220-0600 Section 19 ROM 19.17 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.17.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.10). Table 19.32 Hardware Protection Functions Item FWE pin protection Description • Program Erase Yes Yes When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Yes Reset/standby protection • Yes • 19.17.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode (see table 19.33). Rev.6.00 Sep. 27, 2007 Page 822 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.33 Software Protection Functions Item SWE bit protection Description • • Block specification protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory.) Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation Yes register (RAMER) places all blocks in the program/erase-protected state. Yes — Yes Program Yes Erase Yes • Emulation protection • 19.17.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: • When flash memory is read during programming/erasing (including a vector read or instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction (including software standby) is executed during programming/erasing • When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing Rev.6.00 Sep. 27, 2007 Page 823 of 1268 REJ09B0220-0600 Section 19 ROM Error protection is released only by a reset and in hardware standby mode. Figure 19.43 shows the flash memory state transition diagram. Normal operating mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or STBY = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19.43 Flash Memory State Transitions Rev.6.00 Sep. 27, 2007 Page 824 of 1268 REJ09B0220-0600 Section 19 ROM 19.18 Flash Memory Emulation in RAM 19.18.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.44 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.44 Flowchart for Flash Memory Emulation in RAM Rev.6.00 Sep. 27, 2007 Page 825 of 1268 REJ09B0220-0600 Section 19 ROM 19.18.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 Flash memory EB8 to EB11 On-chip RAM H'FFFBFF H'3FFFF H'FFEBFF Figure 19.45 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. Rev.6.00 Sep. 27, 2007 Page 826 of 1268 REJ09B0220-0600 Section 19 ROM 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.19 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. • Rev.6.00 Sep. 27, 2007 Page 827 of 1268 REJ09B0220-0600 Section 19 ROM 19.20 Flash Memory PROM Mode 19.20.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.34 shows PROM mode pin settings. Table 19.34 PROM Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: P66, P65, P64 FWE pin STBY pin RES pin XTAL, EXTAL pins Other pins requiring setting: P32, P25 Settings/External Circuit Connection Low-level input High-level input to P66, low-level input to P65 and P64 High-level input (in auto-program and auto-erase modes) High-level input (do not select hardware standby mode) Reset circuit Oscillator circuit High-level input to P32, low-level input to P25 Rev.6.00 Sep. 27, 2007 Page 828 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figure 19.47. Figure 19.46 shows the on-chip ROM memory map and figure 19.47 shows the socket adapter pin assignments. MCU mode address H'00000000 On-chip ROM space 256 kbytes H'0003FFFF H'3FFFF PROM mode address H'00000 Figure 19.46 Memory Map in PROM Mode Rev.6.00 Sep. 27, 2007 Page 829 of 1268 REJ09B0220-0600 Section 19 ROM H8S/2328B F-ZTAT TFP-120 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 43 44 45 46 48 49 50 51 68 69 67 72 FP-128B 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 49 50 51 52 54 55 56 57 76 77 75 80 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D8 D9 D10 D11 D12 D13 D14 D15 CE OE WE FWE VCC Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1, 40 11, 30 5, 6, 7 8 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 Flash write enable Data input/output Address input Chip enable Output enable Write enable 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 6, 15, 24, 31, 32, 38, 3, 10, 19, 28, 35, 36, 47, 59, 66, 79, 103, 37, 38, 44, 53, 65, 104, 113, 114, 115 67, 68, 74, 87, 99, 100, 113, 114, 123, 124, 125 73 81 9 Legend: *1 FWE: Reset circuit RES I/O7 to I/O0: 77 85 XTAL A18 to A0: *2 Oscillation circuit CE: 78 86 EXTAL OE: Other pins NC (OPEN) WE: Notes: This figure shows pin assignments, and does not show the entire socket adapter circuit. 1. A reset oscillation stabilization time (tosc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. VSS Figure 19.47 H8S/2328B F-ZTAT Socket Adapter Pin Assignments Rev.6.00 Sep. 27, 2007 Page 830 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.3 PROM Mode Operation Table 19.35 shows how the different operating modes are set when using PROM mode, and table 19.36 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.35 Settings for Each Operating Mode in PROM Mode Pin Names Mode Read Output disable Command write 1 Chip disable* FWE H or L H or L H or L H or L *3 CE L L L H OE L H H X WE H H L X I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain X Ain* X 2 Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. Rev.6.00 Sep. 27, 2007 Page 831 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.36 PROM Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA PA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.20.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Rev.6.00 Sep. 27, 2007 Page 832 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.37 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Command write A18 to A0 Memory read mode Address stable CE OE WE Data twep tceh tnxtc tces tf tr H'00 tdh tds Data Note: Data is latched at the rising edge of WE. Figure 19.48 Memory Read Mode Timing Waveforms after Command Write Rev.6.00 Sep. 27, 2007 Page 833 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.38 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Memory read mode A18 to A0 CE OE WE Address stable tnxtc Other mode command write tces tceh tf twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 19.49 Timing Waveforms when Entering Another Mode from Memory Read Mode Rev.6.00 Sep. 27, 2007 Page 834 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.39 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns A18 to A0 CE OE WE I/O7 to I/O0 Address stable Address stable VIL VIL VIH tacc tacc toh toh Figure 19.50 Timing Waveforms for CE/OE Enable State Read A18 to A0 CE Address stable tce Address stable tce toe OE WE VIH I/O7 to I/O0 tacc toh tacc tdf toe toh tdf Figure 19.51 Timing Waveforms for CE/OE Clocked Read Rev.6.00 Sep. 27, 2007 Page 835 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur. • Memory address transfer is executed in the second cycle (figure 19.52). Do not perform transfer later than the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed. • Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation). • Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev.6.00 Sep. 27, 2007 Page 836 of 1268 REJ09B0220-0600 Section 19 ROM AC Characteristics Table 19.40 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 — 0 60 1 — — 100 100 Max — — — — — — — 150 — — 3000 30 30 — — Unit µs ns ns ns ns ns ms ns ns ns ms ns ns ns ns Rev.6.00 Sep. 27, 2007 Page 837 of 1268 REJ09B0220-0600 Section 19 ROM FWE A18 to A0 tpns tces CE OE tf WE tds I/O7 tdh twep tceh tnxtc Address stable tpnh tnxtc tr tas tah Data transfer 1 byte to 128 bytes twsts tspa twrite Programming operation end identification signal I/O6 Programming normal end identification signal I/O5 to I/O0 H'40 H'00 Figure 19.52 Auto-Program Mode Timing Waveforms 19.20.6 Auto-Erase Mode • • • Auto-erase mode supports only total memory erasing. Do not perform a command write during auto-erasing. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an autoerase operation). Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. • Rev.6.00 Sep. 27, 2007 Page 838 of 1268 REJ09B0220-0600 Section 19 ROM AC Characteristics Table 19.41 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 — 100 — — 100 100 Max — — — — — — — 150 40000 30 30 — — Unit µs ns ns ns ns ns ms ns ms ns ns ns ns FWE A18 to A0 tens tces CE OE WE tf twep tr tdh tests tspa terase Erase end identification signal Erase normal end confirmation signal tenh tceh tnxtc tnxtc tds I/O7 I/O6 I/O5 to I/O0 H'20 H'20 H'00 Figure 19.53 Auto-Erase Mode Timing Waveforms Rev.6.00 Sep. 27, 2007 Page 839 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19.42 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns A18 to A0 tces CE tce OE WE tf twep tr tdh H'71 tf twep tr tdh H'71 toe tdf tceh tnxtc tces tceh tnxtc tnxtc tds I/O7 to I/O0 tds Note: I/O3 and I/O2 are undefined. Figure 19.54 Status Read Mode Timing Waveforms Rev.6.00 Sep. 27, 2007 Page 840 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.43 Status Read Mode Return Commands Pin Name I/O7 Attribute I/O6 I/O5 Programming error I/O4 Erase error I/O3 — I/O2 — I/O1 I/O0 Normal Command end error identification 0 Command error: 1 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 0 — ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O3 and I/O2 are undefined. 19.20.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.44 Status Polling Output Truth Table Pin Names I/O7 I/O6 I/O0 to I/O5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 Rev.6.00 Sep. 27, 2007 Page 841 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.9 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 19.45 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 30 10 0 Max — — — Unit ms ms ms tosc1 VCC RES FWE tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/ abnormal end identification tdwn Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19.55 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence Rev.6.00 Sep. 27, 2007 Page 842 of 1268 REJ09B0220-0600 Section 19 ROM 19.20.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed. 19.21 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off (see figures 19.56 to 19.58): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (see figures 19.56 to 19.58): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. Rev.6.00 Sep. 27, 2007 Page 843 of 1268 REJ09B0220-0600 Section 19 ROM The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. • Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). • In boot mode, apply and disconnect FWE during a reset. • In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Rev.6.00 Sep. 27, 2007 Page 844 of 1268 REJ09B0220-0600 Section 19 ROM Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev.6.00 Sep. 27, 2007 Page 845 of 1268 REJ09B0220-0600 Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ tOSC1 VCC Min 0 μs FWE tMDS*3 Min 0 μs MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.56 Power-On/Off Timing (Boot Mode) Rev.6.00 Sep. 27, 2007 Page 846 of 1268 REJ09B0220-0600 Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ tOSC1 VCC Min 0 μs FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.57 Power-On/Off Timing (User Program Mode) Rev.6.00 Sep. 27, 2007 Page 847 of 1268 REJ09B0220-0600 Section 19 ROM Programming/erasing possible Programming/erasing possible Programming/erasing possible Programming/erasing possible Wait time: 100 μs Wait time: 100 μs Wait time: 100 μs φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode Wait time: x SWE bit SWE cleared Mode User change*1 mode Wait time: x User program mode Wait time: x User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200 ns is necessary with respect to RES clearance timing. 3. See section 22.2.6, Flash Memory Characteristics. Figure 19.58 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode) Rev.6.00 Sep. 27, 2007 Page 848 of 1268 REJ09B0220-0600 Wait time: x Wait time: 100 μs Section 19 ROM 19.22 Overview of Flash Memory (H8S/2326 F-ZTAT) 19.22.1 Features The H8S/2326 F-ZTAT has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. • Programming/erase times The flash memory programming time is 10.0 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 μs (typ.) per byte, and the erase time is 50 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed minimum 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. Rev.6.00 Sep. 27, 2007 Page 849 of 1268 REJ09B0220-0600 Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.22.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Flash memory (512 kbytes) Bus interface/controller Operating mode FWE pin Mode pins Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Figure 19.59 Block Diagram of Flash Memory Rev.6.00 Sep. 27, 2007 Page 850 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a resetstart is executed, the chip enters one of the operating modes shown in figure 19.60. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. MD1 = 1, MD2 = 1, FWE = 0 User mode (on-chip ROM enabled) FWE = 0 or SWE = 0 RES = 0 RES = 0 RES = 0 FWE = 1, MD1 = 1, MD2 = 0 * RES = 0 Reset state FWE = 1, SWE = 1 PROM mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 Figure 19.60 Flash Memory Mode Transitions Rev.6.00 Sep. 27, 2007 Page 851 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program Chip Boot program Flash memory RAM SCI Chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Boot program Flash memory RAM Boot program area Flash memory prewrite-erase Programming control program Chip SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 19.61 Boot Mode Rev.6.00 Sep. 27, 2007 Page 852 of 1268 REJ09B0220-0600 Section 19 ROM • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Boot program Flash memory FWE assessment program Chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Figure 19.62 User Program Mode (Example) Rev.6.00 Sep. 27, 2007 Page 853 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.63 Reading Overlap RAM Data in User Mode and User Program Mode Rev.6.00 Sep. 27, 2007 Page 854 of 1268 REJ09B0220-0600 Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program Execution state Application program Figure 19.64 Writing Overlap RAM Data in User Program Mode 19.22.6 Differences between Boot Mode and User Program Mode Table 19.46 Differnces between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.6.00 Sep. 27, 2007 Page 855 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.7 Block Configuration On-chip 512-kbyte flash memory is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'000000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes 512 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'07FFFF Figure 19.65 Flash Memory Block Configuration Rev.6.00 Sep. 27, 2007 Page 856 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.8 Pin Configuration The flash memory is controlled by means of the pins shown in tables 19.47. Table 19.47 Flash Memory Pins Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port 64 Port 65 Port 66 Transmit data Receive data Abbreviation RES FWE MD2 MD1 MD0 P64 P65 P66 TxD1 RxD1 I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Sets MCU operating mode in PROM mode Serial transmit data output Serial receive data input Rev.6.00 Sep. 27, 2007 Page 857 of 1268 REJ09B0220-0600 Section 19 ROM 19.22.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.48. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.48 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register 2 RAM emulation register Abbreviation R/W FLMCR1 * 6 FLMCR2 * EBR1* 6 EBR2* SYSCR2 * RAMER 7 6 6 Initial Value 3 Address* H'FFC8* 2 H'FFC9* H'FFCA* 2 H'FFCB* H'FF42 H'FEDB 2 2 1 R/W * 3 R/W * R/W * 3 R/W * R/W R/W 3 H'00/H'80* H'00 H'00* 5 H'00* H'00 H'00 5 4 Notes: 1. Lower 16 bits of the address. 2. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in FLMCR1. 4. When a high level is input to the FWE pin, the initial value is H'80. 5. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, bits EB11 to EB0 are initialized to 0, and if the SWE2 bit is not set, bits EB15 to EB12 are initialized to 0. 6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 7. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified. Rev.6.00 Sep. 27, 2007 Page 858 of 1268 REJ09B0220-0600 Section 19 ROM 19.23 Register Descriptions 19.23.1 Flash Memory Control Register 1 (FLMCR1) Bit : 7 FWE Initial value : R/W : 1/0 R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the EV1 or PV1 bit. Program mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. The initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE1 bit in FLMCR1 are valid only when FWE = 1; writes to the ESU1, PSU1, EV1, and PV1 bits only when FWE = 1 and SWE1 = 1; writes to the E1 bit only when FWE = 1, SWE1 = 1, and ESU1 = 1; and writes to the P1 bit only when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming and erasing for addresses H'000000 to H'03FFFF. This bit should be set when setting bits 5 to 0 in FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 3 to 0. When SWE1 = 1, the flash memory can only be read in program-verify or erase-verify mode. Rev.6.00 Sep. 27, 2007 Page 859 of 1268 REJ09B0220-0600 Section 19 ROM Bit 6 SWE1 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1, SWE1 = 1 (Initial value) Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1, SWE1 = 1 (Initial value) Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1, SWE1 = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 860 of 1268 REJ09B0220-0600 Section 19 ROM Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1, SWE1 = 1 (Initial value) Bit 1—Erase 1 (E1): Selects erase mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 E1 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 (Initial value) Bit 0—Program 1 (P1): Selects program mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 861 of 1268 REJ09B0220-0600 Section 19 ROM 19.23.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 FLER Initial value : R/W : 0 R 6 SWE2 0 R/W 5 ESU2 0 R/W 4 PSU2 0 R/W 3 EV2 0 R/W 2 PV2 0 R/W 1 E2 0 R/W 0 P2 0 R/W FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the EV2 or PV2 bit. Program mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the PSU2 bit, and finally setting the P2 bit. Erase mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the ESU2 bit, and finally setting the E2 bit. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE2 bit in FLMCR2 are valid only when FWE = 1; writes to the ESU2, PSU2, EV2, and PV2 bits only when FWE = 1 and SWE2 = 1; writes to the E2 bit only when FWE = 1, SWE2 = 1, and ESU2 = 1; and writes to the P2 bit only when FWE = 1, SWE2 = 1, and PSU2 = 1. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.26.3, Error Protection (Initial value) Rev.6.00 Sep. 27, 2007 Page 862 of 1268 REJ09B0220-0600 Section 19 ROM Bit 6—Software Write Enable Bit 2 (SWE2): Enables or disables flash memory programming and erasing for addresses H'040000 to H'07FFFF. This bit should be set when setting bits 5 to 0 in FLMCR2, and EBR2 bits 7 to 4. When SWE2 = 1, the flash memory can only be read in program-verify or erase-verify mode. Bit 6 SWE2 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5—Erase Setup Bit 2 (ESU2): Prepares for a transition to erase mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, PSU2, EV2, PV2, E2, or P2 bit at the same time. Bit 5 ESU2 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1, SWE2 = 1 (Initial value) Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, EV2, PV2, E2, or P2 bit at the same time. Bit 4 PSU2 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1, SWE2 = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 863 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3 EV2 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1, SWE2 = 1 (Initial value) Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, EV2, E2, or P2 bit at the same time. Bit 2 PV2 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1, SWE2 = 1 (Initial value) Bit 1—Erase 2 (E2): Selects erase mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, EV2, PV2, or P2 bit at the same time. Bit 1 E2 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE2 = 1, and ESU2 = 1 (Initial value) Rev.6.00 Sep. 27, 2007 Page 864 of 1268 REJ09B0220-0600 Section 19 ROM Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF. Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time. Bit 0 P2 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE2 = 1, and PSU2 = 1 (Initial value) 19.23.3 Erase Block Register 1 (EBR1) Bit EBR1 Initial value : R/W : : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set when a high level is being input to the FWE pin. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19.49 Rev.6.00 Sep. 27, 2007 Page 865 of 1268 REJ09B0220-0600 Section 19 ROM 19.23.4 Bit EBR2 Erase Block Registers 2 (EBR2) : 7 EB15 0 R/W : 6 EB14 0 R/W 5 EB13 0 R/W 4 EB12 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Initial value : R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block. Bits 3 to 0 in EBR2 are initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is being input to the FWE pin, and when the SWE1 bit in FLMCR1 is not set when a high level is being input to the FWE pin. Bits 7 to 4 are initialized to 0 when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE2 bit in FLMCR2 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.49. Rev.6.00 Sep. 27, 2007 Page 866 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.49 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) EB12 (64 kbytes) EB13 (64 kbytes) EB14 (64 kbytes) EB15 (64 kbytes) Address H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF H'040000 to H'04FFFF H'050000 to H'05FFFF H'060000 to H'06FFFF H'070000 to H'07FFFF 19.23.5 System Control Register 2 (SYSCR2) Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 867 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. 19.23.6 RAM Emulation Register (RAMER) Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.50. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Sep. 27, 2007 Page 868 of 1268 REJ09B0220-0600 Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM (see table 19.50). Table 19.50 Flash Memory Area Divisions RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don’t care Rev.6.00 Sep. 27, 2007 Page 869 of 1268 REJ09B0220-0600 Section 19 ROM 19.24 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.51. For a diagram of the transitions to the various flash memory modes, see figure 19.59. Table 19.51 Setting On-Board Programming Modes Mode MCU Mode Boot mode CPU Operating Mode Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode User program mode* Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 1 FWE 1 MD2 0 Pins MD1 1 MD0 0 1 0 1 Note: * Normally, user mode should be used. Set the FWE pin to 1 to make a transition to user program mode before performing a program/erase/verify operation. 19.24.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2326 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.66, and the boot program mode execution procedure in figure 19.67. Rev.6.00 Sep. 27, 2007 Page 870 of 1268 REJ09B0220-0600 Section 19 ROM Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 19.66 System Configuration in Boot Mode Rev.6.00 Sep. 27, 2007 Page 871 of 1268 REJ09B0220-0600 Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19.67 Boot Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 872 of 1268 REJ09B0220-0600 Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2326 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19.52 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19.68 Automatic SCI Bit Rate Adjustment Table 19.52 System Clock Frequencies for which Automatic Adjustment of H8S/2326 F-ZTAT Bit Rate is Possible Host Bit Rate 19,200 bps 9,600 bps System Clock Frequency for which Automatic Adjustment of H8S/2326 F-ZTAT Bit Rate is Possible 16 MHz to 25 MHz 8 MHz to 25 MHz Rev.6.00 Sep. 27, 2007 Page 873 of 1268 REJ09B0220-0600 Section 19 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.69. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFDC00 H'FFE3FF Boot program area* (2 kbytes) Programming control program area (6 kbytes) H'FFFBFF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.69 RAM Areas in Boot Mode Notes on Use of Boot Mode • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. Rev.6.00 Sep. 27, 2007 Page 874 of 1268 REJ09B0220-0600 Section 19 ROM • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1). • The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19.51 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode. Do not make the FWE pin low level while a boot program is executing, or while programming or erasing flash memory*2. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Input to the mode pins and FWE pin must satisfy the mode programming setup time (tMDS = 200 ns) requirement with regard to the reset release timing, as shown in figures 19.86 to 19.88. 2. Refer to section 19.30, Flash Memory Programming and Erasing Precautions, for precautions regarding applying signals to and releasing the FWE pin. 3. See section 9, I/O Ports. Rev.6.00 Sep. 27, 2007 Page 875 of 1268 REJ09B0220-0600 Section 19 ROM 19.24.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board programming of the on-chip flash memory can be carried out by providing ahead of time an on-board FWE control means to supply programming data, and storing a program/erase control program in part of the program area if necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7) and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. While the SWE1 bit is set to 1 to perform programming or erasing for the addresses H'000000 to H'03FFFF, this address area cannot be read. While the SWE2 bit is set to 1 to perform programming or erasing for the addresses H'040000 to H'07FFFF, this address area cannot be read. The control program that performs programming and erasing should be run in on-chip RAM or flash memory except for the above address areas. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 19.70 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Rev.6.00 Sep. 27, 2007 Page 876 of 1268 REJ09B0220-0600 Section 19 ROM Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand MD2, MD1, MD0 = 101 or 111 Reset start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high* Execute programming/erase control program (flash memory rewriting) Clear FWE* Branch to application program in flash memory Notes: Do not apply a constant high level to the FWE pin. A high level should be applied to the FWE pin only when programming or erasing flash memory. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 19.30, Flash Memory Programming and Erasing Precautions. Figure 19.70 Example of User Program Mode Execution Procedure Rev.6.00 Sep. 27, 2007 Page 877 of 1268 REJ09B0220-0600 Section 19 ROM 19.25 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for addresses H'000000 to H'03FFFF by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1, and for addresses H'040000 to H'07FFFF by setting the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM, external memory, or flash memory except for the above address areas. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 bits in FLMCR1 or setting/resetting of the SWE2, ESU2, PSU2, EV2, PV2, E2, and P2 bits in FLMCR2 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing is not performed when FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 4. Do not program addresses H'000000 to H'03FFFF and H'040000 to H'07FFFF simultaneously. Operation is not guaranteed when programming is performed simultaneously. 19.25.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) Follow the procedure shown in the program/program-verify flowchart in figure 19.70 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. Rev.6.00 Sep. 27, 2007 Page 878 of 1268 REJ09B0220-0600 Section 19 ROM Following the elapse of (x) µs or more after the SWEn bit is set to 1 in flash memory control register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β ) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the Pn bit in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 19.25.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the Pn bit in FLMCRn is cleared to 0, then the PSUn bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.70) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode and wait for at least (η) µs, then clear the SWEn bit in FLMCRn to 0, and wait again for at least (θ) μs. If reprogramming is necessary, set program mode again, and repeat the program/programverify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev.6.00 Sep. 27, 2007 Page 879 of 1268 REJ09B0220-0600 Section 19 ROM Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU1 (2) bit in FLMCR1 (2) Wait (y) μs Set P1 (2) bit in FLMCR1 (2) n=1 Wait (z1) μs or (z2) μs or (z3) μs Clear P1 (2) bit in FLMCR1 (2) Wait (α) μs Clear PSU1 (2) bit in FLMCR1 (2) Wait (β) μs Disable WDT End sub *6 Note 7: Write Pulse Width Number of Writes (n) Write Time (z) μs 1 z1 2 z1 3 z1 4 z1 5 z1 6 z1 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 . . . . . . 998 z2 999 z2 1000 z2 Note: Use a (z3) µs write pulse for additional programming. RAM Program data area (128 bytes) 128-byte data verification completed? OK Clear PV1 (2) bit in FLMCR1 (2) Wait (η) μs 6≥n? NG *6 *6 *6 *5 *6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call Write pulse (z1) μs or (z2) μs Set PV1 (2) bit in FLMCR1 (2) Wait (γ) μs H'FF dummy write to verify address Increment address Wait (ε) μs Read verify data *6 *2 n←n+1 *6 See Note 7 for pulse width *6 *6 Start of programming Start Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs Store 128-byte program data in program data area and reprogram data area *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Read data = verify data? OK 6≥n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area *4 *3 *4 NG Reprogram data area (128 bytes) Additional program data area (128 bytes) OK Sequentially write 128-byte data in additional program data area in RAM to flash memory *1 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must Write Pulse *6 be performed even if writing fewer than 128 bytes; in this case, H'FF (z3) µs additional write pulse data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. *6 NG NG 3. Even bits for which programming has been completed in the 128-byte m = 0? n ≥ N? programming loop will be subjected to additional programming if they fail the subsequent verify operation. OK OK 4. A 128-byte area for storing program data, a 128-byte area for storing Clear SWE1 (2) bit in FLMCR1 (2) Clear SWE1 (2) bit in FLMCR1 (2) reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and Wait (θ) μs Wait (θ) μs *6 additional program data areas are modified as programming proceeds. 5. A write pulse of (z1) or (z2) μs should be applied according to the progress End of programming Programming failure of programming. See Note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics. Program Data Operation Chart Original Data Verify Data Reprogram Data (D) (V) (X) 0 1 0 1 0 1 1 0 1 Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Additional Program Data Operation Chart Reprogram Data (X') 0 1 Verify Data Additional (V) Program Data (Y) 0 0 1 1 0 1 Comments *6 Additional programming executed Additional programming not executed Additional programming not executed Additional programming not executed Figure 19.71 Program/Program-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 880 of 1268 REJ09B0220-0600 Section 19 ROM 19.25.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.71. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWEn bit to 1 in flash memory control register n (FLMCRn). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during which the En bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. Rev.6.00 Sep. 27, 2007 Page 881 of 1268 REJ09B0220-0600 Section 19 ROM 19.25.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is cleared to 0, then the ESUn bit in FLMCRn is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β ) µs or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWEn bit in FLMCRn to 0 and wait for at least (θ) μs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.6.00 Sep. 27, 2007 Page 882 of 1268 REJ09B0220-0600 Section 19 ROM Start *1 Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs n=1 Set EBR1, EBR2 Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait (y) μs Set E1 (2) bit in FLMCR1 (2) Wait (z) ms Clear E1 (2) bit in FLMCR1(2) Wait (α) μs Clear ESU1 (2) bit in FLMCR1 (2) Wait (β) μs Disable WDT Set EV1 (2) bit in FLMCR1 (2) Wait (γ) μs Set block start address to verify address *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 n←n+1 H'FF dummy write to verify address Wait (ε) μs Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV1 (2) bit in FLMCR1 (2) Wait (η) μs *2 *2 *3 NG Clear EV1 (2) bit in FLMCR1 (2) Wait (η) μs *2 *2 NG *5 End of erasing of all erase blocks? OK n ≥ N? NG Clear SWE1 (2) bit in FLMCR1 (2) Wait (θ) μs End of erasing Notes: 1. 2. 3. 4. 5. OK Clear SWE1 (2) bit in FLMCR1 (2) Wait (θ) μs Erase failure Prewriting (setting erase block data to all 0) is not necessary. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19.72 Erase/Erase-Verify Flowchart Rev.6.00 Sep. 27, 2007 Page 883 of 1268 REJ09B0220-0600 Section 19 ROM 19.26 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.26.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.53). Table 19.53 Hardware Protection Functions Item FWE pin protection Description • When a low level is input to the FWE pin, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized and the program/erase protected state is entered. In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in section 22.2.3, AC Characteristics. Program Yes Erase Yes Reset/standby protection • Yes Yes • 19.26.2 Software Protection Software protection can be implemented by setting the SWE1 bit in flash memory control register 1 (FLMCR1), SWE2 bit in FLMCR2 erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in FLMCR1, or the P2 or E2 bit in FLMCR2 does not cause a transition to program mode or erase mode (see table 19.54). Rev.6.00 Sep. 27, 2007 Page 884 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.54 Software Protection Functions Item SWE bit protection Description • Program Erase Yes Clearing the SWE1 bit to 0 in FLMCR1 sets Yes the program/erase-protected state for area H'000000 to H'03FFFF (Execute in on-chip RAM, external memory, or addresses H'040000 to H'07FFFF) Clearing the SWE2 bit to 0 in FLMCR2 sets the program/erase-protected state for area H'040000 to H'07FFFF (Execute in on-chip RAM, external memory, or addresses H'000000 to H'03FFFF) — Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. • Block specification protection • Yes • Emulation protection • Yes 19.26.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or E2 bit. However, PV1, PV2, EV1, and EV2 bit setting is enabled, and a transition can be made to verify mode. Rev.6.00 Sep. 27, 2007 Page 885 of 1268 REJ09B0220-0600 Section 19 ROM FLER bit setting conditions are as follows: • When flash memory is read during programming/erasing (including a vector read or instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction (including software standby) is executed during programming/erasing • When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 19.73 shows the flash memory state transition diagram. Normal operating mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or STBY = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19.73 Flash Memory State Transitions Rev.6.00 Sep. 27, 2007 Page 886 of 1268 REJ09B0220-0600 Section 19 ROM 19.27 Flash Memory Emulation in RAM 19.27.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.74 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.74 Flowchart for Flash Memory Emulation in RAM Rev.6.00 Sep. 27, 2007 Page 887 of 1268 REJ09B0220-0600 Section 19 ROM 19.27.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'000000 EB0 H'001000 EB1 H'002000 EB2 H'030000 EB3 H'004000 EB4 H'005000 EB5 H'006000 EB6 H'007000 EB7 H'008000 H'FFDC00 Flash memory EB8 to EB15 On-chip RAM H'FFFBFF H'07FFFF H'FFEBFF Figure 19.75 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or setting Rev.6.00 Sep. 27, 2007 Page 888 of 1268 REJ09B0220-0600 Section 19 ROM the P2 or E2 bit in FLMCR2 will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.28 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMCR2), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1, or the P2 or E2 bit remains set in FLMCR2. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMCR2.), correct read data will not be obtained (undetermined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. • Rev.6.00 Sep. 27, 2007 Page 889 of 1268 REJ09B0220-0600 Section 19 ROM 19.29 Flash Memory PROM Mode 19.29.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19.55 shows PROM mode pin settings. Table 19.55 PROM Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: P66, P65, P64 FWE pin STBY pin RES pin XTAL, EXTAL pins Other pins requiring setting: P32, P25 Settings/External Circuit Connection Low-level input High-level input to P66, low-level input to P65 and P64 High-level input (in auto-program and auto-erase modes) High-level input (do not select hardware standby mode) Reset circuit Oscillator circuit High-level input to P32, low-level input to P25 Rev.6.00 Sep. 27, 2007 Page 890 of 1268 REJ09B0220-0600 Section 19 ROM 19.29.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figure 19.77. Figure 19.76 shows the on-chip ROM memory map and figure 19.77 shows the socket adapter pin assignments. MCU mode address H'00000000 On-chip ROM space 512 kbytes H'0007FFFF H'7FFFF PROM mode address H'00000 Figure 19.76 Memory Map in PROM Mode Rev.6.00 Sep. 27, 2007 Page 891 of 1268 REJ09B0220-0600 Section 19 ROM H8S/2326 F-ZTAT TFP-120 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 43 44 45 46 48 49 50 51 68 69 67 72 FP-128B 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 49 50 51 52 54 55 56 57 76 77 75 80 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D8 D9 D10 D11 D12 D13 D14 D15 CE OE WE FWE VCC Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1, 40 11, 30 5, 6, 7 8 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 Flash write enable Data input/output Address input Chip enable Output enable Write enable 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 6, 15, 24, 31, 32, 38, 3, 10, 19, 28, 35, 36, 47, 59, 66, 79, 103, 37, 38, 44, 53, 65, 104, 113, 114, 115 67, 68, 74, 87, 99, 100, 113, 114, 123, 124, 125 73 81 9 Legend: *1 FWE: Reset circuit RES I/O7 to I/O0: 77 85 XTAL A18 to A0: *2 Oscillation circuit CE: 78 86 EXTAL OE: Other pins NC (OPEN) WE: Notes: This figure shows pin assignments, and does not show the entire socket adapter circuit. 1. A reset oscillation stabilization time (tosc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. VSS Figure 19.77 H8S/2326 F-ZTAT Socket Adapter Pin Assignments Rev.6.00 Sep. 27, 2007 Page 892 of 1268 REJ09B0220-0600 Section 19 ROM 19.29.3 PROM Mode Operation Table 19.56 shows how the different operating modes are set when using PROM mode, and table 19.57 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.56 Settings for Each Operating Mode in PROM Mode Pin Names Mode Read Output disable Command write 1 Chip disable* FWE H or L H or L H or L H or L *3 CE L L L H OE L H H X WE H H L X I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain X Ain* X 2 Legend: H: High level L: Low level Hi-Z: High impedance X: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. Rev.6.00 Sep. 27, 2007 Page 893 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.57 PROM Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA PA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address PA: Program address Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.29.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Rev.6.00 Sep. 27, 2007 Page 894 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.58 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Command write A18 to A0 Memory read mode Address stable CE OE WE Data twep tceh tnxtc tces tf tr H'00 tdh tds Data Note: Data is latched at the rising edge of WE. Figure 19.78 Memory Read Mode Timing Waveforms after Command Write Rev.6.00 Sep. 27, 2007 Page 895 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.59 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Memory read mode A18 to A0 CE OE WE Address stable tnxtc Other mode command write tces tceh tf twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 19.79 Timing Waveforms when Entering Another Mode from Memory Read Mode Rev.6.00 Sep. 27, 2007 Page 896 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.60 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns A18 to A0 CE OE WE I/O7 to I/O0 Address stable Address stable VIL VIL VIH tacc tacc toh toh Figure 19.80 Timing Waveforms for CE/OE Enable State Read A18 to A0 CE Address stable tce Address stable tce toe OE WE VIH I/O7 to I/O0 tacc toh tacc tdf toe toh tdf Figure 19.81 Timing Waveforms for CE/OE Clocked Read Rev.6.00 Sep. 27, 2007 Page 897 of 1268 REJ09B0220-0600 Section 19 ROM 19.29.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur. • Memory address transfer is executed in the second cycle (figure 19.82). Do not perform transfer later than the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed. • Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-program operation). • Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev.6.00 Sep. 27, 2007 Page 898 of 1268 REJ09B0220-0600 Section 19 ROM AC Characteristics Table 19.61 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 — 0 60 1 — — 100 100 Max — — — — — — — 150 — — 3000 30 30 — — Unit µs ns ns ns ns ns ms ns ns ns ms ns ns ns ns Rev.6.00 Sep. 27, 2007 Page 899 of 1268 REJ09B0220-0600 Section 19 ROM FWE A18 to A0 tpns tces CE OE tf WE tds I/O7 tdh twep tceh tnxtc Address stable tpnh tnxtc tr tas tah Data transfer 1 byte to 128 bytes twsts tspa twrite Programming operation end identification signal I/O6 Programming normal end identification signal I/O5 to I/O0 H'40 H'00 Figure 19.82 Auto-Program Mode Timing Waveforms 19.29.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE . Rev.6.00 Sep. 27, 2007 Page 900 of 1268 REJ09B0220-0600 Section 19 ROM AC Characteristics Table 19.62 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 — 100 — — 100 100 Max — — — — — — — 150 40000 30 30 — — Unit µs ns ns ns ns ns ms ns ms ns ns ns ns Rev.6.00 Sep. 27, 2007 Page 901 of 1268 REJ09B0220-0600 Section 19 ROM FWE A18 to A0 tens tces CE OE WE tf twep tr tdh tests tspa terase Erase end identification signal Erase normal end confirmation signal tenh tceh tnxtc tnxtc tds I/O7 I/O6 I/O5 to I/O0 H'20 H'20 H'00 Figure 19.83 Auto-Erase Mode Timing Waveforms 19.29.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Rev.6.00 Sep. 27, 2007 Page 902 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.63 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns A18 to A0 tces CE tce OE WE tf twep tr tdh H'71 tf twep tr tdh H'71 toe tdf tceh tnxtc tces tceh tnxtc tnxtc tds I/O7 to I/O0 tds Note: I/O3 and I/O2 are undefined. Figure 19.84 Status Read Mode Timing Waveforms Rev.6.00 Sep. 27, 2007 Page 903 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.64 Status Read Mode Return Commands Pin Name I/O7 Attribute I/O6 I/O5 Programming error I/O4 Erase error I/O3 — I/O2 — I/O1 I/O0 Normal Command end error identification 0 Command error: 1 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 0 — ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O3 and I/O2 are undefined. 19.29.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.65 Status Polling Output Truth Table Pin Names I/O7 I/O6 I/O0 to I/O5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 19.29.9 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Rev.6.00 Sep. 27, 2007 Page 904 of 1268 REJ09B0220-0600 Section 19 ROM Table 19.66 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 30 10 0 Max — — — Unit ms ms ms tosc1 VCC RES FWE tbmv Memory read mode Command wait state Command wait state Auto-program mode Auto-erase mode Normal/ abnormal end identification tdwn Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19.85 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence 19.29.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed. Rev.6.00 Sep. 27, 2007 Page 905 of 1268 REJ09B0220-0600 Section 19 ROM 19.30 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off (see figures 19.86 to 19.88): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (see figures 19.86 to 19.88): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. • Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). • In boot mode, apply and disconnect FWE during a reset. • In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1, and SWE2, ESU2, PSU2, EV2, PV2, P2, and E2 bits in FLMCR2 are cleared. Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, E1, and SWE2, ESU2, PSU2, EV2, PV2, P2, and E2 bits are not set by mistake when applying or disconnecting FWE. Rev.6.00 Sep. 27, 2007 Page 906 of 1268 REJ09B0220-0600 Section 19 ROM Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1 or the P2 or E2 bit in FLMCR2, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Notes on setting/clearing of bits SWE1 and SWE2: Do not set or clear the SWE1 bit or SWE2 bit during execution of a program in flash memory. Wait for at least 100 µs after clearing the SWE1 bit or SWE2 bit before executing a program or reading data in flash memory. When the SWE1 bit or SWE2 bit is set, data in flash memory can be rewritten, but flash memory addresses H'000000 to H'03FFFF can only be read in program-verify or erase-verify mode when SWE1 = 1, and flash memory addresses H'040000 to H'07FFFF can only be read in programverify or erase-verify mode when SWE2 = 1. Access the relevant address area in flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE1 bit or SWE2 bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE1 bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Rev.6.00 Sep. 27, 2007 Page 907 of 1268 REJ09B0220-0600 Section 19 ROM Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Programming/ erasing possible Wait time: 100 μs Wait time: x φ tOSC1 VCC Min 0 μs FWE tMDS*3 Min 0 μs MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.86 Power-On/Off Timing (Boot Mode) Rev.6.00 Sep. 27, 2007 Page 908 of 1268 REJ09B0220-0600 Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ tOSC1 VCC Min 0 μs FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE bit SWE cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 22.2.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.87 Power-On/Off Timing (User Program Mode) Rev.6.00 Sep. 27, 2007 Page 909 of 1268 REJ09B0220-0600 Section 19 ROM Programming/erasing possible Programming/erasing possible Programming/erasing possible Programming/erasing possible Wait time: 100 μs Wait time: 100 μs Wait time: 100 μs φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE set Mode change*1 Boot mode Wait time: x SWE bit SWE cleared Mode User change*1 mode Wait time: x User program mode Wait time: x User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200 ns is necessary with respect to RES clearance timing. 3. See section 22.2.6, Flash Memory Characteristics. Figure 19.88 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode) Rev.6.00 Sep. 27, 2007 Page 910 of 1268 REJ09B0220-0600 Wait time: x Wait time: 100 μs Section 20 Clock Pulse Generator Section 20 Clock Pulse Generator 20.1 Overview The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit. In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip. A clock from φ/2 to φ/32 can be selected. 20.1.1 Block Diagram Figure 20.1 shows a block diagram of the clock pulse generator. SCKCR SCK2 to SCK0 DIV EXTAL Oscillator XTAL Duty adjustment circuit Mediumspeed clock divider φ/2 to φ/32 Bus master clock selection circuit System clock to φ pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC* Note: * The DMAC is not supported in the H8S/2321. Figure 20.1 Block Diagram of Clock Pulse Generator Rev.6.00 Sep. 27, 2007 Page 911 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator 20.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration. Table 20.1 Clock Pulse Generator Register Name System clock control register Abbreviation SCKCR R/W R/W Initial Value H'00 Address* H'FF3A Note: * Lower 16 bits of the address. 20.2 20.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 — 0 R/W 5 DIV 0 R/W 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): Controls φ output. Description Bit 7 PSTOP 0 1 Normal Operation φ output (Initial value) Fixed high Sleep Mode φ output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bit 6—Reserved: This bit can be read or written to, but only 0 should be written. Rev.6.00 Sep. 27, 2007 Page 912 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the division ratio. As the frequency of φ changes, the following points must be noted. • The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the guaranteed operation range of clock cycle time tcyc given in the AC timing table in the Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz does not arise. • All internal modules basically operate on φ. Note, therefore, that time processing involving the timers, the SCI, etc., will change when the division ratio changes. The wait time when software standby is cleared will also change in line with a change in the division ratio. • The division ratio can be changed while the chip is operating. The clock output from the φ pin will also change when the division ratio is changed. The frequency of the clock output from the φ pin in this case will be as follows: φ = EXTAL × n Where: EXTAL: Crystal resonator or external clock frequency n: Division ratio (n = φ/2, φ/4, or φ/8) • Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits SCK2 to SCK0. Bit 5 DIV 0 1 Description When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed mode is set (Initial value) When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is supplied to the entire chip Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0, these bits select the medium-speed mode; when the DIV bit is set to 1, they select the division ratio of the clock supplied to the entire chip. Rev.6.00 Sep. 27, 2007 Page 913 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 1 0 1 0 1 0 1 — Description DIV = 0 Bus master is in high-speed mode (Initial value) Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — DIV = 1 Bus master is in high-speed mode (Initial value) Clock supplied to entire chip is φ/2 Clock supplied to entire chip is φ/4 Clock supplied to entire chip is φ/8 — — — 20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20.2. Select the damping resistance Rd according to table 20.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 20.2 Connection of Crystal Resonator (Example) Table 20.2 Damping Resistance Value Frequency (MHz) Rd (Ω) 2 6.8 k 4 500 8 200 12 0 16 0 20 0 25 0 Rev.6.00 Sep. 27, 2007 Page 914 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator Crystal Resonator: Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.3 and the same resonance frequency as the system clock (φ). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 20.3 Crystal Resonator Equivalent Circuit Table 20.3 Crystal Resonator Characteristics Frequency (MHz) RS max (Ω) C0 max (pF) 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 25 40 7 Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B Chip CL2 XTAL EXTAL CL1 Figure 20.4 Example of Incorrect Board Design Rev.6.00 Sep. 27, 2007 Page 915 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator 20.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 20.5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (φ). Table 20.4 and figure 20.6 show the input conditions for the external clock. Rev.6.00 Sep. 27, 2007 Page 916 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator Table 20.4 External Clock Input Conditions VCC = 2.7 V to 3.6 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol tEXL tEXH tEXr tEXf tCL tCH Min 20 20 — — 0.4 80 0.4 80 Max — — 5 5 0.6 — 0.6 — VCC = 3.0 V to 3.6 V Min 10 10 — — 0.4 80 0.4 80 Max — — 5 5 0.6 — 0.6 — Unit ns ns ns ns tcyc ns tcyc ns φ ≥ 5 MHz φ < 5 MHz φ ≥ 5 MHz φ < 5 MHz Figure 22-2 Test Conditions Figure 20.6 EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 20.6 External Clock Input Timing Rev.6.00 Sep. 27, 2007 Page 917 of 1268 REJ09B0220-0600 Section 20 Clock Pulse Generator 20.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 20.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 20.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. Rev.6.00 Sep. 27, 2007 Page 918 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Section 21 Power-Down Modes 21.1 Overview In addition to the normal program execution state, the chip has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The chip operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Sleep mode 4. Module stop mode 5. Software standby mode 6. Hardware standby mode Of these, 2 to 6 are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the chip is in high-speed mode. Table 21.1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode. Rev.6.00 Sep. 27, 2007 Page 919 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Table 21.1 Operating Modes Operating Mode High speed mode Transition Clearing Condition Condition Control register CPU Oscillator Functions Functions High speed Registers Function High speed Modules Registers I/O Ports Function High speed High speed MediumControl speed mode register Sleep mode Module stop mode Software standby mode Hardware standby mode Instruction Control register Instruction External interrupt Interrupt Medium Function speed Halted Retained High/ Function medium 1 speed * High speed Halted Function Retained/ 2 reset * Retained/ 2 reset * Reset Functions Functions High speed Retained High/ Function medium speed Halted Retained Halted Halted Retained Pin Halted Halted Undefined Halted High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. Some SCI registers and the A/D converter are reset, and other on-chip supporting modules retain their states. 21.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21.2 summarizes these registers. Table 21.2 Power-Down Mode Registers Name Standby control register System clock control register Module stop control register H Module stop control register L Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D Note: * Lower 16 bits of the address. Rev.6.00 Sep. 27, 2007 Page 920 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.2 21.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 — 0 — 1 — 0 — 0 IRQ37S 0 R/W Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it. Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction (Initial value) Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 21.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made*. Note: * Except in the F-ZTAT versions. Rev.6.00 Sep. 27, 2007 Page 921 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states* (Initial value) Note: * Not available in the F-ZTAT versions. Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value) Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0. Bit 0—IRQ37 Software Standby Clear Select (IRQ37S): Specifies whether inputs IRQ3 to IRQ7 can be used as software standby mode clearing sources in addition to the usual sources, NMI and IRQ0 to IRQ2 inputs. Bit 0 IRQ37S 0 1 Description Inputs IRQ3 to IRQ7 cannot be used as software standby mode clearing sources (Initial value) Inputs IRQ3 to IRQ7 can be used as software standby mode clearing sources Rev.6.00 Sep. 27, 2007 Page 922 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 — 0 R/W 5 DIV 0 R/W 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): Controls φ output. Description Bit 7 PSTOP 0 1 Normal Operating Mode φ output (Initial value) Fixed high Sleep Mode φ output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bit 6—Reserved: This bit can be read or written to, but only 0 should be written. Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the division ratio. As the frequency of φ changes, the following points must be noted. • The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the guaranteed operation range of clock cycle time tcyc given in the AC timing table in the Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz does not arise. • All internal modules basically operate on φ. Note, therefore, that time processing involving the timers, the SCI, etc., will change when the division ratio changes. The wait time when software standby is cleared will also change in line with a change in the division ratio. Rev.6.00 Sep. 27, 2007 Page 923 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes • The division ratio can be changed while the chip is operating. The clock output from the φ pin will also change when the division ratio is changed. The frequency of the clock output from the φ pin in this case will be as follows: φ = EXTAL × n Where: EXTAL: Crystal resonator or external clock frequency n: Division ratio (n = φ/2, φ/4, or φ/8) • Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits SCK2 to SCK0. Bit 5 DIV 0 1 Description When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed mode is set (Initial value) When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is supplied to the entire chip Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0, these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of the clock supplied to the entire chip. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 1 0 1 0 1 0 1 — Description DIV = 0 Bus master is in high-speed mode (Initial value) Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — DIV = 1 Bus master is in high-speed mode (Initial value) Clock supplied to entire chip is φ/2 Clock supplied to entire chip is φ/4 Clock supplied to entire chip is φ/8 — — — Rev.6.00 Sep. 27, 2007 Page 924 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0—Module Stop (MSTP15 to MSTP0): These bits specify module stop mode. See table 21.3 for the method of selecting on-chip supporting modules. Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set 21.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC* and DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. Rev.6.00 Sep. 27, 2007 Page 925 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21.1 shows the timing for transition to and clearance of medium-speed mode. Note: * The DMAC is not supported in the H8S/2321. Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 21.1 Medium-Speed Mode Transition and Clearance Timing 21.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.6.00 Sep. 27, 2007 Page 926 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.5 21.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained. After reset clearance, all modules other than DMAC* and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Do not make a transition to sleep mode with MSTPCR set to H'FFFF or H'EFFF, as this will halt operation of the bus controller. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 927 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Table 21.3 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module DMA controller (DMAC)* Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) 8-bit timer module Programmable pulse generator (PPG) D/A converter (channels 0 and 1) A/D converter — Serial communication interface (SCI) channel 2 Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 — — — — — Notes: Bits 8 and 4 to 0 can be read or written to, but do not affect operation. * The DMAC is not supported in the H8S/2321. 21.5.2 Usage Notes DMAC*/DTC Module Stop: Depending on the operating status of the DMAC* or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC* or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupts: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. Note: * The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 928 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.6 21.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. See Appendix D, Pin States, for details. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ7*), or by means of the RES pin or STBY pin. Clearing with an Interrupt: When an NMI or IRQ0 to IRQ7* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ7* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Note: * Setting the IRQ37S bit to 1 enables IRQ3 to IRQ7 to be used as software standby mode clearing sources. Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.6.00 Sep. 27, 2007 Page 929 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21.4 Oscillation Stabilization Time Settings 25 20 16 12 10 8 6 4 2 STS2 STS1 STS0 Standby Time MHz MHz MHz MHz MHz MHz MHz MHz MHz 0 0 0 1 1 0 1 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 0.32 0.65 1.3 2.6 0.41 0.82 1.6 3.3 6.6 — 0.8 0.51 0.68 0.8 1.0 2.0 4.1 8.2 — 1.0 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 4.1 8.2 Unit ms 8.2 16.4 10.9 16.4 32.8 131072 states 5.2 262144 states 10.4 Reserved 16 states — 0.6 10.9 13.1 16.4 21.8 32.8 65.5 — 1.3 — 1.6 — 2.0 — 2.7 — 4.0 — 8.0 — µs 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 : Recommended time setting Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended.* Note: * The 16-state standby time cannot be used in the F-ZTAT versions; a standby time of 8192 states or longer should be used. 21.6.4 Software Standby Mode Application Example Figure 21.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Rev.6.00 Sep. 27, 2007 Page 930 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 21.2 Software Standby Mode Application Example 21.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 6.9, Write Data Buffer Function, for details of the write data buffer function. Rev.6.00 Sep. 27, 2007 Page 931 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes 21.7 21.7.1 Hardware Standby Mode Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the chip is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 21.7.2 Hardware Standby Mode Timing Figure 21.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Rev.6.00 Sep. 27, 2007 Page 932 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21.3 Hardware Standby Mode Timing 21.8 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 21.5 shows the state of the φ pin in each processing state. Table 21.5 φ Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode Sleep mode Normal operating state 0 — High impedance High impedance High impedance High impedance Fixed high φ output φ output Fixed high Fixed high 1 0 1 Rev.6.00 Sep. 27, 2007 Page 933 of 1268 REJ09B0220-0600 Section 21 Power-Down Modes Rev.6.00 Sep. 27, 2007 Page 934 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Mask ROM Version (H8S/2328, H8S/2327, H8S/2323) and ROMless Version (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) Absolute Maximum Ratings 22.1.1 Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin Vref AVCC VAN Topr Tstg Value –0.3 to +4.6 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +4.6 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 –55 to +125 Unit V V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Rev.6.00 Sep. 27, 2007 Page 935 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.1.2 DC Characteristics Table 22.2 DC Characteristics (H8S/2328, H8S/2327, H8S/2323) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Schmitt Ports 1, 2, trigger input P6 to P6 4 7 voltage PA4 to PA7 Port 5 (when using IRQ) Input high voltage RES, STBY, NMI, MD2 to MD0 EXTAL Ports 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0 Port 4 VOH VOL | Iin | VIL VIH VCC × 0.9 VCC × 0.7 2.2 — — — VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V Symbol VT VT – + + – Min VCC × 0.2 — Typ — — Max — VCC × 0.7 — Unit V V V Test Conditions VT – VT VCC × 0.07 — 2.2 –0.3 –0.3 — — — AVCC + 0.3 V VCC × 0.1 VCC × 0.2 V V VCC – 0.5 VCC – 1.0 — — — — — — — — — — — — 0.4 10.0 1.0 1.0 V V V μA μA μA IOH = –200 μA IOH = –1 mA IOL = 1.6 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Rev.6.00 Sep. 27, 2007 Page 936 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Test Conditions Vin = 0.5 V to VCC – 0.5 V Item Symbol Min — Typ — Max 1.0 Unit μA Three-state Ports 1, 2, 3, 5, 6, A | ITSI | leakage to G current (off state) Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI Current Normal operation 2 dissipation* Sleep mode Standby mode* Analog power supply voltage Reference power supply voltage During A/D and D/A conversion Idle During A/D and D/A conversion Idle VRAM AICC 3 –Ip 10 — 300 μA VCC = 2.7 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Cin — — — — — — 30 30 15 pF pF pF ICC* 4 — — — — — — 40 (3.0 V) 80 55 (3.3 V) 100 32 (3.0 V) 64 44 (3.3 V) 80 0.01 — 10 80 mA mA mA mA μA μA mA μA mA μA V f = 20 MHz f = 25 MHz f = 20 MHz f = 25 MHz Ta ≤ 50°C 50°C < Ta AICC — — — — 2.0 0.2 (3.0 V) 2.0 0.01 5.0 1.4 (3.0 V) 3.0 0.01 — 5.0 — RAM standby voltage Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current dissipation values are for VIH min = VCC – 0.5 V and VIL max = 0.5 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 1.10 (mA/(MHz × V)) × VCC × f (normal operation) ICC max = 1.0 (mA) + 0.88 (mA/(MHz × V)) × VCC × f (sleep mode) Rev.6.00 Sep. 27, 2007 Page 937 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Table 22.3 DC Characteristics (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Ports 1, 2, Schmitt trigger input P6 to P6 4 7 voltage PA4 to PA7 Port 5 (when using IRQ) Input high voltage RES, STBY, NMI, MD2 to MD0 EXTAL Ports 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0 Port 4 Three-state Ports 1, 2, 3, 5, 6, A | ITSI | leakage to G current (off state) VOH VOL | Iin | VIL VIH VCC × 0.9 VCC × 0.7 2.2 — — — VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V Symbol VT VT – + + – Min VCC × 0.2 — Typ — — Max — — Unit V V Test Conditions VCC × 0.7 V VT – VT VCC × 0.06 — 2.2 –0.3 –0.3 — — — AVCC + 0.3V VCC × 0.1 V VCC × 0.2 V VCC – 0.5 VCC – 1.0 — — — — — — — — — — — — — — 0.4 10.0 1.0 1.0 1.0 V V V μA μA μA μA IOH = –200 μA IOH = –1 mA IOL = 1.6 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC – 0.5 V Rev.6.00 Sep. 27, 2007 Page 938 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Test Conditions VCC = 2.7 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Item Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI Current Normal operation 2 dissipation* Sleep mode Standby mode Analog power supply voltage Reference power supply voltage *3 Symbol –Ip Min 10 Typ — Max 300 Unit μA Cin — — — — — — 30 30 15 pF pF pF ICC* 4 — — — — — — 30 (3.0 V) 42 (3.3 V) 22 (3.0 V) 31 (3.3 V) 0.01 — 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 — 66 82 51 64 10 80 2.0 5.0 3.0 5.0 — mA mA mA mA μA μA mA μA mA μA V f = 20 MHz f = 25 MHz f = 20 MHz f = 25 MHz Ta ≤ 50°C 50°C < Ta During A/D and D/A conversion Idle During A/D and D/A conversion Idle AICC — — AICC — — RAM standby voltage VRAM 2.0 Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current dissipation values are for VIH min = VCC – 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 0.90 (mA/(MHz × V)) × VCC × f (normal operation) ICC max = 1.0 (mA) + 0.70 (mA/(MHz × V)) × VCC × f (sleep mode) Rev.6.00 Sep. 27, 2007 Page 939 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Table 22.4 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol IOL ΣlOL –IOH Σ–IOH Min — — — — Typ — — — — Max 2.0 80 2.0 40 Unit mA mA mA mA Note: To protect chip reliability, do not exceed the output current values in table 22.4. 22.1.3 AC Characteristics 3V C = 50 pF: ports 1, A to F C = 30 pF: ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (VCC = 2.7 V to 3.6 V) RL Chip output pin C RH Figure 22.1 Output Load Circuit Rev.6.00 Sep. 27, 2007 Page 940 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (1) Clock Timing Table 22.5 Clock Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 50 20 20 — — 10 10 500 Max 500 — — 5 5 — — — Condition B Min 40 15 15 — — 10 10 500 Max 500 — — 5 5 — — — Unit ns ns ns ns ns ms ms μs Figure 22.3 Figure 22.3 Test Conditions Figure 22.2 Rev.6.00 Sep. 27, 2007 Page 941 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics tcyc tCH tCf φ tCL tCr Figure 22.2 System Clock Timing EXTAL tDEXT VCC STBY tDEXT NMI tOSC1 RES φ tOSC1 Figure 22.3 Oscillation Stabilization Timing Rev.6.00 Sep. 27, 2007 Page 942 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (2) Control Signal Timing Table 22.6 Control Signal Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min 200 20 150 10 200 150 10 200 Max — — — — — — — — Condition B Min 200 20 150 10 200 150 10 200 Max — — — — — — — — ns Unit ns tcyc ns Figure 22.5 Test Conditions Figure 22.4 Rev.6.00 Sep. 27, 2007 Page 943 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics φ tRESS RES tRESW tRESS Figure 22.4 Reset Input Timing φ tNMIS NMI tNMIW IRQ tIRQW tIRQS IRQ edge input tIRQS IRQ level input tIRQH tNMIH Figure 22.5 Interrupt Input Timing Rev.6.00 Sep. 27, 2007 Page 944 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (3) Bus Timing Table 22.7 Bus Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time Precharge time* CS delay time 1 CS delay time 2* CS delay time 3* AS delay time RD delay time 1 RD delay time 2 CAS delay time* Read data setup time Read data hold time Symbol tAD tAS tAH tPCH tCSD1 tCSD2 tCSD3 tASD tRSD1 tRSD2 tCASD tRDS tRDH Min — 0.5 × tcyc – 15 0.5 × tcyc – 10 1.5 × tcyc– 20 — — — — — — — 15 0 — — — — — — Max 20 — — — 20 20 25 20 20 20 20 — — 1.0 × tcyc – 25 1.5 × tcyc – 25 2.0 × tcyc – 25 2.5 × tcyc – 25 3.0 × tcyc – 25 1.0 × tcyc – 25 Min — 0.5 × tcyc – 15 0.5 × tcyc – 8 1.5 × tcyc– 15 — — — — — — — 15 0 — — — — — — Condition B Max 20 — — — 15 15 20 15 15 15 15 — — 1.0 × tcyc – 20 1.5 × tcyc – 20 2.0 × tcyc – 20 2.5 × tcyc – 20 3.0 × tcyc – 20 1.0 × tcyc – 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 22.6 to 22.13 Read data access time 1 tACC1 Read data access time 2 tACC2 Read data access time 3 tACC3 Read data access time 4 tACC4 Read data access time 5 tACC5 Read data access time 6* tACC6 Rev.6.00 Sep. 27, 2007 Page 945 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Condition A Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time* WR hold time* CAS setup time* WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWCS tWCH tCSR tWTS tWTH tBRQS tBACD tBZD tBRQOD Min — — 1.0 × tcyc – 20 1.5 × tcyc – 20 — 0.5 × tcyc – 20 0.5 × tcyc – 10 0.5 × tcyc – 10 0.5 × tcyc – 10 0.5 × tcyc – 10 30 5 30 — — — Max 20 20 — — 30 — — — — — — — — 15 50 30 Min — — 1.0 × tcyc – 15 1.5 × tcyc – 15 — 0.5 × tcyc – 15 0.5 × tcyc – 8 0.5 × tcyc – 10 0.5 × tcyc – 10 0.5 × tcyc – 8 25 5 30 — — — Condition B Max 15 15 — — 20 — — — — — — — — 15 40 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 22.15 Figure 22.14 Figure 22.10 Figure 22.8 Test Conditions Figures 22.6 to 22.13 Note: * The DRAM interface is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 946 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tRSD1 RD (read) tAS D15 to D0 (read) tWRD2 HWR, LWR (write) tAS tWDD D15 to D0 (write) tACC3 tACC2 tAS T2 tAH tASD tRSD2 tRDS tRDH tWRD2 tWSW1 tAH tWDH Figure 22.6 Basic Bus Timing (2-State Access) Rev.6.00 Sep. 27, 2007 Page 947 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tRSD1 RD (read) tAS tAS T2 T3 tAH tASD tACC4 tRSD2 tACC5 D15 to D0 (read) tWRD1 HWR, LWR (write) tRDS tRDH tWRD2 tAH tWDH tWDD tWDS tWSW2 D15 to D0 (write) Figure 22.7 Basic Bus Timing (3-State Access) Rev.6.00 Sep. 27, 2007 Page 948 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ T2 Tw T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 22.8 Basic Bus Timing (3-State Access, 1 Wait) Rev.6.00 Sep. 27, 2007 Page 949 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Tp φ tAD A23 to A0 Tr Tc1 Tc2 tAD tAS tPCH CS5 to CS2 (RAS) tCSD2 CAS tAH tACC4 tCSD3 tCASD tACC6 tCASD tACC3 D15 to D0 (read) tWRD2 HWR, (WE) (write) tWDD D15 to D0 (write) tWCS tWDS tWCH tRDS tRDH tWRD2 tWDH Figure 22.9 DRAM Bus Timing (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 950 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics TRp φ TRr TRc1 TRc2 tCSD2 CS5 to CS2 (RAS) tCASD CAS tCSD1 tCSR tCASD Figure 22.10 CAS-Before-RAS Refresh Timing (Not Supported in the H8S/2321) TRp φ tCSD2 CS5 to CS2 (RAS) tCASD CAS tCASD tCSD2 TRr TRc TRc Figure 22.11 Self-Refresh Timing (Not Supported in the H8S/2321) Rev.6.00 Sep. 27, 2007 Page 951 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ T2 or T3 T1 T2 tAD A23 to A0 tAS CS0 tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH tASD tAH Figure 22.12 Burst ROM Access Timing (2-State Access) Rev.6.00 Sep. 27, 2007 Page 952 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ T2 or T3 T1 tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22.13 Burst ROM Access Timing (1-State Access) Rev.6.00 Sep. 27, 2007 Page 953 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics φ tBRQS BREQ tBACD BACK A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBZD tBZD tBACD tBRQS Figure 22.14 External Bus Release Timing φ tBRQOD BREQO tBRQOD Figure 22.15 External Bus Request Output Timing Rev.6.00 Sep. 27, 2007 Page 954 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (4) DMAC Timing Note: The DMAC is not supported in the H8S/2321. Table 22.8 DMAC Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol tDRQS tDRQH tTED tDACD1 tDACD2 Min 30 10 — — — Max — — 20 20 20 Condition B Min 25 10 — — — Max — — 18 18 18 ns Figure 22.18 Figures 22.16 and 22.17 Unit ns Test Conditions Figure 22.19 Rev.6.00 Sep. 27, 2007 Page 955 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ T2 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 22.16 DMAC Single Address Transfer Timing (2-State Access) Rev.6.00 Sep. 27, 2007 Page 956 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 22.17 DMAC Single Address Transfer Timing (3-State Access) Rev.6.00 Sep. 27, 2007 Page 957 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics T1 φ tTED TEND0, TEND1 T2 or T3 tTED Figure 22.18 DMAC TEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 Figure 22.19 DMAC DREQ Input Timing Rev.6.00 Sep. 27, 2007 Page 958 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (5) Timing of On-Chip Supporting Modules Table 22.9 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item I/O ports Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification WDT Overflow output delay time Symbol tPWD tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD Min — 30 30 — — 30 30 1.5 2.5 — 30 30 1.5 2.5 — Max 50 — — 50 50 — — — — 50 — — — — 50 Condition B Min — 25 25 — — 25 25 1.5 2.5 — 25 25 1.5 2.5 — Max 40 — — 40 40 — — — — 40 — — — — 40 ns Figure 22.27 ns ns ns tcyc Figure 22.24 Figure 22.26 Figure 22.25 ns tcyc Figure 22.23 ns ns Figure 22.21 Figure 22.22 Unit ns Test Conditions Figure 22.20 Rev.6.00 Sep. 27, 2007 Page 959 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Condition A Item SCI Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tScyc Min 4 6 0.4 — — — 50 50 30 Max — — 0.6 1.5 1.5 50 — — — Condition B Min 4 6 0.4 — — — 40 40 30 Max — — 0.6 1.5 1.5 40 — — — ns ns ns ns Figure 22.30 Figure 22.29 tScyc tcyc Unit tcyc Test Conditions Figure 22.28 Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time T1 φ tPRS tPRH Ports 1 to 6, A to G (read) T2 tPWD Ports 1, 2, 3, 5, 6, A to G (write) Figure 22.20 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 22.21 PPG Output Timing Rev.6.00 Sep. 27, 2007 Page 960 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22.22 TPU Input/Output Timing φ tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22.23 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 22.24 8-Bit Timer Output Timing Rev.6.00 Sep. 27, 2007 Page 961 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics φ tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 22.25 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 22.26 8-Bit Timer Reset Input Timing φ tWOVD WDTOVF tWOVD Figure 22.27 WDT Output Timing tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 22.28 SCK Clock Input Timing Rev.6.00 Sep. 27, 2007 Page 962 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 22.29 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 22.30 A/D Converter External Trigger Input Timing Rev.6.00 Sep. 27, 2007 Page 963 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.1.4 A/D Conversion Characteristics Table 22.10 A/D Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 6.7 — — — — — — — Typ 10 — — — — — — — — Max 10 — 20 5 ±5.5 ±5.5 ±5.5 ±0.5 ±6.0 Min 10 10.6 — — — — — — — Condition B Typ 10 — — — — — — — — Max 10 — 20 5 ±5.5 ±5.5 ±5.5 ±0.5 ±6.0 Unit Bits μs pF kΩ LSB LSB LSB LSB LSB Rev.6.00 Sep. 27, 2007 Page 964 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.1.5 D/A Conversion Characteristics Table 22.11 D/A Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition A Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Min 8 — — — Condition B Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Unit Bits μs LSB LSB 20 pF capacitive load 2 MΩ resistive load 4 MΩ resistive load Test Conditions Rev.6.00 Sep. 27, 2007 Page 965 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2 Electrical Characteristics of F-ZTAT (H8S/2329B F-ZTAT, H8S/2329E F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) Absolute Maximum Ratings 22.2.1 Table 22.12 Absolute Maximum Ratings Item Power supply voltage 2 3 Input voltage (FWE* , EMLE* ) Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin Vin Vref AVCC VAN Topr Tstg Value –0.3 to +4.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +4.3 –0.3 to AVCC +0.3 1 Regular specifications: –20 to +75* Unit V V V V V V V °C 1 Wide-range specifications: –40 to +85* –55 to +125 °C °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: 1. The operating temperature ranges for flash memory programming/erasing are as follows: Ta = 0°C to +75°C (regular specifications), Ta = 0°C to +85°C (wide-range specifications). 2. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT. 3. The EMLE pin applies to the H8S/2329B F-ZTAT and H8S/2329E F-ZTAT. Rev.6.00 Sep. 27, 2007 Page 966 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2.2 DC Characteristics Table 22.13 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Schmitt trigger input voltage Ports 1, 2, P64 to P67 PA4 to PA7 Port 5 (when using IRQ) Input high voltage RES, STBY, NMI, MD2 to MD0,, 2 3 FWE* , EMLE* EXTAL Ports 3, 5, B to G, P60 to P63, PA0 to PA3 Port 4 Input low voltage RES, STBY, MD2 to MD0, 2 3 FWE* , EMLE* NMI, EXTAL, Ports 3 to 5, B to G, P60 to P63, PA0 to PA3 Output high voltage Output low voltage Input leakage current All output pins All output pins RES STBY, NMI, MD2 to MD0, 2 3 FWE* , EMLE* Port 4 VOH VOL | Iin | VIL VIH VCC × 0.9 — VCC + 0.3 V Symbol VT VT – + + – Min VCC × 0.2 — Typ — — Max — — Test Unit Conditions V V VCC × 0.7 V VT – VT VCC × 0.07 — VCC × 0.7 2.2 — — VCC + 0.3 V VCC + 0.3 V 2.2 –0.3 — — AVCC + 03 V VCC × 0.1 V –0.3 — VCC × 0.2 V VCC – 0.5 VCC – 1.0 — — — — — — — — — — 0.4 10.0 1.0 V V V μA μA IOH = –200 μA IOH = –1 mA IOL = 1.6 mA Vin = 0.5 V to VCC – 0.5 V — — 1.0 μA Vin = 0.5 V to AVCC – 0.5 V Rev.6.00 Sep. 27, 2007 Page 967 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Test Unit Conditions μA Vin = 0.5 V to VCC – 0.5 V Item Three-state leakage current (off state) Symbol Ports 1, 2, 3, 5, 6, A | ITSI | to G Min — Typ — Max 1.0 Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI Current Normal operation 4 dissipation* Sleep mode 5 Standby mode* Analog power supply voltage Reference power supply voltage During A/D and D/A conversion Idle During A/D and D/A conversion Idle –Ip 10 — 300 μA VCC = 3.0 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Cin — — — — — — 30 30 15 pF pF pF ICC* 6 — — — — 55 (3.3 V) 100 44 (3.3 V) 80 0.01 — 10 80 mA mA μA μA mA μA mA μA V f = 25 MHz Ta ≤ 50°C 50°C < Ta AICC — — 0.2 (3.0 V) 2.0 0.01 5.0 AICC — — 1.4 (3.0 V) 3.0 0.01 — 5.0 — RAM standby voltage VRAM 2.0 Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT. 3. The EMLE pin applies to the H8S/2329B F-ZTAT and H8S/2329E F-ZTAT. 4. Current dissipation values are for VIH min = VCC – 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 5. The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC × 0.9, and VIL max = 0.3 V. 6. ICC depends on VCC and f as follows: ICC max = 1.0 (mA) + 1.10 (mA/(MHz × V)) × VCC × f (normal operation) ICC max = 1.0 (mA) + 0.88 (mA/(MHz × V)) × VCC × f (sleep mode) Rev.6.00 Sep. 27, 2007 Page 968 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Table 22.14 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol IOL ∑ IOL –IOH ∑ –IOH Min — — — — Typ — — — — Max 2.0 80 2.0 40 Unit mA mA mA mA Note: To protect chip reliability, do not exceed the output current values in table 22.14. Rev.6.00 Sep. 27, 2007 Page 969 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2.3 AC Characteristics (1) Clock Timing Table 22.15 Clock Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 40 15 15 — — 10 10 500 Max 500 — — 5 5 — — — Unit ns ns ns ns ns ms ms μs Figure 22.3 Figure 22.3 Test Conditions Figure 22.2 Rev.6.00 Sep. 27, 2007 Page 970 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (2) Control Signal Timing Table 22.16 Control Signal Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min 200 20 150 10 200 150 10 200 Max — — — — — — — — ns Unit ns tcyc ns Figure 22.5 Test Conditions Figure 22.4 Rev.6.00 Sep. 27, 2007 Page 971 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (3) Bus Timing Table 22.17 Bus Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 Read data access time 6 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time WR hold time Symbol tAD tAS tAH tPCH tCSD1 tCSD2 tCSD3 tASD tRSD1 tRSD2 tCASD tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tACC6 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWCS tWCH Min — 0.5 × tcyc – 15 0.5 × tcyc – 8 1.5 × tcyc– 15 — — — — — — — 15 0 — — — — — — — — 1.0 × tcyc – 15 1.5 × tcyc – 15 — 0.5 × tcyc – 15 0.5 × tcyc – 8 0.5 × tcyc – 10 0.5 × tcyc – 10 Max 20 — — — 15 15 20 15 15 15 15 — — 1.0 × tcyc – 20 1.5 × tcyc – 20 2.0 × tcyc – 20 2.5 × tcyc – 20 3.0 × tcyc – 20 1.0 × tcyc – 20 15 15 — — 20 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 22.6 to 22.13 Rev.6.00 Sep. 27, 2007 Page 972 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Condition B Item CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol tCSR tWTS tWTH tBRQS tBACD tBZD tBRQOD Min 0.5 × tcyc – 8 25 5 30 — — — Max — — — — 15 40 25 Unit ns ns ns ns ns ns ns Figure 22.15 Figure 22.14 Test Conditions Figure 22.10 Figure 22.8 (4) DMAC Timing Table 22.18 DMAC Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol tDRQS tDRQH tTED tDACD1 tDACD2 Min 25 10 — — — Max — — 18 18 18 ns Figure 22.18 Figures 22.16 and 22.17 Unit ns Test Conditions Figure 22.19 Rev.6.00 Sep. 27, 2007 Page 973 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics (5) Timing of On-Chip Supporting Modules Table 22.19 Timing of On-Chip Supporting Modules Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item I/O ports Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification SCI Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tPWD tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tScyc Min — 25 25 — — 25 25 1.5 2.5 — 25 25 1.5 2.5 4 6 0.4 — — — 40 40 30 Max 40 — — 40 40 — — — — 40 — — — — — — 0.6 1.5 1.5 40 — — — ns ns ns ns Figure 22.30 Figure 22.29 tScyc tcyc tcyc Figure 22.28 ns ns ns tcyc Figure 22.24 Figure 22.26 Figure 22.25 ns tcyc Figure 22.23 ns ns Figure 22.21 Figure 22.22 Unit ns Test Conditions Figure 22.20 Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time Rev.6.00 Sep. 27, 2007 Page 974 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2.4 A/D Conversion Characteristics Table 22.20 A/D Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 10.6 — — — — — — — Typ 10 — — — — — — — — Max 10 — 20 5 ±5.5 ±5.5 ±5.5 ±0.5 ±6.0 Unit Bits μs pF kΩ LSB LSB LSB LSB LSB Rev.6.00 Sep. 27, 2007 Page 975 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2.5 D/A Conversion Characteristics Table 22.21 D/A Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Unit Bits μs LSB LSB 20 pF capacitive load 2 MΩ resistive load 4 MΩ resistive load Test Conditions Rev.6.00 Sep. 27, 2007 Page 976 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics 22.2.6 Flash Memory Characteristics Table 22.22 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to +75°C (program/erase operating temperature range: regular specifications), Ta = 0°C to +85°C (program/erase operating temperature range: wide-range specifications) Item 124 Programming time* * * 136 Erase time* * * Symbol tP tE NWEC tDRP*9 1 Min — — Typ 10 Max 200 Unit ms/ 128 bytes ms/block Times year μs μs μs μs μs Test Conditions Rewrite times Data hold time Programming Wait time after SWE bit setting* Wait time after PSU bit setting* 14 Wait time after P bit setting* * 1 50 1000 100*7 10000*8 — — — — — — — — — — 30 200 10 1 50 10 x y z (z1) — (z2) — (z3) — 1≤n≤6 7 ≤ n ≤ 1000 Wait time for additional writing Wait time after P bit clearing* 1 1 α β γ 1 5 5 4 2 2 100 — 1 100 — 10 10 20 2 4 100 — — — — — — — — — — — — — — — — — — — — — — — μs μs μs μs μs Wait time after PSU bit clearing* Wait time after PV bit setting* 1 Wait time after H'FF dummy write* Wait time after PV bit clearing* 1 1 Wait time after SWE bit clearing* 14 Maximum number of writes* * 1 Wait time after SWE bit setting* 1 Wait time after ESU bit setting* 16 Wait time after E bit setting* * ε η θ N x y z α — μs 1000*5 Times — — 10 — — — — — — 100 μs μs ms μs μs μs μs μs μs Times Wait time for erase time Erasing Wait time after E bit clearing* 1 1 Wait time after ESU bit clearing* Wait time after EV bit setting* 1 β γ 1 Wait time after H'FF dummy write* Wait time after EV bit clearing* 1 1 ε η θ N Wait time after SWE bit clearing* 16 Maximum number of erases* * Rev.6.00 Sep. 27, 2007 Page 977 of 1268 REJ09B0220-0600 Section 22 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (In the H8S/2329B and H8S/2328B, indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). In the H8S/2326, indicates the total time during which the P1 bit and P2 bit in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) are set. Does not include the program-verify time.) 3. Time to erase one block. (In the H8S/2329B and H8S/2328B, indicates the time during which the E bit is set in FLMCR1. In the H8S/2326, indicates the total time during which the E1 bit in FLMCR1 and the E2 bit in FLMCR are set. Does not include the eraseverify time.) 4. Maximum programming time tP(max) = i=1 Σ wait time after P bit setting (z) N 5. The maximum number of writes (N) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (tP(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1≤n≤6 z = 30 μs 7 ≤ n ≤ 1000 z = 200 μs 1≤n≤6 z = 10 μs: For additional writing 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): tE(max) = Wait time after E bit setting (z) × maximum number of erases (N) 7. The minimum number of rewrites after which all characteristics are guaranteed. (The guaranteed range is one to min. rewrites.) 8. Reference value at 25°C. (This is a general indication of the number of rewrites possible under normal conditions.) 9. The data retention characteristics within the specified range, including min. rewrites. 22.3 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. If the F-ZTAT version is used to carry out system evaluation and testing, therefore, when switching to the mask ROM version the same evaluation and testing procedures should also be conducted on this version. Rev.6.00 Sep. 27, 2007 Page 978 of 1268 REJ09B0220-0600 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation General register (destination)* 1 General register (source)* 1 General register* General register (32-bit register) 2 Multiply-and-accumulate register (32-bit register)* Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ¬ Logical NOT (logical complement) ( ) Contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2329 Group and H8S/2328 Group. Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → 1 Rev.6.00 Sep. 27, 2007 Page 979 of 1268 REJ09B0220-0600 Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of the instruction * 0 1 — Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction Rev.6.00 Sep. 27, 2007 Page 980 of 1268 REJ09B0220-0600 (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Table A.1 Condition Code Operation #xx:8→Rd8 —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— Rs8→@aa:32 #xx:16→Rd16 —— —— Rs16→Rd16 —— @ERs→Rd16 —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— IHNZVC No. of States*1 Advanced 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic B2 B B B B B B B B B B B B B B B W4 W W 2 2 6 4 2 2 8 4 2 Rs8→@ERd Rs8→@(d:16,ERd) Rs8→@(d:32,ERd) ERd32-1→ERd32,Rs8→@ERd Rs8→@aa:8 Rs8→@aa:16 6 @aa:32→Rd8 4 @aa:16→Rd8 2 @aa:8→Rd8 2 @ERs→Rd8,ERs32+1→ERs32 8 @(d:32,ERs)→Rd8 4 @(d:16,ERs)→Rd8 2 @ERs→Rd8 2 Rs8→Rd8 Instruction Set MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 981 of 1268 REJ09B0220-0600 MOV.W @ERs,Rd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ MOV.W Rs,Rd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation @(d:16,ERs)→Rd16 —— —— 0— 0— 0— 0— 0— —— —— 0— 0— 0— —— —— —— —— —— —— @(d:32,ERs)→ERd32 —— @ERs→ERd32,ERs32+4→@ERs32 —— @aa:16→ERd32 —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— @(d:32,ERs)→Rd16 IHNZVC No. of States*1 Advanced 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 Mnemonic W W W W W W W W W W W L6 L L L L L L L 6 8 4 10 6 4 2 6 Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 @(d:16,ERs)→ERd32 4 Rs16→@aa:16 2 8 Rs16→@(d:32,ERd) 4 Rs16→@(d:16,ERd) 2 Rs16→@ERd 6 @aa:32→Rd16 —— —— 4 @aa:16→Rd16 —— 2 @ERs→Rd16,ERs32+2→ERs32 — — 8 4 MOV MOV.W @(d:16,ERs),Rd Appendix A Instruction Set MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ERd32-2→ERd32,Rs16→@ERd — — —— 0— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 982 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — @aa:32→ERd32 6 MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ERs32→@ERd —— —— —— 0— 0— 0— 0— 0— 0— —— —— —— —— 0— 0— 0— 0— —————— IHNZVC No. of States*1 Advanced 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] Mnemonic L 6 10 4 6 8 2 4 2 4 4 SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) Repeated for each register restored L 4 (SP-4→SP,ERn32→@SP) Repeated for each register saved Cannot be used in the chip Cannot be used in the chip —————— @SP→ERn32,SP+4→SP @SP→Rn16,SP+2→SP ERs32→@aa:32 ERs32→@aa:16 —— —— ERd32-4→ERd32,ERs32→@ERd — — ERs32→@(d:32,ERd) ERs32→@(d:16,ERd) 4 MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L L L L W L W L L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.W Rn POP.L ERn ↔↔↔↔↔↔↔↔↔↔ PUSH.L ERn LDM LDM @SP+,(ERm-ERn) ↔↔↔↔↔↔↔↔↔↔ PUSH PUSH.W Rn Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — STM STM (ERm-ERn),@-SP 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd [2] Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 983 of 1268 REJ09B0220-0600 MOVTPE MOVTPE Rs,@aa:16 [2] (2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC No. of States*1 Advanced 1 1 2 1 3 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Appendix A Instruction Set Mnemonic ADD.B Rs,Rd W4 W L6 L B2 B L L L B W W L L B B W4 2 2 2 2 2 2 2 2 2 2 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 2 Rd8+Rs8+C→Rd8 Rd8+#xx:8+C→Rd8 2 ERd32+ERs32→ERd32 ERd32+#xx:32→ERd32 2 Rd16+Rs16→Rd16 — [3] — [4] — [4] Rd16+#xx:16→Rd16 — [3] B 2 Rd8+Rs8→Rd8 — ADD.W #xx:16,Rd ADD.W Rs,Rd ↔↔ ↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔ ↔↔ — ADD ADD.B #xx:8,Rd B2 Rd8+#xx:8→Rd8 ADDX Rs,Rd — [5] ↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔ ↔↔ ↔↔↔↔↔ SUB.W #xx:16,Rd — [3] ↔↔↔ SUB SUB.B Rs,Rd — ↔ Rev.6.00 Sep. 27, 2007 Page 984 of 1268 REJ09B0220-0600 1 — [5] 1 1 —— — —— — —— — —— — —— — —— — —— —— —— —— —— —* — — — — — * 1 1 1 1 1 1 1 1 1 1 2 ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd16-Rs16→Rd16 — [3] — [4] — [4] — — ERd32-#xx:32→ERd32 IHNZVC No. of States*1 Advanced 1 3 1 Mnemonic W L6 L B2 B L L L B W W L L B B W 2 2 2 2 2 2 Rd16-2→Rd16 ERd32-1→ERd32 ERd32-2→ERd32 Rd8 decimal adjust→Rd8 2 Rd16-1→Rd16 2 Rd8-1→Rd8 2 ERd32-4→ERd32 2 ERd32-2→ERd32 2 ERd32-1→ERd32 2 Rd8-Rs8-C→Rd8 Rd8-#xx:8-C→Rd8 2 ERd32-ERs32→ERd32 [5] [5] 2 SUB SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ↔↔↔↔↔ ↔↔ ↔↔↔↔↔ ↔↔↔ ↔↔↔↔↔ SUBX SUBX #xx:8,Rd 1 1 1 SUBX Rs,Rd SUBS SUBS #1,ERd —————— —————— —————— —— —— —— —— —— —* — — — — — *— SUBS #2,ERd 1 1 1 1 1 1 1 1 12 SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DAS DAS Rd MULXU MULXU.B Rs,Rd Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — Rd16×Rs16→ERd32 (unsigned multiplication) —————— ↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔ DEC.L #2,ERd MULXU.W Rs,ERd 20 MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 (signed multiplication) Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 985 of 1268 REJ09B0220-0600 B 4 —— ↔↔ ↔↔ —— MULXS MULXS.B Rs,Rd Rd8×Rs8→Rd16 (signed multiplication) —— —— 13 21 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — RdL: quotient) (unsigned division) IHNZVC No. of States*1 Advanced 12 Mnemonic B 2 Appendix A Instruction Set DIVXU DIVXU.B Rs,Rd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — DIVXU.W Rs,ERd Rd: quotient) (unsigned division) B RdL: quotient) (signed division) W Rd: quotient) (signed division) B2 B W4 W L6 L B W L W L 2 2 2 2 2 2 2 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32) Rd16-#xx:16 2 Rd8-Rs8 Rd8-#xx:8 — — 4 4 W 2 ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — — 20 NEG.L ERd — ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔ EXTU.L ERd —— 0 ↔↔↔ ↔↔ ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 986 of 1268 REJ09B0220-0600 Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — — 13 ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — — 21 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 1 1 1 —— 0 0— 0— 1 1 DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.B Rd NEG.W Rd EXTU EXTU.W Rd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ( of Rd16) ( of ERd32) @ERd-0→CCR set, (1)→ ( of @ERd) IHNZVC No. of States*1 Advanced 1 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic MAC MAC @ERn+, @ERm+ Cannot be used in the chip ↔ ↔ TAS TAS @ERd*3 B 4 —— ↔ ↔ EXTS.L ERd —— L 2 ↔ ↔ EXTS —— 0— EXTS.W Rd W 2 ( of Rd16)→ ( of ERd32)→ 0— 1 0— 4 [2] CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 987 of 1268 REJ09B0220-0600 (3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8∧#xx:8→Rd8 —— —— —— —— —— —— —— —— —— —— —— —— —— —— Rd16⊕#xx:16→Rd16 —— Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 —— —— ERd32⊕ERs32→ERd32 ¬ Rd8→Rd8 ¬ Rd16→Rd16 —— —— —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— IHNZVC No. of States*1 Advanced 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 Appendix A Instruction Set Mnemonic B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 L B W L 2 2 2 4 2 2 4 2 Rd16∨#xx:16→Rd16 Rd16∨Rs16→Rd16 ERd32∨#xx:32→ERd32 ERd32∨ERs32→ERd32 Rd8⊕#xx:8→Rd8 Rd8⊕Rs8→Rd8 2 Rd8∨Rs8→Rd8 Rd8∨#xx:8→Rd8 4 ERd32∧ERs32→ERd32 ERd32∧#xx:32→ERd32 2 Rd16∧Rs16→Rd16 Rd16∧#xx:16→Rd16 2 Rd8∧Rs8→Rd8 AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ NOT.L ERd ¬ ERd32→ERd32 —— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 988 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd 0— 1 (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation —— —— 0 —— —— —— —— —— —— —— MSB LSB C —— —— —— —— —— 0 C MSB LSB —— —— —— —— C MSB LSB IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔ Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 989 of 1268 REJ09B0220-0600 SHLL.L #2,ERd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ SHLL.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation — — — 0 — — — — — — — C MSB — — — — — — MSB — — LSB C LSB —— 0 —— 0 —— —— —— —— —— —— —— —— —— —— —— —— MSB LSB —— 0 C —— 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 —— 0 0 —— 0 0 IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Mnemonic B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SHLR SHLR.B Rd Appendix A Instruction Set SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ROTXR.L #2,ERd ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 990 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd Addressing Mode/ Instruction Length (Bytes) Condition Code Operation —— —— —— C MSB —— —— — — — MSB — 1 LSB C —— —— —— —— —— —— LSB —— 0 0 0 0 0 0 0 0 0 0 0 0 IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 1 1 1 1 1 1 Mnemonic B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ ROTR.L #2,ERd ↔↔↔↔↔↔↔↔↔↔↔↔ ROTR.L ERd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 991 of 1268 REJ09B0220-0600 (5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (#xx:3 of Rd8)←1 —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— (#xx:3 of @aa:32)←0 (Rn8 of Rd8)←0 —————— —————— (Rn8 of @ERd)←0 —————— IHNZVC No. of States*1 Advanced 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 Appendix A Instruction Set Mnemonic B B B B B B B B B B B B B B B B B B B 4 4 6 2 8 6 4 4 2 8 6 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 (#xx:3 of @ERd)←0 (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 4 (Rn8 of @aa:8)←1 4 (Rn8 of @ERd)←1 2 (Rn8 of Rd8)←1 8 (#xx:3 of @aa:32)←1 6 (#xx:3 of @aa:16)←1 4 (#xx:3 of @aa:8)←1 4 (#xx:3 of @ERd)←1 2 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 Rev.6.00 Sep. 27, 2007 Page 992 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 —————— —————— 4 5 BCLR Rn,@aa:16 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (Rn8 of @aa:32)←0 —————— (#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — —————— IHNZVC No. of States*1 Advanced 6 1 4 Mnemonic B B B [¬ (#xx:3 of @ERd)] B [¬ (#xx:3 of @aa:8)] B [¬ (#xx:3 of @aa:16)] B [¬ (#xx:3 of @aa:32)] B B B B 6 4 4 2 (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] —————— 8 (#xx:3 of @aa:32)← —————— 6 (#xx:3 of @aa:16)← —————— 4 (#xx:3 of @aa:8)← —————— 4 (#xx:3 of @ERd)← 2 8 BCLR BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BNOT #xx:3,@aa:8 4 BNOT #xx:3,@aa:16 5 BNOT #xx:3,@aa:32 6 BNOT Rn,Rd 1 4 4 —————— 5 BNOT Rn,@ERd (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← [¬ (Rn8 of @aa:16)] BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32)← [¬ (Rn8 of @aa:32)] —————— 6 BTST B B B 4 BTST #xx:3,Rd B 2 ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z 4 6 ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z ——— ——— ——— ——— —— —— —— —— 1 3 3 4 BTST #xx:3,@ERd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 993 of 1268 REJ09B0220-0600 BTST #xx:3,@aa:16 ↔↔↔↔ BTST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ¬ (#xx:3 of @aa:32)→Z ——— ——— ——— ——— ——— ——— —— —— —— —— —— ————— ————— ————— ————— ————— ————— ————— ————— ————— ¬ (#xx:3 of @aa:32)→C C→(#xx:3 of Rd8) ————— —— ¬ (Rn8 of Rd8)→Z IHNZVC No. of States*1 Advanced 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 Mnemonic B B B B B B B B B B B B B B B B B B B 4 4 2 8 6 4 4 2 8 6 (#xx:3 of @aa:16)→C (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C ¬ (#xx:3 of @ERd)→C ¬ (#xx:3 of @aa:8)→C ¬ (#xx:3 of @aa:16)→C 4 (#xx:3 of @aa:8)→C 4 (#xx:3 of @ERd)→C 2 (#xx:3 of Rd8)→C 8 ¬ (Rn8 of @aa:32)→Z 6 ¬ (Rn8 of @aa:16)→Z 4 ¬ (Rn8 of @aa:8)→Z 4 ¬ (Rn8 of @ERd)→Z 2 8 BTST BTST #xx:3,@aa:32 Appendix A Instruction Set BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BILD #xx:3,@aa:32 BST BST #xx:3,Rd —————— C→(#xx:3 of @ERd) C→(#xx:3 of @aa:8) —————— —————— ↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 994 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ↔↔↔↔↔↔ 1 4 4 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BST #xx:3,@ERd BST #xx:3,@aa:8 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation C→(#xx:3 of @aa:16) —————— —————— —————— —————— —————— —————— —————— ————— ————— ————— ————— ————— ————— ————— C∧[¬ (#xx:3 of @aa:8)]→C C∧[¬ (#xx:3 of @aa:16)]→C C∧[¬ (#xx:3 of @aa:32)]→C C∨(#xx:3 of Rd8)→C ————— ————— ————— ————— C∨(#xx:3 of @ERd)→C ————— C→(#xx:3 of @aa:32) ¬ C→(#xx:3 of Rd8) IHNZVC No. of States*1 Advanced 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 Mnemonic B B B B B B B B B B B B B B B B B B B 4 2 8 6 4 4 2 8 6 4 4 C∧(#xx:3 of @ERd)→C C∧(#xx:3 of @aa:8)→C C∧(#xx:3 of @aa:16)→C C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @ERd)]→C 2 C∧(#xx:3 of Rd8)→C 8 ¬ C→(#xx:3 of @aa:32) 6 ¬ C→(#xx:3 of @aa:16) 4 ¬ C→(#xx:3 of @aa:8) 4 ¬ C→(#xx:3 of @ERd) 2 8 6 BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 995 of 1268 REJ09B0220-0600 BOR #xx:3,@ERd ↔↔↔↔↔↔↔↔↔↔↔↔ BOR BOR #xx:3,Rd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Addressing Mode/ Instruction Length (Bytes) Condition Code Operation C∨(#xx:3 of @aa:8)→C ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C C⊕[¬ (#xx:3 of @aa:32)]→C ————— ————— ————— C∨(#xx:3 of @aa:16)→C C∨(#xx:3 of @aa:32)→C C∨[¬ (#xx:3 of Rd8)]→C IHNZVC No. of States*1 Advanced 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 Mnemonic B B B B B B B B B B B B B B B B B B 8 6 4 4 2 8 6 4 4 2 C⊕(#xx:3 of Rd8)→C C⊕(#xx:3 of @ERd)→C C⊕(#xx:3 of @aa:8)→C C⊕(#xx:3 of @aa:16)→C C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C C⊕[¬ (#xx:3 of @ERd)]→C 8 C∨[¬ (#xx:3 of @aa:32)]→C 6 C∨[¬ (#xx:3 of @aa:16)]→C 4 C∨[¬ (#xx:3 of @aa:8)]→C 4 C∨[¬ (#xx:3 of @ERd)]→C 2 8 6 4 BOR BOR #xx:3,@aa:8 Appendix A Instruction Set BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIXOR #xx:3,@aa:32 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Sep. 27, 2007 Page 996 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 2 Mnemonic — — — — — — — — — — — — — — — — — — 4 2 4 V=0 2 4 Z=1 2 4 Z=0 2 4 C=1 2 4 C=0 2 4 C∨Z=1 2 C∨Z=0 4 2 else next; Never 4 PC←PC+d 2 if condition is true then Always Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 3 2 3 2 3 2 3 2 3 2 3 2 3 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 997 of 1268 REJ09B0220-0600 BVC d:16 Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 2 3 Mnemonic — — — — — — — — — — — — — — 4 2 4 2 4 2 4 N⊕V=1 2 N⊕V=0 4 2 N=1 4 2 N=0 4 —————— —————— —————— —————— —————— —————— —————— —————— —————— Z∨(N⊕V)=0 — — — — — — —————— Z∨(N⊕V)=1 — — — — — — —————— 2 V=1 —————— Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — IHNZVC Bcc BVS d:8 Appendix A Instruction Set BVS d:16 BPL d:8 BPL d:16 BMI d:8 Rev.6.00 Sep. 27, 2007 Page 998 of 1268 REJ09B0220-0600 2 3 2 3 2 3 2 3 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PC←ERn —————— —————— —————— —————— —————— —————— —————— —————— —————— IHNZVC No. of States*1 Advanced 2 3 5 4 5 4 5 6 5 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ 2 4 2 2 4 2 4 2 2 PC←@SP+ PC→@-SP,PC←@aa:8 PC→@-SP,PC←aa:24 PC→@-SP,PC←ERn PC→@-SP,PC←PC+d:16 PC→@-SP,PC←PC+d:8 PC←@aa:8 PC←aa:24 Mnemonic — — — — — — — — — JMP JMP @ERn JMP @aa:24 JMP @@aa:8 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS @aa @(d,PC) @@aa — Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 999 of 1268 REJ09B0220-0600 (7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PC→@-SP,CCR→@-SP, 1 ————— EXR→@-SP,→PC IHNZVC No. of States*1 Advanced 8 [9] Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic — Appendix A Instruction Set TRAPA TRAPA #xx:2 ↔ ↔ EXR←@SP+,CCR←@SP+, PC←@SP+ Transition to power-down state #xx:8→CCR #xx:8→EXR 2 2 4 4 6 6 10 10 4 4 6 6 8 8 @ERs→EXR @(d:16,ERs)→CCR @(d:16,ERs)→EXR @(d:32,ERs)→CCR @(d:32,ERs)→EXR @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR @aa:32→EXR @ERs→CCR Rs8→EXR Rs8→CCR SLEEP B2 B4 B B W W W W W W W W W W W W SLEEP — —————— ↔ ↔ ↔ ↔ RTE RTE — 5 [9] 2 ↔ ↔ ↔ ↔ LDC Rs,CCR LDC Rs,EXR —————— ↔ ↔ ↔ ↔ ↔ ↔ LDC @ERs,CCR LDC @ERs,EXR —————— ↔ ↔ ↔ ↔ ↔ ↔ LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR —————— ↔ ↔ ↔ ↔ ↔ ↔ LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR —————— ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev.6.00 Sep. 27, 2007 Page 1000 of 1268 REJ09B0220-0600 —————— LDC LDC #xx:8,CCR ↔ ↔ ↔ ↔ 1 2 1 1 3 3 4 4 6 6 4 —————— 4 4 —————— 4 5 —————— 5 LDC #xx:8,EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Addressing Mode/ Instruction Length (Bytes) Condition Code Operation CCR→Rd8 —————— —————— —————— —————— —————— —————— —————— —————— EXR→Rd8 IHNZVC No. of States*1 Advanced 1 1 3 3 4 4 6 6 4 Mnemonic B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 — 8 8 6 6 CCR→@aa:16 EXR→@aa:16 CCR→@aa:32 EXR→@aa:32 CCR∧#xx:8→CCR EXR∧#xx:8→EXR CCR∨#xx:8→CCR EXR∨#xx:8→EXR CCR⊕#xx:8→CCR EXR⊕#xx:8→EXR 2 PC←PC+2 4 4 10 EXR→@(d:32,ERd) 10 CCR→@(d:32,ERd) 6 EXR→@(d:16,ERd) 6 CCR→@(d:16,ERd) 4 EXR→@ERd 4 CCR→@ERd 2 2 STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd —————— —————— —————— —————— —————— STC EXR,@-ERd 4 4 4 5 5 STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ↔ ↔ ↔ ↔ ↔ ↔ ANDC ANDC #xx:8,CCR 1 —————— 2 ANDC #xx:8,EXR ↔ ↔ ↔ ↔ ↔ ↔ ORC ORC #xx:8,CCR 1 —————— 2 ORC #xx:8,EXR ↔ ↔ ↔ ↔ ↔ ↔ XORC XORC #xx:8,CCR 1 —————— —————— 2 1 XORC #xx:8,EXR Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1001 of 1268 REJ09B0220-0600 NOP NOP (8) Block Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation —————— IHNZVC No. of States*1 Advanced 4+2n *2 Appendix A Instruction Set Mnemonic — 4 if R4L 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; 4 if R4 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; Rev.6.00 Sep. 27, 2007 Page 1002 of 1268 REJ09B0220-0600 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — — —————— 4+2n *2 EEPMOV EEPMOV.B EEPMOV.W Notes: 1. 2. 3. [1] [2] [3] [4] [5] [6] [7] [8] [9] The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. Cannot be used in the chip. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. Appendix A Instruction Set A.2 Instruction Codes Table A.2 shows the instruction codes. Rev.6.00 Sep. 27, 2007 Page 1003 of 1268 REJ09B0220-0600 Instruction Size 1st byte 8 rd 8 rd rd rd 0 erd IMM IMM 9 9 A A B B B rd E rd IMM rs rd rd rd 0 erd 0 IMM 4 1 IMM rd 0 7 0 0 disp 0 0 disp 1 0 disp disp abs abs 7 6 0 IMM 0 6 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 0 6 0 IMM 0 erd abs 1 3 6 6 0 ers 0 erd IMM IMM 6 rs 6 F rd 6 9 6 A 1 6 1 6 C E A A 0 8 1 8 rs IMM 9 0 erd 8 0 erd 0 0 erd 1 ers 0 erd 1 rs 1 rs 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L L L L B B B B W W L L B B B B B B B — — — — Mnemonic Instruction Format Table A.2 ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd Appendix A Instruction Set ADDS #2,ERd Instruction Codes ADDS #4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd Rev.6.00 Sep. 27, 2007 Page 1004 of 1268 REJ09B0220-0600 AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Instruction Size 1st byte 4 2 8 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 disp A disp B disp C disp D disp E disp F 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 0 disp 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — Mnemonic Instruction Format Bcc BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1005 of 1268 REJ09B0220-0600 BLE d:16 Instruction Size 1st byte 7 2 rd 0 7 2 0 0 7 2 0 7 2 0 0 IMM abs 0 IMM 2 abs 0 IMM 7 8 8 rd 0 6 2 rn 0 0 6 2 rn 6 2 rn 0 0 abs rn abs 2 6 8 8 rd 0 7 6 0 0 7 6 0 7 6 1 IMM 0 abs 1 IMM 6 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 7 abs 1 IMM 0 7 7 1 IMM 0 7 abs 1 IMM 7 0 0 rd 0 7 4 0 0 7 abs 4 1 IMM 0 7 4 1 IMM 0 4 abs 1 IMM 7 0 0 1 IMM 1 IMM 1 IMM 0 IMM D F A 1 3 rn 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 A 2 D F A A 6 C E A A 7 C E A A 4 C E A A abs 0 erd 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B B B B B B B B B B B Mnemonic Instruction Format BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd Appendix A Instruction Set BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd Rev.6.00 Sep. 27, 2007 Page 1006 of 1268 REJ09B0220-0600 BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Instruction Size 1st byte 6 7 rd 0 6 7 7 abs 6 7 0 6 7 0 1 IMM abs 1 IMM 1 IMM 0 6 8 8 rd 0 7 5 5 abs 7 5 0 7 5 1 IMM 0 abs 1 IMM 1 IMM 0 7 0 0 rd 0 7 7 7 abs 7 7 0 7 7 0 IMM 0 abs 0 IMM 0 IMM 0 7 0 0 rd 0 7 1 1 abs 7 1 abs 0 IMM 0 0 IMM 0 7 1 0 IMM 0 7 8 8 rd 0 6 1 1 abs abs rn 0 6 1 rn 0 6 1 rn 0 6 8 8 rn 0 0 IMM 0 0 IMM 0 1 IMM 0 1 IMM 0 D F A 1 3 1 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 5 C E A A 7 C E A A 1 D F A A 1 D F A A abs 0 erd 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 1 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B B B B B B B B B B B Mnemonic Instruction Format BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1007 of 1268 REJ09B0220-0600 BNOT Rn,@aa:32 Instruction Size 1st byte 7 4 rd 0 7 7 0 0 rd 0 7 7 8 8 rd 0 6 6 8 8 disp 0 0 rd 0 6 6 7 0 6 abs 7 0 IMM 0 6 7 0 IMM 0 abs 0 IMM 8 8 rd 0 7 3 abs abs 0 0 rd 0 6 3 rn 0 0 IMM 7 3 0 IMM 0 0 7 3 0 IMM 0 7 3 0 IMM 0 7 0 0 IMM 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd disp abs 6 abs 6 0 rn 0 0 rn 0 0 rn 0 0 rn 0 abs 7 0 0 IMM 0 abs 7 0 0 0 IMM 0 0 0 IMM 0 0 0 IMM abs 7 4 0 0 IMM abs 7 4 0 0 IMM 4 0 0 IMM 4 0 0 IMM C E A 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 0 D F A A 0 D F A A 5 C 7 D F A A 3 C E A A 3 C abs 0 erd 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B — — B B B B B B B B B B B B Mnemonic Instruction Format BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd Appendix A Instruction Set BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd Rev.6.00 Sep. 27, 2007 Page 1008 of 1268 REJ09B0220-0600 BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd Instruction Size 1st byte 7 E 6 3 rn 0 6 abs 6 3 rn 0 3 rn 0 abs 0 0 rd 0 7 5 0 0 7 abs 7 5 0 0 IMM 5 0 IMM 0 5 abs 0 IMM 7 0 0 0 IMM A 1 3 0 IMM 0 erd abs 1 3 A 5 C E A A abs 6 6 7 7 7 6 6 Cannot be used in the chip A rd C rs rd rd rd 0 erd IMM IMM 2 rs 2 1 ers 0 erd 0 rd rd rd rd rd 0 erd 0 erd 0 5 1 rs rs 3 5 0 rd 0 erd C 5 5 4 9 9 8 8 F F rd 0 erd 0 0 5 D 7 F D D rs rs 5 D 9 D A F F F A B B B B 1 1 1 3 B B 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B — B B W W L L B B B W W L L B W B W — — Mnemonic Instruction Format BTST BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1009 of 1268 REJ09B0220-0600 EEPMOV.W Instruction Size 1st byte 1 7 D rd 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern 0 abs abs IMM 4 1 0 7 rs rs 0 6 9 0 0 0 0 0 0 0 0 ers D B B 0 0 0 0 0 abs abs 6 6 6 B B disp disp 2 2 0 0 disp disp 9 F F 8 8 D 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 6 6 6 7 7 6 6 6 1 0 1 0 1 0 1 0 1 0 ers 0 1 4 4 4 4 4 4 4 4 4 4 IMM F 5 7 0 5 D 7 F 0 ern 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W L W L B W W L L — — — — — — B B B B W W W W W W W W W W Mnemonic Instruction Format EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd Appendix A Instruction Set INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Rev.6.00 Sep. 27, 2007 Page 1010 of 1268 REJ09B0220-0600 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR Instruction Size 1st byte 0 1 4 0 6 B 2 2 7 7 7 0 ern+3 0 ern+2 0 ern+1 0 abs B D D D 6 6 6 6 1 0 0 0 4 1 2 3 1 1 1 1 0 0 0 0 Cannot be used in the chip 0 abs 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W L L L L L — B rd C rs rd rd rd 0 6 A 2 rd rd disp disp 0 ers 0 ers 0 ers 0 ers abs 0 rd rd rs rs 0 6 A A rs rs disp disp abs abs 2 1 erd 1 erd 0 erd 1 erd abs 8 rs rs rd rd rd rd 0 6 B disp 2 rd disp IMM A 0 rs 0 ers 0 ers 0 ers abs abs abs 8 E 8 C rd A A 8 E 8 C rs A A 9 D 9 F 8 B B B B B B B B B B B B B B B W W W W W 7 6 6 0 7 6 6 3 6 7 6 6 6 6 2 6 7 6 6 0 F IMM Mnemonic Instruction Format LDC LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1011 of 1268 REJ09B0220-0600 MOV.W @(d:32,ERs),Rd Instruction Size 1st byte 6 D rd rd rd rs rs 0 6 B A rs rs rs rs 0 erd IMM abs abs disp disp abs abs B 0 2 1 erd 1 erd 0 erd 1 erd 8 A 0 1 ers 0 erd 0 0 6 9 F 8 0 6 B 2 D B 0 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 1 erd 0 ers 8 A 0 ers 0 ers abs abs B disp A 0 ers disp 0 erd B 9 F 8 D B B 0 erd abs abs 0 ers 0 erd 0 ers 0 erd 0 ers 0 erd disp disp 6 7 6 6 6 6 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ers 0 erd B 9 F 8 D B B A F 1 1 1 1 1 1 1 1 1 1 1 1 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Cannot be used in the chip 0 ers 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W W W W W W W W L L L L L L L L L L L L L L B B B 0 1 C 0 5 0 2 5 0 rd 0 erd C rs rs 1 0 2 0 5 5 W B W rs rs rd 0 erd Mnemonic Instruction Format MOV MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) Appendix A Instruction Set MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd Rev.6.00 Sep. 27, 2007 Page 1012 of 1268 REJ09B0220-0600 MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd Instruction Size 1st byte 1 7 8 rd rd 0 erd 0 rd rd 0 erd IMM rs rd rd rd 0 erd 0 IMM 4 1 rn 0 rn 0 rd rd rd rd 0 erd 0 erd 6 D F 0 ern 6 D 7 0 ern 7 0 F 0 8 C 9 D B F 0 4 IMM 6 4 0 ers 0 erd IMM IMM 4 rs 4 F 9 B 0 0 1 3 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B W L — B W L B B W W L L B B W L W L B B W W L L Mnemonic Instruction Format NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1013 of 1268 REJ09B0220-0600 ROTL.L #2, ERd Instruction Size 1st byte 1 3 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L B B W W L L B B W W L L — — B B W W L L Mnemonic Instruction Format ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd Appendix A Instruction Set ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd Rev.6.00 Sep. 27, 2007 Page 1014 of 1268 REJ09B0220-0600 ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd Instruction Size 1st byte 1 1 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 6 6 7 8 D D 7 8 6 F 6 F 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 6 9 1 erd 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 6 9 0 1 erd C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L B B W W L L B B W W L L — B B W W Mnemonic Instruction Format SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W W STC.W CCR,@-ERd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1015 of 1268 REJ09B0220-0600 STC.W EXR,@-ERd Instruction Size 1st byte 0 1 4 0 6 B 8 0 0 0 0 0 ern 0 ern 0 ern abs abs abs 8 A A F F F B B B D D D 6 6 6 6 6 6 1 0 1 0 0 0 4 4 4 1 2 3 1 1 1 1 1 1 0 0 0 0 0 0 Cannot be used in the chip abs 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W W W L L L L L B 8 rs rd rd rd 0 erd IMM IMM 3 rs 3 1 ers 0 erd 0 8 9 IMM rs rd 0 7 B C 0 0 erd E 00 IMM IMM rs rd rd rd 0 erd 0 6 5 IMM 0 ers 0 erd IMM 5 rs 5 F 0 erd 0 erd 0 erd 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 W W L L L L L B B B — B B W W L L 0 7 6 7 1 D 5 0 1 B 1 1 1 1 7 1 7 1 Mnemonic Instruction Format STC STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP Appendix A Instruction Set STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd Rev.6.00 Sep. 27, 2007 Page 1016 of 1268 REJ09B0220-0600 SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd*2 TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd Instruction Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B Mnemonic Instruction Format XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 0000 0001 • • • 0111 1000 1001 • • • 1111 R0H R1H • • • R7H R0L R1L • • • R7L General Register Register Field General Register 8-Bit Register Address Register 32-Bit Register Register Field General Register 000 001 • • • 111 ER0 ER1 • • • ER7 Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1017 of 1268 REJ09B0220-0600 A.3 Table A.3 Instruction when most significant bit of BH is 0. BL Instruction when most significant bit of BH is 1. Instruction code 1st byte 2nd byte AH AL BH Appendix A Instruction Set AL 3 ORC XORC ADD SUB CMP SUBX MOV ADDX XOR MOV.B AND Table A.3(2) ANDC OR LDC 4 5 D F E 6 B C 8 9 A 7 AH 0 1 2 0 NOP 1 Table A.3(2) LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Operation Code Map Operation Code Map (1) 2 Table A.3 shows the operation code map. 3 BLS RTS BSR XOR MOV MOV EEPMOV Table A.3(2) AND BST Table A.3(2) Table A.3(2) RTE BSR MOV Table A.3(3) JMP OR TRAPA Table A.3(2) BCC BCS BNE BMI BGE BVC BVS BPL BEQ BLT BGT JSR BLE Rev.6.00 Sep. 27, 2007 Page 1018 of 1268 REJ09B0220-0600 BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD ADD ADDX CMP SUBX OR XOR AND MOV 4 BRA BRN BHI 5 MULXU DIVXU MULXU DIVXU 6 BSET BNOT BCLR BTST 7 8 9 A B C D E F Note: * Cannot be used in the chip. Table A.3 Instruction code BH BL 1st byte 2nd byte AH AL BH 3 STM STC ADD INC INC ADDS MOV SHLL SHLR ROTXL ROTXR NOT EXTU EXTU NEG ROTXR ROTR NEG SUB DEC DEC SUBS CMP BLS BCC Table * A.3(4) MOVFPE SUB SUB OR XOR AND OR XOR AND BCS BEQ BNE BVC MOV BVS BPL MOV BMI BGE MOVTPE* BLT BGT DEC ROTXL ROTL SHLR SHAR SHLL SHAL SHAL SHAR ROTL ROTR EXTS INC LDC MAC* SLEEP CLRMAC * Table A.3(3) Table A.3(3) 4 5 7 9 A B D 8 6 C E TAS AH AL 0 1 2 F Table A.3(3) 01 MOV LDM 0A INC 0B ADDS INC Operation Code Map (2) 0F DAA 10 SHLL SHAL SHAR ROTL ROTR EXTS 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS DEC 1F DAS 58 BRA BRN BHI BLE 6A MOV Table A.3(4) MOV 79 MOV ADD CMP 7A MOV ADD CMP Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1019 of 1268 REJ09B0220-0600 Note: * Cannot be used in the chip. Table A.3 Instruction code BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte Appendix A Instruction Set AH AL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL 2 3 4 5 6 7 8 9 A B C D MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND AH AL BH BL CH 0 1 E F Operation Code Map (3) 01C05 MULXS 01D05 DIVXS Rev.6.00 Sep. 27, 2007 Page 1020 of 1268 REJ09B0220-0600 BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BNOT 7Dr07 *1 BSET BNOT 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET BNOT 7Faa7 *2 BSET BNOT Notes: 1. r is the register specification field. 2. aa is the absolute address specification. Table A.3 Instruction code BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 2 4 5 6 7 8 9 A B C D BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 3 E F 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte AH AL EL AHALBHBLCHCLDHDLEH 0 1 6A10aaaa6* Operation Code Map (4) 6A10aaaa7* 6A18aaaa6* BCLR BSET BNOT 6A18aaaa7* Instruction code BH BL CH CL DH DL EH EL FH FL 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. AH AL GL 2 4 5 6 7 BTST 3 AHALBHBL ... FHFLGH 0 1 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BCLR BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 6A38aaaaaaaa7* Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1021 of 1268 REJ09B0220-0600 Note: * aa is the absolute address specification. Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 Rev.6.00 Sep. 27, 2007 Page 1022 of 1268 REJ09B0220-0600 Appendix A Instruction Set Table A.4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus Cycle Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM SN On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev.6.00 Sep. 27, 2007 Page 1023 of 1268 REJ09B0220-0600 Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Branch Instruction Address Fetch Read Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 J ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 Rev.6.00 Sep. 27, 2007 Page 1024 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction Bcc Mnemonic BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1025 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction BIAND Mnemonic BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1026 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction BNOT Mnemonic BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 Advanced Advanced I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1027 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Cannot be used in the chip 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 11 19 11 19 1 1 1 1 1 1 1 1 1 1 1 1 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1028 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Advanced JSR JSR @ERn JSR @aa:24 Advanced Advanced I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 1 1 1 J Byte Stack Data Operation Access K L 2n+2* 2n+2* 2 2 Word Data Access M Internal Operation N JSR @@aa:8 Advanced LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR Rev.6.00 Sep. 27, 2007 Page 1029 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction LDM Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd Cannot be used in the chip 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 2 2 2 J Byte Stack Data Operation Access K 4 6 8 L Word Data Access M Internal Operation N 1 1 1 Cannot be used in the chip Rev.6.00 Sep. 27, 2007 Page 1030 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction MOV Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd 2 2 1 1 1 1 1 1 1 1 1 11 19 11 19 I 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Can not be used in the chip 2 2 2 2 2 2 2 2 2 2 2 2 1 1 J Byte Stack Data Operation Access K L Word Data Access M 1 1 1 1 1 1 Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1031 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction OR Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd I 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 1 1 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Rev.6.00 Sep. 27, 2007 Page 1032 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction ROTXR Mnemonic ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP Advanced I 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2/3* 2 1 Byte Stack Data Operation Access K L Word Data Access M Internal Operation N J 1 1 Rev.6.00 Sep. 27, 2007 Page 1033 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA 3 TAS @ERd* 2 2 3 3 4 4 2 2 2 Cannot be used in the chip 1 2 1 3 1 1 1 1 2 2 2 2/3* 1 2 2 TRAPA #x:2 Advanced Rev.6.00 Sep. 27, 2007 Page 1034 of 1268 REJ09B0220-0600 Appendix A Instruction Set Branch Instruction Address Fetch Read Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 1 3 2 1 2 J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Sep. 27, 2007 Page 1035 of 1268 REJ09B0220-0600 Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 Internal operation, 1 state 3 R:W EA 4 5 6 7 8 End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev.6.00 Sep. 27, 2007 Page 1036 of 1268 REJ09B0220-0600 Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1st byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) Rev.6.00 Sep. 27, 2007 Page 1037 of 1268 REJ09B0220-0600 2 3 4 5 6 7 8 9 Table A.6 R:W NEXT R:W 3rd R:W NEXT Appendix A Instruction Set R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Instruction Execution Cycles Rev.6.00 Sep. 27, 2007 Page 1038 of 1268 REJ09B0220-0600 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) 1 R:W NEXT R:W 2nd 4 5 6 7 8 9 BRN d:16 (BF d:16) R:W 2nd BHI d:16 R:W 2nd BLS d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd BCS d:16 (BLO d:16) R:W 2nd BNE d:16 R:W 2nd BEQ d:16 R:W 2nd BVC d:16 R:W 2nd BVS d:16 R:W 2nd BPL d:16 R:W 2nd BMI d:16 R:W 2nd BGE d:16 R:W 2nd BLT d:16 R:W 2nd BGT d:16 R:W 2nd BLE d:16 R:W 2nd 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1039 of 1268 REJ09B0220-0600 R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1040 of 1268 REJ09B0220-0600 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Advanced BSR d:8 Advanced BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 Rev.6.00 Sep. 27, 2007 Page 1041 of 1268 REJ09B0220-0600 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1042 of 1268 REJ09B0220-0600 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 ← Repeated n times*2 → R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC 1 2 R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:B EA R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:B EA R:W 2nd R:B EA R:W 2nd R:W 3rd R:W 2nd R:W 3rd Cannot be used in the chip CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA R:W NEXT 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 JMP @@aa:8 Advanced R:W NEXT JSR @ERn JSR @aa:24 Advanced R:W NEXT Advanced R:W 2nd JSR @@aa:8 Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR R:W 2nd Rev.6.00 Sep. 27, 2007 Page 1043 of 1268 REJ09B0220-0600 LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state Appendix A Instruction Set Instruction LDM.L @SP+,(ERn–ERn+2) R:W NEXT 1 R:W 2nd 2 R:W NEXT 6 7 8 9 LDM.L @SP+,(ERn–ERn+3) R:W 2nd 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state LDMAC ERs,MACH Cannot be used in the chip Appendix A Instruction Set LDMAC ERs,MACL Rev.6.00 Sep. 27, 2007 Page 1044 of 1268 REJ09B0220-0600 R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:B EA R:W NEXT R:B EA W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd R:W 2nd R:W 2nd R:W NEXT 4 R:W NEXT W:W EA Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd 1 R:W 2nd R:W 2nd R:W NEXT 3 W:W EA R:E 4th W:W EA 5 6 7 8 9 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd W:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA R:W NEXT R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the chip W:W EA+2 R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd Rev.6.00 Sep. 27, 2007 Page 1045 of 1268 REJ09B0220-0600 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Appendix A Instruction Set 2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn R:W EA+2 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT 3 4 5 6 7 8 9 Appendix A Instruction Set POP.L ERn R:W 2nd PUSH.W Rn W:W EA+2 R:W NEXT Rev.6.00 Sep. 27, 2007 Page 1046 of 1268 REJ09B0220-0600 R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state PUSH.L ERn R:W 2nd ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 2 R:W stack (EXR) R:W stack (H) R:W:M stack (H) R:W stack (L) R:W stack (L) Instruction ROTXR.L #2,ERd RTE Internal operation, R:W*4 1 state Internal operation, R:W*4 1 state 1 R:W NEXT R:W NEXT 3 4 5 6 7 8 9 RTS Advanced R:W NEXT SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1047 of 1268 REJ09B0220-0600 5 R:W NEXT R:W NEXT W:W EA W:W EA Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd W:W EA W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 Appendix A Instruction Set STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn–ERn+1),@–SP STM.L(ERn–ERn+2),@–SP Rev.6.00 Sep. 27, 2007 Page 1048 of 1268 REJ09B0220-0600 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state R:W NEXT R:W 3rd R:W NEXT STM.L(ERn–ERn+3),@–SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 Advanced 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the chip R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC R:W NEXT R:W VEC+2 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state 2 R:W NEXT 3 4 5 6 7 8 9 Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Advanced Reset exception handling Interrupt exception Advanced handling R:W*6 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt handling routine. 8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Appendix A Instruction Set Rev.6.00 Sep. 27, 2007 Page 1049 of 1268 REJ09B0220-0600 Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands m= 15 for word operands 7 for byte operands Si Di Ri Dn — The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev.6.00 Sep. 27, 2007 Page 1050 of 1268 REJ09B0220-0600 Appendix A Instruction Set Table A.7 Instruction ADD Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS ADDX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. ———— ————— ————— ———— ———— ———— ————— ———— ———— ————— ———— ————— ————— ————— —— —— C = C' · Dn C = C' · Dn C = Dn C = C' + Dn C = C' · Dn + C' · Dn C = Dn C = C' + Dn Z = Dn C = C' · Dn + C' · Dn ———— Rev.6.00 Sep. 27, 2007 Page 1051 of 1268 REJ09B0220-0600 Appendix A Instruction Set Instruction CLRMAC CMP H N Z V C Definition Cannot be used in the chip H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS DIVXU EEPMOV EXTS EXTU INC — — —— —— N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 N = Sm Z = Sm · Sm–1 · ...... · S0 ————— — —0 — 0 0 — — — N = Rm Z = Rm · Rm–1 · ...... · R0 Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm JMP JSR LDC LDM LDMAC MAC ————— Cannot be used in the chip ————— ————— Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev.6.00 Sep. 27, 2007 Page 1052 of 1268 REJ09B0220-0600 Appendix A Instruction Set Instruction MOV MOVFPE MOVTPE MULXS MULXU NEG — —— N = R2m Z = R2m · R2m–1 · ...... · R0 ————— H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL — — — 0 0 0 — — ————— — — 0 0 — — N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) H — N Z V 0 C — Definition N = Rm Z = Rm · Rm–1 · ...... · R0 Cannot be used in the chip Rev.6.00 Sep. 27, 2007 Page 1053 of 1268 REJ09B0220-0600 Appendix A Instruction Set Instruction ROTXL H — N Z V 0 C Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ————— — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift) C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR —0 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ————— ————— ————— Cannot be used in the chip Stores the corresponding bits of the result. Rev.6.00 Sep. 27, 2007 Page 1054 of 1268 REJ09B0220-0600 Appendix A Instruction Set Instruction SUB H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS SUBX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS TRAPA XOR XORC — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 ————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev.6.00 Sep. 27, 2007 Page 1055 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 List of Registers (Address Order) Register Name MRA SAR Module Name DTC Data Bus Width 16/ 1 32* bits Address H'F800 to H'FBFF Bit 7 SM1 Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz MRB DAR CHNE DISEL CHNS — — — — — CRA CRB H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 CCLR2 — IOB3 IOD3 TTGE — CCLR1 — IOB2 IOD2 — — CCLR0 BFB IOB1 IOD1 — — CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16 bits TGR3A TGR3B TGR3C TGR3D Rev.6.00 Sep. 27, 2007 Page 1056 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width 16 bits Address H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB4 H'FEB5 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF Register Name TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 Bit 7 — — IOB3 TTGE TCFD Bit 6 CCLR1 — IOB2 — — Bit 5 CCLR0 — IOB1 TCIEU TCFU Bit 4 CKEG1 — IOB0 TCIEV TCFV Bit 3 CKEG0 MD3 IOA3 — — Bit 2 TPSC2 MD2 IOA2 — — Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU4 TGR4A TGR4B TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 16 bits TGR5A TGR5B P1DDR P2DDR P3DDR P5DDR P6DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PGDDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Ports P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR — — — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR — — P53DDR P52DDR P51DDR P50DDR 8 bits P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Rev.6.00 Sep. 27, 2007 Page 1057 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width Address H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 H'FEDB H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FEE4 H'FEE5 H'FEE6 H'FEE7 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF Register Name IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ABWCR ASTCR WCRH WCRL BCRH BCRL MCR Bit 7 — — — — — — — — — — — ABW7 AST7 W71 W31 ICIS1 BRLE TPC RFSHE Bit 6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 Bit 5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 Bit 4 IPR4 IPR4 IPR4 IPR4 I PR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 Bit 3 — — — — — — — — — — — ABW3 AST3 W51 W11 DDS*2 MXC1 CMIE Bit 2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 Bit 1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 Bit 0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 Module Name Interrupt 8 bits controller Bus 8 bits controller BRSTRM BRSTS1 BRSTS0 RMTS2*2 RMTS1*2 RMTS0*2 — — — MXC0 CKS2 W DBE*2 WAITE RLW1 CKS1 RLW0 CKS0 BREQOE EAE BE RCW RCDM *3 *3 DRAMCR RMODE CMF RTCNT*3 RTCOR RAMER*4 — MAR0AH — — — — — — — RAMS — RAM2 — RAM1 — RAM0 — Flash memory 8 bits DMAC*5 16 bits MAR0AL IOAR0A ETCR0A MAR0BH — — — — — — — — MAR0BL IOAR0B ETCR0B Rev.6.00 Sep. 27, 2007 Page 1058 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width 5 Address H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FEFE H'FEFF H'FF00 H'FF01 H'FF02 Register Name MAR1AH Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module Name DMAC* 16 bits MAR1AL IOAR1A ETCR1A MAR1BH — — — — — — — — MAR1BL IOAR1B ETCR1B DMAWER — DMATCR — — — DTID — TEE1 RPE — TEE0 DTDIR WE1B — DTF3 WE1A — DTF2 WE0B — DTF1 WE0A — DTF0 Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode 8 bits DMACR0A DTSZ 16 bits DTSZ SAID SAIDE BLKDIR BLKE — — — H'FF03 DMACR0B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 H'FF04 DMACR1A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DTSZ SAID SAIDE BLKDIR BLKE — — — H'FF05 DMACR1B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Rev.6.00 Sep. 27, 2007 Page 1059 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width Address H'FF06 Register Name Bit 7 Bit 6 FAE0 Bit 5 SAE1 Bit 4 SAE0 Bit 3 DTA1B Bit 2 DTA1A Bit 1 DTA0B Bit 0 DTA0A Module Name Short address mode Full address mode Short address mode Full address mode DMABCRH FAE1 FAE1 FAE0 — — DTA1 — DTA0 — H'FF07 DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A H'FF2C H'FF2D H'FF2E H'FF2F H'FF30 to H'FF35 H'FF37 H'FF38 ISCRH ISCRL IER ISR DTCER IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt 8 bits IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA controller IRQ7E IRQ7F DTCE7 IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC 8 bits DTVECR SBYCR SWDTE SSBY DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 STS2 STS1 STS0 OPE — — IRQ37S Powerdown mode MCU 8 bits H'FF39 H'FF3A SYSCR SCKCR — PSTOP — — INTM1 DIV INTM0 — NMIEG — LWROD IRQPAS RAME SCK2 SCK1 SCK0 8 bits Clock 8 bits pulse generator MCU Powerdown mode MCU 8 bits 8 bits H'FF3B H'FF3C H'FF3D H'FF42 H'FF44 HFF45 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4C *6 H'FF4D *6 H'FF4E*6 H'FF4F*6 MDCR — — — — — MDS2 MDS1 MDS0 MSTP8 MSTP0 — — A20E MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 SYSCR2*4 — Reserved PFCR1 PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL — — MSTP6 — — — MSTP5 — — — MSTP4 — — — MSTP3 FLSHE — A23E MSTP2 — — A22E MSTP1 — — A21E 8 bits Reserved — Port 8 bits 8 bits G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 POD15 POD7 NDR15 NDR7 — — NDER6 POD14 POD6 NDR14 NDR6 — — NDER5 POD13 POD5 NDR13 NDR5 — — NDER4 POD12 POD4 NDR12 NDR4 — — NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 Rev.6.00 Sep. 27, 2007 Page 1060 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width 8 bits Address H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 Register Name PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR Bit 7 P17 P27 — P47 — P67 PA7 PB7 PC7 PD7 PE7 PF7 — P17DR P27DR — — P67DR PA7DR PB7DR PC7DR PD7DR PE7DR PF7DR — Bit 6 P16 P26 — P46 — P66 PA6 PB6 PC6 PD6 PE6 PF6 — P16DR P26DR — — P66DR PA6DR PB6DR PC6DR PD6DR PE6DR PF6DR — Bit 5 P15 P25 P35 P45 — P65 PA5 PB5 PC5 PD5 PE5 PF5 — P15D R P25DR P35DR — P65DR PA5DR PB5DR PC5DR PD5DR PE5DR PF5DR — Bit 4 P14 P24 P34 P44 — P64 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR — P64DR PA4DR PB4DR PC4DR PD4DR PE4DR PF4DR PG4DR Bit 3 P13 P23 P33 P43 P53 P63 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR PG3DR Bit 2 P12 P22 P32 P42 P52 P62 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR PA2DR PB2DR PC2DR PD2DR PE2DR PF2DR PG2DR Bit 1 P11 P21 P31 P41 P51 P61 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR PA1DR PB1DR PC1DR PD1DR PE1DR PF1DR PG1DR Bit 0 P10 P20 P30 P40 P50 P60 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR PG0DR Module Name Ports PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Rev.6.00 Sep. 27, 2007 Page 1061 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width Address H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA4 H'FFA5 H'FFA6 Register Name SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR01 Bit 7 C/A/ 7 GM* Bit 6 CHR/ 8 BLK* Bit 5 PE Bit 4 O/E Bit 3 Bit 2 Bit 1 Bit 0 CKS0 Module Name STOP/ MP/ CKS1 9 10 BCP1* BCP0* 8 bits SCI0, smart card interface 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS*11 PER TEND MPB MPBT — C/A/ GM*7 — CHR/ BLK*8 — PE — O/E SDIR SINV — SMIF CKS0 SCI1, 8 bits smart card interface 1 STOP/ MP/ CKS1 BCP1*9 BCP0*10 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ 11 ERS* PER TEND MPB MPBT — C/A/ 7 GM* — CHR/ 8 BLK* — PE — O/E SDIR SINV — SMIF CKS0 8 bits SCI2, smart card interface 2 STOP/ MP/ CKS1 9 10 BCP1* BCP0* TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS*11 PER TEND MPB MPBT — AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 — AD7 — AD7 — AD7 — AD7 — ADST — — AD6 — AD6 — AD6 — AD6 — SCAN — SDIR AD5 — AD5 — AD5 — AD5 — CKS CKS1 SINV AD4 — AD4 — AD4 — AD4 — CH2 CH3 — AD3 — AD3 — AD3 — AD3 — CH1 — SMIF AD2 — AD2 — AD2 — AD2 — CH0 — D/A 8 bits converter 8 bits A/D converter DAOE1 DAOE0 DAE — — — — — Rev.6.00 Sep. 27, 2007 Page 1062 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width 8 bits 16 bits Address H'FFAC H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBC (read) H'FFBD (read) H'FFBF (read) H'FFC0 H'FFC1 Register Name PFCR2 TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR TCNT RSTCSR TSTR TSYR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ASOD CCLR0 CCLR0 OS3 OS3 Bit 2 — CKS2 CKS2 OS2 OS2 Bit 1 — CKS1 CKS1 OS1 OS1 Bit 0 — CKS0 CKS0 OS0 OS0 Module Name Ports 8-bit timer channel 0, 1 WAITPS BREQOPS CS167E CS25E CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE — OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT 16 bits WOVF — — FWE FLER EB7 — FWE FLER EB7 — FWE FLER EB7 EB15 RSTE — — SWE — EB6 — SWE — EB6 — SWE1 SWE2 EB6 EB14 — CST5 SYNC5 ESU — EB5 — ESU — EB5 EB13 ESU1 ESU2 EB5 EB13 — CST4 SYNC4 PSU — EB4 — PSU — EB4 EB12 PSU1 PSU2 EB4 EB12 — CST3 SYNC3 EV — EB3 EB11 EV — EB3 EB11 EV1 EV2 EB3 EB11 — CST2 SYNC2 PV — EB2 EB10 PV — EB2 EB10 PV1 PV2 EB2 EB10 — CST1 SYNC1 E — EB1 EB9 E — EB1 EB9 E1 E2 EB1 EB9 — CST0 SYNC0 P — EB0 EB8 P — EB0 EB8 P1 P2 EB0 EB8 8 bits Flash memory (H8S/2326 F-ZTAT) Flash 8 bits memory (H8S/2329 F-ZTAT) Flash 8 bits memory (H8S/2328 F-ZTAT) TPU 16 bits H'FFC8*12 FLMCR1 H'FFC9*12 FLMCR2 H'FFCA*12 EBR1 H'FFCB*12 EBR2 H'FFC8*13 FLMCR1 H'FFC9*13 FLMCR2 H'FFCA*13 EBR1 H'FFCB*13 EBR2 H'FFC8*14 FLMCR1 H'FFC9*14 FLMCR2 H'FFCA*14 EBR1 H'FFCB*14 EBR2 Rev.6.00 Sep. 27, 2007 Page 1063 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Data Bus Width 16 bits Address H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB Register Name TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 Bit 7 CCLR2 — IOB3 IOD3 TTGE — Bit 6 CCLR1 — IOB2 IOD2 — — Bit 5 CCLR0 BFB IOB1 IOD1 — — Bit 4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name TPU0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 16 bits TGR1A TGR1B TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 16 bits TGR2A TGR2B Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. Rev.6.00 Sep. 27, 2007 Page 1064 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers 2. 3. 4. 5. 6. Reserved bit in the H8S/2321. Reserved in the H8S/2321. Valid only in F-ZTAT versions. The DMAC is not supported in the H8S/2321. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. Functions as C/A for SCI use, and as GM for smart card interface use. Functions as CHR for SCI use, and as BLK for smart card interface use. Functions as STOP for SCI use, and as BCP1 for smart card interface use. Functions as MP for SCI use, and as BCP0 for smart card interface use. Functions as FER for SCI use, and as ERS for smart card interface use. Applies to the H8S/2328B F-ZTAT. Applies to the H8S/2329B F-ZTAT. Applies to the H8S/2326 F-ZTAT. 7. 8. 9. 10. 11. 12. 13. 14. Rev.6.00 Sep. 27, 2007 Page 1065 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers B.2 Module Interrupt controller List of Registers (By Module) Register System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Abbreviation R/W SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK ABWCR ASTCR WCRH WCRL BCRH BCRL 6 MCR* 6 DRAMCR* 6 RTCNT* 6 RTCOR* Initial Value Address* H'01 H'00 H'00 H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE *5 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'00 2 R/(W)* H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'FF/H'00 H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF Bus controller Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Memory control register DRAM control register Refresh timer counter Refresh time constant register Rev.6.00 Sep. 27, 2007 Page 1066 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Module DTC Register DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable register DTC vector register Module stop control register DMAC0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 7 DMAC1* Abbreviation R/W MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR MSTPCR —* 3 —* 3 —* 3 Initial Value Address* Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3FFF —* 4 —* —* 4 —* —* 4 —* H'FF30 to H'FF35 H'FF37 H'FF3C H'FEE0 H'FEE4 H'FEE6 H'FEE8 H'FEEC H'FEEE H'FEF0 H'FEF4 H'FEF6 H'FEF8 H'FEFC H'FEFE H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF3C 4 4 4 1 —* 3 —* —* 3 3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B Both DMA write enable register DMAC 7 DMA terminal control register channels* DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Module stop control register Rev.6.00 Sep. 27, 2007 Page 1067 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Module TPU0 Register Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Timer interrupt enable register 0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D TPU1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B TPU2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B Abbreviation R/W TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B R/W R/W R/W R/W R/W Initial Value Address* H'00 H'C0 H'00 H'00 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA 1 H'40 *2 H'C0 R/(W) R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 *2 H'C0 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/W R/W R/W R/W R/W R/W H'40 *2 H'C0 R/(W) R/W H'0000 H'FFFF H'FFFF R/W R/W Rev.6.00 Sep. 27, 2007 Page 1068 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Module TPU3 Register Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Timer interrupt enable register 3 Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D TPU4 Timer control register 4 Timer mode register 4 Timer I/O control register 4 Timer interrupt enable register 4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B TPU5 Timer control register 5 Timer mode register 5 Timer I/O control register 5 Timer interrupt enable register 5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B ALL TPU channels Timer start register Timer syncro register Module stop control register Abbreviation R/W TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCR R/W R/W R/W R/W R/W Initial Value Address* H'00 H'C0 H'00 H'00 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FFC0 H'FFC1 H'FF3C 1 H'40 *2 H'C0 R/(W) R/W H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 *2 H'C0 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/W R/W R/W R/W R/W R/W H'40 *2 H'C0 R/(W) R/W H'0000 H'FFFF H'FFFF H'00 H'00 H'3FFF R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1069 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Module PPG Register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Port 1 data direction register Port 2 data direction register Module stop control register 8-bit timer 0 Timer control register 0 Timer control/status register 0 Timer constant register A0 Timer constant register B0 Timer counter 0 8-bit timer 1 Timer control register 1 Timer control/status register 1 Timer constant register A1 Timer constant register B1 Timer counter 1 Both 8-bit timer channels Module stop control register Abbreviation R/W PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL P1DDR P2DDR MSTPCR TCR0 TCSR0 TCORA0 TCORB0 TCNT0 TCR1 TCSR1 TCORA1 TCORB1 TCNT1 MSTPCR R/W R/W R/W R/W 8 Initial Value Address* H'FF H'F0 H'00 H'00 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4C* H'FF4E 9 H'FF4D* H'FF4F H'FEB0 H'FEB1 H'FF3C H'FFB0 H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB1 H'FFB3 H'FFB5 H'FFB7 H'FFB9 H'FF3C 9 1 R/(W)* H'00 8 R/(W)* H'00 R/W R/W W W R/W R/W R/(W) R/W R/W R/W R/W R/(W) R/W R/W R/W R/W *10 *10 H'00 H'00 H'00 H'00 H'3FFF H'00 H'00 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'3FFF Rev.6.00 Sep. 27, 2007 Page 1070 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Module WDT Register Timer control/status register Abbreviation R/W TCSR Initial Value Address* H'FFBC: 11 Write* H'FFBC: Read Timer counter TCNT R/W H'00 H'FFBC: 8 Write* H'FFBD: Read Reset control/status register RSTCSR R/(W)* 12 1 12 R/(W)* H'18 H'1F H'FFBE: 11 Write* H'FFBF: Read SCI0 Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W) R R/W R/W R/W R/W R/W R R/W *2 2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCI1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 SCI2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 H'FF *2 H'84 R/(W) H'00 H'F2 Rev.6.00 Sep. 27, 2007 Page 1071 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Module All SCI channels SMCI0 Register Module stop control register Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register SMCI1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 SMCI2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 All SMCI channels Module stop control register Abbreviation R/W MSTPCR SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 Initial Value Address* H'3FFF H'00 H'FF H'00 H'FF3C H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C 1 H'FF *2 H'84 R/(W) H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'3FFF Rev.6.00 Sep. 27, 2007 Page 1072 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Module ADC Register A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register DAC D/A data register 0 D/A data register 1 D/A control register 01 Module stop control register On-chip RAM Flash memory System control register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Clock pulse generator Powerdown mode System clock control register Abbreviation R/W ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR DADR0 DADR1 DACR01 MSTPCR SYSCR FLMCR1 * 17 FLMCR2 * EBR1* 17 EBR2* RAMER* 18 SYSCR2 * SCKCR 22 17 17 Initial Value Address* H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 12 1 R R R R R R R R R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W * 14 R/W * R/W * 14 R/W * R/W R/W R/W 14 14 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C H'FFA4 H'FFA5 H'FFA6 H'FF3C H'FF39 15 H'00 H'3F H'3FFF H'00 H'00 H'1F H'3FFF H'01 H'00/H'80* H'00 H'00* 16 H'00* H'00 H'00 H'00 16 H'FFC8* 13 H'FFC9* H'FFCA* 13 H'FFCB* H'FEDB H'FF42 H'FF3A 13 13 Standby control register System clock control register Module stop control register H Module stop control register L SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W H'08 H'00 H'3F H'FF H'FF38 H'FF3A H'FF3C H'FF3D Rev.6.00 Sep. 27, 2007 Page 1073 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers Module Port 1 Register Port 1 data direction register Port 1 data register Port 1 register Port 2 Port 2 data direction register Port 2 data register Port 2 register Port 3 Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register Port 4 Port 5 Port 4 register Port 5 data direction register Port 5 data register Port 5 register Port function control register 2 System control register Port 6 Port 6 data direction register Port 6 data register Port 6 register Port function control register 2 Port A Port A data direction register Port A data register Port A register Port A open drain control register Port function control register 1 Port B Port B data direction register Port B data register Port B register Abbreviation R/W P1DDR P1DR PORT1 P2DDR P2DR PORT2 P3DDR P3DR PORT3 P3ODR PORT4 P5DDR P5DR PORT5 PFCR2 SYSCR P6DDR P6DR PORT6 PFCR2 PADDR PADR PORTA PAODR PFCR1 PBDDR PBDR PORTB W R/W R W R/W R W R/W R R/W R W R/W R R/W R/W W R/W R R/W W R/W R R/W R/W R/W W R/W R R/W Initial Value Address* H'00 H'00 Undefined H'00 H'00 Undefined H'00 H'00 Undefined H'00 Undefined 19 H'0* 19 H'0* 1 H'FEB0 H'FF60 H'FF50 H'FEB1 H'FF61 H'FF51 H'FEB2 H'FF62 H'FF52 H'FF76 H'FF53 H'FEB4 H'FF64 H'FF54 H'FFAC H'FF39 H'FEB5 H'FF65 H'FF55 H'FFAC H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77 H'FF45 H'FEBA H'FF6A H'FF5A H'FF71 Undefined H'30 H'01 H'00 H'00 Undefined H'30 H'00 H'00 Undefined H'00 H'00 H'0F H'00 H'00 Undefined H'00 Port A MOS pull-up control register PAPCR Port B MOS pull-up control register PBPCR Rev.6.00 Sep. 27, 2007 Page 1074 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Module Port C Register Port C data direction register Port C data register Port C register Port D Port D data direction register Port D data register Port D register Port E Port E data direction register Port E data register Port E register Port F Port F data direction register Port F data register Port F register Port function control register 2 System control register Port G Port G data direction register Port G data register Port G register Port function control register 2 Notes: 1. 2. 3. 4. Abbreviation R/W PCDDR PCDR PORTC PDDDR PDDR PORTD PEDDR PEDR PORTE PFDDR PFDR PORTF PFCR2 SYSCR PGDDR PGDR PORTG PFCR2 W R/W R R/W W R/W R R/W W R/W R R/W W R/W R R/W R/W W R/W R R/W Initial Value Address* H'00 H'00 Undefined H'00 H'00 H'00 Undefined H'00 H'00 H'00 Undefined H'00 H'FEBB H'FF6B H'FF5B H'FF72 H'FEBC H'FF6C H'FF5C H'FF73 H'FEBD H'FF6D H'FF5D 1 Port C MOS pull-up control register PCPCR Port D MOS pull-up control register PDPCR Port E MOS pull-up control register PEPCR H'FF74 *20 H'FEBE H'80/H'00 H'00 Undefined H'30 H'01 H'10/H'00 *20 *21 H'00* H'30 21 H'FF6E H'FF5E H'FFAC H'FF39 H'FEBF H'FF6F *21 H'FF5F H'FFAC Undefined 5. 6. 7. 8. Lower 16 bits of the address. Only 0 can be written for flag clearing. Registers in the DTC cannot be read or written to directly. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when using the DTC. Determined by the MCU operating mode. Reserved in the H8S/2321. The DMAC is not supported in the H8S/2321. Bits used for pulse output cannot be written to. Rev.6.00 Sep. 27, 2007 Page 1075 of 1266 REJ09B0220-0600 Appendix B Internal I/O Registers 9. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. Only 0 can be written to bits 7 to 5, to clear the flags. For information on writing, see section 13.2.4, Notes on Register Access. Only 0 can be written to bit 7, to clear the flag. Flash memory registers selection is performed by means of the FLSHE bit in system control register 2 (SYSCR2). In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared to 0 (except in the H8S/2329B F-ZTAT). In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, the initial value when a high level is input to the FWE is H'80. The initial value in the H8S/2329B F-ZTAT is H'80. In the H8S/2328B F-ZTAT, this register is initialized to H'00 when a low level is input to the FWE pin, or when a high level is input to the FWE pin when the SWE bit in FLMCR1 is not set. In the H8S/2329B F-ZTAT, this register is initialized to H'00 when the SWE bit in FLMCR1 is not set. In the H8S/2326 F-ZTAT, bits EB11 to EB0 are initialized to 0 when a low level is input to the FWE pin, or a high level is input and the SWE1 bit in FLMCR1 is not set. Bits EB15 to EB12 are initialized to 0 when a low level is input to the FWE pin, or a high level is input and the SWE2 bit is not set. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be used on these registers, with the access requiring two states. (Applies to the H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT.) The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be written to. Value of bits 3 to 0. The initial value depends on the mode. Value of bits 4 to 0. Valid only in the F-ZTAT versions. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. Rev.6.00 Sep. 27, 2007 Page 1076 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers B.3 Functions H'F800—H'FBFF 5 DM1 — 4 DM0 — 3 MD1 — 2 MD0 — 1 DTS — 0 Sz — MRA—DTC Mode Register A Bit : 7 SM1 Initial value : Read/Write : — 6 SM0 — DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 — 0 1 Source Address Mode 0 1 — 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Normal mode Repeat mode Block transfer mode — Destination side is repeat area or block area Source side is repeat area or block area Rev.6.00 Sep. 27, 2007 Page 1077 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers MRB—DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : — 6 DISEL — 5 CHNS — 4 — — H'F800—H'FBFF 3 — — 2 — — 1 — — 0 — — DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reserved Only 0 should be written to these bits DTC Chain Transfer Select DTC Interrupt Select 0 1 After DTC data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After DTC data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable CHNE CHNS 0 1 1 — 0 1 Description No chain transfer. (At end of DTC data transfer, DTC waits for activation) Chain transfer every time Chain transfer only when transfer counter = 0 SAR—DTC Source Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 2 1 0 DTC Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies DTC transfer data source address DAR—DTC Destination Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 2 1 0 DTC Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies DTC transfer data destination address Rev.6.00 Sep. 27, 2007 Page 1078 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers CRA—DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'F800—H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'F800—H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Specifies the number of DTC block data transfers Rev.6.00 Sep. 27, 2007 Page 1079 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR3—Timer Control Register 3 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FE80 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU3 CKEG1 CKEG0 R/W Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096 1 0 0 1 1 0 1 Rev.6.00 Sep. 27, 2007 Page 1080 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR3—Timer Mode Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W H'FE81 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU3 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev.6.00 Sep. 27, 2007 Page 1081 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR3H—Timer I/O Control Register 3H Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FE82 1 IOA1 0 R/W 0 IOA0 0 R/W TPU3 Initial value : TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don’t care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 * : Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture does not occur. TGR3B Output disabled is output compare Initial output is register 0 output TGR3A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Sep. 27, 2007 Page 1082 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR3L—Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 H'FE83 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 IOC2 0 R/W TGR3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 1 0 output 0 register* 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C Capture input is input source is 1 capture TIOCC pin 3 1 * register* * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don’t care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare does not occur. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is input capture register *2 Capture input source is TIOCD3 pin Capture input source is channel 4/count clock TGR3D Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match *2 Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 * : Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture does not occur. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare does not occur. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev.6.00 Sep. 27, 2007 Page 1083 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER3—Timer Interrupt Enable Register 3 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 TGIED 0 R/W H'FE84 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU3 TGR Interrupt Enable A 0 1 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt request (TGIC) by TGFC bit disabled Interrupt request (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt request (TGID) by TGFD bit disabled Interrupt request (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1084 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR3—Timer Status Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* H'FE85 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT=TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1085 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT3—Timer Counter 3 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FE86 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU3 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE88 H'FE8A H'FE8C H'FE8E 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU3 TPU3 TPU3 TPU3 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1086 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR4—Timer Control Register 4 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FE90 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU4 CKEG1 CKEG0 Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Counter Clear 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev.6.00 Sep. 27, 2007 Page 1087 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR4—Timer Mode Register 4 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FE91 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU4 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Sep. 27, 2007 Page 1088 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR4—Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FE92 1 IOA1 0 R/W 0 IOA0 0 R/W TPU4 IOA2 0 R/W TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture * : Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture * : Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 Rev.6.00 Sep. 27, 2007 Page 1089 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER4—Timer Interrupt Enable Register 4 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FE94 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU4 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1090 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR4—Timer Status Register 4 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FE95 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1091 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT4—Timer Counter 4 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FE96 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU4 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE98 H'FE9A 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU4 TPU4 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1092 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR5—Timer Control Register 5 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FEA0 2 TPSC2 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 TPU5 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 5 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev.6.00 Sep. 27, 2007 Page 1093 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR5—Timer Mode Register 5 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FEA1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU5 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Sep. 27, 2007 Page 1094 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR5—Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FEA2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU5 IOA2 0 R/W TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Capture input source is TIOCA5 Input capture at falling edge pin Input capture at both edges * : Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCB5 Input capture at falling edge pin Input capture at both edges * : Don’t care TGR5B Output disabled is output compare Initial output is 0 register output 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Sep. 27, 2007 Page 1095 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER5—Timer Interrupt Enable Register 5 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FEA4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU5 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1096 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR5—Timer Status Register 5 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FEA5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU5 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1097 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT5—Timer Counter 5 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FEA6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU5 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FEA8 H'FEAA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU5 TPU5 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1DDR—Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB0 3 0 W 2 0 W 1 0 W 0 0 W Port 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : Specify input or output for individual port 1 pins Rev.6.00 Sep. 27, 2007 Page 1098 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers P2DDR—Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB1 3 0 W 2 0 W 1 0 W 0 0 Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : W Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register Bit : 7 — Initial value : Read/Write : — 6 — — 5 0 W 4 0 W H'FEB2 3 0 W 2 0 W 1 0 W 0 0 Port 3 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Undefined Undefined Specify input or output for individual port 3 pins P5DDR—Port 5 Data Direction Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 — — H'FEB4 3 0 W 2 0 W 1 0 W 0 0 W Port 5 P53DDR P52DDR P51DDR P50DDR Initial value : Undefined Undefined Undefined Undefined Specify input or output for individual port 5 pins Rev.6.00 Sep. 27, 2007 Page 1099 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers P6DDR—Port 6 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB5 3 0 W 2 0 W 1 0 W Port 6 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : Read/Write : Specify input or output for individual port 6 pins PADDR—Port A Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB9 3 0 W 2 0 W 1 0 W Port A 0 0 W PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Specify input or output for individual port A pins PBDDR—Port B Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBA 3 0 W 2 0 W 1 0 W 0 0 W Port B PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Specify input or output for individual port B pins Rev.6.00 Sep. 27, 2007 Page 1100 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PCDDR—Port C Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBB 3 0 W 2 0 W 1 0 W Port C 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Specify input or output for individual port C pins PDDDR—Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBC 3 0 W 2 0 W 1 0 W Port D 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specify input or output for individual port D pins PEDDR—Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBD 3 0 W 2 0 W 1 0 W Port E 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specify input or output for individual port E pins Rev.6.00 Sep. 27, 2007 Page 1101 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PFDDR—Port F Data Direction Register Bit Modes 4 to 6 Initial value Read/Write Mode 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W : 7 6 5 4 H'FEBE 3 2 1 0 Port F PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for individual port F pins PGDDR—Port G Data Direction Register Bit : 7 — Modes 4 and 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : — — — 1 W 0 W 6 — 5 — 4 H'FEBF 3 2 1 Port G 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 6 and 7 : Undefined Undefined Undefined : — — — Specify input or output for individual port G pins Rev.6.00 Sep. 27, 2007 Page 1102 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Bit — — — — — — — — — — — Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K : 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE 3 — 0 — 2 IPR2 1 R/W Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : Read/Write : Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT —*1 TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC*2 SCI channel 1 Refresh timer*2 A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IRQ1 IRQ4 IRQ5 DTC 2 to 0 Notes: 1. Reserved bits. 2. Reserved bit in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 1103 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ABWCR—Bus Width Control Register Bit : 7 ABW7 Modes 5 to 7 Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4 ABW4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 Bus Controller 0 ABW0 1 R/W 0 R/W ABW1 1 R/W 0 R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR—Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0) Rev.6.00 Sep. 27, 2007 Page 1104 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers WCRH—Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 H'FED2 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bus Controller W51 1 R/W Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.6.00 Sep. 27, 2007 Page 1105 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers WCRL—Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 H'FED3 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bus Controller W11 1 R/W Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.6.00 Sep. 27, 2007 Page 1106 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers BCRH—Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 0 R/W RAM Type Select Bus Controller 1 RMTS1 0 R/W 0 RMTS0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 1 1 0 1 1 — — Normal space Normal space Normal space DRAM space DRAM space DRAM space — Notes: 1. When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT. When PF2 is used as the WAIT pin in the H8S/2323, normal space other than DRAM space should be designated as 16-bit-bus space. RAS down mode cannot be used when this setting is made. Sample settings are shown below. RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 0 0 0 1 1 0 1 Area 2 Normal space Normal space DRAM space (16-bit bus) (8-bit bus) Normal space DRAM space (16-bit bus) (8-bit bus) DRAM space (8-bit bus) 2. In the H8S/2321 these bits are reserved and should only be written with 0. Burst Cycle Select 0 0 1 0 1 0 1 0 1 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Area 0 Burst ROM Enable Basic bus interface Burst ROM interface Idle Cycle Insert 0 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Rev.6.00 Sep. 27, 2007 Page 1107 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers BCRL—Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 — 1 R/W H'FED5 3 DDS 1 R/W 2 — 1 R/W 1 WDBE 0 R/W 0 Bus Controller WAITE 0 R/W WAIT Pin Enable 0 1 Wait input by WAIT pin* disabled Wait input by WAIT pin* enabled Note: * The WAIT input pin can be switched between PF2 and P53 by means of WAITPS. Write Data Buffer Enable 0 Write data buffer function not used 1 Write data buffer function used Reserved Only 1 should be written to this bit DACK Timing Select 0 When DMAC single address transfer is performed in DRAM space, full access is always executed. DACK signal goes low from Tr or T1 cycle Burst access is possible when DMAC single address transfer is performed in DRAM space. DACK signal goes low from Tc1 or T2 cycle 1 Note: In the H8S/2321 this bit is reserved and should only be written with 1. Reserved Only 1 should be written to this bit External Addresses H'010000 to H'03FFFF Enable 0 • In the H8S/2329B, H8S/2328*3, and H8S/2326, addresses H'010000 to H'03FFFF*2 are on-chip ROM • In the H8S/2327, addresses H'010000 to H'01FFFF are on-chip ROM, and addresses H'020000 to H'03FFFF are a reserved area*1 • In the H8S/2323, addresses H'010000 to H'03FFFF are a reserved area*1 1 Addresses H'010000 to H'03FFFF*2 are external addresses in external expanded mode or reserved area*2 in single-chip mode Notes: 1. Do not access a reserved area. 2. Address H'010000 to H'03FFFF in the H8S/2328. Address H'010000 to H'05FFFF in the H8S/2329B. Address H'010000 to H'07FFFF in the H8S/2326. 3. H8S/2328B in flash memory version. BREQO Pin Enable 0 BREQO output disabled 1 BREQO* output enabled Note: * The BREQO output pin can be switched between PF2 and P53 by means of BREQOPS. Bus Release Enable External bus release disabled 0 1 External bus release enabled Rev.6.00 Sep. 27, 2007 Page 1108 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers MCR—Memory Control Register (Not supported in H8S/2321) Bit : 7 TPC Initial value : Read/Write : 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 — 0 R/W H'FED6 Bus Controller 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Refresh Cycle Wait Control 0 0 1 1 0 1 Multiplex Shift Count 0 0 1 1 0 1 Reserved RAS Down Mode 0 1 RAS up mode selected for DRAM interface RAS down mode selected for DRAM interface 8-bit shift 9-bit shift 10-bit shift — No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted Burst Access Enable 0 1 TP Cycle Control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted Burst disabled (always full access) For DRAM space access, access in fast page mode Rev.6.00 Sep. 27, 2007 Page 1109 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DRAMCR—DRAM Control Register (Not supported in H8S/2321) Bit : 7 RFSHE Initial value : Read/Write : 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W H'FED7 Bus Controller 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Refresh Counter Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Count operation disabled Count uses φ/2 Count uses φ/8 Count uses φ/32 Count uses φ/128 Count uses φ/512 Count uses φ/2048 Count uses φ/4096 Compare Match Interrupt Enable 0 1 Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled Compare Match Flag 0 [Clearing condition] When 0 is written to CMF after reading CMF = 1 [Setting condition] When RTCNT = RTCOR 1 Refresh Mode 0 1 RAS-CAS Wait 0 1 Self-refreshing is not performed in software standby mode Self-refreshing is performed in software standby mode Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in Tr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in Tc1 cycle Refresh Control 0 1 Refresh control is not performed Refresh control is performed Rev.6.00 Sep. 27, 2007 Page 1110 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers RTCNT—Refresh Timer Counter (Not supported in H8S/2321) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FED8 Bus Controller 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : Read/Write : Internal clock count value RTCOR—Refresh Time Constant Register (Not supported in H8S/2321) Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FED9 Bus Controller 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the period for compare match operations with RTCNT Rev.6.00 Sep. 27, 2007 Page 1111 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers RAMER—RAM Emulation Register (Valid only in F-ZTAT version) Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 — 0 — 4 — 0 — H'FEDB Bus Controller 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W RAM Select, Flash Memory Area Select RAMS RAM2 RAM1 RAM0 0 1 * 0 * 0 1 1 0 1 * 0 1 0 1 0 1 0 1 RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) *: Don't care Rev.6.00 Sep. 27, 2007 Page 1112 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers MAR0AH—Memory Address Register 0AH (Not supported in H8S/2321) MAR0AL—Memory Address Register 0AL (Not supported in H8S/2321) Bit MAR0AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 * H'FEE0 H'FEE2 DMAC DMAC 24 — 0 23 * 22 * 21 * 20 * 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR0AL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address IOAR0A—I/O Address Register 0A (Not supported in H8S/2321) Bit IOAR0A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE4 DMAC 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Rev.6.00 Sep. 27, 2007 Page 1113 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ETCR0A—Transfer Count Register 0A (Not supported in H8S/2321) Bit ETCR0A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE6 DMAC 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Block transfer mode Transfer counter Transfer number storage register Block size storage register Transfer counter Block size counter * : Undefined MAR0BH—Memory Address Register 0BH (Not supported in H8S/2321) MAR0BL—Memory Address Register 0BL (Not supported in H8S/2321) Bit MAR0BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 * H'FEE8 H'FEEA DMAC DMAC 24 — 0 23 * 22 * 21 * 20 * 19 * 18 * 17 16 * * Initial value : Read/Write : Bit MAR0BL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Rev.6.00 Sep. 27, 2007 Page 1114 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers IOAR0B—I/O Address Register 0B (Not supported in H8S/2321) Bit IOAR0B : : 15 14 13 12 11 10 9 8 H'FEEC DMAC 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR0B—Transfer Count Register 0B (Not supported in H8S/2321) Bit ETCR0B : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEEE DMAC 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Repeat mode Transfer number storage register Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. Transfer counter Transfer counter Rev.6.00 Sep. 27, 2007 Page 1115 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers MAR1AH—Memory Address Register 1AH (Not supported in H8S/2321) MAR1AL—Memory Address Register 1AL (Not supported in H8S/2321) Bit MAR1AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 * H'FEF0 H'FEF2 DMAC DMAC 24 — 0 23 * 22 * 21 * 20 * 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR1AL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address IOAR1A—I/O Address Register 1A (Not supported in H8S/2321) Bit IOAR1A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEF4 DMAC 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Rev.6.00 Sep. 27, 2007 Page 1116 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ETCR1A—Transfer Count Register 1A (Not supported in H8S/2321) Bit ETCR1A : : * * * * * * * 15 14 13 12 11 10 9 H'FEF6 DMAC 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register Block size counter * : Undefined Transfer counter Transfer counter MAR1BH—Memory Address Register 1BH (Not supported in H8S/2321) MAR1BL—Memory Address Register 1BL (Not supported in H8S/2321) Bit MAR1BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * 26 — 0 — 10 * 25 — 0 — 9 * H'FEF8 H'FEFA DMAC DMAC 24 — 0 23 * 22 * 21 * 20 * 19 * 18 * 17 16 * * Initial value : Read/Write : Bit MAR1BL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Rev.6.00 Sep. 27, 2007 Page 1117 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers IOAR1B—I/O Address Register 1B (Not supported in H8S/2321) Bit IOAR1B : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEFC DMAC 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B—Transfer Count Register 1B (Not supported in H8S/2321) Bit ETCR1B : : * * * * * * * 15 14 13 12 11 10 9 H'FEFE DMAC 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : Sequential mode and idle mode Repeat mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Transfer number storage register Transfer counter Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. Rev.6.00 Sep. 27, 2007 Page 1118 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DMAWER—DMA Write Enable Register (Not supported in H8S/2321) Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — H'FF00 DMAC 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER : Initial value : Read/Write : Write Enable 0A 0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled 1 Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled 1 Write Enable 1A 0 1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Write Enable 1B 0 1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Rev.6.00 Sep. 27, 2007 Page 1119 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DMATCR—DMA Terminal Control Register (Not supported in H8S/2321) Bit DMATCR : : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W H'FF01 DMAC 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Initial value : Read/Write : Transfer End Enable 0 0 1 TEND0 pin output disabled TEND0 pin output enabled Transfer End Enable 1 0 1 TEND1 pin output disabled TEND1 pin output enabled Rev.6.00 Sep. 27, 2007 Page 1120 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DMACR0A—DMA Control Register 0A (Not supported in H8S/2321) DMACR0B—DMA Control Register 0B (Not supported in H8S/2321) DMACR1A—DMA Control Register 1A (Not supported in H8S/2321) DMACR1B—DMA Control Register 1B (Not supported in H8S/2321) Full address mode Bit DMACRA : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W H'FF02 H'FF03 H'FF04 H'FF05 DMAC DMAC DMAC DMAC 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W Initial value : Read/Write : Reserved Only 0 should be written to these bits Block Direction/Block Enable 0 0 1 1 0 1 Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area Source Address Increment/Decrement 0 0 1 1 0 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer Rev.6.00 Sep. 27, 2007 Page 1121 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Full address mode (cont) Bit DMACRB : : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Reserved Only 0 should be written to this bit Reserved Only 0 should be written to this bit Data Transfer Factor DTF DTF DTF DTF 3 210 0 000 — Block Transfer Mode Normal Mode — — 1 1 0 Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data-empty interrupt Activated by SCI channel 0 reception data-full interrupt Activated by SCI channel 1 transmission data-empty interrupt Activated by SCI channel 1 reception data-full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt Activated by DREQ pin low-level input 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 — — Auto-request (cycle steal) Auto-request (burst) — — — — — — — — — — Destination Address Increment/Decrement 0 0 1 1 0 1 MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer Rev.6.00 Sep. 27, 2007 Page 1122 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Short address mode Bit DMACR : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Data Transfer Factor DTF DTF DTF DTF Channel A 3 2 10 0 000— Channel B Data Transfer Direction 0 Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Activated by A/D converter conversion end interrupt — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input 1 Activated by SCI channel 0 transmission data-empty interrupt Activated by SCI channel 0 reception data-full interrupt Activated by SCI channel 1 transmission data-empty interrupt Activated by SCI channel 1 reception data-full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Repeat Enable 0 1 Transfer in sequential mode Transfer in repeat mode or idle mode Data Transfer Increment/Decrement 0 1 MAR is incremented after a data transfer MAR is decremented after a data transfer Data Transfer Size 0 1 Byte-size transfer Word-size transfer Rev.6.00 Sep. 27, 2007 Page 1123 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DMABCRH — DMA Band Control Register (Not supported in H8S/2321) DMABCRL — DMA Band Control Register (Not supported in H8S/2321) Full address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W H'FF06 H'FF07 DMAC DMAC 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W DMABCRH : Initial value : Read/Write : Reserved Only 0 should be written to this bit Channel 0 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Reserved Only 0 should be written to this bit Channel 1 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Reserved Only 0 should be written to these bits Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) Rev.6.00 Sep. 27, 2007 Page 1124 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Full address mode (cont) Bit : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 1 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 0 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled Channel 1 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1 Data Transfer Master Enable 0 1 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Continued on next page) Rev.6.00 Sep. 27, 2007 Page 1125 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Short address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : Read/Write : Channel 0A Data Transfer Acknowledge 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled 1 Channel 0B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1A Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 1B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) Rev.6.00 Sep. 27, 2007 Page 1126 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers Short address mode (cont) Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 0A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Rev.6.00 Sep. 27, 2007 Page 1127 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ISCRH — IRQ Sense Control Register H ISCRL — IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FF2C H'FF2D Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n = 7 to 0) Rev.6.00 Sep. 27, 2007 Page 1128 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers IER—IRQ Enable Register Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 H'FF2E 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ4E 0 R/W IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) ISR—IRQ Status Register Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 H'FF2F 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ4F 0 R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1129 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DTCERA to DTCERF—DTC Enable Registers Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W H'FF30 to H'FF35 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE0 0 R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 Correspondence between Interrupt Sources and DTCER Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF 7 IRQ0 — TGI2A — DMTEND0A RXI2 6 IRQ1 ADI TGI2B — DMTEND0B TXI2 5 IRQ2 TGI0A TGI3A TGI5A DMTEND1A — 4 IRQ3 TGI0B TGI3B TGI5B 3 IRQ4 TGI0C TGI3C CMIA0 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 — 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 — 0 IRQ7 TGI1B TGI4B CMIB1 TXI1 — DMTEND1B RXI0 — — Note: For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. Rev.6.00 Sep. 27, 2007 Page 1130 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DTVECR—DTC Vector Register Bit : 7 0 R/W 6 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)* H'FF37 3 0 R/(W)* 2 0 R/(W)* 1 0 R/(W)* 0 0 DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : R/(W)* Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended • When SWDTEND is requested to the CPU, then 0 is written to the SWDTE bit DTC software activation is enabled [Holding conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended • During data transfer due to software activation 1 Note: * DTVEC6 to DTVEC 0 bits can be written to when SWDTE = 0. Rev.6.00 Sep. 27, 2007 Page 1131 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SBYCR—Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FF38 3 OPE 1 R/W 2 — 0 — 1 — 0 — Power-Down State 0 IRQ37S 0 R/W IRQ37 Software Standby Clear Select 0 1 IRQ3 to IRQ7 cannot be used as software standby mode clearing sources IRQ3 to IRQ7 can be used as software standby mode clearing sources Output Port Enable 0 1 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states Rev.6.00 Sep. 27, 2007 Page 1132 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SYSCR—System Control Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W H'FF39 3 0 R/W 2 0 R/W 1 0 R/W 0 RAME 1 R/W MCU NMIEG LWROD IRQPAS RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled IRQ Port Switching Select 0 1 IRQ4 to IRQ7 can be input from PA4 to PA7 IRQ4 to IRQ7 can be input from P50 to P53 Note: IRQ4 to IRQ7 input is always performed from only one of the ports. LWR Output Disable 0 1 PF3 is designated as LWR output pin PF3 is designated as I/O port, and does not function as LWR output pin NMI Input Edge Select 0 1 Falling edge Rising edge Interrupt Control Mode Selection 0 0 1 1 0 1 Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited Reserved Only 0 should be written to this bit Rev.6.00 Sep. 27, 2007 Page 1133 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCKCR—System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 DIV 0 R/W 4 — 0 — 3 — 0 — H'FF3A 2 SCK2 0 R/W 1 SCK1 0 R/W Clock Pulse Generator 0 SCK0 0 R/W Division Ratio Select Reserved Only 0 should be written to this bit System Clock Select SCK2 SCK1 SCK0 0 0 0 1 1 0 1 1 0 0 1 1 — DIV = 0 DIV = 1 Bus master is in high-speed mode Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — Clock supplied to entire chip is φ/2 Clock supplied to entire chip is φ/4 Clock supplied to entire chip is φ/8 — — — φ Clock Output Control PSTOP 0 1 Normal Operation Sleep Mode Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance φ output Fixed high φ output Fixed high Rev.6.00 Sep. 27, 2007 Page 1134 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers MDCR—Mode Control Register Bit : 7 — Initial value : Read/Write : 1 — 6 — 0 — 5 — 0 — 4 — 0 — H'FF3B 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MCU MDS0 —* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH — Module Stop Control Register H MSTPCRL — Module Stop Control Register L MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 H'FF3C H'FF3D MSTPCRL 7 1 6 1 5 1 4 1 3 1 Power-Down State Power-Down State 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set MSTP Bits and On-Chip Supporting Modules Register MSTPCRH Bits Module MSTP15 DMAC* MSTP14 DTC MSTP13 TPU MSTP12 8-bit timer MSTP11 PPG MSTP10 D/A MSTP9 A/D MSTP8 — MSTP7 SCI2 MSTPCRL MSTP6 SCI1 MSTP5 SCI0 MSTP4 — MSTP3 — MSTP2 — MSTP1 — MSTP0 — Note: * Reserved bit in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 1135 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SYSCR2—System Control Register 2 H'FF42 MCU (Valid only in F-ZTAT versions) 2 — 0 — 1 — 0 — 0 — 0 — (R/W) Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W Initial value : Read/Write : In the H8S/2329B only this bit is R/W, and should only be written with 0 Flash Memory Control Register Enable 0 H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT • Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT • Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB 1 Reserved Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 — 0 R/W 4 — 0 — H'FF44 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Reserved Only 0 should be written to these bits Rev.6.00 Sep. 27, 2007 Page 1136 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PFCR1—Port Function Control Register 1 Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 — 0 R/W 4 — 0 R/W H'FF45 3 A23E 1 R/W 2 A22E 1 R/W 1 A21E 1 R/W 0 A20E 1 R/W Address 20 Output Enable* 0 1 PA4DR is output when PA4DDR = 1 A20 is output when PA4DDR = 1 Address 21 Output Enable* 0 1 PA5DR is output when PA5DDR = 1 A21 is output when PA5DDR = 1 Address 22 Output Enable* 0 1 PA6DR is output when PA6DDR = 1 A22 is output when PA6DDR = 1 Address 23 Output Enable* 0 1 PA7DR is output when PA7DDR = 1 A23 is output when PA7DDR = 1 Note: * Valid only in modes 4 to 6. Reserved Only 0 should be written to these bits Rev.6.00 Sep. 27, 2007 Page 1137 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PCR—PPG Output Control Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF46 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W PPG G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : Read/Write : Output Trigger for Pulse Output Group 0 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 2 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 3 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Rev.6.00 Sep. 27, 2007 Page 1138 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PMR—PPG Output Mode Register Bit : 7 G3INV Initial value : Read/Write : 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 H'FF47 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PPG G0INV 1 R/W G3NOV G2NOV G1NOV G0NOV Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the selected TPU channel) (n = 3 to 0) Pulse Output Group n Direct/Inverse Output 0 1 Inverse output for pulse output group n (low-level output at pin for a 1 in PODRH) Direct output for pulse output group n (high-level output at pin for a 1 in PODRH) (n = 3 to 0) 1 Rev.6.00 Sep. 27, 2007 Page 1139 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers NDERH — Next Data Enable Register H NDERL — Next Data Enable Register L NDERH H'FF48 H'FF49 PPG PPG Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 NDERL Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled Bit : 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER6 NDER5 NDER4 NDER3 NDER1 NDER0 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 Pulse outputs PO7 to PO0 are disabled Pulse outputs PO7 to PO0 are enabled Rev.6.00 Sep. 27, 2007 Page 1140 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PODRH — Output Data Register H PODRL — Output Data Register L PODRH H'FF4A H'FF4B PPG PPG Bit : 7 POD15 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output PODRL Bit : 7 POD7 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output Note: * A bit that has been set for pulse output by NDER is read-only. Rev.6.00 Sep. 27, 2007 Page 1141 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers NDRH—Next Data Register H H'FF4C (FF4E) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : Stores the next data for pulse output group 3 (b) Address: H'FF4E Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 2 Rev.6.00 Sep. 27, 2007 Page 1142 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers NDRL—Next Data Register L H'FF4D (FF4F) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : Stores the next data for pulse output group 1 (b) Address: H'FF4F Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 0 Rev.6.00 Sep. 27, 2007 Page 1143 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PORT1—Port 1 Register Bit : 7 P17 Initial value : Read/Write : —* R 6 P16 —* R 5 P15 —* R 4 P14 —* R H'FF50 3 P13 —* R 2 P12 —* R 1 P11 —* R Port 1 0 P10 —* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT2—Port 2 Register Bit : 7 P27 Initial value : Read/Write : —* R 6 P26 —* R 5 P25 —* R 4 P24 —* R H'FF51 3 P23 —* R 2 P22 —* R 1 P21 —* R Port 2 0 P20 —* R State of port 2 pins Note: * Determined by the state of pins P27 to P20. PORT3—Port 3 Register Bit : 7 — Read/Write : — 6 — — 5 P35 —* R 4 P34 —* R H'FF52 3 P33 —* R 2 P32 —* R 1 P31 —* R 0 Port 3 P30 —* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. Rev.6.00 Sep. 27, 2007 Page 1144 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PORT4—Port 4 Register Bit : 7 P47 Initial value : Read/Write : —* R 6 P46 —* R 5 P45 —* R 4 P44 —* R H'FF53 3 P43 —* R 2 P42 —* R 1 P41 —* R Port 4 0 P40 —* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. PORT5—Port 5 Register Bit : 7 — Initial value : Read/Write : —* R 6 — —* R 5 — —* R 4 — —* R H'FF54 3 P53 —* R 2 P52 —* R 1 P51 —* R Port 5 0 P50 —* R State of port 5 pins Note: * Determined by the state of pins P53 to P50. PORT6—Port 6 Register Bit : 7 P67 Initial value : Read/Write : —* R 6 P66 —* R 5 P65 —* R 4 P64 —* R H'FF55 3 P63 —* R 2 P62 —* R 1 P61 —* R Port 6 0 P60 —* R State of port 6 pins Note: * Determined by the state of pins P67 to P60. Rev.6.00 Sep. 27, 2007 Page 1145 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PORTA—Port A Register Bit : 7 PA7 Initial value : Read/Write : —* R 6 PA6 —* R 5 PA5 —* R 4 PA4 —* R H'FF59 3 PA3 —* R 2 PA2 —* R 1 PA1 —* R Port A 0 PA0 —* R State of port A pins Note: * Determined by the state of pins PA7 to PA0. PORTB—Port B Register Bit : 7 PB7 Initial value : Read/Write : —* R 6 PB6 —* R 5 PB5 —* R 4 PB4 —* R H'FF5A 3 PB3 —* R 2 PB2 —* R 1 PB1 —* R Port B 0 PB0 —* R State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC—Port C Register Bit : 7 PC7 Initial value : Read/Write : —* R 6 PC6 —* R 5 PC5 —* R 4 PC4 —* R H'FF5B 3 PC3 —* R 2 PC2 —* R 1 PC1 —* R Port C 0 PC0 —* R State of port C pins Note: * Determined by the state of pins PC7 to PC0. Rev.6.00 Sep. 27, 2007 Page 1146 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PORTD—Port D Register Bit : 7 PD7 Initial value : Read/Write : —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R H'FF5C 3 PD3 —* R 2 PD2 —* R 1 PD1 —* R Port D 0 PD0 —* R State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE—Port E Register Bit : 7 PE7 Initial value : Read/Write : —* R 6 PE6 —* R 5 PE5 —* R 4 PE4 —* R H'FF5D 3 PE3 —* R 2 PE2 —* R 1 PE1 —* R Port E 0 PE0 —* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF—Port F Register Bit : 7 PF7 Initial value : Read/Write : —* R 6 PF6 —* R 5 PF5 —* R 4 PF4 —* R H'FF5E 3 PF3 —* R 2 PF2 —* R 1 PF1 —* R Port F 0 PF0 —* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. Rev.6.00 Sep. 27, 2007 Page 1147 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PORTG—Port G Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 PG4 —* R H'FF5F 3 PG3 —* R 2 PG2 —* R 1 PG1 —* R Port G 0 PG0 —* R Initial value : Undefined Undefined Undefined State of port G pins Note: * Determined by the state of pins PG4 to PG0. P1DR—Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 H'FF60 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Port 1 0 P10DR 0 R/W P14DR 0 R/W Stores output data for port 1 pins (P17 to P10) P2DR—Port 2 Data Register Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 H'FF61 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W Port 2 0 P20DR 0 R/W P24DR 0 R/W Stores output data for port 2 pins (P27 to P20) Rev.6.00 Sep. 27, 2007 Page 1148 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers P3DR—Port 3 Data Register Bit : 7 — Read/Write : — 6 — — 5 P35DR 0 R/W 4 H'FF62 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W Port 3 0 P30DR 0 R/W P34DR 0 R/W Initial value : Undefined Undefined Stores output data for port 3 pins (P35 to P30) P5DR—Port 5 Data Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 — — H'FF64 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 Port 5 P50DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port 5 pins (P53 to P50) P6DR—Port 6 Data Register Bit : 7 P67DR Initial value : Read/Write : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 H'FF65 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W Port 6 0 P60DR 0 R/W P64DR 0 R/W Stores output data for port 6 pins (P67 to P60) Rev.6.00 Sep. 27, 2007 Page 1149 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PADR—Port A Data Register Bit : 7 PA7DR Initial value : Read/Write : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 H'FF69 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W Port A 0 PA0DR 0 R/W PA4DR 0 R/W Stores output data for port A pins (PA7 to PA0) PBDR—Port B Data Register Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 H'FF6A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W Port B 0 PB0DR 0 R/W PB4DR 0 R/W Stores output data for port B pins (PB7 to PB0) PCDR—Port C Data Register Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF6B 3 0 R/W 2 PC2DR 0 R/W 1 0 R/W Port C 0 0 R/W PC6DR PC5DR PC4DR PC3DR PC1DR PC0DR Stores output data for port C pins (PC7 to PC0) Rev.6.00 Sep. 27, 2007 Page 1150 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PDDR—Port D Data Register Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF6C 3 0 R/W 2 PD2DR 0 R/W 1 0 R/W Port D 0 0 R/W PD6DR PD5DR PD4DR PD3DR PD1DR PD0DR Stores output data for port D pins (PD7 to PD0) PEDR—Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 H'FF6D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W Port E 0 PE0DR 0 R/W PE4DR 0 R/W Stores output data for port E pins (PE7 to PE0) PFDR—Port F Data Register Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 H'FF6E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W PF4DR 0 R/W Stores output data for port F pins (PF7 to PF0) Rev.6.00 Sep. 27, 2007 Page 1151 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PGDR—Port G Data Register Bit : 7 — Read/Write : — 6 — — 5 — — 4 0 R/W H'FF6F 3 0 R/W 2 0 R/W 1 0 R/W Port G 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Stores output data for port G pins (PG4 to PG0) PAPCR—Port A MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF70 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port A PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis PBPCR—Port B MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF71 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port B PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis Rev.6.00 Sep. 27, 2007 Page 1152 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PCPCR—Port C MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF72 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port C PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : R/W Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR—Port D MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF73 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port D PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis PEPCR—Port E MOS Pull-Up Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port E PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis Rev.6.00 Sep. 27, 2007 Page 1153 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers P3ODR—Port 3 Open Drain Control Register Bit : 7 — Read/Write : — 6 — — 5 0 R/W 4 0 R/W H'FF76 3 0 R/W 2 0 R/W 1 0 R/W Port 3 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR—Port A Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF77 3 0 R/W 2 0 R/W 1 0 R/W Port A 0 0 R/W PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Read/Write : Controls the PMOS on/off status for each port A pin (PA7 to PA0) Rev.6.00 Sep. 27, 2007 Page 1154 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W SCI0 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Character Length 0 1 8-bit data 7-bit data* Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Sep. 27, 2007 Page 1155 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 0 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W Base Clock Pulse BCP1 BCP0 0 0 1 1 0 1 Parity Mode 0 1 Even parity Odd parity Base Clock Pulse 32 clocks 64 clocks 372 clocks 256 clocks Parity Enable (Set to 1 when using the smart card interface) 0 1 Setting prohibited Parity bit addition and checking enabled Block Transfer Mode Select 0 GSM Mode 0 1 Normal smart card interface mode Block transfer mode Normal smart card interface mode operation • TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Sep. 27, 2007 Page 1156 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers BRR0—Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep. 27, 2007 Page 1157 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W 0 CKE0 0 R/W SCI0 Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1158 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W 0 CKE0 0 R/W Smart Card Interface 0 Initial value : Read/Write : Clock Enable SCMR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SMR GM SCR setting CKE1 CKE0 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port I/O pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1159 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TDR0—Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.6.00 Sep. 27, 2007 Page 1160 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted SCI0 Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Note: 1. The DMAC is not supported in the H8S/2321. Parity Error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR 1 Framing Error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 1 Overrun Error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1161 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Smart Card Interface 0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 Transmission in progress [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR Transmission has ended [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary time unit (time for transfer of 1 bit) 1. The DMAC is not supported in the H8S/2321. Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 Data has been received normally, and there is no error signal [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 Error signal indicating detection of parity error has been sent by receiving device [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1162 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers RDR0—Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R SCI0, Smart Card Interface 0 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 H'FF7E 2 SINV 0 R/W SCI0, Smart Card Interface 0 1 — 1 — 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart card interface function is disabled Smart card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Sep. 27, 2007 Page 1163 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock 0 CKS0 0 R/W SCI1 φ/16 clock φ/64 clock Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Sep. 27, 2007 Page 1164 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 1 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W Base Clock Pulse BCP1 BCP0 0 0 1 1 0 1 Base Clock Pulse 32 clocks 64 clocks 372 clocks 256 clocks Parity Mode (Set to 1 when using the smart card interface) 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Block Transfer Mode Select 0 1 GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control Normal smart card interface mode Block transfer mode 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Sep. 27, 2007 Page 1165 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers BRR1—Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep. 27, 2007 Page 1166 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable 0 CKE0 0 R/W SCI1 Initial value : Read/Write : 0 0 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output 1 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1167 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W 0 CKE0 0 R/W Smart Card Interface 1 Initial value : Read/Write : Clock Enable SCMR SMR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 GM SCR setting CKE1 CKE0 SCK pin function See SCI specification 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1168 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TDR1—Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.6.00 Sep. 27, 2007 Page 1169 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted SCI1 Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: 1. The DMAC is not supported in the H8S/2321. Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1170 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 H'FF84 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 MPB 0 R Smart Card Interface 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Transmit End Transmission in progress 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR 1 Transmission has ended [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Parity Error 0 1 Notes: etu: Elementary time unit (time for transfer of 1 bit) 1. The DMAC is not supported in the H8S/2321. [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 Data has been received normally, and there is no error signal [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 Error signal indicating detection of parity error has been sent by receiving device [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1171 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers RDR1—Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R SCI1, Smart Card Interface 1 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W H'FF86 2 SINV 0 R/W SCI1, Smart Card Interface 1 1 — 1 — 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart card interface function is disabled Smart card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Sep. 27, 2007 Page 1172 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR2—Serial Mode Register 2 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W SCI2 Multiprocessor Mode 0 1 Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Character Length 0 1 8-bit data 7-bit data* Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Sep. 27, 2007 Page 1173 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SMR2—Serial Mode Register 2 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF88 3 BCP1 0 R/W 2 BCP0 0 R/W Smart Card Interface 2 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 φ clock φ/4 clock φ/16 clock φ/64 clock 0 CKS0 0 R/W Base Clock Pulse BCP1 BCP0 0 0 1 1 0 1 Base Clock Pulse 32 clocks 64 clocks 372 clocks 256 clocks Parity Mode (Set to 1 when using the smart card interface) 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Block Transfer Mode Select 0 1 GSM Mode 0 Normal smart card interface mode operation • TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control Normal smart card interface mode Block transfer mode 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Sep. 27, 2007 Page 1174 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers BRR2—Bit Rate Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF89 3 1 R/W SCI2, Smart Card Interface 2 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep. 27, 2007 Page 1175 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR2—Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF8A 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI2 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1176 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SCR2—Serial Control Register 2 Bit : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF8A 1 CKE1 0 R/W 0 CKE0 0 R/W Smart Card Interface 2 Initial value : Read/Write : Clock Enable SCMR SMIF 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SMR GM SCR setting CKE1 CKE0 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port I/O pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled Transmit-end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive-data-full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled Rev.6.00 Sep. 27, 2007 Page 1177 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TDR2—Transmit Data Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF8B SCI2, Smart Card Interface 2 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission Rev.6.00 Sep. 27, 2007 Page 1178 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR2—Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF8C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted SCI2 Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: 1. The DMAC is not supported in the H8S/2321. Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1179 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers SSR2—Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF8C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Smart Card Interface 2 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End Transmission in progress [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR 1 Transmission has ended [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Notes: etu: Elementary time unit (time for transfer of 1 bit) 1. The DMAC is not supported in the H8S/2321. Parity Error 0 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Error Signal Status 0 Data has been received normally, and there is no error signal [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 Error signal indicating detection of parity error has been sent by receiving device [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC*1 or DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC*1 or DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: 1. The DMAC is not supported in the H8S/2321. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1180 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers RDR2—Receive Data Register 2 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF8D SCI2, Smart Card Interface 2 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR2—Smart Card Mode Register 2 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W H'FF8E SCI2, Smart Card Interface 2 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart card interface function is disabled Smart card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Sep. 27, 2007 Page 1181 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL — A/D Data Register AH — A/D Data Register AL — A/D Data Register BH — A/D Data Register BL — A/D Data Register CH — A/D Data Register CL — A/D Data Register DH — A/D Data Register DL H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : Read/Write : Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.6.00 Sep. 27, 2007 Page 1182 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/(W)*1 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W A/D Converter 0 CH0 0 R/W Channel Select Note: These bits select the analog input channels. Ensure that conversion is halted (ADST = 0) before making a channel selection. Group Selection CH2 0 Channel Selection Single Mode (SCAN = 0) CH0 AN0 0 (Initial value) 1 AN1 AN2 0 AN3 1 AN4 0 AN5 1 AN6 0 AN7 1 Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 CH1 0 1 1 0 1 Clock Select Note: CKS is used in combination with bit 3 (CKS1) of ADCR. See ADCR—A/D Control Register H'FF99 A/D Converter. Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends • Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode A/D Interrupt Enable 0 A/D End Flag 0 1 A/D conversion end interrupt request disabled A/D conversion end interrupt request enabled [Clearing conditions] • When 0 is written to the ADF flag after reading ADF = 1 • When the DMAC*2 or DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When A/D conversion ends on all specified channels 1 Notes: 1. Can only be written with 0 for flag clearing. 2. The DMAC is not supported in the H8S/2321. Rev.6.00 Sep. 27, 2007 Page 1183 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers ADCR—A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — H'FF99 3 CKS1 1 R/W 2 CH3 1 R/W 1 — 1 — A/D Converter 0 — 1 — Clock Select Bit 3 CKS1 0 ADCSR Bit 3 CKS 0 1 1 0 1 Timer Trigger Select TRGS1 TRGS1 0 0 1 1 0 1 Channel Select Reserved Only 1 should be written to this bit Description Conversion time = 530 states (max) Conversion time = 68 states (max) Conversion time = 266 states (max) Conversion time = 134 states (max) (Initial value) Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Rev.6.00 Sep. 27, 2007 Page 1184 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DADR0—D/A Data Register 0 DADR1—D/A Data Register 1 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA4 H'FFA5 3 0 R/W 2 0 R/W 1 0 D/A Converter D/A Converter 0 0 R/W Initial value : Read/Write : R/W Stores data for D/A conversion Rev.6.00 Sep. 27, 2007 Page 1185 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers DACR01—D/A Control Register 01 Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — H'FFA6 3 — 1 — 2 — 1 — 1 — 1 — D/A Converter 0 — 1 — D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAOE1 0 DAOE0 0 1 DAE * 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled * : Don’t care Rev.6.00 Sep. 27, 2007 Page 1186 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers PFCR2—Port Function Control Register 2 Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W H'FFAC 3 ASOD R/W 2 — 0 R 1 — 0 R 0 — 0 R Ports WAITPS BREQOPS CS167E CS25E Initial value : Read/Write : AS Output Disable 0 1 PF6 is designated as AS output pin PF6 is designated as I/O port, and does not function as AS output pin Note: This bit is valid in modes 4 to 6. CS25 Enable 0 1 CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports) CS2, CS3, CS4, and CS5 output enabled Note: Clear the DDR bits to 0 before changing the CS25E setting. CS167 Enable 0 1 CS1, CS6, and CS7 output disabled (can be used as I/O ports) CS1, CS6, and CS7 output enabled Note: Clear the DDR bits to 0 before changing the CS167E setting. BREQO Pin Select 0 1 BREQO output is PF2 pin BREQO output is P53 pin Note: Set BREQOPS before setting the BREQOE bit in BCRL to 1. WAIT Pin Select 0 1 WAIT input is PF2 pin WAIT input is P53 pin Note: Set WAITPS before setting the WAITE bit in BCRL to 1. Rev.6.00 Sep. 27, 2007 Page 1187 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 H'FFB0 H'FFB1 1 CKS1 0 R/W 0 CKS0 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 CKS2 0 R/W Initial value : Read/Write : Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of ø/8 Internal clock: counted at falling edge of ø/64 Internal clock: counted at falling edge of ø/8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges 1 1 0 1 Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled Rev.6.00 Sep. 27, 2007 Page 1188 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : 7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4 H'FFB2 H'FFB3 3 OS3 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 2 OS2 0 R/W 8-Bit Timer Channel 0 8-Bit Timer Channel 1 1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W ADTE 0 R/W 4 — 1 — Initial value : Read/Write : TCSR1 Bit : Initial value : Read/Write : Output Select 0 0 1 1 0 1 No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled Timer Overflow Flag 0 1 [Clearing condition] When 0 is written to OVF after reading OVF = 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) Compare Match Flag A 0 [Clearing conditions] • When 0 is written to CMFA after reading CMFA = 1 • When the DTC is activated by a CMIA interrupt, while the DISEL bit of MRB in DTC is 0 [Setting condition] When TCNT matches TCORA 1 Compare Match Flag B 0 [Clearing conditions] • When 0 is written to CMFB after reading CMFB = 1 • When the DTC is activated by a CMIB interrupt, while the DISEL bit of MRB in DTC is 0 [Setting condition] When TCNT matches TCORB 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev.6.00 Sep. 27, 2007 Page 1189 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORB1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFB8 H'FFB9 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCNT1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1190 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCSR—Timer Control/Status Register Bit : 7 OVF Initial value : Read/Write*1 : 0 R/(W)*2 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — H'FFBC (W), H'FFBC (R) 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock Overflow period* (when φ = 20 MHz) 819.2 µs 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s φ/2 (Initial value) 25.6 µs φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal*1 when TCNT overflows*2 Notes: 1. The WDTOVF pin function is not available in the F-ZTAT versions. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset Control/Status Register (RSTCSR). Overflow Flag 0 1 [Clearing condition] When 0 is written to OVF after reading OVF = 1 [Setting condition] When TCNT overflows from H'FF to H'00 in interval timer mode Notes: 1. The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details, see section 13.2.4, Notes on Register Access. 2. Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1191 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT—Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFBC (W), H'FFBD (R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Initial value : Read/Write : R/W RSTCSR—Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 — 0 R/W 4 — 1 — H'FFBE (W), H'FFBF (R) 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — WDT Reserved This bit should be written with 0 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Note: * The modules in the H8S/2329 and H8S/2328 Groups are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] When 0 is written to WOVF after reading RSTCSR when WOVF = 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) during watchdog timer operation Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details, see section 13.2.4, Notes on Register Access. Rev.6.00 Sep. 27, 2007 Page 1192 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSTR—Timer Start Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 CST5 0 R/W 4 CST4 0 R/W H'FFC0 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W TPU Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR—Timer Synchro Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 SYNC5 0 R/W 4 SYNC4 0 R/W H'FFC1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W TPU Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev.6.00 Sep. 27, 2007 Page 1193 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'FFC8 (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Bit : 7 FWE Initial value : Read/Write : —* R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W Flash Memory 0 P 0 R/W Program 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-Verify 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Erase-Verify 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Program Setup 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 Software Write Enable 0 1 Writes disabled Writes enabled [Setting condition] When FWE = 1 Erase Setup 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 Flash Write Enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin (H8S/2328B F-ZTAT). The FWE bit is fixed high in the H8S/2329B F-ZTAT. Rev.6.00 Sep. 27, 2007 Page 1194 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 (H8S/2326 F-ZTAT) Bit : 7 FWE Initial value : R/W : —*1 R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W H'FFC8 Flash Memory 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Program 1*2 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 Erase 1*2 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Program-Verify 1*2 0 Program-verify mode cleared 1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Erase-Verify 1*2 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Program Setup 1*2 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1 and SWE1 = 1 Erase Setup 1*2 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1 and SWE1 = 1 Software Write Enable 1*2 0 Writes disabled 1 Writes enabled [Setting condition] When FWE = 1 Flash Write Enable 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Notes: 1. Determined by the state of the FWE pin. 2. Applicable addresses are H'000000 to H'03FFFF. Rev.6.00 Sep. 27, 2007 Page 1195 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'FFC9 (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Bit : 7 FLER Initial value : Read/Write : 0 R 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — Flash Memory 0 — 0 — Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection. (H8S/2329B F-ZTAT) See section 19.17.3, Error Protection. (H8S/2328B F-ZTAT) 1 Rev.6.00 Sep. 27, 2007 Page 1196 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 (H8S/2326 F-ZTAT) Bit : 7 FLER Initial value : R/W : 0 R 6 SWE2 0 R/W 5 ESU2 0 R/W 4 PSU2 0 R/W H'FFC9 3 EV2 0 R/W 2 PV2 0 R/W Program 2* 0 1 Flash Memory 1 E2 0 R/W 0 P2 0 R/W Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE2 = 1, and PSU2 = 2 Erase 2* 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE2 = 1, and ESU2 = 1 Program-Verify 2* 0 Program-verify mode cleared 1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE2 = 1 Erase-Verify 2* 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE2 = 1 Program Setup 2* 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1 and SWE2 = 1 Erase Setup 2* 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1 and SWE2 = 1 Software Write Enable 2* 0 1 Writes disabled Writes enabled [Setting condition] When FWE = 1 Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) disabled [Clearing condition] Reset or hardware standby mode 1 An error occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) enabled [Setting condition] See section 19.26.3, Error Protection Note: * Applicable addresses are H'040000 to H'07FFFF. Rev.6.00 Sep. 27, 2007 Page 1197 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers EBR1—Erase Block Register 1 H'FFCA (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) EBR2—Erase Block Register 2 H'FFCB (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Bit EBR1 Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : : : 7 EB7 0 R/W 7 — 0 — 6 EB6 0 R/W 6 — 0 — 5 EB5 0 R/W 5 EB13* 0 R/W 4 EB4 0 R/W 4 EB12* 0 R/W 3 EB3 0 R/W 3 EB11 0 R/W 2 EB2 0 R/W 2 EB10 0 R/W 1 Flash Memory Flash Memory 0 EB0 0 R/W 0 EB8 0 R/W EB1 0 R/W 1 EB9 0 R/W Note: * Valid only in the H8S/2329B F-ZTAT. Rev.6.00 Sep. 27, 2007 Page 1198 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers EBR1—Erase Block Register 1 (H8S/2326 F-ZTAT) EBR2—Erase Block Register 2 (H8S/2326 F-ZTAT) Bit EBR1 Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : : : 7 EB7 0 R/W 7 EB15 0 R/W 6 EB6 0 R/W 6 EB14 0 R/W 5 EB5 0 R/W 5 EB13 0 R/W 4 EB4 0 R/W 4 EB12 0 R/W H'FFCA H'FFCB Flash Memory Flash Memory 3 EB3 0 R/W 3 EB11 0 R/W 2 EB2 0 R/W 2 EB10 0 R/W 1 EB1 0 R/W 1 EB9 0 R/W 0 EB0 0 R/W 0 EB8 0 R/W Rev.6.00 Sep. 27, 2007 Page 1199 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR0—Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FFD0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU0 CKEG1 CKEG0 Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev.6.00 Sep. 27, 2007 Page 1200 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR0—Timer Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W H'FFD1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU0 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev.6.00 Sep. 27, 2007 Page 1201 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR0H—Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFD2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU0 TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock * : Don’t care TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock * : Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture does not occur. 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * * Rev.6.00 Sep. 27, 2007 Page 1202 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR0L—Timer I/O Control Register 0L Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W H'FFD3 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is input capture register Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock TGR0C Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match * : Don’t care Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare does not occur. TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is input capture register *2 TGR0D Output disabled is output compare Initial output is register 0 output *2 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCD0 pin Capture input source is channel 1/count clock Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count-up/ count-down*1 * : Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture does not occur. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare does not occur. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev.6.00 Sep. 27, 2007 Page 1203 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER0—Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 H'FFD4 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU0 TGIED 0 R/W TGR Interrupt Enable A 0 1 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt request (TGIC) by TGFC bit disabled Interrupt request (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt request (TGID) by TGFD bit disabled Interrupt request (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1204 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR0—Timer Status Register 0 Bit : 7 — 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* H'FFD5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1205 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT0—Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFD6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFD8 H'FFDA H'FFDC H'FFDE 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1206 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR1—Timer Control Register 1 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFE0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU1 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on φ/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge* 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev.6.00 Sep. 27, 2007 Page 1207 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR1—Timer Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FFE1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU1 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Sep. 27, 2007 Page 1208 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR1—Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFE2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 1 TGR1A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is input capture register Capture input source is TIOCA1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture * : Don’t care 1 0 1 1 0 0 0 1 1 1 * * * TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0C compare match/input compare match/ capture input capture * : Don’t care TGR1B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Sep. 27, 2007 Page 1209 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER1—Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FFE4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU1 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1210 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR1—Timer Status Register 1 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FFE5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU1 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1211 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT1—Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFE6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFE8 H'FFEA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1212 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCR2—Timer Control Register 2 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFF0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU2 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev.6.00 Sep. 27, 2007 Page 1213 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TMDR2—Timer Mode Register 2 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — 4 — 0 — H'FFF1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU2 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — * : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Sep. 27, 2007 Page 1214 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIOR2—Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFF2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU2 TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don’t care Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don’t care TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Sep. 27, 2007 Page 1215 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TIER2—Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — H'FFF4 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU2 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Sep. 27, 2007 Page 1216 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TSR2—Timer Status Register 2 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 — 0 — 2 — 0 — H'FFF5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU2 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Note: 1. The DMAC is not supported in the H8S/2321. Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Sep. 27, 2007 Page 1217 of 1268 REJ09B0220-0600 Appendix B Internal I/O Registers TCNT2—Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFF6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFF8 H'FFFA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Sep. 27, 2007 Page 1218 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Reset WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output DMA controller* DMA transfer acknowledge enable DMA transfer acknowledge TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input R Q D P1nDDR C Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: n = 0 or 1 * The DMAC is not supported in the H8S/2321. Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev.6.00 Sep. 27, 2007 Page 1219 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: n = 2, 3, 5, 7 Figure C.1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17) Rev.6.00 Sep. 27, 2007 Page 1220 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input R Q D P1nDDR C Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: n = 4 or 6 Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev.6.00 Sep. 27, 2007 Page 1221 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.2 Port 2 Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 0 or 1 Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev.6.00 Sep. 27, 2007 Page 1222 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 2 or 4 Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev.6.00 Sep. 27, 2007 Page 1223 of 1268 REJ09B0220-0600 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 8-bit timer module Counter external reset input Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 3 or 5 Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev.6.00 Sep. 27, 2007 Page 1224 of 1268 REJ09B0220-0600 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 8-bit timer module Counter external clock inpu Appendix C I/O Port Block Diagrams Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Internal data bus PPG module Pulse output enable Pulse output 8-bit timer module Compare match output enable Compare match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 6 or 7 Figure C.2 (d) Port 2 Block Diagram (Pins P26 and P27) Rev.6.00 Sep. 27, 2007 Page 1225 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.3 Port 3 Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 P3n Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev.6.00 Sep. 27, 2007 Page 1226 of 1268 REJ09B0220-0600 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 RDR3 RPOR3 Internal data bus SCI module Serial receive data enable Serial receive data Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev.6.00 Sep. 27, 2007 Page 1227 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 P3n Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Internal data bus Serial clock input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: n = 4 or 5 1. Output enable signal 2. Open drain control signal Figure C.3 (c) Port 3 Block Diagram (Pins P34 and P35) Rev.6.00 Sep. 27, 2007 Page 1228 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.4 Port 4 Internal data bus A/D converter module Analog input RPOR4 P4n Legend: RPOR4: Read port 4 Note: n = 0 to 5 Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45) Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output RPOR4 P4n Legend: RPOR4: Read port 4 Note: n = 6 or 7 Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev.6.00 Sep. 27, 2007 Page 1229 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.5 Port 5 Reset Internal data bus R Q D P50DDR C WDDR0 Reset R Q D P50DR C WDR5 P50 SCI module Serial transmit output enable Serial transmit data RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: IRQPAS IRQ4 interrupt input Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (a) Port 5 Block Diagram (Pin P50) Rev.6.00 Sep. 27, 2007 Page 1230 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset WDDR5 Reset P51 R Q D P51DR C WDR5 Internal data bus SCI module Serial receive data enable Serial receive data IRQPAS IRQ5 interrupt input R Q D P51DDR C RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (b) Port 5 Block Diagram (Pin P51) Rev.6.00 Sep. 27, 2007 Page 1231 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D P52DDR C WDDR5 Reset R Q D P52DR C WDR5 P52 Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input IRQPAS IRQ6 interrupt input RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (c) Port 5 Block Diagram (Pin P52) Rev.6.00 Sep. 27, 2007 Page 1232 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5 Bus controller Modes 4 to 6 Bus request output enable Bus request output BREQOPS RDR5 RPOR5 A/D converter A/D converter external trigger input IRQPAS IRQ7 interrupt input Modes 4 to 6 WAITPS Wait input pin enable Bus controller Wait input Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: WAITPS: BREQOPS: Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Wait pin select BREQO pin select Figure C.5 (d) Port 5 Block Diagram (Pin P53) Rev.6.00 Sep. 27, 2007 Page 1233 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.6 Port 6 Reset WDDR6 Mode 7 P60 Modes 4 to 6 Reset R Q D P60DR C WDR6 RDR6 CS25E RPOR6 DMA controller* DMA request input Legend: WDDR6: WDR6: RDR6: RPOR6: CS25E: Write to P6DDR Write to P6DR Read P6DR Read port 6 CS25 enable Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (a) Port 6 Block Diagram (Pin P60) Rev.6.00 Sep. 27, 2007 Page 1234 of 1268 REJ09B0220-0600 Internal data bus Bus controller Chip select R Q D P60DDR C Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P61DDR C WDDR6 Mode 7 P61 Modes 4 to 6 Reset R Q D P61DR C WDR6 CS25E Bus controller Chip select DMA controller* DMA transfer end enable DMA transfer end RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: CS25E: Write to P6DDR Write to P6DR Read P6DR Read port 6 CS25 enable Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (b) Port 6 Block Diagram (Pin P61) Rev.6.00 Sep. 27, 2007 Page 1235 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset WDDR6 Reset P62 R Q D P62DR C WDR6 RDR6 RPOR6 DMA controller* DMA request input Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (c) Port 6 Block Diagram (Pin P62) Rev.6.00 Sep. 27, 2007 Page 1236 of 1268 REJ09B0220-0600 Internal data bus R Q D P62DDR C Appendix C I/O Port Block Diagrams Reset R Q D P63DDR C WDDR6 Reset R Q D P63DR C WDR6 P63 RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (d) Port 6 Block Diagram (Pin P63) Rev.6.00 Sep. 27, 2007 Page 1237 of 1268 REJ09B0220-0600 Internal data bus DMA controller* DMA transfer end enable DMA transfer end Appendix C I/O Port Block Diagrams Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6 RPOR6 Internal data bus IRQm interrupt input Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: n = 4 or 5 m = 0 or 1 Figure C.6 (e) Port 6 Block Diagram (Pins P64 and P65) Rev.6.00 Sep. 27, 2007 Page 1238 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D P6nDDR C WDDR6 Mode 7 P6n Modes 4 to 6 Reset R Q D P6nDR C WDR6 Internal data bus Bus controller Chip select IRQm interrupt input CS167E RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: CS167E: Write to P6DDR Write to P6DR Read P6DR Read port 6 CS167 enable Note: n = 6 or 7 m = 2 or 3 Figure C.6 (f) Port 6 Block Diagram (Pins P66 and P67) Rev.6.00 Sep. 27, 2007 Page 1239 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.7 Port A Modes 6 and 7 Reset WPCRA RPCRA Reset Modes 4 and 5 R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 PAn Mode 7 Modes 4 to 6 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: n = 0 to 3 1. Output enable signal 2. Open drain control signal Figure C.7 (a) Port A Block Diagram (Pins PA0 to PA3) Rev.6.00 Sep. 27, 2007 Page 1240 of 1268 REJ09B0220-0600 Internal address bus Internal data bus R Q D PAnPCR C Appendix C I/O Port Block Diagrams Reset Modes 6 and 7 Internal address bus Internal data bus R Q D PA4PCR C WPCRA RPCRA Reset Modes 4 and 5 R Q D PA4DDR C WDDRA *1 A20E Reset R Q D PA4DR C WDRA *2 PA4 Mode 7 Modes 4 to 6 Reset R Q D PA4ODR C WODRA RODRA RDRA RPORA IRQPAS Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: A20E: IRQPAS: IRQ4 interrupt input Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Address 20 enable IRQ port switching select Notes: 1. Output enable signal 2. Open drain control signal Figure C.7 (b) Port A Block Diagram (Pin PA4) Rev.6.00 Sep. 27, 2007 Page 1241 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Modes 4 to 7 Reset Internal data bus Internal address bus R Q D PAnPCR C WPCRA RPCRA Reset R Q D PAnDDR C WDDRA *1 Reset Mode 7 PAn Modes 4 to 6 R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA AmE Mode 7 RDRA RPORA IRQPAS Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: AmE: IRQPAS: IRQn interrupt input Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Address output enable IRQ port switching select Notes: n = 5 to 7 m = 21 to 23 1. Output enable signal 2. Open drain control signal Figure C.7 (c) Port A Block Diagram (Pins PA5 to PA7) Rev.6.00 Sep. 27, 2007 Page 1242 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.8 Port B Modes 6 and 7 Reset R Q D PBnPCR C WPCRB RPCRB Modes 4 and 5 Reset R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn Mode 7 Modes 4 to 6 RDRB RPORB Legend: WDDRB: WDRB: WPCRB: RDRB: RPORB: RPCRB: Write to PBDDR Write to PBDR Write to PBPCR Read PBDR Read port B Read PBPCR Note: n = 0 to 7 Figure C.8 Port B Block Diagram (Pins PB0 to PB7) Rev.6.00 Sep. 27, 2007 Page 1243 of 1268 REJ09B0220-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.9 Port C Modes 6 and 7 Reset R Q D PCnPCR C WPCRC RPCRC Modes 4 and 5 Reset R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 7 Modes 4 to 6 RDRC RPORC Legend: WDDRC: WDRC: WPCRC: RDRC: RPORC: RPCRC: Write to PCDDR Write to PCDR Write to PCPCR Read PCDR Read port C Read PCPCR Note: n = 0 to 7 Figure C.9 Port C Block Diagram (Pins PC0 to PC7) Rev.6.00 Sep. 27, 2007 Page 1244 of 1268 REJ09B0220-0600 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.10 Port D Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Mode 7 Reset External address write Modes 4 to 6 R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD PDn Mode 7 Modes 4 to 6 External address upper write External address lower write RDRD RPORD Legend: WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR External address upper read External address lower read Note: n = 0 to 7 Figure C.10 Port D Block Diagram (Pins PD0 to PD7) Rev.6.00 Sep. 27, 2007 Page 1245 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.11 Port E Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Mode 7 Bus controller 8-bit bus mode Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write Modes 4 to 6 PEn Modes 4 to 6 RDRE RPORE Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR External address lower read Note: n = 0 to 7 Figure C.11 Port E Block Diagram (Pins PE0 to PE7) Rev.6.00 Sep. 27, 2007 Page 1246 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.12 Port F Internal data bus Bus controller BRLE bit Reset Bus request input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Reset R Q D PF0DDR C WDDRF Modes 4 to 6 PF0 R Q D PF0DR C WDRF RDRF RPORF Figure C.12 (a) Port F Block Diagram (Pin PF0) Rev.6.00 Sep. 27, 2007 Page 1247 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 4 to 6 PF1 RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (b) Port F Block Diagram (Pin PF1) Rev.6.00 Sep. 27, 2007 Page 1248 of 1268 REJ09B0220-0600 Internal data bus Bus controller BRLE bit Bus request acknowledge output Appendix C I/O Port Block Diagrams R Q D PF2DDR C WDDRF Reset R Q D PF2DR C WDRF Modes 4 to 6 PF2 Modes 4 to 6 Internal data bus Reset Bus controller Bus request output enable Bus request output RDRF RPORF Wait input LCAS output enable* Modes 4 and 6 Legend: WDDRF: WDRF: RDRF: RPORF: WAITPS: BREQOPS: Write to PFDDR Write to PFDR Read PFDR Read port F WAIT pin select BREQO pin select LCAS output* Wait enable WAITPS BREQOPS Note: * Not supported in the H8S/2321. Figure C.12 (c) Port F Block Diagram (Pin PF2) Rev.6.00 Sep. 27, 2007 Page 1249 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Mode 7 PF3 Modes 4 to 6 Reset R Q D PF3DR C WDRF Interrupt controller LWROD Bus controller LWR output RDRF Modes 4 to 6 RPORF Legend: WDDRF: WDRF: RDRF: RPORF: LWROD: Write to PFDDR Write to PFDR Read PFDR Read port F LWR output disable Figure C.12 (d) Port F Block Diagram (Pin PF3) Rev.6.00 Sep. 27, 2007 Page 1250 of 1268 REJ09B0220-0600 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PF4DDR C WDDRF Mode 7 PF4 Modes 4 to 6 Reset R Q D PF4DR C WDRF Modes 4 to 6 RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (e) Port F Block Diagram (Pin PF4) Rev.6.00 Sep. 27, 2007 Page 1251 of 1268 REJ09B0220-0600 Internal data bus Bus controller HWR output Appendix C I/O Port Block Diagrams Reset Internal data bus Modes 4 to 6 R Q D PF5DDR C WDDRF Mode 7 PF5 Modes 4 to 6 Reset R Q D PF5DR C WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (f) Port F Block Diagram (Pin PF5) Rev.6.00 Sep. 27, 2007 Page 1252 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset Modes 4 to 6 WDDRF Mode 7 PF6 Modes 4 to 6 Reset R Q D PF6DR C WDRF Internal data bus Interrupt controller ASOD Bus controller AS output R Q D PF6DDR C RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: ASOD: Write to PFDDR Write to PFDR Read PFDR Read port F AS output disable Figure C.12 (g) Port F Block Diagram (Pin PF6) Rev.6.00 Sep. 27, 2007 Page 1253 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Modes 4 to 6 Reset Mode 7 WDDRF Reset R Q D PF7DR C WDRF PF7 Internal data bus φ SR Q D PF7DDR C RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (h) Port F Block Diagram (Pin PF7) Rev.6.00 Sep. 27, 2007 Page 1254 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams C.13 Port G Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C WDRG Modes 4 to 6 PG0 Internal data bus Bus controller CAS enable* CAS output* RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Note: * Not supported in the H8S/2321. Figure C.13 (a) Port G Block Diagram (Pin PG0) Rev.6.00 Sep. 27, 2007 Page 1255 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset R Q D PGnDDR C WDDRG Reset Mode 7 PGn Modes 4 to 6 R Q D PGnDR C WDRG CS25E Internal data bus Interrupt controller Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS25E: Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable Note: n = 1 or 2 Figure C.13 (b) Port G Block Diagram (Pins PG1 and PG2) Rev.6.00 Sep. 27, 2007 Page 1256 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Reset WDDRG Reset Mode 7 PG3 Modes 4 to 6 R Q D PG3DR C WDRG Internal data bus Interrupt controller CS167E Bus controller Chip select R Q D PG3DDR C RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS167E: Write to PGDDR Write to PGDR Read PGDR Read port G CS167 enable Figure C.13 (c) Port G Block Diagram (Pin PG3) Rev.6.00 Sep. 27, 2007 Page 1257 of 1268 REJ09B0220-0600 Appendix C I/O Port Block Diagrams Modes 4 and 5 Reset Modes 6 and 7 WDDRG Mode 7 PG4 Modes 4 to 6 Reset R Q D PG4DR C WDRG Internal data bus SR Q D PG4DDR C Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.13 (d) Port G Block Diagram (Pin PG4) Rev.6.00 Sep. 27, 2007 Page 1258 of 1268 REJ09B0220-0600 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode I/O Port States in Each Processing State Hardware Standby Mode T T T T Software Standby Mode kept kept kept [DAOE1 = 1] kept [DAOE1 = 0] T P46/DA0 4 to 7 T T [DAOE0 = 1] kept [DAOE0 = 0] T P45 to P40 P53/WAIT/ BREQO 4 to 7 4 to 6 T T T T T [BREQOE · BREQOPS + WAITE · WAITPS = 0] kept [BREQOE · BREQOPS = 1] kept [BREQOE · BREQOPS = 0] and T [BREQOE · BREQOPS + WAITE · WAITPS = 0] kept [BREQOE · BREQOPS = 1] BREQO [BREQOE · BREQOPS = 0] and Input port [BREQOE · BREQOPS + WAITE · WAITPS = 0] I/O port [BREQOE · BREQOPS = 1] BREQO [BREQOE · BREQOPS = 0] and kept I/O port Bus-Released State kept kept kept kept Program Execution State Sleep Mode I/O port I/O port I/O port I/O port Table D.1 MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 P47/DA1 4 to 7 4 to 7 4 to 7 4 to 7 Reset T T T T [WAITE · WAITPS · [WAITE · WAITPS · [WAITE · WAITPS · DDR = 1] DDR = 1] DDR = 1] T T WAIT 7 P52 to P50 4 to 7 T T T T kept kept kept kept I/O port I/O port Rev.6.00 Sep. 27, 2007 Page 1259 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode P67/CS7 P66/CS6 4 to 6 Hardware Standby Mode T Program Execution State Sleep Mode [CS167E = 0] I/O port [CS167E · DDR = 1] Input port [CS167E · DDR = 1] CS7 to CS6 I/O port I/O port [CS25E = 0] I/O port Reset T Software Standby Mode Bus-Released State [CS167E = 0], [CS167E = 0] [CS167E · DDR = 1] kept kept [CS167E · DDR = 1] [CS167E · DDR · kept OPE = 1] [CS167E · DDR = 1] T T [CS167E · DDR · OPE = 1] H kept kept [CS25E · DDR · OPE = 1] T [CS25E · DDR · OPE = 1] H [CS25E = 0], [CS25E · DDR = 1] kept kept kept [CS25E = 0] kept 7 P65 to P62 P61/CS5 P60/CS4 4 to 7 4 to 6 T T T T T T [CS25E · DDR = 1] [CS25E · DDR = 1] kept Input port [CS25E · DDR = 1] [CS25E · DDR = 1] T CS5 to CS4 7 PA7/A23 PA6/A22 PA5/A21 4 to 6 T T T T kept [AnE = 0] kept [AnE · DDR = 1] T [AnE · DDR · OPE = 1] T [AnE · DDR · OPE = 1] kept kept [AnE = 0] kept [AnE · DDR = 1] T [AnE · DDR = 1] T I/O port [AnE = 0] I/O port [AnE · DDR = 1] Input port [AnE · DDR = 1] Address output 7 T T kept kept I/O port Rev.6.00 Sep. 27, 2007 Page 1260 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode PA4/A20 4, 5 Hardware Standby Mode T Program Execution State Sleep Mode [A20E · DDR = 1] Output port [A20E+A20E · DDR = 1] Address output Reset L Software Standby Mode [A20E · DDR = 1] kept [A20E · OPE = 1] T [A20E · OPE = 1] kept Bus-Released State [A20E · DDR = 1] kept [A20E+A20E · DDR = 1] T 6 T T [A20E = 0], [A20E · DDR = 1] kept [A20E · DDR · OPE = 1] T [A20E · DDR · OPE = 1] kept [A20E = 0] kept [A20E · DDR = 1] kept [A20E · DDR = 1] T [A20E = 0] I/O port [A20E · DDR = 1] Output port [A20E · DDR = 1] Address output 7 PA3/A19 PA2/A18 PA1/A17 PA0/A16 6 4, 5 T L T T kept [OPE = 0] T [OPE = 1] kept kept T I/O port Address output T T [DDR · OPE = 0] T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output 7 Port B 4, 5 T L T T kept [OPE = 0] T [OPE = 1] kept kept T I/O port Address output 6 T T [DDR · OPE = 0] T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output 7 T T kept kept I/O port Rev.6.00 Sep. 27, 2007 Page 1261 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode Port C 4, 5 Hardware Standby Mode T Program Execution State Sleep Mode Address output Reset L Software Standby Mode [OPE = 0] T [OPE = 1] kept Bus-Released State T 6 T T [DDR · OPE = 0] T [DDR · OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output 7 Port D 4 to 6 7 Port E 4 to 8-bit 6 bus T T T T T T T T T T kept T kept kept T kept [DDR = 0] Input port [DDR = 1] H kept T kept kept T kept [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output [ASOD = 1] kept [ASOD = 0] T I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output [ASOD = 1] I/O port [ASOD = 0] AS 16-bit T bus 7 PF7/φ 4 to 6 Clock output T 7 T T [DDR = 0] Input port [DDR = 1] H PF6/AS 4 to 6 H T [ASOD = 1] kept [ASOD · OPE = 1] T [ASOD · OPE = 1] H 7 PF5/RD PF4/HWR 4 to 6 T H T T kept [OPE = 0] T [OPE = 1] H kept T I/O port RD, HWR 7 T T kept kept I/O port Rev.6.00 Sep. 27, 2007 Page 1262 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode PF3/LWR 4 to 6 Hardware Standby Mode T Program Execution State Sleep Mode [LWROD = 1] I/O port [LWROD = 0] LWR Reset H Software Standby Mode [LWROD = 1] kept Bus-Released State [LWROD = 1] kept [LWROD · OPE = 1] [LWROD = 0] T T [LWROD · OPE = 1] H 7 PF2/LCAS* / 4 to 6 WAIT/ BREQO 1 T T T T kept [LCASE* + BREQOE · BREQOPS + WAITE · WAITPS =0 kept [BREQOE · BREQOPS = 1] and 2 [LCASE* = 0] kept [WAITE · WAITPS · DDR = 1] and 2 [LCASE* + BREQOE · BREQOPS = 0] T [LCASE* = 1, OPE = 0] T [LCASE* = 1, OPE = 1] H 2 2 2 kept [LCASE* + BREQOE · BREQOPS + WAITE · WAITPS =0 kept [BREQOE · BREQOPS = 1] and 2 [LCASE* = 0] BREQO [WAITE · WAITPS · DDR = 1] and 2 [LCASE* + BREQOE · BREQOPS = 0] T [LCASE* = 1] T 2 2 I/O port [LCASE* + BREQOE · BREQOPS + WAITE · WAITPS =0 I/O port [BREQOE · BREQOPS = 1] and 2 [LCASE* = 0] BREQO [WAITE · WAITPS · DDR = 1] and 2 [LCASE* + BREQOE · BREQOPS = 0] WAIT [LCASE* = 1] 1 LCAS* 2 2 7 PF1/BACK 4 to 6 T T T T kept [BRLE=0] kept [BRLE=1] BACK kept L I/O port [BRLE = 0] I/O port [BRLE = 1] BACK 7 T T kept kept I/O port Rev.6.00 Sep. 27, 2007 Page 1263 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode PF0/BREQ 4 to 6 Hardware Standby Mode T Program Execution State Sleep Mode [BRLE = 0] I/O port [BRLE = 1] BREQ kept T I/O port [DDR = 0] Input port [DDR = 1] CS0 kept [CS167E = 0] kept I/O port [CS167E = 0] I/O port [CS167E · DDR = 1] Input port [CS167E · DDR = 1] CS1 Reset T Software Standby Mode [BRLE=0] kept [BRLE=1] T Bus-Released State T 7 PG4/CS0 4, 5 6 7 PG3/CS1 4 to 6 T H T T T T T kept [DDR · OPE = 0] T [DDR · OPE = 1] H T T kept [CS167E = 0] kept [CS167E · DDR = 1] [CS167E = 1] T T [CS167E · DDR · OPE = 1] T [CS167E · DDR · OPE = 1] H 7 PG2/CS2 PG1/CS3 4 to 6 T T T T kept [CS25E = 0] kept [CS25E · DDR = 1] T [CS25E · DDR · OPE = 1] T [CS25E · DDR · OPE = 1] H 7 5 WDTOVF* 4 to 7 kept [CS25E = 0] kept [CS25E = 1] T I/O port [CS25E = 0] I/O port [CS25E · DDR = 1] Input port [CS25E · DDR = 1] CS2 to CS3 T H T H kept H kept H I/O port H* 6 Rev.6.00 Sep. 27, 2007 Page 1264 of 1268 REJ09B0220-0600 Appendix D Pin States MCU Port Name Operating Pin Name Mode PG0/CAS* 3 Reset T Hardware Standby Mode T Software Standby Mode [DRAME* = 0] kept [DRAME* · OPE = 1] T [DRAME* · OPE = 1] 3 CAS* 4 4 4 Bus-Released State T Program Execution State Sleep Mode [DRAME* = 0] Input port [DRAME* = 1] 3 CAS* 4 4 4 to 6 7 T T kept kept I/O port Legend: H: High level L: Low level T: High impedance kept: Input port becomes high-impedance, output port retains state DDR: Data direction register OPE: Output port enable WAITE: Wait input enable WAITPS: WAIT pin select BRLE: Bus release enable BREQOE: BREQO pin enable BREQOPS: BREQO pin select DRAME: DRAM space setting LCASE: DRAM space setting, 16-bit access setting AnE: Address n enable (n = 23 to 21) A20E: Address 20 enable ASOD: AS output disable CS167E: CS167 enable CS25E: CS25 enable LWROD: LWR output disable Notes: 1. LCAS is not supported in the H8S/2321. 2. As the DRAM interface is not supported in the H8S/2321, LCASE is always 0. 3. CAS is not supported in the H8S/2321. 4. As the DRAM interface is not supported in the H8S/2321, DRAME is always 0. 5. The WDTOVF pin function is not usable on the F-ZTAT version. 6. A low level is output if a WDT overflow occurs while WT/IT is set to 1. Rev.6.00 Sep. 27, 2007 Page 1265 of 1268 REJ09B0220-0600 Appendix E Product Lineup Appendix E Product Lineup Table E.1 H8S/2329 Group, H8S/2328 Group Product Lineup Model F-ZTAT™ HD64F2329B HD64F2329E* H8S/2328 Mask ROM version F-ZTAT™ H8S/2327 H8S/2326 H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320 Mask ROM version F-ZTAT™ ROMless version Mask ROM version ROMless version ROMless version ROMless version HD6432328 HD64F2328B HD6432327 HD64F2326 HD6412324S HD6432323 HD6412322R HD6412321 HD6412320 Marking HD64F2329BVTE HD64F2329BVF HD64F2329EVTE HD64F2329EVF HD6432328TE HD6432328F HD64F2328BVTE HD64F2328BVF HD6432327TE HD6432327F HD64F2326VTE HD64F2326VF HD6412324SVTE HD6412324SVF HD6432323TE HD6432323F HD6412322RVTE HD6412322RVF HD6412321VTE HD6412321VF HD6412320VTE HD6412320VF Package (Package Code) 120-pin TFP (TFP-120) 128-pin FP (FP-128B) 120-pin TFP (TFP-120) 128-pin FP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TFP (TFP-120) 128-pin FP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TFP (TFP-120) 128-pin FP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TFP (TFP-120) 128-pin FP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) Product Type H8S/2329 Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions are unavailable when the onchip debug function is in use. Refer to figures 1.7 and 1.8. Rev.6.00 Sep. 27, 2007 Page 1266 of 1268 REJ09B0220-0600 Appendix F Package Dimensions Appendix F Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 61 91 60 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 E HE c Terminal cross section ZE Reference Dimension in Millimeters Symbol 120 31 A2 ZD Index mark F A c 1 30 θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Min Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.12 0.17 0.22 0.15 0.12 0.17 0.22 0.15 0° 8° 0.4 0.07 0.10 1.20 1.20 0.4 0.5 0.6 1.0 Figure F.1 TFP-120 Package Dimensions Rev.6.00 Sep. 27, 2007 Page 1267 of 1268 REJ09B0220-0600 Appendix F Package Dimensions JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 D 65 64 102 103 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 c1 39 ZE c 128 1 ZD Index mark 38 Terminal cross section Reference Dimension in Millimeters Symbol F θ A1 L L1 e *3 y bp x M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 20 14 2.70 21.8 22.0 22.2 15.8 16.0 16.2 3.15 0.00 0.10 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 8˚ 0˚ 0.5 0.10 0.10 0.75 0.75 0.3 0.5 0.7 1.0 Min A A2 Figure F.2 FP-128B Package Dimensions Rev.6.00 Sep. 27, 2007 Page 1268 of 1268 REJ09B0220-0600 c Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2329 Group Publication Date: 1st Edition, March 1999 Rev.6.00, September 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.0 H8S/2329 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0220-0600