HA16107P

HA16107P/FP, HA16108P/FP PWM Switching Regulator for High-performance Voltage Mode Control REJ03F0141-0400 (Previous: ADE-204-012C) Rev.4.00 Jun 15, 2005 Description The IC products in this series are primary control switching regulator control IC’s appropriate for obtaining stabilized DC voltages from commercial AC power. These IC’s can directly drive power MOS FET’s, they have a timer function built in to the secondary overcurrent protection, and they can perform intermittent operation or delayed latched shutdown as protection operations in unusual conditions. They can be used to implement switching power supplies with a high level of safety due to the wide range of built-in functionality. Functions • • • • • • • • • • 6.45 V reference voltage Triangle wave generator Error amplifier Under voltage lockout protector PWM comparator Pulse-by-pulse current limitting Timer-latch current limitting (HA16107) ON/OFF timer function (HA16108) Soft start and quick shutdown Output circuit for power MOS FET driving Features • • • • • • Operating frequencies up to a high 600 kHz Built-in pre-driver circuit for driving power MOS FET Built-in timer latch over-current protection function (HA16107) The OCL enables intermittent operation by an ON/OFF timer for prevention of secondary overcurrent. (HA16108) The UVL function (under voltage lockout) is applied to both Vin and Vref. ON/OFF reset: an auto-reset function which is based on the time constant of an external capacitor and observation of drops in Vin. • Since the over-voltage protection function OVP (the TL pin) only observes voltage drops in Vin, it is possible to use the OVP and ON/OFF pin for independent purposes. • Built-in 34 V Zener diode between Vin and ground. Rev.4.00 Jun 15, 2005 page 1 of 39 HA16107P/FP, HA16108P/FP Ordering Information Typical Threshold Voltage Product HA16107P HA16107FP HA16108P HA16108FP UVL1 Hi: 16.2 V Lo: 9.5 V Hi: 16.2 V Lo: 9.5 V OVP 7.0 V Notes Timer latch protection Package Code (Previous Code) DP-16 PRSP0016DH-A (FP-16DA) DP-16 PRSP0016DH-A (FP-16DA) Hi: 7.0 V Lo: 1.3 V On-off timer protection Pin Arrangement VIN OUT CL(+) VE CL(−) RT1 CT RT2 1 2 3 4 5 6 7 8 (Top view) Notes: 1. In the SOP package models (HA16107FP and HA16108FP) pins 4, 5, and 13 are connected inside the IC. However, all must be connected to the system ground. 2. Pin 16 is TL (HA16107), ON/OFF (HA16108). 16 15 14 13 12 11 10 9 Note 2 TL, ON/OFF E/O IN(−) NC GND IN(+) ST Vref Note 1 Rev.4.00 Jun 15, 2005 page 2 of 39 HA16107P/FP, HA16108P/FP Pin Functions • HA16107P, HA16108P Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VIN OUT CL (+) VE CL (–) RT1 CT RT2 Vref ST IN (+) GND NC IN (–) E/O TL, ON/OFF Symbol Input voltage Pulse output Current limiter Output ground Current limiter Timing resistor (rising time) Timing capacitor Timing resistor (falling time) Reference voltage output Soft start Error amp (+) input Ground NC Error amp (–) input Error output Timer latch (HA16107), ON/OFF (HA16108) Pin Functions • HA16107FP, HA16108FP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VIN OUT CL (+) GND GND RT1 CT RT2 Vref ST IN (+) GND GND IN (–) E/O TL, ON/OFF Symbol Input voltage Pulse output Current limiter Ground Ground Timing resistor (rising time) Timing capacitor Timing resistor (falling time) Reference voltage output Soft start Error amp (+) input Ground Ground Error amp (–) input Error output Timer latch (HA16107), ON/OFF (HA16108) Pin Functions Rev.4.00 Jun 15, 2005 page 3 of 39 HA16107P/FP, HA16108P/FP Block Diagram • HA16107P/FP TL 16 E/O 15 EA − Error amp. + IN (−) 14 NC 13 GND 12 IN (+) 11 ST 10 Vref 9 140 µA UVL1 16 µA H L VL V H RQ S 4 µA On/Off latch (VTH = 7 V) VIN 6.45 V zener type Ref. voltage Gen. UVL2 O V P UVL1 ST Triangle waveform H L 34 V Vref UVL2 4V 5V + + − PWM Comparator UVL1 and UVL2 Pulse-by-pulse latch QR QCLM OUT QS VC VE Vref Current limiter Triangle waveform OSC Triangle waveform Latch reset pulse ON duty pulse 3.4 V 10 µA 1 VIN 2 OUT 3 CL (+) 4 VE 5 CL (−) 6 RT1 7 CT 8 RT2 • HA16108P/FP ON/OFF 16 E/O 15 EA − IN (−) 14 Error amp. + NC 13 GND 12 IN (+) 11 ST 10 Vref 9 140 µA UVL1 16 µA H L VL V H RQ S 4 µA On/Off latch (VTH = 7 V) VIN 6.45 V zener type Ref. voltage Gen. UVL2 O V P UVL1 ST Triangle waveform H L 34 V Vref UVL2 4V 5V + + − PWM Comparator UVL1 and UVL2 Pulse-by-pulse latch QR QCLM OUT QS VC VE Vref Current limiter Triangle waveform OSC Triangle waveform Latch reset pulse ON duty pulse 3.4 V 10 µA 1 VIN 2 OUT 3 CL (+) 4 VE 5 CL (−) 6 RT1 7 CT 8 RT2 Note: Dotted lines apply to the SOP package model (pins 4, 5, and 13: ground) Rev.4.00 Jun 15, 2005 page 4 of 39 HA16107P/FP, HA16108P/FP Function and Timing Chart Triangle Waveform and PWM Output • Timing chart (during normal operation) VTH 4.2 V typ E/O CT Triangle waveform is output to CT pin 2VBE 0V VIN 0V VTL 2.2 V typ VRT2 OUT Dead band tDB • Oscillator equivalent circuit 9 ×2 ×2 RT2 ×2 8 I1 I1 I2 VRT2 tON Vref (connected internally) − + 6 RT1 CT 7 2I2 ×2 0.6 V Comparator for triangle waveform oscillation − + The × 2s are transistors whose emitter area is doubled. Vref − 2VBE RT1 Vref − 2VBE I2 = RT2 I1 = tDB = tON ≈ CT × RT1 × 2V ≈ 0.4 × CT × RT1 (s) Vref − 2VBE RT2 tDB (s) 2RT1 − RT2 Du max = fOSC ≈ RT2 2RT1 1 − Du max (Hz) tDB Note: When fOSC is high, the actual value will differ from that given by the formula due to the delay time. Determine the correct constants after constructing a test circuit. Rev.4.00 Jun 15, 2005 page 5 of 39 HA16107P/FP, HA16108P/FP 1. Timing in Normal Operation Timing in these ICs is based on a triangular voltage waveform. The rising edge (leading edge) defines the deadband time tDB. The falling edge (trailing edge) defines the ON-duty control band tON. PWM output is on in the area within tON that is bounded above by the triangle wave VCT and error output VE/O. The following pin outputs are related to PWM control:  CT (pin 7): triangle-wave voltage output  E/O (pin 15): error output voltage  RT2 (pin 8): ON-duty pulse output voltage  OUT (pin 2): PWM pulse output (for driving the gate of a power MOS FET) 2. Triangle Oscillator, Waveform and Frequency The triangle oscillator in these ICs generates a triangular waveform by charging and discharging timing capacitor CT with a constant current, as shown in the equivalent circuit. The CT charge current is: I(CTchg) = I1 = VREF − 2VBE RT1 VREF − 2VBE RT2 The discharge current is: I(CTdischg) = 2I2 − I1, where I2 = In these equations Vref (reference voltage) is typically 6.45 V, and VBE (base-emitter voltage of internal transistors) is about 0.7 V. The deadband time is: tDB = CT × RT1 × 2V + 0.25 µs VREF − 2VBE ≈ 0.4 × CT × RT1 + 0.25 µs The ON-duty time is: tON = tDB × RT2 2RT1 − RT2 The 0.25 µs in these equations is a correction term for internal circuit delays. The maximum ON-duty is Du max = RT2 2RT1 The oscillating frequency is: fOSC = 1 0.4 CT RT1 + 0.25 µ + 0.25 µ RT2 1– 2RT1 1 (Hz) = 0.8 CT RT12 + 0.25µ × 2RT1 + 0.25 µ 2RT1 − RT2 When RT1 = RT2, the maximum ON-duty is 50%, and: fOSC ≈ = 1 0.8 CT RT1 + 0.25 µ × 2 + 0.25 µ 1 (Hz) 0.8 CT RT1 + 0.75 µ This approximation is fairly close, but it should be checked in-circuit. Rev.4.00 Jun 15, 2005 page 6 of 39 HA16107P/FP, HA16108P/FP 3. Programming of Maximum ON-Duty (Du Max) The preceding equations should be used to program the deadband or maximum ON-duty. The following table gives a summary. Condition Triangle waveform Du max Less than 50% 50% Greater than 50%* Note: In a primary-control switching regulator, Du Max > 50% is dangerous because the transformer will saturate. RT1 > RT2 RT1 = RT2 RT1 < RT2 Soft Start and Quick Shutdown One purpose of the soft-start function is to protect the switching controller and power MOS FET from surges at powerup. Another purpose is to let the secondary-side DC voltage rise smoothly. When power goes off, the quick-shutdown function rapidly discharges the capacitor in the soft-start circuit (and at the same time switches the PWM output off) to prepare for the next power-on. The soft-start function in these ICs lets the PWM output develop smoothly from zero to the designated pulse width at power-up. The soft-start voltage is the 3.8 V voltage value of an internal Zener diode, so the PWM output is able to start widening gradually as soon as the soft-start function starts operating. The soft-start function will start promptly even if CST is large. The soft-start and quick-shutdown modes are selected automatically in the IC, under control of the UVL signal. Rev.4.00 Jun 15, 2005 page 7 of 39 HA16107P/FP, HA16108P/FP • Timing waveforms Level determined by transformer 16.2 V VIN 9.5 V 6.45 V 5V 4V 0V 4.2 V 3.8 V 2.2 V 0V VE/O VOUT (PWM pulse) VIN 0V Soft start Normal operation (Time t) Quick shutdown Vref VIN Vref VST VCT, VST, VE/O VCT CST discharge Vref 9 CST ST 10 3.8 V Zener diode 10 µA Vref from Vref from UVL2 (Effective for quick shutdown) + + − PWM comparator VCT E/O 15 7 Note: The soft-start time constant is determined by CST and the constant-current value (typically 10 µA). Rev.4.00 Jun 15, 2005 page 8 of 39 HA16107P/FP, HA16108P/FP Vref Protection Functions: Overvoltage and Undervoltage Vref overvoltage and undervoltage conditions are detected by the overvoltage detection circuit and UVL2 circuit. PWM output shuts down when Vref ≥ 8 V. UVL2 detects undervoltage with hysteresis between approximately 4 V and 5 V. PWM output also shuts down below these voltages. It follows that PWM output will shut off whenever the Vref pin is shorted to the power supply (VIN) or ground (GND). PWM output also shuts off when VIN is turned on or off. The following diagram shows how these protection functions operate when power comes on and goes off (Vref < 6.45 V), and when a high external voltage is applied to the Vref pin (Vref > 6.45 V). PWM output shutdown region Power-off, or shorted to ground PWM output operating region PWM OUT Shorted to power supply Power-up PWM output shut-down region Vref 0 4V 5V 6.45 V 8 V 10 V Vref OVP UVL2 1. Current-Limiter Circuit The current limiter pin (CL) is connected to the emitter of an npn transistor, as shown in the block diagram. The threshold voltage is 240 mV typ. The switching speed of this circuit is approximately 100 ns from detection of overcurrent to shut-down of PWM output. Switching speed increases with the strength of the signal input to the CL pin. Instead of simple pulse-by-pulse current limiting, in these ICs the current limiting circuit is linked to the timer-andlatch or ON/OFF timer circuit, and also detects the degree of overcurrent. The overcurrent value is determined from the point at which current limiting is triggered in the ON-duty cycle. With a large overcurrent (causing current limiting to operate even at a small ON-duty), the IC automatically shortens the timer time. Rev.4.00 Jun 15, 2005 page 9 of 39 HA16107P/FP, HA16108P/FP Undervoltage Lockout and PWM Output The undervoltage lockout function turns off the PWM pulse output when the controller’s supply voltage goes below a designated value. These ICs have two undervoltage lockout circuits. The UVL1 circuit senses the supply voltage VIN. The UVL2 circuit senses the Vref voltage. A feature of these ICs is that PWM output is turned on only when both voltages are above designated values. Otherwise, the IC operates in standby mode. The two built-in undervoltage lockout circuits make it possible to configure an extremely safe power supply system. PWM output will shut down under a variety of abnormal conditions, such as if Vref is shorted to ground while VIN is applied. • UVL1 (VIN and Vref) IIN 9.5 V 16.2 V *1 0 Vref 10 V 20 V 30 V 6.45 V 34 V VIN Notes: 1. Breakdown voltage of the internal Zener diode (Vz = 34 V typ). 2. Hysteresis characteristic. VIN *2 0 10 V 20 V 30 V • UVL2 (Vref and PWM output) Vref 4V 0 10 V 5V VIN 6.45 V 20 V 30 V Operating region OUT 0 10 V 20 V PWM output shut-down region • UVL1 and UVL2 VIN (UVL1) Vref (UVL2) PWM OUT Standby mode L L L 30 V VIN H L L H H OUT  L H L Note: Double circles indicate standby mode. Rev.4.00 Jun 15, 2005 page 10 of 39 HA16107P/FP, HA16108P/FP Timer Latch and ON/OFF Timer The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function. The timer-latch function is an overvoltage protection function that combines latched shutdown of PWM output with a timer function to vary the time until latched shutdown occurs according to the overcurrent value. A dedicated voltage detection pin is provided in addition to Vref overvoltage protection. The ON/OFF timer function is equivalent to the above timer-latch function without the latch. If overcurrent is detected continuously, PWM output shuts down temporarily, then normal operation resumes. This process repeats, temporary shutdown alternating with normal operation. Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an interval after overcurrent detection before shutting down PWM output. The interval is determined by capacitor CTM and the value of the charge/discharge current supplied internally from the IC. Normal operation therefore continues if a single overcurrent spike is detected, while if continuous overcurrent is detected, the current and voltage droop curves for the secondary-side output have sharp characteristics. 1. Use of Timer-Latch Pin (HA16107)  Timer-Latch Usage See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns on, charging CTM with 12 µA. PWM output shuts down when the voltage at pin 15 exceeds 7 V.  Overvoltage Protection Usage See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an OVP signal received through an optocoupler from the DC output on the secondary side of an AC/DC converter. PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7 V. The shutdown is latched. VIN must go below approximately 6.5 V (VINR2) to release the latched state. • External circuit 1 16 µA from CML OVP with latch timer 4 µA HA16107 7.0 V VTL A 0V OCL detected continuously (activating pulse-by-pulse current limiter) Notes: 1. Path A is followed if the OCL input stops before VTH is reached. 2. Path B is followed if OCL is detected continuously until the latch point is reached. 3. The latch function is cleared when VIN goes below approximately 7.0 V. t VTH Latch (PWM output shuts down) B OVP signal (from secondary) • External circuit 2 VIN 15 CTM TL Rev.4.00 Jun 15, 2005 page 11 of 39 HA16107P/FP, HA16108P/FP 2. Use of ON/OFF Timer Pin (HA16108)  External Circuit 16 µA ION + 16 IOFF 4 µA HA16108 from CML OVP with latch timer  ON/OFF Timer Operation tOFF tON 7.0 V VTHH 1.2 V 0V VTHL t OCL detected PWM OCL detected (PWM output on) output (PWM output on) shut down Pulse-by-pulse current limiting tON ≈ C × 5.8 V (0.9 − Du) × 16 µA − 4 µA tOFF ≈ C × 5.8 V 4 µA Notes: 1. C is the capacitance of an external timing capacitor connected between this pin and ground. 2. Du is the ON-duty of the PWM output when overcurrent limiting is triggered. 3. The values of tON and tOFF for TL can be determined by the same equations as given for the ON/OFF timer, except that 5.8 V (VTHH − VTHL) becomes VTHH = 7 V. 4. If the timer goes off during soft start or in the undervoltage lockout region, after recovery, output will come on after the soft-start time or after the rise time to the undervoltage lockout release point, which is determined by the time constant. Rev.4.00 Jun 15, 2005 page 12 of 39 HA16107P/FP, HA16108P/FP Absolute Maximum Ratings (Ta = 25°C) Item Supply voltage Output current (DC) Output current (peak) Current limiter voltage Error amp input voltage E/O output voltage RT1 pin current RT2 pin current Power dissipation Operating temperature range Storage temperature range VIN IO Iopeak VCL VIEA VIE/O IRT1 IRT2 PT Topr Tstg Symbol 30 ±0.2 ±2 +4, –1 Vref Vref 500 5 680 –20 to +85 –55 to +125 Rating Value V A A V V V µA mA mW °C °C 1, 2 Units Notes Notes: 1. For the “FP” products (SOP package), this value is when mounted on a 40 by 40 by 1.6 mm glass epoxy substrate. However, this value must be derated by 8.3 mW/°C from Ta = 45°C. When the wiring density is 10%, and 11.1 mW/°C from Ta = 64°C when the wiring density is 30%. 2. For the “P” products (DIP package), this value is valid up to 45°C, and must be derated by 8.3 mW/°C above 45°C. 3. In the case of SOP, use center 4 pins, (4), (5), (12), (13) for solder-mounting and connect the wide ground pattern, because these pins are available for heat sink of this IC. Power dissipation PT (mW) 700 600 500 400 300 200 100 −20 0 20 45°C 64°C 30% Wiring density 10% Wiring density 40 60 80 100 120 140 Ambient temperature Ta (°C) Rev.4.00 Jun 15, 2005 page 13 of 39 HA16107P/FP, HA16108P/FP Electrical Characteristics (Ta = 25°C, VIN = 18 V, fOSC = 100 kHz) Section Reference voltage Item Output voltage Line regulation Load regulation Temperature stability Short circuit current Over voltage protection (Vref OVP voltage) Maximum frequency Minimum frequency Voltage stability Temperature stability Frequency accuracy PWM comparator Minimum deadband pulse width Low level threshold voltage High level threshold Differential threshold Deadband width initial accuracy Deadband width voltage stability Deadband width temperature stability Input offset voltage Input bias current Input sink current Output source current High level output voltage Low level output voltage Voltage gain Band width (–) Common mode voltage (+) Common mode voltage (+) Threshold voltage (+) Bias current (–) Threshold voltage (–) Bias current Response time Symbol Vref Line Load ∆Vref/ ∆Ta IOS Vrovp Min 6.10 – – – 30 7.4 Typ 6.45 30 30 40 50 8.0 Max 6.80 60 60 – – 9.0 Unit V mV mV ppm/ °C mA V Test Conditions 12 V ≤ VIN ≤ 30 V 0 mA ≤ IO ≤ 10 mA Note Vref = 0 V Triangle wave generator fmax fmin ∆f/fo1 ∆f/fo2 fOSC tDB VTL VTH ∆VTH ∆DB1 ∆DB2 ∆DB3 VIO IIB Iosink Iosource VOH VOL GV BW VCM– VCM+ VTH+ IB+ VTH– IB– toff 600 – – – 270 – 1.9 3.8 1.7 – – – – – 80 80 Vref – 1.5 – – – 1.2 – 0.216 – –0.264 – – – – ±1 ±1 300 – 2.2 4.2 2.0 ±1 ±0.2 ±1 2 0.8 140 140 – – 55 15 – – 0.240 180 –0.240 950 100 – 1 ±3 – 330 1.0 2.5 4.6 2.3 ±3 ±2.0 – 10 2.0 – – – 0.5 – – – Vref – 1.5 0.264 250 –0.216 1350 – kHz kHz % % kHz µs V V V % % % mV µA µA µA V V dB MHz V V V µA V µA ns VCL+ = 0 V 1, 2 VCL = –0.3 V CL; open VCL = +0.35 V 1, 2 VO = 2 V VO = 5 V IO = 10 µA IO = 10 µA f = 10 kHz RT1 = RT2 = 27 kΩ CT = 470 pF 12 V ≤ VIN ≤ 30 V (Dmax – Dmin)/2 –20°C ≤ Ta ≤ +85°C (Dmax – Dmin)/2 12 V ≤ VIN ≤ 30 V fo1 = (fmax + fmin)/2 –20°C ≤ Ta ≤ +85°C fo2 = (fmax + fmin)/2 RT1 = RT2 = 27 kΩ CT = 120 pF Error amp Overcurrent detector Notes: 1. Only applies to the HA16107P, HA16108P 2. The terminal should not be applied under –1.0 V. Rev.4.00 Jun 15, 2005 page 14 of 39 HA16107P/FP, HA16108P/FP Electrical Characteristics (cont.) (Ta = 25°C, VIN = 18 V, fOSC = 100 kHz) Section Soft start Under voltage lockout 1 Item High level voltage Sink current VIN high level threshold voltage VIN low level threshold voltage Threshold differential voltage Vref high level threshold voltage Vref low level threshold voltage Latch threshold voltage VIN reset voltage Reset voltage Differential threshold to UVL low voltage Source current (OCL mode) Sink current (latch mode) Output Low voltage High voltage Low voltage (standby mode) Rising time Total Falling time Standby current Operation current Symbol VSTH Isink VINTH VINTL ∆VTH VrTH VrTL VTHH VINR2 VTHL2 ∆V Isource Isink VOL1 VOH VOL2 tr tf Ist IIN1 Min 3.2 7 14.7 8.5 5.2 4.5 3.5 6.5 6.0 1.0 2.0 8 2.5 – VIN – 2.2 – – – – – Typ 3.8 10 16.2 9.5 6.2 5.0 4.0 7.0 6.5 1.3 3.0 12 4 1.7 – – 40 60 160 16 Max 4.4 13 17.7 10.5 7.2 5.5 4.5 7.5 7.0 1.6 – 16 5.5 2.2 – 0.5 — — 250 20 Unit V µA V V V V V V V V V µA µA V V V ns ns µA mA 1 (VINTL – VINR2) Over current detection mode TL(ON/OFF) terminal = 4 V Iosink = 0.2 A Iosource = 0.2 A Iosink = 1 mA CL = 1000 pF CL = 1000 pF VIN = 14 V VIN = 30 V, CL = 1000 pF, f = 100 kHz VIN = 30 V, f = 100 kHz, Output open VIN = 14 V Latch threshold voltage (VINTH – VINTL) Test Conditions Isink = 1 mA VST = 2.0 V Note Under voltage lockout 2 Timer latch, ON/OFF 2 timer * Operation current IIN2 – 12 16 mA ON/OFF latch current VIN – GND Zener voltage IIN3 VZ – 30 350 34 460 – µA V Notes: 1. Only applies to the HA16108P/FP. 2. Timer latch: HA16107P/FP. ON/OFF timer: HA16108P/FP. Rev.4.00 Jun 15, 2005 page 15 of 39 HA16107P/FP, HA16108P/FP Note on Standby Current In the test circuit shown in figure 1, the operating current at the start of PWM pulse output is the standby current. If the resistance connected externally to the Vref pin (including RT2) is smaller than that of the test circuit, the apparent standby current will increase. VIN Vref HA16107 Series Rref Figure 1 Standby Current Test Circuit Rev.4.00 Jun 15, 2005 page 16 of 39 ↑ Ist + CIN ↑ IIN HA16107P/FP, HA16108P/FP Application Note • Case: When DC power is applied directly as the power supply of the HA16107/HA16108, without using the transformer backup coil. • Phenomenon: The IC may not be activated in the case of a circuit in which VIN rises quickly (10 V/100 µs or faster), such as that shown in figure 2. • Reason: Because of the IC circuit configuration, the timer latch block operates first. • Remedy (counter measure): Take remedial action such as configuring a time constant circuit as shown in figure 3, to keep the VIN rise speed below 10 V/100 µs. If the IC power supply consists of an activation resistance and backup coil, as in an AC/DC converter, The VIN rise speed is usually around 1 V/100 µs, and there is no risk of this phenomenon occurring. Output Input VIN HA16107 Series VIN GND Feedback Figure 2 Example of Circuit with Fast VIN Rise Time Input Time constant circuit R 51Ω VIN Output VIN 18 V 1 µF C HA16107 Series Feedback GND Figure 3 Sample Remedial Circuit Rev.4.00 Jun 15, 2005 page 17 of 39 HA16107P/FP, HA16108P/FP Characteristic Curves Operating Current vs. Power Supply Voltage 40 Ta = 25°C RT1 = RT2 = 27 kΩ CT = 470 pF 30 Operating current (mA) fOSC = 100 kHz 20 10 0 10 20 30 40 Power supply voltage (V) Latch Current vs. Power Supply Voltage 2.0 Ta = 25°C RT1 = RT2 = 27 kΩ CT =470 pF 1.5 Latch current (mA) fOSC = 100 kHz 1.0 0.5 0 10 20 Power supply voltage (V) 30 40 Rev.4.00 Jun 15, 2005 page 18 of 39 HA16107P/FP, HA16108P/FP Standby Current vs. Power Supply Voltage 400 Ta = 25°C RT1 = RT2 = 27 kΩ CT =470 pF 300 Standby current (µA) fOSC = 100 kHz 200 100 0 4 8 12 16 20 Power supply voltage (V) Output VOH vs. Reference Voltage 20 Ta = 25°C VIN = 20 V CT = 470 pF 15 Output VOH (V) 10 Vref UVL2 Voltage Vref OVP Voltage 5 0 2 4 6 8 10 Reference voltage (V) Rev.4.00 Jun 15, 2005 page 19 of 39 HA16107P/FP, HA16108P/FP Reference Voltage vs. Power Supply Voltage 8 Ta = 25°C RT1 = RT2 = 27 kΩ CT =470 pF fOSC = 100 kHz Reference voltage (V) 6 4 2 0 10 20 Power supply voltage (V) 30 Output OFF Time vs. VCL 400 Ta = 25°C RT1 = RT2 = 27 kΩ CT =470 pF fOSC = 100 kHz 300 Output OFF time (ns) VCL 200 CL = 100 pF 100 CL = unloaded 0 0.2 VCL (V) 0.3 0.4 Rev.4.00 Jun 15, 2005 page 20 of 39 HA16107P/FP, HA16108P/FP Output ON Duty vs. Error Input Voltage 60 50 Ta = 25°C RT1 = RT2 = 27 kΩ CT =470 pF fOSC = 100 kHz Output ON duty (%) 40 30 20 10 0 1 2 3 4 5 Error input voltage (V) Rev.4.00 Jun 15, 2005 page 21 of 39 HA16107P/FP, HA16108P/FP Reference Voltage and PWM Out vs. CL(+) Vref 0 0.1 0.2 0.3 0.4 3.0 PWM OUT 0 0.1 0.2 CL(+) 0.3 0.4 3.0 Reference Voltage and PWM Out vs. CL(−) Vref 0 −0.1 −0.2 −0.3 −0.4 −1.0 PWM OUT 0 −0.1 −0.2 CL(−) −0.3 −0.4 −1.0 Rev.4.00 Jun 15, 2005 page 22 of 39 HA16107P/FP, HA16108P/FP Timing Resistance vs. Deadband Duty 20 VIN = 18V Ta = 25°C Timing resistance RT1,RT2 (kΩ) 15 CT = 470 pF fOSC ≈ 100 kHz 10 RT1 RT2 5 0 30 40 50 60 70 80 Deadband duty (%) Temperature Fluctuation vs. Ambient Temperature 2000 VIN = 18V RT1 = RT2 = 27 kΩ Temperature fluctuation (ppm) 1000 CT = 470 pF fOSC = 100 kHz 0 −1000 −2000 −20 0 25 50 75 85 Ambient temperature (°C) Rev.4.00 Jun 15, 2005 page 23 of 39 HA16107P/FP, HA16108P/FP Frequency Variance vs. Ambient Temperature 10 VIN = 18V RT1 = RT2 = 27 kΩ CT = 470 pF Frequency variance (%) 5 fOSC = 100 kHz 0 −5 −10 −20 0 25 50 75 85 Ambient temperature (°C) Frequency Variance vs. Ambient Temperature 10 VIN = 18V RT1 = RT2 = 27 kΩ CT = 120 pF 5 Frequency variance (%) fOSC = 300 kHz 0 −5 −10 −20 0 25 50 75 85 Ambient temperature (°C) Rev.4.00 Jun 15, 2005 page 24 of 39 HA16107P/FP, HA16108P/FP Frequency Variance vs. Ambient Temperature 10 VIN = 18V RT1 = RT2 = 13 kΩ CT = 120 pF 5 Frequency variance (%) fOSC = 600 kHz 0 −5 −10 −20 0 25 50 75 85 Ambient temperature (°C) Output ON Duty Variance vs. Ambient Temperature 10 VIN = 18V Output ON duty variance (%) 5 0 f = 100 kHz f = 300 kHz −5 f = 600 kHz −10 −20 0 25 50 75 85 Ambient temperature (°C) Rev.4.00 Jun 15, 2005 page 25 of 39 HA16107P/FP, HA16108P/FP Oscillator Frequency vs. Timing Resistance 600 500 VIN = 18 V Ta = 25°C 300 C T = 12 0 pF 27 0 pF Oscillator frequency (kHz) 100 90 70 50 47 0 pF 82 0 pF 30 33 00 pF 10 9 7 5 7 10 30 50 70 100 Timing resistance RT1 (= RT2) (kΩ) Rev.4.00 Jun 15, 2005 page 26 of 39 HA16107P/FP, HA16108P/FP Vout Output Rising Waveform 40 30 Test circuit Ta = 25°C RT1 = RT2 = 27 kΩ CT = 470 pF Vout (V) Current probe 20 10 0 VIN fOSC = 100 kHz TL IO + 1 µF OUT CL (+) 27 kΩ 470 pF CL 1000 pF IO (mA) 500 0 −500 R T1 CT ST CST + 1 µF RT2 Vref 27 kΩ 200 ns/div * Current probe: Tektronix AM503 Vout Output Falling Waveform 40 30 Vout (V) I O (mA) 20 10 0 500 0 −500 200 ns/div Rev.4.00 Jun 15, 2005 page 27 of 39 HA16107P/FP, HA16108P/FP HA16107 Test circuit VIN VIN = 18V RT1 = RT2 = 27 kΩ CT = 470 pF fOSC = 100 kHz Operating waveform at the TL pin When overcurrent is input at the point where the duty cycle is 0%. 7 6 5 4 B TL CL 1000 pF Clock 27 kΩ + 1 µF SW OUT CL(+) RT1 CT ST 470 pF VTL (V) 3 2 1 0 CL(+) when input at a duty of 0% tON tOFF 0.5 sec/div A RT2 Vref 27 kΩ CST + 1 µF Triangle wave Output pulse shutdown region SW ON SW OFF CL(+) when input at a duty of 30% t1 t2 When overcurrent is input at the point where the duty cycle is 30%. 7 6 a b Du = t1 × 100 (%) t2 Enlargement of section c A 5 4 B VTL CTL discharged at 4 µA CTL discharged at 12 µA t VTL (V) 3 2 A Enlargement of section B 1 0 VTL CTL discharged at 4 µA tON tOFF 0.5 sec/div a b t to b : PWM pulse output is High : The point where overcurrent is detected Output pulse shutdown region SW ON SW OFF b to c : PWM pulse output is Low. Rev.4.00 Jun 15, 2005 page 28 of 39 HA16107P/FP, HA16108P/FP HA16108 Test circuit VIN Operating waveform at the ON/OFF pin When overcurrent is input at the point where the duty cycle is 0%. 7 6 B CL 1000 pF Clock 27 k½ V IN = 18V R T1 = R T2 = 27 k½ C T = 470 pF f OSC = 100kHz ON/OFF OUT CL(+) R T1 CT R T2 ST C ST + 1 µF + 1 µF 5 470 pF V ON/OFF (V) 4 3 2 A 27 k½ 1 0 Triangle wave CL(+) when input at a 0.5 sec/div duty of 0% t ON t OFF t ON t OFF t ON t OFF CL(+) when input at a duty of 30% t1 Output pulse shutdown region SW ON SW OFF t2 When overcurrent is input at the point where the duty cycle is 30%. 7 B Du = t1 × 100 (%) t2 Enlargement of section A 6 5 a V TL b c V ON/OFF (V) 4 3 2 1 0 A CTL discharged at 4 µA CTL discharged at 12 µA t Enlargement of section B V TL CTL discharged at 4 µA 0.5 sec/div t ON t OFF t ON t OFF t a to b : PWM pulse output is High. b : The point where overcurrent is detected. SW ON SW OFF Output pulse shutdown region b to c : PWM pulse output is Low. Rev.4.00 Jun 15, 2005 page 29 of 39 HA16107P/FP, HA16108P/FP Error Amplifier Characteristic 60 Open Loop Gain AVO (dB) 40 0 45 90 135 φ 20 AVO 0 10 k 30 k 100 k 300 k 1M 3M 10 M 180 30 M 100 M Input signal frequency fIN (Hz) Examples of Drooping Characteristics of Power Supplies Using these Ics 5.0 ON VOUT (DC) (V) Normal operation Latch state here 2.5 OFF 0 1 2 IOUT (DC) (A) 3 A B Pulse by pulse Current limiter operation A B Heavy load Light load 4 HA16107 (Latch shut-down) 5.0 ON VOUT (DC) (V) OFF 2.5 A B Pulse by pulse Current limiter operation A B Heavy load Light load 0 1 2 IOUT (DC) (A) 3 4 HA16108 (Intermittent operation by means of ON/OFF timer) Rev.4.00 Jun 15, 2005 page 30 of 39 Phase Change φ (deg) HA16107P/FP, HA16108P/FP Operating Circuit Example • Flyback Transforrmer Application Example (IC Vref used as system as reference voltage) Schottky barrier diode Bridge Diode Start-up Resistor 140 V El-30 Trans former HRP 24 + 5V OUTPUT − 1.5 Ω 3W Current Sense FILTER 50 V 22 µF AC INPUT + HZP 16 TL OVP Detector Timerlatch Capacitor + 16 V 1 µF 330 kΩ 23T HRP 32 18.9 V 82 kΩ 1W 51 Ω HZP 16 2SK1567 40T 6T + − 470 µF RFI VIN QCLM −++ 16 OUT 110 Ω CL(+) 1 VC VE OUT 2 3 16 µA 4 µA E/O − Triangle wave PWM Comparator UVL1&UVL2 P{ulse by pulse latch 140 µA 15 UVL1 H L ON/OFF Latch (V TH= 7V) RQ S VL VH IN(−) QR QS Error amp. 14 Current Sense L.P.F. 51 Ω VE 4700 pF 510 kΩ NC Phase Comp. Zener type reference voltage generation circuit 6.45 V 68 kΩ 13 4 CL(−) 27 kΩ Vref Current limiter UVL1 ST VIN O V P UVL2 H L 12 5 6 CT 4V 5V GND 34 V Vref IN(+) 3.225 V ST − +16 V 33kΩ 33kΩ 11 RT1 470 pF UVL2 10 Soft Start Cap. 7 3.4 V 10 µA fosc = 100 kHz, Dumax = 50% 1 µF Frequency, Max, Duty Setting 27 kΩ RT2 HA16107P/FP Rev.4.00 Jun 15, 2005 page 31 of 39 8 9 Vref +− 1 µF 16 V 6.45 V Bridge diode + 200 V − 100 µF DFG1C8 HRW26F 47 µH Power thermister HA16107P/FP, HA16108P/FP AC INPUT Rev.4.00 Jun 15, 2005 page 32 of 39 HA17431P RB 1 W 82 kΩ (Start-up resistor) 10 kΩ + 0.47 µF − 0.5 φ 8T * 0.3 φ 50 T + 50 V – 22 µF 0.3 φ 50 T 0.5 φ 8T * + • Forward Transformer Application Example DC OUT (5 V) 4.7 kΩ B Secondary error amplifier − 330 Ω + 16 V 3.3 kΩ − 1000 µF 1.8 kΩ + − 3.3 µF Timer latch 1 µF − capacitor + 16 15 14 13 12 11 10 9 TL E/O IN NC IN ST Vref (−) (+) HZP16 13 kΩ 2SK1567 HA16107P/108P CL VOUT (+) 1234 5 51 Ω 110 Ω 3W 1.5 Ω (Current sense) 13 kΩ 470 pF RT1 CT CT2 678 (Soft start 1 µF capacitor) − + TLP521 * Bifiler transfomer core size EI-30 equivalent product 4700 pF (Current sense filter) 51 Ω HA16107P/FP, HA16108P/FP • When OVP signal is inserted at CL(+) pin VIN RB OVP detector VIN OUT CL(+) TL + 1 µF When the OVP detection Zener diode turns on, latch shutdown of the output is performed after the elapse of the time determined by the capacitance connected the TL pin. Rev.4.00 Jun 15, 2005 page 33 of 39 HA16107P/FP, HA16108P/FP Application 1. Use of Error Amplifier for Flyback Transformer Primary-Side Control In this example, the fact that the transformers winding ratio and voltage ratio in Figure 4 are mutually proportional is made use of in a flyback transformer type AC-DC converter. As fluctuation of output voltage V2 also appears in IC power supply voltage V3, this is divided by a resistance and amplified by an error amplifier. An advantage of this method is that a photocoupler need not be used, making it possible to configure a power supply with a small number of parts (this example cannot be applied to a forward transformer). Commercial AC input •V1(input voltage) Output Start-up resistance To switch element N1 N2 N3 R1 14 R2 11 R4 − + R3 15 Error amp. E/O C1 Flyback transformer R2 × V3 = R 1 + R2 Where V3 = 1 Vref 2 V2(output voltage) V3(IC power supply voltage) 2.5V N3 × V2, N2 Figure 4 Error Amplifier Peripheral Circuitry Diagram 1. Detrrrmining DC Characteristics In Figure 4, the relational expression in the box is satisfied, and therefore parameters are determined based on this. The absolute value of the number of transformer windings is determined based on the equation N1:N2:N3 = V1:V2:V3, taking primary inductance into consideration. Next, IC operating voltage V3 is made around 11V to 18V, taking the UVL voltage into consideration. If V3 is too large, the power consumption of the IC will increase, causing heat emission problems. If V3 is too small, on the other hand, there will be problems with defective power supply start-up. 2. Determining Error Amplifier Gain vs. Frequency Characteristic Taking the configuration in Figure 4, the error amplifier gain characteristic with respect to fluctuation of output voltage V2 is as shown in Figure 5. G1 Gain G (dB) G2 R6 ≠ 0 R6 = 0 fOSC Frequency f (Hz) f1 fAC f2 Figure 5 Error Amplifier Characteristic Rev.4.00 Jun 15, 2005 page 34 of 39 HA16107P/FP, HA16108P/FP In Figure 5, the parameters are given by the following equations. Gain G1 = V3/V2 × R3/R1 G2 = V3/V2 × R4/R1 Corner frequencies f1 = 1/(2π C1 R3) f2 = 1/(2π C1 R4) Where R3>>R4 (10:1 or above) G1 is made around 30 to 50 dB, taking both regulation and stability into consideration. f1 is made a lower value than commercial frequency ripple fAC, thus preventing hunting (a system instability phenomenon). Next, G2 is set to 0 dB or less as a guideline, so that there is no gain in IC operating frequency fOSC (several tens to several hundreds of kHz). f2 should be set to a value that is substantially smaller than fOSC, and that is appropriate for the power supply response speed (several kHz). In the case of a bridge type rectification circuit, the commercial frequency ripple is twice the input frequency (with a 50 Hz commercial frequency, fAC = 100 Hz). 2. External Constant Design for Current Detection Section (HA16107, HA16108, HA16666) In the above IC models, which incorporate a current detection function, a low-pass filter such as shown in Figure 6 must be inserted between switch element current detection resistance RCS and the current detection pin of the IC. Input voltage VB 140V Floating capacitance CX Output From PWM output pin of IC To current detection pin of IC V12 CA RB Switch element power MOS FET ID RA V11 Current detection resistance RCS Several hundred mΩ to several Ω Filter (LPF) Figure 6 Current Detection Circuit Rev.4.00 Jun 15, 2005 page 35 of 39 HA16107P/FP, HA16108P/FP The reason for this is that, when the switch element is on in each cycle, there is an impulse current associated with charging of transformer floating capacitance CX, and IC current detection malfunctions (see Figure 7). VTH V11 V12 Figure 7 Current Detection Waveform If the switch element current to be detected is designated ID, and the current detection resistance RCS, then the following equation is satisfied using the parameters in Figure 6. ID × RCS = ((RA + RB)/RB) VTH VTH is the detection level voltage of the IC (240 mV in the case of the HA16107, for example). RA and RB are set to values on the order of several hundred Ω to several kΩ, so that RCS is not affected. Next, the filter cutoff frequency is set according to the following equation. fC = 1/(2π CA (RA/RB)) fC can be found with the following guideline, using IC operating frequency fOSC, power supply rating on-duty D, and power MOS element turn-on time tON. fosc/D ≤ fC ≤ 1/(100 × tON) Value 100 in the above equation provides a margin for noise, ringing, and so forth. In an SW power supply using an HA16107, with a 100 kHz operating frequency and a D value of 30%, the relevant values were as follows: VB = 140 V, CX = 80 pF, tON = 10 ns. Thus, when RCS = 1 Ω, the V11 level peak value reaches the following figure. V11 (peak) = RCS × ID peak = RCS × (VB × CX)/tON = 1Ω × (140 V × 80 pF)/10 ns = 1.12 (V) A filter with the following constants was then inserted. RA = RB = 1 kΩ, CA = 1000 pF At this time, the detectable drain current is 0.48 (A), and the filter cutoff frequency is 318 (kHz). Note that increasing a filter time constant is effective against noise, but if the value is too large, error will arise in the switch element current detection level. Rev.4.00 Jun 15, 2005 page 36 of 39 HA16107P/FP, HA16108P/FP 3. IC Heat Emission Problem and Countermeasures (HA16107 Series, HA16114 Series) While the above ICs can directly drive a power MOS FET gate, if the method of use is not thoroughly investigated, there will be a tendency for the gate drive power to increase and a problem of heat emission by the IC may occur. This section should therefore be noted and appropriate measures taken to prevent this kind of problem. 1. Power MOS FET Drive Characteristics When power MOS FET drive is performed, in order to lower the on-resistance sufficiently, overdrive is normally performed with a voltage considerably higher than 5 V, for example, such as the 15 V power supply voltage of the IC. At this time, the power that should be supplied from the IC to the power MOS FET is determined by gate load Qg in Figure 9. 2. IC Heat-Emission Power Calculation (Figure 9) The power that contributes to IC heat emission is calculated by means of the following equation. Pd = VIN IQ + 2Qg VIN f Where VIN : Power supply voltage of IC IQ : Operating current of IC (unloaded) Qg : Above-mentioned gate load f : Operating frequency of IC The coefficient, 2, indicates that gate discharging also contributes to heat emission. 4. Power MOS FET Gate Resistance Design (HA16107 Series, HA16114 Series) There are the following three purposes in connecting a gate resistance, and the circuit is generally of the kind shown in Figure 8. (1) To suppress peak current due to gate charging (2) To protect IC output pins (3) To provide drive appropriate to power MOS FET input characteristics DG To transformer OUT IC output pin RG1 RG2 Power MOS FET CS RCS Figure 8 Gate Drive Circuit Rev.4.00 Jun 15, 2005 page 37 of 39 HA16107P/FP, HA16108P/FP This gate resistance RG is given by the following equation. RG = (VG/IG) – (VG × tON)/Qg, RG = RG1 + RG2 IG : Gate input peak current VG : Gate drive voltage wave high value (equal to power supply voltage of IC) tON : Power MOS FET turn-on time tOFF : Power MOS FET turn-off time Qg : Gate charge according to Figure 9 VDS (V) VDS VGS VGS (V) Qg (nc) Figure 9 Power MOS FET Dynamic Input Characteristics Refer to the power MOS FET catalog for information on tON and Qg. By dividing RG into RG1 and RG2, it is possible for speed to be slowed when the power MOS FET is on, and increased when off. Power MOS FET on and off times when mounted, tON’ and tOFF’, are as follows. tON’ = tON + Qg(RG1 + RG2)/VG tOFF’ = tOFF + Qg ⋅ RG2/VG When driving a power MOS FET and 2SK1567 with an HA16107, etc. (RG1 = 100 Ω, RG2 = 20 Ω, VG = 15 V) tON’ = 70 ns + 36 nc ⋅ (100 Ω + 20 Ω)/(15 V) = 360 (ns) tOFF’ = 135 ns + 36 nc ⋅ (20 Ω)/(15 V) = 183 (ns) Generally, the gate resistance values in the case of this circuit configuration are on the order of 100 to 470 Ω for RG1 and 10 to 47 Ω for RG2. Rev.4.00 Jun 15, 2005 page 38 of 39 HA16107P/FP, HA16108P/FP Package Dimensions 19.20 20.00 Max 16 9 As of January, 2003 Unit: mm 1 1.3 1.11 Max 8 7.40 Max 6.30 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 − 0.05 0 ° − 15 ° Package Code JEDEC JEITA Mass (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-A Previous Code FP-16DA MASS[Typ.] 0.24g *1 D F 9 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 E HE c1 Index mark Reference Symbol *2 c Dimension in Millimeters Min Nom 10.06 5.5 Max 10.5 Terminal cross section 1 Z e *3 D E 8 bp x M L1 A2 A1 A b b c p 1 0.00 0.10 0.20 2.20 0.34 0.42 0.40 0.50 0.17 1 0.22 0.20 0.27 A c θ HE 0° 7.50 7.80 1.27 8° 8.00 θ A1 y L e x y 0.12 0.15 0.80 0.50 1 Detail F Z L L 0.70 1.15 0.90 Rev.4.00 Jun 15, 2005 page 39 of 39 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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