HA16121FP

HA16116FP/FPJ, HA16121FP/FPJ Switching Regulator for Chopper Type DC/DC Converter REJ03F0056-0200Z (Previous: ADE-204-019A) Rev.2.0 Sep.18.2003 Description HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in chopper-type DC/DC converters. This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The output logic is preset for booster, step-down, or inverting control in a DC/DC converter. This logic assumes use of an N-channel power MOS FET for booster control, and a P-channel power MOS FET for step-down or inverting control. HA16116 includes a built-in logic circuit for step-down control only, and one for use in both step-down and inverting control. HA16121 has a logic circuit for booster control only and one for both step-down and inverting control. Both ICs have a pulse-by-pulse current limiter, which limits PWM pulse width per pulse as a means of protecting against overcurrent, and which uses an on/off timer for intermittent operation. Unlike conventional methods that use a latch timer for shutdown, when the pulse-by-pulse current limiter continues operation beyond the time set in the timer, the IC is made to operate intermittently (flickering operation), resulting in sharp vertical setting characteristics. When the overcurrent condition subsides, the output is automatically restored to normal. The dual control circuits in the IC output identical triangle waveforms, for completely synchronous configuring a compact, high efficiency dual-channel DC/DC converter, with fewer external components than were necessary previously. Functions • 2.5 V reference voltage (Vref) regulator • Triangle wave form oscillator • Dual overcurrent detector • Dual totem pole output driver • UVL (under voltage lock out) system • Dual error amplifier • Vref overvoltage detector • Dual PWM comparator Rev.2.0, Sep.18.2003, page 1 of 33 HA16116FP/FPJ, HA16121FP/FPJ Features • Wide operating supply voltage range* (3.9 V to 40.0 V) • Wide operating frequency range (600 kHz maximum operation) • Direct power MOS FET driving (output current ±1 A peak in maximum rating) • Pulse-by-pulse overcurrent protection circuit with intermittent operation function (When overcurrent state continues beyond time set in timer, the IC operates intermittently to prevent excessive output current.) • Grounding the ON/OFF pin turns the IC off, saving power dissipation. (HA16116: IOFF = 10 µA max.; HA16121: IOFF = 150 µA max.) • Built-in UVL circuit (UVL voltage can be varied with external resistance.) • Built-in soft start and quick shutoff functions Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V. Ordering Information Hitachi Control ICs for Chopper-Type DC/DC Converters Product Channels Dual Number HA17451 Channel No. Ch 1 Ch 2 Single HA16114 HA16120 Dual HA16116 — — Ch 1 Ch 2 HA16121 Ch 1 Ch 2 Control Functions Step-Up ❍ ❍ — ❍ — — — ❍ Step-Down ❍ ❍ ❍ — ❍ ❍ ❍ — Inverting ❍ ❍ ❍ — ❍ — ❍ — Totem pole power MOS FET driver Pulse-by-pulse current limiter and intermittent operation by on/off timer Output Circuits Open collector Overcurrent Protection SCP with timer (latch) Rev.2.0, Sep.18.2003, page 2 of 33 HA16116FP/FPJ, HA16121FP/FPJ Pin Arrangement S.GND*1 CT RT IN(+)1 IN(−)1 E/O1 Channel 1 DB1 CL1 OUT1 P.GND *1 S.VIN*2 Vref TIM ON/OFF IN(−)2 E/O2 DB2 CL2 OUT2 P.VIN*2 Channel 2 1 2 3 4 5 6 7 8 9 10 (Top view) 20 19 18 17 16 15 14 13 12 11 Notes: 1. Pins S.GND (pin 1) and P.GND (pin 10) have no direct internal interconnection. Both pins must be connected to ground. 2. Pins S.VIN (pin 20) and P.V IN (pin 11) have no direct internal interconnection. Both pins must be connected to VIN. Rev.2.0, Sep.18.2003, page 3 of 33 HA16116FP/FPJ, HA16121FP/FPJ Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol S.GND CT RT IN(+)1 IN(–)1 E/O1 DB1 CL1 OUT1 P.GND P.VIN OUT2 CL2 DB2 E/O2 IN(–)2 ON/OFF TIM Vref S.VIN Function Signal circuitry* ground Timing capacitance (triangle wave oscillator output) Timing resistance (for bias current synchronization) Error amp. noninverting input (1) Error amp. inverting input (1) Error amp. output (1) Dead band timer off period adjustment input (1) Overcurrent detection input (1) PWM pulse output (1) Output stage* ground Output stage* power supply input PWM pulse output (2) Overcurrent detection input (2) Dead band timer off period adjustment input (2) Error amp. output (2) Error amp. inverting input (2)* 2 1 1 1 Channel 1 Channel 2 IC on/off switch input (off when grounded) Setting of intermittent operation timing when overcurrent is detected (collector input of timer transistor) 2.5 V reference voltage output Signal circuitry* power supply input 1 Notes: 1. Here “output stage” refers to the power MOS FET driver circuits, and “signal circuitry” refers to all other circuits on the IC. Note that this IC is not protected against reverse insertion, which can cause breakdown of the IC between VIN and GND. Be careful to insert the IC correctly. 2. Noninverting input of the channel 2 error amp is connected internally to Vref. Rev.2.0, Sep.18.2003, page 4 of 33 [Channel 2] Step-down control only (HA16116) Booster control only (HA16121) Vref 19 from UVL to S.VIN −+ CL2 5k Vref UVL H L V L VH from UVL OR OVP UVL output 0.8V + + − PWM COMP 2 OUT2* NAND (HA16116) 0.2 V VIN − EA2 + 18 17 16 15 14 13 12 11 TIM ON/OFF IN(−)2 E/O2 DB2 CL2 OUT2 P.VIN S.VIN 20 Block Diagram Rev.2.0, Sep.18.2003, page 5 of 33 VIN Latch S R 0.8V Q − + + Triangle wave oscillator circuit 1.6 V HA16116FP/FPJ, HA16121FP/FPJ ON/OFF 2.5 V output band gap reference voltage generator circuit VIN from UVL NAND OUT1 0.8V 5k 1.0 V triangle wave latch reset pulse Bias current 1.1 V RT + EA1 − PWM COMP 1 Vref 5k from UVL CL1 −+ 0.2 V to S.VIN from UVL 1 CT ) in the case of RT IN(+)1 2 3 4 5 IN(−)1 6 E/O1 7 DB1 [Channel 1] (HA16116/HA16121) Step-down or inverting control 8 CL1 9 OUT1 10 P.GND S.GND Note: * This block is AND ( HA16121. HA16116FP/FPJ, HA16121FP/FPJ Function and Timing Chart Relation between triangle wave and PWM output (in steady-state operation) CT triangle wave Dead band voltage 1.0 V typ E/O Error amp output 1.6 V typ Booster channel output (HA16121Ch 2) only PWM pulse output VIN (on) tON tOFF T GND (off) This pulse is for N-channel power MOS FET gate driving. Step-down or inverting output (HA16116Ch 1, Ch 2/ HA16121-Ch 1) VIN (off) GND (on) This pulse is for P-channel power MOS FET gate driving. Note: On duty = tON/T, where T = 1/fOSC. Rev.2.0, Sep.18.2003, page 6 of 33 HA16116FP/FPJ, HA16121FP/FPJ Determining External Component Constants (pin usage) Constant settings are explained for the following items. S.GND 1 Oscillator frequency (fOSC) setting CT 2 RT 3 IN(+)1 4 2. DC/DC converter output voltage setting and error amp usage Dead band duty and soft start setting Output stage circuit and power MOS FET driving method IN(−)1 5 E/O1 6 3. DB1 7 CL1 8 4. OUT1 9 P.GND 10 Channel 1 Channel 2 20 S.VIN 19 Vref 18 TIM 17 ON/OFF 16 IN(−)2 15 E/O2 14 DB2 13 CL2 12 OUT2 11 P.VIN 5. Vref UVL and OVP 1. 6. Setting of intermittent operation timing when overcurrent is detected ON/OFF pin usage 7. 8. Overcurrent detection value setting 1. Oscillator Frequency (fOSC) Setting Figure 1.1 shows an equivalent circuit for the triangle wave oscillator. VH 1.6 V typ (3.3 V IC internal circuits) Vref (2.5 V) t1 t2 VL 1.0 V typ CT charging IO Comparator RA RC IO Discharging 1.1 V RT (external) Inside the IC 1:2 RT CT (external) CT RB Figure 1.1 Equivalent Circuit for the Triangle Wave Oscillator Rev.2.0, Sep.18.2003, page 7 of 33 HA16116FP/FPJ, HA16121FP/FPJ The triangle wave is a voltage waveform used as a reference in creating a PWM pulse. This block operates according to the following principles. A constant current IO, determined by an external timing resistor RT, is made to flow continuously to external timing capacitor CT. When the CT pin voltage exceeds the comparator threshold voltage VH, the comparator output causes a switch to operate, discharging a current IO from CT. Next, when the CT pin voltage drops below threshold voltage VL, the comparator output again causes the switch to operate, stopping the IO discharge. The triangle wave is generated by this repeated operation. Note that IO = 1.1 V/RT. Since the IO current mirror circuit has a very limited current producing ability, RT should be set to ≥ 5 kΩ (IO ≥ 220 µA). With this IC series, VH and VL of the triangle wave are fixed internally at about 1.6 V and 1.0 V by the internal resistors RA, RB, and RC. The oscillator frequency can be calculated as follows. fOSC = Here, t1 = t2 = C R ⋅ (VH − VL) CT ⋅ (VH − VL) = TT 1.1 V/RT 1.1 V C R ⋅ (VH − VL) CT ⋅ (VH − VL) = TT = t1 (2 − 1) × 1.1 V/RT 1.1 V 1 t1 + t2 + t3 VH − VL = 0.6 V t1 = t2 = 0.6 CR 1.1 T T t3 ≈ 0.8 µs (comparator delay time in the oscillator) Accordingly, fOSC ≈ 1 1 [Hz] ≈ 2t1 + t3 1.1 CT RT + 0.8 µs Note that the value of fOSC may differ slightly from the above calculation depending on the amount of delay in the comparator circuit. Also, at high frequencies this comparator delay can cause triangle wave overshoot or undershoot, skewing the dead band threshold. Confirm the actual value in implementation and adjust the constants accordingly. Rev.2.0, Sep.18.2003, page 8 of 33 HA16116FP/FPJ, HA16121FP/FPJ 2. DC/DC Converter Output Voltage Setting and Error Amp Usage 2.1 Positive Voltage Booster (VO > VIN) or Step-Down (VIN > VO > Vref) Use VO = R1 + R2 ⋅ Vref (V) R2 Booster output is possible only at channel 2 of HA16121. HA16116 or channel 1 of HA16121 are used. VO R1 R2 VO R1 R2 For step-down output, both channels of Error amp. IN(−)1 − CH1 IN(+)1 + IN(−)2 − + Vref 2.5 V (internal connection) CH2 Vref pin Figure 2.1 2.2 Negative Voltage (VO < Vref) for Inverting Output Use VO = −Vref ⋅ R3 + R 4 R1 ⋅ −1 R3 R1 + R 2 (V) Channel 1 is used for inverting output on both ICs. Vref pin R1 R3 IN(+)2 R4 VO Vref 2.5 V IN(−)1 R2 − + Error amp CH1 Figure 2.2 Inverting Output Rev.2.0, Sep.18.2003, page 9 of 33 HA16116FP/FPJ, HA16121FP/FPJ 2.3 Error Amplifier Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier on these ICs is configured of a simple NPN transistor differential input amplifier and the output circuit of a constant-current driver. This amplifier features wide bandwidth (fT = 4 MHz) with open loop gain kept to 50 dB, allowing stable feedback to be applied when the power supply is designed. Phase compensation is also easy. Both HA16116 and HA16121 have a noninverting input (IN(+)) pin, in order to allow use of the channel 1 error amplifier for inverting control. The channel 2 error amplifier, on the other hand, is used for stepdown control in HA16116 and booster control in HA16121; so the channel 2 noninverting input is connected internally to Vref. IC internal VIN IN(−) IN(+) 80 µA 40 µA E/O To internal PWM comparator Figure 2.3 Error Amplifier Equivalent Circuit 3. Dead Band (DB) Duty and Soft Start Setting (common to both channels) 3.1 Dead Band Duty Setting Dead band duty is set by adjusting the DB pin input voltage (VDB). A convenient means of doing this is to connect two external resistors to the Vref of this IC so as to divide VDB (see figure 3.1). VDB = Vref × Duty (DB) = Here, T = R2 (V) R1 + R2 VTH − VDB × 100 (%) ⋅ ⋅ ⋅ ⋅ This applies when VDB > VTL. VTH − VTL If VDB < VTL, there is no PWM output. 1 fOSC Note: VTH: 1.6 V (Typ) VTL: 1.0 V (Typ) Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V. Rev.2.0, Sep.18.2003, page 10 of 33 HA16116FP/FPJ, HA16121FP/FPJ To Vref CT VDB R1 DB E/O 5k From UVL 0.8V VTH VE/O VDB − + + PWM comparator VIN VTL Booster channel 1.6 V typ 1.0 V typ On tON VIN Off GND VIN GND tOFF CST R 2 PWM pulse output Step-down/ inverting channel Off On T Figure 3.1 Dead Band Duty Setting 3.2 Soft Start (SST) Setting (each channel) When the power is turned on, the soft start function gradually raises VDB (refer to section 3.1), and the PWM output pulse width gradually widens. This function is realized by adding a capacitor CST to the DB pin. The function is realized as follows. In the figure 3.2, the DB pin is clamped internally at approximately 0.8 V, which is 0.2 V lower than the triangle wave VTL = 1.0 V typ. tA: Standby time until PWM pulse starts widening. tB: Time during which SST is in effect. During soft start, the DB pin voltage in the figure below is as expressed in the following equation. VSST = VDB ⋅ 1 − e Here, t0.8 = −T ln 1− 0.8 VDB , T = CST ⋅ (R1 // R2) −t − t0.8 T , tSST = tA + tB How to select values: If the soft start time tSST is too short, the DC/DC converter output voltage will tend to overshoot. To prevent this, set tSST to a few tens of ms or above. Rev.2.0, Sep.18.2003, page 11 of 33 HA16116FP/FPJ, HA16121FP/FPJ V (voltage) Triangle wave VTH VSST 1.6 V VTL Starts from clamp voltage of 0.8 V 1.0 V PWM output pulse starts to widen t0.8 tA tB Steady-state operation 0V Booster channel PWM pulse output Step-down/ inverting channel VIN 0V VIN 0V VO DC/DC converter output (positive in this example) 0V t = 0 (here IC is on) t = tSST Figure 3.2 Soft Start (SST) Setting Rev.2.0, Sep.18.2003, page 12 of 33 HA16116FP/FPJ, HA16121FP/FPJ 4. Totem Pole Output Stage Circuit and Power MOS FET Driving Method The output stage of this IC series is configured of totem pole circuits, allowing direct connection to a power MOS FET as an external switching device, so long as VIN is below the gate breakdown voltage. If there is a possibility that VIN will exceed the gate breakdown voltage of the power MOS FET, a Zener diode circuit like that shown figure 4.1 or other protective measures should be used. The figure 4.1 shows an example using a P-channel power MOS FET. P.VIN E.g.: VIN = 18 V Zener diode for gate protection Bias circuit OUT Gate protection resistor Schottky barrier diode VO + − Drive circuit Figure 4.1 P-channel Power MOS FET (example) 5. Vref Undervoltage Error Prevention (UVL) and Overvoltage Protection (OVP) Functions 5.1 Operation Principles The reference voltage circuit is equipped with UVL and OVP functions. • UVL In normal operation the Vref output voltage is fixed at 2.5 V. If VIN is lower than normal, the UVL circuit detects the Vref output voltage with a hysteresis of 1.7 V and 2.0 V, and shuts off the PWM output if Vref falls below this level, in order to prevent malfunction. • OVP The OVP circuit protects the IC from inadvertent application of a high voltage from outside, such as if VIN is shorted. A Zener diode (5.6 V) and resistor are used between Vref and GND for overvoltage detection. PWM output is shut off if Vref exceeds approximately 7.0 V. Note that the PWM output pulse logic and the precision of the switching regulator output voltage are not guaranteed at an applied voltage of 2.5 V to 7 V. Rev.2.0, Sep.18.2003, page 13 of 33 HA16116FP/FPJ, HA16121FP/FPJ 5.2 Quick Shutoff When the UVL circuit goes into operation, a sink transistor is switched on as in the figure below, drawing off the excess current. This transistor also functions when the IC is turned off, drawing off current from the CT, E/O, and DB pins and enabling quick shutoff. PWM output On PWM output off PWM output on PWM output off Off 1.7 2.0 2.5 5.0 7.0 Vref (V) When VIN is low Abnormal voltage applied to Vref Relation of Vref to UVL and OVP VIN Vref Vref generation circuit 2.0 V and 1.7 V detection ZD 5.6 V R Internal pulse signal line Vref UVL OUT Sink transistor OUT OVP 10 kΩ To other circuitry Figure 5.1 Quick Shutoff Rev.2.0, Sep.18.2003, page 14 of 33 HA16116FP/FPJ, HA16121FP/FPJ 6. Setting of Intermittent Operation Timing when Overcurrent is Detected 6.1 Operation Principles The current limiter on this IC detects overcurrent in each output pulse, providing pulse-by-pulse overcurrent protection by limiting pulse output whenever an overcurrent is detected. If the overcurrent state continues, the TIM pin and ON/OFF pin can be used to operate the IC intermittently. As a result, a power supply with sharp vertical characteristics can be configured. The ON/OFF timing for intermittent operation makes use of the hysteresis in the ON/OFF pin threshold voltage VON and VOFF, such that VON – VOFF = VBE. Setting method is performed as described on the following pages. VBE is based-emitter voltage of internal transistor. Note: When an overcurrent is detected in one channel of this IC but not the other, the pulse-by-pulse current limiter still goes into operation on both channels. Also, when the intermittent operation feature is not used, the TIM pin should be set to open state and the ON/OFF pin pulled up to high level (above VON). VIN 390 kΩ 4.7 kΩ 2.2 µF + − RA TM ON/OFF Vref generation circuit Current limiter CL Latch S Q R RB CON/OFF Figure 6.1 Connection Diagram (example) 6.2 Intermittent Operation Timing Chart (VON/OFF only) *1 4VBE c VON/OFF 3VBE 2VBE VBE 0V c On On Off IC is on IC is off a b TON t TOFF 2TON a. Continuous overcurrent detected b. Intermittent operation starts (IC is off) c. Overcurrent cleared (dotted line) Note: 1.V BE is the base-emitter voltage in transistors on the IC, and is approximately 0.7 V (see the figure 7.1). For details, see the overall waveform timing diagram. Figure 6.2 Intermittent Operation Timing Chart Rev.2.0, Sep.18.2003, page 15 of 33 HA16116FP/FPJ, HA16121FP/FPJ 6.3 Calculating Intermittent Operation Timing Intermittent operation timing is calculated as follows. (1) TON time (the time until the IC is shut off when continuous overcurrent occurs) TON = CON/OFF × RB × ln 3VBE 2VBE × 1 1 − On duty* VIN − 2VBE VIN − 3VBE 1 1 − On duty* ≈ 0.4 × CON/OFF × RB × 1 1 − On duty* = CON/OFF × RB × ln1.5 × (2) TOFF time (when the IC is off, the time until it next goes on) TOFF = CON/OFF × (RA + RB) × ln Where, VBE ≈ 0.7 V Note: 1. On duty is the percent of time the IC is on during one PWM cycle when the pulse-by-pulse current limiter is operating. From the first equation (1) above, it is seen that the shorter the time TON when the pulse-by-pulse current limiter goes into effect (resulting in a larger overload), the smaller the value TON becomes. As seen in the second equation (2), TOFF is a function of VIN. Further, according to this setting, when VIN is switched on, the IC goes on only after TOFF has elapsed. Dead band voltage Point at which current limiter operate Triangle wave PWM output (step-down channel) tON On duty = T tON T Where T = 1/fOSC Note: On duty is the percent of time the IC is on during one PWM cycle when the pulse-by-pulse current limiter is operating. Figure 6.3 Rev.2.0, Sep.18.2003, page 16 of 33 HA16116FP/FPJ, HA16121FP/FPJ 6.4 Examples of Intermittent Operation Timing (calculated values) (1) TON TON = T1 × CON/OFF × RB Here, coefficient T1 = 0.4 × 1 1 − On duty T1 1 Example: If CON/OFF = 2.2 µF, RB = 4.7 kΩ, and the on duty of the current limiter is 75%, then TON = 16 ms. 3 4 2 from section 6.3 (1) previously. 0 0 20 40 60 80 100 (PWM) ON Duty (%) Figure 6.4 Examples of Intermittent Operation Timing (1) (2) TOFF TOFF = T2 × CON/OFF × (RA + RB) Here, coefficient T2 = ln VIN − 2VBE VIN − 3VBE T2 0.05 0.1 from section 6.3 (2) previously. Example: If CON/OFF = 2.2 µF, RB = 4.7 kΩ, RA = 390 kΩ, VIN = 12 V, 0 then TOFF = 60 ms. 0 10 20 VIN (V) 30 40 Figure 6.5 Examples of Intermittent Operation Timing (2) Rev.2.0, Sep.18.2003, page 17 of 33 HA16116FP/FPJ, HA16121FP/FPJ Triangle wave VCT Dead band VDB Error output VE/O PWM pulse output (In case of HA16120) Power MOS FET drain current (ID) (dotted line shows inductor current) VIN Current limiter pin (CL) VIN − 0.2 V IC Example of step-up circuit VIN CF RF CL OUT RCS Inductor L ID VOUT F.B. Determined by L and VIN VTH (CL) Determined by RCS and RF Figure 6.6 7. ON/OFF Pin Usage 7.1 IC Shutoff by the ON/OFF Pin As shown in the figure 7.1, these ICs can be turned off safely by lowering the voltage at the ON/OFF pin to below 2VBE. This feature is used to conserve the power in the power supply system. In off state the IC current consumption (IOFF) is 10 µA (Max) for HA16116 and 150 µA (Max) for HA16121. The ON/OFF pin can also be used to drive logic ICs such as TTL or CMOS with a sink current of 50 µA (Typ) at an applied voltage of 5 V. When it is desired to employ this feature along with intermittent operation, an open collector or open drain logic IC should be used. VIN IIN RA External logic IC Off On RB P.VIN S.VIN To output stage To latch 50 kΩ 4 VBE Q1 Q2 Q3 To other circuitry TIM Switch + − ON/OFF Vref generation circuit Q4 Vref output CON/OFF GND HA16116, HA16121 On/off hysteresis circuit Figure 7.1 IC Shutoff by the ON/OFF Pin Rev.2.0, Sep.18.2003, page 18 of 33 HA16116FP/FPJ, HA16121FP/FPJ 7.2 Adjusting UVL Voltage (when intermittent operation is not used) The UVL voltage setting in this IC series can be adjusted externally as shown below. Using the relationships shown in the figure, the UVL voltage in relation to VIN can be adjusted by changing the relative values of VTH and VTL. When the IC is operating, transistor Q4 is off, so VON = 3VBE ≈ 2.1 V. Accordingly, by connecting resistors RC and RD, the voltage at which UVL is cancelled is as follows. VIN = 2.1 V × RC + RD RD This VIN is simply the supply voltage at which the UVL stops functioning, so in this state Vref is still below 2.5 V. In order to restore Vref to 2.5 V, a VIN of approximately 4.3 V should be applied. With this IC series, VON/OFF makes use of the VBE of internal transistors, so when designing a power supply system it should be noted that VON has a temperature dependency of around –6 mV/°C. VIN P.VIN RC TIM (open) ON/OFF 50 kΩ RD Q2 Q3 GND To output stage To latch Q1 S.VIN To other circuitry Vref generation circuit Q4 Vref output On/off hysteresis circuit 3 2 Vref 1 0 VOFF 1.4 V 2.5 V VIN ≥ 4.5 V VON 2.1 V 0 1 2 3 4 5 VON/OFF Figure 7.2 Adjusting UVL Voltage Rev.2.0, Sep.18.2003, page 19 of 33 HA16116FP/FPJ, HA16121FP/FPJ Overcurrent Detection Value Setting The overcurrent detection value VTH for this IC series is 0.2 V (Typ) and the bias current is 200 µA (Typ) The power MOS FET peak current value before the current limiter goes into operation is derived from the following equation. ID = VTCL − (RF + RCS) ⋅ IBCL RCS Here VTH = VIN – VCL = 0.2 V, VCL is a voltage referd on GND. Note that CF and RCS form a low-pass filter, determined by their time constants, that prevents malfunctions from current spikes when the power MOS FET is turned on or off. S.VIN VCL To other circuitry CL CF 1800 PF IBCL RF 240 Ω G D This circuit is an example for step-down output use. S VO + − RCS 0.05 Ω VIN 1k 200 µA OUT Detection output (internal) IN(−) −+ Figure 8.1 Example for Step-Down Use The sample values given in this figure are calculated from the following equation. ID = 0.2 V − (240 Ω + 0.05 Ω) × 200 µA 0.05 Ω = 3.04 [A] The filter cutoff frequency is calculated as follows. fC = 1 2π CF RF = 1 6.28 × 1800 pF × 240 Ω = 370 [kHz] Rev.2.0, Sep.18.2003, page 20 of 33 HA16116FP/FPJ, HA16121FP/FPJ Absolute Maximum Ratings (Ta = 25°C) Rating Item Supply voltage Output current (DC) Output current (peak) Current limiter pin voltage Error amp input voltage E/O input voltage RT pin source current TIM pin sink current Power dissipation* 1 Symbol VIN IO IO peak VCL VIEA VIE/O IRT ITM PT Topr TjMax Tstg HA16116FP, HA16121FP 40 ±0.1 ±1.0 VIN VIN Vref 500 20 680* 1 HA16116FPJ, HA16121FPJ 40 ±0.1 ±1.0 VIN VIN Vref 500 20 680* 1 Unit V A A V V V µA mA mW °C °C °C Operation temperature range Junction temperature Storage temperature range Note: –40 to +85 125 –55 to +125 –40 to +85 125 –55 to +125 1. This value is based on actual measurements on a 40 × 40 × 1.6 mm glass epoxy circuit board. At a wiring density of 10%, it is the permissible value up to Ta = 45°C, but at higher temperatures this value should be derated by 8.3 mW/°C. At a wiring density of 30% it is the permissible value up to Ta = 64°C, but at higher temperatures it should be derated by 11.1 mW/°C. Permissible dissipation PT (mW) 800 680 mW 600 447 mW 400 348 mW 10% wiring density 30% wiring density 200 45°C 64°C 85°C 125°C 0 −40 −20 0 20 40 60 80 100 120 140 Operating ambient temperature Ta (°C) Rev.2.0, Sep.18.2003, page 21 of 33 HA16116FP/FPJ, HA16121FP/FPJ Electrical Characteristics (Ta = 25°C, VIN = 12 V, fOSC = 300 kHz) Item Reference voltage block Output voltage Line regulation Load regulation Output shorting current Vref OVP voltage Output voltage temperature dependence Triangle wave oscillator block Maximum oscillator frequency Minimum oscillator frequency Oscillator frequency input voltage stability Oscillator frequency temperature stability Oscillator frequency Dead band adjust block Low-level threshold voltage High-level threshold voltage Threshold differential voltage Output source current PWM comparator block Low-level threshold voltage High-level threshold oltage Threshold differential voltage Dead band precision Symbol Vref Line Load IOS Vrovp ∆Vref/∆Ta Min 2.45 — — 10 6.2 — Typ 2.50 30 30 25 6.8 100 Max 2.55 60 60 — 7.0 — Unit V mV mV mA V ppm/°C Test Conditions IO = 1 mA 4.5 V ≤ VIN ≤ 40 V 0 ≤ IO ≤ 10 mA Vref = 0 V fOSCmax fOSCmin ∆fOSC/∆VIN ∆fOSC/∆Ta fOSC VTLDB VTHDB ∆VTDB IOsource (DB) VTLCMP VTHCMP ∆VTCMP DBdev 600 — — — 270 0.87 1.48 0.55 100 0.87 1.48 0.55 –5 — — ±1 ±5 300 0.97 1.65 0.65 150 0.97 1.65 0.65 0 — 1 ±3 — 330 1.07 1.82 0.75 200 1.07 1.82 0.75 +5 kHz Hz % % kHz V V V µA V V V % 4.5 V ≤ VIN ≤ 40 V –20°C ≤ Ta ≤ 85°C CT = 220 pF, RT = 10 kΩ) Output on duty 0% Output on duty 100% ∆VTH = VTH – VTL DB pin = 0 V Output on duty = 0% Output on duty = 100% ∆VTH = VTH – VTL Deviation when VEO = (VTL + VTH)/2, duty = 50 % Rev.2.0, Sep.18.2003, page 22 of 33 HA16116FP/FPJ, HA16121FP/FPJ Electrical Characteristics (cont.) (Ta = 25°C, VIN = 12 V, fOSC = 300 kHz) Item Error amp block Input offset voltage Input bias current Output sink current Output source current Voltage gain Unity gain band-width High-level output voltage Low-level output voltage Overcurrent detection block Threshold voltage CL bias current Operating time Symbol VIOEA IBEA IOsink (EA) IOsource (EA) AV BW VOHEA VOLEA VTCL IBCL tOFFCL Min — — 28 28 40 3 2.2 — VIN–0.22 150 — — Output stage Output low voltage VOL1 — — — Off state low voltage VOL2 — Typ 2 0.8 40 40 50 4 3.0 0.2 VIN–0.2 200 200 500 0.7 1.6 1.0 1.6 Max 10 2 52 52 — — — 0.5 VIN–0.18 250 300 600 2.2 1.9 1.3 1.9 Unit mV µA µA µA dB MHz V V V µA ns ns V V V V CL = VIN CL = VIN –0.3 V Applies only to ch 2 of HA16121 IOsink = 10 mA Applies only to HA16116 IOsink = 10 mA Applies only to HA16121 IOsink = 0 mA Applies only to HA16121 IOsink = 1 mA ON/OFF pin = 0 V Applies only to ch 2 of HA16121 IOsink = 0 mA ON/OFF = 0 V Applies only to ch 2 of HA16121 IOsource = 10 mA IOsource = 0 A IOsource = 1 mA ON/OFF pin = 0 V IOsource = 0 A ON/OFF pin = 0 V CL = 1000 pF (to VIN) *1, *2 CL = 1000 pF (to VIN) *1, *2 IO = 10 µA IO = 10 µA In open loop, VI = 3 V, VO = 2 V In open loop, VI = 2 V, VO = 1 V f = 10 kHz Test Conditions — 1.0 1.3 V Output high voltage VOH1 VIN–1.9 VIN–1.3 VIN–1.6 VIN–1.0 VIN–1.6 VIN–1.0 70 70 — — — — 130 130 V V V V ns ns Off state high voltage VOH2 VIN–1.9 VIN–1.3 Rise time Fall time tr tf — — Rev.2.0, Sep.18.2003, page 23 of 33 HA16116FP/FPJ, HA16121FP/FPJ Electrical Characteristics (cont.) (Ta = 25°C, VIN = 12 V, fOSC = 300 kHz) Item UVL block VIN high-level threshold voltage VIN low-level threshold voltage VIN threshold differential voltage Vref high-level threshold voltage Vref low-level threshold voltage Vref threshold differential voltage ON/OFF block ON/OFF pin sink current IC on-state voltage IC off-state voltage ON/OFF threshold differential voltage TIM block TIM pin sink current in steady state TIM pin sink current at overcurrent detection Common block Operating current Symbol VTUH1 VTUL1 ∆VTU1 VTUH2 VTUL2 ∆VTU2 ION/OFF VON VOFF ∆VON/OFF ITIM1 ITIM2 IIN Min 3.3 3.0 0.1 1.7 1.4 0.1 — 1.8 1.1 0.5 0 10 6.0 8.5 11.0 Off current IOFF 0 0 Typ 3.6 3.3 0.3 2.0 1.7 0.3 35 2.1 1.4 0.7 — 15 8.5 12.1 15.7 — 120 Max 3.9 3.6 0.5 2.3 2.0 0.5 50 2.4 1.7 0.9 10 20 11.1 15.7 20.5 10 150 Unit V V V V V V µA V V V µA mA mA mA mA µA µA CL pin = VIN, VTIM = 0.3 V CL pin = VIN – 0.3 V VTIM = 0.3 V CL = 0 pF (to VIN) *1, *2 CL = 500 pF (to VIN) *1, *2 CL = 1000 pF (to VIN) *1, *2 HA16116FP HA16121FP ON/OFF pin = 0 V ∆VTU2 = VTUH2 – VTUL2 ON/OFF pin = 5 V ∆VTU1 = VTUH1 – VTUL1 Test Conditions Notes: 1. CL is load capacitor for Power MOS FET’s gate, and CL = 1000 pF to GND in the case of HA16121 – ch 2. 2. CL in channel 2 of HA16121 is connected to GND. Rev.2.0, Sep.18.2003, page 24 of 33 HA16116FP/FPJ, HA16121FP/FPJ Characteristic Curves • Reference Voltage Block (Vref) Reference Voltage vs. Power Supply Input Voltage 3 Reference voltage Vref (V) Reference voltage Vref (V) Ta = 25°C RA = 390 kΩ (Between the VIN and ON/OFF pins) Vref Temperature Characteristics 2.54 VIN = 12 V IO (Vref) = 1 mA 2.52 2.5 V 2 UVL release: 3.6 V UVL operate: 3.3 V 2.50 1 3.3 3.6 0 4.3 40 2.48 85 0 20 40 60 80 100 Ambient temperature Ta (°C) 1 2 3 4 5 Power supply input voltage VIN (V) 2.46 −20 Vref Load Regulation 3.0 Reference voltage Vref (V) 2.5 2.0 1.50 0 10 20 Output current IO sink (mA) Short circuit current 30 • UVL (Low Input Voltage Malfunction Prevention) Block Hysteresis Voltage Temperature Characteristics 4.5 High threshold voltage 4.0 VIN UL voltage (V) 3.5 Hysteresis 3.0 Low threshold voltage 2.5 −20 0 20 40 60 80 Ambient temperature Ta (°C) 100 Rev.2.0, Sep.18.2003, page 25 of 33 HA16116FP/FPJ, HA16121FP/FPJ • Triangle Wave Oscillator Block 1.1 RT pin Output Current Characteristics Sawtooth wave level (V) Sawtooth Wave Amplitude vs. Oscillator Frequency 2.0 VTH 1.5 VTL Sawtooth wave amplitude RT pin voltage (V) 1.0 1.0 0.9 Reccomended usage range 10 (RT ≈ 100 kΩ) 0.8 0 100 200 IRT (µA) 0.5 Note: Due to these characteristics, the dead band and PWM comparator threshold voltages change at high frequencies. 330 (RT ≈ 3 kΩ) 300 400 500 0 (DC) 100 200 300 400 500 600 fOSC (kHz) (linear scale) 100 70 50 RT (kΩ) CT, RT Values (VIN = 12V) vs. Oscillator Frequency C 10 0 pF T = F 47 30 20 22 10 47 00 .1 µF 00 pF 47 00 pF 0 pF 22 0p pF 600 kHz 10 7 5 3 10 00 pF 20 30 50 70 100 200 300 Oscillator frequency fOSC (kHz) 500 700 1 M Oscillator Frequency Temperature Stability +10 Frequency variation (∆f/fo) (%) VIN = 12 V +5 B 0 −5 −10 −20 A A: fOSC = 300 kHz B: fOSC = 600 kHz A B 85 0 20 40 60 Ambient temperature Ta (°C) 80 100 Rev.2.0, Sep.18.2003, page 26 of 33 HA16116FP/FPJ, HA16121FP/FPJ • Error Amplifier Block Open Loop Gain Characteristics 60 Open loop gain AVO (dB) AVO 40 φ 0 45 90 20 135 BW 0 1k 3k 10 k 30 k 100 k 300 k 1M 3M 180 10 M Error amplifier input frequency fIN (Hz) Common Mode Input Characteristics +100 Output offset VO (mV) 0 − EA + −100 VI Vref −200 VO −+ −300 0 1 2 3 Input voltage VI (V) 4 • On Duty Characteristics On Duty Characteristics 100 Step-down PWM output (HA16116-1, 2ch HA16121-1ch) 100 On Duty Characteristics Boost PWM output (HA16121-2 ch) Hz =5 0 kH z 0k 80 80 On duty*1 (%) SC 60 60 fO 0 On duty*2 (%) k Hz 30 60 0 z 40 40 kH z kH 30 20 20 0 0.8 1.0 1.2 1.4 VDB or VE/O (V) 1.6 1.8 0 0.8 1.0 fO 1.2 1.4 VDB or VE/O (V) SC =5 0k 0 Hz 60 1.6 Phase delay φ (deg.) 1.8 Notes: 1. The percentage of a single timing cycle during which the output is low. 2. The percentage of a single timing cycle during which the output is high. Rev.2.0, Sep.18.2003, page 27 of 33 HA16116FP/FPJ, HA16121FP/FPJ • Other Characteristics Current Limiter Level Temperature Characteristics 220 Detection voltage VTH (mV) IC On Voltage and Off Voltage Temperature Characteristics 4 VON or VOFF (V) 210 85°C 3 VON on voltage (about −6mV/°C) 2 VOFF off voltage (about −4mV/°C) 85°C 200 190 1 180 −20 0 20 40 60 Ambient temperature Ta (°C) 80 100 0 −20 0 20 40 60 80 Ambient temperature Ta (°C) 100 IIN vs. VIN Characteristics 40 fOSC = 300 kHz On duty: 50% Ta = 25°C 30 Current dissipation IIN (mA) Output pin (Output Resistor) Characteristics 12 Output high voltage when on Output high voltage when off (channels 1 and 2 in the HA16116 and channel 1 in the HA16121) VGS (P-channel Power MOS FET) Maximum rating at Ta = 25°C: 680 mW Output voltage VO (VDC) 11 10 Load capacitance: 1000 pF/ch 20 500 pF/ch 9 3 Output low voltage when on 2 Output low voltage when off (channels 1 and 2 in the HA16121) No load 10 1 0 10 20 30 Power supply voltage VIN (V) 40 0 2 4 6 8 IO sink or IO source (mA) 10 VGS (N-channel Power MOS FET) Output Drive Circuit Power MOS FET Direct Drive ability Data 800 VIN = 12 V fOSC = 130 kHz 600 IO peak (mA) Gate Drive Waveforms for the 2SJ214 2SJ214 400 2SJ176 2SJ216 Drive voltage: 5 V/div 200 Drive current: * 200 mA/div 1000 2000 Ciss (pF) Note: The solid line is data measured with discrete capacitances (for each channel of HA16116). 3000 4000 650 nsec/div Note: * Measured using a current probe. (The boost channel (channel 2 in the HA16121) load is with respect to ground, and has almost identical characteristics.) 0 Rev.2.0, Sep.18.2003, page 28 of 33 HA16116FP is used in a ±5 V output power supply, with a +12 V input. RA 390k 4700p 24k 1800p 33k 4.7 2SJ214 + 330µH HRP24 Vref VIN 0.05 12V 10k 240 100k + 2.2 − RB 4.7k CTM 2.2 S.VIN TIM E/O2 DB2 CL2 OUT2 P.VIN Cref 0.1 Vref ON/OFF IN(−)2 20 IN Application Examples (1) 19 − EA2 + from UVL VIN 5k UVL H OUT2* from UVL OR NAND (HA16116) L V L VH OVP PWM COMP 2 −+ CL2 0.2 V 18 + 470 − 17 16 15 14 13 to S.V 12 11 Rev.2.0, Sep.18.2003, page 29 of 33 20k 20k Step-down output +5 V 1A output − UVL output 0.8V + + − VIN VIN from UVL 0.8V 1.6 V HA16116FP/FPJ, HA16121FP/FPJ 2.5 V output band gap reference voltage ON/OFF generation circuit Triangle wave oscillator circuit Latch S R 0.8V PWM COMP 1 Vref 5k from UVL Q NAND OUT1 − + + Inverting output − 5k 1.0 V from UVL Triangle wave Latch reset pulse Bias current 1.1 V RT + EA1 − 330µH + − 470 −5 V 1A output CL1 −+ 0.2 V to S.VIN + HRP24 1 S.GND IN(+)1 2 CT RT IN(−)1 3 E/O1 4 100k 33k 4700p 10k 12k 12k 5 6 7 DB1 − + 8 9 CL1 OUT1 10 P.GND 2SJ214 4.7 2.2 24k R3 2k R4 12k 1800p CT 220p RT 10k 240 0.05 Units: R : Ω C : µF (unless otherwise specified) pF (p) The IC is the HA16116. HA16116FP/FPJ, HA16121FP/FPJ Overall Waveform Timing Diagram (for Application Examples (1)) 12 V VIN 0V 2.8 V 2.1 V VTIM, VON/OFF 2.1 V 1.4 V VTIM, VON/OFF 0V On (V) 3.0 VE/O Off 2.0 VE/O, VCT, VDB 1.0 VDB 0.0 VCL 12 V 11.8 V 0V Pulse-by-pulse current limiter operates VOUT*1 12 V PWM pulse 0 V DC/DC output (example for positive voltage) Soft start IC operation states Power IC on supply on Steady-state operation Overcurrent detected; intermittent operation Overcurrent Quick cleared; shut-off steady-state operation Power supply off, IC off VCT triangle wave Off On On On Off Off Off On Note: 1.This PWM pulse is on the step-down/inverting control channel. The booster control channel output consists of alternating L and H of the IC ÒonÓ cycle. Rev.2.0, Sep.18.2003, page 30 of 33 HA16116FP/FPJ, HA16121FP/FPJ Application Examples (2) (Some Pointers on Use) 1. Inductor, Power MOS FET, and Diode Connections 1. Booster specification VIN CF VIN CL RF RCS Applicable only to channel 2 of HA16121FP VO OUT GND FB 3. Inverting specification CF VIN CL OUT VO GND FB Vref GND FB RF RCS Applicable only to channel 1 GND FB 4. Negative booster specification (Flyback transformer) CF VIN CL OUT RF RCS Applicable only to channel 1 2. Step-down specification VIN CF VIN CL OUT RF RCS Applicable to HA16116FP and to channel 1 of HA16121FP VO 2. Turning Output On and Off while the IC is On 1. To turn only one channel off, ground the DB pin or the E/O pin. In the case of E/O, however, there will be no soft start when the output is turned back on. DB E/O OFF 2. When only one channel is to be used, the channel not used should be connected as follows. VIN Connect CL to VIN. Ground IN(+) and IN(−). Leave other pins open. CL IN + IN − GND Rev.2.0, Sep.18.2003, page 31 of 33 Power supply using the HA16121FP: +5 V input, +12 and −22 V outputs VIN RA 390k 24k RB 4.7k 4700p 10k 33k − + 5V Cref 0.1 0.05 1800p 2.2 330µH 240 CTM 2.2 20 from UVL 0.2 V VIN 5k Vref UVL H OUT2* from UVL OR NAND (HA16116) L VL VH OVP PWM COMP 2 −+ CL2 Application Examples (3) S.VIN 19 18 TIM 17 16 15 14 13 11 E/O2 DB2 CL2 OUT2 12 to S.VIN 4.7 HRP24 P.VIN Vref ON/OFF 100k IN(−)2 + 5.1 k + − EA2 + 470 − 2SK1094 1.3 k Boost output Rev.2.0, Sep.18.2003, page 32 of 33 +12 V output − UVL output 0.8V + + − VIN VIN from UVL 0.8V 1.6 V HA16116FP/FPJ, HA16121FP/FPJ 2.5 V band gap reference voltage ON/OFF generation circuit Triangle wave generation circuit Latch S R 0.8V PWM COMP 1 Vref 5k from UVL Q − + + 5k 1.0 V NAND OUT1 from UVL Triangle wave Latch reset pulses Bias current 1.1 V RT + EA1 − Inverting output + CL1 −+ 0.2 V to S.VIN 330µH + − 470 −12 V output − 1 S.GND CT RT RT 10k 4700p 10k CT 220p IN(+)1 IN(−)1 100k 33k 2 3 4 5 6 E/O1 − + 7 DB1 8 CL1 9 OUT1 10 P.GND 4.7 2.2 24k 1800p 240 0.05 2SJ214 12k 12k R3 1.2k Units: R : Ω C : µF (unless otherwise specified) pF (p) The IC is the HA16121. R4 22k HA16116FP/FPJ, HA16121FP/FPJ Package Dimensions As of January, 2003 12.6 13 Max 20 Unit: mm 11 5.5 1 10 2.20 Max *0.22 ± 0.05 0.20 ± 0.04 0.20 7.80 + 0.30 – 0.80 Max 1.15 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0˚ – 8 ˚ 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-20DA — Conforms 0.31 g Rev.2.0, Sep.18.2003, page 33 of 33 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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