Datasheet
RAA23021x
5.5V Input, 3A, Step-Down DC/DC Converter + LDO
R18DS0013EJ0102
Rev.1.02
Jul 23, 2014
Description
The RAA23021x is a high efficiency monolithic step-down DC/DC synchronous converter plus a LDO (low dropout)
regulator which has an ultra-low power mode.
Features
• DC/DC converter (ch1)
⎯ Synchronous rectification type step-down circuit
⎯ Integrated power MOSFETs
⎯ Preset output voltage (There are also products that have adjustable output voltage using external resistors.)
⎯ Internal phase compensator
⎯ Switching frequency: 1 MHz (fixed)
⎯ Internal timer-latch-type short-circuit protector (fixed delay time)
⎯ 100% duty cycle operation
• LDO (ch2)
⎯ 500mA
⎯ Internal over current protector (foldback-current limiting)
⎯ Ultra low-power save mode (25uA typical)
• Common Features
⎯ Internal rise up sequencer
⎯ Internal digital soft-start function (2 ms fixed soft-start time)
⎯ Internal discharge circuit
⎯ Power good function
⎯ Internal timer-latch-type thermal shutdown circuit (shutdown temperature: 150°C or higher)
⎯ Internal recovery-type under voltage lockout circuit
Application
⎯
⎯
⎯
⎯
Communication
Industrial
Building
Smart meter
And, usable around MCU, ASIC, FPGA, etc.
Ordering Information
Ordering Part No.
RAA230214GSB#HA0
RAA230215GSB#HA0
Package
20-pin HTSSOP
Tape and Reel
Embossed taping. 2,500pcs/reel
Note: A quality grade of these ICs is “Standard”. Recommended applications are indicated below.
Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment,
and industrial robots, etc.
R18DS0013EJ0102 Rev.1.01
Jul 23, 2014
Page 1 of 34
RAA23021x
Part No Summary
Part No.
RAA230214GSB
RAA230215GSB
Output
ch1:DC/DC
(step-down,
current mode)
ch2:LDO
Input
Voltage
3.0 V
to
5.5 V
Output Voltage
ch1
ch2
3.3
3.3
0.9 V to VIN×0.8
(Adjustable each
output individually
by external resistor)
Maximum
Output Current
ch1:3 A
ch2:0.5 A
Switching
Frequency
1 MHz
(fixed)
Package
20-pin
HTSSOP
Circuit example (RAA230215GSB)
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 2 of 34
RAA23021x
Block Diagram
ch1/ch2: Preset output voltage by internal resistor.
Sequence pattern 1 (ch1 followed by ch2)
VREG
Short-Circuit
Protection
Circuit SCP
SHDNB1
SHDNB2
Micro
controller
Control Circuit
Thermal
Shutdown
Circuit TSD
• ON/OFF
• Soft Start
• Discharge
AGND
Internal
Power Supply
VREG
AVDD
Reference
Voltage
VREF
VIN
Under Voltage Lockout
Circuit UVLO
TEST1
Oscillator
OSC
DSTB
VREG
TEST Circuit
TEST2
TEST3
VPIN1
ch1 OUT
E/A1
II1
0.8V
+
+
–
LOUT1
Output Control
(Current mode
/current limit)
ch1 OUT
PGND1
Phase
Compensator
ch1 or ch2
Discharge Control
PG
VPIN2
Control
LDO
ch2 OUT
OUT2
II2
Discharge Control
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 3 of 34
RAA23021x
ch1/ch2: Adjustable output voltage by external resistor.
Sequence pattern 2 (ch2 followed by ch1)
VREG
Short-Circuit
Protection
Circuit SCP
SHDNB1
Control Circuit
SHDNB2
Micro
controller
Thermal
Shutdown
Circuit TSD
• ON/OFF
• Soft Start
• Discharge
AGND
Internal
Power Supply
VREG
AVDD
Reference
Voltage
VREF
VIN
Under Voltage Lockout
Circuit UVLO
TEST1
Oscillator
OSC
DSTB
VREG
TEST Circuit
TEST2
TEST3
VPIN1
ch1 OUT
E/A1
II1
0.8V
+
+
–
LOUT1
Output Control
(Current mode
/current limit)
ch1 OUT
PGND1
Phase
Compensator
ch1 or ch2
Discharge Control
PG
VPIN2
Control
LDO
ch2 OUT
OUT2
Discharge Control
II2
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 4 of 34
RAA23021x
Pin Configuration
(Top View)
Pin Function
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
TEST1
II1
PGND11
PGND12
LOUT11
LOUT12
VPIN11
VPIN12
VPIN2
OUT2
II2
PG
AVDD
AGND
TEST2
VREG
TEST3
DSTB
SHDNB2
SHDNB1
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
I/O
—
Input
Ground
Ground
Output
Output
Power supply
Power supply
Power supply
Output
Input
Output
Power supply
Ground
—
Output
—
Input
Input
Input
Function
Test pin 1 (connect to AGND)
Inverted input for error amplifier of ch1
Power ground
Power ground
Inductor connection 1 for ch1
Inductor connection 2 for ch1
Output stage power input 1 of ch1
Output stage power input 2 of ch1
Output stage power input of ch2
Output of ch2
Inverted input for error amplifier of ch2
Power-good output (open-drain)
Analog block power supply
Analog ground
Test pin 2 (connect to VREG)
Internal power supply output (connect 1uF)
Test pin 3 (open)
Light-load operation mode setting pin
Output ON/OFF of ch2
Output ON/OFF of ch1
Page 5 of 34
RAA23021x
Absolute Maximum Ratings
(Unless otherwise specified, TA = 25°C)
Parameter
Analog power supply (AVDD pin)
VPIN pin applied voltage
SHDNB pin applied voltage
DSTB pin applied voltage
PG pin applied voltage
II pin applied voltage
VPIN11+VPIN12 pin sink current (peak)
Symbol
AVDD
VPIN
VSHDNB
VDSTB
VPG
VII
IPIN1(peak)–
LOUT11+LOUT12 pin output source
current (peak)
VPIN2 pin sink current (DC)
OUT2 pin output source current (DC)
ILO1(peak)+
LOUT11+LOUT12, OUT2 pin output
source current (DC)
Total power dissipation
Operating ambient temperature
Junction temperature
Storage temperature
ILO1,O2(DC)–
IPIN2(DC)–
IO2(DC)+
PT
TA
TJ
Tstg
Ratings
–0.5 to +6.5
–0.5 to +6.5
–0.5 to +6.5
–0.5 to +6.5
–0.5 to +6.5
–0.5 to +6.5
3500
3500
Unit
V
V
V
V
V
V
mA
mA
500
500
100
mA
mA
mA
3400*1
–40 to +85
–40 to +150
–55 to +150
mW
°C
°C
°C
Condition
AVDD
VPIN11, VPIN12, VPIN2
SHDNB1, SHDNB2
DSTB
PG
II1, II2
VPIN11+VPIN12
LOUT11, LOUT12
VPIN2
OUT2
when discharge circuit is
operation.
TA ≤ +25°C
Note:
*1 This is the value at TA ≤ +25°C. At TA > +25°C, the total power dissipation is derated by 34mW/°C.
Board specification : 4-layers glass epoxy board, 76.2mm x 114.3mm x 1.664mm.
Copper coverage area: 50%, 0.070mm thickness (top and bottom layers)
95%, 0.035mm thickness ( layers 2 and 3).
Connecting exposed pad
Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering
physical damage, and therefore the product must be used under conditions that ensure that the absolute
maximum ratings are not exceeded.
Recommended Operating Condition
(Unless otherwise specified, TA = 25°C)
Analog power supply voltage
(AVDD pin)
VPIN pin applied voltage
Parameter
AVDD
Min
3.0
Typ
5.0
Max
5.5
Unit
V
VPIN
—
AVDD
—
V
VPIN11, VPIN12, VPIN2
SHDNB pin applied voltage
DSTB pin applied voltage
PG pin applied voltage
II pin applied voltage
VREG pin capacitance
Operating junction temperature
VSHDNB
VDSTB
VPG
VII
CREG
TJO
0
0
0
0
—
–40
—
—
—
—
1.0
—
AVDD
AVDD
AVDD
AVDD
—
+125
V
V
V
V
μF
°C
SHDNB1, SHDNB2
DSTB
PG
II1, II2
VREG
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Symbol
Condition
AVDD
Page 6 of 34
RAA23021x
Electrical Characteristics
(Unless otherwise specified, TA = 25°C, AVDD = VPIN1 = VPIN2 = 5.0 V, VOUT2 = 3.3 V, fOSC = 1 MHz, DSTB = L)
Parameter
Total
Symbol
Min
Typ
Max
Unit
Condition
Standby current
IDD(STNBY)
—
1
2
μA
AIDD+IPIN1+IPIN2
SHDNB1 = SHDNB2 = AGND
Circuit operation current 1
IDD1
—
1.2
2
mA
AIDD, SHDNB1 = SHDNB2 = AVDD
DSTB = GND (normal mode)
Circuit operation current 2
IDD2
—
25
45
μA
AIDD, SHDNB1 = SHDNB2 = AVDD
DSTB = AVDD (ultra low-power
mode)
Internal power supply
voltage
VREG
2.25
2.4
2.55
V
IREG = 0mA
Operation start voltage
during rise time
AVDD(L-H)
2.7
2.9
3.0
V
AVDD pin voltage is detected
out circuit
(UVLO)
Operation stop voltage
AVDD(H-L)
2.6
2.8
3.0
V
AVDD pin voltage is detected
Short-circuit
II1 input detection voltage
(ch1)
VTH(II)1
65
75
85
%
II1 pin, Ratio to the output voltage
or E/A1 threshold voltage
Internal
power
supply block
(VREG)
Under
voltage lock
protection
circuit (SCP)
Delay time
t(DLY)
—
10
20
ms
Oscillation
block
Oscillation frequency
fOSC
—
1000
—
kHz
Soft start
block
Soft start time
tss
0.9
2.0
4.0
ms
ch1, ch2
PWM block
Maximum duty
DMAX.(PWM)
—
100
—
%
ch1
Output
ch1 output voltage accuracy
VOUT1
–2.5
—
+2.5
%
IO1 = 200mA, (with internal resistor)
voltage
ch2 output voltage accuracy
VOUT2
–1
—
+1
%
IO2 = 10mA, (with internal resistor)
E/A 1 input threshold
voltage
VITH1
0.780
0.800
0.820
V
Including input offset, (with external
resistor)
E/A 2 input threshold
voltage
VITH2
0.792
0.800
0.808
V
Including input offset, (with external
resistor)
accuracy
(with resistor
inside)
E/A block
(with resistor
outside)
P-ch ON resistance
Ron-p1
—
0.15
0.3
Ω
IO = 100mA
N-ch ON resistance
Ron-n1
—
0.15
0.3
Ω
IO = –100mA
ch1 ON resistance
Rondc1
—
100
200
Ω
ch1, IDC = 20mA
ch2 ON resistance
Rondc2
—
200
400
Ω
ch2, IDC = 20mA
VDIF2
0.5
—
—
V
IO2 = 20mA
regulator
The voltage between the
input and output
block (ch2,
Input regulation
REGIN2
—
—
50
mV
DSTB =
Load regulation
REGL2
—
—
50
mV
IO2 = 1mA to 500mA
Output short-circuit current
IO2short
—
100
—
mA
OUT2=AGND
Peak output current
IO2peak
550
—
—
mA
The voltage between the
input and output
VDIF2
0.5
—
—
V
regulator
block (ch2,
Input regulation
REGIN2
—
—
100
mV
IO2 = 10μA, VPIN = 3.0V to 5.5V
DSTB =
Load regulation
REGL2
—
—
100
mV
IO2 = 10μA to 50mA
Output block
Discharging
circuit block
Series
AGND:
normal
mode)
Series
AVDD: ultra
IO2 = 20mA, VPIN = 3.0V to 5.5V
IO2 = 10μA
low-power
mode)
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 7 of 34
RAA23021x
Electrical Characteristics (cont.)
(Unless otherwise specified, TA = 25°C, AVDD = VPIN1 = VPIN2 = 5.0 V, VOUT2 = 3.3 V, fOSC = 1 MHz, DSTB = L)
Parameter
Power-good
circuit block
Symbol
Min
Typ
Max
Unit
Condition
Threshold voltage
VTH(PG)
86
90
94
%
PG = "HiZ"→"L", "L"→"HiZ"
Ratio to the output voltage
PG pin output voltage
VPG
—
—
0.1
V
IPG– = 0.1mA
PG pin leakage current
ILEAK-PG
—
—
1
μA
SHDNB1, SHDNB2 = AGND
Delay time
tDLY-PG
—
—
2
ms
Time from detecting of output
startup until change form L to HiZ
on PG pin
ON/OFF
Threshold voltage
VTH
0.6
—
1.4
V
SHDNB1, SHDNB2, DSTB
controller
block
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 8 of 34
RAA23021x
Typical Performance Characteristics
(Unless otherwise specified, TA = 25°C, AVDD = VPIN1 = VPIN2 = 5.0 V)
Efficiency vs. Output Current (ch1)
VOUT=3.3 V
VOUT=1.8 V
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
VOUT=2.5V
VOUT=1.2V
Page 9 of 34
RAA23021x
Load Step Transient Waveforms
TA = 25°C, VIN = 5V, L1 = 2.2uH, CIN1 = CIN2 = 10uF, COUT1 = 20uF, COUT2 = 10uF
ch1
VOUT1
200mV/Div.
ch1
VOUT1=1.2V
VOUT1=3.3V
VOUT1
200mV/Div.
3A
IOUT1
1A/Div.
3A
0.02A
IOUT1
1A/Div.
0.02A
100us/Div.
100us/Div.
ch2 Normal operation
VOUT2
50mV/Div.
ch2 Normal operation
VOUT2=3.3V
VOUT2=1.2V
VOUT2
50mV/Div.
0.5A
IOUT2
0.2A/Div.
0A
IOUT2
0.2A/Div.
0.25A
0A
100us/Div.
100us/Div.
ch2 Ultra low-power mode
ch2 Ultra low-power mode
VOUT2
20mV/Div.
IOUT2
0.05A/Div.
VOUT2=3.3V
VOUT2
20mV/Div.
0.1A
0A
100us/Div.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
IOUT2
0.05A/Div.
VOUT2=1.2V
0.1A
0A
100us/Div.
Page 10 of 34
RAA23021x
Ch1 Operation Waveforms
VOUT1=3.3V, IOUT1=0.01A
VOUT1=3.3V, IOUT1=1A
VOUT1
50mV/Div.
VOUT1
50mV/Div.
LOUT1
2V/Div.
LOUT1
2V/Div.
IL1
0.5A/Div.
IL1
0.1A/Div.
0.4us/Div.
0.4us/Div.
VOUT1=3.3V, IOUT1=0A
VOUT1
50mV/Div.
LOUT1
2V/Div.
IL1
0.1A/Div.
4ms/Div.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 11 of 34
RAA23021x
Start-up and Shutdown Waveforms
Only SHDNB1 ON
Only SHDNB2 ON
SHDNB2
5V/div.
SHDNB1
5V/div.
VOUT2(3.3V) 1V/div.
VOUT1(2.5V)
1V/div.
VOUT2(3.3V) 1V/div.
VOUT1(2.5V)
1V/div.
2ms/Div.
2ms/Div.
Both SHDNB1 and SHDNB2 ON at the same time
SHDNB1
SHDNB2
5V/div.
VOUT2(3.3V) 1V/div.
VOUT1(2.5V)
1V/div.
2ms/Div.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 12 of 34
RAA23021x
Power Good Waveform *PG pin is connected to ch2 output(3.3V)
Start-up
Shutdown
SHDNB1
SHDNB2
5V/div.
SHDNB1
SHDNB2
5V/div.
VOUT2
2V/Div.
VOUT2
2V/Div.
PG
2V/Div.
PG
2V/Div.
1ms/Div.
1ms/Div.
Short-circuit protection waveform
VIN
2V/Div.
5V
VOUT1 3.3V
2V/Div.
Current limiting. (Typ. 4.5A)
After 10ms(Typ.),
all the outputs are latched to OFF by SCP.
IOUT1
2A/Div.
4ms/Div.
Ch1 output short-circuits.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 13 of 34
RAA23021x
Ch2(LDO) peak output current vs. output voltage (VIN=5.0V)
Ch2(LDO) output voltage vs. output current (VIN=5.0V)
VOUT2=3.3V
VOUT2=1.2V
Standby current vs. Operating ambient temperature
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 14 of 34
RAA23021x
IC Surface Temperature vs. Time
Ch1 and ch2 operation (normal mode)
VIN=5V
ch1:3.3V, 2A ch2 : 1.8V, 0.3A
TA = 25℃
Measured on Renesas Evaluation Board
Temperature Derating Curve
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 15 of 34
RAA23021x
Pakage Tempereture Rise vs. IOUT
VIN=5.0V
Only ch1 operation
Only ch2 operation
Maximum IOUT vs. Ambient Tempereture
VIN=5.0V
Only ch1 operation
Only ch2 operation
Note : When calculate the package temperature with both ch1 and ch2 operation, reference these data.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 16 of 34
RAA23021x
Control Block
SHDNB1, SHDNB2: ON/OFF Setting
Note:
SHDNB1
L
H
SHDNB2
L
L
ch1
OFF
ch2
OFF
L
H
Start-up in order of ch2 and ch1
Stop ch1 and ch2 at the same time
H
H
Start-up ch1 and ch2 at the same time
Stop ch1 and ch2 at the same time
Start-up in order of ch1 and ch2
Stop ch1 and ch2 at the same time
L: Low level, H: High level
OFF: circuit stand-by, ON: circuit operation status
When both SHDNB1 and SHDNB2 are H, RAA23021x continues operation even if one of them is turned to L.
RAA23021x stops when both of them are turned L.
DSTB: IC Ultra Low-Power Mode Setting
DSTB
L
H
Note:
IC Operation
Normal operation
Ultra low-power mode operation (ch1: stop, ch2: operation)
L: Low level, H: High level
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 17 of 34
RAA23021x
Output Status
VREG Pin Status
SHDNB1
L
H
L
H
H
L
H
Note:
SHDNB2
L
L
H
H
L
H
H
DSTB
L or H
L
VREG
AGND
2.4 V
H
AGND
L: Low level, H: High level
ch1, ch2 Output Pin Status
ch1 ⋅ ch2
Status
Stop
Operation
Note:
ch1
LOUT1
ch2
OUT2
PGND
(Discharge circuit: On)*
AGND
(Discharge circuit: On)
Set voltage
Pulse
(VPIN1 or PGND)
Ch1 discharge circuit is “On” during ultra low-power mode.
PG Pin Status (ch1, ch2 output detect)
IC Operation Status
DSTB
Pin
ch1, ch2 Output Status
PG
Output
Status
SHDNB1 = L
SHDNB2 = L
L or H
Stop
HiZ
SHDNB1 = H
or
SHDNB2 = H
L
SHDNB Pin
Note:
H
ch1 or ch2 output voltage is under 90% of the set voltage
L
ch1 and ch2 output voltage are over 90% of the set voltage
HiZ
ch1: Stop
ch2: Operation (Both output voltage is over 90% of setting voltage and under 90%)
HiZ
L: Low level, H: High level, HiZ: High impedance
Caution: When both ch1 and ch2 output voltage start up over 90%, there is delay time (under 2ms) before PG pin
becomes HiZ.
When using power good (PG pin), connect it to ch1 or ch2 output. Recommended value of pull-up resistor is
100kΩ.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 18 of 34
RAA23021x
Timing Chart
z Input
AVDD
SHDNB1
SHDNB2
z Output
2.4 V
VREG
90％
ch1 OUT
90％
AND
ch2 OUT
PG (Open)
PG
( Connect to
ch1 OUT or
ch2 OUT )
90％
90％
HiZ
HiZ
HiZ
HiZ
ch1OUT
or ch2OUT
2ms
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
2ms
2ms
Page 19 of 34
RAA23021x
Operation of Each Block (Overview)
Rise up sequencer
The IC “rise up” sequence feature has 3 patterns described below. The internal “rise up” sequence capability does not
need any additional external circuitry or components.
Pattern 1 : ch1 -> ch2
Pattern 2 : ch2 -> ch1
SHDNB1
SHDNB2
VOUT1
VOUT1
2ms
2ms
VOUT2
VOUT2
2ms
2ms
Pattern 3 : ch1 and ch2 at the same time
SHDNB1
SHDNB2
Note1 : Actuary, soft start begin after VREG rises up
VOUT1
2ms
Note2 : In all patterns, ch1 and ch2 shutdown starts at
the same time.
VOUT2
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 20 of 34
RAA23021x
Soft start
To limit the startup inrush current and output voltage overshoot, a soft start circuit is used to ramp up the reference
voltage from 0 V to its final value linearly. The soft start time are fixed for both ch1 and ch2 are 2ms(Typ.) and no
additional components are needed. Soft start feature gradually increases the error amplifier (E/A) input threshold
voltage by using the voltage that is generated by the digital soft start (DSS) circuit in 64 steps.
VOUT
E/A1, E/A2
II1, II2
-
DSS Circuit
+
0.8V
Note1 : This figure is the case of RAA230215
64 steps
SHDNB1
SHDNB2
VREG
0.8V
DSS
64 steps
LOUT1
VOUT1
VOUT2
2ms
Note2 : This chart is the case that ch1 and ch2 start
at the same time
Note3 : DSS waveform cannot be observed from IC
outside.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 21 of 34
RAA23021x
Discharge circuit
This IC has the discharge circuit for both ch1 and ch2. This enables a rapid discharge without an external MOSFET.
When SHDNB pin is changed from high level to low, discharge switches of ch1 and ch2 turn on at the same time, and
they discharge all capacitors which are connected to each output through LOUT1 and OUT2 pin.
When AVDD pin voltage becomes low level, discharge switches become off because there are no voltage to keep them
on. The control voltage of discharge switches is VREG, and the discharge time of VREG capacitor is over 100ms when
AVDD voltage fall down, so even if SHDNB pin is connected to AVDD pin, the output voltage of ch1 and ch2 can be
discharged because VREG voltage level can keep the discharge switches on.
About calculation of discharge time, see page 30.
VIN
ch1
Output
Control
VPIN11,12
Device A
Device B
LOUT11, 12
VREG
PGND11, 12
Device C
Discharge
Control
VPIN2
LDO
Device D
Discharge
Control
OUT2
Device E
Note : These dashed arrow are discharge line.
Power Good
Power Good (PG) is an open-drain output that requires a pull − up resistor (Recommended value = 100kΩ). PG releases
when the both ch1 and ch2 FB voltage and thus the output voltage rises above 90% of nominal regulation point. The PG
goes low when the FB voltage falls below 90% of the regulation point. When both SHDNB pins become low level, PG
pin become high impedance (HiZ) because VREG is used for PG control and it fall down at this time. So, if PG is
connected to AVDD, its status keep high level. PG pin must be connected to ch1 or ch2 output.
This function can be used for sequence signal for other devices.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 22 of 34
RAA23021x
Protection Circuit View
Operation Status
Protection
Circuit
Function
Short-circuit
protection
(SCP)
*Only ch1
Detect ch1 output voltage
dropping because of
short-circuit, etc.
(Timer latch type)
Thermal
shutdown
circuit
(TSD)
Detect increase of IC
internal temperature
(Over 150°C)
(Timer latch type)
Detect ch2 over current
Over current
protection
(OCP)
*Only ch2
Under voltage
lockout circuit
(UVLO)
Note:
Detect dropping of AVDD
(IC power supply)
Common Circuit
(VREG, OSC, etc.)
Operation
Output
Operation
All the output are
latched to OFF
Change SHDNB1 pin and
SHDNB2 pin from high to low
or
Drop AVDD pin input voltage
under the operation stop
voltage (2.8 V)
Operation
ch2 output is down
(ch1 continues
operation)
Release over current status
(Under the output short-circuit
current: 100 mA)
All the outputs are
stop
Up AVDD pin input voltage
over the operation start
voltage (2.9 V)
*1
Operation
All the output are
latched to OFF
Reset
The common circuit stops if AVDD is lower than VREG.
When ultra low-power mode, these protection circuits DO NOT operate.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 23 of 34
RAA23021x
Short-Circuit Protection Circuit (ch1)
When the voltage of ch1 drops, the voltage of the II1 pin also drops. If it falls below the input detection voltage of the
short-circuit protection circuit (under 75% of output voltage), the timer circuit starts operating. And after 10 ms, all the
outputs are latched to OFF. At this time, common circuits (such as the internal power supply block, and oscillator, etc.)
continue operating.
When the short-circuit protection circuit is operating, to reset the latch circuit, either change the level of the SHDNB1
pin and SHDNB2 pin from high to low or drop the level of the power supply voltage (AVDD) to the level below the
operation stop voltage of the under voltage lockout circuit (2.8 V).
• Timing Chart (when ch1 is short circuited)
SHDNB1
II1
The input
detection voltage
(1)
(2)
(3)
(1)
(1) At starting
⎯ A short-circuit will not be detected while the ch1 is undergoing a soft start (that is, short-circuit protection is not
triggered). If a short circuit occurs while ch1 is starting, short-circuit protection will start after the soft start time
elapses following startup.
⎯ If a short-circuit occurs in a channel that is operating while another channel is being soft-started, short-circuit
protection will start immediately.
(2) Short-circuit protection operation
⎯ If a short circuit is detected in ch1 (ch1 II pin voltage is lower than the input detection voltage except soft-stare
period), the timer circuit starts operating. And after 10 ms, all the outputs are latched to OFF.
⎯ Common circuits (such as the internal power supply block, and oscillator, etc.) continue operating.
(3) Cancelling short-circuit protection
⎯ To reset the latch circuit, either change the level of the SHDNB1 pin and SHDNB2 pin from high to low, or drop
the level of the power supply voltage (AVDD) to the operation stop voltage of the under voltage lockout circuit
(2.8 V).
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 24 of 34
RAA23021x
Thermal Shutdown Circuit (Timer Latch Type)
After overheating has been detected (shutdown temperature: 150°C or higher), the timer circuit starts operating (as same
as SCP). And after 10 ms, all the outputs are latched to OFF. Common circuits (such as the internal power supply block,
and oscillator, etc.) continue operating.
When the thermal shutdown circuit is operating, either change the level of the SHDNB1 pin and SHDNB2 pin from
high to low, or drop the level of the power supply voltage (AVDD) to the operation stop voltage of the under voltage
lockout circuit (2.8 V).
When ultra low-power mode, this circuits DOES NOT operate.
Under Voltage Lockout Circuit (Auto Recovery Type)
(1) Under voltage lockout operation
When the power supply voltage (AVDD) falls to the operation stop voltage (2.8 V), output from all channels stops.
Common circuits (such as the internal power supply block, and oscillator, etc.) continue operating.
(2) Restoring output
Once AVDD voltage is restored to the operation start voltage (2.9 V), the under voltage lockout operation is canceled
and output automatically resumes. The output voltage cannot be restored while the under voltage lockout circuit is
operating, not even by manipulating the SHDNB pin.
When ultra low-power mode, this circuits DOES NOT operate.
Current Limiting
Ch1 operates under the current control mode. If an overcurrent occurs, the current is limited on a pulse-by-pulse basis.
If the current sensor detects an overcurrent, the current is limited and the switching operation of the Power MOSFET in
the output stage stops until the next cycle.
When the ch1 current is limited, the output voltage drops. If the ch1 II pin voltage falls below the input detection
voltage, the short-circuit protection circuit starts operating.
Reference data (Unless otherwise specified, TA = 25°C, AVDD = VPIN1 = 5.0 V)
Item
Current limit
value
Symbol
Min
Typ
Max
unit
Measurement condition
ch1 Current limet 1
ILIM1_1
—
4.5
—
A
ch1OUT 3.3V
ch1 Current limet 2
ILIM1_2
—
4.5
—
A
ch1OUT 1.2V
Note: These data are for reference and not guaranteed as specifications.
Reverse Current Protection (ch1)
Ch1 have a reverse current protection circuit. When the bottom of inductor current is under ground, low-side N-ch
MOSFET of output block is stopped, and ch1 operate as diode rectification. So, consumption current at light load can
be reduced.
Over Current Protection (ch2)
Ch2 have a fold back type current protection circuit. If over current occur, protection operation is started and load
current is limited (output short-circuit current: 100 mA).
Peak output current depend on output voltage. When VPIN2=5V and VOUT2=3.3V,.it is over 550mA.
When ultra low-power mode, this circuits DOES NOT operate.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 25 of 34
RAA23021x
Ultra Low-Power Mode
This IC has the ultra-low power mode. By setting DSTB pin into high level, the IC operates in the ultra-low power
mode, and ch2 (LDO) operates. Then the consumption current is 25 μA (TYP.) and ch1 stops. If DSTB pin is set from
high level to low level, the IC operation changes to normal mode, and ch1 starts up with soft start.
When ultra low-power mode, protection circuits DOES NOT operate.
• Timing chart
• Input
DSTB
• Output
VREG
ch1 OUT
ch2 OUT
The output is continued.
PG
(Open)
HiZ
ch1 OUT
PG
(Connect to
ch1 OUT)
PG
(Connect to
ch2 OUT)
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
ch2 OUT
Page 26 of 34
RAA23021x
Advance on Designing
Setting Output Voltage (When the output voltage is set by external resistor)
The output voltage settings are shown in the figures below. The output voltage can be calculated by the equations
shown in these figures.
[Setting output voltage of ch1, ch2 by external resistor]
VOUT = (1+R1/R2) × 0.8
VOUT (Output voltage)
R1
E/A1, E/A2
–
+
R2
0.8V(TYP.)
Examples of R1 and R2 selection
Vout
0.9V
1.0V
1.05V
1.1V
1.18V
1.2V
1.5V
1.8V
2.5V
3.3V
R1
12k
16k
16k
15k
39k
15k
24k
30k
100k
75k
R2
91k
62k
51k
39k
82k
30k
27k
24k
47k
24k
Output voltage accuracy (When the output voltage is set by external resistor)
Output voltage accuracy can be calculated by an equation below.
VOUTACC is the output voltage accuracy (%).
VITHACC is the E/A input threshold voltage accuracy (%).
VOUT is the output voltage (V).
RACC is the external resistor accuracy (%).
So, each ch1 and ch2 output voltage accuracy is below.
Note : These equation don’t include Vout fluctuation by load step transient.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 27 of 34
RAA23021x
Handling of pins when not used
Connect unused pins as below.
Always connect AVDD pin, VPIN1 pin and VPIN2 pin with power supplies, and connect PGND1 pin and AGND with
the ground.
When DSTB pin is not used:.
Pin number
18
Pin name
DSTB
Connection
AGND
Pin name
SHDNB1
Connection
AGND
Pin name
SHDNB2
Connection
AGND
Pin name
PG
Connection
AGND
When SHDNB1 pin is not used:.
Pin number
20
When SHDNB2 pin is not used:.
Pin number
19
When PG pin is not used:.
Pin number
12
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 28 of 34
RAA23021x
Inductor selection
It is recommended to choose a inductor which ripple current (∆IL) becomes 20 to 40 % of Iout(max).
When ∆IL increases, inductor current peak raises, so ripple of Vout gets larger and power loss increases. But, large
inductor is required to lower ∆IL.
∆IL can be calculated by an equation below.
fsw is 1MHz.
Peak current of inductor (ILpeak) can be calculated by an equation below.
Choose a inductor which saturation current is higher than ILpeak .
Inductor Example
ch
Output Current
Inductor
Manufacturer
Inductance
ITEMP (A)
ISAT (A)
(uH)
ch1
less than 1.5A
1.5A to 3A
Size
(LxWxT, mm)
VLF504012MT-3R3M
TDK
3.3
2.4
2.1
5x4x1.2
NRS4018T3R3MDGJ
TAIYO YUDEN
3.3
2
2.3
4x4x1.8
744042003
WURTH
3.3
1.9
1.8
4.8x4.8x1.8
LTF5022T-2R2N3R2-LC
TDK
2.2
3.4
3.2
5.2x5x2.2
NR5024T2R2NMGJ
TAIYO YUDEN
2.2
3.1
4.1
4.9x4.9x2.4
744062002
WURTH
2.2
3.4
2.7
6.8x6.8x2.3
LTF5022T-1R5N3R6-LC
TDK
1.5
3.4
3.2
5.2x5x2.2
NR6020T1R5N
TAIYO YUDEN
1.5
3.2
4
6x6x2
7440620015
WURTH
1.5
4.3
4
6.8x6.8x2.3
Note ITEMP : Rated current by temperature rising
ISAT : Rated current by inductance loss
These inductors are examples. About inductor detail, contact each manufacturer
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 29 of 34
RAA23021x
Output capacitor selection
Each channel of RAA23021x has a phase compensation circuit which is optimized to each operation. In order to operate
stably with the phase compensation, connect the output capacitor :
DC/DC converter (ch1) : over 22uF
LDO (ch2) : over 10uF
Ceramic capacitor can be used for output capacitor. It has low ESR, so VOUT ripple is decreased.
VOUT ripple (∆Vrpl) can be calculated by an equation below.
Input capacitor selection
Recommended input capacitor of DC/DC converter can be calculated by an equation below. Connect the capacitor that
value is over calculated one.
About LDO, connect the capacitor that value is over 10uF.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 30 of 34
RAA23021x
Feedback capacitor
When RAA230215 (output voltage is set by external resistors) is used, connect 100pF capacitor in parallel to high side
output voltage setting resistor of ch1 to improve phase characteristic.
Don’t use at ch2.
VOUT
RAA230215
100pF
R1
II1
R2
Discharge time
RAA23021x has discharge circuit. Discharge time can be calculated by an equation below.
Vdc is a voltage after tdc(s).
CALL is sum of all capacitance which are connected to the output of RAA23021x (output capacitor, bypass
capacitor around MCU, etc.).
Rondc is on resistance of discharge circuit.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 31 of 34
RAA23021x
Notes on Use
Connection of power input pin
Be sure to apply the same voltage to AVDD pin and VPIN11 pin.
VPIN2 input voltage must be same or less than AVDD.
PG Connection
When using power good (PG pin), connect it to ch1 or ch2 output. If PG is connected to AVDD, PG outputs high (AVDD)
when SHDNB1 and SHDNB2 is low (because PG is high impedance when SHDNB1 and SDHNB2 is low).
Protection Circuit at Ultra Low-Power Mode
When ultra low-power mode, all protection circuits DO NOT operate.
Actual Pattern Wiring
To actually perform pattern wiring, separate the ground of the control signals (AGND) from the ground of the power
signals (PGND), so that these signals do not have common impedance as much as possible. In addition, lower the highfrequency impedance by using a capacitor, so that noise is not superimposed on the VREG pin.
Connection of Exposed PAD
RAA23021x has an exposed pad on the bottom to improve radiation performance. On the mounting board, connect to
AGND.
Connection of Component Ground
When connecting a component to ground, connect to the ground below.
Component
ch1 input capacitor, ch1 output capacitor
ch2 input capacitor, ch2 output capacitor
ch1 output voltage setting resistor (low side)
ch2 output voltage setting resistor (low side)
VREG capacitor
Connect Ground
PGND
AGND
Fixed Usage of Control Input Pin
When using fixed input pins SHDNB1, SHDNB2, DSTB input pins, connect each input to the pins listed below.
Connect Pin
Input Pin
SHDNB1
SHDNB2
DSTB
Fixed to Low Level
AGND
AGND
AGND
Fixed to High Level
AVDD
AVDD
AVDD
Connection of Test Pin
Connect each test pin to the pins listed below.
Test Pin
TEST1
TEST2
TEST3
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Connect Pin
AGND
VREG
OPEN
Page 32 of 34
RAA23021x
The case short-circuit is not protected.
If a power supply of RAA23021x has current limit which is under ch1 current limit 4.5A (Typ.), the voltage and thus
AVDD falls when ch1 output short-circuits. If it becomes under operation stop voltage of UVLO (Typ. 2.8V), all the
output voltage are stopped. Then ch1 short-circuit is stopped, so AVDD recovers. After it becomes above operation
start voltage of UVLO (Typ. 2.9V), ch1 and ch2 output are restored, and ch1 short-circuits again. A large current may
flow continuously by repeating these operations.
To avoid devices destruction by the large current, set the power supply current limit higher or use a fuse into the power
supply line.
VIN
2V/Div.
5V
VOUT1 3.3V
2V/Div.
In this case, VIN current limit = 1.5A
Large current flows
continuously.
IOUT1
2A/Div.
4ms/Div.
Ch1 output short-circuits.
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 33 of 34
RAA23021x
Package Dimensions
20-pin HTSSOP
R18DS0013EJ0102 Rev.1.02
Jul 23. 2014
Page 34 of 34
Revision History
RAA23021x Datasheet
Description
Rev.
1.01
1.02
Date
Jan 17, 2014
Jul 23, 2014
Page
2
7
Summary
First Edition of datasheet issued
Circuit example, added
Range of “Circuit operation current 2” and “Internal power supply voltage”,
changed
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