HA9P5127-5Z

DATASHEET HA-5127, HA-5127A FN2906 Rev 8.00 November 29, 2011 8.5MHz, Ultra-Low Noise Precision Operational Amplifier The HA-5127 monolithic operational amplifier features an unparalleled combination of precision DC and wideband high speed characteristics. Utilizing the Intersil D. I. technology and advanced processing techniques, this unique design unites low noise (3nV/Hz) precision instrumentation performance with high speed (10V/s) wideband capability. This amplifier’s impressive list of features include low VOS (10V), wide unity gain-bandwidth (8.5MHz), high open loop gain (1800V/mV), and high CMRR (126dB). Additionally, this flexible device operates over a wide supply range (5V to 15V) while consuming only 140mW of power. Using the HA-5127 allows designers to minimize errors while maximizing speed and bandwidth. This device is ideally suited for low level transducer signal amplifier circuits. Other applications which can utilize the HA-5127’s qualities include instrumentation amplifiers, pulse amplifiers, audio preamplifiers, and signal conditioning circuits. This device can easily be used as a design enhancement by directly replacing the 725, OP25, OP06, OP07, OP27 and OP37. For the military grade product, refer to the HA-5127/883 data sheet. Features • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/s • Unity Gain Bandwidth. . . . . . . . . . . . . . . . . . . . . . 8.5MHz • Low Noise . . . . . . . . . . . . . . . . . . . . . . . 3nV/Hz at 1kHz • Low VOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V • High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126dB • High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800V/mV • Pb-Free Available (RoHS Compliant) Applications • High Speed Signal Conditioners • Wide Bandwidth Instrumentation Amplifiers • Low Level Transducer Amplifiers • Fast, Low Level Voltage Comparators • Highest Quality Audio Preamplifiers • Pulse/RF Amplifiers Ordering Information Pinout HA-5127 (CERDIP, SOIC) TOP VIEW BAL 1 -IN 2 +IN 3 V- 4 PART NUMBER (Note 3) 8 BAL - + 7 V+ 6 OUT 5 NC PART MARKING TEMP. RANGE (°C) PKG. DWG. # PACKAGE HA7-5127A-5 (Note 4) HA7- 5127A-5 0 to +75 8 Ld CERDIP F8.3A HA9P5127-5 (Note 4) 5127 5 0 to +75 8 Ld SOIC M8.15 HA9P5127-5Z (Note 1) 5127 5Z 0 to +75 8 Ld SOIC (Pb-free) M8.15 8 Ld SOIC (Pb-free) M8.15 HA9P5127-5ZX96 5127 5Z (Notes 1, 2) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications. 3. For Moisture Sensitivity Level (MSL), please see device information page for HA-5127, HA-5127A. For more information on MSL please see techbrief TB363. 4. Not recommended for new designs. FN2906 Rev 8.00 November 29, 2011 Page 1 of 12 HA-5127, HA-5127A Absolute Maximum Ratings Thermal Information Supply Voltage Between V+ and V- Terminals . . . . . . . . . . . . . 44V Differential Input Voltage (Note 7) . . . . . . . . . . . . . . . . . . . . . . . 0.7V Output Current . . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection Thermal Resistance (Typical, Note 6) JA (°C/W) JC (°C/W) CERDIP Package. . . . . . . . . . . . . . . . . . . 115 28 SOIC Package . . . . . . . . . . . . . . . . . . . . . 157 N/A Maximum Junction Temperature (Ceramic Package, Note 5). . +175°C Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range HA5127/27A-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Maximum power dissipation, including output load must be designed to maintain the maximum junction temperature below +175°C for Hermetic packages, and below +150°C for the plastic packages. 6. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes. Electrical Specifications VSUPPLY = 15V, CL < 50pF, RS < 100Boldface limits apply over the operating temperature range, 0°C to +75°C. HA-5127A PARAMETER TEST CONDITIONS HA-5127 TEMP. (°C) MIN (Note 13) MAX MIN (Note 13) (Note 13) TYP 25 - 10 25 - 30 - V Full - 30 60 - 70 300 V TYP MAX (Note 13) UNITS INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Full - 0.2 0.6 - 0.4 1.8 V/°C Bias Current 25 - 10 40 - 15 80 nA Full - 20 60 - 35 150 nA Offset Current 25 - 7 35 - 12 75 nA Full - 15 50 - 30 135 nA Common Mode Range Full 10.3 11.5 - 10.3 11.5 - V Differential Input Resistance (Note 8) Input Noise Voltage (Note 9) Input Noise Voltage Density 25 1.5 6 - 0.8 4 - M 0.1Hz to 10Hz 25 - 0.08 0.18 - 0.09 0.25 VP-P f = 10Hz 25 - 3.5 8.0 - 3.8 8.0 nV/Hz - 3.1 4.5 - 3.3 4.5 nV/Hz - 3.0 3.8 - 3.2 3.8 nV/Hz - 1.7 4.0 - 1.7 - pA/Hz f = 100Hz - 1.0 2.3 - 1.0 - pA/Hz f = 1000Hz - 0.4 0.6 - 0.4 0.6 pA/Hz - 700 1500 - V/mV f = 100Hz f = 1000Hz Input Noise Current Density f = 10Hz 25 TRANSFER CHARACTERISTICS Large Signal Voltage Gain VOUT = 10V, RL = 2k 25 1000 1800 Full 600 1200 - 300 800 - V/mV Common Mode Rejection Ratio VCM = 10V Full 114 126 - 100 120 - dB Minimum Stable Gain 25 1 - - 1 - - V/V Unity-Gain-Bandwidth 25 5 8.5 - 5 8.5 - MHz RL = 600 25 10.0 11.5 - 10.0 11.5 - V RL = 2k Full 11.7 13.8 - 11.5 13.5 - V 25 111 160 - 111 160 - kHz 25 - 70 - - 70 -  25 16.5 25 - 16.5 25 - mA OUTPUT CHARACTERISTICS Output Voltage Swing Full Power Bandwidth (Note 10) Output Resistance Output Current FN2906 Rev 8.00 November 29, 2011 Open Loop Page 2 of 12 HA-5127, HA-5127A Electrical Specifications VSUPPLY = 15V, CL < 50pF, RS < 100Boldface limits apply over the operating temperature range, 0°C to +75°C. (Continued) HA-5127A PARAMETER TEST CONDITIONS TEMP. (°C) MIN (Note 13) TYP HA-5127 MAX MIN (Note 13) (Note 13) TYP MAX (Note 13) UNITS TRANSIENT RESPONSE (Note 11) Rise Time VOUT = 10V Slew Rate 25 - - 150 - - 150 ns 25 7 10 - 7 10 - V/s Settling Time (Note 12) 25 - 1.5 - - 1.5 - s Overshoot 25 - 20 40 - 20 40 % 25 - 3.5 - - 3.5 - mA POWER SUPPLY CHARACTERISTICS Supply Current VS = 4.5V to 18V Power Supply Rejection Ratio Full - - 4.0 - - 4.0 mA Full - 2 4 - 16 51 V/V NOTES: 8. This parameter value is based upon design calculations. 9. Refer to Typical Performance Curves. Slew Rate 10. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = --------------------------- . 2V PEAK 11. Refer to “Test Circuits and Waveforms” on page 3. 12. Settling time is specified to 0.1% of final value for a 10V output step and AV = -1. 13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Test Circuits and Waveforms IN + OUT - 1.8k IN 50pF + OUT - 2k 50pF 200 FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUITS IN IN OUT OUT Vertical Scale: Input = 0.5V/Div., Output = 5V/Div. Horizontal Scale: 1s/Div. LARGE SIGNAL RESPONSE FN2906 Rev 8.00 November 29, 2011 Vertical Scale: 100mV/Div. Horizontal Scale: 200ns/Div. SMALL SIGNAL RESPONSE Page 3 of 12 HA-5127, HA-5127A Test Circuits and Waveforms (Continued) +15V 2N4416 TO OSCILLOSCOPE 5k 5k 2k 14. AV = -1. +15V + AUT VIN 15. Feedback and summing resistors should be 0.1% matched. VOUT 50pF - 2k NOTES: 16. Clipping diodes are optional. HP5082-2810 recommended. -15V 2k FIGURE 2. SETTLING TIME TEST CIRCUIT Schematic Diagram BALANCE 1 R25 QP32 R15 R1 8 R16 QP37 R20 R2 QP35 R21 QP43 R17 QP38 QP44 QP55 C5 QN19 QN46 QP56 C4 QN47 QN13 R1A R2A R9 D9 QP26 D41 QN12 QP26 QN4 R18 QN1A QN18 QN1 QN7 QN5 QN42A QN49 R6 R10 R8 C2 C3 QN50 QN48 QN39 R5 QN6 QN42 QN25 QN24 QP30 R19 QP40 D31 R4 QP16 R3 QN2A D22 4 QP17 D54 QP36 QP27 QP36A QN2 QN15 QN52 C6 D53 QN14 R7 QN51 QN3 C1 R22 R23 QN10 UBSTRATE QN11 3 +INPUT 2 -INPUT FN2906 Rev 8.00 November 29, 2011 Page 4 of 12 R11 HA-5127, HA-5127A Application Information V+ RT 10k 1 2 3 4 8 - + 7 6 5 NOTE: Tested Offset Adjustment Range is |VOS + 1mV| minimum referred to output. Typical range is 4mV with RT = 10k. FIGURE 3. SUGGESTED OFFSET VOLTAGE ADJUSTMENT CS + R1 R1 - R3 R2 R2 - + R3 C3 Low resistances are preferred for low noise applications as a 1k resistor has 4nV/Hz of thermal noise. Total resistances of greater than 10k on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability. FIGURE 4. SUGGESTED STABILITY CIRCUITS FN2906 Rev 8.00 November 29, 2011 Page 5 of 12 HA-5127, HA-5127A Unless Otherwise Specified: TA = +25°C, VSUPPLY = 15V 30 20 NOISE VOLTAGE (nV/Hz) OFFSET VOLTAGE (V) 10 0 -10 -20 -30 -40 12 6 10 5 8 4 6 3 NOISE VOLTAGE 4 1 NOISE CURRENT -60 -60 -40 -20 0 20 40 60 80 100 0 120 1 10 100 1k 10k FREQUENCY (Hz) TEMPERATURE (°C) 0.14 140 0.12 120 0.10 100 0.08 0.06 0.02 20 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 0 10 20 FIGURE 7. NOISE vs SUPPLY VOLTAGE 9 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 8. CMRR vs FREQUENCY 6.0 OFFSET VOLTAGE CHANGE (V) TA = +45°C 8 VIO DRIFT (V) 0 60 40 6 1M 80 0.04 4 100k FIGURE 6. NOISE CHARACTERISTICS CMRR (dB) INPUT NOISE VOLTAGE (VP-P) FIGURE 5. TYPICAL OFFSET VOLTAGE DRIFT vs TEMPERATURE 0 2 2 -50 NOISE CURRENT (pA/Hz) Typical Performance Curves 7 6 5 4 5.0 4.0 3.0 2.0 1.0 5 TYPICAL UNITS 3 0 10 20 30 40 DAYS FIGURE 9. OFFSET VOLTAGE DRIFT vs TIME FN2906 Rev 8.00 November 29, 2011 0.0 0.0 1.0 2.0 3.0 4.0 TIME AFTER POWER ON (MINUTES) FIGURE 10. OFFSET VOLTAGE WARM UP DRIFT Page 6 of 12 5.0 HA-5127, HA-5127A Typical Performance Curves Unless Otherwise Specified: TA = +25°C, VSUPPLY = 15V 140 (Continued) 40 30 120 20 100 80 +PSRR 60 0 0 PHASE -10 90 -20 40 -30 20 0 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M FIGURE 11. PSRR vs FREQUENCY 100 10K 100K 1M FREQUENCY (Hz) 10M 100M 1.05 SLEW RATE NORMALIZED TO 1 AT 30°C 16 AVOL (100kV/V) AND VOUT (V) 1K FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY 17 15 AVOL 14 13 12 VOUT 11 10 9 8 7 6 5 0 2 4 6 LOAD RESISTANCE (k) 8 10 1.01 1.0 0.99 0.98 0.97 0.96 -40 -20 0 20 40 60 28 80 100 120 RL = 2k CL = 50pF 24 OUTPUT VOLTAGE (VP-P) 2.80 2.78 2.76 2.74 2.72 20 16 12 8 2.70 4 2.68 25 TEMPERATURE (°C) FIGURE 15. SUPPLY CURRENT vs TEMPERATURE FN2906 Rev 8.00 November 29, 2011 1.02 FIGURE 14. NORMALIZED SLEW RATE vs TEMPERATURE VO = 0V -55 1.03 TEMPERATURE (°C) FIGURE 13. AVOL AND VOUT vs LOAD RESISTANCE 2.82 RL = 2k 1.04 CL = 50pF 0.95 -60 4 SUPPLY CURRENT (mA) 180 -40 PHASE (DEGREES) GAIN (dB) PSRR (dB) GAIN 10 -PSRR 125 0 0.4 0.8 1.2 FREQUENCY (MHz) 1.6 FIGURE 16. MAX UNDISTORTED SINEWAVE OUTPUT vs FREQUENCY Page 7 of 12 2.0 HA-5127, HA-5127A Typical Performance Curves Unless Otherwise Specified: TA = +25°C, VSUPPLY = 15V NORMALIZED SLEW RATE AND BANDWIDTH 2.60 2.58 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 140 GAIN (dB) 0 20 -45 0 -90 PHASE GAIN (dB) -135 10K 100K 1M -180 10M 100M FREQUENCY (Hz) FIGURE 19. OPEN LOOP GAIN AND PHASE FN2906 Rev 8.00 November 29, 2011 0.95 0.94 0.93 SLEW RATE 0.92 0.91 0.90 2 15 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 20 10 AV = +1 RL = 2k CL = 50pF 5 GAIN PHASE SHIFT (DEGREES) 40 1K 0.96 0 GAIN 100 BANDWIDTH 0.97 20 80 10 0.98 FIGURE 18. BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 100 60 0.99 0 RL = 2k 120 1.00 20 FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE BANDWIDTH AT 0dB AOL VOUT = 10V STEP RL = 2k, CL = 50pF 1.01 0 PHASE -45 -90 -135 1K 10K 100K 1M FREQUENCY (Hz) 10M -180 100M FIGURE 20. CLOSED LOOP GAIN AND PHASE Page 8 of 12 PHASE SHIFT (DEGREES) SUPPLY CURRENT (mA) 2.56 1.02 (Continued) HA-5127, HA-5127A Typical Performance Curves Unless Otherwise Specified: TA = +25°C, VSUPPLY = 15V (Continued) Horizontal Scale = 1s/Div. Vertical Scale = 0.002V/Div. ACL = 25,000V/V, EN = 0.08VP-P RTI FIGURE 21. PEAK-TO-PEAK NOISE VOLTAGE (0.1Hz TO 10Hz) FN2906 Rev 8.00 November 29, 2011 Page 9 of 12 HA-5127, HA-5127A Die Characteristics DIE DIMENSIONS: PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ 104 mils x 65 mils x 19 mils 2650m x 1650m x 483m METALLIZATION: TRANSISTOR COUNT: Type: Al, 1% Cu Thickness: 16kÅ 2kÅ 63 SUBSTRATE POTENTIAL (Powered Up): PROCESS: V- Bipolar Dielectric Isolation Metallization Mask Layout HA-5127 BAL V+ OUT NC BAL -IN FN2906 Rev 8.00 November 29, 2011 +IN V- Page 10 of 12 HA-5127, HA-5127A Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN2906 Rev 8.00 November 29, 2011 Page 11 of 12 HA-5127, HA-5127A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) LEAD FINISH c1 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL (c) E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 b2 ccc M C A-B S D S eA/2 NOTES - 0.200 - 5.08 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 eA e b MAX b  A A MIN A A L MILLIMETERS MAX M (b) D BASE PLANE MIN b1 SECTION A-A D S INCHES SYMBOL c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.  90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 8 5. This dimension allows for off-center lid, meniscus, and glass overrun. 8 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH © Copyright Intersil Americas LLC 2002-2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2906 Rev 8.00 November 29, 2011 Page 12 of 12