HD6417020SVX12I

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Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. User’s Manual 32 SH7020 and SH7021 Hardware Manual SuperH™ RISC engine HD6437020, HD6477021, HD6437021, HD6417021 Rev.3.0 1998.09 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Introduction The SH7020 and SH7021 are part of a new generation of reduced instruction-set computer-type (RISC) microcomputers that integrate RISC-type CPUs and the peripheral functions required for system configuration onto a single chip to achieve high-performance operations processing. They can operate in a power-down state, which is an essential feature for portable equipment. The SH7020 and SH7021 CPUs have RISC-type instruction sets. Basic instructions can be executed in a single clock cycle, which strikingly improves instruction execution speed. The SH7020 and SH7021 include peripheral functions such as large-capacity ROM (PROM or masked ROM), RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an interrupt controller (INTC), and I/O ports. These on-chip elements enable users to construct systems with the fewest possible components. External memory access support functions enable direct connection to SRAM and DRAM. without the use of glue logics. This Hardware Manual describes in detail the hardware functions of the SH7020 and SH7021. For information on the instructions, please refer to the Programming Manual. Related Manuals SH7000 Series Instructions "SH-1/SH-2/SH-DSP Programming Manual" For development support tools, contact your Hitachi sales office. Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the Sections within this manual. Table 1 Manual Organization Category Section Title Abbreviation Overview 1. Overview — Features, internal block diagram, pin layout, pin functions CPU 2. CPU CPU Register configuration, data structure. instruction features, instruction types, instruction lists Operating Modes 3. Operating Modes — MCU mode, PROM mode Internal Modules 4. Exception Processing — Resets, address errors, interrupts, trap instructions, illegal instructions 5. Interrupt Controller INTC NMI interrupts, user break interrupts, IRQ interrupts, on-chip module interrupts 6. User Break Controller UBC Break address and break bus cycles selection Clock 7. Clock Pulse Generator CPG Crystal pulse generator, duty correction circuit Buses 8. Bus State Controller BSC Division of memory space, DRAM interface, refresh, wait state control, parity control 9. Direct Memory Access Controller DMAC Auto request, external request, on-chip peripheral module request, cycle steal mode, burst mode 10. 16-Bit IntegratedTimer Pulse Unit ITU Waveform output mode, input capture function, counter clear function, buffer operation, PWM mode, complementary PWM mode, reset synchronized mode, synchronized operation, phase counting mode, compare match output mode 11. Programmable Timing Pattern Controller TPC Compare match output triggers, non-overlap operation 12. Watchdog Timer WDT Watchdog timer mode, interval timer mode 13. Serial Communication Interface SCI Asynchronous mode, clock synchronous mode, multiprocessor communication function Timers Data Processing Contents Table 1 Manual Organization (cont) Abbreviation Contents 14. Pin Function Controller PFC Pin function selection 15. Parallel I/O Ports I/O I/O port 16. ROM ROM On-chip ROM 17. RAM RAM On-chip RAM Power-Down States 18. Power-Down States — Sleep mode, standby mode Electrical Characteristics 19. Electrical Characteristics — Absolute maximum ratings, AC characteristics, DC characteristics, operation timing Category Section Title Pins Memory 1. Overview 3. Operating modes 2. CPU On-chip modules 4. Exception processing 5. Interrupt controller (INTC) 6. User break controller (UBC) 7. Clock pulse generator (CPG) Timers Buses 8. Bus state controller (BC) 10. 16-bit integrated-timer pulse unit (ITU) 9. Direct memory access controller (DMAC) 11. Programmable timing pattern controller (TPC) 12. Watchdog timer (WDT) Memory Data processing 16. ROM 17. RAM 13. Serial communication interface (SCI) Pins 14. Pin function controller (PFC) 15. Parallel I/O ports 18. Power-down states 19. Electrical characteristics Manual Organization Scheme Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas in 512 byte units that contain exactly the same contents as the actual registers are thus provided in the on-chip peripheral module space. In this manual, register addresses are specified as though the on-chip peripheral module registers were in the 512 bytes H'5FFFE00–H'5FFFFFF. Only the values of the A27–A24 and A8–A0 bits are valid; the A23–A9 bits are ignored. When H'5000000–H'50001FF is accessed, for example, the result will be the same as when H'5FFFE00–H'5FFFFFF is accessed. For more details, see Section 8.3.5, Area Description: Area 5. Free Addresses in the On-chip Peripheral Module Space (Area 5) Avoid reading/writing from/to the free addresses without registers in the on-chip peripheral module space (area 5: H'5000000-H'5FFFFFF). Contents Section 1 Overview ............................................................................................................ 1.1 1.2 1.3 SH Microcomputer Features.............................................................................................. Block Diagram................................................................................................................... Pin Descriptions................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 1.3.3 Pin Layout by Mode ............................................................................................. 1 1 7 8 8 9 13 Section 2 CPU ...................................................................................................................... 15 2.1 2.2 2.3 2.4 2.5 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn) ......................................................................................... 2.1.2 Control Registers.................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers .................................................................................... Data Formats...................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory ....................................................................................... 2.2.3 Immediate Data Format........................................................................................ Instruction Features .............................................................................................................. 2.3.1 RISC-Type Instruction Set ................................................................................... 2.3.2 Addressing Modes................................................................................................ 2.3.3 Instruction Formats .............................................................................................. Instruction Set.................................................................................................................... 2.4.1 Instruction Set by Classification .......................................................................... 2.4.2 Operation Code Map ............................................................................................ CPU State .......................................................................................................................... 2.5.1 State Transitions ................................................................................................... 2.5.2 Power-Down State................................................................................................ 15 15 15 16 17 17 17 18 18 19 19 22 25 28 28 39 41 41 43 Section 3 Operating Modes .............................................................................................. 45 3.1 3.2 Types of Operating Modes and Their Selection................................................................ Operating Mode Descriptions............................................................................................ 3.2.1 Mode 0 (MCU Mode 0)........................................................................................ 3.2.2 Mode 1 (MCU Mode 1)........................................................................................ 3.2.3 Mode 2 (MCU Mode 2)........................................................................................ 3.2.4 Mode 7 (PROM Mode) ........................................................................................ 45 45 45 45 45 45 Section 4 Exception Processing ..................................................................................... 47 4.1 Overview............................................................................................................................ 47 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.1.1 Exception Processing Types and Priorities .......................................................... 4.1.2 Exception Processing Operation .......................................................................... 4.1.3 Exception Process Vector Table .......................................................................... Reset .................................................................................................................................. 4.2.1 Reset Types .......................................................................................................... 4.2.2 Power-On Reset.................................................................................................... 4.2.3 Manual Reset........................................................................................................ Address Errors ................................................................................................................... 4.3.1 Address Error Sources.......................................................................................... 4.3.2 Address Error Exception Processing.................................................................... Interrupts............................................................................................................................ 4.4.1 Interrupt Sources .................................................................................................. 4.4.2 Interrupt Priority Rankings................................................................................... 4.4.3 Interrupt Exception Processing ............................................................................ Instruction Exceptions ....................................................................................................... 4.5.1 Types of Instruction Exceptions........................................................................... 4.5.2 Trap Instruction .................................................................................................... 4.5.3 Illegal Slot Instruction .......................................................................................... 4.5.4 General Illegal Instructions .................................................................................. Cases in Which Exceptions Are Not Accepted ................................................................. 4.6.1 Immediately after Delayed Branch Instructions................................................... 4.6.2 Immediately after Interrupt-Disabling Instructions.............................................. Stack Status after Exception Processing............................................................................ Notes.................................................................................................................................. 4.8.1 Value of the Stack Pointer (SP)............................................................................ 4.8.2 Value of the Vector Base Register (VBR) ........................................................... 4.8.3 Address Errors that Are Caused by Stacking During Address Error Exception Processing............................................................................................ 47 49 49 51 51 51 52 52 52 53 54 54 54 55 55 55 55 56 56 57 57 57 58 59 59 59 59 Section 5 Interrupt Controller (INTC) .......................................................................... 61 5.1 5.2 5.3 Overview............................................................................................................................ 61 5.1.1 Features ................................................................................................................ 61 5.1.2 Block Diagram...................................................................................................... 61 5.1.3 Pin Configuration ................................................................................................. 63 5.1.4 Registers ............................................................................................................... 63 Interrupt Sources................................................................................................................ 63 5.2.1 NMI Interrupts...................................................................................................... 64 5.2.2 User Break Interrupt ............................................................................................. 64 5.2.3 IRQ Interrupts ...................................................................................................... 64 5.2.4 On-Chip Interrupts................................................................................................ 64 5.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 65 Register Descriptions......................................................................................................... 68 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) ................................................... 68 5.4 5.5 5.5 5.3.2 Interrupt Control Register (ICR) .......................................................................... 69 Interrupt Operation ............................................................................................................ 70 5.4.1 Interrupt Sequence................................................................................................ 70 5.4.2 Stack after Interrupt Exception Processing .......................................................... 72 Interrupt Response Time.................................................................................................... 73 Usage Notes ....................................................................................................................... 74 Section 6 User Break Controller (UBC) ...................................................................... 75 6.1 6.2 6.3 6.4 6.5 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 6.2.1 Break Address Registers (BAR) .......................................................................... 6.2.2 Break Address Mask Register (BAMR)............................................................... 6.2.3 Break Bus Cycle Register (BBR) ......................................................................... Operation ........................................................................................................................... 6.3.1 Flow of the User Break Operation........................................................................ 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing............................................................................................................. Setting User Break Conditions .......................................................................................... Notes.................................................................................................................................. 6.5.1 On-Chip Memory Instruction Fetch ..................................................................... 6.5.2 Instruction Fetch at Branches ............................................................................... 6.5.3 Instruction Fetch Break ........................................................................................ 75 75 75 76 77 77 78 79 81 81 84 84 84 86 86 86 87 Section 7 Clock Pulse Generator (CPG) ..................................................................... 89 7.1 7.2 7.3 Overview............................................................................................................................ 89 Clock Source...................................................................................................................... 89 7.2.1 Connecting a Crystal Resonator ........................................................................... 89 7.2.2 External Clock Input ............................................................................................ 90 Usage Notes ....................................................................................................................... 91 Section 8 Bus State Controller (BSC) ........................................................................... 93 8.1 8.2 Overview............................................................................................................................ 93 8.1.1 Features ................................................................................................................ 93 8.1.2 Block Diagram...................................................................................................... 93 8.1.3 Pin Configuration ................................................................................................. 95 8.1.4 Register Configuration ......................................................................................... 95 8.1.5 Overview of Areas................................................................................................ 96 Register Descriptions......................................................................................................... 97 8.2.1 Bus Control Register (BCR) ................................................................................ 97 8.2.2 Wait State Control Register 1 (WCR1)................................................................ 8.2.3 Wait State Control Register 2 (WCR2)................................................................ 8.2.4 Wait State Control Register 3 (WCR3)................................................................ 8.2.5 DRAM Area Control Register (DCR).................................................................. 8.2.6 Refresh Control Register (RCR) .......................................................................... 8.2.7 Refresh Timer Control/Status Register (RTCSR) ................................................ 8.2.8 Refresh Timer Counter (RTCNT) ........................................................................ 8.2.9 Refresh Time Constant Register (RTCOR).......................................................... 8.2.10 Parity Control Register (PCR).............................................................................. 8.2.11 Notes on Register Access ..................................................................................... 8.3 Address Space Subdivision................................................................................................ 8.3.1 Address Spaces and Areas.................................................................................... 8.3.2 Bus Width............................................................................................................. 8.3.3 Chip Select Signals (CS0–CS7)............................................................................ 8.3.4 Shadows................................................................................................................ 8.3.5 Area Description .................................................................................................. 8.4 Accessing External Memory Space ................................................................................... 8.4.1 Basic Timing ........................................................................................................ 8.4.2 Wait State Control ................................................................................................ 8.4.3 Byte Access Control ............................................................................................. 8.5 DRAM Interface Operation ............................................................................................... 8.5.1 DRAM Adress Multiplexing ............................................................................... 8.5.2 Basic Timing ........................................................................................................ 8.5.3 Wait State Control ................................................................................................ 8.5.4 Byte Access Control ............................................................................................. 8.5.5 DRAM Burst Mode .............................................................................................. 8.5.6 Refresh Control .................................................................................................... 8.6 Address/Data Multiplexed I/O Space Access.................................................................... 8.6.1 Basic Timing ........................................................................................................ 8.6.2 Wait State Control ................................................................................................ 8.6.3 Byte Access Control ............................................................................................. 8.7 Parity Check and Generation ............................................................................................. 8.8 Warp Mode........................................................................................................................ 8.9 Wait State Control ............................................................................................................. 8.10 Bus Arbitration .................................................................................................................. 8.10.1 The Operation of Bus Arbitration ........................................................................ 8.10.2 BACK Operation.................................................................................................. 8.11 Usage Notes ....................................................................................................................... 8.11.1 Usage Notes on Manual Reset.............................................................................. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 8.11.3 Maximum Number of States from BREQ Input to Bus Release ......................... 98 101 103 104 107 108 110 112 112 114 115 115 117 117 118 120 128 128 129 133 134 134 136 138 140 142 148 151 152 153 153 154 154 155 157 158 159 161 161 164 164 Section 9 Direct Memory Access Controller (DMAC) ......................................... 169 9.1 9.2 9.3 9.4 9.5 Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Pin Configuration ................................................................................................. 9.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 9.2.2 DMA Destination Address Registers 0-3 (DAR0–DAR3) .................................. 9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... 9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 9.2.5 DMA Operation Register (DMAOR)................................................................... Operation ........................................................................................................................... 9.3.1 DMA Transfer Flow ............................................................................................. 9.3.2 DMA Transfer Requests....................................................................................... 9.3.3 Channel Priority.................................................................................................... 9.3.4 DMA Transfer Types ........................................................................................... 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 9.3.6 DMA Transfer Ending Conditions ....................................................................... Examples of Use................................................................................................................ 9.4.1 DMA Transfer between On-Chip RAM and a Memory-Mapped External Device .................................................................................................... 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory.......... Cautions ............................................................................................................................. 169 169 170 172 173 174 174 174 175 175 180 182 182 184 186 191 198 205 206 206 207 208 Section 10 16-Bit Integrated-Timer Pulse Unit (ITU) ............................................ 213 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Input/Output Pins.................................................................................................. 10.1.4 Register Configuration ......................................................................................... 10.2 ITU Register Descriptions ................................................................................................. 10.2.1 Timer Start Register (TSTR)................................................................................ 10.2.2 Timer Synchro Register (TSNC).......................................................................... 10.2.3 Timer Mode Register (TMDR) ............................................................................ 10.2.4 Timer Function Control Register (TFCR)............................................................ 10.2.5 Timer Output Control Register (TOCR) .............................................................. 10.2.6 Timer Counters (TCNT)....................................................................................... 10.2.7 General Registers A and B (GRA and GRB) ....................................................... 10.2.8 Buffer Registers A and B (BRA, BRB)................................................................ 10.2.9 Timer Control Register (TCR) ............................................................................. 10.2.10 Timer I/O Control Register (TIOR) ..................................................................... 10.2.11 Timer Status Register (TSR) ................................................................................ 10.2.12 Timer Interrupt Enable Register (TIER) .............................................................. 213 213 216 221 222 224 224 226 227 230 231 232 233 234 235 237 239 240 10.3 CPU Interface .................................................................................................................... 10.3.1 16-Bit Accessible Registers.................................................................................. 10.3.2 8-Bit Accessible Registers.................................................................................... 10.4 Description of Operation ................................................................................................... 10.4.1 Overview .............................................................................................................. 10.4.2 Basic Functions .................................................................................................... 10.4.3 Synchronizing Mode ............................................................................................ 10.4.4 PWM Mode .......................................................................................................... 10.4.5 Reset-Synchronized PWM Mode ......................................................................... 10.4.6 Complementary PWM Mode................................................................................ 10.4.7 Phase Counting Mode .......................................................................................... 10.4.8 Buffer Mode ......................................................................................................... 10.4.9 ITU Output Timing .............................................................................................. 10.5 Interrupts............................................................................................................................ 10.5.1 Timing of Setting Status Flags ............................................................................. 10.5.2 Clear Timing of Status Flags................................................................................ 10.5.3 Interrupt Sources and Activating the DMAC....................................................... 10.6 Notes and Precautions........................................................................................................ 10.6.1 Contention between TCNT Write and Clear........................................................ 10.6.2 Contention between TCNT Word Write and Increment ...................................... 10.6.3 Contention between TCNT Byte Write and Increment........................................ 10.6.4 Contention between GR Write and Compare Match............................................ 10.6.5 Contention between TCNT Write and Overflow/Underflow ............................... 10.6.6 Contention between General Register Read and Input Capture ........................... 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment.............................................................................................................. 10.6.8 Contention between General Register Write and Input Capture.......................... 10.6.9 Note on Waveform Cycle Setting ........................................................................ 10.6.10 Contention Between BR Write and Input Capture ............................................... 10.6.11 Note on Writing in the Synchronizing Mode ....................................................... 10.6.12 Note on Setting Reset-synchronized PWM Mode/Complementary PWM Mode .......................................................................................................... 10.6.13 Clearing the Complementary PWM Mode........................................................... 10.6.14 ITU Operating Modes .......................................................................................... 241 241 243 244 244 245 256 258 262 264 272 274 280 281 281 283 284 285 285 286 287 288 289 290 291 292 292 293 294 294 295 295 Section 11 Programmable Timing Pattern Controller (TPC) ............................... 303 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Input/Output Pins.................................................................................................. 11.1.4 Registers ............................................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 303 303 304 305 306 306 306 11.2.2 Port B Data Register (PBDR)............................................................................... 11.2.3 Next Data Register A (NDRA) ............................................................................ 11.2.4 Next Data Register B (NDRB) ............................................................................. 11.2.5 Next Data Enable Register A (NDERA).............................................................. 11.2.6 Next Data Enable Register B (NDERB) .............................................................. 11.2.7 TPC Output Control Register (TPCR) ................................................................. 11.2.8 TPC Output Mode Register (TPMR) ................................................................... 11.3 Operation ........................................................................................................................... 11.3.1 Overview .............................................................................................................. 11.3.2 Output Timing ...................................................................................................... 11.3.3 Examples of Use of Ordinary TPC Output .......................................................... 11.3.4 TPC Output Non-Overlap Operation.................................................................... 11.3.5 TPC Output by Input Capture .............................................................................. 11.4 Usage Notes ....................................................................................................................... 11.4.1 Non-Overlap Operation........................................................................................ 307 308 310 311 312 313 314 316 316 317 317 320 324 325 325 Section 12 Watchdog Timer (WDT) ............................................................................ 327 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Timer Counter (TCNT) ........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Register Access .................................................................................................... 12.3 Operation ........................................................................................................................... 12.3.1 Operation in the Watchdog Timer Mode.............................................................. 12.3.2 Operation in the Interval Timer Mode.................................................................. 12.3.3 Operation in the Standby Mode............................................................................ 12.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 12.4 Usage Notes ....................................................................................................................... 12.4.1 TCNT Write and Count Up Contention ............................................................... 12.4.2 Changing CKS2-CKS0 Bit Values ...................................................................... 12.4.3 Changing Watchdog Timer/Interval Timer Modes .............................................. 12.4.4 System Reset With WDTOVF ............................................................................. 12.4.5 Internal Reset With the Watchdog Timer ............................................................ 327 327 328 328 329 329 329 330 331 333 334 334 336 336 337 337 338 338 338 338 339 339 Section 13 Serial Communication Interface (SCI) .................................................. 341 13.1 Overview............................................................................................................................ 341 13.1.1 Features ................................................................................................................ 341 13.2 13.3 13.4 13.5 13.1.2 Block Diagram...................................................................................................... 13.1.3 Input/Output Pins.................................................................................................. 13.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 13.2.1 Receive Shift Register .......................................................................................... 13.2.2 Receive Data Register .......................................................................................... 13.2.3 Transmit Shift Register ........................................................................................ 13.2.4 Transmit Data Register......................................................................................... 13.2.5 Serial Mode Register ............................................................................................ 13.2.6 Serial Control Register ......................................................................................... 13.2.7 Serial Status Register............................................................................................ 13.2.8 Bit Rate Register (BRR)....................................................................................... Operation ........................................................................................................................... 13.3.1 Overview .............................................................................................................. 13.3.2 Operation in Asynchronous Mode........................................................................ 13.3.3 Multiprocessor Communication ........................................................................... 13.3.4 Clocked Synchronous Operation.......................................................................... SCI Interrupt Sources and the DMAC............................................................................... Usage Notes ....................................................................................................................... 342 343 343 344 344 344 344 345 345 347 351 355 363 363 366 376 384 394 394 Section 14 Pin Function Controller (PFC) ................................................................... 399 14.1 Overview............................................................................................................................ 399 14.2 Register Configuration ...................................................................................................... 401 14.3 Register Descriptions......................................................................................................... 401 14.3.1 Port A I/O Register (PAIOR) ............................................................................... 401 14.3.2 Port A Control Registers (PACR1 and PACR2) .................................................. 402 14.3.3 Port B I/O Register (PBIOR)................................................................................ 407 14.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 408 14.3.5 Column Address Strobe Pin Control Register (CASCR) ..................................... 413 Section 15 Parallel I/O Ports ............................................................................................ 415 15.1 Overview............................................................................................................................ 415 15.2 Port A................................................................................................................................. 415 15.2.1 Register Configuration ......................................................................................... 415 15.2.2 Port A Data Register (PADR) .............................................................................. 416 15.3 Port B ................................................................................................................................. 417 15.3.1 Register Configuration ......................................................................................... 417 15.3.2 Port B Data Register (PBDR)............................................................................... 418 Section 16 ROM .................................................................................................................. 419 16.1 Overview............................................................................................................................ 419 16.2 PROM Mode...................................................................................................................... 421 16.2.1 Setting the PROM Mode ...................................................................................... 421 16.2.2 Socket Adapter Pin Correspondence and Memory Map ..................................... 16. 3 PROM Programming ......................................................................................................... 16.3.1 Selecting the Programming Mode........................................................................ 16.3.2 Write/Verify and Electrical Characteristics.......................................................... 16.3.3 Points to Note About Writing............................................................................... 16.3.4 Reliability After Writing ...................................................................................... 421 423 423 424 428 429 Section 17 RAM .................................................................................................................. 431 17.1 Overview............................................................................................................................ 431 17.2 Operation ........................................................................................................................... 431 Section 18 Power-Down States ...................................................................................... 433 18.1 Overview............................................................................................................................ 18.1.1 Power-Down Modes............................................................................................. 18.1.2 Register................................................................................................................. 18.2 Standby Control Register (SBYCR).................................................................................. 18.3 Sleep Mode........................................................................................................................ 18.3.1 Transition to the Sleep Mode ............................................................................... 18.3.2 Canceling the Sleep Mode.................................................................................... 18.4 S tandby Mode .................................................................................................................... 18.4.1 Transition to the Standby Mode ........................................................................... 18.4.2 Canceling the Standby Mode................................................................................ 18.4.3 Standby Mode Application................................................................................... 433 433 434 434 435 435 435 436 436 438 439 Section 19 Electrical Characteristics ............................................................................ 441 19.1 Absolute Maximum Ratings.............................................................................................. 19.2 DC Characteristics ............................................................................................................. 19.3 AC Characteristics ............................................................................................................. 19.3.1 Clock Timing........................................................................................................ 19.3.2 Control Signal Timing.......................................................................................... 19.3.3 Bus Timing ........................................................................................................... 19.3.4 DMAC Timing ..................................................................................................... 19.3.5 16-bit Integrated Timer Pulse Unit Timing.......................................................... 19.3.6 Programmable Timing Pattern Controller and I/O Port Timing .......................... 19.3.7 Watchdog Timer Timing ...................................................................................... 19.3.8 Serial Communications Interface Timing ............................................................ 19.3.9 AC Characteristics Measurement Conditions ...................................................... 19.4 Usage Note ........................................................................................................................ 441 442 449 449 451 454 490 491 493 494 495 497 498 Appendix A On-Chip Peripheral Module Registers ................................................ 499 A.1 A.2 List of Registers................................................................................................................. 499 Register tables.................................................................................................................... 509 A.2.1 Serial Mode Register (SMR)................................................................................ 509 A.2.2 A.2.3 A.2.4 A.2.5 A.2.6 A.2.7 A.2.8 A.2.9 A.2.10 A.2.11 A.2.12 A.2.13 A.2.14 A.2.15 A.2.16 A.2.17 A.2.18 A.2.19 A.2.20 A.2.21 A.2.22 A.2.23 A.2.24 A.2.25 A.2.26 A.2.27 A.2.28 A.2.29 A.2.30 A.2.31 A.2.32 A.2.33 A.2.34 A.2.35 A.2.36 A.2.37 A.2.38 A.2.39 A.2.40 A.2.41 A.2.42 A.2.43 A.2.44 Bit Rate Register (BRR)....................................................................................... Serial Control Register (SCR).............................................................................. Transmit Data Register (TDR) ............................................................................. Serial Status Register (SSR)................................................................................. Receive Data Register (RDR) .............................................................................. Timer Start Register (TSTR)................................................................................ Timer Synchronization Register (TSNC)............................................................. Timer Mode Register (TMDR) ............................................................................ Timer Function Control Register (TFCR)............................................................ Timer Control Registers 0–4 (TCR0–TCR4) ....................................................... Timer I/O Control Registers 0–4 (TIO0–TIO4)................................................... Timer Interrupt Enable Registers 0–4 (TIER0–TIER4)....................................... Timer Status Registers 0–4 (TSR0–TSR4) .......................................................... Timer Counter 0–4 (TCNT0–TCNT4)................................................................. General Registers A0–4 (GRA0–GRA4) ............................................................. General Registers B0–4 (GRB0–GRB4).............................................................. Buffer Registers A3, A4 (BRA3, BRA4)............................................................. Buffer registers B3, B4 (BRB3, BRB4) ............................................................... Timer Output Control Register (TOCR) .............................................................. DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... DMA Operation Registers (DMAOR) ................................................................. Interrupt Priority Setting Register A (IPRA)........................................................ Interrupt Priority Setting Register B (IPRB)........................................................ Interrupt Priority Setting Register C (IPRC)........................................................ Interrupt Priority Setting Register D (IPRD)........................................................ Interrupt Priority Setting Register E (IPRE) ........................................................ Interrupt Control Register (ICR) .......................................................................... Break Address Register H (BARH) ..................................................................... Break Address Register L (BARL) ...................................................................... Break Address Mask Register H (BAMRH)........................................................ Break Address Mask Register L (BAMRL)......................................................... Break Bus Cycle Register (BBR) ......................................................................... Bus Control Register (BCR) ................................................................................ Wait State Control Register 1 (WCR1)................................................................ Wait State Control Register 2 (WCR2)................................................................ Wait State Control Register 3 (WCR3)................................................................ DRAM Area Control Register (DCR).................................................................. Parity Control Register (PCR).............................................................................. Refresh Control Register (RCR) .......................................................................... Refresh Timer Control/Status Register (RSTCR) ................................................ 510 510 512 512 514 515 515 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 535 536 537 538 539 540 541 542 543 544 545 546 548 549 550 552 553 555 556 557 A.2.45 A.2.46 A.2.47 A.2.48 A.2.49 A.2.50 A.2.51 A.2.52 A.2.53 A.2.54 A.2.55 A.2.56 A.2.57 A.2.58 A.2.59 A.2.60 A.2.61 A.2.62 A.2.63 A.2.64 A.3 Refresh Timer Counter Register (RTCNT).......................................................... Refresh Timer Constant Register (RTCOR) ........................................................ Timer Control/Status Register (TCSR) ................................................................ Timer Counter (TCNT) ........................................................................................ Reset Control/Status Register (RSTCSR) ............................................................ Standby Control Register (SBYCR) .................................................................... Port A Data Register (PADR) .............................................................................. Port B Data Register (PBDR)............................................................................... Port A I/O Register (PAIOR) ............................................................................... Port B Data Register (PBIOR) ............................................................................. Port A Control Register 1 (PACR1)..................................................................... Port A Control Register 2 (PACR2)..................................................................... Port B Control Register 1 (PBCR1) ..................................................................... Port B Control Register 2 (PBCR2) ..................................................................... Column Address Strobe Pin Control Register (CASCR) ..................................... TPC Output Mode Register (TPMR) ................................................................... TPC Output Control Register (TPCR) ................................................................. Next Data Enable Register A (NDERA).............................................................. Next Data Enable Register B (NDERB) .............................................................. Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are the same) ................................................................................ A.2.65 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are the same) ................................................................................ A.2.66 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are different) ................................................................................ A.2.67 Next Data Register A (NDRA) (When the output triggers of TPC output groups 0 and 1 are different) ................................................................................ A.2.68 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are the same) ................................................................................ A.2.69 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are the same) ................................................................................ A.2.70 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are different) ................................................................................ A.2.71 Next Data Register B (NDRB) (When the output triggers of TPC output groups 2 and 3 are different) ................................................................................ Register Status in Reset and Power-Down States.............................................................. 558 559 559 561 561 562 563 564 565 566 567 569 571 573 575 576 577 579 579 580 581 581 582 582 583 584 584 585 Appendix B Pin States ....................................................................................................... 588 Appendix C External Dimensions ................................................................................. 594 Section 1 Overview 1.1 SuperH Microcomputer Features The SuperH microcomputer (SH7000 series) is a new generation reduced instruction set computer (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which strikingly improves instruction execution speed. In addition, the CPU has a 32-bit internal architecture for enhanced data-processing ability. As a result, the CPU enables high-performance systems to be constructed with advanced functionality at low cost, even in applications such as realtime control that require very high speeds, an impossibility with conventional microcomputers. The SH microcomputer includes peripheral functions such as large-capacity ROM, RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an interrupt controller (INTC), and I/O ports. External memory access support functions enable direct connection to SRAM and DRAM. These features can drastically reduce system cost. For on-chip ROM, masked ROM or electrically programmable ROM (PROM) can be selected. The PROM version can be programmed by users with a general-purpose EPROM programmer. Table 1.1 lists the features of the SH microcomputers (SH7020 and SH7021). RENESAS 1 Table 1.1 Features of the SH7020 and SH7021 Microcomputers Feature Description CPU Original Hitachi architecture 32-bit internal data paths General-register machine: • Sixteen 32-bit general registers • Three 32-bit control registers • Four 32-bit system registers RISC-type instruction set: • Instruction length: 16-bit fixed length for improved code efficiency • Load-store architecture (basic arithmetic and logic operations are executed between registers) • Delayed unconditional branch instructions reduce pipeline disruption • Instruction set optimized for C language Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation) Address space: 4 Gbytes available on the architecture On-chip multiplier: multiplication operations (16 bits × 16 bits → 32 bits) executed in 1–3 cycles, and multiplication/accumulation operations (16 bits × 16 bits + 42 bits → 42 bits) executed in 2–3 cycles Five-stage pipeline Operating modes Operating modes: • On-chip ROMless mode • On-chip ROM mode Processing states: • Power-on reset state • Manual reset state • Exception processing state • Program execution state • Power-down state • Bus-released state Power-down states: • Sleep mode • Software standby mode 2 RENESAS Table 1.1 Features of the SH7020 and SH7021 Microcomputers (cont) Feature Description Interrupt controller (INTC) Nine external interrupt pins (NMI, IRQ0–IRQ7) Thirty internal interrupt sources Sixteen programmable priority levels User break controller (UBC) Generates an interrupt when the CPU or DMAC generates a bus cycle with specified conditions Simplifies configuration of a self-debugger Clock pulse generator (CPG) On-chip clock pulse generator (maximum operating frequency: 20 MHz): • 20-MHz pulses can be generated from a 20-MHz crystal with a duty cycle correcting circuit Bus state controller (BSC) Supports external memory access: • Sixteen-bit external data bus Address space divided into eight areas with the following preset features: • Bus size (8 or 16 bits) • Number of wait cycles can be defined by user. • Type of area (external memory area, DRAM area, etc.) — Simplifies connection to ROM, SRAM, DRAM, and peripheral I/O • When the DRAM area is accessed: — RAS and CAS signals for DRAM are output — Tp cycles can be generated to assure RAS precharge time — Address multiplexing is supported internally, so DRAM can be connected directly • Chip select signals (CS0 to CS7) are output for each area DRAM refresh function: • Programmable refresh interval • Supports CAS-before-RAS refresh and self-refresh modes DRAM burst access function: • Supports high-speed access modes for DRAM Wait cycles can be inserted by an external WAIT signal One-stage write buffer improves the system performance Data bus parity can be generated and checked RENESAS 3 Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description Direct memory access controller (DMAC) (4 channels) Permits DMA transfer between the following modules: • External memory • External I/O • On-chip memory • Peripheral on-chip modules (except DMAC) DMA transfer can be requested from external pins, on-chip SCI, onchip timers, and on-chip A/D converter Cycle-steal mode or burst mode Channel priority level is selectable Channels 0 and 1: dual or single address transfer mode is selectable; external request sources are supported; Channels 2 and 3: dual address transfer mode, internal request sources only 16-bit integrated-timer pulse unit (ITU) Ten types of waveforms can be output Input pulse width and cycle can be measured PWM mode: pulse output with 0–100% duty cycle (maximum resolution: 50 ns) Complementary PWM mode: can output a maximum of three pairs of non-overlapping PWM waveforms Phase counting mode: can count up or down according to the phase of an external two-phase clock Timing pattern controller (TPC) Maximum 16-bit output (4 bits × 4 channels) can be output Non-overlap intervals can be established between pairs of waveforms Timing-source timer is selectable Watchdog timer (WDT) (1 channel) Can be used as watchdog timer or interval timer Timer overflow can generate an internal reset, external signal, or interrupt Power-on reset or manual reset can be selected as the internal reset Serial communication Asynchronous or clocked synchronous mode is selectable interface (SCI) (2 channels) Can transmit and receive simultaneously (full duplex) On-chip baud rate generator in each channel Multiprocessor communication function 4 RENESAS Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): • Port A: 16 input/output lines (input or output can be selected for each bit) • Port B: 16 input/output lines (input or output can be selected for each bit) On-chip memory SH7020: 16-kbyte masked ROM, and 1-kbyte RAM SH7021: 32-kbyte electrically programmable ROM or masked Rom, and 1-kbyte RAM 32-bit data can be accessed in one clock cycle RENESAS 5 ROMless ROM masked PROM 6 RENESAS SH7020 masked SH7021 ROM On-Chip ROM HD6437021X HD6437021XI HD6437021VX HD6437021VXI HD6477021X HD6477021XI HD6477021VX HD6477021VXI HD6437020X HD6437020XI HD6437020VX HD6437020VXI HD6417020SX20I HD6417020SVX12I -20 to +75 °C -40 to +85 °C -20 to +75 °C -40 to +85 °C -20 to +75 °C -40 to +85 °C -20 to +75 °C -40 to +85 °C -20 to +75 °C -40 to +85 °C -20 to +75 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C 2 to 20MHz 2 to 16.6MHz 2 to 20MHz 2 to 12.5MHz 3.3V 2 to 12.5MHz 2 to 16.6MHz 2 to 20MHz 2 to 12.5MHz 2 to 12.5MHz 2 to 16.6MHz 2 to 20MHz Model Operating temperature Operating Frequency 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V Operating Voltage Product Line Product Number Table 1.2 HD6417020VX12I HD6417020X20I HD6437020VTEI HD6437020VTE HD6437020TEI HD6437020TE HD6477021VTEI HD6477021VTE HD6477021TEI HD6477021TE HD6437021VTEI HD6437021VTE HD6437021TEI HD6437021TE Marking Model No. (TFP-100B) plastic TQFP 100-pin Package Address RES(Vpp)*2 WDTOVF MD2 MD1 MD0 NMI CK EXTAL XTAL VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVref AVCC AVSS PROM or masked ROM*1 Serial communication interface (2 channels) Programmable timing pattern controller 16-bit integrated-timer pulse unit Watchdog timer PB15/TP15/IRQ7 PB14/TP14/IRQ6 PB13/TP13/IRQ5/SCK1 PB12/TP12/IRQ4/SCK0 PB11/TP11/TxD1 PB10/TP10/RxD1 PB9/TP9/TxD0 PB8/TP8/RxD0 PB7/TP7/TOCXB4/TCLKD PB6/TP6/TOCXA4/TCLKC PB5/TP5/TIOCB4 PB4/TP4/TIOCA4 PB3/TP3/TIOCB3 PB2/TP2/TIOCA3 PB1/TP1/TIOCB2 PB0/TP0/TIOCA2 : Peripheral data bus (16 bits) : Internal address bus (24 bits) ;;;;; ;;;;; : Internal upper data bus (16 bits) ;;;;; ;;;;; : Internal lower data bus (16 bits) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Bus state controller Port B : Peripheral address bus (24 bits) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (HBS) RAM*1 ;;;; ;; ;; ;; ;; ;;;; ;;;; ;; ;; ;; ;; ;; ;; ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; ;;;; ;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Direct ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; memory ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;; ;;;;; CPU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;; ;;;;; access ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;; ;;;; controller ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; User Interrupt break controller controller Address CS3/CASL CS2 CS1/CASH CS0 A21 A20 A19 A18 A17 A16 Port A Data/address PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TIOCB1 PA10/DPL/TIOCA1 PA9/AH/IRQOUT/ADTRG PA8/BREQ PA7/BACK PA6/RD PA5/WRH (LBS) PA4/WRL (WR) PA3/CS7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 Block Diagram Clock pulse generator 1.2 Notes: *1. SH7020: 16-kbyte masked ROM and 1-kbyte RAM. SH7021: 32-kbyte PROM or Masked ROM and 1-kbyte RAM. *2. Vpp: SH7021 (PROM version) Figure 1.1 Block Diagram RENESAS 7 Pin Descriptions 1.3.1 Pin Arrangement TFP-100B (Top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A5 A6 A7 A8 A9 A10 VSS A11 A12 A13 A14 A15 VCC A16 A17 VSS A18 A19 A20 A21 CS0 CS1/CASH CS2 CS3/CASL VSS AD0 AD1 AD2 VSS AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 VCC AD11 VSS AD12 AD13 AD14 AD15 A0(HBS) A1 A2 A3 VSS A4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB15/TP15/IRQ7 PB14/TP14/IRQ6 PB13/TP13/IRQ5/SCK1 PB12/TP12/IRQ4/SCK0 PB11/TP11/TxD1 PB10/TP10/RxD1 PB9/TP9/TxD0 PB8/TP8/RxD0 VSS PB7/TP7/TOCXB4/TCLKD PB6/TP6/TOCXA4/TCLKC PB5/TP5/TIOCB4 VCC PB4/TP4/TIOCA4 PB3/TP3/TIOCB3 PB2/TP2/TIOCA3 PB1/TP1/TIOCB2 PB0/TP0/TIOCA2 VSS VSS VCC MD2 MD1 MD0 RES(Vpp)* 1.3 Notes: Vpp: SH7021 (PROM version) Figure 1.2 Pin Arrangement 8 RENESAS WDTOVF NMI VCC XTAL EXTAL VSS CK PA15/IRQ3/DREQ1 PA14/IRQ2/DACK1 PA13/IRQ1/DREQ0/TCLKB PA12/IRQ0/DACK0/TCLKA PA11/DPH/TICOB1 VCC PA10/DPL/TIOCA1 PA9/AH/IRQOUT PA8/BREQ VSS PA7/BACK PA6/RD PA5/WRH(LBS) PA4/WRL(WR) PA3/CA7/WAIT PA2/CS6/TIOCB0 PA1/CS5/RAS PA0/CS4/TIOCA0 1.3.2 Pin Functions Table 1.3 describes the pin functions. Table 1.3 Pin Functions Type Symbol Pin No. I/O Name and Function Power VCC 13, 38, 63, 73, 80, 88 I Power: Connected to the power supply. Connect all VCC pins to the system power supply . The chip will not operate if any VCC pin is left unconnected. VSS 4, 15, 24, 32, 41, 50, 59, 70, 81, 82, 92 I Ground: Connected to ground. Connect all V SS pins to the system ground. The chip will not operate if any VSS pin is left unconnected. VPP 76* I RES pin in the MCU mode. Apply +12.5V when programming the PROM in the SH7021 (PROM version). EXTAL 71 I Crystal/external clock: Connected to a crystal resonator or external clock input having the same frequency as the system clock (CK). XTAL 72 I Crystal: Connected to a crystal resonator with the same frequency as the system clock (CK). If an external clock is input at the EXTAL pin, leave XTAL open. CK 69 O System clock: Supplies the system clock (CK) to peripheral devices. RES 76 I Reset: Low input causes a power-on reset if NMI is high, or a manual reset if NMI is low. WDTOVF 75 O Watchdog timer overflow: Overflow output signal from the watchdog timer. BREQ 60 I Bus request: Driven low by an external device to request the bus ownership. BACK 58 O Bus request acknowledge: Indicates that bus ownership has been granted to an external device. By receiving the BACK signal, a device that has sent a BREQ signal can confirm that it has been granted the bus. Clock System control Note: Pin 76 is RES in the SH7020, SH7021 (Masked ROM version) and Vpp in the SH7021 (PROM version). RENESAS 9 Table 1.3 Type Pin Functions (cont) Symbol Operating MD2, mode MD1, control MD0 Pin No. I/O Name and Function 79–77 I Mode select: Selects the operating mode. Do not change these inputs while the chip is operating. The following table lists the possible operating modes and their corresponding MD2–MD0 values. Operating MD2 MD1 MD0 Mode Interrupts 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MCU mode On-chip ROM Bus Size in Area 0 Disabled 8 bits 16 bits Enabled* 1 (Reserved) PROM mode* 2 NMI 74 I Nonmaskable interrupt: Nonmaskable interrupt request signal. The rising or falling edge can be selected for signal detection. IRQ0– IRQ7 65–68, I Interrupt request 0–7: Maskable interrupt request signals. Level input or edge-triggered input can be selected. IRQOUT 61 O Slave interrupt request output: Indicates occurrence of an interrupt while the bus is released. Address bus A21–A0 45–42, 40, O 39, 37–33, 31–25, 23–20 Address bus: Outputs addresses. Data bus AD15– AD0 19–16, 14, I/O 12-5, 3–1 Data bus: 16-bit bidirectional data bus that is multiplexed with the lower 16 bits of the address bus. DPH 64 I/O Upper data bus parity: Parity data for D15–D8. DPL 62 I/O Lower data bus parity: Parity data for D7–D0. WAIT 54 I Wait: Requests the insertion of wait states (T W ) into the bus cycle when the external address space is accessed. Bus control 97–100 Notes : 1.Use prohibited in the SH7020 Romless version. 2.Can only be used in the SH7021 ZTAT version. 10 RENESAS Table 1.3 Pin Functions (cont) Type Symbol Pin No. I/O Name and Function Bus control RAS 52 O Row address strobe: DRAM row-address strobe-timing signal. (cont) CASH 47 O Column address strobe high: DRAM column-address strobe-timing signal outputs low level to access the upper eight data bits. CASL 49 O Column address strobe low: DRAM column-address strobe-timing signal outputs low level to access the lower eight data bits. RD 57 O Read: Indicates reading of data from an external device. WRH 56 O Upper write: Indicates write access to the upper eight bits of an external device. WRL 55 O Lower write: Indicates write access to the lower eight bits of an external device. CS0–CS7 46–49, 51–54 O Chip select 0–7: Chip select signals for accessing external memory and devices. AH 61 O Address hold: Address hold timing signal for a device using a multiplexed address/data bus. O Upper/lower byte strobe: Upper and lower byte strobe signals. (Also used as WRH and A0.) HBS, LBS 20, 56 DMAC 16-bit integratedtimer pulse unit (ITU) WR 55 O Write: Brought low during write access. (Also used as WRL.) DREQ0, DREQ1 66, 68 I DMA transfer request (channels 0 and 1): Input pins for external DMA transfer requests. DACK0, DACK1 65, 67 O DMA transfer acknowledge (channels 0 and 1): Indicates that DMA transfer is acknowledged. TIOCA0, TIOCB0 51, 53 I/O ITU input capture/output compare (channel 0): Input capture or output compare pins. TIOCA1, TIOCB1 62, 64 I/O ITU input capture/output compare (channel 1): Input capture or output compare pins. TIOCA2, TIOCB2 83, 84 I/O ITU input capture/output compare (channel 2): Input capture or output compare pins. TIOCA3, TIOCB3 85, 86 I/O ITU input capture/output compare (channel 3): Input capture or output compare pins. TIOCA4, TIOCB4 87, 89 I/O ITU input capture/output compare (channel 4): Input capture or output compare pins. RENESAS 11 Table 1.3 Pin Functions (cont) Type Symbol Pin No. I/O Name and Function 16-bit integratedtimer pulse unit (ITU) TOCXA4, TOCXB4 90, 91 O ITU output compare (channel 4): Output compare pins. TCLKA– TCLKD 65, 66, 90, 91 I ITU timer clock input: External clock input pins for ITU counters. Timing pattern controller (TPC) TP15– TP0 100–93, 91–89, 87–83 O Timing pattern output 15–0: Timing pattern output pins. Serial communication interface (SCI) TxD0, TxD1 94, 96 O Transmit data (channels 0 and 1): Transmit data output pins for SCI0 and SCI1. RxD0, RxD1 93, 95 I Receive data (channels 0 and 1): Receive data input pins for SCI0 and SCI1. SCK0, SCK1 97, 98 I/O Serial clock (channels 0 and 1): Clock input/output pins for SCI0 and SCI1. PA15– PA0 68–64, 62–60, 58-51 I/O Port A: 16-bit input/output pins. Input or output can be selected individually for each bit. PB15– PB0 100–93, 91–89, 87–83 I/O Port B: 16-bit input/output pins. Input or output can be selected individually for each bit. I/O ports 12 RENESAS 1.3.3 Pin Layout by Mode Table 1.4 shows pin layout by mode Table 1.4 Pin Layout by Mode MCU Mode PROM Mode (SH7021PROM version) Pin No. MCU Mode PROM Mode (SH7021PROM version) 1 AD0 AD0 29 A8 A8 2 AD1 AD1 30 A9 OE 3 AD2 AD2 31 A10 A10 4 Vss Vss 32 VSS VSS 5 AD3 AD3 33 A11 A11 6 AD4 AD4 34 A12 A12 7 AD5 AD5 35 A13 A13 8 AD6 AD6 36 A14 A14 9 AD7 AD7 37 A15 A15 10 AD8 NC 38 VCC VCC 11 AD9 NC 39 A16 A16 12 AD10 NC 40 A17 VCC 13 VCC VCC 41 VSS VSS 14 AD11 NC 42 A18 VCC 15 VSS VSS 43 A19 NC 16 AD12 NC 44 A20 NC 17 AD13 NC 45 A21 NC 18 AD14 NC 46 CS0 NC 19 AD15 NC 47 CS1/CASH NC 20 A0(HBS) A0 48 CS2 NC 21 A1 A1 49 CS3/CASL NC 22 A2 A2 50 VSS VSS 23 A3 A3 51 PA0/CS4/TIOCA0 NC 24 VSS VSS 52 PA1/CS5/RAS NC 25 A4 A4 53 PA2/CS6/ TIOCB0 PGM 26 A5 A5 54 PA3/CS7/WAIT CE 27 A6 A6 55 PA4/WRL(WR) NC 28 A7 A7 56 PA5/WRH(LBS) NC Pin No. RENESAS 13 Table 1.3.3 Pin Layout by Mode (cont) MCU Mode PROM Mode (SH7021PROM version) Pin No. MCU Mode PROM Mode (SH7021PROM version) 57 PA6/RD NC 80 VCC VCC 58 PA7/BACK NC 81 VSS VSS 59 VSS VSS 82 VSS VSS 60 PA8/BREQ NC 83 PB0/TP0/TIOCA2 NC 61 PA9/AH/IRQOUT NC 84 PB1/TP1/TIOCB2 NC 62 PA10/DPL/TIOCA1 NC 85 PB2/TP2/TIOCA3 NC 63 VCC VCC 86 PB3/TP3/TIOCB3 NC 64 PA11/DPH/TIOCB1 NC 87 PB4/TP4/TIOCA4 NC 65 PA12/IRQ0/DACK0/ NC Pin No. TCLKA 66 88 VCC VCC 89 PB5/TP5/TIOCB4 NC PB6/TP6/TOCXA4/ TCLKC NC PB7/TP7/TOCXB4/ NC PA13/IRQ1/DREQ0/ TCLKLB NC 90 91 67 PA14/IRQ2/DACK1 NC 68 PA15/IRQ3/DREQ1 NC 69 CK NC 92 VSS VSS 70 VSS VSS 93 PB8/TP8/RxD0 NC 71 EXTAL NC 94 PB9/TP9/TxD0 NC 72 XTAL NC 95 PB10/TP10/RxD1 NC 73 VCC VCC 96 PB11/TP11/TXD1 NC 74 NMI A9 97 PB12/TP12/IRQ4/ NC TCLKD SCK0 75 WDTOVF NC 76 RES Vpp 77 MD0 VCC 78 MD1 VCC 99 PB14/TP14/IRQ6 NC 79 MD2 VCC 100 PB15/TP15/IRQ7 NC 14 RENESAS 98 PB13/TP13/IRQ5/ NC SCK1 Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data processing and address calculation. Register R0 also functions as an index register. For some instructions, the R0 register must be used. Register R15 functions as a stack pointer to save or recover status registers (SR) and program counter (PC) during exception processing. 31 0 R0 R1 R2 R3 R4 R0 functions as an index register in the indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a source register or a destination register. R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP R15 functions as a stack pointer (SP) during exception processing. Figure 2.1 General Registers (Rn) 2.1.2 Control Registers Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register RENESAS15 functions as a base address for the indirect GBR addressing mode to transfer data to the registers of peripheral on-chip modules. The vector base register functions as the base address of the exception processing vector area including interrupts. 9 8 7 6 5 4 32 1 0 31 SR M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP, TAS, TST, BT, BF, SETT, and CLRT instructions use the T bit to indicate a true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I0–I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. 31 GBR 31 VBR Global base register (GBR): 0 Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used to transfer data to the register areas peripheral on-chip modules. 0 Vector base register (VBR): Stores the base address of the exception processing vector area. Figure 2.2 Control Registers 2.1.3 System Registers System registers consist of four 32-bit registers: multiply and accumulate registers high and low (MACH and MACL), procedure register (PR), and program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. 16 RENESAS 31 9 (sign extended) 0 MACH MACL 0 31 PR 0 31 PC Multiply and accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply and accumulate operations. MACH is sign-extended when read because only the lowest 10 bits are valid. Procedure register (PR): Stores a return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. Figure 2.3 System Registers 2.1.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Classification Register Initial Value General register R0–R14 Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I0-I3 are 1111(H'F), reserved bits are 0, and other bits are undefined GBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Control register System register 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always long words (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a long word when stored into a register (figure 2.4). RENESAS17 31 0 Long word Figure 2.4 Data Format in Registers 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and long words. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or long word data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, which is referred to by the hardware stack pointer (SP, R15), uses only long word data starting from address 4n because this area stores the program counter and status register (figure 2.5). Address m + 1 Address m 23 31 Address m + 3 Address m + 2 7 15 0 7 Byte 0 7 Byte 0 7 Byte 0 7 Byte 0 Address 2n 15 Address 4n 31 Word 0 15 Word Long word 0 0 Figure 2.5 Data Format in Memory 2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as long word data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and is handled as long word data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or long word immediate data is not located in the instruction code but rather is stored in a memory table. The memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. 18 RENESAS 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. Their features are as follows: 16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more efficient. One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system. One-cycle instructions are executed in 50 ns at 20 MHz. Data Length: Long word is the standard data length for all operations. Memory can be accessed in bytes, words, or long words. Byte or word data accessed from memory is sign-extended and handled as long word data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations (handled as long word data). Table 2.2 Sign Extension of Word Data CPU of SH7000 Series Description Conventional CPUs MOV.W @(disp,PC),R1 ADD R1,R0 ...................... .. .DATA.W H'1234 Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. ADD.W #H'1234, R0 Note: The address of the immediate data is accessed by @(disp, PC). Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption during branching is reduced by first executing the instruction that follows the branch instruction, and then branching. See the SH-1/SH-2 Programming Manual for details. Table 2.3 Delayed Branch Instructions CPU of SH7000 Series Description Conventional CPU BRA ADD Executes an ADD before branching to TRGET. ADD.W BRA TRGET R1, R0 R1, R0 TRGET Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip multiplier enable 16-bit × 16-bit → 32-bit multiplication operations to be executed in 1–3 cycles. 16-bit × 16-bit + 42-bit → 42-bit multiplication/accumulation operations can be executed in 2–3 RENESAS19 cycles. T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the condition (True/False) that determines if the program will branch. The T bit in the status register is only changed by selected instructions, thus improving the processing speed. Table 2.4 T bit CPU of SH7000 Series Description Conventional CPU CMP/GE R1, R0 BT TRGET0 BF TRGET1 T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 refresh > DMAC > CPU Thus, an external device has priority when it generates a bus request, even when the DMAC is doing a burst transfer. Note that when a refresh request is generated while the bus is released to an external device, BACK becomes high level and the bus right can be acquired to perform the refresh upon receipt of a BREQ = high level response from the external device. Input all bus requests from external devices to the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 8.35 illustrates the bus release procedure. RENESAS 157 External device SuperH BREQ = low Bus request BREQ received Strobe pin: High-level output Address, data, strobe pin: High impedance BACK = low Bus release response BACK acknowledge Bus acquisition Bus released Figure 8.35 Bus Release Procedure 8.10.1 The Operation of Bus Arbitration This LSI has the bus arbitration function which can give bus ownership to an external device when the device requests the bus ownership. When BREQ is input and the bus cycle being executed by the CPU or DMAC is completed, BACK becomes low and a bus is released for an external device. At this time, the following operates when bus arbitration conflicts with refresh. 1. If DRAM refresh is requested in this LSI when a bus is released and BACK is low, BACK becomes high and the occurrence of the refresh request can be informed externally. At this time, the external device may generate a bus cycle when BREQ is low even if BACK is high. Therefore, a bus remains released to the external device. Then, when BREQ becomes high, this LSI gets bus ownership, and executes refresh and the bus cycle of the CPU or DMAC. After the external device gets bus ownership and BACK is low, refresh is requested when BACK becomes high even if the low level of BREQ is input. Therefore, turn BREQ high immediately to release a bus for this LSI to hold DRAM data (See figure 8.36). 2. When BREQ changes from high to low and internal refresh is requested at the timing of the bus release of this LSI, BACK may remain high (do not become low). A bus is released to the external device since the low level of BREQ is input. This operation is based on the above specification (1). To hold DRAM data, turn BREQ high and release a bus to this LSI immediately when the external device detects that BACK does not change to low during a fixed time this LSI (See figure 8.37). When a refresh request is generated and BACK returns to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where BACK was originally supposed to become low. 158 RENESAS BREQ BACK Refresh execution Refresh damand Figure 8.36 BACK Operation by Refresh Demand (1) If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level. BREQ BACK BACK does not go low. Refresh request Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release. Figure 8.37 BACK Operation in Response to Refresh Request (2) 8.10.2 BACK Operation 1. BACK Operation When an internal refresh is requested during an attempt to assert the BACK signal and BACK is not asserted but remains high, a momentary narrow pulse-shaped spike may be output, as shown below. BREQ BACK pulse width of the spike is approx. 2 to 5 ns. Refresh demand RENESAS 159 2. Countermeasure against a spike on the BACK signal The following describes the countermeasure against a spike on the BACK signal: a. When BREQ is input to release the bus of the LSI, make sure that conflicts with a refresh operation do not occur. Stop the refresh operation or operate the refresh timer counter (RTCNT) or the refresh time constant register (RTCOR) of the bus controller (BSC) to shift the refresh timing. b. The spike on the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which can be eliminated by using a capacitor as shown in the figure below. For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike above 2.0 V. Note that delay of the BACK signal increases approximately in units of 0.1 ns/pF. (When a capacitance of 220 pF is added, the delay increases approximately by 22 ns. BACK C SuperH Microcomputer Capacitor-incorporating circuit for eliminating a spike c. Latching the BACK signal by using a flip-flop or triggering the flip-flop may be successful or unsuccessful due to the narrow pulse width of the spike. Implement a circuit configuration which will cause no problems when latching BACK or using BACK as a trigger signal. When splitting the BACK signal into two signals and latching each of them using the flipflop or triggering the flip-flop, the flip-flop may operate for one signal but may not for another. To capture the BACK signal using the flip-flop, receive the BACK signal using a single flip-flop then distribute the signal (see figure below). 160 RENESAS Trigger OK D Q BACK Q Trigger NG D Q BACK Q D Q Q 8.11 Usage Notes 8.11.1 Usage Notes on Manual Reset Condition: When DRAM (long-pitch mode) is used and manual reset is performed. The low width of RAS output may be shorter than usual in rese + (2.5tcyc→1.5tcyc), causing the specified value (tRAS) of DRAM not to be satisfied. Corresponding DRAM conditions: long pitch/normal mode long pitch/high-speed page mode There are no problems regarding operations except for the above conditions. There are the following four cases (Figure 8.38 to Figure 8.41) for the output states of DRAM control signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown by solid lines (not by dashed lines). RENESAS 161 Tp RES latch timing Tr Tc1 Tc2 CK Manual reset RES A0 to A21 Row address Colum address FFFF RAS CAS WR AD0 to AD15 Data output Figure 8.38 Long - pitch Mode Write (1) Tp RES latch timing Tr Tc1 CK RES A0 to A21 Manual reset Row address FFFF RAS CAS WR AD0 to AD15 Data output Figure 8.39 Long - pitch Mode Write (2) 162 RENESAS Tc2 RES latch timing Tp Tr Tc1 Tc2 CK Manual reset RES A0 to A21 Row address Colum address FFFF RAS CAS RD Figure 8.40 Long - pitch Mode Read (1) Tp RES latch timing Tr Tc1 Tc2 CK RES A0 to A21 Manual reset Row address FFFF RAS CAS RD Figure 8.41 Long - pitch Mode Read (2) For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM data must be held after reset, take one of the coutermeasures described as follows. 1. When resetting manually, do this in watchdog timer (WDT) condition. 2. Even if the Low width of RAS becomes as short as 1.5 tcyc as shown above, use with a frequency that satisfies the DRAM standard (tRAS). 3. Even in case the Low width of RAS has become 1.5 tcyc, proceed by using the external circuit so that a RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the DRAM). RENESAS 163 The countermeasures are not required when DRAM data is initialized or loaded again after manual reset. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL The following specifies the setup time tDS of the parity dada DPH and DPL to CAS signal rising when the parity dada DPH and DPL are written to DRAM in long-pitch mode (early write). Table 8.12 Setup Time of Parity Data DPH and DPL Item Symbol min tDS –5 ns Data setup time to CAS (for only DPH and DPL in long-pitch mode) Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the WRH and WRL signals of this LSI and write with delayed writing. Nomal dada is also delayed-written, causing no problems. SuperH RAS RAS Microcomputer CAS CAS OE RD *1 WRH or WRL CK *1 D *2 Q Q DWRH or DWRL WE *1: For preventing signal racing *2: Negative edge latch Figure 8.42 Delayed-Write Control Circuit 8.11.3 Maximum Number of States from BREQ Input to Bus Release The maximum number of states from BREQ input to bus release is: Maximum number of states for which bus is not released + approx. 4.5 states Note: Breakdown of approx. 4.5 states: 1.5 states: Until BACK output after end of bus cycle 1 state (min.): tBACD1 1 state (max.): tBRQS 1 state: Sampling in 1 state before end of bus cycle 164 RENESAS DRAM BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43. The maximum number of states from BREQ input to bus release are used when B is a cycle comprising the maximum number of states for which the bus is not released; the number of states is the maximum number of states for which bus is not released + approx. 4.5 states. The maximum number of states for which the bus is not released requires careful investigation. CK Bus cycle A B BREQ tBACD1 tBRQS BACK Bus release Figure 8.43 When BREQ is Input without Satisfying tBRQS 1. Cycles in which bus is not released (a) One bus cycle The bus is never released during one bus cycle. For example, in the case of a longword read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit ordinary space, as shown in figure 8.44. The bus is not released between these accesses. Assuming one memory access to require 2 states, the bus is not released for a period of 8 states. 8 bits 8 bits 8 bits 8 bits Cycle during which bus is not released Figure 8.44 One Bus Cycle (b) TAS instruction read cycle and write cycle The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45). The TAS instruction read cycle and write cycle should be regarded as one bus cycle during which the bus is not released. RENESAS 165 Read cycle Write cycle Cycle during which bus is not released (1 bus cycle) Figure 8.45 TAS Instruction Read Cycle and Write Cycle (c) Refresh cycle + bus cycle The bus is never released during a refresh cycle and the following bus cycle ((a) or (b) above)) (figure 8.46). Refresh cycle 1 bus cycle Cycle during which bus is not released Figure 8.46 Refresh Cycle and Following Bus Cycle 166 RENESAS 2. Bus release procedure The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7020 and SH7021, the bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). CK tBRQS tBRQS BREQ tBACD1 tBACD1 BACK tBZD RD, WR RAS, CAS CSn tBZD A21 to A0 Bus cycle Bus release Strobe pin: high-level output Bus cycle Address & data strobe pins: high impedance The bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). Bus cycle restart Figure 8.47 Bus Release Procedure RENESAS 167 Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SuperH microprocomputer chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, on-chip memory and on-chip peripheral modules (excluding the DMAC itself). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. 9.1.1 Features The DMAC has the following features. • • • • • • Four channels Four Gbytes of address space on the architecture Byte or word selectable data transfer unit 65536 transfers (maximum) Single address mode transfers (channels 0 and 1): Either the transfer source or transfer destination (peripheral device) is accessed by a DACK signal (selectable) while the other is accessed by address. 1 transfer unit of data is transferred in each bus cycle. Device combinations able to transfer:  External devices with DACK and memory-mapped external devices (including external memories)  External devices with DACK and memory-mapped external memories Dual address mode transfer: (channels 0–3): Both the transfer source and transfer destination are accessed by address. 1 transfer unit of data is transferred in 2 bus cycles. Device combinations able to transfer:  Two external memories  External memory and memory-mapped external devices  Two memory-mapped devices  External memory and on-chip memory  Memory-mapped external devices and on-chip peripheral module (excluding the DMAC itself)  External memory and on-chip memory  Memory-mapped external device and on-chip peripheral module (excluding the DMAC)  Two on-chip memories  On-chip memory and on-chip peripheral modules (excluding DMAC) RENESAS 169 • • • • •  Two on-chip peripheral modules (excluding DMAC) Transfer requests  External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level)  Requests from on-chip peripheral modules (serial communications interface (SCI), and 16bit integrated-timer pulse unit (ITU))  Auto-request (the transfer request is generated automatically within the DMAC) Selectable bus modes: Cycle-steal mode or burst mode Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes CPU can be asked for interrupt when data transfer ends Maximum transfer rate  20 M words/s (320 MB/s) For 5V and 20 MHz Bus mode: Burst mode Transmit size: Word 9.1.2 Block Diagram Figure 9.1 is a block diagram of the DMAC. 170 RENESAS On-chip ROM On-chip RAM On-chip peripheral module SARn Register control DREQ0, DREQ1 ITU SCI Start-up control TCRn CHCRn DMAC module bus Iteration control Internal bus Peripheral bus DARn DMAOR Request priority control DACK0, DACK1 DEIn External RAM External device (memory mapped) External device (with acknowledge) External bus External ROM Bus interface Bus controller DMAC DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination address register TCRn: DMA transfer count register CHCRn: DMA channel control register DEIn: DMA transfer-end interrupt request to CPU. n: 0–3 Figure 9.1 DMAC Block Diagram RENESAS 171 9.1.3 Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Channel Name Symbol I/O Function 0 DMA transfer request DREQ0 I DMA transfer request input from external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to external device DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device 1 172 RENESAS 9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels Table 9.2 DMAC Registers Channel Name Abbreviation R/W Initial Value 0 DMA source address register 0 SAR0*3 R/W Undefined H'5FFFF40 16, 32 DMA destination address register 0 DAR0* 3 R/W Undefined H'5FFFF44 16, 32 DMA transfer count register 0 TCR0*3 R/W Undefined H'5FFFF4A 16, 32 DMA channel control register 0 CHCR0 R/(W)*1 H'0000 DMA source address register 1 SAR1*3 R/W Undefined H'5FFFF50 16, 32 DMA destination address register 1 DAR1* 3 R/W Undefined H'5FFFF54 16, 32 DMA transfer count register 1 TCR1*3 R/W Undefined H'5FFFF5A 16, 32 DMA channel control register 1 CHCR1 R/(W)*1 H'0000 DMA source address register 2 SAR2*3 R/W Undefined H'5FFFF60 16, 32 DMA destination address register 2 DAR2* 3 R/W Undefined H'5FFFF64 16, 32 DMA transfer count register 2 TCR2*3 R/W Undefined H'5FFFF6A 16, 32 DMA channel control register 2 CHCR2 R/(W)*1 H'0000 DMA source address register 3 SAR3*3 R/W Undefined H'5FFFF70 16, 32 DMA destination address register 3 DAR3* 3 R/W Undefined H'5FFFF74 16, 32 DMA transfer count register 3 TCR3*3 R/W Undefined H'5FFFF7A 16, 32 CHCR3 R/(W)*1 H'0000 H'5FFFF7E 8, 16, 32 DMAOR R/(W)*2 H'0000 H'5FFFF48 1 2 3 DMA channel control register 3 Shared DMA operation register Address Access Size H'5FFFF4E 8, 16, 32 H'5FFFF5E 8, 16, 32 H'5FFFF6E 8, 16, 32 8, 16, 32 Notes: 1. Write 0 alone in bit 1 of CHCR0–CHCR3 to clear flags. 2. Write 0 alone in bits 1 and 2 of the DMAOR to clear flags. 3. Access SAR0–SAR3, DAR0–DAR3, and TCR0–TCR3 by long word or word. If byte access is used when writing, the value of the register contents becomes undefined; if used when reading, the value read is undefined. RENESAS 173 9.2 Register Descriptions 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address (in single-address mode, SAR is ignored in transfers from external devices with DACK to memory-mapped external devices or external memory). The initial value after resets or in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 Bit name: Initial value: R/W: Bit: … Bit name: Initial value: R/W: 9.2.2 0 … — — — — … — R/W R/W R/W R/W … R/W DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address (in single-address mode, DAR is ignored in transfers from memorymapped external devices or external memory to external devices with DACK). The initial value after resets or in standby mode is undefined. Bit: 31 30 29 28 27 26 25 24 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 174 RENESAS … 0 … — — — — … — R/W R/W R/W R/W … R/W 9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMA transfer count registers 0-3 (TCR0–TCR3) are 16-bit read/write registers that specify the DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001, 65535 when the setting is H'FFFF and 65536 (the maximum) when H'0000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The initial value after resets or in standby mode is undefined. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 9.2.4 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) are 16-bit read/write registers that control the DMA transfer mode. They also indicate DMA transfer status. They are initialized to H'0000 by a reset or standby mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 AM AL DS TM TS IE TE DE 0 0 0 0 0 0 0 0 R/(W)*2 R/(W)*2 R/(W)*2 R/W R/W R/W R/(W)* R/W Notes: 1. Write only 0 to clear the flag. 2. Writing is effective only for CHCR0 and CHCR1. RENESAS 175 • Bits 15 and 14 (destination address mode bits 1, 0 (DM1 and DM0)): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed (in the single address mode, DM1 and DM0 are ignored when transfers are made from memory-mapped external devices or external memory to external devices with DACK). DM1 and DM0 are initialized to 00 by resets or in standby mode. Bit 15: DM1 Bit 14: DM0 Description 0 0 Fixed destination address (initial value) 0 1 Destination address is incremented (+1 or +2 depending on if the transfer size is word or byte) 1 0 Destination address is decremented (–1 or –2 depending on if the transfer size is word or byte) 1 1 Reserved (illegal setting) • Bits 13 and 12 (source address mode bits 1, 0 (SM1 and SM0)): SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed (in the single address mode, SM1 and SM0 are ignored when transfers are made from external devices with DACK to memory-mapped external devices or external memory). SM1 and SM0 are initialized to 00 by resets or in standby mode. Bit 13: SM1 Bit 12: SM0 Description 0 0 Fixed source address (initial value) 0 1 Source address is incremented (+1 or +2 depending on if the transfer size is word or byte) 1 0 Source address is decremented (–1 or –2 depending on if the transfer size is word or byte) 1 1 Reserved (illegal setting) • Bits 11–8 (resource select bits 3–0 (RS3-RS0)): RS3–RS0 specify which transfer requests will be sent to the DMAC. Do not change the transfer request source unless the DMA enable bit (DE) is 0. The RS3–RS0 bits are initialized to 0000 by resets or in standby mode. 176 RENESAS Bit 11: RS3 Bit 10: RS2 Bit 9: RS1 Bit 8: RS0 Description 0 0 0 0 DREQ (External request*1, dual address mode) (initial value) 0 0 0 1 Reserved (illegal setting) 0 0 1 0 DREQ (External request*1, single address mode* 2) 0 0 1 1 DREQ (External request*1, single address mode* 3) 0 1 0 0 RXI0 (On-chip serial communication interface 0 receive data full interrupt transfer request)*4 0 1 0 1 TXI0 (On-chip serial communication interface 0 transmit data empty interrupt transfer request)*4 0 1 1 0 RXI1 (On-chip serial communication interface 1 receive data full interrupt transfer request)*4 0 1 1 1 TXI1 (On-chip serial communication interface 1 transmit data empty interrupt transfer request)*4 1 0 0 0 IMIA0 (On-chip ITU0 input capture/compare-match A interrupt transfer request)*4 1 0 0 1 IMIA1 (On-chip ITU1 input capture/compare-match A interrupt transfer request)*4 1 0 1 0 IMIA2 (On-chip ITU2 input capture/compare-match A interrupt transfer request)*4 1 0 1 1 IMIA3 (On-chip ITU3 input capture/compare-match A interrupt transfer request)*4 1 1 0 0 Auto-request (Transfer requests automatically generated within DMAC)*4 1 1 0 1 Reserved (illegal setting) 1 1 1 0 Reserved (illegal setting) 1 1 1 1 Reserved (illegal setting) SCI0, SCI1: Serial communications interface channels 0 and 1. ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit. Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be selected in channels 2 and 3. 2. Transfer from memory-mapped external device or external memory to external device with DACK. 3. Transfer from external device with DACK to memory-mapped external device or external memory. 4. Dual address mode. RENESAS 177 • Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1. The AM bit is initialized to 0 by resets or in standby mode. The AM bit is not valid in single address mode. Bit 7: AM Description 0 DACK is output in read cycle (initial value) 1 DACK is output in write cycle • Bit 6 (acknowledge Level Bit (AL)): AL selects active high signal or active low signal for the DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by resets or in standby mode. Bit 6: AL Description 0 DACK is active high (initial value) 1 DACK is active low • Bit 5 (DREQ select bit (DS)): DS selects the DREQ input detection method used. This bit is valid only in channels 0 and 1. The DS bit is initialized to 0 by resets or in standby mode. Bit 5: DS Description 0 DREQ detected by low level (initial value) 1 DREQ detected by falling edge • Bit 4 (transfer bus mode bit (TM)): TM selects the bus mode for DMA transfers. The TM bit is initialized to 0 by resets or in standby mode. When the source of the transfer request is an onchip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes with the RS Bit. Bit 4: TM Description 0 Cycle-steal mode (initial value) 1 Burst mode 178 RENESAS • Bit 3 (transfer size bit (TS)): TS selects the transfer unit size. If the on-chip peripheral module that is the source or destination of the transfer can only be accessed in bytes, byte must be selected in this bit. The TS bit is initialized to 0 by resets or in standby mode. Bit 3: TS Description 0 Byte (8 bits) (initial value) 1 Word (16 bits) • Bit 2 (interrupt enable bit (IE)): IE determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) is requested from the CPU when the TE bit is set. The IE bit is initialized to 0 by resets or in standby mode. Bit 2: IE Description 0 Interrupt request disabled (initial value) 1 Interrupt requeste enabled • Bit 1 (transfer end flag bit (TE)): TE indicates that the transfer has ended. When a DMA transfer ends normally and the value in the DMA transfer count register (TCR) becomes 0, the TE bit is set to 1. This flag is not set if the transfer ends because of an NMI interrupt or address error, or because the DE bit or the DME bit of the DMA operation register (DMAOR) was cleared. To clear the TE bit, read 1 from it and then write 0. When this flag is set, setting the DE bit to 1 does not enable a DMA transfer. The TE bit is initialized to 0 by resets or in standby mode. Bit 1: TE Description 0 DMA has not ended or was aborted (initial value) To clear TE, the CPU must read TE after it has been set to 1, then write a 0 in this bit 1 DMA has ended normally RENESAS 179 • Bit 0 (DMA enable bit (DE)): DE enables or disables DMA transfers. In the auto-request mode, the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The TE bit and the NMIF and AE bits of the DMAOR must be all cleared to 0. In external request mode or on-chip peripheral module request mode, the transfer begins when the DMA transfer request is received from said device or on-chip peripheral module, provided this bit and the DME bit are set to 1. As with the auto request mode, the TE bit and the NMIF and AE bits of the DMAOR must be all cleared to 0. The transfer can be stopped by clearing this bit to 0. The DE bit is initialized to 0 by resets or in standby mode. Bit 0: DE Description 0 DMA transfer disabled (initial value) 1 DMA transfer enabled 9.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset or the standby mode. Bit: 15 14 13 12 11 10 9 8 —— — — — — — PR1 PR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — AE NMIF DME Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/(W)* R/(W)* R Bit name: Note: Write only 0 to clear the flag. • Bits 15–10 (reserved): These bits always read 0. The write value should always be 0. 180 RENESAS • Bits 9 and 8 (priority mode bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description 0 0 Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (initial value) 0 1 Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0) 1 0 Round-robin mode priority order (the priority order immediately after a reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) 1 1 External-pin round-robin mode priority order (the priority order immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0) • • Bits 7–3 (reserved): These bits always read 0. The write value should always be 0. Bit 2 (address error flag bit (AE)): AE indicates that an address error occurred in the DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read 1 from it and then write 0. It is initialized to 0 by a reset or the standby mode. Bit 2: AE Description 0 No DMAC address error (initial value) To clear the AE bit, read 1 from it and then write 0. 1 • Address error by DMAC Bit 1 (NMI Flag Bit (NMIF)): NMIF indicates that an NMI interrupt occurred. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the CHCR and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and then write 0. It is initialized to 0 by a reset or the standby mode. Bit 1: NMIF Description 0 No NMI interrupt (initial value) To clear the NMIF bit, read 1 from it and then write 0. 1 NMI has occurred RENESAS 181 • Bit 0 (DMA master enable bit (DME)): DME enables or disables DMA transfers on all channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's CHCR and the DME bit are set to 1. For this to be effective, however, the TE bit of each CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are aborted. Bit 0: DME Description 0 Disable DMA transfers on all channels (initial value) 1 Enable DMA transfers on all channels 9.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. Transfer can be in either the single address mode or the dual address mode. The bus mode can be either burst or cycle steal 9.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (TCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (for an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The TCR value will be decremented by 1). The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when TCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Figure 9.2 is a flowchart of this procedure. 182 RENESAS Start Initial settings (SAR, DAR, TCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 *2 No Yes *3 Transfer (1 transfer unit); TCR–1 → TCR, SAR and DAR updated TCR = 0? Yes DEI interrupt request (when IE = 1) No Bus mode, transfer request mode, DREQ detection selection system Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes No Transfer aborted Does NMIF = 1, AE = 1, DE = 0, and DME = 0? Yes No Normal end Notes: 1. 2. 3. Transfer ends In auto-request mode, transfer begins when NMIF, AE and TE are all and the DE and DME bits are set to 1. DREQ = level detection in the burst mode (external request), or cycle steal mode. DREQ = edge detection in the burst mode (external request), or auto request mode in burst mode. Figure 9.2 DMA Transfer Flowchart RENESAS 183 9.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. The request mode is selected in the RS3–RS0 bits of the DMA channel control registers 0–3 (CHCR0–CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0–CHCR3 and the DME bit of the DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0–CHCR3 and the NMIF and AE bits of DMAOR are all 0). External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an external device. Choose one of the modes shown in table 9.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit of CHCR0–CHCR3 (DS = 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 9.3 Selecting External Request Modes with the RS Bits RS3 RS2 RS1 RS0 Address Mode Source Destination 0 0 0 0 Dual address mode Any* Any* 0 0 1 0 Single address mode External memory or memory-mapped external device External device with DACK 0 0 1 1 Single address mode External device with DACK External memory or memory-mapped external device Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC) On-Chip Module Request: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip module. The transfer request signals include the receive data full interrupt (RXI) of the serial communication interface (SCI), the transmit data empty interrupt (TXI) of the SCI, the input capture A/compare match A interrupt request (IMIA) of the 16-bit integrated-pulse timer (ITU), (table 9.4). When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. The source of the transfer request does not have to be the data transfer 184 RENESAS source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI’s receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bit DMA Transfer Request DMA Transfer Request RS3 RS2 RS1 RS0 Source Signal Source Desti- Bus Mode nation 0 1 0 0 SCI0 receiver RXI0 (SCI0 receive data full interrupt transfer request) RDR0 Any* Cycle steal 0 1 0 1 SCI0 transmitter TXI0 (SCI0 transmit data empty interrupt transfer request) Any TDR0 Cycle steal 0 1 1 0 SCI1 receiver RXI1 (SCI1 receive data full interrupt transfer request) RDR1 Any* Cycle steal 0 1 1 1 SCI1 transmitter TXI1 (SCI1 transmit data empty interrupt transfer request) Any* TDR1 Cycle steal 1 0 0 0 ITU0 IMIA0 (ITU0 input capture A/ compare-match A) Any* Any* Burst/Cycle steal 1 0 0 1 ITU1 IMIA1 (ITU1 input capture A/ compare-match A) Any* Any* Burst/Cycle steal 1 0 1 0 ITU2 IMIA2 (ITU2 input capture A/ compare-match A) Any* Any* Burst/Cycle steal 1 0 1 1 ITU3 IMIA3 (ITU3 input capture A/ compare-match A) Any* Any* Burst/Cycle steal SCI0, SCI1: Serial communications interface channels 0 and 1 ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit. RDR0, RDR1: Receive data registers 0, 1 of SCI TDR0, TDR1: Transmit data registers 0, 1 of SCI Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC) When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from onchip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip peripheral module is specified as the transfer request source, set the priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller (INTC) at or below the levels set in the I3–I0 bits of the CPU’s status register (SR) so that the CPU does not acknowledge the interrupt request signal. RENESAS 185 The DMA transfer request signals of table 9.4 are automatically withdrawn when the corresponding DMA transfer is performed. If the cycle steal mode is being employed, the DMA transfer request (interrupt request) will be cleared at the first transfer; if the burst mode is being used, it will be cleared at the last transfer. 9.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The three modes (fixed mode, round-robin mode, and external-pin round-robin mode) are selected by the priority bits PR1 and PR0 in the DMA operation register. Fixed Mode: In these modes, the priority levels among the channels remain fixed. When PR1 and PR0 bits are set 00, the priority order, high to low, is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1. When PR1 and PR0 bits are set 01, the priority order, high to low, is Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0. Round-Robin Mode: Each time one word or byte is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. When necessary, the priority order of channels other than the one that just finished the transfer can also be shifted to keep the relationship between the channels from changing (figure 9.3). The priority order immediately after a reset is channel 0 > channel 3 > channel 2 > channel 1. 186 RENESAS (1) When channel 0 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Channel 0 becomes bottom priority Priority order after transfer ch3 > ch2 > ch1 > ch0 (2) When channel 3 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Priority order after transfer ch2 > ch1 > ch0 > ch3 (3) When channel 2 transfers Initial priority order Priority order after transfer ch0 > ch3 > ch2 > ch1 ch1 > ch0 > ch3 > ch2 Post-transfer priority order when there is an immediate transfer request to channel 3 only ch2 > ch1 > ch0 > ch3 Channel 3 becomes bottom priority. The priority of channel 0, which was higher than channel 3, is also shifted. Channel 2 becomes bottom priority. The priority of channels 0and 3, which were higher than channel 2, are also shifted. If immediately thereafter there is a request to transfer channel 3 only, channel 3 becomes bottom priority and the priority of channels 0 and 1, which were higher than channel 3, are also shifted. (4) When channel 1 transfers Initial priority order ch0 > ch3 > ch2 > ch1 Priority order does not change Priority order after transfer ch0 > ch3 > ch2 > ch1 Figure 9.3 Round-Robin Mode Figure 9.4 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 3 transfer is requested during the channel 0 transfer. The DMAC operates as follows: RENESAS 187 1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for transfer). 3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 3 has a higher priority than channel 1, so the channel 3 transfer begins (channel 1 waits for transfer). 6. When the channel 3 transfer ends, channel 3 becomes lowest priority. 7. The channel 1 transfer begins. 8. When the channel 1 transfer ends, channels 1 and 2 shift downward in priority so that channel 1 becomes the lowest priority. Transfer request Waiting channel(s) (1) Channels 0 and 1 DMAC operation Channel priority (2) Channel 0 transfer starts 0>3>2>1 1 (3) Channel 3 1, 3 (4) Channel 0 transfer ends Priority order changes 3>2>1>0 (5) Channel 3 transfer starts 1 (6) Channel 3 transfer ends Priority order changes 2>1>0>3 (7) Channel 1 transfer starts None (8) Channel 1 transfer ends Priority order changes 0>3>2>1 Figure 9.4 Changes in Channel Priority in Round-Robin Mode 188 RENESAS External-Pin Round-Robin Mode: External-pin round-robin mode switches the priority levels of channel 0 and channel 1, which are the channels that can receive transfer requests from external pins DREQ0 and DREQ1. The priority levels are changed after each (byte or word) transfer on channel 0 or channel 1 is completed. The channel which just finished the transfer rotates to the bottom of the priority order. The priority levels of channels 2 and 3 do not change. The initial priority order after a reset is channel 3 > channel 2 > channel 1 > channel 0. Figure 9.5 shows how the priority order changes when channel 0 and channel 1 transfers are requested simultaneously and a channel 0 transfer is requested again after both channels finish their transfers. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 1 has a higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 3. When the channel 1 transfer ends, channel 1 becomes lowest priority. 4. The channel 0 transfer begins. 5. When the channel 0 transfer ends, channel 0 becomes lowest priority. 6. A channel 0 transfer request occurs again. 7. The channel 0 transfer begins. 8. When the channel 0 transfer ends, the priority order does not change, because channel 0 is already the lowest priority. RENESAS 189 Transfer request Waiting channel(s) (1) Channels 0 and 1 DMAC operation Channel priority (2) Channel 1 transfer starts 3>2>1>0 0 (3) Channel 1 transfer ends Priority order changes 3>2>0>1 (4) Channel 0 transfer starts None (5) Channel 0 transfer ends (7) Channel 0 transfer starts (6) Channel 0 None (8) Channel 0 transfer ends Priority order changes 3>2>1>0 Waiting for transfer request Priority order does not change 3>2>1>0 Figure 9.5 Example of Changes in Priority in External-Pin Round-Robin Mode 190 RENESAS 9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode or dual address mode, which are defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 9.5 Supported DMA Transfers Destination External Memory MemoryMapped External On-Chip Device Memory On-Chip Peripheral Module External device with DACK Not available Single Single Not available Not available External memory Single Dual Dual Dual Dual Memory-mapped external Single device Dual Dual Dual Dual On-chip memory Not available Dual Dual Dual Dual On-chip peripheral module Not available Dual Dual Dual Dual Source External Device with DACK Single: Single address mode Dual: Dual address mode RENESAS 191 Address Modes: • Single Address Mode In the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge DACK signal to one external device to access it while outputting an address to the other end of the transfer. Figure 9.6 shows an example of a transfer between an external memory and an external device with DACK in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle. External address bus External data bus SH microcomputer External memory DMAC Read Write * * (1) (2) External device with DACK DACK DREQ : Data flow Note: The read/write direction is decided by the RS3-RS0 bits of the CHCRn registers. If RS3RS0=0010, the direction is shown as case 1 (circled number above); if RS3-RS0=0010, the direction is shown as case 2. Also, DACK output (when writing) indicates case 2. Figure 9.6 Data Flow in Single Address Mode Two types of transfers are possible in the single address mode: 1) transfers between external devices with DACK and memory-mapped external devices, and 2) transfers between external devices with DACK and external memory. The only transfer requests for either of these is the external request (DREQ). Figure 9.7 shows the DMA transfer timing for the single address mode. 192 RENESAS The DACK output when a transfer occurs from an external device with DACK to a memorymapped external device is the write waveform. The DACK output when a transfer occurs from a memory-mapped external device to an external device with DACK is the read waveform. The setting of the acknowledge mode (AM) bits in the channel control registers (CHCR0, CHCR1) have no effect. CK A21–A0 Address output to external memory space CSn D15–D0 DACK WRH WRL Data that is output from the external device with DACK DACK signal to external devices with DACK (active low) WR signal to external memory space (a) External device with DACK to external memory space CK A21–A0 Address output to external memory space CSn D15–D0 RD DACK Data that is output from external memory space RD signal to external memory space DACK signal to external device with DACK (active low) (b) External memory space to external device with DACK Figure 9.7 Example of DMA Transfer Timing in the Single Address Mode RENESAS 193 • Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. The source is accessed in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8 shows an example of a transfer between two external memories in which data is read from one memory in the read cycle and written to the other memory in the following write cycle. External data bus SuperH microcomputer 2 DMAC External memory External memory 1 : Data flow 1: Read cycle 2: Write cycle Figure 9.8 Data Flow in Dual Address Mode In the dual address mode transfers, external memory, memory-mapped external devices, onchip memory and on-chip peripheral modules can be mixed without restriction. Specifically, this enables the following transfer types: 1. 2. 3. 4. 5. 6. 7. External memory and external memory transfer External memory and memory-mapped external devices transfer Memory-mapped external devices and memory-mapped external devices transfer External memory and on-chip memory transfer External memory and on-chip peripheral modules (excluding the DMAC) transfer Memory-mapped external devices and on-chip memory transfer Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC) transfer 8. On-chip memory and on-chip memory transfer 9. On-chip memory and on-chip peripheral modules (excluding the DMAC) transfer 10. On-chip peripheral modules (excluding the DMAC) and on-chip peripheral modules (excluding the DMAC) transfer 194 RENESAS Transfer requests can be auto requests, external requests, or on-chip peripheral module requests. When the transfer request source is either the SCI or A/D converter, however, either the data destination or source must be the SCI or A/D converter (figure 9.4), In dual address mode, DACK is output in read or write cycles to onchip memory or onchip peripheral modules. The CHCR controls the cycle of DACK output. Figure 9.9 shows the DMA transfer timing in the dual address mode. CK A21–A0 Source address Destination address CSn D15–D0 RD WRH WRL DACK Figure 9.9 DMA Transfer Timing in the Dual Address Mode (External memory space to external memory space transfer with DACK output in the read cycle) Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TM bits of CHCR0–CHCR3. • Cycle-Steal Mode In the cycle steal mode, the bus right is given to another bus master after a one-transfer-unit (word or byte) DMA transfer. When another transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. The cycle steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 9.10 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are:  Dual address mode  DREQ level detection RENESAS 195 DREQ Bus right returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC Read Write CPU Figure 9.10 Transfer Example in the Cycle-Steal Mode (Dual address mode, DREQ level detection) • Burst Mode Once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used when the serial communications interface (SCI) is the transfer request source. Figure 9.11 shows an example of DMA transfer timing in the burst mode. The transfer conditions shown in the figure are:  Single address mode  DREQ level detection DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 9.11 Transfer Example in the Burst Mode (Single address mode, DREQ level detection) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6 shows the relationship between request modes and bus modes by DMA transfer category. 196 RENESAS Table 9.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category Addres s Mode Transfer Category Request Mode Bus Mode Transfer Size (bits) Usable Channels Single External device with DACK and external memory External B/C 8/16 0,1 External device with DACK and memory-mapped external device External B/C 8/16 0, 1 External memory and external memory Everything*1 B/C 8/16 0–3* 5 External memory and memorymapped external device Everything*1 B/C 8/16 0–3* 5 Memory-mapped external device and Everything*1 memory-mapped external device B/C 8/16 0–3* 5 External memory and on-chip memory Everything*1 B/C 8/16 0–3* 5 External memory and on-chip peripheral module Everything*2 B/C* 3 8/16*4 0–3* 5 Memory-mapped external device and Everything*1 on-chip memory B/C 8/16 0–3* 5 Memory-mapped external device and Everything*2 on-chip peripheral module B/C* 3 8/16*4 0–3* 5 Dual On-chip memory and on-chip memory Everything*1 B/C 8/16 0–3* 5 On-chip memory and on-chip peripheral module Everything*2 B/C* 3 8/16*4 0–3* 5 On-chip peripheral module and onchip peripheral module Everything*2 B/C* 3 8/16*4 0–3* 5 B: Burst, C: Cycle steal Notes: 1. External requests, auto requests and on-chip peripheral module requests are all available. For on-chip peripheral module requests, however, SCI cannot be specified as the transfer request source. 2. External requests, auto requests and on-chip peripheral module requests are all available. When the SCI is also the transfer request source, however, the transfer destination or transfer source must be the SCI respectively. 3. If the transfer request source is the SCI, cycle steal only. 4. The access size permitted when the transfer destination or source is an on-chip peripheral module register. 5. If the transfer request is an external request, channels 0 and 1 only. Bus Mode and Channel Priority Order: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (2) with a higher priority, the transfer of the channel RENESAS 197 with higher priority (2) will begin immediately. When channel 2 is also operating in the burst mode, the channel 1 transfer will continue when the channel 2 transfer has completely finished. When channel 2 is in the cycle steal mode, channel 1 will begin operating again after channel 2 completes the transfer of one transfer unit, but the bus will then switch between the two in the order channel 1, channel 2, channel 1, channel 2. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in figure 9.12. Bus status CPU CPU DMAC ch1 DMAC ch1 DMAC ch1 Burst mode DMAC ch2 DMAC ch1 DMAC ch2 ch2 ch1 ch2 DMAC ch1 and ch2 Cycle steal mode DMAC ch1 DMAC ch1 DMAC ch1 Burst mode CPU CPU Figure 9.12 Bus Handling when Multiple Channels Are Operating 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller just as it is when the CPU is the bus master. The bus cycle in the dual address mode is controlled by wait state control register 1 (WCR1) while the single address mode bus cycle is controlled by wait state control register 2 (WCR2). For details, see section 8.9, Wait State Control. DREQ Pin Sampling Timing: Normally, when DREQ input is detected immediately prior to the rise edge of the clock pulse (CK) in external request mode, a DMAC bus cycle will be generated and the DMA transfer performed two states later at the earliest. The sampling timing after DREQ input detection differs by bus mode, address mode and method of DREQ input detection. • DREQ pin sampling timing in the cycle steal mode In the cycle steal mode, the sampling timing is the same regardless of whether the DREQ is detected by edge or level. When edge is being detected, however, once sampled it will not be sampled again until the next edge detection. Once DREQ input is detected, the next sampling is not performed until the first state, among those DMAC bus cycles thereby produced, in which a DACK signal is output (including the detection state itself). The next sampling occurs immediately prior to the rise edge of the clock pulse(CK) of the third state after the bus cycle previous to the bus cycle in which the DACK signal is output. 198 RENESAS Figure 9.13 to 9.22 show the sampling timing of the pin DREQ in the cycle steal mode for each bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ detection, the next sampling occurs in the next stage in which a DACK signal is output. If no DREQ input is detected at this time, sampling occurs at every state thereafter. CK DREQ Bus cycle CPU CPU CPU DMAC CPU CPU CPU CPU DACK Figure 9.13 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 1 state) CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC Read cycle. Figure 9.14 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 1 state) RENESAS 199 CK DREQ Bus cycle CPU CPU CPU DMAC CPU CPU CPU CPU DACK Figure 9.15 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 2 states) CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: Illustrates the case when DACK is output during the DMAC write cycle. Figure 9.16 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 2 states) 200 RENESAS T1 Tw T2 T1 Tw T2 CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.17 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = 2 states + 1 wait state) T1 Tw T2 T1 Tw T2 CK DREQ Bus cycle CPU CPU CPU DMAC (R) DMAC (W) CPU CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Figure 9.18 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = 2 states + 1 wait state) RENESAS 201 Tp Tr Tc Tc Tp Tr Tc Tc CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.19 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = DRAM bus cycle (long pitch normal mode)) Tp Tr Tc Tc Tp Tr Tc Tc CK DREQ Bus cycle CPU CPU CPU DMAC(R) DMAC (W) CPU DMAC (R) DMAC (W) CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.20 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = DRAM bus cycle (long pitch normal mode)) 202 RENESAS T1 T2 T3 T4 T1 T2 T3 T4 CK DREQ Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DACK Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.21 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Single address mode, bus cycle = Address/data multiplex I/O bus cycle) T1 T2 T3 T4 T1 T2 T3 T4 CK DREQ Bus cycle CPU CPU CPU DMAC(R) DMAC (W) CPU DMAC (R) DMAC (W) CPU DACK DMAC (R): DMAC read cycle DMAC (W): DMAC write cycle Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer will be executed because the sampling is done at the second state of the DMAC cycle. Figure 9.22 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level detection and DACK active low) (Dual address mode, bus cycle = Address/data multiplex I/O bus cycle) RENESAS 203 • DREQ pin sampling timing in the burst mode In the burst mode, the sampling timing differs depending on whether DREQ is detected by edge or level. When DREQ input is being detected by edge, once the falling edge of the DREQ signal is detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless of the status of the DREQ pin. No sampling happens during this time. After the transfer ends, sampling occurs every state until the TE bit of the CHCR is cleared. When DREQ input is being detected by level, once the DREQ input is detected, next sampling is performed at the end of every CPU or DMAC bus cycle in the single address mode. In the dual address mode, the next sampling is performed at the start of every DMAC read cycle. In both the single address mode and dual address mode, if no DREQ input is detected at this time, sampling thereafter occurs at every state. Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is detected by low level. CK DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC CPU DACK Note: Single address DREQ level detection, DACK active low, 1 bus cycle = 2 states. Figure 9.23 DREQ Pin Sampling Timing in Burst Mode 204 RENESAS CK DREQ Bus cycle CPU CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU DACK Note: Dual address DREQ level detection, DACK active low, DACK output in read cycle, 1 bus cycle = 2 states. Figure 9.24 DREQ Pin Sampling Timing in Burst Mode 9.3.6 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (TCR) is 0, or when the DE bit of the channel's CHCR is cleared to 0. • When TCR is 0: When the TCR value becomes 0 and the corresponding channel’s DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) is requested to the CPU. • When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel’s CHCR. The TE bit is not set when this happens. Conditions for Ending All Channels Simultaneously: Transfers on all channels end when 1) the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or 2) when the DME bit in the DMAOR is cleared to 0. RENESAS 205 • • Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their transfers. The SAR, DAR, TCR are all updated by the transfer immediately preceding the halt. The TE bit is not set. To resume the transfers after NMI interrupt exception processing or address error exception processing, clear the appropriate flag bit to 0. When a channel’s DE bit is then set to 1, the transfer on that channel will restart. To avoid restarting a transfer on a particular channel, keep its DE bit cleared to 0. In the dual address mode, the DMA transfer will be halted after the completion of the write cycle that follows the initial read cycle in which the address error occurs. SAR, DAR and TCR are updated by the final transfer. Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly aborts the transfers on all channels at the end of the current cycle. The TE bit is not set. 9.4 Examples of Use 9.4.1 DMA Transfer between On-Chip RAM and a Memory-Mapped External Device In the following example, data is transferred from an on-chip RAM to a memory-mapped external device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit integrated-timer pulse unit (ITU) as the transfer request signal. The transfer is performed by DMAC channel 3. Table 9.7 shows the transfer conditions and register values. Table 9.7 Transfer Conditions and Register Settings for Transfer Between On-Chip RAM and Memory-Mapped External Device Transfer Conditions Register Setting Transfer source: on-chip RAM SAR3 H'FFFFE00 Transfer destination: memory-mapped external device DAR3 Destination address Number of transfers: 8 TCR3 H'0008 Transfer destination address: fixed CHCR3 H'1805 DMAOR H'0001 Transfer source address: incremented Transfer request source (transfer request signal): ITU channel 0 (IMIA0) Bus mode: cycle steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer) Channel priority order: fixed (0 > 3 > 2 > 1) (all channels transfer enabled) 206 RENESAS 9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory In this example, receive data of on-chip serial communications interface (SCI) channel 0 is transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions and register settings. Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI and External Memory Transfer Conditions Register Setting Transfer source: RDR0 of on-chip SCI0 SAR3 H'FFFFEC5 Transfer destination: external memory DAR3 Destination address Number of transfers: 64 TCR3 H'0040 Transfer destination address: incremented CHCR3 H'4405 DMAOR H'0001 Transfer source address: fixed Transfer request source (transfer request signal): SCI0 (RXI0) Bus mode: cycle steal Transfer unit: byte DEI interrupt request generated at end of transfer (channel 3 enabled for transfer Channel priority order: fixed (0 > 3 > 2 > 1) (all channels transfer enabled) RENESAS 207 9.5 Cautions 1. All registers other than the DMA operations register (DMAOR) and DMA channel control registers 0–3 (CHCR0–CHCR3) should be accessed in word or long word units. 2. Before rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (when rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance). 3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR will be set. 4. Interrupt during DMAC Transfer a. When an NMI interrupt is input, the DMAC stops operation and returns the bus right to the CPU. The CPU then executes the interrupt processing. b. When an interrupt other than an NMI occurs. • When the DMAC is in burst mode. The DMAC does not return the bus right to the CPU in burst mode. Therefore, even when an interrupt is requested in DMAC operation, the CPU cannot get the bus right, causing the interrupt processing not to be executed. When the DMAC completes transfer and the CPU gets the bus right, the CPU executes the interrupt processing if the interrupt requested during DMAC transfer is not cleared.* * Clear conditions for an interrupt request.  When an interrupt is requested from an on-chip peripheral module, the interrupt factor flag is cleared.  When an interrupt is requested by IRQ (edge detection), the CPU begins the IRQ interrupt processing of the request source.  When an interrupt is requested by IRQ (level detection), the IRQ interrupt request signal returned to high level. • When the DMAC is in cycle-steal mode. The DMAC returns the bus right to the CPU every when the DMAC completes a transfer unit in cycle-steal mode. Therefore, the CPU executes the requested interrupt processing when getting the bus right. 5. The CPU and DMAC leaves the bus right released and the operation of the LSI is stopped when the following conditions are satisfied. • The warp bit (WARP) of the bus control register (BCR) of the bus controller (BSC)is set. • The DMAC is in cycle-steal transfer mode. • The CPU accesses (reads/writes) the on-chip I/O space. • Countermeasure Set the warp bit of BCR to 0 and set it to normal mode. 208 RENESAS 6. Notes on use of the SLEEP command a. Operation contents When the bus cycle of DMAC is entered immediately after executing the SLEEP command, there are cases when the DMA transfer is carried out correctly. b. Countermeasure • Stop the operation (for exemple, clearing of the DMA enable bit (DE) of the DMA channel control register(CHCRn)) before entering SLEEP. • When using DMAC during SLEEP, operate DMAC after releasing SLEEP through interruption. In cases when the CPU does not carry out any other processing but is waiting for DMAC to end its transfer during DMAC operation, do not use the SLEEP command, but use the transfer end flag bit (TE) of the channel DMA control register and the polling software loop. Phenomenon: If the bus cycle of DMAC is entered immediately after executing the SLEEP command, the bus cycle of DMAC may conflict with that of CPU. Address bus CPU CPU Fetch cycle of SLEEP command CPU DMAC CPU DMAC CPU This is in itself a DMAC cycle but involves CPU operation. Accordingly, the bus cycle of DMAC which has conflicted with that of CPU may malfunction. 7. Sampling of DREQ If DREQ is set to level detection in the DMA cycle steal mode, sampling of DREQ may take place before DACK is output. Note that some system configurations involve unnecessary DMA transfers. • Operation As shown in Figure 9.16, sampling of DREQ is carried out immediately before the leading edge of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus cycle where DACK is output. If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be carried out before DACK is output. RENESAS 209 Number of states of DMAC bus cycle 1 2 3 4 Sampling point : Bus cycle of DMAC Figure 9.16 Sampling Points of DREQ Especially as shown in Figure 9.17, if the bus cycle of DMA is a full access to DRAM or if refresh demand is generated, sampling of DREQ takes place before DACK is output as mentioned above. This phenomenon is found when one of the following transfers is made with DREQ set to the level detection in the DMA cycle steal mode, in a system which employs DRAM (refresh enabled). CK Tp Tr Tc Refresh T1 T2 DACK Sampling point Bus cycle of DRAM (Full access) Sampling point When refresh operation is entered Sampling point of DREQ for DACK output position differs with presence/absence of the refresh operation. Figure 9.17 Example of DREQ Sampling before Output of DACK • Transfer from a device having DACK to memory in the single address mode (not restricted to DRAM) • Transfer from DRAM to a device having DACK in the single address mode • Output at DACK write in the dual address mode Output at DACK read in the dual address mode and DMA transfer using DRAM as a source • Countermeasure To prevent unnecessary DMA transfers, configure the system where DREQ is used for edge detection and the edge corresponding to the next transfer request occurs after the DACK output. 210 RENESAS 8. When the following operations are performed in the order shown when the pin to which DREQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-level signal, the DREQ falling edge is detected, and a DMA transfer request accepted, immediately after the setting in (b) is performed: (a) A channel control register (CHCRn) setting is made so that an interrupt is detected at the falling edge of DREQ. (b) The function of the pin to which DREQ input is assigned is switched from general input to DREQ input by a pin function controller (PFC) setting. Therefore, when switching the pin function from general input pin to DREQ input, the pin function controller (PFC) setting should be changed to DREQ input while the pin to which DREQ input is assigned is high. RENESAS 211 Section 10 16-Bit Integrated-Timer Pulse Unit (ITU) 10.1 Overview The SuperH microcomputer has an on-chip 16-bit integrated-timer pulse unit (ITU) with five channels of 16-bit timers. 10.1.1 Features ITU features are listed below: • • • • • • • • Can process a maximum of twelve different pulse outputs and ten different pulse inputs. Has ten general registers (GR), two per channel, that can be set to function independently as output compare or input capture. Selection of eight counter input clock sources for all channels  Internal clock: φ, φ/2, φ/4, φ/8,  External clock: TCLKA, TCLKB, TCLKC, TCLKD All channels can be set for the following operating modes:  Compare match waveform output: 0 output/1 output/selectable toggle output (0 output/1 output for channel 2).  Input capture function: Selectable rising edge, falling edge, or both rising and falling edges.  Counter clearing function: Counters can be cleared by a compare match or input capture.  Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a compare match or input capture. Counter synchronization functions enable synchronized input/output.  PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, enables up to five-phase PWM output. Channel 2 can be set to the phase counting mode: Two-phase encoder output can be counted automatically. Channels 3 and 4 can be set in the following modes:  Reset-synchronized PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with positive and negative waveforms .  Complementary PWM mode: By combining channels 3 and 4, 3-phase PWM output is possible with non-overlapping positive and negative waveforms. Buffer operation: Input capture registers can be double-buffered. Output compare registers can be updated automatically. High-speed access via internal 16-bit bus: The TCNT, GR, and buffer register (BR) 16-bit registers can be accessed at high speed via a 16-bit bus. RENESAS 213 • • • Fifteen interrupt sources: Ten compare match/input capture interrupts (2 sources per channel) and five overflow interrupts are vectored independently for a total of 15 sources. Can activate DMAC: The compare match/input capture interrupts of channels 0–3 can start the DMAC (one for each of four channels). Output trigger can be generated for the programmable timing pattern controller (TPC): The compare match/input capture signals of channel 0–3 can be used as output triggers for the TPC. Table 10.1 summarizes the ITU functions. 214 RENESAS Table 10.1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Counter clocks Internal: φ, φ/2, φ/4, φ/8 External: Independently selectable from TCLKA, TCLKB, TCLKC, and TCLKD General registers (output compare/ input capture dual registers) GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 Buffer registers No No No BRA3, BRB3 BRA4, BRB4 Input/output pins TIOCA0, TIOCB0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3 TIOCA4, TIOCB4 Output pins No No No No TOCXA4, TOCXB4 Counter clear func- GRA0/GRB0 tion (compare match or input capture) GRA1/GRB1 GRA2/GRB2 GRA3/GRB3 GRA4/GRB4 Compare 0 Yes match 1 Yes output Toggle Yes output Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Input capture function Yes Yes Yes Yes Yes Synchronization Yes Yes Yes Yes Yes PWM mode Yes Yes Yes Yes Yes Reset-synchronized No PWM mode No No Yes Yes Complementary PWM mode No No No Yes Yes Phase counting mode No No Yes No No Buffer operation No No No Yes Yes DMAC activation GRA0 comGRA1 comGRA2 comGRA3 comNo pare match or pare match or pare match or pare match or input capture input capture input capture input capture Interrupt sources (three) • Compare • Compare • Compare • Compare • Compare match/input match/input match/input match/input match/input capture A0 capture A1 capture A2 capture A3 capture A4 • Compare • Compare • Compare • Compare • Compare match/input match/input match/input match/input match/input capture B0 capture B1 capture B2 capture B3 capture B4 • Overflow • Overflow • Overflow • Overflow • Overflow RENESAS 215 10.1.2 Block Diagram ITU Block Diagram (Complete): Figure 10.1 is the block diagram of the ITU. Control logic IMIA0–IMIA4 IMIB0–IMIB4 OVI0–OVI4 TOCR TSTR TSNC TMDR TFCR Module data bus TOCR: Timer output control register (8 bits) TSTR: Timer start regsiter (8 bits) TSNC: Timer synchronization register (8 bits) TMDR: Timer mode register (8 bits) TFCR: Timer function control register (8 bits) Figure 10.1 ITU Block Diagram 216 RENESAS Bus interface 16-bit timer channel 0 16-bit timer channel 4 16-bit timer channel 1 Counter control and pulse I/O control unit TOCXA4, TOCXB4 TIOCA0–TIOCA4 TIOCB0–TIOCB4 16-bit timer channel 2 φ, φ/2, φ/4, φ/8 Clock selection 16-bit timer channel 3 TCLKA–TCLKD Internal data bus Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2 is a block diagram of channels 0 and 1. Clock selection IMIAn IMIBn OVIn TSRn Control logic TCRn GRBn GRAn TCNTn Comparator TIERn φ, φ/2, φ/4, φ/8 TIOCAn TIOCBn TIORn TCLKA– TCLKD Module data bus TCNTn: Timer counter n (16 bits) GRAn, GRBn: General registers An, Bn (input capture/output compare dual use) (16 bits × 2) TCRn: Timer control register n (8 bits) TIORn: Timer I/O control register n (8 bits) TIERn: Timer interrupt enable register n (8 bits) TSRn: Timer status register n (8 bits) (n = 0 or 1) Figure 10.2 Channels 0 and 1 Block Diagram (One Channel Shown) RENESAS 217 Block Diagram of Channel 2: Figure 10.3 is a block diagram of channel 2. Channel 2 is 0 output/1 output only. Clock selection IMIA2 IMIB2 OVI2 TSR2 Control logic TCR2 GRB2 GRA2 TCNT2 Comparator TIER2 φ, φ/2, φ/4, φ/8 TIOCA2 TIOCB2 TIOR2 TCLKA– TCLKD Module data bus TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2, B2 (input capture/output compare dual use) (16 bits × 2) TCR2: Timer control register 2 (8 bits) TIOR2: Timer I/O control register 2 (8 bits) TIER2: Timer interrupt enable register 2 (8 bits) TSR2: Timer status register 2 (8 bits) Figure 10.3 Channel 2 Block Diagram 218 RENESAS Block Diagrams of Channels 3 and 4: Figure 10.4 is a block diagram of channel 3; figure 10.5 is a block diagram of channel 4. TCLKA– TCLKD Clock selection TIOCA3 TIOCB3 IMIA3 IMIB3 OVI3 TSR3 TIER3 TIOR3 GRB3 Control logic BRB3 GRA3 BRA3 TCNT3 Comparator TCR3 φ, φ/2, φ/4, φ/8 Module data bus TCNT3: Timer counter 3 (16 bits) GRA3, GRB3: General registers A3, B3 (input capture/output compare dual use) (16 bits × 2) BRA3, BRB3: Buffer registers A3, B3 (input capture/output compare dual use) (16 bits × 2) TCR3: Timer control register 3 (8 bits) TIOR3: Timer I/O control register 3 (8 bits) TIER3: Timer interrupt enable register 3 (8 bits) TSR3: Timer status register 3 (8 bits) Figure 10.4 Channels 3 Block Diagram RENESAS 219 TCLKA– TCLKD TOCXA4 TOCXB4 Clock selection TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 TSR4 TIER4 TIOR4 GRB4 Control logic BRB4 GRA4 BRA4 GCNT4 Comparator TCR4 φ, φ/2, φ/4, φ/8 Module data bus TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4, B4 (input capture/output compare dual use) (16 bits × 2) BRA4, BRB4: Buffer registers A4, B4 (input capture/output compare dual use) (16 bits × 2) TCR4: Timer control register 4 (8 bits) TIOR4: Timer I/O control register 4 (8 bits) TIER4: Timer interrupt enable register 4 (8 bits) TSR4: Timer status register 4 (8 bits) Figure 10.5 Channel 4 Block Diagram 220 RENESAS 10.1.3 Input/Output Pins Table 10.2 summarizes the ITU pins. External pin functions should be set with the pin function controller to match to the ITU setting. See section 15, Pin Function Controller, for details. ITU pins need to be set using the pin function controller (PFC) after the LSI is set to the ITU mode. Table 10.2 Pin Configuration Channel Name Pin Name I/O Function Shared Clock input A TCLKA I External clock A input pin (A-phase input pin in phase counting mode) Clock input B TCLKB I External clock B input pin (B-phase input pin in phase counting mode) Clock input C TCLKC I External clock C input pin Clock input D TCLKD I External clock D input pin Input capture/output compare A0 TIOCA0 I/O GRA0 output compare/GRA0 input capture/PWM output pin (in PWM mode) Input capture/output compare B0 TIOCB0 I/O GRB0 output compare/GRB0 input capture Input capture/output compare A1 TIOCA1 I/O GRA1 output compare/GRA1 input capture/PWM output pin (in PWM mode) Input capture/output compare B1 TIOCB1 I/O GRB1 output compare/GRB1 input capture Input capture/output compare A2 TIOCA2 I/O GRA2 output compare/GRA2 input capture/PWM output pin (in PWM mode) Input capture/output compare B2 TIOCB2 I/O GRB2 output compare/GRB2 input capture Input capture/output compare A3 TIOCA3 I/O GRA3 output compare/GRA3 input capture/PWM output pin (in PWM mode, complementary PWM mode, or reset-synchronized PWM mode) Input capture/output compare B3 TIOCB3 I/O GRB3 output compare/GRB3 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) Input capture/output compare A4 TIOCA4 I/O GRA4 output compare/GRA4 input capture/PWM output pin (in PWM mode, complementary PWM mode or reset-synchronized PWM mode) Input capture/output compare B4 TIOCB4 I/O GRB4 output compare/GRB4 input capture/PWM output pin (in complementary PWM mode or resetsynchronized PWM mode) Output compare XA4 TOCXA4 I/O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode) Output compare XB4 TOCXB4 I/O PWM output pin (in complementary PWM mode or reset-synchronized PWM mode) 0 1 2 3 4 RENESAS 221 10.1.4 Register Configuration Table 10.3 summarizes the ITU register configuration. Table 10.3 Register Configuration Access Size Channel Name Abbreviation R/W Initial Value Shared Timer start register TSTR R/W H'E0/H'60 H'5FFFF00 8 Timer synchro register TSNC R/W H'E0/H'60 H'5FFFF01 8 Timer mode register TMDR R/W H'80/H'00 H'5FFFF02 8 Timer function control register TFCR R/W H'C0/H'40 H'5FFFF03 8 Timer output control register TOCR R/W H'FF/H'7F H'5FFFF31 8 Timer control register 0 TCR0 R/W H'80/H'00 H'5FFFF04 8 Timer I/O control register 0 TIOR0 R/W H'88/H'08 H'5FFFF05 8 Timer interrupt enable register 0 TIER0 R/W H'F8/H'78 H'5FFFF06 8 Timer status register 0 TSR0 R/(W)*2 H'F8/H'78 H'5FFFF07 8 Timer counter 0 TCNT0 R/W H'00 H'5FFFF08 8, 16, 32 H'5FFFF09 8, 16, 32 0 General register A0 GRA0 R/W H'FF Address* 1 H'5FFFF0A 8, 16, 32 H'5FFFF0B 8, 16, 32 General register B0 GRB0 R/W H'FF H'5FFFF0C 8, 16 H'5FFFF0D 8, 16 1 Timer control register 1 TCR1 R/W H'80/H'00 H'5FFFF0E 8 Timer I/O control register 1 TIOR1 R/W H'88/H'08 H'5FFFF0F 8 Timer interrupt enable register 1 TIER1 R/W H'F8/H'78 H'5FFFF10 8 Timer status register 1 TSR1 R/(W)*2 H'F8/H'78 H'5FFFF11 8 Timer counter 1 TCNT1 R/W H'00 H'5FFFF12 8, 16 H'5FFFF13 8, 16 H'5FFFF14 8, 16, 32 H'5FFFF15 8, 16, 32 H'5FFFF16 8, 16, 32 H'5FFFF17 8, 16, 32 General register A1 General register B1 222 RENESAS GRA1 GRB1 R/W R/W H'FF H'FF Table 10.3 Register Configuration (cont) Channel Name Abbreviation R/W Initial Value Address* 1 Access Size 2 Timer control register 2 TCR2 R/W H'80/H'00 H'5FFFF18 8 Timer I/O control register 2 TIOR2 R/W H'88/H'08 H'5FFFF19 8 Timer interrupt enable register TIER2 2 R/W H'F8/H'78 H'5FFFF1A 8 Timer status register 2 TSR2 R/(W)*2 H'F8/H'78 H'5FFFF1B 8 Timer counter 2 TCNT2 R/W H'00 H'5FFFF1C 8, 16, 32 H'5FFFF1D 8, 16, 32 General register A2 General register B2 3 GRA2 GRB2 R/W R/W H'FF H'FF H'5FFFF1E 8, 16, 32 H'5FFFF1F 8, 16, 32 H'5FFFF20 8, 16 H'5FFFF21 8, 16 Timer control register 3 TCR3 R/W H'80/H'00 H'5FFFF22 8 Timer I/O control register 3 TIOR3 R/W H'88/H'08 H'5FFFF23 8 Timer interrupt enable register TIER3 3 R/W H'F8/H'78 H'5FFFF24 8 Timer status register 3 TSR3 R/(W)*2 H'F8/H'78 H'5FFFF25 8 Timer counter 3 TCNT3 R/W H'00 H'5FFFF26 8, 16 H'5FFFF27 8, 16 H'5FFFF28 8, 16, 32 H'5FFFF29 8, 16, 32 General register A3 General register B3 GRA3 GRB3 R/W R/W H'FF H'FF H'5FFFF2A 8, 16, 32 H'5FFFF2B 8, 16, 32 Buffer register A3 BRA3 R/W H'FF H'5FFFF2C 8, 16, 32 H'5FFFF2D 8, 16, 32 Buffer register B3 4 BRB3 R/W H'FF H'5FFFF2E 8, 16, 32 H'5FFFF2F 8, 16, 32 Timer control register 4 TCR4 R/W H'80/H'00 H'5FFFF32 8 Timer I/O control register 4 TIOR4 R/W H'88/H'08 H'5FFFF33 8 Timer interrupt enable register TIER4 4 R/W H'F8/H'78 H'5FFFF34 8 Timer status register 4 R/(W)*2 H'F8/H'78 H'5FFFF35 8 TSR4 RENESAS 223 Table 10.3 Register Configuration (cont) Channel Name Abbreviation R/W Initial Value Address* 1 Access Size 4 (cont) TCNT4H H'00 H'5FFFF36 8, 16 H'5FFFF37 8, 16 H'5FFFF38 8, 16, 32 H'5FFFF39 8, 16, 32 Timer counter 4 General register A4 GRA4H General register B4 GRB4H R/W R/W R/W H'FF H'FF H'5FFFF3A 8, 16, 32 H'5FFFF3B 8, 16, 32 Buffer register A4 BRA4H R/W H'FF H'5FFFF3C 8, 16, 32 H'5FFFF3D 8, 16, 32 Buffer register B4 BRB4H R/W H'FF H'5FFFF3E 8, 16, 32 H'5FFFF3F 8, 16, 32 Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write 0 to clear flags. 10.2 ITU Register Descriptions 10.2.1 Timer Start Register (TSTR) The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 upon reset or standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — STR4 STR3 STR2 STR1 STR0 Initial value: * 1 1 0 0 0 0 0 R/W: — — — R/W R/W R/W R/W R/W Note: Undefined • Bits 7–5 (reserved): Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1. 224 RENESAS • Bit 4 (count start 4 (STR4)): STR4 starts and stops TCNT4. Bit 4: STR4 Description 0 TCNT4 is halted (initial value) 1 TCNT4 is counting • Bit 3 (count start 3 (STR3)): STR3 starts and stops TCNT3. Bit 3: STR3 Description 0 TCNT3 is halted (initial value) 1 TCNT3 is counting • Bit 2 (count start 2 (STR2)): STR2 starts and stops TCNT2. Bit 2: STR2 Description 0 TCNT2 is halted (initial value) 1 TCNT2 is counting • Bit 1 (count start 1 (STR1)): STR1 starts and stops TCNT1. Bit 1: STR1 Description 0 TCNT1 is halted (initial value) 1 TCNT1 is counting • Bit 0 (count start 0 (STR0)): STR0 starts and stops TCNT0. Bit 0: STR0 Description 0 TCNT0 is halted (initial value) 1 TCNT0 is counting RENESAS 225 10.2.2 Timer Synchro Register (TSNC) The timer synchro register (TSNC) is an eight-bit read/write register that selects timer synchronizing modes for channels 0–4. Channels for which 1 is set to the corresponding bit will be synchronized. TSNC is initialized to H'E0 or H'60 upon reset or standby mode. Bit: 7 6 5 4 3 Bit name: — — — Initial value: * 1 1 0 0 0 0 0 R/W: — — — R/W R/W R/W R/W R/W SYNC4 SYNC3 2 SYNC2 1 0 SYNC1 SYNC0 Note: Undefined • Bits 7–5 (reserved): Bit 7 is read as undefined. Bits 6 and 5 are always read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should always be 1. • Bit 4 (timer synchro 4 (SYNC4)): SYNC4 selects the synchronizing mode for channel 4. Bit 4: SYNC4 Description 0 The timer counter for channel 4 (TCNT4) operates independently (Preset/clear of TCNT4 is independent of other channels) (initial value) 1 Channel 4 operates synchronously. Synchronized preset/clear of TNCT4 enabled. • Bit 3 (timer Synchro 3 (SYNC3)): SYNC3 selects the synchronizing mode for channel 3. Bit 3: SYNC3 Description 0 The timer counter for channel 3 (TCNT3) operates independently (Preset/clear of TCNT3 is independent of other channels) (initial value) 1 Channel 3 operates synchronously. Synchronized preset/clear of TNCT3 enabled. • Bit 2 (timer synchro 2 (SYNC2)): SYNC2 selects the synchronizing mode for channel 2. Bit 2: SYNC2 Description 0 The timer counter for channel 2 (TCNT2) operates independently (Preset/clear of TCNT2 is independent of other channels) (initial value) 1 Channel 2 operates synchronously. Synchronized preset/clear of TNCT2 enabled. 226 RENESAS • Bit 1 (timer synchro 1 (SYNC1)): SYNC1 selects the synchronizing mode for channel 1. Bit 1: SYNC1 Description 0 The timer counter for channel 1 (TCNT1) operates independently (Preset/clear of TCNT1 is independent of other channels) (initial value) 1 Channel 1 operates synchronously. Synchronized preset/clear of TNCT1 enabled. • Bit 0 (timer synchro 0 (SYNC0)): SYNC0 selects the synchronizing mode for channel 0. Bit 0: SYNC0 Description 0 The timer counter for channel 0 (TCNT0) operates independently (Preset/clear of TCNT0 is independent of other channels) (initial value) 1 Channel 0 operates synchronously. Synchronized preset/clear of TNCT0 enabled. 10.2.3 Timer Mode Register (TMDR) The timer mode register (TMDR) is an eight-bit read/write register that selects the PWM mode for channels 0–4, sets the phase counting mode for channel 2, and sets the conditions for the overflow flag (OVF). TMDR is initialized to H'80 or H'00 by a reset or the standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: — MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value: * 0 0 0 0 0 0 0 R/W: — R/W R/W R/W R/W R/W R/W R/W Note: Undefined • Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1. • Bit 6 (phase counting mode (MDF)): MDF selects the phase counting mode for channel 2. Bit 6: MDF Description 0 Channel 2 operates normally (initial value) 1 Channel 2 operates in phase counting mode RENESAS 227 When the MDF is set to 1 to select the phase counting mode, the timer counter (TCNT2) becomes an up/down counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2 counts on both the rising and falling edges of TCLKA and TCLKB, with the increment/decrement chosen as follows: Count Direction Decrement Increment TCLKA pin Rising High Falling Low Rising High Falling Low TCLKB pin L Rising High Falling High Falling Low Rising In the phase counting mode, selections for external clock edge made in the CKEG1 and CKEG0 bits of the timer control register 2 (TCR2) and the selection for counter clock made in the TPSC2 –TPSC0 bits are ignored. The phase counting mode described above takes priority. Settings for counter clear conditions in the CCLR1 and CCLR0 bits of TCR2 and settings for timer I/O control register 2 (TIOR2), timer interrupt enable register (TIER2) and timer status register 2 (TSR2) compare match/input capture functions and interrupts, however, are valid even in the phase counting mode. • Bit 5 (flag direction (FDIR)): FDIR selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in. Bit 5: FDIR Description 0 OVF of TSR2 is set to 1 when TCNT2 overflows or underflows (initial value) 1 OVF of TSR2 is set to 1 when TCNT2 overflows • Bit 4 (PWM Mode 4 (PWM4)): PWM4 selects the PWM mode for channel 4. When the PWM4 bit is set to 1 and the PWM mode entered, the TIOCA4 pin becomes a PWM output pin. 1 is output on a compare match of general register A4 (GRA4); 0 is output on a compare match of general register B4 (GRB4). When the complementary PWM mode or resetsynchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0. Bit 4: PWM4 Description 0 Channel 4 operates normally (initial value) 1 Channel 4 operates in PWM mode 228 RENESAS • Bit 3 (PWM Mode 3 (PWM3)): PWM3 selects the PWM mode for channel 3. When the PWM3 bit is set to 1 and the PWM mode entered, the TIOCA3 pin becomes a PWM output pin. 1 is output on a compare match of general register A3 (GRA3); 0 is output on a compare match of general register B3 (GRB3). When the complementary PWM mode or resetsynchronized PWM mode are set by the CMD1 and CMD0 bits of the timer function control register (TFCR), the setting of this bit is ignored in favor of the settings of CMD1 and CMD0. Bit 3: PWM3 Description 0 Channel 3 operates normally (initial value) 1 Channel 3 operates in PWM mode • Bit 2 (PWM Mode 2 (PWM2)): PWM2 selects the PWM mode for channel 2. When the PWM2 bit is set to 1 and the PWM mode entered, the TIOCA2 pin becomes a PWM output pin. 1 is output on a compare match of general register A2 (GRA2); 0 is output on a compare match of general register B2 (GRB2). Bit 2: PWM2 Description 0 Channel 2 operates normally (initial value) 1 Channel 2 operates in PWM mode • Bit 1 (PWM Mode 1 (PWM1)): PWM1 selects the PWM mode for channel 1. When the PWM1 bit is set to 1 and the PWM mode entered, the TIOCA1 pin becomes a PWM output pin. 1 is output on a compare match of general register A1 (GRA1); 0 is output on a compare match of general register B1 (GRB1). Bit 1: PWM1 Description 0 Channel 1 operates normally (initial value) 1 Channel 1 operates in PWM mode • Bit 0 (PWM Mode 0 (PWM0)): PWM0 selects the PWM mode for channel 0. When the PWM0 bit is set to 1 and the PWM mode entered, the TIOCA0 pin becomes a PWM output pin. 1 is output on a compare match of general register A0 (GRA0); 0 is output on a compare match of general register B0 (GRB0). Bit 0: PWM0 Description 0 Channel 0 operates normally (initial value) 1 Channel 0 operates in PWM mode RENESAS 229 10.2.4 Timer Function Control Register (TFCR) The timer function control register (TFCR) is an 8-bit read/write register that selects complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation. TFCR is initialized on a reset or standby mode to H'C0 or H'40. Bit: 7 6 5 4 3 2 1 0 Bit name: — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value: * 1 0 0 0 0 0 0 R/W: — — R/W R/W R/W R/W R/W R/W Note: Undefined • Bits 7 and 6 (reserved): Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to bit 7 should be 0 or 1. The write value to bit 6 should always be 1. • Bits 5 and 4 (combination mode 1 and 0 (CMD1 and CMD0)): CMD1 and CMD0 select the complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being used is off. When these bits are used to set the complementary PWM/reset-synchronized PWM mode, they take priority over the PWM4 and PWM3 bits of the TMDR. While the complementary PWM/reset-synchronized PWM mode settings and the SYNC4 and SYNC3 bit settings of the timer synchro register (TSNC) are valid simultaneously, when the complementary PWM mode is set, channels 3 and 4 should not be set to operate simultaneously (SYNC 4 and SYNC 3 bits of TSNC should not both be set to 1). Bit 5: CMD1 Bit 4: CMD0 Description 0 0 Channels 3 and 4 operate normally (initial value) 1 Channels 3 and 4 operate normally 0 Channels 3 and 4 operate together in complementary PWM mode 1 Channels 3 and 4 operate together in reset-synchronized PWM mode 1 • Bit 3 (buffer mode B4 (BFB4)): BFB4 selects the buffer mode for GRB4 and BRB4 in channel 4. Bit 3: BFB4 Description 0 GRB4 operates normally in channel 4 (initial value) 1 GRB4 and BRB4 operate in buffer mode in channel 4 230 RENESAS • Bit 2 (buffer mode A4 (BFA4)): BFA4 selects the buffer mode for GRA4 and BRA4 in channel 4. Bit 2: BFA4 Description 0 GRA4 operates normally in channel 4 (initial value) 1 GRA4 and BRA4 operate in buffer mode in channel 4 • Bit 1 (buffer mode B3 (BFB3)): BFB3 selects the buffer mode for GRB3 and BRB3 in channel 3. Bit 1: BFB3 Description 0 GRB3 operates normally in channel 3 (initial value) 1 GRB3 and BRB3 operate in buffer mode in channel 3 • Bit 0 (buffer Mode A3 (BFA3)): BFA3 selects the buffer mode for GRA3 and BRA3 in channel 3. Bit 0: BFA3 Description 0 GRA3 operates normally in channel 3 (initial value) 1 GRA3 and BRA3 operate in buffer mode in channel 3 10.2.5 Timer Output Control Register (TOCR) The timer output control register (TOCR) is an eight-bit read/write register that inverts the output level of the complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and OLS4 is valid in only the complementary PWM mode and reset-synchronized PWM mode. In other output situations, these bits are ignored. The TOCR is initialized to H'FF or H'7F by a reset or in the standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — — OLS4 OLS3 Initial value: * 1 1 1 1 1 1 1 R/W: — — — — — — R/W R/W Note: Undefined • Bits 7–2 (reserved): Bit 7 is read as undefined. Bits 6–2 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6–2 should always be 1. RENESAS 231 • Bit 1 (output level select 4 (OLS4)): OLS4 selects the output level of the complementary PWM mode or reset-synchronized PWM mode. Bit 1: OLS4 Description 0 TIOCA3, TIOCA4, and TIOCB4 are inverted and output 1 TIOCA3, TIOCA4, and TIOCB4 are output directly (initial value) • Bit 0 (output level select 3 (OLS3)): OLS3 selects the output level of the complementary PWM mode or reset-synchronized PWM mode. Bit 0: OLS3 Description 0 TIOCB3, TOCXA4, and TOCXB4 are inverted and output 1 TIOCB3, TOCXA4, and TOCXB4 are output directly (initial value) 10.2.6 Timer Counters (TCNT) The ITU has five 16-bit timer counters (TCNT), one for each channel (table 10.4). Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock source is selected by timer prescalar bits 2–0 (TPSC2–TPSC0) in the timer control register (TCR). TCNT0 and TCNT 1 are strictly upcounters. Up/down counting occurs for TCNT2 when the phase counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is selected. In other modes, they are upcounters. The TCNT can be cleared to H'0000 by compare match with the corresponding general register A or B (GRA, GRB) or input capture to GRA or GRB (counter clear function). When the TCNT overflows (changes from H'FFFF–H'0000), the overflow flag (OVF) in the timer status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when the TCNT underflows (changes from H'0000–H'FFFF). The TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word access or byte access. The TCNT is initialized to H'0000 by a reset or in standby mode. 232 RENESAS Table 10.4 Timer Counters (TCNT) Channel Abbreviation Function 0 TCNT0 Increment counter 1 TCNT1 2 TCNT2 Phase counting mode: Increment/decrement All others: Increment 3 TCNT3 4 TCNT4 Complementary PWM mode: Increment/decrement All others: Increment Bit: 15 14 13 12 11 10 9 8 Bit name: Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: 10.2.7 General Registers A and B (GRA and GRB) Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers (table 10.5). Each GR is a 16-bit read/write register that can function as either an output compare register or an input capture register. The function is selected by settings in the timer I/O control register (TIOR). When a general register (GRA/GRB) is used as an output compare register, its value is constantly compared with the timer counter (TCNT) value. When the two values match (compare match), the IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected in the TIOR, a specified value is output at the output compare pin. When a general register is used as an input capture register, an external input capture signal is detected and the TCNT value is stored. The IMFA/IMFB bit of the corresponding TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in the TIOR. The TIOR setting is ignored when set for the PWM mode, complementary PWM mode or resetsynchronized PWM mode. RENESAS 233 General registers are connected to the CPU by a 16-bit bus, so general registers can be written or read by either word access or byte access. General registers are initialized to the output compare register (no pin output) by a reset or in standby mode. The initial value is H'FFFF. Table 10.5 General Registers A and B (GRA and GRB) Channel Abbreviation Function 0 GRA0, GRB0 Output compare/input capture dual register 1 GRA1, GRB1 2 GRA2, GRB2 3 GRA3, GRB3 4 GRA4, GRB4 Bit: Output compare/input capture dual register. Can also be set for buffer operation in combination with the buffer registers (BRA, BRB) 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 10.2.8 Buffer Registers A and B (BRA, BRB) Each buffer register is a 16-bit read/write register that is used in the buffer mode. The ITU has four buffer registers, two each for channels 3 and 4 (table 10.6). Buffer operation can be set independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3 bits. The buffer registers are paired with the general registers and their function changes automatically to match the function of its corresponding general register. The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset or in standby mode. 234 RENESAS Table 10.6 Buffer Registers A and B (BRA, BRB) Channel Abbreviation Function 3 BRA3, BRB3 4 BRA4, BRB4 When used for buffer operation: When the corresponding GRA and GRB are output compare registers, the buffer registers function as output compare buffer registers that can automatically transfer the BRA and BRB values to GRA and GRB upon a compare match. When the corresponding GRA and GRB are input capture registers, the buffer registers function as input capture buffer registers that can automatically transfer the values stored until an input capture in the GRA and GRB to the BRA and BRB. Bit: 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 10.2.9 Timer Control Register (TCR) The TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the external clock source, and the counter clear source. Each ITU channel has one TCR. TCR is initialized H'80 or H'00 by a reset or the standby mode (table 10.7). Table 10.7 Timer Control Register (TCR) Channel Abbreviation 0 TCR0 1 TCR1 2 TCR2 3 TCR3 4 TCR4 Function The TCR controls the TCNTs. The TCRs have the same functions on all channels. When channel 2 is set for phase counting mode, setting the CKEG1, CKEG2 and TPSC2–TPSC0 bits will have no effect. RENESAS 235 Bit: 7 6 5 4 Bit name: — CCLR1 CCLR0 Initial value: * 0 0 0 R/W: — R/W R/W R/W 3 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 0 R/W R/W R/W R/W CKEG1 CKEG0 Note: Undefined • Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1. • Bits 6 and 5 (counter clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the counter clear source. Bit 6: Bit 5: CCLR1 CCLR0 Description 0 1 0 TCNT is not cleared (initial value) 1 TCNT is cleared by general register A (GRA) compare match or input capture* 1 0 TCNT is cleared by general register B (GRB) compare match or input capture* 1 1 Synchronizing clear: TCNT is cleared in synchronization with clear of other timer counters operating in sync.* 2 Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a compare match. When functioning as an input capture register, TCNT is cleared upon input capture. 2. The timer synchro register (TSNC) set the synchronization. • Bits 4 and 3 (external clock edge 1/0 (CKEG1 and CKEG0)): CKEG1 and CKEG0 select external clock input edges. When channel 2 is set for phase counting mode, settings of the CKEG1 and CKEG0 of the TCR are ignored and the phase counting mode operation takes priority. Bit 4: CKEG 1 Bit 3: CKEG 0 Description 0 0 Count rising edges (initial value) 1 Count falling edges — Count both rising and falling edges 1 • Bits 2–0 (timer prescalar 2–0 (TPS2–TPS0)): TPS2–TPS0 select the counter clock source. When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges. When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and CKEG0. When the phase counting mode is selected for channel 2 (MDF bit in the timer mode register is 1), the settings of TPSC2–TPSC0 of TCR2 are ignored and the phase counting operation takes priority. 236 RENESAS Bit 2: Bit 1: Bit 0: TPSC2 TPSC1 TPSC0 Counter Clock (and cycle when φ = 10 MHz) 0 0 1 1 0 1 10.2.10 0 Internal clock φ (initial value) 1 Internal clock φ/2 0 Internal clock φ/4 1 Internal clock φ/8 0 External clock A (TCLKA) 1 External clock B (TCLKB) 0 External clock C (TCLKC) 1 External clock D (TCLKD) Timer I/O Control Register (TIOR) The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output compare or input capture function for the general registers GRA and GRB. It also selects the function of the TIOCA and TIOCB pins. If output compare is selected, the TIOR also selects the output settings. If input capture is selected, the TIOR also select the input capture edges. TIOR is initialized to H'88 or H'08 on a reset or standby mode. Each ITU channel has one TIOR (table 10.8). Table 10.8 Timer I/O Control Register (TIOR) Channel Abbreviation 0 TIOR0 1 TIOR1 2 TIOR2 3 TIOR3 4 TIOR4 Function The TIOR controls the GRs. Some functions vary during PWM. When channels 3 and 4 are set for complementary PWM mode/reset-synchronized PWM mode, TIOR3 and TIOR4 settings are not valid. Bit: 7 6 5 4 3 2 1 0 Bit name: — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value: * 0 0 0 1 0 0 0 R/W: — R/W R/W R/W — R/W R/W R/W Note: Undefined • Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1. RENESAS 237 • Bits 6–4 (I/O control B2–B0 (IOB2–IOB0)): IOB2–IOB0 selects the GRB function. Bit 6: IOB2 Bit 5: IOB1 Bit 4: IOB0 0 0 0 1 1 0 GRB Function GRB is an Compare match with pin output disabled (initial value) output compare 0 output at GRB compare match* 1 register 1 output at GRB compare match* 1 1 1 0 0 1 1 0 Output toggles at GRB compare match (1 output for channel 2 only)* 1,* 2 GRB is an input capture register GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input 1 Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output. • Bit 3 (reserved): Bit 3 always reads as 1. The write value should always be 1. • Bits 2–0 (I/O control A2–A0 (IOA2–IOA0)): IOA2–IOA0 select the GRB function. Bit 2: IOA2 Bit 1: IOA1 Bit 0: IOA0 0 0 0 1 1 0 GRA Function GRA is an Compare match with pin output disabled (initial value) output compare 0 output at GRA compare match* 1 register 1 output at GRA compare match* 1 1 1 0 0 1 1 0 Output toggles at GRA compare match (1 output for channel 2 only)* 1,* 2 GRA is an input capture register GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input 1 Notes: 1. After reset, the value output is 0 until the first compare match occurs. 2. Channel 2 has no compare-match driven toggle output function. If it is set for toggle, 1 is automatically selected as the output. 238 RENESAS 10.2.11 Timer Status Register (TSR) The timer status register (TSR) is an eight-bit read/write register containing flags that indicate timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER), an interrupt is requested of the CPU. TSR is initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TSR (table 10.9). Table 10.9 Timer Status Register (TSR) Channel Abbreviation Function 0 TSR0 1 TSR1 The TSR indicates input capture, compare match and overflow status. 2 TSR2 3 TSR3 4 TSR4 Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — OVF IMFB IMFA Initial value: *1 1 1 1 1 0 0 0 R/W: — — — — — R/(W)*2 R/(W)*2 R/(W)*2 Notes: 1. Undefined 2. Write 0 to clear the flag. • Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1. • Bit 2 (overflow flag (OVF)): OVF indicates a TCNT overflow/underflow has occurred. Bit 2: OVF Description 0 Clearing condition: Read OVF when OVF = 1, then write 0 in OVF (initial value) 1 Setting condition: TCNT overflowed from H'FFFF–H'0000 or underflowed from H'0000–H'FFFF. Note: A TCNT underflow occurs when the TCNT up/down counter is functioning. It may occur in the following cases: (1) When channel 2 is set in the phase counting mode (MDF bit of TMDR is 1), or (2) When channel 3 and 4 are set to the complementary PWM mode (CMD1 bit of TFCR is 1 and CMD0 bit is 0). RENESAS 239 • Bit 1 (input capture/compare match B (IMFB)): IMFB indicates a GRB compare match or input capture. Bit 1: IMFB Description 0 Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB (initial value) 1 Setting condition: • GRB is functioning as an output compare register and TCNT = GRB • GRB is functioning as an input capture register and the value of TCNT is transferred to GRB by an input capture signal • Bit 0 (input capture/compare match A (IMFA)): IMFA indicates a GRA compare match or input capture. Bit 0: IMFA Description 0 Read IMFA when IMFA = 1, then write 0 in IMFA (initial value). Clearing condition: DMAC is activated by an IMIA interrupt (only channels 0–3) 1 Setting condition: • GRA is functions as an output compare register and TCNT = GRA • GRA is functioning as an input capture register and the value of TCNT is transferred to GRA by an input capture signal 10.2.12 Timer Interrupt Enable Register (TIER) The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls enabling/disabling of overflow interrupt requests and general register compare match/input capture interrupt requests. TIER is initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TIER (table 10.10). Table 10.10 Timer Interrupt Enable Register (TIER) Channel Abbreviation Function 0 TIER0 The TIER controls interrupt enable/disable. 1 TIER1 2 TIER2 3 TIER3 4 TIER4 240 RENESAS Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — OVIE IMIEB IMIEA Initial value: * 1 1 1 1 0 0 0 R/W: — — — — — R/W R/W R/W Note: Undefined • Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1. • Bit 2 (overflow interrupt enable (OVIE)): When the TSR overflow flag (OVF) is set to 1, OVIE enables or disables interrupt requests from the OVF. Bit 2: OVIE Description 0 Disables interrupt requests by the OVF (initial value) 1 • Enables interrupt requests from the OVF Bit 1 (input capture/compare match interrupt enable B (IMIEB)): When the IMFB bit of the TSR is set to 1, IMIEB enables or disables the interrupt requests from the IMFB. Bit 1: IMIEB Description 0 Disables interrupt requests by the IMFB (IMIB) (initial value) 1 Enables interrupt requests from the IMFB (IMIB) • Bit 0 (input capture/compare match interrupt enable A (IMIEA)): When the IMFA bit of the TSR is set to 1, IMIEA enables or disables the interrupt requests from the IMFA. Bit 0: IMIEA Description 0 Disables interrupt requests by the IMFA (IMIA) (initial value) 1 Enables interrupt requests from the IMFA (IMIA) 10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B (BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a 16-bit data bus. Byte access is also possible. Read and write operations performed on the TCNT in word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and TCNTL are shown in figures 10.8–10.11. RENESAS 241 Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.6 Accessing TCNT (CPU–TCNT (word)) Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.7 Accessing TCNT (TCNT–CPU (word)) Internal data bus H H CPU L Bus interface L TCNTH TCNTL Figure 10.8 Accessing TCNT (CPU–TCNT (upper byte)) 242 RENESAS Module data bus Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.9 Accessing TCNT (CPU–TCNT (lower byte)) Internal data bus H H CPU Bus interface L L TCNTH Module data bus TCNTL Figure 10.10 Accessing TCNT (TCNT–CPU (upper byte)) Internal data bus H H CPU L Bus interface L TCNTH Module data bus TCNTL Figure 10.11 Accessing TCNT (TCNT–CPU (lower byte)) 10.3.2 8-Bit Accessible Registers All registers other than the TCNT, general registers, and buffer registers are 8-bit registers. These are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and writing in byte units with the timer control register (TCR). These registers must be accessed by byte access. RENESAS 243 Internal data bus Module data bus Bus interface CPU TCR Figure 10.12 TCR Access (CPU–TCR) Internal data bus CPU Module data bus Bus interface TCR Figure 10.13 TCR Access (TCR–CPU ) 10.4 Description of Operation 10.4.1 Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers A and B (GRA and GRB) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs of other channels are simultaneously rewritten as well. The CCLR1 and CCLR0 bits of the timer control register of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously. 244 RENESAS PWM Mode: In PWM mode, a PWM waveform is output from the TIOCA pin. Output becomes 1 upon compare match A and 0 upon compare match B. GRA and GRB can be set so that the PWM waveform output has a duty cycle between 0% and 100%. When set for PWM mode, the GRA and GRB automatically become output compare registers. Reset-synchronized PWM Mode: Three pairs of positive and negative PWM waveforms can be obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point on one side). When set for reset-synchronized PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also automatically become PWM output pins and TCNT3 becomes an upcounter. TCNT4 functions independently (although GRA and GRB are isolated from TCNT4). Complementary PWM Mode: Three pairs of complementary positive and negative PWM waveforms whose positive and negative phases do not overlap can be obtained using channels 3 and 4. When set for complementary PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins also automatically become PWM output pins while TCNT3 and TCNT4 become upcounters. Phase Counting Mode: In phase counting mode, the phase differential between two clocks input from the TCLKA and TCLKB pins is detected and the TCNT2 operates as an up/downcounter. In phase counting mode, the TCLKA and TCLKB pins become clock inputs and TCNT2 functions as an up/downcounter. Buffer Mode: • • • • When GR is an output compare register: The BR value of each channel is transferred to the GR when a compare match occurs. When GR is an input capture register: The TCNT value is transferred to the GR when an input capture occurs and simultaneously the value previously stored in the GR is transferred to the BR. Complementary PWM mode: When the TCNT3 and TCNT4 change count directions, the BR value is transferred to the GR. Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare match. 10.4.2 Basic Functions Counter Operation: When a start bit (STR0–STR4) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode. RENESAS 245 • Procedure for selecting counting mode (figure 10.14): 1. Set bits TPSC2–TPSC0 in the TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in the TCR to select the desired edges of the external clock signal. 2. To operate as a periodic counter, set CCLR1 and CCLR0 in the TCR to select whether to clear the TCNT at GRA compare match or GRB compare match. 3. Set the GRA or GRB selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the GRA or GRB selected in step 1. 5. Set the STR bit in the TSTR to 1 to start counting. Counting mode selection Select counter clock Counting? (1) No Yes Free-running counter Periodic counter Select counter clear source (2) Select output compare register (3) Set period (4) Start counting (5) Periodic counter Start counting Free-running counter Figure 10.14 Procedure for Selecting the Counting Mode 246 RENESAS (5) • Free-running count and periodic count A reset of the counters for channels 0–4 leaves them all in the free-running mode. When a corresponding bit in the TSTR is set to 1, the corresponding timer counter operates as a freerunning counter and begins to increment. When the count wraps around from H'FFFF–H'0000, the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit in the timer’s corresponding interrupt enable register (TIER) is set to 1, the CPU will be asked for an interrupt. After the TCNT overflows, counting continues from H'0000. Figure 10.15 shows an example of free-running counting. Periodic counter operation is obtained for a given channel’s TCNT by selecting compare match as a TCNT clear source. (Set the GRA or GRB for period setting to output compare register and select counter clear upon compare match using the CCLR1 and CCLR0 bits of the timer control register (TCR).) After setting, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the count matches GRA or GRB, the IMFA/IMFB bit in the TSR is set to 1 and the counter is automatically cleared to H'0000. If the IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, the CPU will be asked for an interrupt. After the compare match, TCNT continues counting from H'0000. Figure 10.16 shows an example of periodic counting. TCNT value H'FFFF H'0000 Time STR0–STR4 OVF Figure 10.15 Free-Running Counter Operation RENESAS 247 Counter cleared by GR compare match TCNT value GR H'0000 Time STR0–STR4 IMF Figure 10.16 Periodic Counter Operation • TCNT counter timing Internal clock source: Bits TPSC2–TPSC0 in the TCR select the system clock (CK) or one of three internal clock sources (φ/2, φ/4, φ/8) obtained by prescaling the system clock. Figure 10.17 shows the timing. External clock source: The external clock input pin (TCLKA–TCLKD) source is selected by bits TPSC2–TPSC0 in the TCR and its valid edges are selected with the CKEG1 and CKEG0 bits of the TCR. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10.18 shows the timing when both edges are detected. CK Internal clock TCNT input clock TCNT value N–1 N Figure 10.17 Count Timing for Internal Clock Sources 248 RENESAS N+1 CK External clock input pin TCNT input clock TCNT N–1 N N+1 Figure 10.18 Count Timing for External Clock Sources Compare-Match Waveform Output Function: For ITU channels 0, 1, 3, and 4, the output from the corresponding TIOCA and TIOCB pins upon compare matches A and B can be in three modes: 0-level output, 1-level output, or toggle. Toggle output cannot be selected in channel 2. • Procedure for selecting the waveform output mode (figure 10.19): 1. Set the TIOR to select 0 output, 1 output, or toggle output for compare match output. The compare match output pin will output 0 until the first compare match occurs. 2. Set a value in the GRA or GRB to select the compare match timing. 3. Set the STR bit in the TSTR to 1 to start counting. Output selection Select waveform output mode (1) Select output timing (2) Start counting (3) Waveform output Figure 10.19 Procedure for Selecting the Compare Match Waveform Output Mode RENESAS 249 • Waveform output operation Figure 10.20 illustrates 0 output/1 output. In the example, TCNT is a free-running counter, 0 is output upon compare match A and 1 is output upon compare match B. When the pin level matches the set level, the pin level does not change. Figure 10.21 shows an example of toggle output. In the figure, the TCNT operates as a periodic counter cleared by GRB compare match with toggle output at both compare match A and compare match B. TCNT value H'FFFF GRB GRA Time TIOCB Does not change Does not change 1 output TIOCA Does not change Does not change Figure 10.20 Example of 0 Output/1 Output 250 RENESAS 0 output TCNT value Counter cleared at GRB compare match GRB GRA Time TIOCB Toggle output TIOCA Toggle output Figure 10.21 Example of Toggle Output RENESAS 251 • Compare match output timing The compare match signal is generated in the last state in which the TCNT and the general register match (when the TCNT changes from the matching value to the next value). When a compare match signal is generated, the output value set in TIOR is output to the output compare pin (TIOCA, TIOCB). Accordingly, when the TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 10.22 shows the output timing of the compare match signal. CK TCNT input clock TCNT N GR N N–1 Compare match signal TIOCA TIOCB Figure 10.22 Compare Match Signal Output Timing 252 RENESAS Input Capture Mode: In the input capture mode, the counter value is captured into a general register when the input edge is detected at an input capture/output compare pin (TIOCA, TIOCB). Detection can take place on the rising edge, falling edge, or both edges. Pulse width and cycle can be measured by using the input capture function. • Procedure for selecting the input capture mode (figure 10.23) 1. Set the TIOR to select the input capture function of the GR and select the rising edge, falling edge, or both edges as the input edge of the input capture signal. Put the corresponding port into input-capture using the pin function controller before setting the TIOR. 2. Set the STR bit in the TSTR to 1 to start the TCNT counting. Input selection Select input-capture input Start counting Capture Figure 10.23 Procedure for Selecting Input Capture Mode RENESAS 253 • Input capture operation Figure 10.24 illustrates input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture edges. In the example, TCNT is set to clear at the input capture of GRB. TCNT value Counter cleared by TIOCB input (falling edge) H'0180 H'0160 H'0005 H'0000 Time TIOCB TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 10.24 Input Capture Operation 254 RENESAS • Input capture timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in the TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. CK Input capture input Input capture signal TCNT N GRA/GRB N Figure 10.25 Input Capture Signal Timing RENESAS 255 10.4.3 Synchronizing Mode In the synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR settings (synchronized clear). The synchronizing mode can increase the general registers for a single time base. All five channels can be set for synchronous operation. Procedure for Selecting the Synchronizing Mode (figure 10.26): 1. Set 1 in the SYNC bit of the timer synchro register (TSNC) to use the channels in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with compare match/input capture using bits CCLR1 and CCLR0 in the TCR. 4. Set the counter clear source to synchronized clear using the CCLR1 and CCLR0 bits. 5. Set the STR bits in the TSTR to 1 to start counting in the TCNT. Select synchronizing mode Set synchronizing mode (1) Synchronized preset Set TCNT Synchronized clear (2) Channel that generated clear source? Yes No Select counter clear source (3) Select counter clear source (4) Start counting (5) Start counting (5) Synchronizing preset Counter clear Synchronized clear Figure 10.26 Procedure for Selecting the Synchronizing Mode 256 RENESAS Synchronized Operation: Figure 10.27 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM output. Channel 0 is set for a counter clear upon compare match with GRB0. Channels 1 and 2 are set for counter clears by synchronizing clears. Accordingly, their timers are sync preset, then sync cleared by a GRB0 compare match, and then a three-phase PWM waveform is output from the TIOCA0, TIOCA1 and TIOCA2 pins. See section 10.4.4, PWM Mode, for details on the PWM mode. TCNT0–TCNT2 values Synchronized clear on GRB0 compare match GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Time TIOCA0 TIOCA1 TIOCA2 Figure 10.27 Synchronized Operation Example RENESAS 257 10.4.4 PWM Mode The PWM mode is controlled using both the GRA and GRB in pairs. The PWM waveform is output from the TIOCA output pin. The PWM waveform’s 1 output timing is set in GRA and the 0 output timing is set in GRB. A PWM waveform with duty cycle between 0% and 100% can be output from the TIOCA pin by having either compare match GRA or GRB be the counter clear source for the timer counter. All five channels can be set to PWM mode. Table 10.11 lists the combinations of PWM output pins and registers. Note that when the GRA and GRB are set to the same value, the output will not change even if a compare match occurs. Table 10.11 Combinations of PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output 0 TIOCA0 GRA0 GRB0 1 TIOCA1 GRA1 GRB1 2 TIOCA2 GRA2 GRB2 3 TIOCA3 GRA3 GRB3 4 TIOCA4 GRA4 GRB4 Procedure for Selecting the PWM Mode (figure 10.28): 1. Set bits TPSC2–TPSC0 in the TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in the TCR to select the desired edges of the external clock signal. 2. Set CCLR1 and CCLR0 in the TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in the GRA. 4. Set the time at which the PWM waveform should go to 0 in the GRB. 5. Set the PWM bit in TMDR to select the PWM mode. When the PWM mode is selected, regardless of the contents of TIOR, the GRA and GRB become output compare registers specifying the times at which the PWM waveform goes high and low. TIOCA automatically becomes a PWM output pin. TIOCB becomes whatever is set in the TIOR's IOB1 and IOB0 bits. 6. Set the STR bit in the TSTR to let the TCNT start counting. 258 RENESAS PWM mode Select counter clock (1) Select counter clear source (2) Set GRA (3) Set GRB (4) Select PWM mode (5) Start counting (6) PWM mode Figure 10.28 Procedure for Selecting the PWM Mode PWM Mode Operation: Figure 10.29 illustrates PWM mode operations. When the PWM mode is set, the TIOCA pin becomes the output pin. Output is 1 when the TCNT matches the GRA, and 0 when the TCNT matches the GRB. The TCNT can be cleared by compare match with either GRA or GRB. This can be used in both free-running and synchronized operation. Figure 10.30 shows examples of PWM waveforms output with 0% and 100% duty cycles. A 0% duty waveform can be obtained by setting the counter clear source to GRB and then setting GRA to a larger value than GRB. A 100% duty waveform can be obtained by setting the counter clear source to GRA and then setting GRB to a larger value than GRA. RENESAS 259 TCNT value Counter cleared by GRA compare match GRA GRB Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by GRB compare match GRB GRA Time TIOCA b. Counter cleared by GRB Figure 10.29 PWM Mode Operation Example 1 260 RENESAS TCNT value Counter cleared on compare match B GRB GRA Time H'0000 TIOCA GRA write GRA write a. 0% duty TCNT value Counter cleared on compare match A GRA GRB Time H'0000 TIOCA GRB write GRB write b. 100% duty Figure 10.30 PWM Mode Operation Example 2 RENESAS 261 10.4.5 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three pairs of complementary positive and negative PWM waveforms that share a common wave turning point can be obtained using channels 3 and 4. When set for reset-synchronized PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins automatically become PWM output pins and TCNT3 becomes an upcounter. Table 10.12 shows the PWM output pins used and table 10.13 shows the settings of the registers used. Table 10.12 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description 3 TIOCA3 PWM output 1 TIOCB3 PWM output 1' (negative-phase waveform of PWM output 1) TIOCA4 PWM output 2 TOCXA4 PWM output 2' (negative-phase waveform of PWM output 2) TIOCB4 PWM output 3 TOCXB4 PWM output 3' (negative-phase waveform of PWM output 3) 4 Table 10.13 Register Settings for Reset-Synchronized PWM Mode Register Description of Contents TCNT3 Initial setting of H'0000 TCNT4 Not used (functions independently) GRA3 Set count cycle for TCNT3 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins Procedure for Selecting the Reset-Synchronized PWM Mode (figure 10.31): 1. Clear the STR3 bits in the TSTR to halt TCNT3. The reset-synchronized PWM mode must be set up while TCNT3 is halted. 2. Set bits TPSC2–TPSC0 in the TCR to select the counter clock source for channel 3. If an external clock source is selected, select the external clock edges with bits CKEG1 and CKEG0 in the TCR. 3. Set bits CCLR1 and CCLR0 in the TCR3 to select GRA3 as a counter clear source. 4. Set bits CMD1 and CMD0 in TMDB to select the reset-synchronized PWM mode. TIOCA3– TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins. 262 RENESAS 5. Reset the TCNT3 (to H'0000). The TCNT4 need not be set. 6. The GRA3 is the waveform period register. Set the waveform period value in the GRA3. Set the transition times of the PWM output waveforms in the GRB3, GRA4, and GRB4. Set times within the compare match range of the TCNT3. X ≤ GRA3 (X: setting value) 7. Set the STR3 bits in the TSTR to 1 to let the TCNT3 start counting. Reset synchronized PWM mode Stop counting (1) Select counter clock (2) Select counter clear source (3) Select reset-synchronized PWM mode (4) Set TCNT (5) Set general registers (6) Start counting (7) Reset-synchronized PWM mode Figure 10.31 Procedure for Selecting the Reset-Synchronized PWM Mode RENESAS 263 Reset-Synchronized PWM Mode Operation: Figure 10.32 shows an example of operation in the reset-synchronized PWM mode. TCNT3 operates as an upcounter that is cleared to H'0000 at compare match with GRA3. TCNT4 runs independently and is isolated from GRA4 and GRB4. The PWM waveform outputs toggle at each compare match (GRB3, GRA3, and GRB4 with TCNT3) and when the counter is cleared. See section 10.4.8, Buffer Mode, for details on simultaneously setting reset-synchronized PWM mode and buffer operation. TCNT value Counter cleared at GRA3 compare match GRA3 GRB3 GRA4 GRB4 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10.32 Reset-Synchronized PWM Mode Operation Example 1 10.4.6 Complementary PWM Mode In the complementary PWM mode, three pairs of complementary, non-overlapping, positive and negative PWM waveforms can be obtained using channels 3 and 4. In complementary PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 pins automatically become PWM output pins and TCNT3 and TCNT4 become upcounters. Table 10.14 shows the PWM output pins used and table 10.15 shows the settings of the registers used. 264 RENESAS Table 10.14 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOCA3 PWM output 1 TIOCB3 PWM output 1' (non-overlapping negative-phase waveform of PWM output 1) TIOCA4 PWM output 2 TOCXA4 PWM output 2' (non-overlapping negative-phase waveform of PWM output 2) TIOCB4 PWM output 3 TOCXB4 PWM output 3' (non-overlapping negative-phase waveform of PWM output 3) 4 Table 10.15 Register Settings for Complementary PWM Mode Register Description of Contents TCNT3 Initial setting of non-overlap cycle (the difference with TCNT4) TCNT4 Initial setting of H'0000 GRA3 Set upper limit of TCNT3–1 GRB3 Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins. GRA4 Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins. GRB4 Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins. Procedure for Selecting the Complementary PWM Mode (figure 10.33): 1. Clear STR3 and STR4 bits in the TSTR to halt the timer counters. The complementary PWM mode must be set up while TCNT3 and TCNT4 are halted. 2. Set bits TPSC2–TPSC0 in the TCR to select the same counter clock source for channels 3 and 4. If an external clock source is selected, select the external clock edges with bits CKEG1 and CKEG0 in the TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in the TCR. 3. Set bits CMD1 and CMD0 in TMDB to select the complementary PWM mode. TIOCA3– TIOCB4, TOCXA4, and TOCXB4 automatically become PWM pins. 4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and TCNT4 to the same value. RENESAS 265 5. GRA3 is the waveform period register. Set the upper limit of TCNT3–1*. Set the transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4. T≤X (X: initial setting of GRB3, GRA4, and GRB4; T: initial setting of TCNT3) Note: GRA3 = [cycle count/2] + [count of non-overlaps] – 2cyc=[upper limit of TCNT3] – 1 6. Set the STR3 and STR4 bits in the TSTR to 1 to let TCNT3 and TCNT4 start counting. Complementary PWM mode Stop counting (1) Select counter clock (2) Select complementary PWM mode (3) Set TCNT (4) Set general registers (5) Start counting (6) Complementary PWM mode Note To re-engage the complementary PWM mode after it has been aborted, start settings from step 1. Figure 10.33 Procedure for Selecting the Complementary PWM Mode Complementary PWM Mode Operation: Figure 10.34 shows an example of operation in the complementary PWM mode. TCNT3 and TCNT4 operate as up/downcounters, counting down from compare match of TCNT3 and GRA3 and counting up when TCNT4 underflows. PWM waveforms are output by repeated compare matches with each of the general registers in the 266 RENESAS sequence TCNT3, TCNT4, TCNT4, TCNT3 (in this mode, TCNT3 starts out larger than TCNT4). Figure 10.35 shows examples of PWM waveforms with 0% and 100% duty cycles (in one phase) in the complementary PWM mode. In this example, the pin output changes upon GRB3 compare match, so duty cycles of 0% and 100% can be obtained by setting GRB3 to a value larger than GRA3. Combining buffer operation with the above operation makes it easy to change the duty while operating. See section 10.4.8, Buffer Operation, for details. TCNT3, TCNT4 value GRA3 Down-counting starts at compare match between TCNT3 and GRA3 TCNT3 GRB3 GRA4 GRB4 TCNT4 Time Up-counting starts at TCNT4 underflow TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10.34 Complementary PWM Mode Operation Example 1 RENESAS 267 TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 Duty 0% (a) With 0% duty TCNT3, TCNT4 value GRA3 GRB3 Time TIOCA3 TIOCB3 Duty 100% (b) With 100% duty Figure 10.35 Complementary PWM Mode Operation Example 2 At the point where the up-count/down-count changes in the complementary PWM mode, TCNT3 and TCNT4 will overshoot and undershoot, respectively. When this occurs, the setting conditions for the IMFA bit of channel 3 and the overflow flag (OVF) of channel 4 are different from usual. Transfer conditions for the buffer also differ. The timing is as shown in figures 10.36 and 10.37. 268 RENESAS TCNT3 N–1 N N+1 N N–1 N GRA3 Flag not set IMFA Set to 1 Buffer transfer signal (BR to GR) GR Buffer transfer performed Buffer transfer not performed Figure 10.36 Overshoot Timing Underflow TCNT4 H' 0001 H' 0000 H' FFFF Overflow H' 0000 Flag not set OVF Set to 1 Buffer transfer signal (BR to GR) GR Buffer transfer performed Buffer transfer not performed Figure 10.37 Undershoot Timing RENESAS 269 The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1 for underflows only. The buffer register (BR) set for the buffer operation is transferred to the GR upon compare match A3 (when incrementing) or TCNT4 underflow. GR Setting in Complementary Mode: Be aware of the following when setting the general registers in complementary PWM mode and when making changes during operation. • • • Initial values: Setting H'0000 to T–1 (the initial setting T: TCNT3) is prohibited. After counting starts, this setting is allowed from the point when the first A3 compare match occurs. Methods of changing settings: Use the buffer operation. Writing directly to general registers may result in incorrect waveform output. When changing settings: See figure 10.38. GRA3 GR H' 0000 Prohibited BR GR Figure 10.38 Example of Changing GR Settings with Buffer Operation (1) 270 RENESAS Buffer Transfers when Changing from Increment to Decrement: When the contents of the GR are within GRA3 – T + 1 and GRA3, do not transfer a value outside this range. When the contents of GR are outside this range, do not a transfer a value within it. Figure 10.39 illustrates a point of caution regarding changing of GR settings with a buffer operation. GRA3 + 1 GRA3 Changes inhibited TCNT3 GRA3 – T + 1 GRA3 – T TCNT4 Figure 10.39 Caution for Changing GR Settings with Buffer Operation (1) Buffer Transfers when Changing from Decrement to Increment: When the contents of the GR are within H'0000 to T–1, do not transfer a value outside this range. When the contents of GR are outside this range, do not transfer a value within it. Figure 10.40 illustrates this point of caution regarding changing of GR settings with a buffer operation TCNT3 TCNT4 T T–1 Changes inhibited H' 0000 H' FFFF Figure 10.40 Caution for Changing GR Settings with Buffer Operation (2) When GR Settings are Outside the Count Range (H'0000–GRA3): Waveforms of duty cycle 0% and 100% can be output by setting GR outside the count area. Be sure to make the direction of the count (increment/decrement) when writing a setting from outside the count area into the buffer register (BR) the same as the count direction when writing the setting that returns to within the count area in the BR. RENESAS 271 GRA3 GR H' 0000 Duty 0% Duty 100% Output pin Output pin BR GR Write on decrement Write on increment Figure 10.41 Example of Changing GR Settings with Buffer Operation (2) The above settings are made by detecting the occurrence of a GRA3 compare match or underflow of TCNT4 and then writing to BR. They can also be accomplished by starting up the DMAC with a GRA3 compare match. 10.4.7 Phase Counting Mode The phase counting mode detects the phase differential of two external clock inputs (TCLKA and TCLKB) and counts TCNT2 up or down. When set in the phase counting mode, the TCLKA and TCLKB pins automatically become external clock input pins, regardless of the settings of the TPSC2–TPSC0 bits of TCR2 or the CKEG1 and CKEG0 bits. TCNT2 also becomes an up/down counter. Since the TCR2 CCLR1/CCLR0 bits, TIOR2, TIER2, TSR2, GRA2 and GRB2 are all enabled, input capture and compare match functions and interrupt sources can be used. Phase counting is available only in channel 2. Procedure for Selecting the Phase Counting Mode: Figure 10.42 shows the procedure for selecting the phase counting mode. 1. Set the MDF bit of the timer mode register (TMDR) to 1 to select the phase counting mode. 2. Select the flag set conditions using the FDIR bit of the TMDR. 3. Set the STR2 bit of the timer start register (TSTR) to 1 to start the count. 272 RENESAS Phase counting mode Select phase counting mode (1) Select flag setting condition (2) Start counting (3) Phase counting mode Figure 10.42 Procedure for Selecting the Phase Counting Mode Phase Counting Operation: Figure 10.43 shows an example of phase counting mode operation. Table 10.16 lists the upcounting and downcounting conditions for TCNT2. The ITU counts on both rise and fall edges of TCLKA and TCLKB. The phase differential and overlap of TCLKA and TCLKB must be 1.5 cycles or more and the pulse width must be 2.5 cycles or more. TCNT2 value Increment Decrement TCNT2 Time TCLKB TCLKA Figure 10.43 Phase Counting Mode Operation Table 10.16 Up/Down Counting Conditions Counting Direction Increment TCLKB Rising High Falling Low Rising High Falling Low TCLKA Low Rising High Falling High Falling Low Rising Decrement RENESAS 273 Phase differential Phase differential Pulse width Pulse width TCLKA TCLKB Overlap Overlap Phase differential, overlap: 1.5 cycles minimum Pulse width: 2.5 cycles minimum Figure 10.44 Phase Differentials, Overlap and Pulse Width in the Phase Counting Mode 10.4.8 Buffer Mode In the buffer mode, the buffer operation functions differ depending on whether the general registers are set to output compare or input capture, the reset-synchronized PWM mode, or complementary PWM mode. The buffer mode is a function of channels 3 and 4 only. Buffer operations set this way function as follows. GR is an Output Compare Register: The value of the buffer registers of a channel is transferred to the GR when the channel experiences a compare match. This is illustrated in figure 10.45. Compare match signal BR GR Comparator TCNT Figure 10.45 Compare Match Buffer Operation GR is an Input Capture Register: TCNT values are transferred to GR when input capture occurs and the value previously stored in GR is transferred to BR. This operation is illustrated in figure 10.46. 274 RENESAS Input capture signal BR GR TCNT Figure 10.46 Input Capture Buffer Operation Complementary PWM Mode: When the count direction of TCNT3 and TCNT4 change, the BR value is transferred to the GR. The following timing is employed for this transfer: • • Whenever TCNT3 and GRA3 compare-match Whenever TCNT4 underflows Reset-Synchronized PWM Mode: The BR value is transferred to GR upon a GRA3 compare match. Procedure for Selecting the Buffer Mode (figure 10.47): 1. Set the TIOR to select the output compare or input capture function of the GR. 2. Set bits BFA3, BFB3 and BFB4 in the TFCR to select the buffer mode for the GR. 3. Set the STR bit in the TSTR to 1 to start the TCNT counting. Buffer mode Select general register function (1) Select buffer mode (2) Start counting (3) Buffer mode Figure 10.47 Procedure for Selecting the Buffer Mode RENESAS 275 Buffer Mode Operation: Figure 10.48 shows an example of an operation in the buffer mode with GRA set as an output compare register and GRA and buffer register A (BRA) set for buffer operation. The TCNT operates as a periodic counter that is cleared by GRB compare match. TIOCA and TIOCB are set to toggle at compare matches A and B. Since buffer mode is selected, when TIOCA toggles at a compare match A, the BRA value is simultaneously transferred to the GRA. This operation is repeated at every compare match A. The transfer timing is shown in figure 10.49. Counter cleared by compare match B TCNT value GRB H' 0250 H' 0200 H' 0100 H' 0000 Time BRA H' 0200 GRA H' 0250 H' 0100 H' 0200 H' 0200 H' 0100 H' 0200 Toggle output TIOCB TIOCA Toggle output Compare match A Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register) 276 RENESAS CK TCNT n n+1 Compare match signal Buffer transfer signal BR GR N n N Figure 10.49 Compare Match Timing Example for Buffer Operation RENESAS 277 Figure 10.50 shows an example of input capture operation in the buffer mode between GRA and BRA with GRA as an input capture register. The TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is transferred to the BRA. The timing is shown in figure 10.51. TCNT value Counter cleared at input capture B H' 0180 H' 0160 H' 0005 Time TIOCB TIOCA GRA H' 0005 H' 0160 H' 0005 BRA H' 0160 H' 0180 GRB Input capture A Figure 10.50 Buffer Mode Operation Example 2 (Input Capture Register) 278 RENESAS CK TIOC pin Input capture signal n TCNT n+1 M GR BR N n m N+1 n M N M n Figure 10.51 Input Capture Timing Example for Buffer Operation An example of buffer operation in the complementary PWM mode between GRB3 and BRB3 is as shown in figure 10.52. By making GRB3 larger than GRA3 using the buffer operation, a PWM waveform with a duty cycle of 0% is generated. The transfer from BRB–GRB occurs upon TCNT3 and GRA compare match and TCNT4 underflow. TCNT3 and TCNT4 values TCNT3 GRB3 H' 1FFF GRA3 H' 0999 TCNT4 H' 0000 Time BRB3 H' 0999 GRB3 H' 0999 H' 1FFF H' 0999 H' 1FFF H' 0999 H' 1FFF H' 0999 TIOCA3 TIOCB3 Figure 10.52 Buffer Operation 4 (Complementary PWM Mode) RENESAS 279 10.4.9 ITU Output Timing ITU outputs in channels 3 and 4 can be inverted with the TOCR. Output Inversion Timing with the TOCR: Output levels can be inverted by inverting the output level select bits (OLS4 and OLS3) of the TOCR in the complementary PWM mode and resetsynchronized PWM mode. Figure 10.53 illustrates the timing. T1 T2 T3 CK Address TOCR address TOCR ITU output pin Inversion Figure 10.53 Example of Inverting ITU Output Levels by Writing to TOCR 280 RENESAS 10.5 Interrupts The ITU has two interrupt sources: input capture/compare match and overflow. 10.5.1 Timing of Setting Status Flags Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits of the TSR are set to 1 by a compare match signal generated when the TCNT matches a general register. The compare match signal is generated in the last state in which the values match (when the TCNT is updated from the matching count to the next count). Therefore, when the TCNT matches the GRA or GRB, the compare match signal is not generated until the next timer clock input. Figure 10.54 shows the timing of setting the IMF bits. CK TCNT input clock TCNT GR N N+1 N Compare match signal IMF IMI Figure 10.54 Timing of Setting Compare Match Flags (IMFA, IMFB) RENESAS 281 Timing of Setting IMFA, IMFB for Input Capture: The IMFA and IMFB are set to 1 by an input capture signal. At this time, the TCNT contents are transferred to the GR. Figure 10.55 shows the timing. CK Input capture signal IMF TCNT GR N N IMI Figure 10.55 Timing of Setting IMFA and IMFB for Input Capture Timing of Setting Overflow Flag (OVF): The OVF is set to 1 when the TCNT overflows from H'FFFF–H'0000 or underflows from H'0000–H'FFFF. Figure 10.56 shows the timing. 282 RENESAS CK TCNT H' FFFF H' 0000 Overflow signal OVF OVI Figure 10.56 Timing of Setting OVF 10.5.2 Clear Timing of Status Flags The status flags are cleared by a write cycle in which 1 is read on the CPU and then 0 is written to it. This timing is shown in figure 10.57. TSR write cycle T1 T2 T3 CK Address TSR address IMF, OVF Figure 10.57 Timing of Status Flag Clearing RENESAS 283 10.5.3 Interrupt Sources and Activating the DMAC The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are allocated their own independently vectored addresses. When the interrupt’s interrupt request flag is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested. The channel priority order can be changed with the interrupt controller. For more information, see section 5, Interrupt Controller. The compare match/input capture A interrupts of channels 0–3 can start the DMAC to transfer data. Table 10.17 lists the interrupt sources. Table 10.17 ITU Interrupt Sources Channel Interrupt Source Description DMAC Activation Priority Order* 0 IMIA0 Compare match or input capture A0 Yes High IMIB0 Compare match or input capture B0 No ↑ OVI0 Overflow 0 No IMIA1 Compare match or input capture A1 Yes IMIB1 Compare match or input capture B1 No OVI1 Overflow 1 No IMIA2 Compare match or input capture A2 Yes IMIB2 Compare match or input capture B2 No OVI2 Overflow 2 No IMIA3 Compare match or input capture A3 Yes IMIB3 Compare match or input capture B3 No OVI3 Overflow 3 No IMIA4 Compare match or input capture A4 No IMIB4 Compare match or input capture B4 No ↓ OVI4 Overflow 4 No Low 1 2 3 4 Note: Indicates the initial status following reset. The ranking of channels can be altered using the interrupt controller. 284 RENESAS 10.6 Notes and Precautions This section describes contention and other matters requiring special attention during ITU operations. 10.6.1 Contention between TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes priority and the write is not performed. The timing is shown in figure 10.58. TCNT write cycle by CPU T1 T2 T3 CK Address TCNT address Internal write signal Counter clear signal TCNT N H' 0000 Figure 10.58 Contention between TCNT Write and Clear RENESAS 285 10.6.2 Contention between TCNT Word Write and Increment If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and the TCNT is not incremented. The timing is shown in figure 10.59. TCNT word write cycle by CPU T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M TCNT write data Figure 10.59 Contention between TCNT Word Write and Increment 286 RENESAS 10.6.3 Contention between TCNT Byte Write and Increment If an increment pulse occurs in the T2 state or T3 state of a TCNT byte write cycle, counter writing takes priority and the byte data on the side that was previously written is not incremented. The TCNT byte data that was not written is also not incremented and retains its previous value. The timing is shown in figure 10.60 (which shows an increment during state T2 of a byte write cycle to TCNTH). TCNTH byte write cycle by CPU T1 T2 T3 CK TCNTH address Address Internal write signal TCNT input clock N TCNTH M TCNT write data TCNTL X X+1 X Figure 10.60 Contention between TCNT Byte Write and Increment RENESAS 287 10.6.4 Contention between GR Write and Compare Match If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes priority and the compare match signal is inhibited. The timing is shown in figure 10.61. GR write cycle T1 T2 T3 CK Address GR address Internal write signal TCNT N N+1 GR N M GR write data Compare match signal Inhibited Figure 10.61 Contention between General Register Write and Compare Match 288 RENESAS 10.6.5 Contention between TCNT Write and Overflow/Underflow If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter incrementing. The OVF is set to 1. The same applies to underflows. This timing is shown in figure 10.62. TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 10.62 Contention between TCNT Write and Overflow RENESAS 289 10.6.6 Contention between General Register Read and Input Capture If an input capture signal is generated during the T3 state of a general register read cycle, the value before input capture is read. The timing is shown in figure 10.63. GR read cycle T1 T2 T3 CK Address GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 10.63 Contention between General Register Read and Input Capture 290 RENESAS 10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The TCNT value before the counter is cleared is transferred to the general register. The timing is shown in figure 10.64. CK Input capture signal Counter clear signal TCNT input clock TCNT GR N H'0000 N Figure 10.64 Contention between Counter Clearing by Input Capture and Counter Increment RENESAS 291 10.6.8 Contention between General Register Write and Input Capture If an input capture signal is generated during the T3 state of a general register write cycle, the input capture transfer takes priority and the write to the GR is not performed. The timing is shown in figure 10.65. GR write cycle T1 T2 T3 CK Address GR address Internal write signal Input capture signal TCNT GR M M Figure 10.65 Contention between General Register Write and Input Capture 10.6.9 Note on Waveform Cycle Setting When a counter is cleared by compare match, the counter is cleared in the last state in which the TCNT value matches the GR value (when the TCNT is updated from the matching count to the next count). The actual counter frequency is therefore given by the following formula: f = φ/(N + 1) (f: counter frequency. φ: operating frequency. N: value set in the GR.) 292 RENESAS 10.6.10 Contention Between BR Write and Input Capture When a buffer register (BR) is being used as an input capture register and an input capture signal is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write. The timing is shown in figure 10.66. BR write cycle T1 T2 T3 CK Address BR address Internal write signal Input capture signal GR N X TCNT value BR M N Figure 10.66 Contention between BR Write and Input Capture RENESAS 293 10.6.11 Note on Writing in the Synchronizing Mode After the synchronizing mode is selected, if the TCNT is written by byte access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are synchronized TCNT2 W X TCNT3 Y Z Upper byte Lower byte Figure 10.67 W X TCNT3 Y Z Upper byte Lower byte 10.6.12 TCNT2 A X TCNT3 A X Upper byte Lower byte TCNT2 Y A TCNT3 Y A Upper byte Lower byte Write A to lower byte of channel 3 Byte Write to Channel 2 or Byte Write to Channel 3 TCNT2 Figure 10.68 Write A to upper byte of channel 2 Word write of AB for channel 2 or 3 TCNT2 A B TCNT3 A B Upper byte Lower byte Word Write to Channel 2 or Word Write to Channel 3 Note on Setting Reset-synchronized PWM Mode/Complementary PWM Mode When the CMD1 and CMD0 bits of TFCR are set, note the following. 1. Writes to CMD1 and CMD0 should be done while TCNT3 and TCNT4 are halted. 2. Changes of setting from the reset-synchronized PWM mode to the complementary PWM mode and vice versa are inhibited. Set the reset-synchronized PWM mode or complementary PWM mode after first setting normal operation (clear CMD1 bit to 0). 294 RENESAS 10.6.13 Clearing the Complementary PWM Mode Figure 10.69 shows the procedure for clearing the complementary PWM mode. First, reset the combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to either 00 or 01. The mode will switch from complementary PWM mode to normal operating mode. Next, wait for at least 1 clock of the counter input clock being used for channels 3 and 4 and then clear the counter start bits STR3 and STR4 of the timer start register (TSTR). The channels 3 and 4 counters TCNT3 and TCNT4 will stop counting. Clearing the complementary PWM mode by any other procedure may result in changes other than those set for the output waveform when complementary PWM mode is set again. Complementary PWM mode Clear complementary PWM mode Halt Count Normal operation 1. Clear the CMD1 bit of the TFCR to 0 to set channels 3 and 4 for normal operation 2. Wait at least 1 clock after setting channels 3 and 4 for normal operation and then clear the STR3 and STR4 bits of the TSTR to 0 to halt the TCNT3 and TCNT4 counters Figure 10.69 Clearing the Complementary PWM Mode 10.6.14 ITU Operating Modes Tables 10.18–10.22 show the ITU operating modes for channels 0–4. 10.6.15 Note on Counter Clearing by Input Capture If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not occur. RENESAS 295 Table 10.18 ITU Operating Modes (Channel 0) Register Setting TSNC Operating Mode Sync TMDR MDF FDIR PWM TFCR TOCR TIOR0 Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA TCR0 IOB Clear Clock Select Select Synchronized preset SYNC0 — =1 — √ — — — — √ √ √ √ PWM √ — — PWM0 — =1 — — — — √ √ √ Output √ compare A function — — PWM0 — =0 — — — IOA2 = √ 0, others free √ √ Output √ compare B function — — √ — — — — √ IOB2 = √ 0, others free √ Input √ capture A function — — PWM0 — =0 — — — IOA2 = √ 1, others free Input √ capture B function — — PWM0 — =0 — — — √ √ √ IOB2 = √ 1, others free √ Counter Clear Function √ Clear at compare match/ input capture A — — √ — — — — √ √ CCLR1 √ =0 CCLR0 =1 √ Clear at compare match/ input capture B — — √ — — — — √ √ CCLR1 √ =1 CCLR0 =0 SYNC0 — =1 — √ — — — — √ √ CCLR1 √ =1 CCLR0 =1 Synchronized clear √: Settable, —: Setting does not affect current mode Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 296 RENESAS Table 10.19 ITU Operating Modes (Channel 1) Register Setting TSNC Operating Mode Sync TMDR MDF FDIR PWM TFCR TOCR TIOR1 Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA TCR1 IOB Clear Clock Select Select Synchronized preset SYNC1 — =1 — √ — — — — √ √ √ √ PWM √ — — PWM1 — =1 — — — — √*1 √ √ Output √ compare A function — — PWM1 — =0 — — — IOA2 = √ 0, others free √ √ Output √ compare B function — — √ — — — — √ IOB2 = √ 0, others free √ Input √ capture A function — — PWM1 — =0 — — — IOA2 = √ 1, others free Input √ capture B function — — PWM1 — =0 — — — √ √ √ IOB2 = √ 1, others free √ Counter Clear Function √ Clear at compare match/ input capture A — — √ — — — — √ √ CCLR1 √ =0 CCLR0 =1 √ Clear at compare match/ input capture B — — √ — — — — √ √ CCLR1 √ =1 CCLR0 =0 SYNC1 — =1 — √ — — — — √ √ CCLR1 √ =1 CCLR0 =1 Synchronized clear √: Settable, —: Setting does not affect current mode Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. RENESAS 297 Table 10.20 ITU Operating Modes (Channel 2) Register Setting TSNC Operating Mode Sync TMDR MDF FDIR PWM TFCR TOCR TIOR2 Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA TCR2 IOB Clear Clock Select Select Synchronized preset SYNC2 — =1 — √ — — — — √ √ √ √ PWM √ — — PWM2 — =1 — — — — √ √ √ Output √ compare A function — — PWM2 — =0 — — — IOA2 = √ 0, others free √ √ Output √ compare B function — — √ — — — — √ IOB2 = √ 0, others free √ Input √ capture A function — — PWM2 — =0 — — — IOA2 = √ 1, others free Input √ capture B function — — PWM2 — =0 — — — √ √ √ IOB2 = √ 1, others free √ Counter Clear Function √ Clear at compare match/ input capture A — — √ — — — — √ √ CCLR1 √ =0 CCLR0 =1 √ Clear at compare match/ input capture B — — √ — — — — √ √ CCLR1 √ =1 CCLR0 =0 Synchronized clear SYNC2 — =1 — √ — — — — √ √ CCLR1 √ =1 CCLR0 =1 Phase counting √ √ — — — — √ √ √ MDF √ =1 √: Settable, —: Setting does not affect current mode 298 RENESAS — Note: In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Table 10.21 ITU Operating Modes (Channel 3) Register Setting TSNC Operating Mode Sync TMDR MDF FDIR PWM TFCR TOCR TIOR3 TCR3 Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA IOB Clear Clock Select Select √*2 Synchronized preset SYNC3 — =1 — √ √ √ — √ √ √ √ PWM mode √ — — PWM3 CMD1 CMD1 √ =1 =0 =0 — — √*1 √ √ Output √ compare A function — — PWM3 CMD1 CMD1 √ =0 =0 =0 — IOA2 = √ 0, others free √ √ Output √ compare B function — — √ CMD1 CMD1 √ =0 =0 — √ IOB2 = √ 0, others free √ Input √ capture A function — — PWM3 CMD1 CMD1 √ =0 =0 =0 — IOA2 = √ 1, others free Input √ capture B function — — PWM3 CMD1 CMD1 √ =0 =0 =0 — √ √ √ IOB2 = √ 1, others free √ Counter Clear Function √ Clear at compare match/ input capture A — — √ CMD1 √*3 = 1, CMD0 =0 inhibited √ — √ √ CCLR1 √ =0 CCLR0 =1 √ Clear at compare match/ input capture B — — √ CMD1 CMD1 √ =0 =0 — √ √ CCLR1 √ =1 CCLR0 =0 SYNC3 — =1 — √ CMD1 √ = 1, CMD0 =0 inhibited — √ √ CCLR1 √ =1 CCLR0 =1 Synchronized clear √ RENESAS 299 Table 10.21 ITU Operating Modes (Channel 3) (cont) Counter Clear Function Register Setting TSNC Operating Mode Sync TMDR TFCR TOCR Reset Comp Sync BufMDF FDIR PWM PWM PWM fer TIOR3 Output Level Select IOA IOB TCR3 Clear Clock Select Select — — — CMD1 CMD1 √ =1 =1 CMD0 CMD0 =0 =0 √ — — CCLR1 √*4 =0 CCLR0 =0 √ Reset synchronized PWM mode — — — CMD1 CMD1 √ =1 =1 CMD0 CMD0 =1 =1 √ — — CCLR1 √ =0 CCLR0 =1 Buffer (BRA) √ — — √ √ √ BFA3 — = 1, others free √ √ √ √ Buffer (BRB) √ — — √ √ √ BFB3 — = 1, others free √ √ √ √ Complementary PWM mode √*2 √: Settable, —: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing by input capture A cannot be used when the reset-synchronized PWM mode is set. 4. Clock selection when the complementary PWM mode is set should be the same for channels 3 and 4. 300 RENESAS Table 10.22 ITU Operating Modes (Channel 4) Register Setting TSNC Operating Mode Sync TMDR MDF FDIR PWM TFCR TOCR TIOR4 TCR4 Reset Output Comp Sync Buf- Level PWM PWM fer Select IOA IOB Clear Clock Select Select √*2 Synchronized preset SYNC4 — =1 — √ √ √ — √ √ √ √ PWM √ — — PWM4 CMD1 CMD1 √ =1 =0 =0 — — √*1 √ √ Output √ compare A function — — PWM4 CMD1 CMD1 √ =0 =0 =0 — IOA2 = √ 0, others free √ √ Output √ compare B function — — √ CMD1 CMD1 √ =0 =0 — √ IOB2 = √ 0, others free √ Input √ capture A function — — PWM4 CMD1 CMD1 √ =0 =0 =0 — IOA2 = √ 1, others free Input √ capture B function — — PWM4 CMD1 CMD1 √ =0 =0 =0 — √ √ √ IOB2 = √ 1, others free √ Counter Clear Function √ Clear at compare match/ input capture A — — √ CMD1 √*3 = 1, CMD0 =0 inhibit ed √ — √ √ CCLR1 √ =0 CCLR0 =1 √ Clear at compare match/ input capture B — — √ CMD1 √*3 = 1, CMD0 =0 inhibit ed √ — √ √ CCLR1 √ =1 CCLR0 =0 RENESAS 301 Table 10.22 ITU Operating Modes (Channel 4) (cont) Counter Clear Function Register Setting TSNC Operating Mode Sync TMDR TFCR TOCR Reset Comp Sync BufMDF FDIR PWM PWM PWM fer Synchronized clear SYNC4 — =1 — √ CMD1 √*3 = 1, CMD1 =0 inhibit ed Complementary PWM √*2 — — — Reset √ synchronized PWM — — Buffer (BRA) √ — Buffer (BRB) √ — TIOR4 Output Level Select IOA IOB TCR4 Clear Clock Select Select — √ √ CCLR1 √ =1 CCLR0 =1 CMD1 CMD1 √ =1 =1 CMD0 CMD0 =0 =0 √ — — CCLR1 √*4 =0 CCLR0 =0 — CMD1 CMD1 √ =1 =1 CMD0 CMD0 =1 =1 √ — — √*5 √*5 — √ √ √ BFA4 — = 1, others free √ √ √ √ — √ √ √ BFB4 — = 1, others free √ √ √ √ √ √: Settable, —: Setting does not affect current mode Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. When set for complementary PWM mode, do not simultaneously set channel 3 and channel 4 to function synchronously. 3. Counter clearing works with the reset-synchronized PWM mode, but TCNT4 runs independently. The output waveform is not affected. 4. Clock selection when the complementary PWM mode is set should be the same for channels 3 and 4. 5. In the reset-synchronized PWM mode, TCNT4 runs independently. The output waveform is not affected. 302 RENESAS Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The SuperH microcomputer has a built-in programmable timing pattern controller (TPC). The TPC can provide pulse outputs by using the 16-bit integrated-timer pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups 3–0. These can operate simultaneously, or independently. 11.1.1 Features Features of the programmable timing pattern controller are listed below. • • • • • • 16-bit output data: Maximum 16-bit data can be output. TPC output can be enabled on a bitby-bit basis. Four output groups: Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. Selectable output trigger signals: Output trigger signals can be selected by group from the 4-channel compare-match signals of the 16-bit integrated-timer pulse unit (ITU). Non-overlap mode: A non-overlap interval can be set to come between multiple pulse outputs. Can connect to DMA controller: The compare-match signals selected as output trigger signals can activate the DMA controller for sequential output of data without CPU intervention. RENESAS 303 11.1.2 Block Diagram Figure 11.1 is the block diagram of the TPC. ITU compare match signal Control logic TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 PBCR1 PBCR2 NDERA NDERB TPMR TPCR Pulse output pin group 3 NDRB Pulse output pin group 2 PBDR Pulse output pin group 1 NDRA Pulse output pin group 0 TPC TPMR: TPC output mode register PBCR1: Port B control register 1 TPCR: TPC output control register PBCR2: Port B control register 2 NDERB: Next data enable register B NDRB: Next data register B NDERA: Next data enable register A NDRA: Next data register A PBDR: Port B data register Figure 11.1 TPC Block Diagram 304 RENESAS Internal data bus 11.1.3 Input/Output Pins Table 11.1 summarizes the TPC input/output pins. Table 11.1 TPC Pins Name Symbol Input/Output Function TPC output 0 TP0 Output Group 0 pulse output TPC output 1 TP1 Output TPC output 2 TP2 Output TPC output 3 TP3 Output TPC output 4 TP4 Output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 Output Group 1 pulse output Group 2 pulse output Group 3 pulse output RENESAS 305 11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Name Abbreviation R/W Initial Value Address* 1 Access Size` Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16 Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16 Port B data register PBDR R/(W)*2 H'0000 H'5FFFFC2 8, 16 TPC output mode register TPMR R/W H'F0 H'5FFFFF0 8, 16 TPC output control register TPCR R/W H'FF H'5FFFFF1 8, 16 Next data enable register B NDERB R/W H'00 H'5FFFFF2 8, 16 Next data enable register A NDERA R/W H'00 H'5FFFFF3 8, 16 Next data register A NDRA R/W H'00 H'5FFFFF5/ H'5FFFFF7*3 8, 16 Next data register B NDRB R/W H'00 H'5FFFFF4/ H'5FFFFF6*3 8, 16 Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Bits used for TPC output cannot be written to. 3. These addresses change depending on TPCR settings. When TPC output groups 0 and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is H'5FFFFF4. 11.2 Register Descriptions 11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2) The port B control register 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the functions of port B pins. Port B consists of the dual use pins TP15–TP0. Bits corresponding to the pins to be used for TPC output must be set to 1. For details, see the port B description in the section 15, Pin Function Controller. 306 RENESAS PCBR1: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PB9MD1 PB9MD0 PB8MD1 PB8MD0 PCBR2: Bit: Bit name: PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit name: PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value: R/W: 11.2.2 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Port B Data Register (PBDR) The port B data register is a 16-bit read/write register that, when used for TPC output stores, output data for groups 0–3. For details, see the port B description in section 16, I/O Ports. Bit: 15 14 13 12 11 10 9 8 Bit name: PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/W: 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bits set to TPC output by NDERA or NDERB are read-only. RENESAS 307 Bit: Bit name: Initial value: R/W: 7 PB7DR 6 5 PB6DR PB5DR 4 3 PB4DR PB3DR 2 PB2DR 1 0 PB1DR PB0DR 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bits set to TPC output by NDERA or NDERB are read-only. 11.2.3 Next Data Register A (NDRA) NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1 and 0 (TP7–TP0). When used for TPC output, the contents of the NDRA are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register TPCR occurs. The address of the NDRA differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 1 and 0. When reset, NDRA is initialized to H'00. It is not initialized by standby mode. Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by the same compare match, the address of the NDRA is H'FFFFF5. The 4 upper bits becomes group 1 and the 4 lower bits become group 0. Address H'5FFFFF7 in such cases consists entirely of reserved bits. These bits cannot be modified and always read as 1. Address H'5FFFFF5: • Bits 7–4 (next data 7–4 (NDR7–NDR4)): NDR7-NDR4 store the next output data for TPC output group 1. • Bits 3–0 (next data 3–0 (NDR3–NDR0)): NDR3-NDR0 store the next output data for TPC output group 0. Bit: Bit name: Initial value: R/W: 308 RENESAS 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address H'5FFFFF7: • Bits 7–0 (reserved): These bits always read as 1. The write value should always be 1. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: — — — — — — — — Different Triggers for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by different compare matches, the address of the upper 4 bits of NDRA (group 1) is H'5FFFFF5 and the address of the lower 4 bits of NDRA (group 0) is H'5FFFFF7. Bits 3–0 of address H'5FFFFF5 and bits 7–4 of address H'5FFFFF7 are reserved bits. The write value should always be 1. These bits always read as 1. Address H'5FFFFF5: • Bits 7–4 (next data 7–4 (NDR7–NDR4)): NDR7–NDR4 store the next output data for TPC output group 1. • Bits 3–0 (reserved): These bits always read as 1. The write value should always be 1. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W — — — — Address H'5FFFFF7: • Bits 7–4 (reserved): These bits always read as 1. The write value should always be 1. • Bits 3–0 (next data 3–0 (NDR3–NDR0)): NDR3-NDR0 store the next output data for TPC output group 0. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — NDR3 NDR2 NDR1 NDR0 Initial value: 1 1 1 1 0 0 0 0 R/W: — — — — R/W R/W R/W R/W RENESAS 309 11.2.4 Next Data Register B (NDRB) NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3 and 2 (TP15–TP8). When used for TPC output, the contents of the NDRB are transferred to the corresponding PBDR bits when the ITU compare match specified in the TPC output control register TPCR occurs. The address of the NDRB differs depending on whether TPCR settings select the same trigger or different triggers for TPC output groups 3 and 2. When reset, NDRB is initialized to H'00. It is not initialized by standby mode. Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by the same compare match, the address of the NDRB is H'FFFFF4. The 4 upper bits becomes group 3 and the 4 lower bits become group 2. Address H'5FFFFF6 becomes completely reserved bits. These bits always read as 1, and the write value should always be 1. Address H'5FFFFF4: • Bits 7–4 (next data 15–12 (NDR15–NDR12)): NDR15–NDR12 store next output data for TPC output group 3. • Bits 3–0 (next data 11–8 (NDR11–NDR8)): NDR11–NDR8 store next output data for TPC output group 2. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Address H'5FFFFF6: • Bits 7–0 (reserved): These bits always read as 1. The write value should always be 1. Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: — — — — — — — — 310 RENESAS Different Triggers for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by different compare matches, the address of the upper 4 bits of NDRB (group 3) is H'5FFFFF4 and the address of the lower 4 bits of NDRB (group 2) is H'5FFFFF6. Bits 3-0 of address H'5FFFFF4 and bits 7–4 of address H'5FFFFF6 are reserved bits. These bits always read as 1. The write value should always be 1. Address H'5FFFFF4: • Bits 7–4 (next data 15–12 (NDR15–NDR12)): NDR15–NDR12 store next output data for TPC output group 3. • Bits 3–0 (reserved): These bits always read as 1. The write value should always be 1. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W — — — — Address H'5FFFFF6: • Bits 7–4 (reserved): These bits always read as 1. The write value should always be 1. • Bits 3–0 (next data 11–8 (NDR11–NDR8)): NDR11–NDR8 store next output data for TPC output group 2. 11.2.5 Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — NDR11 NDR10 NDR9 NDR8 Initial value: 1 1 1 1 0 0 0 0 R/W: — — — — R/W R/W R/W R/W Next Data Enable Register A (NDERA) NDERA is an eight-bit read/write register that enables TPC output groups 1 and 0 (TP7–TP0) on a bit-by-bit basis. When the bits enabled for TPC output by NDERA generate the ITU compare match selected in the TPC output control register, the value of the next data register A (NDRA) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. When reset, NDERA is initialized to H'00. It is not initialized by standby mode. RENESAS 311 Bit: Bit name: Initial value: R/W: • 7 6 NDER7 5 NDER6 NDER5 4 3 NDER4 NDER3 2 NDER2 1 0 NDER1 NDER0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7–0 (next data enable 7–0 (NDER7–NDER0)): NDER7–NDER0 select enable/disable for TPC output groups 1 and 0 (TP7–TP0) in bit units. Bit 7–0: NDER7–NDER0 Description 0 Disables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7– PB0 is disabled) (initial value) 1 Enables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7– PB0 is enabled) 11.2.6 Next Data Enable Register B (NDERB) NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15–TP8) on a bit-by-bit basis. When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the TPC output control register, the value of the next data register B (NDRB) is automatically transferred to the corresponding PBDR bits and the output value is updated. For disabled bits, there is no transfer and the output value does not change. When reset, NDERB is initialized to H'00. It is not initialized by standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value: R/W: • 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7–0 (next data enable 15–8 (NDER15–NDER8)): NDER15–NDER8 select enable/disable for TPC output groups 3 and 2 (TP15–TP8) in bit units. Bit 7–0: NDER15–NDER8 Description 0 Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8 is disabled) (initial value) 1 Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8 is enabled) 312 RENESAS 11.2.7 TPC Output Control Register (TPCR) TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. When reset, TPCR is initialized to H'FF. It is not initialized by standby mode. Bit: 7 6 5 4 3 2 1 0 Bit name: G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value: R/W: • 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6 (group 3 compare-match select 1 and 0 (G3CMS1 and G3CMS0)): G3CMS1 and G3CMS0 select the compare match that triggers TPC output group 3 (TP15–TP12). Bit 7: G3CMS1 Bit 6: G3CMS0 Description 0 0 TPC output group 3 (TP15–TP12) output is triggered by compare-match in ITU channel 0 1 TPC output group 3 (TP15–TP12) output is triggered by compare-match in ITU channel 1 0 TPC output group 3 (TP15–TP12) output is triggered by compare-match in ITU channel 2 1 TPC output group 3 (TP15–TP12) output is triggered by compare-match in ITU channel 3 (initial value) 1 • Bits 5 and 4 (group 2 compare-match select 1 and 0 (G2CMS1 and G2CMS0)): G2CMS1 and G2CMS0 select the ITU channel that triggers TPC output group 2 (TP11–TP8). Bit 5: G2CMS1 Bit 4: G2CMS0 Description 0 0 TPC output group 2 (TP11–TP18) output is triggered by compare-match in ITU channel 0 1 TPC output group 2 (TP11–TP18) output is triggered by compare-match in ITU channel 1 0 TPC output group 2 (TP11–TP18) output is triggered by compare-match in ITU channel 2 1 TPC output group 2 (TP11–TP18) output is triggered by compare-match in ITU channel 3 (initial value) 1 RENESAS 313 Bits 3 and 2 (group 1 compare-match select 1 and 0 (G1CMS1 and G1CMS0)): G1CMS1 and G1CMS0 select the ITU channel that triggers TPC output group 1 (TP7–TP4). Bit 3: G1CMS1 Bit 2: G1CMS0 Description 0 0 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 0 1 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 1 0 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 2 1 TPC output group 1 (TP7–TP4) output is triggered by compare-match in ITU channel 3 (initial value) 1 • Bits 1 and 0 (group 0 compare-match select 1 and 0 (G0CMS1 and G0CMS0)): G0CMS1 and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3–TP0). Bit 1: G0CMS1 Bit 0: G0CMS0 Description 0 0 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 0 1 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 1 0 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 2 1 TPC output group 0 (TP3–TP0) output is triggered by compare-match in ITU channel 3 (initial value) 1 11.2.8 TPC Output Mode Register (TPMR) TPMR is an eight-bit read/write register that selects between the TPC's ordinary output and nonoverlap output modes in group units. During non-overlap operation, the output waveform cycle is set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in general register A (GRA). The output value then changes on compare matches A and B. For details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 on a reset. It is not initialized in standby mode. Bit: 7 6 5 4 Bit name: — — — — Initial value: 1 1 1 1 0 0 0 0 R/W: — — — — R/W R/W R/W R/W 314 RENESAS 3 2 1 0 G3NOV G2NOV G1NOV G0NOV Bits 7–4 (reserved): These bits always read as 1. The write value should always be 1. • Bit 3 (group 3 non-overlap mode (G3NOV)): G3NOV selects the ordinary or non-overlap mode for TPC output group 3 (TP15–TP12). Bit 3: G3NOV Description 0 TPC output group 3 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) 1 TPC output group 3 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR) • Bit 2 (group 2 non-overlap mode (G2NOV)): G2NOV selects the ordinary or non-overlap mode for TPC output group 2 (TP11–TP8). Bit 2: G2NOV Description 0 TPC output group 2 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) 1 TPC output group 2 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR) • Bit 1 (group 1 non-overlap mode (G1NOV)): G1NOV selects the ordinary or non-overlap mode for TPC output group 1 (TP7–TP4). Bit 1: G1NOV Description 0 TPC output group 1 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) 1 TPC output group 1 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR) • Bit 0 (group 0 non-overlap mode (G0NOV)): G0NOV selects the ordinary or non-overlap mode for TPC output group 0 (TP3–TP0). RENESAS 315 Bit 0: G0NOV Description 0 TPC output group 0 operates normally (output value updated according to compare-match A of the ITU channel selected by TPCR) (initial value) 1 TPC output group 0 operates in non-overlap mode (1 output and 0 output can be performed independently according to compare-match A and B of the ITU channel selected by TPCR) 11.3 Operation 11.3.1 Overview When corresponding bits in the PBCR1, PBCR2, NDERA and NDERB registers are set to 1, TPC output is enabled and the PBDR data register values are output. After that, when the comparematch event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are transferred to the PBDR and output values are updated. Figure 11.2 illustrates the TPC output operation. CR NDER Q Q Output trigger signal C Port function select Q DR D Q NDR D Internal data bus TPC output pin Figure 11.2 TPC Output Operation If new data is written in next data registers A and B before the next compare-match occurs, a maximum 16 bits of data can be output at each successive compare-match. See section 11.3.4, TPC Output Non-Overlap Operation, for details on non-overlap operation. 316 RENESAS 11.3.2 Output Timing If TPC output is enabled, next data register (NDRA/NDRB) contents are transferred to the data register (PBDR) and output when the selected compare-match occurs. Figure 11.3 shows the timing of these operations. The example is of ordinary output upon compare match A with groups 2 and 3. CK N TCNT GRA N+1 N Compare match A signal n NDRB PBDR m n TP15–TP8 m n Figure 11.3 Transfer and Output Timing for NDR Data 11.3.3 Examples of Use of Ordinary TPC Output Settings for Ordinary TPC Output (figure 11.4): 1. Select GRA as the output compare register (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle. 3. Select the counter clock with the TPSC2–TPSC0 bits of the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by TPC. 6. Set the I/O port control register to be used by TPC as the TP pin function (11). RENESAS 317 7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Set the next TPC output value in the NDR. 10. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter counting. 11. Set the next output value in the NDR whenever an IMIA interrupt is generated. Original TPC output operation Select GR function (1) Set GRA (2) Set count operation (3) Select interrupt request (4) Set initial output value (5) Set port output (6) Set TPC output enable (7) ITU setting Port and TPC setting Select TPC output trigger ITU setting (8) Set next TPC output value (9) Start count (10) Compare match? No Yes Set next TPC output value (11) Figure 11.4 Example of Setting Procedure for TPC Ordinary Output 318 RENESAS Five-Phase Pulse Output (figure 11.5): 1. Set the GRA of the ITU that serves as output trigger as the output compare register. Set the cycle time in the GRA of the ITU and select to clear the counter upon compare match A. Set the IMIEA bit of TIER to 1 to enable the compare match A interrupt. 2. Write H'FFC0 in the PBCR1, write H'F8 in the NDERB, and set G3CMS0, G3CMS1, G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the output trigger. Write output data H'80 in the NDRB. 3. When the selected ITU channel starts operating and a compare-match occurs, the values in the NDRB are transferred to the PBDR and output. The compare-match/input capture A (IMIA) interrupt service routine writes the next output data (H'C0) in the NDRB. 4. Five-phase pulse output can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive compare-match interrupts. If the DMA controller is set for activation by compare-match, pulse output can be obtained without loading the CPU. TCNT value TCNT GRA Compare matches H'0000 NDRB PBDR Time 80 C0 40 60 20 30 10 18 08 88 80 C0 8000 C000 4000 6000 2000 3000 1000 1800 0800 8800 8000 C000 TP15 TP14 TP13 TP12 TP11 Figure 11.5 TPC Output Example (5-Phase Pulse Output) RENESAS 319 11.3.4 TPC Output Non-Overlap Operation Setting Procedures for TPC Output Non-Overlap Operation (figure 11.6): 1. Select GRA and GRB as output compare registers (output disable) with the timer I/O control register (TIOR). 2. Set the TPC output trigger cycle to GRB and the non-overlap cycle to GRA. 3. Select the counter clock with the TPSC2–TPSC0 bits of the timer control register (TCR). Select the counter clear sources with the CCLR1 and CCLR0 bits. 4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR can also be set using the DMAC. 5. Set the initial output value in the I/O port data register to be used by TPC. 6. Set the I/O port control register to be used by TPC as the TP pin function (11). 7. Set to 1 the bit that performs TPC output to the next data enable register (NDER). 8. Select the ITU compare match that will be the TPC output trigger using the TPC output control register (TPCR). 9. Select the group that performs the non-overlap operation in the TPC output mode register (TPMR). 10. Set the next TPC output value in the NDR. 11. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter counting. 12. Set the next output value in the NDR whenever an IMIA interrupt is generated. 320 RENESAS TPC output nonoverlap operation Select GR function (1) Set GRA (2) Set count operation (3) Select interrupt request (4) Set initial output value (5) Set TPC output (6) Set TPC transfer enable (7) Select TPC output trigger (8) Select non-overlap group (9) Set next TPC output value (10) Start count (11) ITU setting Port and TPC setting ITU setting Compare match A? No Yes Set next TPC output value (12) Figure 11.6 Example of Setting Procedures for TPC Output Non-Overlap Operation RENESAS 321 TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output) (figure 11.7): 1. Set GRA and GRB of the ITU that serves as output trigger in the output compare registers. Set the cycle in the GRB and the non-overlap cycle time in the GRA and select to clear the counter upon compare match B. Set the IMIEA bit of TIER to 1 to enable the IMIA interrupt. 2. Write H'FFFF in the PBCR1, write H'FF in the NDERB, and set G3CMS1, G3CMS0, G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the output trigger. Set the G3NOV and G2NOV bits in the TPMR to 1 to set the non-overlap operation. Write output data H'95 in the NDRB. 3. When the selected ITU channel starts operating and a GRB compare-match occurs, 1 output changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt service routine writes the next output data (H'65) in the NDRB. 4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95… at successive IMIA interrupts. If the DMA controller is set for activation by compare-match, pulse output can be obtained without loading the CPU. 322 RENESAS TCNT value GRB TCNT GRA Time H'0000 NDRB 95 PBDR 00 65 95 05 59 65 41 56 59 50 95 56 14 65 95 05 65 Non-overlap cycle TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 Figure 11.7 Non-Overlap Output Example (Four-Phase Complementary Output) RENESAS 323 11.3.5 TPC Output by Input Capture TPC can also be output by using input capture rather than ITU compare matches. The general register A (GRA) of the ITU selected by the TPCR functions as an input capture register and TPC output occurs upon an input capture signal. Figure 11.8 shows the timing. CK TIOC pin Input capture signal NDR DR N M N Figure 11.8 TPC Output by Input Capture 324 RENESAS 11.4 Usage Notes 11.4.1 Non-Overlap Operation During non-overlap operation, transfers from the NDR to data registers (DR) occurs as follows. 1. NDR contents are always transferred to the DR on compare match A. 2. The contents of the bit transferred by the NDR are only transferred on compare match B when they are 0. No transfer occurs for a 1. Figure 11.9 illustrates the TPC output operation during non-overlap. CR NDER Q Q Compare match A Compare match B C Port function select Q DR D Q NDR D TPC output pin Figure 11.9 TPC Output Non-Overlap Operation RENESAS 325 When a compare match B occurs before the compare match A, the 0 data transfer can be performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases, be sure not to change the NDR contents until the compare match A after the compare match B occurs (non-overlap period). This can be ensured by writing the next data to the NDR using the IMIA interrupt service routine. The DMAC can also be started up using an IMIA interrupt. However, these write operations should be performed prior to the next compare match B. The timing is shown in figure 11.10. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output NDR write period NDR write disable period 0 output 0/1 output NDR write period NDR write disable period Figure 11.10 Non-Overlap Operation and NDR Write Timing 326 RENESAS Section 12 Watchdog Timer (WDT) 12.1 Overview The SuperH microcomputer has a one-channel watchdog timer (WDT) for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally . The WDT can simultaneously generate an internal reset signal for the entire chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from the standby mode. 12.1.1 • • • • • Features Watchdog timer mode and interval timer mode can be selected. Outputs WDTOVF in the watchdog timer mode. When the counter overflows in the watchdog timer mode, overflow signal WDTOVF is output externally. You can select whether or not to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. Generates interrupts in the interval timer mode. When the counter overflows, it generates an interval timer interrupt. Used to clear the standby mode. Selection of eight counter clock sources RENESAS 327 12.1.2 Block Diagram Figure 12.1 is the block diagram of the WDT. Overflow Interrupt control Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources TCSR Bus interface Module bus Internal data bus ITI (interrupt signal) WDT TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: The internal reset signal can be generated by setting the register. The type of reset can be selected (power-on or manual resets). Figure 12.1 WDT Block Diagram 12.1.3 Pin Configuration Table 12.1 shows the pin configuration. RENESAS 328 Table 12.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in the watchdog mode 12.1.4 Register Configuration Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 12.2 WDT Registers Address Name Abbreviation R/W Initial Value Write*1 Timer control/status register TCSR R/(W)*3 H'18 H'5FFFFB8 Timer counter TCNT R/W H'00 Reset control/status register RSTCSR R/(W)*3 H'3F Read* 2 H'5FFFFB8 H'5FFFFB9 H'5FFFFBA H'5FFFFBB Notes: 1. Write by word transfer. It cannot be written in byte or long word. 2. Read by byte transfer. It cannot be read in word or long word. 3. Only 0 can be written in bit 7 to clear the flag. 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) The TCNT is an eight-bit readable and writable upcounter. The TCNT differs from other registers in that it is more difficult to write. See section 12.2.4, Register Access, for details. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2–0 (CKS2–CKS0) in the TCSR. When the value of the TCNT overflows (changes from H'FF–H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of the TCSR. The TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in the standby mode. RENESAS 329 Bit: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: 12.2.2 Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an eight-bit readable and writable register. The TCSR differs from other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a reset or in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their values in the standby mode. Bit: Bit name: Initial value: R/W: • 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W — — R/W R/W R/W Bit 7 (overflow flag (OVF)): OVF indicates that the TCNT has overflowed from H'FF–H'00. It is not set in the watchdog timer mode. Bit 7: OVF Description 0 No overflow of TCNT in interval timer mode (initial value) Cleared by reading OVF, then writing 0 in OVF 1 • TCNT overflow in the interval timer mode Bit 6 (timer mode select (WT/IT)): WT/IT selects whether to use the WDT as a watchdog timer or interval timer. When the TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT Description 0 Interval timer mode: interval timer interrupt to the CPU when TCNT overflows (initial value) 1 Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in the watchdog timer mode. • Bit 5 (timer enable (TME)): TME enables or disables the timer. RENESAS 330 Bit 5: TME Description 0 Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) 1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. • Bits 4 and 3 (reserved): These bits always read as 1. The write value should always be 1. • Bits 2–0 (clock Select 2–0 (CKS2–CKS0)): CKS2–CKS0 select one of eight internal clock sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source Overflow Interval* (φ = 20 MHz) 0 0 0 φ/2 (initial value) 25.6 µs 0 0 1 φ/64 819.2 µs 0 1 0 φ/128 1.6 ms 0 1 1 φ/256 3.3 ms 1 0 0 φ/512 6.6 ms 1 0 1 φ/1024 13.1 ms 1 1 0 φ/4096 52.4 ms 1 1 1 φ/8192 104.9 ms Note: The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. 12.2.3 Reset Control/Status Register (RSTCSR) The RSTCSR is an eight-bit readable and writable register that controls output of the reset signal generated by timer counter (TCNT) overflow and selects the internal reset signal type. The RSTCSR differs from other registers in that it is more difficult to write. See section 12.2.4 Register Access, for details. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 WOVF RSTE RSTS — — — — — 0 0 0 1 1 1 1 1 R/(W)* R/W R/W — — — — — Note: Only 0 can be written in bit 7 to clear the flag. RENESAS 331 • Bit 7 (watchdog timer overflow (WOVF)): WOVF indicates that the TCNT has overflowed (H'FF → H'00) in the watchdog timer mode. It is not set in the interval timer mode. Bit 7: WOVF Description 0 No TCNT overflow in watchdog timer mode (initial value) Cleared when software reads WOVF, then writes 0 in WOVF 1 Set by TCNT overflow in watchdog timer mode • Bit 6 (reset enable (RSTE)): RSTE selects whether to reset the chip internally if the TCNT overflows in the watchdog timer mode. Bit 6: RSTE Description 0 Not reset when TCNT overflows (initial value). LSI not reset internally, but TCNT and TCSR reset within WDT. 1 Reset when TCNT overflows • Bit 5 (reset select (RSTS)): RSTS selects the type of internal reset generated if the TCNT overflows in the watchdog timer mode. Bit 5: RSTS Description 0 Power-on reset initial value) 1 Manual reset • Bits 4–0 (reserved): These bits always read as 1. The write value should always be 1. RENESAS 332 12.2.4 Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. The TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the TCSR) (figure 12.2). This transfers the write data from the lower byte to the TCNT or TCSR. Writing to the TCNT 15 Address: H'5FFFFB8 8 H'5A 7 0 Write data Writing to the TCSR 15 Address: H'5FFFFB8 H'A5 8 7 0 Write data Figure 12.2 Writing to the TCNT and TCSR RENESAS 333 Writing to the RSTCSR: The RSTCSR must be written by a word access to address H'5FFFFFBA. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 12.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'5FFFFBA 8 H'A5 7 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'5FFFFBA 8 H'5A 7 0 Write data Figure 12.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'5FFFFB8 for the TCSR, H'5FFFFB9 for the TCNT, and H'5FFFFBB for the RSTCSR. 12.3 Operation 12.3.1 Operation in the Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If the TCNT fails to be rewritten and overflows due to a system crash or the like, a WDTOVF signal is output (figure 12.4). The WDTOVF signal can be used to reset external system devices. The WDTOVF signal is output for 128φ clock cycles. If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit. The internal reset signal is output for 512φ clock cycles. When a watchdog reset is generated simultaneously with input at the RES pin, the software distinguishes the RES reset from the watchdog reset by checking the WOVF bit in the RSTCSR. The RES reset takes priority. The WOVF bit is cleared to 0. RENESAS 334 TCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128φ clock Internal reset signal* 512φ clock WT/IT: Timer mode select bit TME: Timer enable bit Note: The internal reset signal is only generated when the RSTE bit is 1. Figure 12.4 Operation in the Watchdog Timer Mode RENESAS 335 12.3.2 Operation in the Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 12.5). TCNT value Overflow H'FF Overflow Overflow Overflow H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI Figure 12.5 Operation in the Interval Timer Mode 12.3.3 Operation in the Standby Mode The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When using the standby mode, set the WDT as described below. Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby mode while the TME bit is set to 1. Set bits CKS2–CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 20.3, AC Characteristics, for the oscillation settling time. Recovery from the Standby Mode: When an NMI request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits CKS2–CKS0 before the standby mode was entered. When the TCNT overflows (changes from H'FF–H'00), the system clock (φ) is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. For details on the standby mode, see section 19, Power Down States. RENESAS 336 12.3.4 Timing of Setting the Overflow Flag (OVF) In the interval timer mode, when the TCNT overflows the OVF flag is set to 1 and an interval timer interrupt is requested (figure 12.6). CK H'FF TCNT H'00 Overflow signal (internal signal) OVF Figure 12.6 Timing of Setting the OVF 12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When the TCNT overflows the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 12.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 12.7 Timing of Setting the WOVF Bit and Internal Reset RENESAS 337 12.4 Usage Notes 12.4.1 TCNT Write and Count Up Contention If a timer counter clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 12.8). TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.4.2 Changing CKS2-CKS0 Bit Values If the values of bits CKS2–CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2–CKS0. 12.4.3 Changing Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. RENESAS 338 12.4.4 System Reset With WDTOVF If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 12.9. SuperH microprocessor Reset input Reset signal to entire system RES WDTOVF Figure 12.9 Example of a System Reset Circuit with a WDTOVF Signal 12.4.5 Internal Reset With the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a TCNT overflow occurs, but the TCNT and TCSR in WDT will reset. RENESAS 339 Section 13 Serial Communication Interface (SCI) 13.1 Overview The SuperH microcomputer has a serial communication interface (SCI) with two independent channels. Both channels are functionally identical. The SCI supports both asynchronous and clocked synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 13.1.1 • • • • • • Features Asynchronous mode  Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats.  Data length: seven or eight bits  Stop bit length: one or two bits  Parity: even, odd, or none  Multiprocessor bit: one or none  Receive error detection: parity, overrun, and framing errors  Break detection: by reading the RxD level directly when a framing error occurs Clocked synchronous mode  Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a clocked synchronous communication function. There is one serial data communication format.  Data length: eight bits  Receive error detection: overrun errors Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. On-chip baud rate generator with selectable bit rates Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. RENESAS 341 13.1.2 Block Diagram Bus interface Figure 13.1 shows a block diagram of the SCI. Module data bus RDR TDR BRR SSR SCR RXD RSR TSR SMR Transmit/ receive control TXD Parity generation Parity check SCK Baud rate generator External clock SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 13.1 SCI Block Diagram RENESAS 342 φ φ/4 φ/16 φ/64 Clock SCI RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register Internal data bus TEI TXI RXI ERI 13.1.3 Input/Output Pins Table 13.1 summarizes the SCI pins by channel. Table 13.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function 0 Serial clock pin SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input 1 13.1.4 Transmit data pin TxD0 Output SCI0 transmit data output Serial clock pin SCK1 Input/output SCI1 clock input/output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output Register Configuration Table 13.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or clocked synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 13.2 Registers Channel Address* 1 Name Abbreviation R/W Initial Value Access size 0 H'05FFFEC0 Serial mode register SMR0 R/W H'00 8, 16 H'05FFFEC1 Bit rate register BRR0 R/W H'FF 8, 16 H'05FFFEC2 Serial control register SCR0 R/W H'00 8, 16 H'05FFFEC3 Transmit data register TDR0 R/W H'FF 8, 16 H'05FFFEC4 Serial status register SSR0 R/(W)*2 H'84 8, 16 H'05FFFEC5 Receive data register RDR0 R H'00 8, 16 H'05FFFEC8 Serial mode register SMR1 R/W H'00 8, 16 H'05FFFEC9 Bit rate register 1 BRR1 R/W H'FF 8, 16 H'05FFFECA Serial control register SCR1 R/W H'00 8, 16 H'05FFFECB Transmit data register TDR1 R/W H'FF 8, 16 H'05FFFECC Serial status register SSR1 R/(W)*2 H'84 8, 16 H'05FFFECD Receive data register RDR1 R H'00 8, 16 Notes: 1. Only the values of bits A27–A24 and A8-A0 are valid; bits A23–A9 are ignored. For details on the register addresses, see section 8.3.5, Description of Areas. 2. Write 0 to clear flags. RENESAS 343 13.2 Register Descriptions 13.2.1 Receive Shift Register The receive shift register (RSR) receives serial data. Data input at the RxD pin are loaded into the RSR in the order received, LSB (bit 0) first. In this way the SCI converts received data to parallel form. When one byte has been received, it is automatically transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly. Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Bit name: R/W: 13.2.2 Receive Data Register The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into the RDR for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby mode. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit name: 13.2.3 Transmit Shift Register The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1, however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the TSR directly. Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Bit name: R/W: RENESAS 344 13.2.4 Transmit Data Register The transmit data register (TDR) is an eight-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the TDR during serial transmission from the TSR. The CPU can always read and write the TDR. The TDR is initialized to H'FF by a reset or in standby mode. Bit: 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: 13.2.5 Serial Mode Register The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SMR. The SMR is initialized to H'00 by a reset or in standby mode. Bit: Bit name: Initial value: R/W: • 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 (communication mode (C/A)): C/A selects whether the SCI operates in the asynchronous or clocked synchronous mode. Bit 7: C/A Description 0 Synchronous mode (initial value) 1 Clocked synchronous mode RENESAS 345 • Bit 6 (character length (CHR)): CHR selects seven-bit or eight-bit data in the asynchronous mode. In the clocked synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 Eight-bit data (initial value) 1 Seven-bit data. When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. • Bit 5 (parity enable (PE)): PE selects whether to add a parity bit to transmit data and check the parity of receive data, in the asynchronous mode. In the clocked synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. Bit 5: PE Description 0 Parity bit not added or checked (initial value) 1 Parity bit added and checked. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. • Bit 4 (parity mode (O/E): O/E selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored in the clocked synchronous mode, or in the asynchronous mode when parity addition and check is disabled. Bit 4: O/E Description 0 Even parity. If even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined (initial value). 1 Odd parity. If odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. RENESAS 346 • Bit 3 (stop bit length (STOP)): STOP selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clocked synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP Description 0 One stop bit. In transmitting, a single bit of 1 is added at the end of each transmitted character (initial value). 1 Two stop bits. In transmitting, two bits of 1 are added at the end of each transmitted character. • Bit 2 (multiprocessor mode (MP)): MP selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in the asynchronous mode; it is ignored in the clocked synchronous mode. For the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication. Bit 2: MP Description 0 Multiprocessor function disabled (initial value) 1 Multiprocessor format selected • Bits 1 and 0 (clock select 1 and 0 (CKS1 and CKS0)): CKS1 and CKS0 select the internal clock source of the on-chip baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 13.2.8, Bit Rate Register. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 System clock (φ) (initial value) 1 φ/4 0 φ/16 1 φ/64 1 RENESAS 347 13.2.6 Serial Control Register The serial control register (SCR) enables the SCI transmitter/receiver, selects serial clock output in the asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a reset or in standby mode. Bit: Bit name: Initial value: R/W: • 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 (transmit interrupt enable (TIE)): TIE enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 due to transfer of serial transmit data from the TDR to the TSR. Bit 7: TIE Description 0 Transmit-data-empty interrupt request (TXI) is disable. The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0 (initial value). 1 Transmit-data-empty interrupt request (TXI) is enabled • Bit 6 (receive interrupt enable (RIE)): RIE enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 due to transfer of serial receive data from the RSR to the RDR. Also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled. RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0 (initial value). 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled RENESAS 348 Bit 5 (transmit enable (TE)): TE enables or disables the SCI transmitter. Bit 5: TE Description 0 Transmitter disabled. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1 (initial value). 1 Transmitter enabled. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1. • Bit 4 (receive enable (RE)): RE enables or disables the SCI receiver. Bit 4: RE Description 0 Receiver disabled (initial value). Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled. Serial reception starts when a start bit is detected in the asynchronous mode, or serial clock input is detected in the clocked synchronous mode. Select the receive format in the SMR before setting RE to 1. • Bit 3 (multiprocessor interrupt enable (MPIE)): MPIE enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in the clocked synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts are disabled (normal receive operation) (initial value) MPE is cleared to 0 when: 1. MPIE is cleared to 0, or 2. Multiprocessor bit (MPB) is set to 1 in receive data. 1 Multiprocessor interrupts are enabled: Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until the multiprocessor bit is set to 1. The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the FER and ORER to be set. RENESAS 349 • Bit 2 (transmit-end interrupt enable (TEIE)): TEIE enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) requests are disabled* (initial value) The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. 1 • Transmit-end interrupt (TEI) requests are enabled. Bits 1 and 0 (clock enable 1 and 0 (CKE1 and CKE0)): CKE1 and CKE0 select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in the clocked synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source, see table 13.9 in section 13.3, Operation. Bit 1: CKE1 Bit 0: CKE0 Description*1 0 0 Synchronous mode Internal clock, SCK pin used for input pin (input signal is ignored or output pin output level is undefined) Clocked synchronous mode Internal clock, SCK pin used for serial clock output*2 0 1 Synchronous mode Internal clock, SCK pin used for clock output*3 Clocked synchronous mode Internal clock, SCK pin used for serial clock output 1 0 Synchronous mode External clock, SCK pin used for clock input* 4 Clocked synchronous mode External clock, SCK pin used for serial clock input 1 1 Synchronous mode External clock, SCK pin used for clock input* 4 Clocked synchronous mode External clock, SCK pin used for serial clock input Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to select the SCK function and the SCK input/output of the SCK pin. 2. Initial value 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. RENESAS 350 13.2.7 Serial Status Register The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is initialized to H'84 by a reset or in standby mode. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: Write 0 to clear flag. • Bit 7 (transmit data register empty (TDRE)): TDRE indicates that the SCI has loaded transmit data from the TDR into the TSR and serial transmit new data can be written in the TDR. Bit 7: TDRE Description 0 TDR contains valid transmit data TDRE is cleared to 0 when: • Software reads TDRE after it has been set to 1, then writes 0 in TDRE • The DMAC writes data in TDR 1 TDR does not contain valid transmit data (initial value) TDRE is set to 1 when: • The chip is reset or enters standby mode • The TE bit in the serial control register (SCR) is cleared to 0 • TDR contents are loaded into TSR, so new data can be written in TDR RENESAS 351 • Bit 6 (receive data register full (RDRF)): RDRF indicates that RDR contains received data. Bit 6: RDRF Description 0 RDR does not contain valid received data (initial value) RDRF is cleared to 0 when: • The chip is reset or enters standby mode • Software reads RDRF after it has been set to 1, then writes 0 in RDRF • The DMAC reads data from RDR 1 RDR contains valid received data. RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR. Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost. • Bit 5 (overrun error (ORER)): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER Description 0 Receiving is in progress or has ended normally (initial value)* 1 ORER is cleared to 0 when: • The chip is reset or enters standby mode • Software reads ORER after it has been set to 1, then writes 0 in ORER 1 A receive overrun error occurred*2 ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clocked synchronous mode, serial transmitting is disabled. RENESAS 352 • Bit 4 (framing error (FER)): FER indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Bit 4: FER Description 0 Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value (initial value). FER is cleared to 0 when: • The chip is reset or enters standby mode • Software reads FER after it has been set to 1, then writes 0 in FER 1 A receive framing error occurred. When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clocked synchronous mode, serial transmitting is also disabled. FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0. • Bit 3 (parity error (PER)): PER indicates that data reception (with parity) ended abnormally due to a parity error in the asynchronous mode. Bit 3: PER Description 0 Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value (initial value). PER is cleared to 0 when: • The chip is reset or enters standby mode • Software reads PER after it has been set to 1, then writes 0 in PER 1 A receive parity error occurred. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clocked synchronous mode, serial transmitting is also disabled. PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR). RENESAS 353 • Bit 2 (transmit end (TEND)): TEND indicates that when the last bit of a serial character was transmitted, the TDR did not contain new transmit data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2: TEND Description 0 Transmission is in progress TEND is cleared to 0 when: • Software reads TDRE after it has been set to 1, then writing 0 in TDRE • The DMAC writes data in TDR 1 End of transmission (initial value) TEND is set to 1 when: • The chip is reset or enters standby mode • TE is cleared to 0 in the serial control register (SCR) • TDRE is 1 when the last bit of a one-byte serial character is transmitted • Bit 1 (multiprocessor bit (MPB)): MPB stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written. Bit 1: MPB Description 0 Multiprocessor bit value in receive data is 0. If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value (initial value). 1 Multiprocessor bit value in receive data is 1 • Bit 0 (multiprocessor bit transfer (MPBT)): MPBT stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. The MPBT setting is ignored in the clocked synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT Description 0 Multiprocessor bit value in transmit data is 0 (initial value) 1 Multiprocessor bit value in transmit data is 1 RENESAS 354 13.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in standby mode. SCI1 and SCI2 have independent baud rate generator control, so different values can be set in the two channels. Bit: 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows examples of BBR settings in the clocked synchronous mode. Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) 2 Bit Rate (bits/s) n N 110 1 141 150 1 300 2.097152 Error (%) Error (%) n N 0.03 1 148 –0.04 103 0.16 1 108 0.21 0 207 0.16 0 217 0.21 600 0 103 0.16 0 108 0.21 1200 0 51 0.16 0 54 –0.70 2400 0 25 0.16 0 26 1.14 4800 0 12 0.16 0 13 –2.48 9600 — — — 0 6 –2.48 19200 — — — — — — 31250 0 1 0.00 — — — 38400 — — — — — — RENESAS 355 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 2.4576 3 3.6864 Bit Rate(bits/s) n N Error (%) n N Error (%) n N Error (%) 110 1 174 –0.26 1 212 0.03 2 64 0.70 150 1 127 0.00 1 155 0.16 1 191 0.00 300 0 255 0.00 1 77 0.16 1 95 0.00 600 0 127 0.00 0 155 0.16 0 191 0.00 1200 0 63 0.00 0 77 0.16 0 95 0.00 2400 0 31 0.00 0 38 0.16 0 47 0.00 4800 0 15 0.00 0 19 –2.34 0 23 0.00 9600 0 7 0.00 0 9 –2.34 0 11 0.00 19200 0 3 0.00 0 4 –2.34 0 5 0.00 31250 — — — 0 2 0.00 — — — 38400 0 1 0.00 — — — 0 2 0.00 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 4 4.9152 5 Bit Rate(bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 — — — 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 –1.70 0 4 0.00 38400 — — — 0 3 0.00 0 3 1.73 RENESAS 356 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 6 6.144 7.3728 Bit Rate(bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 –2.34 0 19 0.00 0 23 0.00 19200 0 9 –2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 — — — 38400 0 4 –2.34 0 4 0.00 0 5 0.00 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 8 9.8304 10 12 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34 31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00 38400 — — — 0 7 0.00 7 1.73 0 9 –2.34 0 RENESAS 357 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 12.288 14 14.7456 16 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 –0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 –0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 –1.70 0 15 0.00 38400 0 9 0.00 — — — 0 11 0.00 0 12 0.16 Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode (cont) φ (MHz) 17.2032 18 19.6608 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 1 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 0 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 –0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 –1.36 31250 0 16 1.20 0 17 0.00 0 19 –1.70 0 19 0.00 38400 0 13 0.00 0 14 –2.34 0 15 0.00 0 15 1.73 RENESAS 358 Table 13.4 Bit Rates and BRR Settings in Clocked Synchronous Mode φ (MHz) 2 4 8 10 16 20 Bit Rate (bits/s) n N n N n N n N n N n N 110 3 70 — — — — — — — — — — 250 2 124 2 249 3 124 — — 3 249 — — 500 1 249 2 124 2 249 — — 3 124 — — 1k 1 124 1 249 2 124 — — 2 249 — — 2.5k 0 199 1 99 1 199 1 249 2 99 2 124 5k 0 99 0 199 1 99 1 124 1 199 1 249 10k 0 49 0 99 0 199 0 249 1 99 1 124 25k 0 19 0 39 0 79 0 99 0 159 0 199 50k 0 9 0 19 0 39 0 49 0 79 0 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0√ 0 1 0 3 0 4 0 7 0 9 0 0* 0 1 — — 0 3 0 4 — — 0 0* — — 0 1 — — 0 0* 1M 2.5M 5M Note Settings with an error of 1% or less are recommended. Blank: No setting available —: Setting possible, but error occurs √: Continuous transmit/receive not possible The BRR setting is calculated as follows: Asynchronous mode N = [φ/(64 × 2 2n – 1 × B)] × 10 6 – 1 Clocked synchronous mode N = [φ/(8 × 2 2n – 1 × B)] × 10 6 – 1 B: bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: φ frequency (MHz) n: baud rate generator clock source (n = 0, 1, 2, 3) For the clock sources and values of n, see table 13.5. RENESAS 359 SMR Settings n Clock Source CKS1 CKS0 0 φ 0 0 1 φ/4 0 1 2 φ/16 1 0 3 φ/24 1 1 Find the bit rate error for the asynchronous mode by the following formula. Error (%) = {(φ × 10 6)/[(N + 1) × B × 64 × 22n – 1 ] – 1 } × 100 RENESAS 360 Table 13.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used. Tables 13.6 and 13.7 show the maximum rates for external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 RENESAS 361 Table 13.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6834 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 RENESAS 362 Table 13.7 Maximum Bit Rates during External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 13.3 Operation 13.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous/clocked synchronous mode and the communication format are selected in the serial mode register (SMR), as shown in table 13.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 13.9. Asynchronous Mode: • • • • Data length is selectable: seven or eight bits. Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The preceding selections constitute the communication format and character length. In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) RENESAS 363 Clocked Synchronous Mode: • • • The communication format has a fixed eight-bit data length. In receiving, it is possible to detect overrun errors (ORER). An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Table 13.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Mode Bit 7: Bit 6: Bit 5: Bit 2: Bit 3: C/A CHR PE MP STOP Data Parity Length Bit MultiproStop Bit cessor Bit Length Asynchronous 0 8-bit Absent 0 0 0 0 Absent 1 1 2 bits 0 Present 1 bit 1 1 0 0 2 bits 7-bit Absent 1 bit 1 1 2 bits 0 Present 1 bit 1 Asynchronous (multiprocessor format) Clocked synchronous 0 1 1 * * 1 0 * 1 * 0 * 1 * * * Note: Asterisks (*) in the table indicate don’t-care bits. RENESAS 364 1 bit 2 bits 8-bit Absent Present 1 bit 2 bits 7-bit 1 bit 2 bits 8-bit Absent None Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Bit 7: C/A Asynchronous 0 mode SCR Settings SCI Transmit/Receive Clock Bit 1: CKE1 Bit 0: CKE0 Clock Source SCK Pin Function* 0 0 Internal 1 1 0 SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Internal Outputs the serial clock External Inputs the serial clock 1 Clocked synchronous mode 1 0 0 1 1 0 1 Note: Select the function in combination with the pin function controller (PFC). RENESAS 365 13.3.2 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. 1 Serial data (LSB) 0 D0 (MSB) D1 D2 D3 D4 D5 Start bit D6 D7 Idling (mark state) 1 0/1 1 1 Parity bit Stop bit 1 or no bit 1 or 2 bits Transmit/receive data 1 bit 7 or 8 bits One unit of communication (characters or frames) Figure 13.2 Data Format in Asynchronous Communication (Example: 8-bit data with parity and two stop bits) RENESAS 366 Transmit/Receive Formats: Table 13.10 shows the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 13.10 Serial Communication Formats (asynchronous mode) SMR Bits CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 START 8-Bit data STOP 0 0 0 1 START 8-Bit data STOP STOP 0 1 0 0 START 8-Bit data P STOP 0 1 0 1 START 8-Bit data P STOP STOP 1 0 0 0 START 7-Bit data STOP 1 0 0 1 START 7-Bit data STOP STOP 1 1 0 0 START 7-Bit data P STOP 1 1 0 1 START 7-Bit data P STOP STOP 0 — 1 0 START 8-Bit data MPB STOP 0 — 1 1 START 8-Bit data MPB STOP STOP 1 — 1 0 START 7-Bit data MPB STOP 1 — 1 1 START 7-Bit data MPB STOP STOP —: Don't care bits. Note: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 13.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the RENESAS 367 desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.3 Phase Relationship Between Output Clock and Serial Data (asynchronous mode) Transmitting and Receiving Data (SCI initialization (asynchronous mode)): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 13.4 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is as follows: 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to SCR. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). RENESAS 368 Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR (2) Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) (3) Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary (4) End Note: Circled numbers refer to the preceding procedure. Figure 13.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (asynchronous mode): Figure 13.5 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is as follows: 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. RENESAS 369 Initialize (1) Start transmitting Read TDRE bit in SSR (2) No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR (3) All data transmitted? No Yes Read TEND bit in SSR No TEND = 1? Yes No Output break signal? (4) Yes Set DR = 0 Clear TE bit of SCR to 0; Select theTxD pin function as an output port with the PFC Transmission ends Note: Circled numbers refer to the preceding procedure. Figure 13.5 Sample Flowchart for Transmitting Serial Data RENESAS 370 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: 1. Start bit: one 0 bit is output. 2. Transmit data: seven or eight bits of data are output, LSB first. 3. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. 4. Stop bit: one or two 1 bits (stop bits) are output. 5. Mark state: output of 1 bits continues until the start bit of the next transmit data. 6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode. RENESAS 371 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Data D0 D1 Parity Stop 1 bit bit D7 0/1 1 Idle (mark state) TDRE TEND TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-bit data with parity and one stop bit) Receiving Serial Data (asynchronous mode): Figure 13.7 shows a sample flowchart for receiving serial data. The procedure for receiving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER and FER bits of the SSR to identify the error. After executing the necessary error handling, clear ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive data read: read the serial status register (SR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDRF and RDR, and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. RENESAS 372 Initialization (1) Start receiving Read the ORER, PER, and FER bits of the SSR PER, FER, ORER = 1? Yes (2) No Read the RDRF bit of the SSR No Error handling (3) RDRF = 1? Yes Read the RDR's receive data (4) and clear the SSR's RDRF bit to 0 No Total count received? Yes Clear the RE bit of the SCR to 0 Reception ends Note: Circled numbers refer to the preceding procedure. Figure 13.7 Sample Flowchart for Receiving Serial Data RENESAS 373 Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit to 0 in SCR PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Note: Circled numbers refer to the preceding procedure. Figure 13.7 Sample Flowchart for Receiving Serial Data (cont) RENESAS 374 In receiving, the SCI operates as follows: 1. The SCI monitors the receive data line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from the RSR into the RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.11. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 13.8 shows an example of SCI receive operation in the asynchronous mode. Table 13.11 Receive Error Conditions and SCI Operation Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while RDRF is still set to 1 in SSR Receive data not loaded from RSR into RDR Framing error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs from even/odd parity setting in SMR Receive data loaded from RSR into RDR RENESAS 375 1 Start bit Serial data 0 Parity Stop Start bit bit bit Data D0 D1 D7 1 0/1 0 Parity Stop bit bit Data D0 D1 D7 0/1 0 1 Idle (mark state) TDRE RXI request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0 Framing error, ERI request Figure 13.8 Example of SCI Receive Operation (8-bit data with parity and one stop bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13.9 shows the example of communication among processors using the multiprocessor format. RENESAS 376 Transmitting processor Serial communication line Serial data Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) H'01 H'AA (MPB = 1) ID-sending cycle: receiving processor address (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: multiprocessor bit Figure 13.9 Example of Communication among Processors Using Multiprocessor Format (sending data H'AA to receiving processor A) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 13.8. Clock: See the description in the asynchronous mode section. Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. RENESAS 377 Initialize (1) Start transmitting Read TDRE bit in SSR TDRE = 1? (2) No Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? No (3) Yes Read TEND bit in SSR TEND = 1? No Yes Output break signal? No (4) Yes Set DR = 0 Clear TE bit to 0 in SCR; select theTxD pin function as an output port with the PFC End Note: Circled numbers refer to the preceding procedure. Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data In transmitting serial data, the SCI operates as follows: RENESAS 378 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11): 1. 2. 3. 4. 5. 6. Start bit: one 0 bit is output. Transmit data: seven or eight bits are output, LSB first. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. Stop bit: one or two 1 bits (stop bits) are output. Mark state: output of 1 bits continues until the start bit of the next transmit data. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 1 Serial data Start bit 0 Multiprocessor Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 D0 Multiprocessor Stop 1 Data bit bit D1 D7 0/1 1 Idle (mark state) TDRE TEND TXI TXI interrupt request handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-bit data with multiprocessor bit and one stop bit) RENESAS 379 Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. ID receive cycle: set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). RENESAS 380 Initialization (1) Start receiving Set the MPIE bit of the SCR to 1 (2) Read the ORER and FER bits of the SSR FER = 1? or ORER = 1? No Read the RDRF bit of the SSR No Yes (3) RDRF = 1? Yes Read the receive data of the RDR No Own ID? Yes Read the ORER and FER bits of the SSR FER = 1? or ORER = 1? Yes No Read the SSR's RDRF bit RDRF = 1? (5) No Yes Read the RDR's receive data No Total count received? Yes Clear the RE bit of the SCR to 0 (4) Error handling Reception ends Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data RENESAS 381 Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER to 0 in SSR End Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) RENESAS 382 Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. 1 Serial data Stop Start Data ID1 MPB bit bit Start bit 0 D0 D1 D7 1 1 0 Data 1 D0 D1 D7 Stop 1 MPB bit 0 1 Idle (mark state) MPB MPIE RDRF RDR value RXI request, (multiprocessor interrupt) MPIE = 0 ID1 RXI interrupt handler reads data in RDR and clears RDRF to 0 Not own ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 13.13 Example of SCI Receive Operation (own ID does not match data) (8-bit data with multiprocessor bit and one stop bit) RENESAS 383 1 Serial data Start bit 0 Stop Start Data ID1 MPB bit bit D0 D1 D7 1 1 0 Data 1 D0 D1 D7 Stop 1 MPB bit 0 1 Idle (mark state) MPB MPIE RDRF RDR value RXI request, (multiprocessor interrupt) MPIE = 0 ID1 RXI interrupt handler reads data in RDR and clears RDRF to 0 Not own ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 13.13 Example of SCI Receive Operation (own ID matches data) (8-bit data with multiprocessor bit and one stop bit) (cont) 13.3.4 Clocked Synchronous Operation In the clocked synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13.14 shows the general format in clocked synchronous serial communication. RENESAS 384 Transfer direction One unit (character or frame) of serial data * * Serial clock LSB Serial data Note: Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 High except in continuous transmitting or receiving. Figure 13.14 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clocked synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 13.6. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. Figure 13.15 shows an example of SCI transmit operation. In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source RENESAS 385 is selected, the SCI outputs data in synchronization with the input clock. Data are output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from the TDR into the TSR, transmits the MSB, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Transmit direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE to 0 TXI request TEI request 1 frame Figure 13.15 Example of SCI Transmit Operation Transmitting and Receiving Data: SCI Initialization (clocked synchronous mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 13.16 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI is listed below. RENESAS 386 1. Select the communication format in the serial mode register (SMR). 2. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 3. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE. Setting the corresponding bit of the pin function controller, TE and RE enables the SCI to use the TxD or RxD pin. Start of initialization Clear TE and RE bits to 0 in SCR Select communication format in SMR (1) Set value in BRR (2) Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (leaving TE and RE cleared to 0) (3) Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE (4) End Note: High except in continuous transmitting or receiving. Figure 13.16 Sample Flowchart for SCI Initialization RENESAS 387 Transmitting Serial Data (clocked synchronous mode): Figure 13.17 shows a sample flowchart for transmitting serial data. The procedure for transmitting serial data is listed below. 1. SCI initialization: select the TxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-dataempty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. RENESAS 388 Initialize (1) Start transmitting Read TDRE bit in SSR TDRE = 1? (2) No Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR All data transmitted? No (3) Yes Read TEND bit in SSR TEND = 1? No Yes Clear TE bit SCR to 0 Transmission ends Figure 13.17 Sample Flowchart for Serial Transmitting Receiving Serial Data (clocked synchronous mode): Figure 13.18 shows a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clocked synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an example of SCI recieve operation. The procedure for recieving serial data is listed below. 1. SCI initialization: select the RxD pin function with the PFC. 2. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving RENESAS 389 cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Initialization (1) Start receiving Read the ORER bit of the SSR Yes ORER = 1? No (2) Error handling Read RDRF bit of the SSR No (3) RDRF = 1? Yes Read the RDR's receive data (4) and clear the SSR's RDRF bit to 0 No Total count received? Yes Clear the RE bit of the SCR to 0 Reception ends Figure 13.18 Sample Flowchart for Serial Receiving RENESAS 390 Error handling No ORER = 1? Yes Overrun error handling Clear ORER bit of SSR to 0 End Figure 13.18 Sample Flowchart for Serial Receiving (cont) Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF to 0 RXI request Overrun error, ERI request 1 frame Figure 13.19 Example of SCI Receive Operation In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the RENESAS 391 RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If the check does not pass (receive error), the SCI operates as indicated in table 13.8. When the error flag is set to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during reception. When restarting the reception, make sure to clear the error flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (clocked synchronous mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure for transmitting and receiving serial data simultaneously is listed below. 1. SCI initialization: select the TxD and RxD pin function with the PFC. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. To continue transmitting and receiving serial data: read the RDRF bit and RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. RENESAS 392 Initialization (1) Start transmitting and receiving Read TDRE bit of the SSR No (2) TDRE = 1? Yes Write transmit data to the TDR and clear the TDRE bit of the SSR to 0 Read the ORER bit of the SSR ORER = 1? No Read the SSR's RDRF bit No Yes (3) Error handling (4) RDRF = 1? Yes Read the receive data of the RDR and clear the RDRF bit of the SSR to 0 No (5) Total count transmitted and received? Yes Clear the TE and RE bits of the SCR to 0 Transmitting/receiving ends Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1. Figure 13.20 Sample Flowchart for Serial Transmitting RENESAS 393 13.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in the SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC executes the data transfer to the transmit data register (TDR). RXI is requested when the RDRF bit in the SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC executes the data transfer to the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC. A TXI interrupt indicates that transmit data writing is enabled. A TEI interrupt indicates that the transmit operation is complete. Table 13.12 SCI Interrupt Sources Interrupt Source Description DMAC Availability Priority ERI Receive error (ORER, PER, or FER) No High RXI Receive data full (RDRF) Yes ↑ TXI Transmit data empty (TDRE) Yes ↓ TEND Transmit end (TEND) No Low 13.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from the TDR into the TSR. The SCI sets TDRE to 1 when it transfers data from the TDR to the TSR. If new data is written in the TDR when TDRE is 0, the old data stored in the TDR will be lost because these data have not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the RDR, so receive data is lost. RENESAS 394 Table 13.13 SSR Status Flags and Transfer of Receive Data Receive Error Status RDRF ORER FER PER Receive Data Transfer RSR → RDR Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X SSR Status Flags O: X: Receive data is transferred from RSR–RDR. Receive data is not transferred from RSR–RDR. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: When TE is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by the data register (DR) of the I/O port and the control register (CR) of the PFC. This feature can be used to send a break signal. The DR value substitutes for the mark state until the PFC setting is performed. The DR bits should therefore be set as an output port that outputs 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0, and select output port as the TxD pin function by the PFC. When TE is cleared to 0, the transmitter is initialized, regardless of its current state. Receive Error Flags and Transmitter Operation (clocked synchronous mode only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: In the asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse. See figure 13.21. RENESAS 395 16 clocks 8 clocks Internal base clock 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 –7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as in equation 1. Equation 1: M = M: N: D: L: F: 0.5 – 1 2N – (L – 0.5)F – D – 0.5 N (1 + F ) × 100% Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0–1.0) Frame length (L = 9–12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2. Equation 2: D M = 0.5, F = 0 = (0.5 – 1/(2 × 16)) × 100% = 46.875% (2) This is a theoretical value. A reasonable margin to allow in system designs is 20–30%. Constraints on DMAC Use: RENESAS 396 • • When using an external clock source for the serial clock, update the TDR with the DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 13.22). Before reading the receive data register (RDR) with the DMAC, select the receive-data-full interrupt of the SCI as a start-up source using the resource select bit (RS) in the channel control register (CHCR). SCK t TDRE D0 Note: D1 D2 D3 D4 D5 D6 D7 During external clock operation, an error may occur if t is 4φ or less. Figure 13.22 Clocked Synchronous Transmitting Example with DMAC Cautions for Clocked Synchronous External Clock Mode: • • • Set TE = RE = 1 only when the external clock SCI is 1. Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0 to 1. When receiving, RDRF = 1 when RE is set to zero 2.5–3.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to RDR. Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF = 1 when RE is set to zero 1.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to RDR. RENESAS 397 Section 14 Pin Function Controller (PFC) 14.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the LSI. Table 14.1 lists the multiplexed pins. Table 14.1 List of Multiplexed Pins Port Function 1 Function 2 (related module) (related module) Function 3 (related module) Function 4 (related module) Pin # A PA15 I/O (port) IRQ3 input (INTC) DREQ1 input (DMAC) — 68 A PA14 I/O (port) IRQ2 input (INTC) DACK1 output (DMAC) — 67 A PA13 I/O (port) IRQ1 input (INTC) TCLKB input (ITU) DREQ0 input (DMAC) 66 A PA12 I/O (port) IRQ0 input (INTC) TCLKA input (ITU) DACK0 output (DMAC) 65 A PA11 I/O (port) DPH I/O (D bus) TIOCB1 I/O (ITU) — 64 A PA10 I/O (port) DPL I/O (D bus) TIOCA1 I/O (ITU) — 62 A PA9 I/O (port) AH output (BSC) — IRQOUT output (INTC) 61 A PA8 I/O (port) BREQ input (system) — — 60 A PA7 I/O (port) BACK output (system) — — 58 A PA6 I/O (port) RD output (BSC) — — 57 A PA5 I/O (port) WRH output (BSC) (LBS output (BSC))* 1 — — 56 A PA4 I/O (port) WRL output — (BSC) (WR output (BSC))*1 — 55 A PA3 I/O (port) CS7 output (BSC) WAIT input (BSC) — 54 A PA2 I/O (port) CS6 output (BSC) TIOCB0 I/O (ITU) — 53 A PA1 I/O (port) CS5 output (BSC) RAS output (BSC) — 52 A PA0 I/O (port) CS4 output (BSC) TIOCA0 I/O (ITU) — 51 RENESAS 399 Table 14.1 List of Multiplexed Pins (cont) Port Function 1 Function 2 (related module) (related module) Function 3 (related module) Function 4 (related module) Pin # B PB15 I/O (port) IRQ7 input (INTC) — TP15 output (TPC) 100 B PB14 I/O (port) IRQ6 input (INTC) — TP14 output (TPC) 99 B PB13 I/O (port) IRQ5 input (INTC) SCK1 I/O (SCI) TP13 output (TPC) 98 B PB12 I/O (port) IRQ4 input (INTC) SCK0 I/O (SCI) TP12 output (TPC) 97 B PB11 I/O (port) TxD1 output (SCI) TP11 output (TPC) — 96 B PB10 I/O (port) RxD1 input (SCI) TP10 output (TPC) — 95 B PB9 I/O (port) TxD0 output (SCI) TP9 output (TPC) — 94 B PB8 I/O (port) RxD0 input (SCI) TP8 output (TPC) — 93 B PB7 I/O (port) TCLKD input (ITU) TOCXB4 output (ITU) TP7 output (TPC) 91 B PB6 I/O (port) TCLKC input (ITU) TOCXA4 output (ITU) TP6 output (TPC) 90 B PB5 I/O (port) TIOCB4 I/O (ITU) TP5 output (TPC) — 89 B PB4 I/O (port) TIOCA4 I/O (ITU) TP4 output (TPC) — 87 B PB3 I/O (port) TIOCB3 I/O (ITU) TP3 output (TPC) — 86 B PB2 I/O (port) TIOCA3 I/O (ITU) TP2 output (TPC) — 85 B PB1 I/O (port) TIOCB2 I/O (ITU) TP1 output (TPC) — 84 B PB0 I/O (port) TIOCA2 I/O (ITU) TP0 output (TPC) — 83 — CS1 output (BSC) CASH output (BSC) — — 47 — CS3 output (BSC) CASL output (BSC) — — 49 INTC: Interrupt controller DMAC: Direct memory access controller ITU: 16-bit integrated timer pulse unit D bus: Data bus control BSC: Bus state controller System: System control SCI: Serial communications interface TPC: Programmable timing pattern controller Port: I/O port Notes: 1. The bus control register of the bus state controller handles switching between the two functions. RENESAS 400 14.2 Register Configuration Table 14.2 summarizes the registers of the pin function controller. Table 14.2 Pin Function Controller Registers Name Abbreviation R/W Initial Value Address Access Size Port A I/O register PAIOR R/W H'0000 H'5FFFFC4 8, 16, 32 Port A control register 1 PACR1 R/W H'3302 H'5FFFFC8 8, 16, 32 Port A control register 2 PACR2 R/W H'FF95 H'5FFFFCA 8, 16, 32 Port B I/O register PBIOR R/W H'0000 H'5FFFFC6 8, 16, 32 Port B control register 1 PBCR1 R/W H'0000 H'5FFFFCC 8, 16, 32 Port B control register 2 PBCR2 R/W H'0000 H'5FFFFCE 8, 16, 32 Column address strobe pin control register CASCR R/W H'5FFF H'5FFFFEE 8, 16, 32 14.3 Register Descriptions 14.3.1 Port A I/O Register (PAIOR) The port A I/O register (PAIOR) is a 16-bit read/write register that selects input or output for individual pins on a bit-by-bit basis. Bits PA15IOR–PA0IOR correspond to pins PA15/IRQ3/DREQ1–PA0/CS4/TIOCA0. PAIOR is enabled when the port A pins function as input/outputs (PA15–PA0) and for ITU input capture and output compare (TIOCA1, TIOCA0, TIOCB1, and TIOCB0). For other functions, they are disabled. For port A pin functions PA15– PA0 and TIOCA1, TIOCA0, TIOCB1, and TIOCB0, a given pin in port A is an output pin if its corresponding PAIOR bit is set to 1, and an input pin if the bit is cleared to 0. PAIOR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets, standby mode, or sleep mode. RENESAS 401 Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 14.3.2 15 14 13 12 11 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Port A Control Registers (PACR1 and PACR2) PACR1 and PACR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port A. PACR1 selects the function of the top eight bits of port A; PACR2 selects the function of the bottom eight bits of port A. PACR1 and PACR2 are initialized to H'3302 and H'FF95 respectively by power-on resets but are not initialized for manual resets, standby mode, or sleep mode. PACR1: Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: • 15 14 13 12 11 10 9 8 PA15 MD1 PA15 MD0 PA14 MD1 PA14 MD0 PA13 MD1 PA13 MD0 PA12 MD1 PA12 MD0 0 0 1 1 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA11 MD1 PA11 MD0 PA10 MD1 PA10 MD0 — PA8MD 0 0 0 0 0 0 1 0 R/W R/W R/W R/W R/W R/W — R/W PA9MD1 PA9MD0 Bits 15 and 14 (PA15 mode (PA15MD1 and PA15MD0)): PA15MD1 and PA15MD0 select the function of the PA15/IRQ3/DREQ1 pin. RENESAS 402 Bit 15: PA15MD1 Bit 14: PA15MD0 Function 0 0 Input/output (PA15) (initial value) 1 Interrupt request input (IRQ3) 0 Reserved 1 DMA transfer request input (DREQ1) 1 • Bits 13 and 12 (PA14 mode (PA14MD1 and PA14MD0)): PA14MD1 and PA14MD0 select the function of the PA14/IRQ2/DACK1 pin. Bit 13: PA14MD1 Bit 12: PA14MD0 Function 0 0 Input/output (PA14) 1 Interrupt request input (IRQ2) 0 Reserved 1 DMA transfer acknowledge output (DACK1) (initial value) 1 • Bits 11 and 10 (PA13 Mode (PA13MD1 and PA13MD0)): PA13MD1 and PA13MD0 select the function of the PA13/IRQ1/DREQ0/TCLKB pin. Bit 11: PA13MD1 Bit 10: PA13MD0 Function 0 0 Input/output (PA13) (initial value) 1 Interrupt request input (IRQ1) 0 ITU timer clock input (TCLKB) 1 DMA transfer request input (DREQ0) 1 • Bits 9 and 8 (PA12 mode (PA12MD1 and PA12MD0)): These bits select the function of the PA12/IRQ0/DACK0/TCLKA pin. Bit 9: PA12MD1 Bit 8: PA12MD0 Function 0 0 Input/output (PA12) 1 Interrupt request input (IRQ0) 0 ITU timer clock input (TCLKA) 1 DMA transfer acknowledge output (DACK0) (initial value) 1 RENESAS 403 • Bits 7 and 6 (PA11 mode (PA11MD1 and PA11MD0)): These bits select the function of the PA11/DPH/TIOCB1 pin. Bit 7: PA11MD1 Bit 6: PA11MD0 Function 0 0 Input/output (PA11) (initial value) 1 Upper data bus parity input/output (DPH) 0 ITU input capture/output compare (TIOCB1) 1 Reserved 1 • Bits 5 and 4 (PA10 mode (PA10MD1 and PA10MD0)): These bits select the function of the PA10/DPL/TIOCA1 pin. Bit 5: PA10MD1 Bit 4: PA10MD0 Function 0 0 Input/output (PA10) (initial value) 1 Lower data bus parity input/output (DPL) 0 ITU input capture/output compare (TIOCA1) 1 Reserved 1 • Bits 3 and 2 (PA9 mode (PA9MD1 and PA9MD0)): These bits select the function of the PA9/AH/IRQOUT pin. Bit 3: PA9MD1 Bit 2: PA9MD0 Function 0 0 Input/output (PA9) (initial value) 1 Address hold output (AH) 0 Reserved 1 Interrupt request output (IRQOUT) 1 • Bit 1 (reserved): This bit always reads as 1. The write value should always be 1. • Bit 0 (PA8 mode (PA8MD)): PA8MD selects the function of the PA8/BREQ. Bit 0: PA8MD Function 0 Input/output (PA8) (initial value) 1 Bus request input (BREQ) RENESAS 404 PACR2: Bit: 15 14 13 12 11 10 9 8 Bit name: — PA7MD — PA6MD — PA5MD — PA4MD Initial value: 1 1 1 1 1 1 1 1 R/W: — R/W — R/W — R/W — R/W Bit: 7 6 5 4 3 2 1 0 Bit name: PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 Initial value: R/W: 1 0 0 1 0 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W • Bit 15 (reserved): This bit always reads as 1. The write value should always be 1. • Bit 14 (PA7 mode (PA7MD)): PA7MD selects the function of the PA7/BACK pin. Bit 14: PA7MD Function 0 Input/output (PA7) 1 Bus request acknowledge output (BACK) (initial value) • Bit 13 (reserved): This bit always reads as 1. The write value should always be 1. • Bit 12 (PA6 mode (PA6MD)): PA6MD selects the function of the PA6/RD pin. Bit 12: PA6MD Function 0 Input/output (PA6) 1 Read output (RD) (initial value) • Bit 11 (reserved): This bit always reads as 1. The write value should always be 1. • Bit 10 (PA5 mode (PA5MD)): PA5MD selects the function of the PA5/WRH (LBS) pin. Bit 10: PA5MD Function 0 Input/output (PA5) 1 Upper write output (WRH) or lower byte strobe output (LBS) (initial value) • Bit 9 (reserved): This bit always reads as 1. The write value should always be 1. RENESAS 405 • Bit 8 (PA4 mode (PA4MD)): PA4MD selects the function of the PA4/WRL (WR) pin. Bit 8: PA4MD Function 0 Input/output (PA4) 1 Lower write output (WRL) or write output (WR) (initial value) • Bits 7 and 6 (PA3 mode (PA3MD1 and PA3MD0)): PA3MD1 and PA3MD0 select the function of the PA3/CS7/WAIT pin. This pin has a pull-up MOS that is used when it functions as a WAIT pin to allow selection of pull up or no pull up (for the WAIT pin) using the wait state control register of the bus state controller (BSC). There is no pull up when if functions as PA3 or CS7. Bit 7: PA3MD1 Bit 6: PA3MD0 Function 0 0 Input/output (PA3) 1 Chip select output (CS7) 0 Wait state input (WAIT) (initial value) 1 Reserved 1 • Bits 5 and 4 (PA2 mode (PA2MD1 and PA2MD0)): PA2MD1 and PA2MD0 select the function of the PA2/CS6/TIOCB0 pin. Bit 5: PA2MD1 Bit 4: PA2MD0 Function 0 0 Input/output (PA2) 1 Chip select output (CS6) (initial value) 0 ITU input capture/output compare (TIOCB0) 1 Reserved 1 • Bits 3 and 2 (PA1 mode (PA1MD1 and PA1MD0)): PA1MD1 and PA1MD0 select the function of the PA1/CS5/RAS pin. Bit 3: PA1MD1 Bit 2: PA1MD0 Function 0 0 Input/output (PA1) 1 Chip select output (CS5) (initial value) 0 Row address strobe output (RAS) 1 Reserved 1 RENESAS 406 • Bits 1 and 0 (PA0 mode (PA0MD1 and PA0MD0)): PA0MD1 and PA0MD0 select the function of the PA0/CS4/TIOCA0 pin. Bit 1: PA0MD1 Bit 0: PA0MD0 Function 0 0 Input/output (PA0) 1 Chip select output (CS4) (initial value) 0 ITU input capture/output compare (TIOCA0) 1 Reserved 1 14.3.3 Port B I/O Register (PBIOR) The port B I/O register (PBIOR) is a 16-bit read/write register that selects input or output for individual pins on a bit-by-bit basis. Bits PB15IOR–PB0IOR correspond to pins of port B. PBIOR is enabled when the port B pins function as input/outputs (PB15–PB0), for ITU input capture and output compare (TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2), and as serial clocks (SCK1, SCK0). For other functions, they are disabled. For port B pin functions PB15–PB0, and TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2, and SCK1/SCK0, a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1, and an input pin if the bit is cleared to 0. PBIOR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets, standby mode, or sleep mode. Bit: Bit name: Initial value: R/W: Bit: Bit name: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W RENESAS 407 14.3.4 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port B. PBCR1 selects the function of the top eight bits of port B; PBCR2 selects the function of the bottom eight bits of port B. PBCR1 and PBCR2 are initialized to H'0000 by power-on resets but are not initialized for manual resets, standby mode, or sleep mode. PBCR1: Bit: Bit name: 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Bit name: Initial value: R/W: • Bits 15 and 14 (PB15 mode (PB15MD1 and PB15MD0)): PB15MD1 and PB15MD0 select the function of the PB15/TP15/IRQ7 pin. Bit 15: PB15MD1 Bit 14: PB15MD0 Function 0 0 Input/output (PB15) (initial value) 1 Interrupt request input (IRQ7) 0 Reserved 1 Timing pattern output (TP15) 1 • Bits 13 and 12 (PB14 mode (PB14MD1 and PB14MD0)): PB14MD1 and PB14MD0 select the function of the PB14/TP14/IRQ6 pin. Bit 13: PB14MD1 Bit 12: PB14MD0 Function 0 0 Input/output (PB14) (initial value) 1 Interrupt request input (IRQ6) 0 Reserved 1 Timing pattern output (TP14) 1 RENESAS 408 • Bits 11 and 10 (PB13 mode (PB13MD1 and PB13MD0)): PB13MD1 and PB13MD0 select the function of the PB13/TP13/IRQ5/SCK1 pin. Bit 11: PB13MD1 Bit 10: PB13MD0 Function 0 0 Input/output (PB13) (initial value) 1 Interrupt request input (IRQ5) 0 Serial clock input/output (SCK1) 1 Timing pattern output (TP13) 1 • Bits 9 and 8 (PB12 mode (PB12MD1 and PB12MD0)): PB12MD1 and PB12MD0 select the function of the PB12/TP12/IRQ4/SCK0 pin. Bit 9: PB12MD1 Bit 8: PB12MD0 Function 0 0 Input/output (PB12) (initial value) 1 Interrupt request input (IRQ4) 0 Serial clock input/output (SCK0) 1 Timing pattern output (TP12) 1 • Bits 7 and 6: PB11 mode (PB11MD1 and PB11MD0): PB11MD1 and PB11MD0 select the function of the PB11/TP11/TxD1 pin. Bit 7: PB11MD1 Bit 6: PB11MD0 Function 0 0 Input/output (PB11) (initial value) 1 Reserved 0 Transmit data output (TxD1) 1 Timing pattern output (TP11) 1 • Bits 5 and 4 (PB10 mode (PB10MD1 and PB10MD0): PB10MD1 and PB10MD0 select the function of the PB10/TP10/RxD1 pin. Bit 5: PB10MD1 Bit 4: PB10MD0 Function 0 0 Input/output (PB10) (initial value) 1 Reserved 0 Receive data input (RxD1) 1 Timing pattern output (TP10) 1 RENESAS 409 • Bits 3 and 2 (PB9 mode (PB9MD1 and PB9MD0)): PB9MD1 and PB9MD0 select the function of the PB9/TP9/TxD0 pin. Bit 3: PB9MD1 Bit 2: PB9MD0 Function 0 0 Input/output (PB9) (initial value) 1 Reserved 0 Transmit data output (TxD0) 1 Timing pattern output (TP9) 1 • Bits 1 and 0 (PB8 mode (PB8MD1 and PB8MD0)): PB8MD1 and PB8MD0 select the function of the PB8/TP8/RxD0 pin. Bit 1: PB8MD1 Bit 0: PB8MD0 Function 0 0 Input/output (PB8) (initial value) 1 Reserved 0 Receive data input (RxD0) 1 Timing pattern output (TP8) 1 PBCR2: Bit: 15 14 13 12 11 10 9 8 Bit name: PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit name: PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 Initial value: R/W: RENESAS 410 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W • Bits 15 and 14 (PB7 mode (PB7MD1 and PB7MD0)): PB7MD1 and PB7MD0 select the function of the PB7/TP7/TOCXB4/TCLKD pin. Bit 15: PB7MD1 Bit 14: PB7MD0 Function 0 0 Input/output (PB7) (initial value) 1 ITU timer clock input (TCLKD) 0 ITU output compare (TOCXB4) 1 Timing pattern output (TP7) 1 • Bits 13 and 12 (PB6 mode (PB6MD1 and PB6MD0)): PB6MD1 and PB6MD0 select the function of the PB6/TP6/TOCXA4/TCLKC pin. Bit 13: PB6MD1 Bit 12: PB6MD0 Function 0 0 Input/output (PB6) (initial value) 1 ITU timer clock input (TCLKC) 0 ITU output compare (TOCXA4) 1 Timing pattern output (TP6) 1 • Bits 11 and 10 (PB5 mode (PB5MD1 and PB5MD0)): PB5MD1 and PB5MD0 select the function of the PB5/TP5/TIOCB4 pin. Bit 11: PB5MD1 Bit 10: PB5MD0 Function 0 0 Input/output (PB5) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCB4) 1 Timing pattern output (TP5) 1 • Bits 9 and 8 (PB4 mode (PB4MD1 and PB4MD0)): PB4MD1 and PB4MD0 select the function of the PB4/TP4/TIOCA4 pin. Bit 9: PB4MD1 Bit 8: PB4MD0 Function 0 0 Input/output (PB4) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCA4) 1 Timing pattern output (TP4) 1 RENESAS 411 • Bits 7 and 6 (PB3 mode (PB3MD1 and PB3MD0)): PB3MD1 and PB3MD0 select the function of the PB3/TP3/TIOCB3 pin. Bit 7: PB3MD1 Bit 6: PB3MD0 Function 0 0 Input/output (PB3) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCB3) 1 Timing pattern output (TP3) 1 • Bits 5 and 4 (PB2 mode (PB2MD1 and PB2MD0)): PB2MD1 and PB2MD0 select the function of the PB2/TP2/TIOCA3 pin. Bit 5: PB2MD1 Bit 4: PB2MD0 Function 0 0 Input/output (PB2) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCA3) 1 Timing pattern output (TP2) 1 • Bits 3 and 2 (PB1 mode (PB1MD1 and PB1MD0)): PB1MD1 and PB1MD0 select the function of the PB1/TP1/TIOCB2 pin. Bit 3: PB1MD1 Bit 2: PB1MD0 Function 0 0 Input/output (PB1) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCB2) 1 Timing pattern output (TP1) 1 • Bits 1 and 0 (PB0 mode (PB0MD1 and PB0MD0)): PB0MD1 and PB0MD0 select the function of the PB0/TP0/TIOCA2 pin. Bit 1: PB0MD1 Bit 0: PB0MD0 Function 0 0 Input/output (PB0) (initial value) 1 Reserved 0 ITU input capture/output compare (TIOCA2) 1 Timing pattern output (TP0) 1 RENESAS 412 14.3.5 Column Address Strobe Pin Control Register (CASCR) CASCR is a 16-bit read/write register that allows selection between column address strobe and chip select pin functions. The CASCR is initialized to H'5FFF by power-on resets but is not initialized for manual resets, standby mode, or sleep mode. Bit: Bit name: 15 14 13 12 11 10 9 8 CASH MD1 CASH MD0 CASL MD1 CASL MD0 — — — — Initial value: 0 1 0 1 1 1 1 1 R/W R/W R/W R/W — — — — Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: — — — — — — — — R/W: • Bits 15 and 14 (CASH mode (CASHMD1 and CASHMD0)): CASHMD1 and CASHMD0 select the function of the CS1/CASH pin. Bit 15: CASHMD1 Bit 14: CASHMD0 Function 0 0 Reserved 1 Chip select output (CS1) (initial value) 0 Column address strobe output (CASH) 1 Reserved 1 • Bits 13 and 12 (CASL mode (CASLMD1 and CASLMD0)): CASLMD1 and CASLMD0 select the function of the CS3/CASL pin. Bit 13: CASLMD1 Bit 12: CASLMD0 Function 0 0 Reserved 1 Chip select output (CS3) (initial value) 0 Column address strobe output (CASL) 1 Reserved 1 • Bits 11–0 (reserved): This bit always reads as 1. The write value should always be 1. RENESAS 413 Section 15 Parallel I/O Ports 15.1 Overview There are two ports, A and B. Ports A and B are 16-bit I/O ports. The pins of the ports are all multiplexed for use as general-purpose I/Os or for other functions. (Use the pin function controller (PFC) to select the function of multiplexed pins.) Ports A and B each have one data register for storing pin data. 15.2 Port A Port A is a 16-pin input/output port, as shown in figure 15.1. The PA3/CS7/WAIT pin of port A has a pull-up MOS so that when it is functioning as a WAIT pin, the wait state control register of the bus state controller can be used to select whether to pull up the WAIT pin or not. It is not pulled up when the pin is functioning as either PA3 or CS7. Port A PA15 (Input/output)/IRQ3 (Input)/DREQ1 (Input) PA14 (Input/output)/IRQ2 (Input)/DACK1 (Output) PA13 (Input/output)/IRQ1 (Input)/DREQ0 (Input)/TCLKB (Input) PA12 (Input/output)/IRQ0 (Input)/DACK0 (Output)/TCLKA (Input) PA11 (Input/output)/DPH (Input/output)/TIOCB1 (Input/output) PA10 (Input/output)/DPL (Input/output)/TIOCA1 (Input/output) PA9 (Input/output)/AH (Output)/IRQOUT (Output) PA8 (Input/output)/BREQ (Input) PA7 (Input/output)/BACK (Output) PA6 (Input/output)/RD (Output) PA5 (Input/output)/WRH (Output) (LBS (Output)) PA4 (Input/output)/WRL (Output) (WR (Output)) PA3 (Input/output)/CS7 (Output)/WAIT (Input) PA2 (Input/output)/CS6 (Output)/TIOCB0 (Input/output) PA1 (Input/output)/CS5 (Output)/RAS (Output) PA0 (Input/output)/CS4 (Output)/TIOCA0 (Input/output) Figure 15.1 Port A Configuration 15.2.1 Register Configuration Table 15.1 summarizes the port A register. RENESAS 415 Table 15.1 Port A Register Name Abbreviation R/W Initial Value Address Access Size Port A data register PADR R/W H'0000 H'5FFFFC0 8, 16, 32 15.2.2 Port A Data Register (PADR) PADR is a 16-bit read/write register that stores data for port A. The bits PA15DR–PA0DR correspond to the PA15/IRQ3/DREQ1–PA0/CS4/TIOCA0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PADR; when PADR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADR is read. When a value is written to PADR, that value can be written into PADR, but it will not affect the pin status. Table 15.2 shows the read/write operations of the port A data register. PADR is initialized by a power-on reset. However, PADR is not initialized for manual reset, standby mode, or sleep mode. Bit: Bit name: 15 13 12 11 10 9 8 PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR Initial value: R/W: Bit: Bit name: 14 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7DR PA6DR Initial value: R/W: PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 15.2 Read/Write Operation of the Port A Data Register (PADR) PAIOR Pin Status Read Write 0 Input Pin status Can write to PADR, but it has no effect on pin status. Other function Pin status Can write to PADR, but it has no effect on pin status. Output PADR value Value written is output by pin Other function PADR value Can write to PADR, but it has no effect on pin status. 1 RENESAS 416 15.3 Port B Port B is a 16-bit input/output port as shown in figure 16.2. Port B PB15 (Input/output)/TP15 (Output)/IRQ7 (Input) PB14 (Input/output)/TP14 (Output)/IRQ6 (Input) PB13 (Input/output)/TP13 (Output)/IRQ5 (Input)/SCK1 (Input/output) PB12 (Input/output)/TP12 (Output)/IRQ4 (Input)/SCK0 (Input/output) PB11 (Input/output)/TP11 (Output)/TxD1 (Output) PB10 (Input/output)/TP10 (Output)/RxD1 (Input) PB9 (Input/output)/TP9 (Output)/TxD0 (Output) PB8 (Input/output)/TP8 (Output)/RxD0 (Input) PB7 (Input/output)/TP7 (Output)/TOCXB4 (Output)/TCLKD (Input) PB6 (Input/output)/TP6 (Output)/TOCXA4 (Output)/TCLKC (Input) PB5 (Input/output)/TP5 (Output)/TIOCB4 (Output) PB4 (Input/output)/TP4 (Output)/TIOCA4 (Output) PB3 (Input/output)/TP3 (Output)/TIOCB3 (Input/output) PB2 (Input/output)/TP2 (Output)/TIOCA3 (Input/output) PB1 (Input/output)/TP1 (Output)/TIOCB2 (Input/output) PB0 (Input/output)/TP0 (Output)/TIOCA2 (Input/output) Figure 15.2 Port B Configuration 15.3.1 Register Configuration Table 15.3 summarizes the port B register. Table 15.3 Port B Register Name Abbreviation R/W Initial Value Address Access Size Port B data register PBDR R/W H'0000 H'5FFFFC2 8, 16, 32 RENESAS 417 15.3.2 Port B Data Register (PBDR) PBDR is a 16-bit read/write register that stores data for port B. The bits PB15DR–PB0DR correspond to the PB15/TP15/IRQ7–PB0/TP0/TIOCA2 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PBDR is read. When a value is written to PBDR, that value can be written into PBDR, but it will not affect the pin status. When the pin function is set to timing pattern output and the TPC output is enabled by the TPC next data enable register (NDER), no value can be written to PBDR. Table 15.4 shows the read/write operations of the port B data register. PBDR is initialized by a power-on reset. However, PBDR is not initialized for a manual reset, standby mode, or sleep mode. Bit: Bit name: 15 13 12 11 10 9 8 PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR Initial value: R/W: Bit: Bit name: 14 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DR PB6DR Initial value: R/W: PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 15.4 Read/Write Operation of the Port B Data Register (PBDR) PBIOR Pin Status Read Write 0 Input Pin status Can write to PBDR, but it has no effect on pin status TPn Pin status Disabled Other function Pin status Can write to PBDR, but it has no effect on pin status Output PBDR value Value written is output by pin TPn PBDR value Disabled Other function PBDR value Can write to PBDR, but it has no effect on pin status 1 TPn: Timing pattern output RENESAS 418 Section 16 ROM 16.1 Overview The SH7020 microcomputer has 16 kbytes of on-chip ROM (mask ROM). The SH7021 microcomputer has 32 kbytes of on-chip ROM (mask ROM or PROM). The on-chip ROM is connected to the CPU and the direct memory access controller (DMAC) through a 32-bit data bus (figure 16.1). The CPU can access the on-chip ROM in 8-, 16- and 32-bit widths and the DMAC can access the ROM in 8- and 16-bit widths. Data in the on-chip ROM can always be accessed in one cycle. RENESAS 419 SH7020 Internal data bus (32 bits) H'0000000 H'0000001 H'0000002 H'0000003 H'0000004 H'0000005 H'0000006 H'0000007 On-chip ROM H'0003FFC H'0003FFD H'0003FFE H'0003FFF SH7021 Internal data bus (32 bits) H'0000000 H'0000001 H'0000002 H'0000003 H'0000004 H'0000005 H'0000006 H'0000007 On-chip ROM H'0007FFC Note: H'0007FFD H'0007FFE H'0007FFF The addresses shown in the figure are the first shadow addresses in the on-chip ROM space. Figure 16.1 Block Diagram of ROM The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins MD0-MD2 as shown in table17.1. If you are using the on-chip ROM, select mode 2; if you are not, select mode 0 or 1. The on-chip ROM is allocated to address H'0000000–H'0003FFF (SH7020), H'0000000–H'0007FFF (SH7021) of memory area 0. Memory area 0 (H'0000000-H'0FFFFFF and H'8000000–H'8FFFFFF) is divided into 16-kbyte (SH7020) or 32-kbyte (SH7021) shadows. No matter which shadow is accessed, the on-chip ROM is accessed. See section 8, Bus State Controller, for more information on shadows. 420 RENESAS Table 16.1 Operating Modes and ROM Mode Setting Pin Operating Mode MD2 MD1 MD0 Area 0 Mode 0 (MCU mode 0) 0 0 0 On-chip ROM invalid, external 8-bit space Mode 1 (MCU mode 1) 0 0 1 On-chip ROM invalid, external 16-bit space Mode 2 (MCU mode 2) 0 1 0 On-chip ROM valid Mode 7 (PROM mode) 1 1 1 — 0: Low 1: High When the SH7021 is set to PROM mode, the PROM version can write programs exactly like ordinary EPROM using a general purpose EPROM writer. 16.2 PROM Mode 16.2.1 Setting the PROM Mode To program the on-chip PROM, set the pins as shown in figure 16.2 and use the chip in PROM mode. 16.2.2 Socket Adapter Pin Correspondence and Memory Map Mount the socket adapter to the SH7021 as shown in figure 16.2. This allows the on-chip PROM to be programmed in exactly the same way as ordinary 32-pin EPROMs (HN27C101). Figure 16.2 shows the correspondence of SH7021 pins and HN27C101 pins. Figure 16.3 shows the memory map of the on-chip ROM. The address range of the HN27C101 (128 kbytes) is H'00000–H'1FFFF. The on-chip PROM (34 kbytes) is not found in H'08000–H'1FFFF. When programming with a PROM writer, the program address range must be set to H'00000– H'07FFF. The data for the H'08000–H'1FFFF address area should all be H'FF. Set byte mode, not page mode. RENESAS 421 SH7021 Pin Name Pin Number 76 RES 74 NMI 1 AD0 2 AD1 3 AD2 5 AD3 6 AD4 7 AD5 8 AD6 9 AD7 20 A0/HBS 21 A1 22 A2 23 A3 25 A4 26 A5 27 A6 28 A7 29 A8 30 A9 31 A10 33 A11 34 A12 35 A13 36 A14 37 A15 39 A16 53 PA2/CS6/TIOCB0 54 PA3/CS7/WAIT 40 A17 42 A18 VCC 13, 38, 63, 73, 80, 88 77 MD0 78 MD1 79 MD2 4, 15, 24, 32, 41, VSS 50, 59, 70, 81, 82,92 Pin other than the above NC (release) EPROM Socket HN27C101 Adapter Pin Name Pin Number VPP 1 A9 26 I/O0 13 I/O1 14 I/O2 15 I/O3 17 I/O4 18 I/O5 19 I/O6 20 I/O7 21 A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 6 A7 5 A8 27 24 OE A10 23 A11 25 A12 4 A13 28 A14 29 A15 3 A16 2 31 PGM 22 CE VCC 32 VSS 16 • VPP: PROM program power adapter • A16–A0: Address input • I/O7–I/O0: Data input/ output • OE: Output enable • PGM: Program enable • CE: Chip enable Figure 16.2 Correspondence Between SH7021 Pins and HN27C101 Pins 422 RENESAS Addresses in MCU modes 0, 1, and 2* Addresses in PROM mode H'0000000 H'0000 On-chip ROM space (area 0) H'0007FFF H'7FFF Note: Addresses in the figure are the uppermost shadow addresses of the on-chip ROM space. Figure 16.3 Memory Map of On-chip ROM 16.3 PROM Programming The write/verify specifications in PROM mode are the same as for the standard EPROM HN27C101. The page program system is not supported, so do not set the PROM writer to the page programming mode. Naturally, PROM writers that only support the page programming mode cannot be used. When selecting a PROM writer, check that the high-speed, high-reliability programming system for each byte is supported. 16.3.1 Selecting the Programming Mode There are two on-chip PROM programming modes: write and verify (which reads and confirms the data written). Use the pins to select the modes (table 16.2). RENESAS 423 Table 16.2 Select PROM Programming Mode Pin Mode CE OE PGM VPP VCC I/O7–I/O0 A16–A0 Write 0 1 0 VPP VCC Data input Address input Verify 0 0 1 Data output Program inhibit 0 0 0 High impedance 0 1 1 1 0 0 1 1 1 Symbols: 0: Low 1: High VPP: VPP level VCC: VCC level 16.3.2 Write/Verify and Electrical Characteristics Write/Verify: Write/verify can be accomplished by an efficient high-speed high-reliability programming system. This system can write data quickly and accurately without placing voltage stress on the device. The basic flowchart for this high-speed, high-reliability programming system is shown in figure 16.4. 424 RENESAS Start Set EPROM writer to write/verify mode (VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V) Address = 0 n=0 n+1→n No Yes Data write (tPW = 0.2 ms ± 5%) n = 25? No Address + 1 → Address Verify result OK? Yes Data write (tOPW = (0.2 × n) ms) Final address? No Yes Set EPROM writer to read mode (VCC = 5.0 V ± 0.25 V, VPP = VCC) No good VCC: VPP: tPW: tOPW: Power supply PROM program power supply Initial programming pulse width Over programming pulse width No Results of reading all address OK? Yes End Figure 16.4 Basic Flowchart of High-Speed High-Reliability Programming RENESAS 425 Electrical Characteristics: Tables 16.3 and 16.4 show the electrical characteristics of programming. Figure 16.5 shows the timing. Table 16.3 DC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V, Ta = 25 ± 5˚C) Pins Symbol Min Typ Max Input high voltage I/O7–I/O0, A16–A0, OE, CE, PGM VIH 2.4 — VCC + 0.3 V Input low voltage I/O7–I/O0, A16–A0, OE, CE, PGM VIL –0.3 — 0.8 V Output high voltage I/O7–I/O0 VOH 2.4 — — V I OH = -200 µA Output low voltage I/O7–I/O0 VOL — — 0.45 V I OL = 1.6 mA Input leak current I/O7–I/O0, A16–A0, OE, CE, PGM |ILI| — — 2 µA VIN = 5.25 V/0.5 V VCC current I CC — — 40 mA VPP current I PP — — 40 mA 426 RENESAS Unit Measurement Conditions Item Table 16.4 AC Characteristics (VCC = 6.0 V ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V, Ta = 25 ± 5˚C) Item Symbol Min Typ Max Unit Measurement Conditions Address setup time t AS 2 — — µs Figure 16.5*1 OE setup time t OES 2 — — µs Data setup time t DS 2 — — µs Address hold time t AH 0 — — µs Data hold time t DH 2 — — µs — — 130 ns 2 — — µs 0.19 0.20 0.21 ms 0.19 — 5.25 ms *2 Data output disable time t DF VPP setup time t VPS PGM pulse width in initial programming t PW *3 PGM pulse width in over programming t OPW VCC setup time t VCS 2 — — µs CE setup time t CES 2 — — µs Data output delay time t OE 0 — 150 ns Notes: 1. Input pulse level: 0.45–2.4 V Input rise, fall time ≤ 20 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V 2. t DF is defined as when output reaches the release state and the output level could not be referenced. 3. t OPW is defined as the value given in the flowchart. RENESAS 427 Write Verify Address tAS tAH Write data Data VCC tDF tDH tDS VPP Read data VPP VCC tVPS VCC + 1 VCC tVCS CE tCES PGM tPW tOES tOE (tOPW) OE Note: t OPW is defined as the value given in the flowchart. Figure 16.5 Write/Verify Timing 16.3.3 Points to Note About Writing 1. Always write using the prescribed voltage and timing. The write voltage (programming voltage) VPP is 12.5 V (when the EPROM writer is set to the Hitachi specifications for HN27C101, VPP becomes 12.5 V.) Applying a voltage in excess of the rated voltage may damage the device. Pay particular attention to overshooting in the EPROM writer. 2. Before programming, always check that the indexes of the EPROM writer socket, socket adapter, and devices are consistent with each other. If they are not mounted in the proper location, an overcurrent may be generated, damaging the device. 3. Do not touch the socket adapter or device during writing. Contact can cause malfunctions that prevent data from being written accurately. 428 RENESAS 4. You cannot write in the page programming mode. Always set the equipment to the byte programming mode. 5. The capacity of the on-chip ROM is 32 kbytes, so the data of PROM writer addresses H'08000–H'1FFFF should be H'FF. Always set the range for PROM addresses to H'0000– H'7FFF. 6. When write errors occur on consecutive addresses, stop writing. Check to see if there are any abnormalities in the EPROM writer and socket adapter. 16.3.4 Reliability After Writing After programming, we recommend letting the device stand at high temperature (125–150°C) for 24–48 hours to increase the reliability of data retention. Letting it stand at high temperature is a type of screening method that can get rid of initial data retention defects of the on-chip PROM's memory cell within a short period of time. Figure 16.6 shows the flow from programming of the on-chip PROM, including screening, to mounting on the device board. Writing and verification of program Flow chart from figure 16.4 Let stand in nonconductive, high temperature environment (125–150°C, 24–48 hours) Data read and verification (VCC = 5.0 V) Mount on board Figure 16.6 Screening Flow If abnormalities are found when the program is written and verified or the program is read and checked after the writing/verification or letting the chip stand at high temperature, contact Hitachi's engineering departments. RENESAS 429 Section 17 RAM 17.1 Overview The SH7020 and SH7021 has 1-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 17.1). The CPU can access data in the on-chip RAM in byte, word, or long word units. The DMAC can access byte or word data. On-chip RAM data can always be accessed in one state, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the on-chip RAM are held in both the sleep and standby modes. Memory area 7 addresses H'FFFFC00 to H'FFFFFFF are allocated to the on-chip RAM. Internal data bus (32 bits) H'FFFFC00 H'FFFFC01 H'FFFFC02 H'FFFFC03 H'FFFFC04 H'FFFFC05 H'FFFFC06 H'FFFFC07 On-chip RAM H'FFFFFFC H'FFFFFFD H'FFFFFFE H'FFFFFF Figure 17.1 Block Diagram of RAM 17.2 Operation Accesses to addresses H'FFFFC00–H'FFFFFFF are directed to the on-chip RAM. Memory area 7 (H'F000000–H'FFFFFFF) is divided into shadows in 1 kbyte units. All shadow accesses are onchip RAM accesses. For more information on shadows, see section 8, Bus State Controller. RENESAS 431 Section 18 Power-Down States 18.1 Overview In the power-down mode, all CPU functions are halted. This lowers power consumption dramatically. 18.1.1 Power-Down Modes The SH microprocessor has two power-down modes. 1. Sleep mode 2. Standby mode The sleep mode and standby mode are entered from the program execution state according to the transition conditions given in table 18.1. Table 18.1 also describes procedures for canceling each mode and the states of the CPU and peripheral functions. Table 18.1 Power-Down States State Mode Entering Procedure Clock CPU Peripheral Functions CPU Registers RAM I/O Ports Canceling Procedure Sleep mode Execute SLEEP instruction with SBY bit set to 0 in SBYCR Run Halt Run Held Held Held • Interrupt • DMA address error • Power-on reset • Manual reset Standb y mode Execute SLEEP instruction with SBY bit set to 1 in SBYCR Halt Halt Halt*1 Held Held Held or high-Z*2 • NMI • Power-on reset • Manual reset SBYCR: Standby control register SBY: Standby bit Notes: 1. Some of the registers of the on-chip peripheral modules are not initialized in the standby mode. For details, see table 18.3, Status of Registers in the Standby Mode in section 18.4.1, Transition to the Standby Mode, or the descriptions of registers given where the on-chip peripheral modules are covered. 2. The status of I/O ports in the standby mode are set by the port high-impedance bit (HIZ) of the SBYCR. See section 18.2, Standby Control Register (SBYCR) for details. The status of pins other than the I/O ports are described in appendix B, Pin States. RENESAS 433 18.1.2 Register Table 18.2 summarizes the register related to the power-down state. Table 18.2 Standby Control Register (SBYCR) Name Abbreviation R/W Initial Value Address Access size Standby control register SBYCR R/W H'1F H'5FFFFBC 8, 16, 32 18.2 Standby Control Register (SBYCR) The standby control register (SBYCR) is an 8-bit register that can be read or written to. It is set in order to enter the standby mode and also sets the port states in standby mode. The SBYCR is initialized to H'1F when reset. Bit: Bit name: Initial value: R/W: • 7 6 5 4 3 2 1 0 SBY HIZ — — — — — — 0 0 0 1 1 1 1 1 R/W R/W — — — — — — Bit 7 (standby (SBY)): SBY enables transition to the standby mode. The SBY bit cannot be set to 1 while the timer enable bit (bit TME) in timer control/status register TCSR of watchdog timer WDT is set to 1. To enter the standby mode, clear the TME bit to 0 to halt the WDT and set the SBY bit. SBY Description 0 Executing SLEEP instruction puts the LSI into sleep mode (initial value) 1 Executing SLEEP instruction puts the LSI into standby mode • Bit 6 (port high-impedance (HIZ)): HIZ selects whether I/O ports remain in their previous states during standby, or are placed in the high-impedance state when the standby mode is entered. The HIZ bit cannot be set to 1 while the TME bit is set to 1. To place the pins of the I/O ports in high impedance, clear the TME bit to 0 before setting the HIZ bit. HIZ Description 0 Port states are maintained during standby (initial value) 1 Ports are placed in the high-impedance state in standby RENESAS 434 • Bits 5–0 (reserved): Bit 5 is a read-only bit that always reads as 0. Only write 0 to bit 5. Writing to bits 4–0 is disabled. These bits always read 1. 18.3 Sleep Mode 18.3.1 Transition to the Sleep Mode Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register (SBYCR) is cleared to 0 causes a transition from the program execution state to the sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules do not halt in the sleep mode. 18.3.2 Canceling the Sleep Mode The sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset. Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt exception processing is executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU’s status register (SR). Likewise, the sleep mode is not canceled if the interrupt is disabled by the on-chip peripheral module. Cancellation by a DMA Address Error: If the DMAC operates during the sleep mode and a DMA address error occurs, the sleep mode is canceled and DMA address error exceptionprocessing is executed. Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the sleep mode is canceled and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the LSI for power-on resets, an NMI interrupt will occur whenever the rising edge of the NMI is selected as the valid edge (in NMI edge select bit NMIE of the interrupt control register ICR of the interrupt controller). When this occurs, the NMI interrupt cancels the sleep mode. Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the sleep mode is canceled and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the LSI for manual resets, the sleep mode will be canceled by an NMI interrupt whenever the falling edge of the NMI is selected as the valid edge (in the NMIE bit). RENESAS 435 18.4 Standby Mode 18.4.1 Transition to the Standby Mode To enter the standby mode, set the standby bit (SBY) to 1 in the standby control register (SBYCR), then execute the SLEEP instruction. The LSI moves from the program execution state to the standby mode. The standby mode greatly reduces power consumption by halting not only the CPU, but the clock and on-chip peripheral modules as well. Some registers of the on-chip peripheral modules are initialized, others are not (See table 18.3). As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are held. The I/O port state (hold or high impedance) depends on the port high-impedance bit (HIZ) in the SBYCR. For details on the states of these pins, see appendix B. Pin States. RENESAS 436 Table 18.3 Register States in the Standby Mode Module Register Initialized Registers That Hold Data Interrupt controller (INTC) — All registers User break controller (UBC) — All registers Bus state controller (BSC) — All registers Pin function controller (PFC) — All registers I/O ports — All registers Direct memory access controller (DMAC) All registers — Watchdog timer (WDT) • Bits 7–5 (OVF, WT/IT, TME) of the timer control status register (TCSR) • Bits 2–0 (CKS2–CKS0) of the timer control status register (TCSR) • Reset control/status register (RSTCSR) • Timer counter (TCNT) 16-bit integrated timer pulse unit (ITU) All registers — Programmable timing pattern controller (TPC) — All registers Serial communications interface (SCI) • Receive data register (RDR) — • Transmit data register (TDR) • Serial mode register (SMR) • Serial control register (SCR) • Serial status register (SSR) • Bit rate register (BBR) Power-down state register — Standby control register (SBYCR) RENESAS 437 18.4.2 Canceling the Standby Mode The standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset. Cancellation by an NMI: When a rising edge or falling edge (as selected by the NMIE bit in interrupt control register ICR of interrupt controller INTC) is detected at the NMI pin, the clock oscillator begins operating. At first, clock pulses are supplied only to the watchdog timer. After the time that was selected before entering the standby mode using clock select bits 2–0 (CKS2–CKS0) in the timer control/status register TCSR of the watchdog timer WDT, the watchdog timer overflows. After the overflow, the clock is considered stable and supplied to the entire chip. The standby mode is canceled and the NMI exception-processing sequence begins. When the standby mode is cleared by an NMI interrupt, bits CKS2–CKS0 must be set so that the WDT overflow interval is equal to or greater than the clock settling time. When the standby mode is cleared when the fall edge has been selected in the NMI bit, be sure that the NMI pin is high when standby is entered (when the clock is halted) and low when the chip returns from standby (clock starts up after oscillator is stabilized). Likewise, when the standby mode is cleared when the rise edge has been selected in the NMI bit, be sure that the NMI pin is low when standby is entered (clock halted) and high when the chip returns from standby (clock starts up after oscillator is stabilized). Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the standby mode is canceled and the power-on reset state is entered. If the NMI signal is brought from low to high in order to set the LSI for power-on resets, the standby mode will not be canceled by an NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode (by the NMIE bit). Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the standby mode is canceled and the manual reset state is entered. If the NMI signal is brought from high to low in order to set the LSI for manual resets, the standby mode will first be canceled by an NMI interrupt, because the NMI signal is initialized for the falling edge in the standby mode (by the NMIE bit). RENESAS 438 18.4.3 Standby Mode Application In this example, the standby mode is entered on the falling edge of the NMI signal and canceled on the rising edge of the NMI signal. Figure 18.1 shows the timing. After an NMI interrupt is accepted (high goes to low) while the NMI edge select bit NMIE in the interrupt control register ICR is cleared to 0 to select detection of the falling edge, the NMI exception service routine sets the NMIE to 1 (selecting detection of the rising edge) and sets the SBY bit to 1. Finally, it executes a SLEEP instruction to enter the standby mode. The standby mode is canceled on the rising edge of the NMI signal. Oscillator CK NMI NMIE SSBY Clock setting time NMI Exception exception service processing routine SBY = 1 SLEEP instruction Standby Oscillation mode start time Time set in WDT NMI exception processing Figure 18.1 NMI Timing for the Standby Mode (Example) RENESAS 439 Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings Table 19.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage VCC –0.3 to +7.0 V Program voltage VPP –0.3 to +13.5 V Input voltage Vin –0.3 to VCC + 0.3 V Operating temperature Topr –20 to +75* ˚C Storage temperature Tstg –55 to +125 ˚C Caution: Operating the LSI in excess of the absolute maximum rating may result in permanent damage. Note: Normal Products: Topr = –40 to +85°C for wide-temperature range products RENESAS 441 19.2 DC Characteristics Table 19.2 lists DC characteristics. Table 19.3 lists the permissible output current values. Usage Conditions: • The current consumption value is measured under conditions of V IH min = VCC – 0.5 V and VIL max = 0.5 V with no load on any output pin and the on-chip pull-up MOS off. Table 19.2 DC Characteristics (1) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Typ Max Measurement Unit Conditions VCC – 0.7— VCC + 0.3 V EXTAL VCC × 0.7— VCC + 0.3 V Other input pins 2.2 — VCC + 0.3 V –0.3 — 0.5 V –0.3 — 0.8 V VT+ 4.0 — — V VT– — Input high- RES, NMI, MD2–MD0 level voltage Input low- RES, NMI, MD2–MD0 level voltage Other input pins Schmidt trigger input voltage PA13–PA10, PA2, PA0, PB7– PB0 Input leak current RES 3-state leak current (while off) Ports A and B, CS3–CS0, A21– A0, AD15–AD0 Input pullup MOS current Output high-level voltage VIH VIL — 1.0 V VT+–VT– 0.4 — — V |Iin| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V — — 1.0 µA Vin = 0.5 to VCC – 0.5 V |ITSI| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V PA3 –Ip 20 — 300 µA Vin = 0V All output pins VOH VCC – 0.5— — V I OH = –200 µA 3.5 — V I OH = –1 mA NMI, MD2–MD0 RENESAS 442 — Table 19.2 DC Characteristics (1) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products . Item Symbol Min Typ Max — — 0.4 V I OL = 1.6 mA — — 1.2 V I OL = 8 mA — — 30 pF NMI — — 30 pF All other input pins — — 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25°C — 65 80 mA f = 12.5 MHz — 75 90 mA f = 16.6 MHz — 90 100 mA f = 20 MHz — 30 50 mA f = 12.5 MHz — 35 55 mA f = 16.6 MHz — 40 60 mA f = 20 MHz — 0.01 5 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta 2.0 — — V Output low level voltage All output pins Input capacitance RES Current consumption Ordinary operation VOL Cin I CC Sleep Standby RAM stand-by Measurement Unit Conditions voltage VRAM Usage Notes: 1. Current dissipation values are for VIH min = VCC - 0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 5. The ZTAT and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. Caution is therefore required in carrying out system design, and when switching between ZTAT and mask versions. RENESAS 443 Table 19.2 DC Characteristics (2) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Measurement Unit Conditions VCC – 0.7 — VCC + 0.3 V EXTAL VCC × 0.7 — VCC + 0.3 V Other input pins 2.2 — VCC + 0.3 V –0.3 — 0.5 V –0.3 — 0.8 V Input high- RES, NMI, MD2–MD0 level voltage Input lowlevel voltage Typ Max RES, NMI, MD2–MD0 VIH VIL Other input pins Schmidt trigger input voltage PA13–10, PA2, PA0, PB7–PB0 Input leak current RES + VT 4.0 — — V VT– — — 1 V VT+–VT– 0.4 — — V |Iin| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V — — 1.0 µA Vin = 0.5 to VCC – 0.5 V NMI, MD2–MD0 3-state leak Ports A and B, current (while CS3–CS0, A21– off) A0, AD15–AD0 |ITSI| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Input pull-up PA3 MOS current –Ip 20 — 300 µA Vin = 0 V Output highlevel voltage All output pins VOH VCC – 0.5 — — V I OH = –200 µA 3.5 — — V I OH = –1 mA Output low level voltage All output pins — — 0.4 V I OL = 1.6 mA — — 1.2 V I OL = 8 mA RENESAS 444 VOL Table 19.2 DC Characteristics (2) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products . Item Input capacitance Current consumption Min Typ Max Unit Cin — — 30 pF NMI — — 30 pF All other input pins — — 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25°C — 65 80 mA f = 12.5 MHz — 75 90 mA f = 16.6 MHz — 30 50 mA f = 12.5 MHz — 35 55 mA f = 16.6 MHz — 0.01 5 µA Ta ≤ 50°C — — 20.0 µA 50°C < Ta 2.0 — — V RES Ordinary operation I CC Sleep Standby RAM stand-by Measurement Conditions Symbol voltage VRAM RENESAS 445 Table 19.2 DC Characteristics (3) Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Typ Max Measurement Unit Conditions VCC × 0.9 — VCC + 0.3 V EXTAL VCC × 0.7 — VCC + 0.3 V Other input pins VCC × 0.7 — VCC + 0.3 V –0.3 — VCC × 0.1 V –0.3 — VCC × 0.2 V VT VCC × 0.9 — — V VT– — — VCC × 0.2 V VT+–VT– VCC × 0.07 — — V |Iin| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Item Input highlevel voltage Input lowlevel voltage Symbol Min RES, NMI, MD2–MD0 RES, NMI, MD2–MD0 VIH VIL Other input pins Schmidt trigger PA13–10, PA2, input PA0, PB7–PB0 voltage Input leak current RES + NMI, MD2–MD0 3-state leak Ports A and B, current (while CS3–CS0, A21– off) A0, AD15–AD0 |ITSI| — — 1.0 µA Vin = 0.5 to VCC – 0.5 V Input pull-up MOS current PA3 –Ip 20 — 300 µA Vin = 0V Output highlevel voltage All output pins VOH VCC – 0.5 — — V I OH = –200 µA VCC – 1.0 — — V I OH = –1 mA Output low level voltage All output pins — — 0.4 V I OL = 1.6 mA — — 1.2 V I OL = 8 mA RENESAS 446 VOL Table 19.2 DC Characteristics (3) (cont) Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products . Item Input capacitance Current consumption Measurement Conditions Symbol Min Typ Max Unit Cin — — 30 pF NMI — — 30 pF All other input pins — — 20 pF Vin = 0 V Input signal f = 1 MHz Ta = 25°C — 65 80 mA f = 12.5 MHz Sleep — 30 50 mA f = 12.5 MHz Standby — 0.01 5.0 µA Ta ≤ 50°C — — 20 µA 50°C < Ta 2.0 — — V RES Ordinary operation RAM stand-by voltage I CC VRAM RENESAS 447 Table 19.3 Permitted Output Current Values Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* Case C: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. 12.5 MHz Item Symbol Min Typ Max Unit Output low-level permissible current (per pin) I OL — — 10 mA Output low-level permissible current (total) ∑ IOL — — 80 mA Output high-level permissible current (per pin) –I OH — — 2.0 mA Output high-level permissible current (total) –∑ IOH — — 25 mA Caution: To ensure LSI reliability, do not exceed the value for output current given in table 19.3. RENESAS 448 19.3 AC Characteristics The following AC timing chart represents the AC characteristics, not signal functions. For signal functions, see the explanation in the text. 19.3.1 Clock Timing Table 19.4 Clock Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Case A Case B Sym- 12.5 MHz bol Min Max Min Max Min Max Unit Figures EXTAL input high level pulse width t EXH 20 — 10 — 10 — ns 19.1 EXTAL input low level pulse width t EXL 20 — 10 — 10 — ns EXTAL input rise time t EXr — 10 — 5 — 5 ns EXTAL input fall time t EXf — 10 — 5 — 5 ns Clock cycle time t cyc 80 — 60 500 50 500 ns 19.1, 19.2 Clock high pulse width t CH 30 — 20 — 20 — ns 19.2 Clock low pulse width t CL 30 — 20 — 20 — ns Clock rise time t Cr — 10 — 5 — 5 ns Clock fall time t Cf — 10 — 5 — 5 ns Reset oscillation settling time t OSC1 10 — 10 — 10 — ms Software standby oscillation settling time t OSC2 10 — 10 — 10 — ms Item 16.6 MHz 20 MHz 19.3 RENESAS 449 tcyc tEXH 1/2 VCC EXTAL tEXL VIH VIL tEXr tEXf Figure 19.1 EXTAL Input Timing tCYC tCH tCL CK tCf tCr Figure 19.2 System Clock Timing CK VCC tOSC2 tOSC1 RES Figure 19.3 Oscillation Settling Time RENESAS 450 19.3.2 Control Signal Timing Table 19.5 Control Signal Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Case A 12.5 MHz Case B 16.6 MHz 20 MHz Item Symbol Min Max Min Max Min Max Unit Figure RES setup time t RESS 320 — 240 — 200 — ns 19.4 RES pulse width t RESW 20 — 20 — 20 — t cyc NMI reset setup time t NMIRS 320 — 240 — 200 — ns NMI reset hold time t NMIRH 320 — 240 — 200 — ns NMI setup time t NMIS 160 — 120 — 100 — ns NMI hold time t NMIH 80 — 60 — 50 — ns IRQ0–IRQ7 setup time (edge detection time) t IRQES 160 — 120 — 100 — ns IRQ0–IRQ7 setup time (level detection time) t IRQLS 160 — 120 — 100 — ns IRQ0–IRQ7 hold time t IRQEH 80 — 60 — 50 — ns IRQOUT output delay time) t IRQOD — 80 — 60 — 50 ns 19.6 Bus request setup time t BRQS 80 — 60 — 50 — ns 19.7 Bus acknowledge delay time 1 t BACD1 — 80 — 60 — 50 ns Bus acknowledge delay time 2 t BACD2 — 80 — 60 — 50 ns Bus 3-state delay time t BZD — 80 — 60 — 50 ns 19.5 RENESAS 451 CK tRESS tRESS RES tNMIRS tRESW tNMIRH NMI Figure 19.4 Reset Input Timing CK tNMIS tNMIH tIRQES tIRQEH NMI IRQ edge tIRQLS IRQ level Figure 19.5 Interrupt Signal Input Timing RENESAS 452 CK tIRQOD tIRQOD IRQOUT Figure 19.6 Interrupt Signal Output Timing CK tBRQS BREQ (Input) tBRQS tBACD1 tBACD2 BACK (Output) tBZD RD, WR, RAS, CAS, CSn tBZD A21–A0 Figure 19.7 Bus Release Timing RENESAS 453 19.3.3 Bus Timing Table 19.6 Bus Timing (1) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. RENESAS 454 Item Symbol Min Max Unit Figures ns 19.8, 19.9, 19.11–19.14, 19.19, 19.20 19.8, 19.9, 19.20 Address delay time t AD — 20*1 CS delay time 1 t CSD1 — 25 ns CS delay time 2 t CSD2 — 25 ns CS delay time 3 t CSD3 — 20 ns CS delay time 4 t CSD4 — 20 ns t RDAC1 t cyc × 0.65 – 20 — ns t cyc × 0.5 – 20 — ns t cyc × (n+1.65) – 20 *3 — ns t cyc × (n+1.5) – — – 20 *3 ns t cyc × (n+0.65) – 20 *3 — ns t cyc × (n+0.5) – — – 20 *3 ns 1*6 Access time 35% duty *2 from read strobe 50% duty 2*6 Access time 35% from read strobe duty *2 t RDAC2 50% duty Access time 3*6 35% duty *2 from read strobe t RDAC3 50% duty 19.19 19.8 19.9, 19.10 19.19 Read strobe delay time t RSD — 20 ns 19.8, 19.9, 19.11–19.15, 19.19, 19.24–19.28 19.8, 19.9, 19.11–19.14, 19.19 Read data setup time t RDS 15 — ns Read data hold time t RDH 0 — ns Write strobe delay time 1 t WSD1 — 20 ns 19.9, 19.13, 19.14, 19.19, 19.20 Write strobe delay time 2 t WSD2 — 20 ns 19.9, 19.13, 19.14, 19.19 Write strobe delay time 3 t WSD3 — 20 ns 19.11, 19.12 Write strobe delay time 4 t WSD4 — 20 ns 19.11, 19.12, 19.20 Write data delay time 1 t WDD1 — 35 ns 19.9, 19.13, 19.14, 19 Write data delay time 2 t WDD2 — 20 ns 19.11, 19.12 Write data hold time t WDH 0 — ns 19.9, 19.11–19.14 RENESAS 455 Table 19.6 Bus Timing (1) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures Parity output delay time 1 t WPDD1 — 40 ns 19.9, 19.13, 19.14 Parity output delay time 2 t WPDD2 — 20 ns 19.11, 19.12 Parity output hold time t WPDH 0 — ns 19.9, 19.11–19.14 Wait setup time t WTS 14 — ns 19.10, 19.15, 19.19 Wait hold time t WTH 10 — ns Read data access time 1*6 t ACC1 t cyc – 30* 4 — ns 19.8, 19.11, 19.12 Read data access time 2*6 t ACC2 t cyc × (n+2) – 30*3 — ns 19.9, 19.10, 19.13, 19.14 RAS delay time 1 t RASD1 — 20 ns RAS delay time 2 t RASD2 — 30 ns 19.11–19.14, 19.16–19.18 CAS delay time 1 t CASD1 — 20 ns 19.11 CAS delay time 2 t CASD2 — 20 ns CAS delay time 3 t CASD3 — 20 ns 19.13, 19.14, 19.16–19.18 t ASC 0 — ns 19.11, 19.12 t CAC1 t cyc × 0.65 – 19 — ns t cyc × 0.5 – 19 — ns Column address setup time Read data access time from CAS 1 *6 35% duty *2 50% duty Read data access time from CAS 2 *6 t CAC2 t cyc × (n+1) – 25*3 — ns 19.13, 19.14, 19.15 Read data access time from RAS 1 *6 t RAC1 t cyc × 1.5 – 20 — ns 19.11, 19.12 Read data access time from RAS 2 *6 t RAC2 t cyc × (n+2.5) – — 20*3 ns 19.13, 19.14, 19.15 High-speed page mode CAS precharge time t CP t cyc × 0.25 ns 19.12 RENESAS 456 — Table 19.6 Bus Timing (1) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures AH delay time 1 t AHD1 — 20 ns AH delay time 2 t AHD2 — 20 ns Multiplexed address delay time t MAD — 30 ns Multiplexed address hold time t MAH 0 — ns DACK0, DACK1 delay time 1 t DACD1 — 23 ns DACK0, DACK1 delay time 2 t DACD2 — 23 ns DACK0, DACK1 delay time 3 t DACD3 — 20 ns 19.9, 19.13, 19.14, 19.19 DACK0, DACK1 delay time 4 t DACD4 — 20 ns 19.11, 19.12 DACK0, DACK1 delay time 5 t DACD5 — 20 ns t RDD — t cyc × 0.35 + 12 ns — t cyc × 0.5 + 15 ns Read delay time 35% duty *2 50% duty 19.19 19.8, 19.9, 19.11– 19.14, 19.19, 19.20 19.8, 19.9, 19.1119.15, 19.19, 19.2419.28 Data setup time for CAS t DS 0*5 — ns 19.11, 19.13 CAS setup time for RAS t CSR 10 — ns 19.16, 19.17, 19.18 Row address hold time t RAH 10 — ns 19.11, 19.13 Write command hold time t WCH 15 — ns t WCS 0 — ns 0 — ns t cyc — − 20 ns Write command setup time 35% duty *2 50% duty Access time from CAS precharge *6 Notes: 1. 2. 3. 4. 5. 6. t ACP 19.11 19.12 HBS and LBS signals are 25 ns. When frequency is 10 MHz or more. n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25. –5 ns for parity output of DRAM long-pitch access. It is not necessary to meet the tRDS specification as long as the access time specification is met. RENESAS 457 Table 19.7 Bus Timing (2) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures ns 19.8, 19.9, 19.11–19.14, 19.19, 19.20 19.8, 19.9, 19.20 Address delay time t AD — 25*1 CS delay time 1 t CSD1 — 30 ns CS delay time 2 t CSD2 — 25 ns CS delay time 3 t CSD3 — 25 ns CS delay time 4 t CSD4 — 25 ns Access time 1*6 35% duty *2 from read strobe t RDAC1 t cyc × 0.65 – — 20 ns t cyc × 0.5 – 20 — ns t cyc × (n + 1.65) – 20 *3 — ns t cyc × (n + 1.5) – 20 *3 — ns t cyc × (n + 0.65) – 20 *3 — ns t cyc × (n + 0.5) – 20 *3 — ns t RSD — 25 ns 19.8, 19.9, 19.19 Read data setup time t RDS 15 — ns 19.8, 19.9, 19.11–19.14, Read data hold time t RDH 0 — ns 19.19 Write strobe delay time 1 t WSD1 — 25 ns 19.9, 19.13, 19.14, 19.19, 19.20 Write strobe delay time 2 t WSD2 — 25 ns 19.9, 19.13, 19.14, 19.19 Write strobe delay time 3 t WSD3 — 25 ns 19.11, 19.12 Write strobe delay time 4 t WSD4 — 25 ns 19.11, 19.12, 19.20 Write data delay time 1 t WDD1 — 45 ns 19.9, 19.13, 19.14, 19.19 Write data delay time 2 t WDD2 — 25 ns 19.11, 19.12 Write data hold time t WDH 0 — ns 19.9, 19.11–19.14 Parity output delay time 1 t WPDD1 — 45 ns 19.9, 19.13, 19.14 Parity output delay time 2 t WPDD2 — 25 ns 19.11, 19.12 Parity output hold time t WPDH 0 — ns 19.9, 19.11–19.14 50% duty Access time 2*6 35% duty *2 from read strobe t RDAC2 50% duty Access time 3*6 35% duty *1 from read strobe t RDAC3 50% duty Read strobe delay time RENESAS 458 19.19 19.8 19.9, 19.10 19.19 Table 19.7 Bus Timing (2) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures Wait setup time t WTS 19 — ns Wait hold time t WTH 10 — ns Read data access time 1*6 t ACC1 t cyc – 30* 4 — ns 19.8, 19.11, 19.12 Read data access time 2*6 t ACC2 t cyc × (n+2) – 30*3 — ns 19.9, 19.10, 19.13, 19.14 RAS delay time 1 t RASD1 — 25 ns RAS delay time 2 t RASD2 — 35 ns 19.11–19.14, 19.16–19.18 CAS delay time 1 t CASD1 — 25 ns 19.11 CAS delay time 2 t CASD2 — 25 ns CAS delay time 3 t CASD3 — 25 ns 19.13, 19.14, 19.16–19.18 t ASC 0 — ns 19.11, 19.12 t CAC1 t cyc × 0.65 – 19 — ns t cyc × 0.5 – 19 — ns Column address setup time Read data access 35% time from CAS 1*6 duty *2 50% duty 19.10, 19.15, 19.19 Read data access time from CAS 2 *6 t CAC2 t cyc × (n + 1) – — 25*3 ns 19.13, 19.14, 19.15 Read data access time from RAS 1 *6 t RAC1 t cyc × 1.5 – 20 — ns 19.11, 19.12 Read data access time from RAS 2 *6 t RAC2 t cyc × (n + 2.5) — – 20 *3 ns 19.13, 19.14, 19.15 High-speed page mode CAS precharge time t CP t cyc × 0.25 — ns 19.12 AH delay time 1 t AHD1 — 25 ns 19.19 AH delay time 2 t AHD2 — 25 ns Multiplexed address delay time t MAD — 30 ns Multiplexed address hold time t MAH 0 — ns RENESAS 459 Table 19.7 Bus Timing (2) (cont) Conditions: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures DACK0, DACK1 delay time 1 t DACD1 — 25 ns DACK0, DACK1 delay time 2 t DACD2 — 25 ns DACK0, DACK1 delay time 3 t DACD3 — 25 ns 19.9, 19.13, 19.14, 19.19 DACK0, DACK1 delay time 4 t DACD4 — 25 ns 19.11, 19.12 DACK0, DACK1 delay time 5 t DACD5 — 25 ns t RDD — t cyc × 0.35 + 12 ns — t cyc × 0.5 + 15 ns 19.8, 19.9, 19.11-19.15, 19.19 — ns 19.11, 19.13 Read delay time 35% duty *2 50% duty 19.8, 19.9, 19.11–19.14, 19.19, 19.20 Data setup time for CAS t DS 0*5 CAS setup time for RAS t CSR 10 — ns 19.16, 19.17, 19.18 Row address hold time t RAH 10 — ns 19.11, 19.13 t WCH 15 — ns Write command 35% setup time 50% duty t WCS 0 — ns 0 — ns Access time from CAS precharge *6 t ACP t cyc — −20 ns Write command hold time duty *2 Notes 1. 2. 3. 4. 5. 6. 19.11 19.12 HBS and LBS signals are 30 ns. When frequency is 10 MHz or more n is the number of wait cycles. Access time from addresses A0 to A21 is tcyc-25. –5 ns for parity output of DRAM long-pitch access It is not necessary to meet the tRDS specification as long as the access time specification is met. RENESAS 460 T1 CK tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC1*1 tRSD RD (Read) tACC1*2 tRDS AD15–AD0 DPH, DPL (Read) tDACD1 tRDH*3 tDACD2 DACK0 DACK1 Notes: 1. 2. 3. For t RDAC1 , use t cyc × 0.65 – 20 (for 35% duty) or t cyc × 0.5 – 20 (for 50% duty) instead of tcyc – t RDD – t RDS. For tACC1, use t cyc – 30 instead of t cyc – t AD (or tCSD1) – tRDS. t RDH is measured from A21–A0, CSn, or RD, whichever is negated first. Figure 19.8 Basic Bus Cycle: One-State Access RENESAS 461 T1 CK T2 tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC2*1 tRSD RD (Read) tACC2*2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tDACD1 tWSD1 tRDH*3 tRDS tDACD2 tWSD2 WRH, WRL, WR (Write) tWDH tWDD1 AD15–AD0 (Write) tWPDH tWPDD1 DPH, DPL (Write) tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1 2 3 For tRDAC2, use t cyc × (n + 1.65) – 20 (for 35% duty) or tcyc × (n + 1.5) – 20 (for 50% duty) instead of tcyc × (n + 2) – tRDD – tRDS. For tACC2, use t cyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD (or tCSD1) – tRDS. t RDH is measured from A21–A0, CSn, or RD, whichever is negated first. Figure 19.9 Basic Bus Cycle: Two-State Access RENESAS 462 T1 TW T2 CK A21–A0 HBS, LBS CSn tRDAC2*1 RD (Read) tACC2*2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15–AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. 2. For tRDAC2, use t cyc × (n + 1.65) – 20 (for 35% duty) or tcyc × (n + 1.5) – 20 (for 50% duty) instead of tcyc × (n + 2) – tRDD – tRDS. For tACC2, use t cyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD (or tCSD1) – tRDS. Figure 19.10 Basic Bus Cycle: Two States + Wait State RENESAS 463 Tp Tr Tc CK tAD tAD Row A21–A0 Column tRASD1 tRASD2 tRAH RAS tDS tASC tRDD CAS tRSD tWCH RD(Read) WRH, WRL, (Read) tDACD1 DACK0 DACK1 (Read) tCASD1 tDACD2 tCAC1*1 tACC1*2 AD15–AD0 DPH, DPL (Read) tRAC1*3 tWSD3 RD(Write) WRH, WRL, (Write) tWCS tWDD2 AD15–AD0 (Write) DPH, DPL (Write) tRDS tRDH*4 tWSD4 tWDH tWPDH tWPDD2 tDACD4 tDACD5 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC1, use t cyc × 0.65 – 19 (for 35% duty) or t cyc × 0.5 – 19 (for 50% duty) instead of tcyc – tAD – t ASC – tRDS. For tACC1, use t cyc – 30 instead of tcyc – tAD – t RDS. For tRAC1, use t cyc × 1.5 – 20 instead of t cyc × 1.5 – t RASD1 – tRDS. t RDH is measured from A21–A0, RAS, or CAS, whichever is negated first. Figure 19.11 DRAM Bus Cycle (Short Pitch, Normal Mode) RENESAS 464 Tp Tr Tc Tc Tc Tc CK tAD A21–A0 tAD Row address Column address Column address Column address Column address tRASD2 tRASD1 RAS tASC tCP CAS tRDD tRSD RD(Read) WRH, WRL, WR(Read) tCAC1*1 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) Notes: 1. 2. 3. 4. 5. tRAC1*3 tACC1*2 tACP tRDS tRDH*4 tRDH*5 tDACD1 tDACD2 For tCAC1, use tcyc × 0.65 – 19 (for 35% duty) or t cyc × 0.5 – 19 (for 50% duty) instead of t cyc – t AD – t ASC – tRDS . It is not necessary to meet the tRDS specification as long as the t CAC1 specification is met. For tACC1, use tcyc – 30 instead of t cyc – t AD – t RDS . It is not necessary to meet the tRDS specification as long as the t ACC1 specification is met. For tRAC1, use tcyc × 1.5 – 20 instead of t cyc × 1.5 – t RASD1 – t RDS . It is not necessary to meet the tRDS specification as long as the t RAC1 specification is met. t RDH is measured from A21—A0 or CAS, whichever is negated first. t RDH is measured from A21—A0, RAS, or CAS, whichever is negated first. Figure 19.12 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read) RENESAS 465 Tp Tr Silent cycle Tc Tc CK tAD A21–A0 tAD Row address Column address Column address tRASD2 tRASD1 RAS tASC CAS RD (Write) tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15–AD0 DPH, DPL (Write) DPH, DPL (Write) tDACD4 tDACD5 tDACD5 DACK0 DACK1 (Write) Figure 19.12 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, Burst Operation. RENESAS 466 Tp Tr Tc1 Tc2 CK tAD A21–A0 tRASD1 tAD Row tRAH Column tRASD2 RAS tDS tCASD2 CAS tCASD3 tRDD tRSD RD(Read) WRH, WRL, (Read) AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tWCH tRAC2*3 tACC2*2 tCAC2*1 tRDH*4 tRDS tDACD2 tDACD1 RD(Write) WRH, WRL, (Write) AD15–AD0 (Write) DPH, DPL (Write) tWSD1 tWSD2 tWDH tWDD1 tWPDH tWPDD1 tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC2, use tcyc × (n + 1) – 25 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2 , use t cyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 20 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. t RDH is measured from A21–A0, CAS, or RAS, whichever is negated first. Figure 19.13 DRAM Bus Cycle: (Long Pitch, Normal Mode) RENESAS 467 Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD A21–A0 tAD Row tRASD1 Column Column tRASD2 RAS tCASD2 CAS tRSD WRH, WRL, (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) tCASD3 tRDD RD(Read) AD15–AD0 DPH, DPL (Read) tCASD3 tRAC2*3 tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD1 tDACD2 tWSD1 tWDD1 tWSD2 tRDH*5 tDACD1 tWSD1 tDACD2 tWSD2 tWDH tWDD1 tWDH tWPDH tWPDD1 tWPDH AD15–AD0 (Write) tWPDD1 DPH, DPL (Write) DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. 5. tDACD3 tDACD3 tDACD3 tDACD3 For tCAC2, use t cyc × (n + 1) – 25 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2, use t cyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 20 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. t RDH is measured from A21–A0 or CAS, whichever is negated first. t RDH is measured from A21–A0, RAS, or CAS whichever is negated first. Figure 19.14 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode) RENESAS 468 Tp Tr Tc1 Tw Tc2 CK A21–A0 Row Column tRSD RAS CAS tRDD RD(Read) WRH, WRL, (Read) tCAC2*1 tACC2*2 tRAC2*3 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15–AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. 2. 3. For tCAC2, use t cyc × (n + 1) – 25 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2, use t cyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 20 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. Figure 19.15 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode + Wait State) RENESAS 469 TRp TRr TRc CK tRASD1 tRASD2 RAS tCSR tCASD3 tCASD2 CAS WRH, WRL Figure 19.16 CAS-before-RAS Refresh (Short Pitch) TRp TRr TRc TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL Figure 19.17 CAS-before-RAS Refresh (Long Pitch) RENESAS 470 TRp TRr TRc TRcc CK tRASD1 tRASD2 RAS tCSR tCASD3 tCASD2 CAS Figure 19.18 Self Refresh RENESAS 471 T1 T2 T3 T4 CK tAD A21–A0 HBS, LBS tCSD3 tCSD4 CS6 tAHD1 tAHD2 AH tRDD tRSD RD (Read) tMAD AD15–AD0 (Read) tMAH tRDAC3 Address tRDH Data (input) tDACD1 tDACD2 DACK0 DACK1 (Read) tWSD1 tWSD2 WRH, WRL, WR (Write) tMAD AD15–AD0 (Write) tMAH tWDD1 Data (output) Address tDACD3 DACK0 DACK1 (Write) tWDH tDACD3 tWTH tWTS WAIT Figure 19.19 Address/Data Multiplex I/O Bus Cycle RENESAS 472 T1 CK tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tWSD1 tWSD4 tDACD1 tDACD2 WRH, WRL, WR (Write) DACK0 DACK1 (Write) Figure 19.20 DMA Single Transfer/1 State Access Write RENESAS 473 Table 19.8 Bus Timing (3) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures Address delay time t AD — 40 ns 19.21, 19.22, 19.24– 19.27, 19.32, 19.33 CS delay time 1 t CSD1 — 40 ns 19.21, 19.22, 19.33 CS delay time 2 t CSD2 — 40 ns CS delay time 3 t CSD3 — 40 ns t CSD4 — 40 ns t RDAC1 t cyc × 0.65 – 35 — ns — ns — ns — ns — ns — ns CS delay time 4 1*4 duty *1 2*4 duty *1 Access time 35% from read strobe 50% duty Access time 35% from read strobe 50% duty 3*4 duty *1 t cyc × 0.5 – 35 t RDAC2 t cyc × (n+1.65) – t cyc × (n+1.5) – 35*2 35*2 t cyc × (n+0.65) – 35*2 19.32 19.21, 19.22, 19.23 Access time 35% from read strobe 50% duty t RDAC3 Read strobe delay time t RSD — 40 ns 19.21, 19.22, 19.32 Read data set-up time t RDS 30 — ns 19.21, 19.22, Read data hold time t RDH 0 — ns 19.24-19.27, 19.32 Write strobe delay time 1 t WSD1 — 40 ns 19.22, 19.26, 19.27, 19.32, 19.33 Write strobe delay time 2 t WSD2 — 30 ns 19.22, 19.26, 19.27, 19.32 Write strobe delay time 3 t WSD3 — 40 ns 19.24, 19.25 Write strobe delay time 4 t WSD4 — 40 ns 19.24, 19.25, 19.33 Write data delay time 1 t WDD1 — 70 ns 19.22, 19.26, 19.27, 19.32 Write data delay time 2 t WDD2 — 40 ns 19.24, 19.25 Write data hold time t WDH –10 — ns 19.22, 19.24–19.27, 19.32 Parity output delay time 1 t WPDD1 — 80 ns 19.22, 19.24, 19.27 Parity output delay time 2 t WPDD2 — 40 ns 19.24, 19.25 Parity output hold time t WPDH –10 — ns 19.22, 19.24–19.27 RENESAS 474 t cyc × (n+0.5) – 35*2 19.32 Table 19.8 Bus Timing (3) (cont) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Item Symbol Min Max Unit Figures Wait setup time t WTS 40 — ns 19.23, 19.28, 19.32 Wait hold time t WTH 10 — ns Read data access time 1*4 t ACC1 t cyc – 44 — ns 19.21, 19.24, 19.25 Read data access time 2*4 t ACC2 t cyc × (n+2) – 44*2 — ns 19.22, 19.23, 19.26, 19.28 RAS delay time 1 t RASD1 — 40 ns RAS delay time 2 t RASD2 — 40 ns 19.24–19.27, 19.29– 19.31 CAS delay time 1 t CASD1 — 40 ns 19.24 CAS delay time 2 t CASD2 — 40 ns CAS delay time 3 t CASD3 — 40 ns 19.26, 19.27, 19.29– 19.31 t ASC 0 — ns 19.24, 19.25 Read data 35% access time from 50% duty CAS 1 *4 t CAC1 t cyc × 0.65 – 35 — ns t cyc × 0.5 – 35 — ns Read data access time from CAS 2 *4 t CAC2 t cyc × (n+1) – 35*2 — ns 19.26, 19.27, 19.28 Read data access time from RAS 1 *4 t RAC1 t cyc × 1.5 – 35 — ns 19.24, 19.25 Read data access time from RAS 2 *4 t RAC2 t cyc × (n+2.5) – 35*2 — ns 19.26, 19.27, 19.28 High-speed page mode CAS precharge time t CP t cyc × 0.25 — ns 19.25 AH delay time 1 t AHD1 — 40 ns 19.32 AH delay time 2 t AHD2 — 40 ns Multiplexed address delay time t MAD — 40 ns Multiplexed address hold time t MAH –10 — ns Column address setup time duty *1 RENESAS 475 Table 19.8 Bus Timing (3) (cont) Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products Item Symbol Min Max Unit Figures 19.21, 19.22, 19.24– 19.27, 19.32, 19.33 DACK0, DACK1 delay time 1 t DACD1 — 40 ns DACK0, DACK1 delay time 2 t DACD2 — 40 ns DACK0, DACK1 delay time 3 t DACD3 — 40 ns 19.22, 19.26, 19.27, 19.32 DACK0, DACK1 delay time 4 t DACD4 — 40 ns 19.24, 19.25 DACK0, DACK1 delay time 5 t DACD5 — 40 ns — t cyc × 0.35 + 35 ns — t cyc × 0.5 + 35 ns 19.21, 19.22, 19.2419.28, 19.32 — ns 19.24, 19.26 Read delay time 35% duty *1 t RDD 50% duty Data setup time for CAS t DS 0* 3 CAS setup time for RAS t CSR 10 — ns 19.29–19.31 Row address hold time t RAH 10 — ns 19.24, 19.26 t WCH 15 — ns Write command 35% setup time 50% duty t WCS 0 — ns t WCS 0 — ns Access time from CAS precharge *4 t ACP tcyc — -20 ns Write command hold time duty *1 Notes: 1. 2. 3. 4. 19.24 19.25 When frequency is 10 MHz or more. n is the number of wait cycles. –5 ns for parity output of DRAM long-pitch access It is not necessary to meet the tRDS specification as long as the access time specification is met. RENESAS 476 T1 CK tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tRDD tRDAC1*1 tRSD RD (Read) tACC1*2 tRDS AD15–AD0 DPH, DPL (Read) tDACD1 tRDH*3 tDACD2 DACK0 DACK1 Notes: 1. 2. 3. For tRDAC1, use t cyc × 0.65 – 35 (for 35% duty) or t cyc × 0.5 – 35 (for 50% duty) instead of tcyc – tRDD – t RDS. For tACC1, use t cyc – 44 instead of tcyc – tAD (or tCSD1) – tRDS. t RDH is measured from A21–A0, CSn, or RD, whichever is negated first. Figure 19.21 Basic Bus Cycle: One-State Access RENESAS 477 T1 T2 CK tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tRDAC2*1 tRDD tRSD RD (Read) tACC2*2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tDACD1 tWSD1 tRDH*3 tRDS tDACD2 tWSD2 WRH, WRL, WR (Write) tWDH tWDD1 AD15–AD0 (Write) tWPDH tWPDD1 DPH, DPL (Write) tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. For tRDAC2, use t cyc × (n + 1.65) – 35 (for 35% duty) or tcyc × (n + 1.5) – 35 (for 50% duty) instead of tcyc × (n + 2) – tRDD – tRDS. For tACC2, use t cyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD (or tCSD1) – tRDS. t RDH is measured from A21–A0, CSn, or RD, whichever is negated first. Figure 19.22 Basic Bus Cycle: Two-State Access RENESAS 478 T1 TW T2 CK A21–A0 HBS, LBS CSn tRDAC2*1 RD (Read) tACC2*2 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) WRH, WRL, WR (Write) AD15–AD0 DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. 2. For tRDAC2, use t cyc × (n + 1.65) – 35 (for 35% duty) or tcyc × (n + 1.5) – 35 (for 50% duty) instead of tcyc × (n + 2) – tRDD – tRDS. For tACC2, use t cyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD (or tCSD1) – tRDS. Figure 19.23 Basic Bus Cycle: Two States + Wait State RENESAS 479 Tp Tr Tc CK tAD tAD Row A21–A0 tRASD1 Column tRASD2 tRAH RAS tDS tASC CAS tCASD1 tRSD tRDD RD(Read) tWCH WRH, WRL, (Read) tDACD1 tDACD2 DACK0 DACK1 (Read) tACC1*2 tRAC1*3 AD15–AD0 DPH, DPL (Read) RD(Write) WRH, WRL, (Write) tWSD3 tRDH*4 tRDS tWCS tWDD2 AD15–AD0 (Write) DPH, DPL (Write) tCAC1*1 tWSD4 tWDH tWPDH tWPDD2 tDACD4 tDACD5 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC1, use t cyc × 0.65 – 35 (for 35% duty) or t cyc × 0.5 – 35 (for 50% duty) instead of tcyc – tAD – t ASC – tRDS. For tACC1, use t cyc – 44 instead of tcyc – tAD – t RDS. For tRAC1, use t cyc × 1.5 – 35 instead of t cyc × 1.5 – t RASD1 – tRDS. t RDH is measured from A21–A0, RAS, or CAS, whichever is negated first. Figure 19.24 DRAM Bus Cycle (Short Pitch, Normal Mode) RENESAS 480 Tp Tr Tc Tc Tc Tc CK tAD A21–A0 tAD Row address Column address Column address Column address Column address tRASD2 tRASD1 RAS tASC tCP CAS tRDD tRSD RD(Read) WRH, WRL, WR(Read) tCAC1*1 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) Notes: 1. 2. 3. 4. 5. tRAC1*3 tACC1*2 tACP tRDS tRDH*4 tRDH*5 tDACD1 tDACD2 For tCAC1, use tcyc × 0.65 – 35 (for 35% duty) or t cyc × 0.5 – 35 (for 50% duty) instead of t cyc – t AD – t ASC – tRDS . It is not necessary to meet the tRDS specification as long as the t CAC1 specification is met. For tACC1, use tcyc – 44 instead of t cyc – t AD – t RDS . It is not necessary to meet the tRDS specification as long as the t ACC1 specification is met. For tRAC1, use tcyc × 1.5 – 35 instead of t cyc × 1.5 – t RASD1 – t RDS . It is not necessary to meet the tRDS specification as long as the t RAC1 specification is met. t RDH is measured from A21—A0 or CAS, whichever is negated first. t RDH is measured from A21—A0, RAS, or CAS, whichever is negated first. Figure 19.25 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read) RENESAS 481 Tp Tr Silent cycle Tc Tc CK tAD tAD A21–A0 Row address Column address Column address tRASD2 tRASD1 RAS tASC CAS RD (Write) tWSD3 tWSD4 WRH, WRL, WR (Write) tWDD2 tWDH tWPDD2 tWPDH AD15–AD0 DPH, DPL (Write) DPH, DPL (Write) tDACD4 tDACD5 tDACD5 DACK0 DACK1 (Write) Figure 19.25 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write) Note: For details of the silent cycle, see section 8.5.5, Burst Operation. RENESAS 482 Tp Tr Tc1 Tc2 CK tAD A21–A0 tRASD1 tAD Row tRAH Column tRASD2 RAS tDS tCASD2 CAS tCASD3 tRDD tRDS RD(Read) tWCH WRH, WRL, (Read) tCAC2*1 tACC2*2 tRAC2*3 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) tRDS tRDH*4 tDACD2 tDACD1 RD(Write) WRH, WRL, (Write) AD15–AD0 (Write) DPH, DPL (Write) tWSD1 tWSD2 tWDH tWDD1 tWPDH tWPDD1 tDACD3 tDACD3 DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. For tCAC2, use t cyc × (n + 1) – 35 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2, use t cyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 35 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. t RDH is measured from A21–A0, CAS, or RAS, whichever is negated first. Figure 19.26 DRAM Bus Cycle: (Long Pitch, Normal Mode) RENESAS 483 Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD A21–A0 tAD Row tRASD1 Column Column tRASD2 RAS tCASD2 CAS tRSD WRH, WRL, (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) tCASD3 tRDD RD(Read) AD15–AD0 DPH, DPL (Read) tCASD3 tRAC2*3 tACC2*2 tCAC2*1 tRDS tRDH*4 tDACD1 tDACD2 tWSD1 tWDD1 tWSD2 tRDH*5 tDACD1 tWSD1 tDACD2 tWSD2 tWDH tWDD1 tWDH tWPDH tWPDD1 tWPDH AD15–AD0 (Write) tWPDD1 DPH, DPL (Write) DACK0 DACK1 (Write) Notes: 1. 2. 3. 4. 5. tDACD3 tDACD3 tDACD3 tDACD3 For tCAC2, use t cyc × (n + 1) – 35 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2, use t cyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 35 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. t RDH is measured from A21–A0 or CAS, whichever is negated first. t RDH is measured from A21–A0, RAS, or CAS whichever is negated first. Figure 19.27 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode) RENESAS 484 Tp Tr Tc1 Tw Tc2 CK Row A21–A0 Column tRDS RAS tRDD CAS RD(Read) WRH, WRL, (Read) tCAC2*1 tACC2*2 tRAC2*3 AD15–AD0 DPH, DPL (Read) DACK0 DACK1 (Read) RD(Write) WRH, WRL, (Write) AD15–AD0 (Write) DPH, DPL (Write) DACK0 DACK1 (Write) tWTS tWTH tWTS tWTH WAIT Notes: 1. 2. 3. For tCAC2, use t cyc × (n + 1) – 35 instead of tcyc × (n + 1) – tCASD2 – tRDS. For tACC2, use t cyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD – t RDS. For tRAC2, use t cyc × (n + 2.5) – 35 instead of tcyc × (n + 2.5) – tRASD1 – tRDS. Figure 19.28 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode + Wait State) RENESAS 485 TRp TRr TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL Figure 19.29 CAS-before-RAS Refresh (Short Pitch) TRp TRr TRc TRc CK tRASD1 RAS tRASD2 tCSR tCASD3 tCASD2 CAS WRH, WRL Figure 19.30 CAS-before-RAS Refresh (Long Pitch) RENESAS 486 TRp TRr TRc TRcc CK tRASD1 RAS tCSR tRASD2 tCASD3 tCASD2 CAS Figure 19.31 Self Refresh RENESAS 487 T1 T2 T3 T4 CK tAD A21–A0 HBS, LBS tCSD3 tCSD4 CS6 tAHD1 tAHD2 AH tRDD tRSD RD (Read) tMAD AD15–AD0 (Read) tMAH tRDAC3 Address tRDH Data (input) tDACD1 tDACD2 DACK0 DACK1 (Read) tWSD1 tWSD2 WRH, WRL, WR (Write) tMAD AD15–AD0 (Write) tMAH tWDD1 Data (output) Address tDACD3 DACK0 DACK1 (Write) tWDH tDACD3 tWTH tWTS WAIT Figure 19.32 Address/Data Multiplex I/O Bus Cycle RENESAS 488 T1 CK tAD A21–A0 HBS, LBS tCSD2 tCSD1 CSn tWSD1 tWSD4 tDACD1 tDACD2 WRH, WRL, WR (Write) DACK0 DACK1 (Write) Figure 19.33 DMA Single Transfer/Single State Access Write RENESAS 489 19.3.4 DMAC Timing Table 19.9 DMAC Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Case A 12.5 MHz Case B 16.6 MHz 20 MHz Item Symbol Min Max Min Max Min Max Unit Figure DREQ0, DREQ1 setup time t DRQS 80 — 40 — 27 — ns 19.34 DREQ0, DREQ1 hold time t DRQH 30 — 30 — 30 — ns DREQ0, DREQ1 low level width t DRQW 1.5 — 1.5 — 1.5 — t cyc CK tDRQS DREQ0, DREQ1 level tDRQS tDRQH DREQ0, DREQ1 edge tDRQS DREQ0, DREQ1 level release Figure 19.34 DREQ0, DREQ1 Input Timing (1) CK DREQ0, DREQ1 edge tDRQW Figure 19.35 DREQ0, DREQ1 Input Timing (2) RENESAS 490 19.35 19.3.5 16-bit Integrated Timer Pulse Unit Timing Table 19.10 16-bit Integrated Timer Pulse Unit Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Case A 12.5 MHz Case B 16.6 MHz 20 MHz Item Symbol Min Max Min Max Min Max Unit Figure Output compare delay time t TOCD — 100 — 100 — 100 ns 19.36 Input capture setup time t TICS 50 — 45 — 35 — ns Timer clock input setup time t TCKS 50 — 50 — 50 — ns Timer clock pulse width (single edge) t TCKWH/L 1.5 — 1.5 — 1.5 — t cyc Timer clock pulse width (both edges) t TCKWH/L 2.5 — 2.5 — 2.5 — t cyc 19.37 CK tTOCD Output compare*1 tTICS Output capture*2 Notes: 1. 2. TIOCA0–TIOCA4, TIOCB0–TIOCB4, TOCXA4, TOCXB4 TIOCA0–TIOCA4, TIOCB0–TIOCB4 Figure 19.36 ITU Input/Output Timing RENESAS 491 CK tTCKS TCLKA– TCLKD tTCKWL tTCKS tTCKWH Figure 19.37 ITU Clock Input Timing RENESAS 492 19.3.6 Programmable Timing Pattern Controller and I/O Port Timing Table 19.11 Programmable Timing Pattern Controller and I/O Port Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* Case C: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Cases A, B and C Item Symbol Min Max Unit Figure Port output delay time t PWD — 100 ns 19.38 Port input hold time t PRH 50 — ns Port input setup time t PRS 50 — ns T1 T2 T3 CK tPRS Ports A, B (read) tPRH tPWD Ports A, B (write) Figure 19.38 Programmable Timing Pattern Controller Output Timing RENESAS 493 19.3.7 Watchdog Timer Timing Table 19.12 Watchdog Timer Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 V, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* Case C: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products. Ta = –40 to +85°C for wide-temperature range products. Cases A, B and C Item Symbol Min Max Unit Figure WDTOVF delay time t WOVD — 100 ns 20.39 CK tWOVD tWOVD WDTOVF Figure 19.39 Watchdog Timer Output Timing RENESAS 494 19.3.8 Serial Communications Interface Timing Table 19.13 Serial Communications Interface Timing Case A: V CC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C* Case B: VCC = 5.0 V ±10%, V SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C* Case C: VCC = 5.0 V ±10%, V SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C* *: Normal products: Ta = –40 to +85°C for wide-temperature range products. Cases A, B and C Item Symbol Min Max Unit Figure Input clock cycle t scyc 4 — t cyc 19.40 Input clock cycle (clocked synchronization) t scyc 6 — t cyc Input clock pulse width t sckw 0.4 0.6 t scyc Input clock rise time t sckr — 1.5 t cyc Input clock fall time t sckf — 1.5 t cyc Transmission data delay time (clocked synchronization) t TXD — 100 ns Receive data setup time (clocked synchronization) t RXS 100 — ns Receive data hold time (clocked synchronization) t RXH 100 — ns tSCKW tSCKr tSCKf 19.41 SCK0, SCK1 tscyc Figure 19.40 Input Clock Timing RENESAS 495 tscyc SCK0, SCK1 tTXD TxD0, TxD1 (transmission data) tRXS tRXH RxD0, RxD1 (reception data) Figure 19.41 SCI I/O Timing (Clocked Synchronization Mode) RENESAS 496 19.3.9 AC Characteristics Measurement Conditions IOL LSI output pin Device under test output V Vref CL IOH CL is set as follows for each pin. 30pF: CK, CASH, CASL, CS0–CS7, BREQ, BACK, AH, IRQOUT, RAS, DACK0, DACK1 50pF: A21–A0, AD15–AD0, DPH, DPL, RD, WRH, WRL, HBS, LBS, WR 70pF: All port outputs and peripheral module output pins other than the above. I OL and IOH values are as shown in section 19.2, DC Characteristics, and table 19.3, Permitted Output Current Values. Figure 19.42 Output Load Circuit RENESAS 497 19.4 Usage Note The ZTAT version and the mask ROM version satisfy the electrical properties given in this document. However, effective values of the electrical properties, the operating margin, and the noise margin may differ with the manufacturing processes, on-chip ROM, and layout patterns. When conducting a system evaluation test using the ZTAT version, conduct a similar evaluation test of the mask ROM version before it replaces the ZTAT version. RENESAS 498 SH7020, SH7021 Hardware Manual Publication Date: 1st Edition, September 1994 3rd Edition, September 1998 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1994. All rights reserved. Printed in Japan.