HD6417616SFV

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SH7616 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/ SH7600 Series SH7616 HD6417616 Rev.2.00 2006.03 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 2.00 Mar 09, 2006 page ii of xxvi Preface The SH7616 is a microprocessor that integrates peripheral functions necessary for system configuration with a 32-bit internal architecture SH2-DSP CPU as its core. The SH7616's on-chip peripheral functions include a cache memory, an interrupt controller, timers, an ethernet controller (EtherC), DSP, a serial communication interface with FIFO (SCIF), a USB function module, a user break controller (UBC), a bus state controller (BSC), a direct memory access cntroller (DMAC), and I/O ports, making it ideal for use as a microcomputer in electronic devices that require high speed together with low power consumption. Intended Readership: This manual is intended for users undertaking the design of an application system using the SH7616. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. Purpose: The purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the SH7616. Details of execution instructions can be found in the SH-1, SH-2, SH-DSP Programming Manual, which should be read in conjunction with the present manual. Using this Manual: • For an overall understanding of the SH7616's functions Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics. • For a detailed understanding of CPU functions Refer to the separate publication SH-1, SH-2, SH-DSP Programming Manual. Note on bit notation: Bits are shown in high-to-low order from left to right. Related Material: The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. http://www.renesas.com/ Rev. 2.00 Mar 09, 2006 page iii of xxvi User's Manuals on the SH7616: Manual Title ADE No. SH7616 Hardware Manual This manual SH-1/ SH-2/SH-DSP Software Manual REJ09B0171-0500O Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual REJ10B0152-0101 Simulator Debugger Users Manual REJ10B0210-0200 High-performance Embedded Workshop Users Manual REJ10J0886-0300 Application Note: Manual Title ADE No. C/C++ Complier REJ05B0463-0300 Rev. 2.00 Mar 09, 2006 page iv of xxvi Main Revisions in This Edition Item Page Revision (See Manual for Details) All  • • 2.1.4 DSP Registers 37 Company name amended Hitachi, Ltd. → Renesas Technology Corp. Amendments made due to change in package code FP-208C → PRQP0208KA-A Description added Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2. Registers A0, X0, X1, Y0, Y1, and DSR are handled as system registers by CPU core instructions. 7.1.5 Address Map 255 Table 7.3 Address Map 7.2.7 Individual Memory Control Register (MCR) Table amended Address Space H'1000E000–H'1000EFFF On-chip X RAM area Memory 4 kbytes Size H'1001E000–H'1001EFFF On-chip Y RAM area 4 kbytes 269 to Description replaced 274 Bits 1 and 15 • For synchronous DRAM interface Bits 7, 5, and 4 7.5.11 64 Mbit 323 Synchronous DRAM (2 Mword × 32-bit) Connection Description amended 8.4.7 Associative Purges Figure amended Figure 8.11 Associative Purge Access 369 Synchronous DRAM Mode Settings: To make mode settings for the synchronous DRAM, write to address X+H'FFFF0000 or X+H'FFFF8000 from the CPU. (X represents the setting value.) Whether to use X+H'FFFF0000 or X+H'FFFF8000 determines on the synchronous DRAM used. Associative purge: Bit Address 31 29 28 010 Number of bits 3 10 9 Tag address 19 43 Entry address 6 0 — 4 Rev. 2.00 Mar 09, 2006 page v of xxvi Item Page Revision (See Manual for Details) 10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) 437 Description amended Bit: 31 30 29 ... 19 18 17 16 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RMAFCE — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R Bits 31 to 8—Reserved These bits are always read as 0. The write value should always be 0. Bit 7—Multicast Address Frame Receive (RMAF): Bit Copy Enable (RMAFCE) Bit 7: RMAFCE Description 0 Enables the RMAF bit status to be indicated in the RFS7 bit in the receive descriptor. 1 Disables occurrence of corresponding source to be indicated in the RFS7 bit in the receive descriptor. Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0. 10.3.1 Descriptor 450 List and Data Buffers Transmit Descriptor 0 (TD0) Description amended Bit 27—Transmit Frame Error (TFE): Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. Bit 27: TFE Description 0 No error during transmission 1 An error of some kind occurred during transmission (see bits 26 to 0) Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0): These bits indicate the error status during frame transmission. • TFS26 to TFS9—Reserved • TFS8—Teransmit Abort Detect Note: This bit is set to 1 when any of Transmit Frame Status bits 4 to 0 is set. When this bit is set, the Transmit Frame Error bit (bit 27: TFE) is set to 1. • TFS7 to TFS5—Reserved Rev. 2.00 Mar 09, 2006 page vi of xxvi Page 10.3.1 Descriptor 451 List and Data Buffers Revision (See Manual for Details) Figure amended Receive descriptor Receive Descriptor Figure 10.3 Relationship between Receive Descriptor and Receive Buffer 31 30 29 28 27 26 RD0 RD1 RD2 RACT RDLE RFP1 RFP0 RFE Item RFS 26 to RFS0 31 16 15 31 RBL RBA RDL 0 0 Padding (4 bytes) Rev. 2.00 Mar 09, 2006 page vii of xxvi Item Page 10.3.1 Descriptor 453 List and Data Buffers Receive Descriptor 0 (TD0) Revision (See Manual for Details) Description amended Bit 27—Receive Frame Error (RFE): Indicates that one or other bit of the receive frame status indicated by bits 26 to 0 is set. Whether or not the multicast address frame receive information which is part of the frame status, is copied into this bit is specified by the transmit/receive status copy enable register. Bit 27: RFE Description 0 No error during reception 1 An error of some kind occurred during reception (see bits 26 to 0) (Initial value) • Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0): These bits indicate the error status during frame reception. • RFS26 to RFS10—Reserved • RFS9—Receive FIFO Overflow (corresponds to RFOF bit in EESR) • RFS8—Reserve Abort Detect Note: • • This bit is set to 1 when any of Receive Frame Status bit 9, bit 7, bits 4 to 0 is set. When this bit is set, the Receive Frame Error bit (bit 27: RFE) is set to 1. RFS7— Receive Multicast Address Frame (corresponds to RMAF bit in EESR) 1 RFS6—Reserved* • RSF5— Receive Frame Discard Request Assertion 1 (corresponds to RFAR bit in EESR)* • RFS4—Receive Residual-Bit Frame (corresponds to RRF bit in EESR) • RFS3—Receive Too-Long Frame (corresponds to RTLF bit in EESR) • RFS2—Receive Too-Short Frame (corresponds to RTSF bit in EESR) • RFS1—PHY-LSI Receive Error (corresponds to PRE bit in EESR) • RFS0—CRC Error on Received Frame (corresponds to CERF bit in EESR) Note: 1. Only HD6417616 is effective. HD6417615 is Reserved bit. Rev. 2.00 Mar 09, 2006 page viii of xxvi Item Page Revision (See Manual for Details) 11.3.6 DMA Transfer 496 Request Acknowledge Signal Output Timing Figure replaced Figure 11.13 Example of DACKn Output Timing DACKn (Active high) Clock 0.5 cycles Address bus CPU 14.3.4 Operation in 613 Synchronous Mode Description amended 15.4 SIOF Interrupt 663 Sources and DMAC Description amended Table 15.3 SIOF Interrupt Sources Table amended Appendix C Table C.1 SH7616 Product Lineup 664 904 DMAC In synchronous mode, the SCIF receives data in synchronization with the rise of the serial clock. Each SIOF channel has four interrupt sources: the receive-overrunerror interrupt (RERI0) request, transmit-underrun-error interrupt (TERI0) request, receive-data-full interrupt/receive-control-dataregister-full interrupt (RDFI0) request, and transmit-data-empty interrupt/transmit-control-data-register-empty interrupt (TDEI0) request. Table 15.3 shows the interrupt sources and their relative priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE, RCIE, TIE, and TCIE bits, respectively, in SICTR. The RERI0 and TERI0 interrupts cannot be disabled. Interrupt Source Description DMAC Activation Priority RERI0 Receive overrun error (RERR) Not possible High TERI0 Transmit underrun error (TERR) Not possible ↑ RDFI0 Receive data register full (RDRF)/ Receive Control Data Register Full (RCD) Possible* TDEI0 Possible* Transmit data register empty (TDRE)/ Transmit Control Data Register Empty (TCD) ↓ Low Table amended Abbreviation Voltage Operating Frequency Mark Code Package SH7616 3.3 V 62.5 MHz HD6417616SF PLQP0208KA-A Rev. 2.00 Mar 09, 2006 page ix of xxvi Rev. 2.00 Mar 09, 2006 page x of xxvi Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1.4 Features of SuperH Microcomputer with On-Chip Ethernet Controller ........................... Block Diagram .................................................................................................................. Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Multiplexing .................................................................................................. Processing States............................................................................................................... 1 1 13 14 14 15 21 27 Section 2 CPU ...................................................................................................................... 31 2.1 2.2 2.3 2.4 2.5 2.6 Register Configuration ...................................................................................................... 2.1.1 General Registers ................................................................................................. 2.1.2 Control Registers ................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 DSP Registers ...................................................................................................... 2.1.5 Notes on Guard Bits and Overflow Treatment..................................................... 2.1.6 Initial Values of Registers.................................................................................... Data Formats ..................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Formats in Memory ..................................................................................... 2.2.3 Immediate Data Format ....................................................................................... 2.2.4 DSP Type Data Formats ...................................................................................... 2.2.5 DSP Type Instructions and Data Formats ............................................................ CPU Core Instruction Features ......................................................................................... Instruction Formats ........................................................................................................... 2.4.1 CPU Instruction Addressing Modes..................................................................... 2.4.2 DSP Data Addressing........................................................................................... 2.4.3 Instruction Formats for CPU Instructions ............................................................ 2.4.4 Instruction Formats for DSP Instructions............................................................. Instruction Set ................................................................................................................... 2.5.1 CPU Instruction Set ............................................................................................. 2.5.2 DSP Data Transfer Instruction Set ....................................................................... 2.5.3 DSP Operation Instruction Set ............................................................................. 2.5.4 Various Operation Instructions ............................................................................ Usage Notes ...................................................................................................................... 2.6.1 When not using DSP instructions ........................................................................ 31 31 33 36 37 40 40 41 41 41 42 42 44 48 52 52 56 62 66 72 73 89 93 96 105 105 Rev. 2.00 Mar 09, 2006 page xi of xxvi 2.6.2 When executing a combination of double-precision multiplication or double-precision product-sum operation (CPU instruction) and DSP computing instruction .......................................................................................... 105 Section 3 Oscillator Circuits and Operating Modes .................................................. 107 3.1 3.2 3.3 Overview........................................................................................................................... On-Chip Clock Pulse Generator and Operating Modes .................................................... 3.2.1 Clock Pulse Generator ......................................................................................... 3.2.2 Clock Operating Mode Settings........................................................................... 3.2.3 Connecting a Crystal Resonator........................................................................... 3.2.4 External Clock Input ............................................................................................ 3.2.5 Operating Frequency Selection by Register......................................................... 3.2.6 Clock Modes and Frequency Ranges................................................................... 3.2.7 Notes on Board Design ........................................................................................ Bus Width of the CS0 Area............................................................................................... 107 107 107 109 112 113 114 122 123 124 Section 4 Exception Handling ......................................................................................... 125 4.1 4.2 4.3 4.4 4.5 4.6 Overview........................................................................................................................... 4.1.1 Types of Exception Handling and Priority Order ................................................ 4.1.2 Exception Handling Operations ........................................................................... 4.1.3 Exception Vector Table ....................................................................................... Resets ................................................................................................................................ 4.2.1 Types of Resets .................................................................................................... 4.2.2 Power-On Reset ................................................................................................... 4.2.3 Manual Reset ....................................................................................................... Address Errors .................................................................................................................. 4.3.1 Sources of Address Errors ................................................................................... 4.3.2 Address Error Exception Handling ...................................................................... Interrupts ........................................................................................................................... 4.4.1 Interrupt Sources.................................................................................................. 4.4.2 Interrupt Priority Levels....................................................................................... 4.4.3 Interrupt Exception Handling............................................................................... Exceptions Triggered by Instructions ............................................................................... 4.5.1 Instruction-Triggered Exception Types ............................................................... 4.5.2 Trap Instructions .................................................................................................. 4.5.3 Illegal Slot Instructions ........................................................................................ 4.5.4 General Illegal Instructions.................................................................................. When Exception Sources Are Not Accepted .................................................................... 4.6.1 Immediately after a Delayed Branch Instruction ................................................. 4.6.2 Immediately after an Interrupt-Disabled Instruction............................................ Rev. 2.00 Mar 09, 2006 page xii of xxvi 125 125 127 128 131 131 131 132 132 132 134 135 135 136 136 137 137 137 138 138 139 139 139 4.7 4.8 4.6.3 Instructions in Repeat Loops................................................................................ Stack Status after Exception Handling.............................................................................. Usage Notes ...................................................................................................................... 4.8.1 Value of Stack Pointer (SP) ................................................................................. 4.8.2 Value of Vector Base Register (VBR) ................................................................. 4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ........ 4.8.4 Manual Reset during Register Access.................................................................. 140 141 142 142 142 142 142 Section 5 Interrupt Controller (INTC) ........................................................................... 143 5.1 5.2 5.3 Overview........................................................................................................................... 5.1.1 Features ................................................................................................................ 5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Interrupt Sources ............................................................................................................... 5.2.1 NMI Interrupt....................................................................................................... 5.2.2 User Break Interrupt............................................................................................. 5.2.3 H-UDI Interrupt ................................................................................................... 5.2.4 IRL Interrupts....................................................................................................... 5.2.5 IRQ Interrupts ...................................................................................................... 5.2.6 On-chip Peripheral Module Interrupts ................................................................. 5.2.7 Interrupt Exception Vectors and Priority Order ................................................... Register Descriptions ........................................................................................................ 5.3.1 Interrupt Priority Level Setting Register A (IPRA) ............................................. 5.3.2 Interrupt Priority Level Setting Register B (IPRB).............................................. 5.3.3 Interrupt Priority Level Setting Register C (IPRC).............................................. 5.3.4 Interrupt Priority Level Setting Register D (IPRD) ............................................. 5.3.5 Interrupt Priority Level Setting Register E (IPRE) .............................................. 5.3.6 Vector Number Setting Register WDT (VCRWDT) ........................................... 5.3.7 Vector Number Setting Register A (VCRA)........................................................ 5.3.8 Vector Number Setting Register B (VCRB) ........................................................ 5.3.9 Vector Number Setting Register C (VCRC) ........................................................ 5.3.10 Vector Number Setting Register D (VCRD)........................................................ 5.3.11 Vector Number Setting Register E (VCRE) ........................................................ 5.3.12 Vector Number Setting Register F (VCRF) ......................................................... 5.3.13 Vector Number Setting Register G (VCRG)........................................................ 5.3.14 Vector Number Setting Register H (VCRH)........................................................ 5.3.15 Vector Number Setting Register I (VCRI)........................................................... 5.3.16 Vector Number Setting Register J (VCRJ) .......................................................... 5.3.17 Vector Number Setting Register K (VCRK)........................................................ 143 143 143 145 145 146 147 147 147 147 148 152 152 159 159 160 161 162 163 164 165 166 166 167 168 169 170 171 172 173 174 Rev. 2.00 Mar 09, 2006 page xiii of xxvi 5.4 5.5 5.6 5.7 5.3.18 Vector Number Setting Register L (VCRL) ........................................................ 5.3.19 Vector Number Setting Register M (VCRM) ...................................................... 5.3.20 Vector Number Setting Register N (VCRN)........................................................ 5.3.21 Vector Number Setting Register O (VCRO)........................................................ 5.3.22 Vector Number Setting Register P (VCRP)......................................................... 5.3.23 Vector Number Setting Register Q (VCRQ)........................................................ 5.3.24 Vector Number Setting Register R (VCRR) ........................................................ 5.3.25 Vector Number Setting Register S (VCRS)......................................................... 5.3.26 Vector Number Setting Register T (VCRT) ........................................................ 5.3.27 Vector Number Setting Register U (VCRU)........................................................ 5.3.28 Interrupt Control Register (ICR).......................................................................... 5.3.29 IRQ Control/Status Register (IRQCSR) .............................................................. Interrupt Operation............................................................................................................ 5.4.1 Interrupt Sequence ............................................................................................... 5.4.2 Stack State after Interrupt Exception Handling.................................................... Interrupt Response Time................................................................................................... Sampling of Pins IRL3–IRL0 ........................................................................................... Usage Notes ...................................................................................................................... 175 176 177 178 179 180 181 182 183 184 187 188 190 190 192 192 194 195 Section 6 User Break Controller (UBC) ....................................................................... 199 6.1 6.2 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Mask Register A (BAMRA)........................................................ 6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 6.2.4 Break Address Register B (BARB) ..................................................................... 6.2.5 Break Address Mask Register B (BAMRB) ........................................................ 6.2.6 Break Bus Cycle Register B (BBRB) .................................................................. 6.2.7 Break Address Register C (BARC)...................................................................... 6.2.8 Break Address Mask Register C (BAMRC) ........................................................ 6.2.9 Break Data Register C (BDRC) ........................................................................... 6.2.10 Break Data Mask Register C (BDMRC).............................................................. 6.2.11 Break Bus Cycle Register C (BBRC) .................................................................. 6.2.12 Break Execution Times Register C (BETRC) ..................................................... 6.2.13 Break Address Register D (BARD) ..................................................................... 6.2.14 Break Address Mask Register D (BAMRD)........................................................ 6.2.15 Break Data Register D (BDRD)........................................................................... Rev. 2.00 Mar 09, 2006 page xiv of xxvi 199 199 200 201 203 203 204 205 207 208 209 211 212 214 215 217 218 219 220 222 6.3 6.2.16 Break Data Mask Register D (BDMRD) ............................................................. 6.2.17 Break Bus Cycle Register D (BBRD) .................................................................. 6.2.18 Break Execution Times Register D (BETRD) ..................................................... 6.2.19 Break Control Register (BRCR) .......................................................................... 6.2.20 Branch Flag Registers (BRFR) ............................................................................ 6.2.21 Branch Source Registers (BRSR) ........................................................................ 6.2.22 Branch Destination Registers (BRDR) ................................................................ Operation........................................................................................................................... 6.3.1 User Break Operation Sequence .......................................................................... 6.3.2 Instruction Fetch Cycle Break.............................................................................. 6.3.3 Data Access Cycle Break ..................................................................................... 6.3.4 Saved Program Counter (PC) Value .................................................................... 6.3.5 X Memory Bus or Y Memory Bus Cycle Break .................................................. 6.3.6 Sequential Break .................................................................................................. 6.3.7 PC Traces............................................................................................................. 6.3.8 Examples of Use .................................................................................................. 6.3.9 Usage Notes ......................................................................................................... 223 225 226 227 233 234 235 236 236 237 238 239 239 240 241 243 247 Section 7 Bus State Controller (BSC) ........................................................................... 249 7.1 7.2 7.3 7.4 Overview........................................................................................................................... 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Pin Configuration................................................................................................. 7.1.4 Register Configuration......................................................................................... 7.1.5 Address Map ........................................................................................................ Register Descriptions ........................................................................................................ 7.2.1 Bus Control Register 1 (BCR1) ........................................................................... 7.2.2 Bus Control Register 2 (BCR2) ........................................................................... 7.2.3 Bus Control Register 3 (BCR3) ........................................................................... 7.2.4 Wait Control Register 1 (WCR1)......................................................................... 7.2.5 Wait Control Register 2 (WCR2)......................................................................... 7.2.6 Wait Control Register 3 (WCR3)......................................................................... 7.2.7 Individual Memory Control Register (MCR)....................................................... 7.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 7.2.9 Refresh Timer Counter (RTCNT)........................................................................ 7.2.10 Refresh Time Constant Register (RTCOR) ......................................................... Access Size and Data Alignment ...................................................................................... 7.3.1 Connection to Ordinary Devices.......................................................................... 7.3.2 Connection to Little-Endian Devices ................................................................... Accessing Ordinary Space ................................................................................................ 249 249 251 252 254 255 257 257 260 261 263 265 267 268 276 278 278 279 279 280 282 Rev. 2.00 Mar 09, 2006 page xv of xxvi 7.4.1 Basic Timing........................................................................................................ 7.4.2 Wait State Control................................................................................................ 7.4.3 CS Assertion Period Extension ............................................................................ 7.5 Synchronous DRAM Interface.......................................................................................... 7.5.1 Synchronous DRAM Direct Connection ............................................................. 7.5.2 Address Multiplexing........................................................................................... 7.5.3 Burst Reads .......................................................................................................... 7.5.4 Single Reads ........................................................................................................ 7.5.5 Single Writes........................................................................................................ 7.5.6 Burst Write Mode ................................................................................................ 7.5.7 Bank Active Function .......................................................................................... 7.5.8 Refreshes.............................................................................................................. 7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access ........................ 7.5.10 Power-On Sequence............................................................................................. 7.5.11 64 Mbit Synchronous DRAM (2 Mword × 32-bit) Connection........................... 7.6 DRAM Interface ............................................................................................................... 7.6.1 DRAM Direct Connection ................................................................................... 7.6.2 Address Multiplexing........................................................................................... 7.6.3 Basic Timing........................................................................................................ 7.6.4 Wait State Control................................................................................................ 7.6.5 Burst Access ........................................................................................................ 7.6.6 EDO Mode........................................................................................................... 7.6.7 DRAM Single Transfer........................................................................................ 7.6.8 Refreshing............................................................................................................ 7.6.9 Power-On Sequence............................................................................................. 7.7 Burst ROM Interface......................................................................................................... 7.8 Idles between Cycles......................................................................................................... 7.9 Bus Arbitration.................................................................................................................. 7.9.1 Master Mode ........................................................................................................ 7.10 Additional Items................................................................................................................ 7.10.1 Resets................................................................................................................... 7.10.2 Access as Viewed from CPU, DMAC or E-DMAC ............................................ 7.10.3 STATS1 and STATS0 Pins ................................................................................. 7.10.4 BUSHiZ Specification ......................................................................................... 7.11 Usage Notes ...................................................................................................................... 7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC..... 7.11.2 When Using Iφ: Eφ Clock Ratio of 1: 1, 8-Bit Bus Width, and External Wait Input ....................................................................................... 7.11.3 When connecting external device to synchronous DRAM .................................. Rev. 2.00 Mar 09, 2006 page xvi of xxvi 282 287 291 292 292 294 296 301 303 304 306 317 320 321 323 324 324 325 326 327 329 332 336 337 339 339 343 345 349 350 350 351 352 353 354 354 356 356 Section 8 Cache .................................................................................................................... 357 8.1 8.2 8.3 8.4 8.5 8.6 Introduction....................................................................................................................... 8.1.1 Register Configuration......................................................................................... Register Description.......................................................................................................... 8.2.1 Cache Control Register (CCR)............................................................................. Address Space and the Cache............................................................................................ Cache Operation................................................................................................................ 8.4.1 Cache Reads......................................................................................................... 8.4.2 Write Access ........................................................................................................ 8.4.3 Cache-Through Access ........................................................................................ 8.4.4 The TAS Instruction............................................................................................. 8.4.5 Pseudo-LRU and Cache Replacement ................................................................. 8.4.6 Cache Initialization .............................................................................................. 8.4.7 Associative Purges ............................................................................................... 8.4.8 Cache Flushing..................................................................................................... 8.4.9 Data Array Access ............................................................................................... 8.4.10 Address Array Access.......................................................................................... Cache Use ......................................................................................................................... 8.5.1 Initialization ......................................................................................................... 8.5.2 Purge of Specific Lines ........................................................................................ 8.5.3 Cache Data Coherency......................................................................................... 8.5.4 Two-Way Cache Mode ........................................................................................ Usage Notes ...................................................................................................................... 8.6.1 Standby ................................................................................................................ 8.6.2 Cache Control Register ........................................................................................ 357 358 358 358 360 361 361 363 366 366 366 368 368 369 369 370 371 371 372 372 373 374 374 374 Section 9 Ethernet Controller (EtherC) ......................................................................... 375 9.1 9.2 Overview........................................................................................................................... 9.1.1 Features ................................................................................................................ 9.1.2 Configuration ....................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Ethernet Controller Register Configuration ......................................................... Register Descriptions ........................................................................................................ 9.2.1 EtherC Mode Register (ECMR)........................................................................... 9.2.2 EtherC Status Register (ECSR)............................................................................ 9.2.3 EtherC Interrupt Permission Register (ECSIPR) ................................................. 9.2.4 PHY Interface Register (PIR) .............................................................................. 9.2.5 MAC Address High Register (MAHR)................................................................ 9.2.6 MAC Address Low Register (MALR)................................................................. 9.2.7 Receive Frame Length Register (RFLR) ............................................................. 375 375 376 378 379 380 380 383 384 385 386 387 388 Rev. 2.00 Mar 09, 2006 page xvii of xxvi 9.3 9.4 9.2.8 PHY Interface Status Register (PSR)................................................................... 9.2.9 Transmit Retry Over Counter Register (TROCR) ............................................... 9.2.10 Single Collision Detect Counter Register (SCDCR)............................................ 9.2.11 Delay Collision Detect Counter Register (CDCR) .............................................. 9.2.12 Lost Carrier Counter Register (LCCR) ................................................................ 9.2.13 Carrier Not Detect Counter Register (CNDCR) .................................................. 9.2.14 Illegal Frame Length Counter Register (IFLCR) ................................................. 9.2.15 CRC Error Frame Counter Register (CEFCR)..................................................... 9.2.16 Frame Receive Error Counter Register (FRECR )............................................... 9.2.17 Too-Short Frame Receive Counter Register (TSFRCR)...................................... 9.2.18 Too-Long Frame Receive Counter Register (TLFRCR)...................................... 9.2.19 Residual-Bit Frame Counter Register (RFCR) .................................................... 9.2.20 Multicast Address Frame Counter Register (MAFCR)........................................ Operation .......................................................................................................................... 9.3.1 Transmission........................................................................................................ 9.3.2 Reception ............................................................................................................. 9.3.3 MII Frame Timing ............................................................................................... 9.3.4 Accessing MII Registers ...................................................................................... 9.3.5 Magic Packet Detection ....................................................................................... 9.3.6 CPU Operating Mode and Ethernet Controller Operation ................................... 9.3.7 CAM Match Signal Input Function...................................................................... Connection to PHY-LSI.................................................................................................... 389 390 391 392 393 394 395 396 397 398 399 400 401 402 402 404 406 408 411 412 413 415 Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC) ....................................................................................................... 417 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Configuration ....................................................................................................... 10.1.3 Descriptor Management System .......................................................................... 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 E-DMAC Mode Register (EDMR) ...................................................................... 10.2.2 E-DMAC Transmit Request Register (EDTRR).................................................. 10.2.3 E-DMAC Receive Request Register (EDRRR) ................................................... 10.2.4 Transmit Descriptor List Address Register (TDLAR) ......................................... 10.2.5 Receive Descriptor List Address Register (RDLAR) .......................................... 10.2.6 EtherC/E-DMAC Status Register (EESR) ........................................................... 10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) ...................... 10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) ................................ 10.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................... Rev. 2.00 Mar 09, 2006 page xviii of xxvi 417 417 418 419 419 421 421 422 423 424 425 426 432 437 438 10.2.10 Transmit FIFO Threshold Register (TFTR)......................................................... 10.2.11 FIFO Depth Register (FDR)................................................................................. 10.2.12 Receiver Control Register (RCR) ........................................................................ 10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................ 10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......................................... 10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) .................................... 10.2.16 Transmission-Buffer Read Address Register (TBRAR) ...................................... 10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................... 10.3 Operation........................................................................................................................... 10.3.1 Descriptor List and Data Buffers ......................................................................... 10.3.2 Transmission ........................................................................................................ 10.3.3 Reception ............................................................................................................. 10.3.4 Multi-Buffer Frame Transmit/Receive Processing .............................................. 439 441 442 443 444 445 446 447 448 448 455 457 459 Section 11 Direct Memory Access Controller (DMAC) .......................................... 461 11.1 Overview........................................................................................................................... 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1)..................................... 11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1) ............................ 11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) ..................................... 11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1) ............................. 11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) ................. 11.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1) ............................................................................................... 11.2.7 DMA Operation Register (DMAOR)................................................................... 11.3 Operation........................................................................................................................... 11.3.1 DMA Transfer Flow............................................................................................. 11.3.2 DMA Transfer Requests ...................................................................................... 11.3.3 Channel Priorities................................................................................................. 11.3.4 DMA Transfer Types ........................................................................................... 11.3.5 Number of Bus Cycles ......................................................................................... 11.3.6 DMA Transfer Request Acknowledge Signal Output Timing ............................. 11.3.7 DREQn Pin Input Detection Timing.................................................................... 11.3.8 DMA Transfer End .............................................................................................. 11.3.9 BH Pin Output Timing......................................................................................... 11.4 Usage Examples................................................................................................................ 461 461 463 464 465 466 466 466 467 467 472 473 475 477 477 479 483 486 496 496 507 513 514 516 Rev. 2.00 Mar 09, 2006 page xix of xxvi 11.4.1 Example of DMA Data Transfer Between SCIF and External Memory.............. 516 11.5 Usage Notes ...................................................................................................................... 516 Section 12 16-Bit Free-Running Timer (FRT)............................................................ 519 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Free-Running Counter (FRC) .............................................................................. 12.2.2 Output Compare Registers A and B (OCRA and OCRB).................................... 12.2.3 Input Capture Register (FICR)............................................................................. 12.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 12.2.5 Free-Running Timer Control/Status Register (FTCSR)....................................... 12.2.6 Timer Control Register (TCR)............................................................................. 12.2.7 Timer Output Compare Control Register (TOCR) .............................................. 12.3 CPU Interface.................................................................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 FRC Count Timing .............................................................................................. 12.4.2 Output Timing for Output Compare .................................................................... 12.4.3 FRC Clear Timing................................................................................................ 12.4.4 Input Capture Input Timing ................................................................................. 12.4.5 Input Capture Flag (ICF) Setting Timing............................................................. 12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing ....................................... 12.4.7 Timer Overflow Flag (OVF) Setting Timing....................................................... 12.5 Interrupt Sources ............................................................................................................... 12.6 Example of FRT Use......................................................................................................... 12.7 Usage Notes ...................................................................................................................... 12.7.1 Contention between FRC Write and Clear........................................................... 12.7.2 Contention between FRC Write and Increment ................................................... 12.7.3 Contention between OCR Write and Compare Match......................................... 12.7.4 Internal Clock Switching and Counter Operation ................................................ 12.7.5 Timer Output (FTOA, FTOB) ............................................................................. 519 519 520 521 521 522 522 522 523 523 524 526 527 528 531 531 532 532 533 534 534 535 536 536 537 537 538 539 540 541 Section 13 Watchdog Timer (WDT).............................................................................. 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 543 543 543 544 544 Rev. 2.00 Mar 09, 2006 page xx of xxvi 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 13.2.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 13.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 13.2.4 Notes on Register Access..................................................................................... 13.3 Operation........................................................................................................................... 13.3.1 Operation in Watchdog Timer Mode ................................................................... 13.3.2 Operation in Interval Timer Mode ....................................................................... 13.3.3 Operation when Standby Mode is Cleared........................................................... 13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 13.4 Usage Notes ...................................................................................................................... 13.4.1 Contention between WTCNT Write and Increment............................................. 13.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 13.4.4 System Reset with WDTOVF.............................................................................. 13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 545 545 545 546 547 549 550 550 552 552 553 553 554 554 554 554 555 555 Section 14 Serial Communication Interface with FIFO (SCIF) ............................. 14.1 Overview........................................................................................................................... 14.1.1 Features ................................................................................................................ 14.1.2 Block Diagrams ................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 Receive Shift Register (SCRSR).......................................................................... 14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 14.2.3 Transmit Shift Register (SCTSR) ........................................................................ 14.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 14.2.5 Serial Mode Register (SCSMR)........................................................................... 14.2.6 Serial Control Register (SCSCR)......................................................................... 14.2.7 Serial Status 1 Register (SC1SSR)....................................................................... 14.2.8 Serial Status 2 Register (SC2SSR)....................................................................... 14.2.9 Bit Rate Register (SCBRR).................................................................................. 14.2.10 FIFO Control Register (SCFCR) ......................................................................... 14.2.11 FIFO Data Count Register (SCFDR) ................................................................... 14.2.12 FIFO Error Register (SCFER) ............................................................................. 14.2.13 IrDA Mode Register (SCIMR)............................................................................. 14.3 Operation........................................................................................................................... 557 557 557 559 560 561 562 562 562 563 563 564 567 570 575 578 586 588 589 589 591 Rev. 2.00 Mar 09, 2006 page xxi of xxvi 14.3.1 Overview.............................................................................................................. 14.3.2 Operation in Asynchronous Mode ....................................................................... 14.3.3 Multiprocessor Communication Function............................................................ 14.3.4 Operation in Synchronous Mode ......................................................................... 14.3.5 Use of Transmit/Receive FIFO Buffers ............................................................... 14.3.6 Operation in IrDA Mode...................................................................................... 14.4 SCIF Interrupt Sources and the DMAC ............................................................................ 14.5 Usage Notes ...................................................................................................................... 591 593 605 613 623 626 630 631 Section 15 Serial I/O with FIFO (SIOF) ....................................................................... 637 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.2 Register Configuration...................................................................................................... 15.2.1 Receive Shift Register (SIRSR) ........................................................................... 15.2.2 Receive Data Register (SIRDR) .......................................................................... 15.2.3 Transmit Shift Register (SITSR).......................................................................... 15.2.4 Transmit Data Register (SITDR) ......................................................................... 15.2.5 Serial Control Register (SICTR).......................................................................... 15.2.6 Serial Status Register (SISTR)............................................................................. 15.2.7 Receive Control Data Register (SIRCDR)........................................................... 15.2.8 Transmit Control Data Register (SITCDR) ......................................................... 15.2.9 FIFO Control Register (SIFCR)........................................................................... 15.2.10 FIFO Data Count Register (SIFDR) .................................................................... 15.3 Operation .......................................................................................................................... 15.3.1 Input when TRMD = 0 in SIFCR......................................................................... 15.3.2 Output when TRMD = 0 in SIFCR...................................................................... 15.3.3 Output when TRMD = 1 in SIFCR...................................................................... 15.4 SIOF Interrupt Sources and DMAC.................................................................................. 637 637 639 639 640 641 641 642 645 648 649 649 653 654 654 657 661 663 Section 16 Serial I/O (SIO)............................................................................................... 665 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.2 Register Configuration...................................................................................................... 16.2.1 Receive Shift Register (SIRSR) ........................................................................... 16.2.2 Receive Data Register (SIRDR) .......................................................................... 16.2.3 Transmit Shift Register (SITSR).......................................................................... 16.2.4 Transmit Data Register (SITDR) ......................................................................... 16.2.5 Serial Control Register (SICTR).......................................................................... 16.2.6 Serial Status Register (SISTR)............................................................................. 16.3 Operation .......................................................................................................................... Rev. 2.00 Mar 09, 2006 page xxii of xxvi 665 665 668 669 669 670 670 671 673 675 16.3.1 Input ..................................................................................................................... 675 16.3.2 Output .................................................................................................................. 676 16.4 SIO Interrupt Sources and DMAC .................................................................................... 679 Section 17 16-Bit Timer Pulse Unit (TPU) .................................................................. 681 17.1 Overview........................................................................................................................... 17.1.1 Features ................................................................................................................ 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 Timer Control Register (TCR) ............................................................................. 17.2.2 Timer Mode Register (TMDR) ............................................................................ 17.2.3 Timer I/O Control Register (TIOR) ..................................................................... 17.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 17.2.5 Timer Status Register (TSR)................................................................................ 17.2.6 Timer Counter (TCNT)........................................................................................ 17.2.7 Timer General Register (TGR) ............................................................................ 17.2.8 Timer Start Register (TSTR)................................................................................ 17.2.9 Timer Synchronous Register (TSYR) .................................................................. 17.3 Interface to Bus Master ..................................................................................................... 17.3.1 16-Bit Registers ................................................................................................... 17.3.2 8-Bit Registers ..................................................................................................... 17.4 Operation........................................................................................................................... 17.4.1 Overview.............................................................................................................. 17.4.2 Basic Functions.................................................................................................... 17.4.3 Synchronous Operation........................................................................................ 17.4.4 Buffer Operation .................................................................................................. 17.4.5 PWM Modes ........................................................................................................ 17.4.6 Phase Counting Mode .......................................................................................... 17.5 Interrupts ........................................................................................................................... 17.5.1 Interrupt Sources and Priorities............................................................................ 17.5.2 DMAC Activation................................................................................................ 17.6 Operation Timing .............................................................................................................. 17.6.1 Input/Output Timing ............................................................................................ 17.6.2 Interrupt Signal Timing........................................................................................ 17.7 Usage Notes ...................................................................................................................... 17.8 Usage Notes ...................................................................................................................... 17.8.1 Clearing Flags in TSR0 to TSR2 ......................................................................... 17.8.2 DMA Transfer by TPU0 ...................................................................................... 681 681 684 685 686 687 687 690 692 699 701 704 705 705 706 707 707 707 709 709 710 716 718 721 726 731 731 732 733 733 737 740 750 750 750 Rev. 2.00 Mar 09, 2006 page xxiii of xxvi Section 18 User Debug Interface (H-UDI) .................................................................. 751 18.1 Overview........................................................................................................................... 18.1.1 Features................................................................................................................ 18.1.2 H-UDI Block Diagram......................................................................................... 18.1.3 Pin Configuration................................................................................................. 18.1.4 Register Configuration......................................................................................... 18.2 External Signals ................................................................................................................ 18.2.1 Test Clock (TCK) ................................................................................................ 18.2.2 Test Mode Select (TMS)...................................................................................... 18.2.3 Test Data Input (TDI) .......................................................................................... 18.2.4 Test Data Output (TDO) ...................................................................................... 18.2.5 Test Reset (TRST) ............................................................................................... 18.3 Register Descriptions ........................................................................................................ 18.3.1 Instruction Register (SDIR) ................................................................................. 18.3.2 Status Register (SDSR)........................................................................................ 18.3.3 Data Register (SDDR) ......................................................................................... 18.3.4 Bypass Register (SDBPR) ................................................................................... 18.3.5 Boundary scan register (SDBSR) ........................................................................ 18.3.6 ID code register (SDIDR) .................................................................................... 18.4 Operation .......................................................................................................................... 18.4.1 TAP Controller .................................................................................................... 18.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 18.4.3 H-UDI Reset ........................................................................................................ 18.5 Boundary Scan .................................................................................................................. 18.5.1 Supported Instructions ......................................................................................... 18.5.2 Notes on Use........................................................................................................ 18.6 Usage Notes ...................................................................................................................... 751 751 752 753 753 754 754 754 754 755 755 755 755 757 758 758 758 770 771 771 772 775 775 775 777 777 Section 19 Pin Function Controller (PFC) ................................................................... 781 19.1 Overview........................................................................................................................... 781 19.2 Register Configuration...................................................................................................... 783 19.3 Register Descriptions ........................................................................................................ 783 19.3.1 Port A Control Register (PACR) ......................................................................... 783 19.3.2 Port A I/O Register (PAIOR)............................................................................... 786 19.3.3 Port B Control Registers (PBCR, PBCR2) .......................................................... 787 19.3.4 Port B I/O Register (PBIOR) ............................................................................... 793 Section 20 I/O Ports ............................................................................................................ 795 20.1 Overview........................................................................................................................... 795 20.2 Port A................................................................................................................................ 795 Rev. 2.00 Mar 09, 2006 page xxiv of xxvi 20.2.1 Register Configuration......................................................................................... 20.2.2 Port A Data Register (PADR) .............................................................................. 20.3 Port B ................................................................................................................................ 20.3.1 Register Configuration......................................................................................... 20.3.2 Port B Data Register (PBDR) .............................................................................. 796 796 797 797 798 Section 21 Power-Down Modes ...................................................................................... 21.1 Overview........................................................................................................................... 21.1.1 Power-Down Modes ............................................................................................ 21.1.2 Register ................................................................................................................ 21.2 Register Descriptions ........................................................................................................ 21.2.1 Standby Control Register 1 (SBYCR1) ............................................................... 21.2.2 Standby Control Register 2 (SBYCR2) ............................................................... 21.3 Sleep Mode ....................................................................................................................... 21.3.1 Transition to Sleep Mode..................................................................................... 21.3.2 Canceling Sleep Mode ......................................................................................... 21.4 Standby Mode ................................................................................................................... 21.4.1 Transition to Standby Mode................................................................................. 21.4.2 Canceling Standby Mode ..................................................................................... 21.4.3 Standby Mode Cancellation by NMI Interrupt..................................................... 21.4.4 Clock Pause Function........................................................................................... 21.4.5 Notes on Standby Mode....................................................................................... 21.5 Module Standby Function ................................................................................................. 21.5.1 Transition to Module Standby Function............................................................... 21.5.2 Clearing the Module Standby Function ............................................................... 799 799 799 800 801 801 803 805 805 805 805 805 807 807 808 811 812 812 812 Section 22 Electrical Characteristics.............................................................................. 22.1 Absolute Maximum Ratings.............................................................................................. 22.2 DC Characteristics ............................................................................................................ 22.3 AC Characteristics ............................................................................................................ 22.3.1 Clock Timing ....................................................................................................... 22.3.2 Control Signal Timing ......................................................................................... 22.3.3 Bus Timing........................................................................................................... 22.3.4 Direct Memory Access Controller Timing........................................................... 22.3.5 Free-Running Timer Timing ................................................................................ 22.3.6 Serial Communication Interface Timing.............................................................. 22.3.7 Watchdog Timer Timing...................................................................................... 22.3.8 Serial I/O with FIFO / Serial I/O Timing............................................................. 22.3.9 User Debug Interface Timing............................................................................... 22.3.10 I/O Port Timing.................................................................................................... 813 813 814 816 817 821 823 861 862 864 868 869 872 873 Rev. 2.00 Mar 09, 2006 page xxv of xxvi 22.3.11 Ethernet Controller Timing.................................................................................. 875 22.3.12 STATS, BH, and BUSHiZ Signal Timing ........................................................... 878 22.4 AC Characteristic Test Conditions.................................................................................... 880 Appendix A On-Chip Peripheral Module Registers .................................................. 881 A.1 Addresses .......................................................................................................................... 881 Appendix B Pin States ....................................................................................................... 900 B.1 Pin States in Reset, Power-Down State, and Bus-Released State ..................................... 900 Appendix C Product Lineup ............................................................................................. 904 Appendix D Package Dimensions .................................................................................. 905 Rev. 2.00 Mar 09, 2006 page xxvi of xxvi Section 1 Overview Section 1 Overview 1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Renesas architecture with supporting functions required for an Ethernet system. The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power, and DSP functions have also been enhanced with the implementation of extended Harvard architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. The SH7616 also includes a maximum 4-kbyte cache, for greater CPU processing power when accessing external memory. The SH7616 is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including RAM, timers, a serial communication interface with FIFO (SCIF), interrupt controller (INTC), and I/O ports. To improve the efficiency of frame transmission/reception, the processing power of the DMAC for the Ethernet controller is improved and the FIFO for the DMAC has 2 kbytes. A CAM match signal input function is provided for systems that require multiple MAC addresses. In serial I/O with three channels, one operates with the FIFO for better data processing power when connected to the codec. Rev. 2.00 Mar 09, 2006 page 1 of 906 REJ09B0292-0200 Section 1 Overview Table 1.1 Features Item Specifications CPU • Original Renesas architecture • 32-bit internal architecture • General register machine  Sixteen 32-bit general registers  Six 32-bit control registers (including 3 added for DSP use)  Ten 32-bit system registers • RISC (Reduced Instruction Set Computer) type instruction set  Fixed 16-bit instruction length for improved code efficiency  Load-store architecture (basic operations are executed between registers)  Delayed branch instructions reduce pipeline disruption during branches  C-oriented instruction set • Instruction execution time: One instruction per cycle (16.0 ns/instruction at 62.5 MHz operation) • Address space: Architecture supports 4 Gbytes • On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two to four cycles • Five-stage pipeline Rev. 2.00 Mar 09, 2006 page 2 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications DSP • DSP engine  Multiplier  Arithmetic logic unit (ALU)  Shifter  DSP registers • Multiplier  16 bits × 16 bits → 32 bits  Single-cycle multiplier • DSP registers  Two 40-bit data registers  Six 32-bit data registers  Modulo register (MOD, 32 bits) added to control registers  Repeat counter (RC) added to status register (SR)  Repeat start register (RS, 32 bits) and repeat end register (RE, 32 bits) added to control registers • DSP data bus  Extended Harvard architecture  Simultaneous access to two data buses and one instruction bus • Parallel processing  Maximum of four parallel processes  ALU operations, multiplication, and two loads or stores • Address processors  Two address processors  Address operations to access two memories • DSP data addressing modes  Increment and index  Each with or without modulo addressing • • Repeat control: Zero-overhead repeat (loop) control Instruction set  16-bit length (in case of load or store only)  32-bit length (including ALU operations and multiplication)  Added SuperH microcontroller instructions for accessing DSP registers • Fifth and last pipeline stage is DSP stage Rev. 2.00 Mar 09, 2006 page 3 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications Cache • Mixed instruction/data type cache • Maximum of 4 kbytes • 4-way set-associative type • 16-byte line length • 64 cache tag entries • 16-byte write-back buffer • Selection of write-through or write-back mode for data writes • LRU replacement algorithm • Can also be used as 2-kbyte cache and 2-kbyte RAM (2-way cache mode) • Mixed instruction/data cache, instruction cache, or data cache mode can be set • 1-cycle reads, 2-cycle writes (in write-back mode) • 16 priority levels can be set • On-chip supporting module interrupt vector numbers can be set • 41 internal interrupt sources • The E-DMAC interrupt (EINT) is input to the INTC as the OR of 22 EtherC and E-DMAC interrupt sources (max.). Thus, from the viewpoint of the INTC, there is one EtherC/E-DMAC interrupt source. • Five external interrupt pins (NMI, IRL0 to IRL3) • 15 external interrupt sources (encoded input) can also be selected for pins IRL0 to IRL3 (IRL interrupts) • IRL interrupt vector number setting can also be selected (selection of auto vector or external vector) • Provision for IRQ interrupt setting (low-level, rising-edge, falling-edge, both-edge detection) Interrupt controller (INTC) Rev. 2.00 Mar 09, 2006 page 4 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications User break controller (UBC), 4 channels (A, B, C, D) • Interrupt generation based on independent or sequential conditions for channels A, B, C, D  Three sequential setting patterns: A → B → C → D, B → C → D, C→D • Settable break conditions: Address, data (channels C and D only), bus master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write, operand cycle (byte/word/longword) • User break interrupt generated on occurrence of break condition • Processing can be stopped before or after instruction execution in instruction fetch cycle • Break with specification of number of executions (channels C and D only) Settable number of executions: max. 2 • 12 – 1 (4095) PC trace function Branch source/branch destination can be traced in branch instruction fetch (max. 8 addresses (4 pairs)) Rev. 2.00 Mar 09, 2006 page 5 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications Bus state controller • (BSC) Address space divided into five areas (CS0 to CS4, max. linear 32 Mbytes each)  Memory types such as DRAM, synchronous DRAM, burst ROM, can be specified for each area  Two synchronous DRAM spaces (CS2, CS3); CS3 also supports DRAM  Bus width (8, 16, 32 bits) can be selected for each area  Wait state insertion control for each area  Control signal output for each area  Endian can be set for CS2 and CS4 • Cache  Cache area/cache-through area selection by access address  Selection of write-through or write-back mode • Refresh functions  CAS-before-RAS refreshing (auto refreshing) or self-refreshing  Refresh interval settable by means of refresh counter and clock select setting  Concentrated refreshing according to refresh count setting (1, 2, 4, 6, 8)  Refresh request output possible (REFOUT) • Direct DRAM interface  Multiplexed row address/column address output  Fast page mode burst transfer and continuous access when reading  EDO mode  TP cycle generation to secure RAS precharge time • Direct synchronous DRAM interface  Multiplexed row address/column address output  Bank-active mode (valid for CS3 only)  Selection of burst read/single write mode or burst read/burst write mode • Bus arbitration (BRLS, BGR) • Refresh counter can be used as interval timer  Interrupt request generated on compare match (CMI interrupt request signal) Rev. 2.00 Mar 09, 2006 page 6 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications Direct memory access controller (DMAC), 2 channels • 4-Gbyte address space, maximum 16M (16,777,216) transfers • Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length • Parallel execution of CPU instruction processing and DMA operation possible in case of cache hit • Selection of dual address or single address mode  Single address (data transfer rate of one transfer unit in one bus cycle)  Dual address (data transfer rate of one transfer unit in two bus cycles)  When synchronous DRAM is connected, 16-byte continuous read → continuous write transfer is possible (dual) • When SDRAM is connected, clocked single-address transfer is possible at rates up to 31.25 MHz • Cycle stealing or burst transfer • Relative channel priorities can be set (fixed mode/round robin mode) • DMA transfer is possible for the following devices:  External memory, on-chip memory, on-chip supporting modules (excluding DMAC, BSC, UBC, cache, E-DMAC, EtherC) On-chip RAM Ethernet controller direct memory access controller (E-DMAC), 2 channels • External requests, DMA transfer requests from on-chip supporting modules, auto requests • Interrupt request (DEIn) can be issued to CPU at end of data transfer • DACK used for DREQ sampling (however, there is always one overrun as there is one acceptance before first DACK) • 4-kbyte X-RAM • 4-kbyte Y-RAM • Transfer possible between EtherC and external memory/on-chip memory • 16-byte burst transfer possible • Single address transfer • Chain block transfer • 32-bit transfer data width • 4-Gbyte address space • Data transfer possible from across byte boundaries in transmission • Each transmit and receive FIFO includes 2 kbytes Rev. 2.00 Mar 09, 2006 page 7 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications Ethernet controller (EtherC) • MAC (Media Access Control) functions  Data frame assembly/disassembly (IEEE802.3-compliant frames)  CSMA/CD link management (collision avoidance, processing in case of collision)  CRC processing  Supports full-duplex transmission/reception  Transmitting and receiving short and long packets • Compatible with MII (Media Independent Interface) standard  Converts 8-bit stream data from MAC level to MII nibble stream (4 bits)  Station management (STA) functions  18 TTL-level signals Serial communication interface with FIFO (SCIF), 2 channels •  Variable transfer rate: 10/100 Mbps Magic Packet™* (with WOL (Wake On LAN) output) • CAM match signal input function • Asynchronous mode  Data length: 7 or 8 bits  Stop bit length: 1 or 2  Parity: Even, odd, or none  Receive error detection: Parity errors, framing errors, overrun errors  Break detection • Synchronous mode  One serial communication format (8-bit data length)  Receive error detection: Overrun errors • • IrDA mode (conforming to IrDA 1.0) Simultaneous transmission/reception (full-duplex) capability  Half-duplex communication used for IrDA communication • Built-in dedicated baud rate generator allows selection of bit rate • Built-in 16-stage transmit and receive FIFOs enable high-speed, continuous communication • Internal or external (SCK) transmit/receive clock source Note: * Magic Packet is a registered trademark of Advanced Micro Devices, Inc. Rev. 2.00 Mar 09, 2006 page 8 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications Serial communication interface with FIFO (SCIF), 2 channels • Four interrupt sources  Transmit FIFO data empty  Break  Receive FIFO data full  Receive error • Built-in modem control functions (RTS, CTS) • Detection of transmit and receive FIFO register data quantity and number of receive FIFO register transmit data errors • Timeout error (DR) can be detected during reception Serial I/O with FIFO • (SIOF) Serial I/O (SIO), 2 channels Full-duplex operation (independent transmit and receive registers, and independent transmit and receive clocks) • Transmit and receive FIFO for primary data/transmit and receive buffer for control data (enabling continuous transmission/reception) • Interval transfer mode and continuous transfer mode • Choice of 8- or 16-bit data length • Data transfer communication by means of polling or interrupts • Choice of MSB- or LSB-first transfer for data I/O • Full-duplex operation (independent transmit and receive registers, and independent transmit and receive clocks) • Transmit/receive ports with double-buffer structure (enabling continuous transmission/reception) • Interval transfer mode and continuous transfer mode • Choice of 8- or 16-bit data length • Data transfer communication by means of polling or interrupts • MSB-first transfer between SIO and data I/O Rev. 2.00 Mar 09, 2006 page 9 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications User debug interface (H-UDI) • Conforms to IEEE1149.1 standard  Five test signals (TCK, TDI, TDO, TMS, TRST)  TAP controller  Instruction register  Data register  Bypass register • Test mode that conforms to the IEEE1149.1 standard  Standard instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST  Optional instructions: CLAMP, HIGHZ, and IDCODE • H-UDI interrupt  H-UDI interrupt request to INTC Timer pulse unit (TPU), 3 channels • Reset hold • Maximum 8-pulse input/output • Total of eight timer general registers (TGR) (four for channel 0, two each for channels 1 and 2)  Waveform output by compare match: Selection of 0, 1, or toggle output  Input capture function: Selection of rising-edge, falling-edge, or bothedge detection  Counter clear operation: Counter clearing possible by compare match or input capture  Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously; simultaneous clearing by compare match and input capture possible; simultaneous register input/output possible by counter synchronous operation  PWM mode: Any PWM output duty can be set; maximum 7-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channel 0  Input capture register double-buffering possible  Automatic rewriting of output compare register possible • Phase counting mode settable independently for channels 1 and 2  Two-phase encoder pulse up/down-count possible • 13 interrupt sources  For channel 0, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently  For channels 1 and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently Rev. 2.00 Mar 09, 2006 page 10 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications 16-bit free-running timer (FRT), 1 channel • Choice of four counter input clocks  Three internal clocks (Pφ/8, Pφ/32, Pφ/128)  External clock (enabling external event counting) • Two independent comparators (allowing generation of two waveform outputs) • Input capture (choice of rising edge or falling edge) • Counter clear specification  Counter value can be cleared by compare match A • Four interrupt sources  Two compare match sources (OCIA, OCIB)  One input capture source (ICI)  One overflow source (OVI) Watchdog timer (WDT), 1 channel Clock pulse generator (CPG) • Can be switched between watchdog timer mode and interval timer mode • Internal reset, external signal (WDTOVF), or interrupt generated on count overflow • Used when standby mode is cleared or the clock frequency is changed, and in clock pause mode • Selection of eight counter input clocks • Built-in clock pulse generator • Selection of crystal or external clock as clock source • Built-in clock-multiplication PLL circuits • Built-in PLL circuit for phase synchronization between external clock and internal clock • CPU/DSP core clock (Iφ), peripheral module clock (Pφ), and external interface clock (Eφ) frequencies can be scaled independently Rev. 2.00 Mar 09, 2006 page 11 of 906 REJ09B0292-0200 Section 1 Overview Item Specifications System controller (SYSC) • Selection of seven operating mode settings, three power-down modes • Operating modes  Control the method of clock generation (PLL ON/OFF) and clock division ratio • Power-down mode  Sleep mode: CPU functions halted  Standby mode: All functions halted  Module standby function: Operation of FRT, SCIF, DMAC, UBC, DSP, TPU, and SIO on-chip supporting modules is halted selectively I/O ports • 29 input/output ports Rev. 2.00 Mar 09, 2006 page 12 of 906 REJ09B0292-0200 Section 1 Overview Internal address bus 16-bit internal data bus Internal address bus 16-bit internal data bus Cache address bus 32-bit cache data bus Block Diagram CPU Serial I/O with FIFO Interrupt controller DSP User debug interface X-RAM Serial I/O Serial communication interface with FIFO Y-RAM Timer pulse unit Cache controller User break controller Free-running timer Watchdog timer Bus state controller Direct memory access controller Clock pulse generator Ethernet controller 16-bit peripheral data bus System controller Peripheral address bus Ethernet controller direct memory access controller Internal address bus Cache address array/data array 32-bit internal data bus 1.2 I/O ports External bus interface Figure 1.1 Block Diagram of SH7616 Rev. 2.00 Mar 09, 2006 page 13 of 906 REJ09B0292-0200 Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PB11/SRS2/CTS/STATS0 PVCC PB12/SRCK2/RTS/STATS1 PB13/TXD1 PB14/RXD1 PB15/SCK1 VSS VSS BGR VCC VCC BRLS DACK0 DACK1 DREQ0 DREQ1 BH BUSHiZ CS4 CS3 CS2 CS1 CS0 RD/WR VCC BS VSS REFOUT RD CKE CAS0 CAS1 CAS2 CAS3 DQMLL/WE0 DQMLU/WE1 DQMUL/WE2 DQMUU/WE3 CAS/OE RAS VCC WAIT VSS VSS VSS A24 VCC VCC A23 A22 A21 A20 Figure 1.2 shows the pin arrangement. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PLQP0208KA-A (Top view) A19 A18 A17 VSS A16 VCC A15 A14 A13 A12 A11 A10 A9 VSS A8 VCC A7 A6 A5 A4 A3 A2 A1 VCC A0 VSS VSS D31 VCC D30 D29 D28 D27 D26 D25 VSS D24 VCC VCC D23 D22 D21 D20 VSS VSS D19 VCC D18 D17 D16 D15 D14 IRL3 IRL2 IRL1 IRL0 NMI ASEMODE* VSS RES PLLVSS PLLCAP2 PLLCAP1 PLLVCC MD4 MD3 MD2 MD1 MD0 VCC EXTAL VSS XTAL VCC CKIO CKPREQ/CKM CKPACK VSS IVECF TDO TDI TCK TMS TRST VCC D0 VSS D1 D2 D3 D4 D5 D6 VCC D7 D8 VSS D9 D10 D11 D12 VCC D13 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PVSS TIOCA1/SRXD2/PB10 TCLKC/TIOCB1/STCK2/PB9 TIOCA2/STS2/PB8 TCLKD/TIOCB2/STXD2/PB7 SCK2/SRCK1/PB6 RXD2/SRS1/PB5 TXD2/SRXD1/PB4 TIOCA0/STCK1/PB3 TIOCB0/STS1/PB2 PVCC TCLKA/TIOCC0/STXD1/PB1 PVSS WOL/TCLKB/TIOCD0/PB0 SRCK0/PA13 SRS0/PA12 SRXD0/PA11 STCK0/PA10 STS0/PA9 STXD0/PA8 WDTOVF/PA7 FTCI/PA6 PVCC FTI/PA5 PVSS FTOA/PA4 FTOB/CKPO LNKSTA/PA2 EXOUT/PA1 PA0/CAMSEN RXER RXDV COL CRS PVSS RXCLK PVCC ERXD0 ERXD1 ERXD2 ERXD3 MDIO MDC PVCC TXCLK PVSS TXEN ETXD0 ETXD1 ETXD2 ETXD3 TXER Body size Height Pin pitch 28 × 28 (mm) 1.7 (mm) 0.5 (mm) Note: * When doing debugging using the E10A emulator, this pin is used for mode switching. It should be connected to Vss when using the E10A emulator and connected to Vcc when using a normal user system. Figure 1.2 SH7616 Pin Arrangement (PLQP0208KA-A) Rev. 2.00 Mar 09, 2006 page 14 of 906 REJ09B0292-0200 Section 1 Overview 1.3.2 Table 1.2 Pin Functions Pin Functions Type Symbol I/O Name Function Power VCC Input Power For connection to the power supply. Connect all VCC pins to the system power supply. The chip will not operate if there are any open pins VSS Input Ground For connection to ground. Connect all VSS pins to the system ground. The chip will not operate if there are any open pins PVCC Input I/O circuit power Power supply for the I/O circuits PVSS Input I/O circuit ground Ground for the I/O circuits XTAL Output Crystal input/ output pin For connection to a crystal resonator EXTAL Input CKIO I/O System clock input/output pin Used as the external clock input or internal clock output pin CKPREQ/ CKM Input Clock pause request input Used as the clock pause request pin for changing the frequency of the clock input from the CKIO pin, or halting the clock CKPACK Output Clock pause acknowledge signal Indicates that the chip is in the clock pause state (standby state) internally CKPO Output On-chip peripheral clock (Pφ) output Outputs the on-chip peripheral clock (Pφ) PLLCAP1 Input PLL capacitance Connects capacitance for operation of connection pins PLL circuit 1 PLLCAP2 Input Connects capacitance for operation of PLL circuit 2 PLLVCC Input PLL power PLL oscillator power supply PLLVSS Input PLL ground PLL oscillator ground Clock For connection to a crystal resonator, or used as external clock input pin Rev. 2.00 Mar 09, 2006 page 15 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O Name Function System control RES Input Reset When RES = 0 and NMI = 1, the chip enters the power-on reset state. When RES = 0 and NMI = 0, the chip enters the manual reset state WDTOVF Output Watchdog timer overflow Counter overflow signal output in watchdog timer mode BGR Output Bus grant Indicates that the bus has been released to an external device. The device that output the BRLS signal recognizes that the bus has been acquired when it receives the BGR signal BRLS Input Bus release Driven low when an external device requests release of the bus Operating mode MD0–MD4 Input Mode setting The operating mode is specified by the levels at these pins Interrupts NMI Input Nonmaskable interrupt Inputs the nonmaskable interrupt request signal IRL3–IRL0 Input External interrupt request input 0 to 3 These pins input maskable interrupt request signals IVECF Output Interrupt vector fetch cycle Indicates an external vector read cycle BS Output Bus cycle start Signal indicating the start of a bus cycle Bus control Asserted every data cycle in burst transfer CS4–CS0 Output Chip select 0 to 4 Chip select signals indicating the area being accessed WAIT Input Wait Wait state request signal RD Output Read Strobe signal indicating a read cycle RAS Output Row address strobe DRAM/synchronous DRAM RAS signal Rev. 2.00 Mar 09, 2006 page 16 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O Name Function Bus control CAS Output Column address strobe Synchronous DRAM CAS signal OE Output Output enable EDO DRAM output enable signal Used in access in RAS down mode DQMUU/ WE3 Output Highest byte access SRAM/synchronous DRAM highest byte select signal DQMUL/ WE2 Output Second byte access SRAM/synchronous DRAM second byte select signal DQMLU/ WE1 Output Third byte access SRAM/synchronous DRAM third byte select signal DQMLL/ WE0 Output Lowest byte access SRAM/synchronous DRAM lowest byte select signal CAS3 Output Column address strobe 3 DRAM highest byte select signal CAS2 Output Column address strobe 2 DRAM second byte select signal CAS1 Output Column address strobe 1 DRAM third byte select signal CAS0 Output Column address strobe 0 DRAM lowest byte select signal CKE Output Clock enable Synchronous DRAM clock enable signal REFOUT Output Refresh out Signal requesting refresh execution when the bus is released RD/WR Output Read/write DRAM/synchronous DRAM write signal BUSHiZ Input Bus high impedance Signal used in combination with WAIT signal to place bus and strobe signals in the high-impedance state without the ending bus cycle BH Output Burst hint Asserted at the start of a DMA burst, negated one bus cycle before the end of the burst STATS0, 1 Output Status CPU, DMAC, and E-DMAC status information Rev. 2.00 Mar 09, 2006 page 17 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O Name Function Bus control A24–A0 Output Address bus Address output D31–D0 I/O Data bus Data input/output TCK Input Test clock Test clock input TMS Input Test mode select Test mode select input signal TDI Input Test data input Serial data input TDO Output Test data output Serial data output TRST Input H-UDI Ethernet controller (EtherC) Test reset Test reset input signal ASEMODE* Input ASE mode input ASE mode/user mode select signal TX-CLK Input Transmitter clock TX-EN, ETXD0–3, TX-ER timing reference signal RX-CLK Input Receive clock RX-DV, ERXD0–3, RX-ER timing reference signal TX-EN Output Transmit enable Signal indicating that transmit data on ETXD0–3 is ready ETXD0–3 Output Transmit data 0–3 4-bit receive data TX-ER Output Transmit error Signal sending error status to another port RX-DV Input Receive data enable Indicates that enable receive data on ERXD0–3 exist ERXD0–3 Input Receive data 0–3 4-bit receive data RX-ER Input Receive error Reports error state that occurred during transfer of frame data CRS Input Carrier sense Carrier detection notification signal COL Input Collision Collision detection signal MDC Output Management data clock Reference clock signal for information transfer by MDIO MDIO I/O Management Bidirectional signal for exchanging data input/output management information between STA and PHY Note: * When carrying out debugging using the E10A emulator, this pin is used for mode switching. It should be connected to VSS when using the E10A emulator and connected to VCC when using a normal user system. When a boundary scan test is performed with the H-UDI, user mode must be used. A boundary scan test cannot be performed in ASE mode. Rev. 2.00 Mar 09, 2006 page 18 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O Name Function Ethernet controller (EtherC) LNKSTA Input Link status Link status input from PHY EXOUT Output General-purpose General-purpose external output pin external output WOL Output Wake on LAN Signal indicating detection of a Magic Packet CAMSEN Input CAM sense CAM sense signal DACK0, 1 Output DMAC channel 0, 1 acknowledge These pins output receiving a DMA transfer request to an external device DREQ0, 1 Input DMAC channel 0, 1 request Pins that input DMA transfer requests from an external device Output Transmit data output channel 1, 2 SCIF channel 1 and 2 transmit data output pins Input Receive data output channel 1, 2 SCIF channel 1 and 2 receive data input pins SCK1, 2 I/O Serial clock input/output channel 1, 2 SCIF clock input/output pins RTS Output Transmit request SCIF channel 1 transmit request output pin CTS Input Transmit enable SCIF channel 1 transmit enable input pin TCLKA TCLKB TCLKC TCLKD Input TPU timer clock input A, B, C, D Pins that input an external clock to the TPU counter TIOCA0 TIOCB0 TIOCC0 TIOCD0 I/O TPU input capture/output compare (channel 0) Channel 0 input capture input/ output compare output/PWM output pins TIOCA1 TIOCB1 I/O TPU input capture/output compare (channel 1) Channel 1 input capture input/ output compare output/PWM output pins Direct memory access controller (DMAC) Serial comTXD1, 2 munication interface with FIFO (SCIF) RXD1, 2 Timer pulse unit (TPU) Rev. 2.00 Mar 09, 2006 page 19 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O Name Function Timer pulse unit (TPU) TIOCA2 TIOCB2 I/O TPU input capture/output compare (channel 2) Channel 2 input capture input/output compare output/PWM output pins 16-bit free-running timer (FRT) FTCI Input Counter clock input FRC counter clock input pin FTOA Output Output compare A output Output compare A output pin FTOB Output Output compare B output Output compare B output pin FTI Input Input capture input Input capture input pin SRXD0 Input Serial receive data input 0 Serial receive data input ports SRCK0 Input Serial receive clock input 0 Serial receive clock ports SRS0 Input Serial receive synchronization clock input 0 Serial receive synchronization input ports STXD0 Output Serial transmit data output 0 Serial data output ports STCK0 Input Serial transmit clock input 0 Serial transmit clock ports STS0 I/O Serial transmit Serial transmit synchronization synchronization input/output ports clock input/output 0 SRXD1, 2 Input Serial receive data input 1, 2 Serial receive data input ports SRCK1, 2 Input Serial receive clock input 1, 2 Serial receive clock ports SRS1, 2 Input Serial receive synchronization input 1, 2 Serial receive synchronization input ports STXD1, 2 Output Serial transmit data output 1, 2 Serial data output ports STCK1, 2 Input Serial transmit clock input 1, 2 Serial transmit clock ports STS1, 2 I/O Serial transmit synchronization input/output 1, 2 Serial transmit synchronization input/output ports Serial I/O with FIFO (SIOF) Serial I/O (SIO) Rev. 2.00 Mar 09, 2006 page 20 of 906 REJ09B0292-0200 Section 1 Overview Type Symbol I/O ports PA0–PA13* I/O I/O Name Function General port General input/output port pins Input or output can be specified bit by bit PB0–PB15 I/O General port General input/output port pins Input or output can be specified bit by bit Note: * PA3 cannot be used; CKPO is valid instead. 1.3.3 Pin Multiplexing Table 1.3 Pin Multiplexing No. Function 1 12 PLLVCC 9 PLLVSS 11 PLLCAP1 Function 2 Function 3 Function 4 Type Clocks 10 PLLCAP2 19 EXTAL 21 XTAL 23 CKIO 24 CKPREQ/CKM 25 CKPACK 9 pins 8 RES System control 13 MD4 14 MD3 15 MD2 16 MD1 17 MD0 6 pins 5 NMI Interrupts 1 IRL3 2 IRL2 3 IRL1 4 IRL0 27 IVECF 6 pins Rev. 2.00 Mar 09, 2006 page 21 of 906 REJ09B0292-0200 Section 1 Overview No. Function 1 131 BS 138 CS4 137 CS3 136 CS2 135 CS1 134 CS0 148 BGR 145 BRLS 115 WAIT 128 RD 117 RAS 118 CAS/OE 119 DQMUU/WE3 120 DQMUL/WE2 121 DQMLU/WE1 122 DQMLL/WE0 123 CAS3 124 CAS2 125 CAS1 126 CAS0 127 CKE 129 REFOUT 133 RD/WR 139 BUSHiZ 140 BH Function 2 Rev. 2.00 Mar 09, 2006 page 22 of 906 REJ09B0292-0200 Function 3 Function 4 Type Bus control 25 pins Section 1 Overview No. Function 1 111 A24 108 A23 107 A22 106 A21 105 A20 104 A19 103 A18 102 A17 100 A16 98 A15 97 A14 96 A13 95 A12 94 A11 93 A10 92 A9 90 A8 88 A7 87 A6 86 A5 85 A4 84 A3 83 A2 82 A1 80 A0 Function 2 Function 3 Function 4 Type Address bus 25 pins Rev. 2.00 Mar 09, 2006 page 23 of 906 REJ09B0292-0200 Section 1 Overview No. Function 1 77 D31 75 D30 74 D29 73 D28 72 D27 71 D26 70 D25 68 D24 65 D23 64 D22 63 D21 62 D20 59 D19 57 D18 56 D17 55 D16 54 D15 53 D14 51 D13 49 D12 48 D11 47 D10 46 D9 44 D8 43 D7 41 D6 40 D5 39 D4 38 D3 37 D2 36 D1 34 D0 Function 2 Rev. 2.00 Mar 09, 2006 page 24 of 906 REJ09B0292-0200 Function 3 Function 4 Type Data bus 32 pins Section 1 Overview No. Function 1 Function 2 Function 3 Function 4 Type 30 TCK 31 TMS 29 TDI 28 TDO 32 TRST 6 ASEMODE* 6 pins 201 TX-CLK EtherC 192 RX-CLK 203 TX-EN 207 ETXD3 206 ETXD2 205 ETXD1 204 ETXD0 208 TX-ER 188 RX-DV 197 ERXD3 196 ERXD2 195 ERXD1 194 ERXD0 187 RX-ER 190 CRS 189 COL 199 MDC 198 MDIO 18 pins 143 DACK1 DMAC 144 DACK0 141 DREQ1 142 DREQ0 H-UDI 5 V I/O compatibility 4 pins Note: * When carrying out debugging using the E10A emulator, this pin is used for mode switching. It should be connected to VSS when using the E10A emulator (ASE mode). When using the chip in the normal user system, and not using the E10A emulator (user mode), connect this pin to VCC. When a boundary scan test is performed with the H-UDI, user mode must be used. A boundary scan test cannot be performed in ASE mode. Rev. 2.00 Mar 09, 2006 page 25 of 906 REJ09B0292-0200 Section 1 Overview Function 2 [01]* Function 3 [10]* Function 4 [11]* No. Function 1 [00]* 151 PB15 SCK1 Port B 152 PB14 RXD1 SCIF, SIO, TPU 153 PB13 TXD1 154 PB12 SRCK2 RTS STATS1 156 PB11 SRS2 CTS STATS0 158 PB10 SRXD2 TIOCA1 159 PB9 STCK2 TIOCB1/TCLKC 160 PB8 STS2 TIOCA2 161 PB7 STXD2 TIOCB2/TCLKD 162 PB6 SRCK1 SCK2 163 PB5 SRS1 RXD2 Type 5 V I/O compatibility 164 PB4 SRXD1 TXD2 165 PB3 STCK1 TIOCA0 166 PB2 STS1 TIOCB0 168 PB1 STXD1 TIOCC0/TCLKA 170 PB0 171 PA13 SRCK0 172 PA12 SRS0 SIOF, FRT, WDT, 173 PA11 SRXD0 EtherC 174 PA10 STCK0 5 V I/O compatibility 175 PA9 STS0 176 PA8 STXD0 177 WDTOVF PA7 178 PA6 FTCI 180 PA5 FTI 182 PA4 FTOA 183 CKPO FTOB 184 PA2 LNKSTA 185 PA1 EXOUT 186 PA0 CAMSEN TIOCD0/TCLKB WOL 16 pins Port A 14 pins Note: * Figures in square brackets indicate the settings of the mode bits (MD0, MD1) in the PFC in order to select the multiplex functions in port A [0:13] and port B [0:15]. WDTOVF: In a reset, this pin becomes an output pin. Rev. 2.00 Mar 09, 2006 page 26 of 906 REJ09B0292-0200 Section 1 Overview When used for general input/output, attention must be paid to the polarity of this pin. 1.4 Processing States State Transitions: The CPU has five processing states: the reset state, exception handling state, bus-released state, program execution state, and power-down state. Figure 1.3 shows the state transitions. From any state when RES = 0 and NMI = 1 From any state when RES = 0 and NMI = 0 RST = 0, NMI = 0 Power-on reset state Manual reset state RST = 0, NMI = 1 RST = 1, NMI = 1 Interrupt or DMA address error RST = 1, NMI = 0 Reset states Exception-handling state NMI interrupt Bus request cleared Bus request Exception Bus-released state Bus request received Bus request cleared End of exception handling CKPREQ = 1* Program execution state Bus request received Bus request cleared SLEEP instruction (SBY = 0) MSTP bit cleared MSTP bit set Sleep mode SBY bit set and CKPREQ = 0* SLEEP instruction (SBY = 1) Standby mode Module standby Power-down state Note: * clock pause function Figure 1.3 Processing State Transitions Rev. 2.00 Mar 09, 2006 page 27 of 906 REJ09B0292-0200 Section 1 Overview • Reset State In this state, the CPU is reset. The reset state is entered when the RES pin goes low. The power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if the NMI pin is low. • Exception Handling State The exception handling state is a transient state that occurs when the CPU alters the normal programming flow dues to a reset, interrupt, or other exception handling source. In the case of a reset, the CPU fetches the execution start address as the initial value of the program counter (PC) from the exception vector table, and the initial value of the stack pointer (SP), stores these values, branches to the start address, and begins program execution at that address. In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register (SR) in the stack area. It fetches the start address of the exception service routine from the exception vector table, branches to that address, and begins program execution. Subsequently, the processing state is the program execution state. • Program Execution State In the program execution state the CPU executes program instructions in normal sequence. • Power-Down State In the power-down state the CPU stops operating to conserve power. The power-down state is entered by executing a SLEEP instruction. The power-down state includes two modes—sleep mode and standby mode—and a module standby function. • Bus-Released State In the bus-released state, the CPU releases the bus to a device that has requested it. Power-Down State: In addition to the normal program execution state, another CPU processing state called the power-down state is provided. In this state, CPU operation is halted and power consumption is reduced. The power-down state includes two modes—sleep mode and standby mode—and a module standby function. • Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit (SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is retained. The functions of the on-chip supporting modules do not stop. Rev. 2.00 Mar 09, 2006 page 28 of 906 REJ09B0292-0200 Section 1 Overview • Standby Mode A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to 1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop. When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0. Also, the cache should be turned off before entering this mode. The contents of the cache and on-chip RAM are not retained in this mode. Standby mode is exited by means of a reset or an external NMI interrupt. When standby mode is exited, the normal program execution state is entered via the exception handling state after the elapse of the oscillation settling time. If a transition is made to standby mode using the clock pause function, it is possible to change the frequency of the CKIO pin input clock, or to stop the clock itself. When SBY in SBYCR1 is set to 1 and a low level is applied to the CKPREQ/CKM pin, a transition is made to standby mode and a low level is output from the CKPACK pin. The clock can then be stopped, or its frequency changed. On-chip supporting module states and pin states are the same as in the normal standby mode entered by means of the SLEEP instruction. A transition to the program execution state is made by applying a high level to the CKPREQ/CKM pin. In this mode the oscillator is halted, greatly reducing power consumption. • Module Standby Function A module standby function is provided for the following on-chip supporting modules: the direct memory access controller (DMAC), DSP, 16-bit free-running timer (FRT), serial communication interface with FIFO (SCIF), serial I/O with FIFO (SIOF), serial I/O (SIO), user break controller (UBC), and timer pulse unit (TPU). A module standby function is not supported for the Ethernet controller (EtherC) or the Ethernet direct memory access controller (E-DMAC). Setting one of module stop bits 11 to 3 and 1 (MSTP11 to MSTP3, MSTP1) to 1 in the standby control register (SBYCR1/2) stops the clock supply to the corresponding on-chip supporting module. Use of this function enables power consumption to be reduced. The module standby function is cleared by clearing the corresponding MSTP bit to 0. DSP instructions must not be used when the DSP has been placed in the module standby state. When using the DMAC module standby function, the direct memory access controller’s DMA master enable bit should be cleared to 0. Rev. 2.00 Mar 09, 2006 page 29 of 906 REJ09B0292-0200 Section 1 Overview Table 1.4 Power-Down State State Mode Entering Conditions Clock Sleep mode Operating Executing SLEEP instruction while SBY bit is cleared in SBYCR1 Standby mode Executing SLEEP instruction while SBY bit is set in SBYCR1 Module standby function Setting Operating MSTP bit corresponding to individual module Halted CPU On-chip Supporting Modules Halted Operating CPU Registers On-Chip Cache or On-Chip RAM Exiting Conditions Held Held 1. Interrupt 2. DMA address error 3. Power-on reset 4. Manual reset Halted Halted and initialized*1 Operating (DSP halted) Clock supply Held to specified module halted, module initialized*2 Held Undefined 1. NMI interrupt 2. Power-on reset 3. Manual reset Held 1. Clearing MSTP bit 2. Power-on reset 3. Manual reset Notes: 1. Depends on individual supporting module or pin. 2. DMAC and DSP registers and specified module interrupt vectors retain their set values. Rev. 2.00 Mar 09, 2006 page 30 of 906 REJ09B0292-0200 Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, six 32-bit control registers and ten 32bit system registers. This chip is upwardly compatible with the SH-1, SH-2 on the object code level. For this reason, several registers have been added to the previous SuperH microcontroller registers. The added registers are the three control registers: repeat start register (RS), repeat end register (RE), and modulo register (MOD) and the six system registers: DSP status register (DSR), and A0, A1, X0, X1, Y0 and Y1 among the DSP data registers. The general registers are used in the same manner as the SH-1, SH-2 with regard to SuperH microcontroller-type instructions. With regard to DSP type instructions, they are used as address and index registers for accessing memory. 2.1.1 General Registers There are 16 general registers (Rn) numbered R0–R15, which are 32 bits in length. General registers are used for data processing and address calculation. With SuperH microcomputer type instructions, R0 is also used as an index register. Several instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. With DSP type instructions, eight of the 16 general registers are used for the addressing of X, Y data memory and data memory (single data) using the I bus. R4, R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X index register (Ix). R6, R7 are used as a Y address register (Ay) for Y memory accesses, and R9 is used as a Y index register (Iy). R2, R3, R4, R5 are used as a single data address register (As) for accessing single data using the I bus, and R8 is used as a single data index register (Is). DSP type instructions can simultaneously access X and Y data memory. There are two groups of address pointers for designating X and Y data memory addresses. Figure 2.1 shows the general registers. Rev. 2.00 Mar 09, 2006 page 31 of 906 REJ09B0292-0200 Section 2 CPU 31 0 R0*1 R1 R2, [As]*3 R3, [As]*3 R4, [As, Ax]*3 R5, [As, Ax]*3 R6, [Ay]*3 R7, [Ay]*3 R8, [Ix, Is]*3 R9, [Iy]*3 R10 R11 R12 R13 R14 R15, SP *2 Notes: 1. R0 also functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, only the R0 functions as a source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. 3. Used as memory address registers, memory index registers with DSP type instructions. Figure 2.1 General Register Configuration With the assembler, symbol names are used for R2, R3 ... R9. If it is wished to use a name that makes clear the role of a register for DSP type instructions, a different register name (alias) can be used. This is written in the following manner for the assembler. Ix: .REG (R8) Rev. 2.00 Mar 09, 2006 page 32 of 906 REJ09B0292-0200 Section 2 CPU The name Ix is an alias for R8. The other aliases are assigned as follows: Ax0: .REG (R4) Ax1: .REG (R5) Ix: .REG (R8) Ay0: .REG (R6) Ay1: .REG (R7) Iy: .REG (R9) As0: .REG (R4) defined when an alias is required for single data transfer As1: .REG (R5) defined when an alias is required for single data transfer As2: .REG (R2) defined when an alias is required for single data transfer As3: .REG (R3) defined when an alias is required for single data transfer Is: .REG (R8) defined when an alias is required for single data transfer 2.1.2 Control Registers The six 32-bit control registers consist of the status register (SR), repeat start register (RS), repeat end register (RE), global base register (GBR), vector base register (VBR), and modulo register (MOD). The SR register indicates processing states. The GBR register functions as a base address for the indirect GBR addressing mode, and is used for such as on-chip peripheral module register data transfers. The VBR register functions as the base address of the exception processing vector area (including interrupts). The RS and RE registers are used for program repeat (loop) control. The repeat count is designated in the SR register repeat counter (RC), the repeat start address in the RS register, and the repeat end address in the RE register. However, note that the address values stored in the RS and RE registers are not necessarily always the same as the physical start and end address values of the repeat. The MOD register is used for modulo addressing to buffer the repeat data. The modulo addressing designation is made by DMX or DMY, the modulo end address (ME) is designated in the upper 16 bits of the MOD register, and the modulo start address (MS) is designated in the lower 16 bits. Note that the DMX and DMY bits cannot simultaneously designate modulo addressing. Modulo addressing is possible with X and Y data transfer instructions (MOVX, MOVY). It is not possible with single data transfer instructions (MOVS). Rev. 2.00 Mar 09, 2006 page 33 of 906 REJ09B0292-0200 Section 2 CPU Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits. Status register (SR) 31 28 27 16 15 12 11 10 9 8 7 4 3 2 1 0 0000 RC 0000 DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T Repeat start register (RS) 31 0 RS Repeat end register (RE) 31 0 RE Global base register (GBR) 31 0 GBR Vector base register (VBR) 31 0 VBR Modulo register (MOD) 31 ME 16 15 0 MS ME: Modulo end address MS: Modulo start address Figure 2.2 Control Register Configuration Rev. 2.00 Mar 09, 2006 page 34 of 906 REJ09B0292-0200 Section 2 CPU Table 2.1 SR Register Bits Bit Name (Abbreviation) Function 27–16 Repeat counter (RC) Designate the repeat count (2–4095) for repeat (loop) control 11 Y pointer usage modulo addressing designation (DMY) 1: modulo addressing mode becomes valid for Y memory address pointer, Ay (R6, R7) 10 X pointer usage modulo addressing designation (DMX) 1: modulo addressing mode becomes valid for X memory address pointer, Ax (R4, R5) 9 M bit Used by the DIV0S/U, DIV1 instructions 8 Q bit Used by the DIV0S/U, DIV1 instructions 7–4 Interrupt request mask (I3–I0) Indicate the receive level of an interrupt request (0 to 15) 3–2 Repeat flags (RF1, RF0) Used in zero overhead repeat (loop) control. Set as below for an SETRC instruction For 1 step repeat 00 RE—RS=–4 For 2 step repeat 01 RE—RS=–2 For 3 step repeat 11 RE—RS=0 For 4 steps or more 10 RE—RS>0 1 0 Saturation arithmetic bit (S) Used with MAC instructions and DSP instructions T bit For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF, BF/S, SETT, CLRT and DT instructions, 1: Designates saturation arithmetic (prevents overflows) 0: represents false 1: represents true For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1, NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and ROTCR/ROTCL instructions, 1: represents occurrence of carry, borrow, overflow or underflow 31–28 15–12 0 bit 0: 0 is always read out; write a 0 Rev. 2.00 Mar 09, 2006 page 35 of 906 REJ09B0292-0200 Section 2 CPU There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For example, the RS register is accessed as follows. LDC Rm,RS; Rm→RS LDC.L @Rm+,RS; (Rm)→RS,Rm+4→Rm STC RS,Rn; RS→Rn STC.L RS,@-Rn; Rn-4→Rn,RS→(Rn) The following instructions set addresses in the RS, RE registers for zero overhead repeat control: LDRS @(disp,PC); disp×2 + PC→RS LDRE @(disp,PC); disp×2 + PC→RE The GBR register and VBR register are the same as the previous SuperH microprocessor registers. An RC counter and four control bits (DMX bit, DMY bit, RF1 bit, RF0 bit) have been added to the SR register. The RS, RE and MOD registers are new registers. 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The MACH and MACL store the results of multiplication or multiply and accumulate operations*. The PR stores the return address from the subroutine procedure. The PC indicates the address of the program in execution; it controls the flow of the processing. The PC indicates the fourth byte after the instruction currently being executed. These registers are the same as those in the SuperH microprocessor. Note: These are used only when executing an instruction that was supported by SH-1 and SH-2. They are not used for newly added multiplication instructions (PMULS). 31 0 MACH MACL Multiply and accumulate register high (MACH) Multiply and accumulate register low (MACL) 0 31 PR Procedure register (PR) 0 31 PC Program counter (PC) Figure 2.3 System Register Configuration Rev. 2.00 Mar 09, 2006 page 36 of 906 REJ09B0292-0200 Section 2 CPU In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers, the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is output from the A0 register, the guard bit section (A0G) is disregarded; when data is input to the A0 register, the MSB of the data is copied into the guard bit section (A0G). 2.1.4 DSP Registers The DSP unit has eight data registers and one control register as its DSP registers. The DSP data registers are comprised of the two 40-bit registers A0 and A1, and the six 32-bit registers M0, M1, X0, X1, Y0 and Y1. The A0 and A1 registers have the 8-bit guard bits A0G and A1G, respectively. The DSP data registers are used for the transfer and processing of the DSP data of DSP instruction operands. There are three types of instructions that access DSP data registers: those for DSP data processing, and those for X or Y data transfer processing. The control register is the 32-bit DSP status register (DSR) that represents operation results. The DSR register has bits that represent operation results, a signed greater than bit (GT), a zero bit (Z), a negative value bit (N), an overflow bit (V), a DSP status bit (DC: DSP condition), and a status selection bit (CS: condition select) for controlling DC bit setting. The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core T bit. For conditional DSP type instructions, DSP data processing execution is controlled in accordance with the DC bit. This control is related to execution in the DSP unit only, and only DSP registers are updated. It bears no relation to address calculation or such SuperH microprocessor CPU core execution instructions as load/store instructions. The control bits CS (bits 2 to 0) designate the status for setting the DC bit. DSP type instructions are comprised of unconditional DSP type instructions and conditional DSP type instructions. The status and DC bits are updated in unconditional DSP type data processing, with the exception of the PMULS, MOVX, MOVY and MOVS instructions. Conditional DSP type instructions are executed according to the status of the DC bit, but regardless of whether or not they are executed, the DSR register is not updated. Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2. Registers A0, X0, X1, Y0, Y1, and DSR are handled as system registers by CPU core instructions. Rev. 2.00 Mar 09, 2006 page 37 of 906 REJ09B0292-0200 Section 2 CPU 39 32 31 0 A0G A0 A1G A1 DSP data registers M0 M1 X0 X1 Y0 Y1 31 8 7 6 5 GT Z N 4 3 2 1 0 V CS[2:0] DC DSP status register (DSR) Figure 2.4 DSP Register Configuration Rev. 2.00 Mar 09, 2006 page 38 of 906 REJ09B0292-0200 Section 2 CPU Table 2.2 DSR Register Bits Bit Name (Abbreviation) Function 31–8 Reserved bits 0: Always read out; always use 0 as a write value 7 Signed greater than bit (GT) Indicates that the operation result is positive (excepting 0), or that operand 1 is greater than operand 2 1: Operation result is positive, or operand 1 is greater 6 Zero bit (Z) 5 Negative bit (N) Indicates that the operation result is zero (0), or that operand 1 is equal to operand 2 1: Operation result is zero (0), or equivalence Indicates that the operation result is negative, or that operand 1 is smaller than operand 2 1: Operation result is negative, or operand 1 is smaller 4 Overflow bit (V) Indicates that the operation result has overflowed 1: Operation result has overflowed 3–1 Status selection bits (CS) Designate the mode for selecting the operation result status set in the DC bit Do not set either 110 or 111 000: Carry/borrow mode 001: Negative value mode 010: Zero mode 011: Overflow mode 100: Signed greater mode 101: Signed above mode 0 DSP status bit (DC) Sets the status of the operation result in the mode designated by the CS bits 0: Designated mode status not realized (unrealized) 1: Designated mode status realized Rev. 2.00 Mar 09, 2006 page 39 of 906 REJ09B0292-0200 Section 2 CPU 2.1.5 Notes on Guard Bits and Overflow Treatment DSP unit data operations are fundamentally performed as 32-bit, but these operations are always executed with a 40-bit length including the 8-bit guard section. When the guard bit section does not match the value of the 32-bit section MSB, the operation result is treated as an overflow. In this case, the N bit indicates the correct status of the operation result regardless of the existence or not of an overflow. This is so even if the destination operand is a 32-bit length register. The 8-bit section guard bits are always presupposed and each status flag is updated. When place overflows occur so that the correct result cannot be displayed even when the guard bits are used, the N flag cannot indicate the correct status. 2.1.6 Initial Values of Registers Table 2.3 lists the values of the registers after reset. Table 2.3 Initial Values of Registers Classification Register Initial Value General registers R0–R14 Undefined R15 (SP) Value of the SP in the vector address table SR Bits I3–I0 are 1111 (H'F), the reserved bits, RC, DMY, and DMX are 0, and other bits are undefined RS Undefined Control registers RE System registers DSP registers GBR Undefined VBR H'00000000 MOD Undefined MACH, MACL, PR Undefined PC Value of the PC in the vector address table A0, A0G, A1, A1G, M0, Undefined M1, X0, X1, Y0, Y1 DSR Rev. 2.00 Mar 09, 2006 page 40 of 906 REJ09B0292-0200 H'00000000 Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operand data size is always longword (32 bits). When loading data from memory into a register, if the memory operand is a byte (8 bits) or a word (16 bits), it is sign-extended into a longword, then loaded into the register. 31 0 Longword Figure 2.5 Register Data Format 2.2.2 Data Formats in Memory These formats are classified into bytes, words, and longwords. Place byte data in any address, word data from 2n addresses, and longword data from 4n addresses. An address error will occur if accesses are made from any other boundary. In such cases, the access results cannot be guaranteed. In particular, the stack area referred to by the hardware stack pointer (SP, R15) stores the program counter (PC) and status register (SR) as longwords, so establish the hardware stack pointer so that a 4n value will always result. To enable sharing of the processor accessing memory in little-endian mode and memory, the CS2, 4 space (area 2, 4) has a function that allows access in little-endian mode. The order of byte data differs between little-endian mode and normal big-endian mode. Address m + 1 Address m 31 23 Byte Address 2n Address 4n Address m + 3 15 Byte Byte Word Address m + 1 Address m + 3 Address m + 2 Address m + 2 7 0 Byte Word 31 23 Byte Address m 15 Byte Byte Word 7 0 Byte Word Longword Longword Big endian Little endian Address 2n Address 4n Figure 2.6 Data Formats in Memory Rev. 2.00 Mar 09, 2006 page 41 of 906 REJ09B0292-0200 Section 2 CPU 2.2.3 Immediate Data Format Byte immediate data is placed in an instruction code. With the MOV, ADD, and CMP/EQ instructions, immediate data is sign-extended and operated in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code; it should be placed in a memory table. Use an immediate data transfer instruction (MOV) to refer the memory table using the PC relative addressing mode with displacement. 2.2.4 DSP Type Data Formats This chip has three different types of data format that correspond to various instructions. These are the fixed-point data format, the integer data format, and the logical data format. The DSP type fixed-point data format has a binary point fixed between bits 31 and 30. There are three types: with guard bits, without guard bits, and multiplication input; each with different valid bit lengths and value ranges. The DSP type integer data format has a binary point fixed between bits 16 and 15. There are three types: with guard bits, without guard bits, and shift amount; each with different valid bit lengths and value ranges. The shift amount of the arithmetic shift (PSHA) has a 7 bit range and can express values from –64 to +63, but the actual valid values are from –32 to +32. In the same manner, the shift amount of the logical shift has a 6 bit range, but the actual valid values are from –16 to +16. The DSP type logical data format does not have a decimal point. The data format and valid data length are determined by the instructions and DSP registers. Figure 2.7 shows the three DSP type data formats and binary point positions. The SuperH type data format is also shown for reference. Rev. 2.00 Mar 09, 2006 page 42 of 906 REJ09B0292-0200 Section 2 CPU DSP fixed decimal point data With guard bits 39 S 32 31 30 0 –28 to +28 – 2–31 31 30 No guard bits 0 –1 to +1 – 2–31 S 39 Multiplication input 31 30 S 16 15 0 –1 to +1 – 2–15 DSP integer data 39 With guard bits 16 15 32 31 0 –223 to +223 –1 S 16 15 31 No guard bits 0 –215 to +215 –1 S 31 Arithmetic shift (PSHA) 22 16 15 0 –32 to +32 S 31 Logical shift (PSHL) 39 31 21 16 15 S 0 16 15 0 –16 to +16 DSP logical data (16 bits) 31 SuperH integer (word) (Reference) 0 –231 to +231 –1 S S : Sign bit : Binary decimal point : Unrelated to processing (ignored) Figure 2.7 DSP Type Data Formats Rev. 2.00 Mar 09, 2006 page 43 of 906 REJ09B0292-0200 Section 2 CPU 2.2.5 DSP Type Instructions and Data Formats The DSP data format and valid data length are determined by DSP type instructions and DSP registers. There are three types of instructions that access DSP data registers, DSP data processing, X, Y data transfer processing, and single data transfer processing instructions. DSP Data Processing: The guard bits (bits 39–32) are valid when the A0 and A1 registers are used as source registers in DSP fixed-point data processing. When any registers other than A0, A1 (e.i., M0, M1, X0, X1, Y0, Y1 registers) are used as source registers, the sign-extended part of that register data becomes the bits 39 to 32 data. When the A0 and A1 registers are used as destination registers, the guard bits (bits 39–32) are valid. When any registers other than A0, A1 are used as destination registers, bits 39 to 32 of the result data are disregarded. Processing for DSP integer data is the same as the DSP fixed-point data processing. However, the lower word (the lower 16 bits, bits 15–0) of the source register is disregarded. The lower word of the destination register is cleared to 0. In DSP logical data processing, the upper word (the upper 16 bits, bits 31–16) of the source register is valid. The lower word and the guard bits of the A0, A1 registers are disregarded. The upper word of the destination register is valid. The lower word and the guard bits of the A0, A1 registers are cleared to 0. X, Y Data Transfers: The MOVX.W and MOVY.W instructions access X, Y memory via the 16-bit X, Y data buses. The data loaded into registers and data stored from registers is always the upper word (the upper 16 bits, bits 31–16). When loading, the MOVX.W instruction loads X memory, with the X0 and X1 registers as the destination registers. The MOVY.W instruction loads Y memory, with the Y0 and Y1 registers as the destination registers. Data is stored in the upper word of the register; the lower word is cleared to 0. The upper word data of the A0, A1 registers can be stored in X or Y memory with these data transfer instructions, but storing is not possible from any other registers. The guard bits and the lower word of the A0, A1 registers are disregarded. Single Data Transfers: The MOVS.W and MOVS.L instructions can access any memory via the data bus (CDB). All DSP registers are connected to the CDB bus, and they can become source or destination registers during data transfers. The two data transfer modes are word and longword. In word mode, data is loaded to and stored in the upper word of the DSP register, with the exception of the A0G, A1G registers. In longword mode, data is loaded to and stored in the 32 bits of the DSP register, with the exception of the A0G, A1G registers. The A0G, A1G registers can be Rev. 2.00 Mar 09, 2006 page 44 of 906 REJ09B0292-0200 Section 2 CPU treated as independent registers during single data transfers. The load/store data length for the A0G, A1G registers is 8 bits. If DSP registers are used as source registers in word mode, when data is stored from any registers other than A0G, A1G, the data in the upper word of the register is transferred. In the case of the A0, A1 registers, the guard bits are disregarded. When the A0G, A1G registers are the source registers in word mode, only 8 bits of the data are stored from the registers; the upper bits are signextended. If the DSP registers are used as destination registers in word mode, the load is to the upper word of the register, with the exception of A0G, A1G. When data is loaded to any register other than A0G, A1G, the lower word of the register is cleared to 0. In the case of the A0, A1 registers, the data sign is extended and stored in the guard bits; the lower word is cleared to 0. When the A0G, A1G registers are the destination registers in word mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values. If the DSP registers are used as source registers in longword mode, when data is stored from any registers other than A0G, A1G, the 32 bits (data) of the register are transferred. When the A0, A1 registers are used as the source registers the guard bits are disregarded. When the A0G, A1G registers are the source registers in longword mode, only 8 bits of the data are stored from the registers; the upper bits are sign-extended. If the DSP registers are used as destination registers in longword mode, the load is to the 32 bits of the register, with the exception of A0G, A1G. In the case of the A0, A1 registers, the data sign is extended and stored in the guard bits. When the A0G, A1G registers are the destination registers in longword mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values. Tables 2.4 and 2.5 indicate the register data formats for DSP instructions. Some registers cannot be accessed by certain instructions. For example, the PMULS instruction can designate the A1 register as a source register but cannot designate A0 as such. Refer to the instruction explanations for details. Figure 2.8 shows the relationship between the buses and the DSP registers during transfers. Rev. 2.00 Mar 09, 2006 page 45 of 906 REJ09B0292-0200 Section 2 CPU Table 2.4 Source Register Data Formats for DSP Instructions Register A0, A1 Instruction DSP operation Data transfer Guard Bits 39–32 Fixed decimal, PDMSB, PSHA 40-bit data Integer 24-bit data Logic, PSHL, PMULS — X0, X1, Y0, Y1, M0, M1 Data transfer MOVS.W DSP operation Fixed decimal, PDMSB, PSHA 15–0 — 16-bit data 32-bit data Data — Sign* 32-bit data — MOVS.L Integer Logic, PSHL, PMULS Data transfer 31–16 MOVX.W, MOVY.W, MOVS.W MOVS.L A0G, A1G Register Bits 16-bit data — MOVS.W MOVS.L Note: * The sign is extended and stored in the ALU’s guard bits. Rev. 2.00 Mar 09, 2006 page 46 of 906 REJ09B0292-0200 32-bit data — Section 2 CPU Table 2.5 Destination Register Data Formats for DSP Instructions Register A0, A1 Instruction DSP operation Fixed decimal, PSHA, PMULS 31–16 (Sign extend) 40-bit result Integer, PDMSB Data transfer 24-bit result Logic, PSHL Clear to 0 MOVS.W Sign extend MOVS.L A0G, A1G Data transfer MOVS.W Register Bits Guard Bits 39–32 15–0 Clear to 0 16-bit result 32-bit data Data Not updated — 32-bit result Not updated MOVS.L X0, X1, Y0, Y1, M0, M1 DSP operation Fixed decimal, PSHA, PMULS Integer, logic, PDMSB, PSHL Data transfer 16-bit result Clear to 0 MOVX.W, MOVY.W, MOVS.W MOVS.L 32-bit data Rev. 2.00 Mar 09, 2006 page 47 of 906 REJ09B0292-0200 Section 2 CPU 32 bits CDB 16 bits XDB 16 bits [7:0] 16 bits 8 bits MOVX.W, MOVY.W MOVS.W, MOVS.L 16 A0 39 7 31 YDB 32 bits MOVS.W, MOVS.L 0 32 A1 A0G M0 A1G M1 DSR X0 0 X1 Y0 Y1 Figure 2.8 DSP Register-Bus Relationship during Data Transfers 2.3 CPU Core Instruction Features The CPU core instructions are RISC type. The characteristics are as follows. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz. Data Length: Longword is the basic data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data. Rev. 2.00 Mar 09, 2006 page 48 of 906 REJ09B0292-0200 Section 2 CPU Table 2.6 Sign Extension of Word Data SH7616 CPU Description MOV.W @(disp,PC),R1 ADD R1,R0 Data is sign-extended to 32 ADD.W bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction ........ Example of Conventional CPU #H'1234,R0 .DATA.W H'1234 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). However, Instructions such as AND manipulating bits, are executed directly in memory. Delayed Branches: Such instructions as unconditional branches are delayed branch instructions. In the case of delayed branch instructions, the branch occurs after execution of the instruction immediately following the delayed branch instruction (slot instruction). This reduces pipeline disruption during branching. The branching operation of the delayed branch occurs after execution of the slot instruction. However, with the exception of such branch operations as register updating, execution of instructions is performed with the order of delayed branch instruction, then delayed slot instruction. For example, even if the contents of a register storing a branch destination address are modified by a delayed slot, the branch destination address will still be the contents of the register before the modification. Table 2.7 Delayed Branch Instructions SH7616 CPU Description Example of Conventional CPU BRA TRGET ADD.W ADD R1,R0 Executes an ADD before branching to TRGET BRA R1,R0 TRGET Multiplication/Multiply-Accumulate Operation: 16 × 16 → 32 multiplications execute in one to three cycles, and 16 × 16 + 64 → 64 multiply-accumulate operations execute in two to three cycles. 32 × 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations execute in two to four cycles. Rev. 2.00 Mar 09, 2006 page 49 of 906 REJ09B0292-0200 Section 2 CPU T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and conditional branches occur in accordance with its true or false status. The number of instructions modifying the T bit is kept to a minimum to improve the processing speed. Table 2.8 T Bit SH7616 CPU Description Example of Conventional CPU CMP/GE R1,R0 T bit is set when R0 ≥ R1. CMP.W R1,R0 BT TRGET0 The program branches to TRGET0 BGE when R0 ≥ R1. TRGET0 BF TRGET1 The program branches to TRGET1 BLT when R0 < R1 TRGET1 ADD #–1,R0 CMP/EQ #0,R0 BT TRGET T bit is not changed by ADD. T bit is set when R0 = 0. The program branches when R0 = 0 SUB.W #1,R0 BEQ TRGET Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate data is not input in instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Table 2.9 Immediate Data Accessing Classification SH7616 CPU Example of Conventional CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 MOV.L #H'12345678,R0 ........ .DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 ........ .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Rev. 2.00 Mar 09, 2006 page 50 of 906 REJ09B0292-0200 Section 2 CPU Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode. Table 2.10 Absolute Address Accessing Classification SH7616 CPU Example of Conventional CPU Absolute address MOV.L @(disp,PC),R1 MOV.B @H'12345678,R0 MOV.B @R1,R0 ........ .DATA.L H'12345678 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode. Table 2.11 Displacement Accessing Classification SH7616 CPU Example of Conventional CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W MOV.W @(R0,R1),R2 @(H'1234,R1),R2 ........ .DATA.W H'1234 Rev. 2.00 Mar 09, 2006 page 51 of 906 REJ09B0292-0200 Section 2 CPU 2.4 Instruction Formats 2.4.1 CPU Instruction Addressing Modes The addressing modes and effective address calculation for instructions executed by the CPU core are listed in table 2.12. Table 2.12 CPU Instruction Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Addresses Calculation Equation Direct register addressing Rn The effective address is register Rn (The operand is the contents of register Rn) — The effective address is the content of register Rn Rn Indirect register @Rn addressing Rn Post-increment @Rn+ indirect register addressing Rn The effective address is the content of register Rn Rn. A constant is added to the content of Rn after (After the the instruction is executed. 1 is added for a byte instruction operation, 2 for a word operation, and 4 for a executes) longword operation Byte: Rn + 1 → Rn Rn Rn Word: Rn + 2 → Rn Rn + 1/2/4 Longword: Rn + 4 + → Rn 1/2/4 Pre-decrement @–Rn indirect register addressing The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation Rn Rn – 1/2/4 1/2/4 Rev. 2.00 Mar 09, 2006 page 52 of 906 REJ09B0292-0200 – Rn – 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation) Section 2 CPU Addressing Mode Instruction Format Effective Addresses Calculation Indirect register @(disp:4, addressing Rn) with displacement The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation Equation Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Rn disp (zero-extended) + Rn + disp × 1/2/4 × 1/2/4 Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0 register Rn addressing + Rn + R0 Rn + R0 R0 Indirect GBR @(disp:8, addressing with GBR) displacement The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation Byte: GBR + disp Word: GBR + disp ×2 Longword: GBR + disp × 4 GBR disp (zero-extended) + GBR + disp × 1/2/4 × 1/2/4 Rev. 2.00 Mar 09, 2006 page 53 of 906 REJ09B0292-0200 Section 2 CPU Addressing Mode Instruction Format Effective Addresses Calculation Indirect indexed GBR addressing @(R0, GBR) The effective address is the GBR value plus the R0 Equation GBR + R0 GBR + GBR + R0 R0 PC relative addressing with displacement @(disp:8, PC) The effective address is the PC value plus an 8-bit displacement (disp). The value of disp is zeroextended, is doubled for a word operation, and is quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked PC (for longword) & H'FFFFFFFC + disp (zero-extended) × 2/4 Rev. 2.00 Mar 09, 2006 page 54 of 906 REJ09B0292-0200 PC + disp × 2 or PC&H'FFFFFFFC + disp × 4 Word: PC + disp ×2 Longword: PC & H'FFFFFFFC + disp × 4 Section 2 CPU PC relative addressing disp:8 The effective address is the PC value sign-extended PC + disp × 2 with an 8-bit displacement (disp), doubled, and added to the PC value PC disp (sign-extended) + PC + disp × 2 × 2 disp:12 The effective address is the PC value sign-extended PC + disp × 2 with a 12-bit displacement (disp), doubled, and added to the PC value PC disp (sign-extended) + PC + disp × 2 × 2 Rn The effective address is the register PC value plus Rn PC + Rn PC + PC + Rn Rn Immediate addressing #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended — #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended — #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled — Rev. 2.00 Mar 09, 2006 page 55 of 906 REJ09B0292-0200 Section 2 CPU 2.4.2 DSP Data Addressing There are two different kinds of memory accesses with DSP instructions. One type is with the X, Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of instructions. Table 2.13 shows a summary of the data transfer instructions. Table 2.13 Overview of Data Transfer Instructions Classification X, Y Data Transfer Processing (MOVX.W, MOVY.W) Single Data Transfer Processing (MOVS.W, MOVS.L) Address registers Ax: R4, R5; Ay: R6, R7 As: R2, R3, R4, R5 Index registers Ix: R8, Iy: R9 Is: R8 Addressing Nop/Inc(+2)/index addition: postupdate Nop/Inc(+2,+4)/index addition: postupdate — Dec(–2,–4): pre-update Possible Not possible Modulo addressing Data bus XDB, YDB CDB Data length 16 bit (word) 16 bit/32 bit (word/longword) Bus contention None Yes Memory X, Y data memory All memory spaces Source registers Dx, Dy: A0, A1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G Destination registers Dx: X0/X1; Dy: Y0/Y1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G X, Y Data Addressing: Among the DSP instructions, the MOVX.W and MOVY.W instructions can be used to simultaneously access X, Y data memory. The DSP instructions have two address pointers for simultaneous accessing of X, Y data memory. Only pointer addressing is possible with DSP instructions; there is no immediate addressing. The address registers are divided into two; the R4, R5 registers become the X memory address register (Ax), and the R6, R7 registers become the Y memory address register (Ay). The following three types of addressing exist with X, Y data transfer instructions. 1. Non-updated address registers: The Ax, Ay registers are address pointers. They are not updated. 2. Add index registers: The Ax, Ay registers are address pointers. The Ix, Iy register values are added to them, respectively, after the data transfer (post-update). Rev. 2.00 Mar 09, 2006 page 56 of 906 REJ09B0292-0200 Section 2 CPU 3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added to each of them after the data transfer (post-update). Each of the address pointers has an index register. The R8 register becomes the index register (Ix) of the X memory address register (Ax), and the R9 register becomes the index register (Iy) of the Y memory address register (Ay). The X, Y data transfer instructions are processed in word lengths. X, Y data memory is accessed in 16 bit lengths. This is why the increment processing adds 2 to the address registers. In order to decrement, set –2 in the index register and designate add index register addressing. During X, Y data addressing, only bits 1 to 15 of the address pointer are valid. Always write a 0 to bit 0 of the address pointer and the index register during X, Y data addressing. Figure 2.9 shows the X, Y data transfer addressing. When X memory and Y memory are accessed using the X, Y bus, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of @Ay+ and @Ay+Iy is stored in the lower word of Ay, and the upper word retains its original value. R8[Ix] R4[Ax] R9[Iy] R6[Ay] R5[Ax] +2 (INC) +0 (No update) R7[Ay] +2 (INC) +0 (No update) ALU Notes: AU* All three addressing methods (increment, index register addition (Ix, Iy), and no update) are post-updating methods. To decrement the address pointer, set the index register to –2 or –4. * Adder added for DSP addressing. Figure 2.9 X, Y Data Transfer Addressing Rev. 2.00 Mar 09, 2006 page 57 of 906 REJ09B0292-0200 Section 2 CPU Single Data Addressing: Among the DSP instructions, the single data transfer instructions (MOVS.W and MOVS.L) are used to either load data into DSP registers or to store it from them. With these instructions, the registers R2 to R5 are used as address registers (As) for the single data transfers. The four following data addressing instructions exist for single data transfer instructions. 1. Non-updated address registers: The As registers are address pointers. They are not updated. 2. Add index registers: The As registers are address pointers. The Is register values are added to them after the data transfer (post-update). 3. Increment address registers: The As registers are address pointers. The value +2 or +4 is added after the data transfer (post-update). 4. Decrement address registers: The As registers are address pointers. The value –2 or –4 is added (+2 or +4 is subtracted) before the data transfer (pre-update). The address pointer (As) uses the R8 register as an index register (Is). Figure 2.10 shows the single data transfer addressing. 0 31 R2[As] 31 0 R8[Is] R3[As] R4[As] R5[As] –2/–4 (DEC) +2/+4 (INC) +0 (No update) ALU 31 MAB CAB 0 Note: There are four addressing methods (no update, index register addition (Is), increment, and decrement). Index register addition and increment are post-updating methods. Decrement is a pre-updating method. Figure 2.10 Single Data Transfer Addressing Rev. 2.00 Mar 09, 2006 page 58 of 906 REJ09B0292-0200 Section 2 CPU Modulo Addressing: The chip has a modulo addressing mode, just as other DSPs do. Address registers are updated in the same manner as with other modes. When the address pointer value becomes the same as a previously established modulo end address, the address pointer becomes the modulo start address. Modulo addressing is valid only with X, Y data transfer instructions (MOVX.W, MOVY.W). When the DMX bit of the SR register is set, the X address register enters modulo addressing mode; when the DMY bit of the SR register is set, the Y address register does so. Modulo addressing is valid only for either the X or the Y address register; it is not possible to make them both modulo addressing mode at the same time. Therefore, do not simultaneously set the DMX and DMY. If they happen to be set at the same time, only the DMY side is valid. The MOD register is used to designate the start and end addresses of the modulo address area; it stores the MS (modulo start) and ME (modulo end). An example of MOD register (MS, ME) usage is indicated below. ModAddr: MOV.L ModAddr,Rn; Rn=ModEnd, ModStart LDC Rn,MOD; ME=ModEnd, MS=ModStart .DATA.W mEnd; ModEnd .DATA.W mStart; ModStart ModStart: .DATA : ModEnd: .DATA Designate the start and end addresses in MS and ME, and then set the DMX or DMY bit to 1. The contents of the address register are compared with ME. If they match ME, the start address MS is stored in the address register. The lower 16 bits of the address register are compared with ME. The maximum modulo size is 64 kbytes. This is sufficient for X, Y data memory accesses. Figure 2.11 shows a block diagram of modulo addressing. Rev. 2.00 Mar 09, 2006 page 59 of 906 REJ09B0292-0200 Section 2 CPU Instruction (MOVX/MOVY) 31 31 0 R8[Ix] 16 15 R4[Ax] 0 DMX DMY 31 16 15 0 R6[Ay] R5[Ax] CONT +2 +0 15 31 R7[Ay] 0 R9[Iy] +2 +0 1 MS ALU AU CMP ABx 1 15 ABy ME 15 1 1 15 XAB YAB Figure 2.11 Modulo Addressing An example of modulo addressing is indicated below: MS=H'E008; ME=H'E00C; R4=H'1000E008; DMX=1; DMY=0; (sets modulo addressing for address register Ax (R4, R5)) The R4 register changes as follows due to the above settings. R4: H'1000E008 Inc. R4: H'1000E00A Inc. R4: H'1000E00C Inc. R4: H'1000E008 (becomes the modulo start address because the modulo end address occurred) Data is placed so that the upper 16 bits of the modulo start and end addresses become identical. This is so because the modulo start address replaces only the lower 15 bits of the address register, excepting bit 0. Note: When using add index with DSP data addressing, there are cases where the value is exceeded without the address pointer matching the ME. In such cases, the address pointer does not return to the modulo start address. Bit 0 is disregarded not only for modulo addressing, but also during X, Y data addressing, so always write 0 to the 0 bits of the address pointer, index register, MS, and ME. Rev. 2.00 Mar 09, 2006 page 60 of 906 REJ09B0292-0200 Section 2 CPU DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the pipeline, including modulo addressing, is indicated below. if ( Operation is MOVX.W MOVY.W ) { ABx=Ax; ABy=Ay; /* memory access cycle uses ABx and ABy. The addresses to be used have not been updated */ /* Ax is one of R4,5 */ if ( DMX==0 || DMX==1 && DMY==1 )} Ax=Ax+(+2 or R8[Ix} or +0); /* Inc,Index,Not-Update */ else if (!not-update) Ax=modulo( Ax, (+2 or R8[Ix]) ); /* Ay is one of R6,7 */ if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0; /* Inc,Index,Not-Update */ else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) ); } else if ( Operation is MOVS.W or MOVS.L ) { if ( Addressing is Nop, Inc, Add-index-reg ) { MAB=As; /* memory access cycle uses MAB. The address to be used has not been updated */ /* As is one of R2–5 */ As=As+(+2 or +4 or R8[Is] or +0); /* Inc.Index,Not-Update */ else { /* Decrement, Pre-update */ /* As is one of R2–5 */ As=As+(–2 or –4); MAB=As; /* memory access cycle uses MAB. The address to be used has been updated */ } /* The value to be added to the address register depends on addressing operations. For example, (+2 or R8[Ix] or +0) means that +2: R8[Ix}: if operation is increment if operation is add-index-reg Rev. 2.00 Mar 09, 2006 page 61 of 906 REJ09B0292-0200 Section 2 CPU +0: if operation is not-update */ function modulo ( AddrReg, Index ) { if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS; else AdrReg=AdrReg+Index; return AddrReg; } 2.4.3 Instruction Formats for CPU Instructions The instruction format of instructions executed by the CPU core and the meanings of the source and destination operands are indicated below. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Rev. 2.00 Mar 09, 2006 page 62 of 906 REJ09B0292-0200 Section 2 CPU Table 2.14 Instruction Formats for CPU Instructions Instruction Formats 0 format 15 Source Operand Destination Operand Example — — NOP — nnnn: Direct register MOVT Rn 0 xxxx xxxx xxxx xxxx n format 15 0 xxxx nnnn xxxx xxxx Control register or nnnn: Direct system register register STS MACH,Rn Control register or nnnn: Indirect pre- STC.L SR,@-Rn system register decrement register m format 15 0 xxxx mmmm xxxx mmmm: Direct register Control register or LDC system register Rm,SR xxxx mmmm: Indirect post- Control register or LDC.L @Rm+,SR increment register system register mmmm: Indirect register — JMP @Rm mmmm: PC relative using Rm — BRAF Rm Rev. 2.00 Mar 09, 2006 page 63 of 906 REJ09B0292-0200 Section 2 CPU Instruction Formats Source Operand Destination Operand nm format mmmm: Direct register nnnn: Direct register ADD mmmm: Direct register nnnn: Indirect register MOV.L Rm,@Rn 15 0 xxxx nnnn mmmm xxxx mmmm: Indirect post- MACH, MACL increment register (multiply/ accumulate) Example Rm,Rn MAC.W @Rm+,@Rn+ nnnn: Indirect postincrement register (multiply/ accumulate)* mmmm: Indirect post- nnnn: Direct increment register register md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx MOV.L @Rm+,Rn mmmm: Direct register nnnn: Indirect pre- MOV.L Rm,@-Rn decrement register mmmm: Direct register nnnn: Indirect indexed register MOV.L Rm,@(R0,Rn) mmmmdddd: indirect R0 (Direct register) MOV.B register with @(disp,Rm),R0 displacement R0 (Direct register) nnnndddd: Indirect MOV.B register with R0,@(disp,Rn) displacement mmmm: Direct register nnnn mmmm dddd nnnndddd: Indirect MOV.L register with Rm,@(disp,Rn) displacement mmmmdddd: Indirect nnnn: Direct register register with displacement Rev. 2.00 Mar 09, 2006 page 64 of 906 REJ09B0292-0200 MOV.L @(disp,Rm),Rn Section 2 CPU Instruction Formats Source Operand d format 15 0 xxxx xxxx dddd dddd Destination Operand Example dddddddd: Indirect R0 (Direct register) MOV.L GBR with @(disp,GBR),R0 displacement R0(Direct register) dddddddd: Indirect MOV.L GBR with R0,@(disp,GBR) displacement d12 format 15 0 xxxx dddd dddd 15 0 nnnn dddd dddd i format 15 0 xxxx xxxx iiii iiii ni format 15 0 xxxx nnnn iiii R0 (Direct register) MOVA @(disp,PC),R0 dddddddd: PC relative — BF dddddddddddd: PC relative — BRA dddddddd: PC relative with displacement nnnn: Direct register MOV.L @(disp,PC),Rn iiiiiiii: Immediate Indirect indexed GBR AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Direct register) AND iiiiiiii: Immediate — TRAPA #imm iiiiiiii: Immediate nnnn: Direct register ADD label label (label=disp+PC) dddd nd8 format xxxx dddddddd: PC relative with displacement #imm,R0 #imm,Rn iiii Note: * In multiply/accumulate instructions, nnnn is the source register. Rev. 2.00 Mar 09, 2006 page 65 of 906 REJ09B0292-0200 Section 2 CPU 2.4.4 Instruction Formats for DSP Instructions New instructions have been added for digital signal processing. The new instructions are divided into the two following types. 1. Memory and DSP register double, single data transfer instructions (16 bit length) 2. Parallel processing instructions processed by the DSP unit (32 bit length) Figure 2.12 shows each of the instruction formats. 15 CPU core instructions Double data transfer instructions Single data transfer instructions Parallel processing instructions 0 0000 to 1110 15 10 9 111100 15 0 10 9 111101 31 0 A field A field 26 25 111110 16 15 A field 0 B field Figure 2.12 Instruction Formats for DSP Instructions Double, Single Data Transfer Instructions: Table 2.15 indicates the data formats for double data transfer instructions, and table 2.16 indicates the data formats for single data transfer instructions. Rev. 2.00 Mar 09, 2006 page 66 of 906 REJ09B0292-0200 Section 2 CPU Table 2.15 Instruction Formats for Double Data Transfers Category Mnemonic 15 14 13 12 11 10 9 X memory data transfers NOPX 1 1 1 1 0 0 0 Y memory data transfers MOVX.W MOVX.W MOVX.W @Ax,Dx @Ax+,Dx @Ax+Ix,Dx MOVX.W MOVX.W MOVX.W Da,@Ax Da,@Ax+ Da,@Ax+Ix Ax 1 NOPY MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy MOVY.W MOVY.W MOVY.W Da,@Ay Da,@Ay+ Da,@Ay+Iy 1 1 1 0 0 Mnemonic 7 X memory data transfers NOPX 0 6 5 4 3 2 0 0 0 MOVX.W MOVX.W MOVX.W @Ax,Dx @Ax+,Dx @Ax+Ix,Dx Dx 0 0 1 1 1 0 1 MOVX.W MOVX.W MOVX.W Da,@Ax Da,@Ax+ Da,@Ax+Ix Da 1 0 1 1 1 0 1 NOPY 0 Ay Category Y memory data transfers 8 1 0 0 0 0 0 MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Dy 0 0 1 1 1 0 1 MOVY.W MOVY.W MOVY.W Da,@Ay Da,@Ay+ Da,@Ay+Iy Da 1 0 1 1 1 0 1 Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1 Rev. 2.00 Mar 09, 2006 page 67 of 906 REJ09B0292-0200 Section 2 CPU Table 2.16 Instruction Formats for Single Data Transfers Category Mnemonic Single data transfer MOVS.W MOVS.W MOVS.W MOVS.W @–As,Ds @As,Ds @As+,Ds @As+Is,Ds MOVS.W MOVS.W MOVS.W MOVS.W Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is MOVS.L MOVS.L MOVS.L MOVS.L @–As,Ds @As,Ds @As+,Ds @As+Is,Ds MOVS.L MOVS.L MOVS.L MOVS.L Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is Category Mnemonic Single data transfer MOVS.W MOVS.W MOVS.W MOVS.W @–As,Ds @As,Ds @As+,Ds @As+Is,Ds MOVS.W MOVS.W MOVS.W MOVS.W 15 14 13 12 11 10 1 1 1 1 0 1 9 8 As 0: R4 1: R5 2: R2 3: R3 7 4 3 2 1 0 0: (*) 1: (*) 2: (*) 3: (*) 0 0 1 1 0 1 0 1 0 0 Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is 4: (*) 5: A1 6: (*) 7: A0 0 0 1 1 0 1 0 1 MOVS.L MOVS.L MOVS.L MOVS.L @–As,Ds @As,Ds @As+,Ds @As+Is,Ds 8: X0 9: X1 A: Y0 B: Y1 0 0 1 1 0 1 0 1 MOVS.L MOVS.L MOVS.L MOVS.L Ds,@-As Ds,@As Ds,@As+ Ds,@As+Is C: M0 D: A1G E: M1 F: A0G 0 0 1 1 0 1 0 1 Note: * System reserved code Rev. 2.00 Mar 09, 2006 page 68 of 906 REJ09B0292-0200 6 Ds 5 1 1 0 1 Section 2 CPU Parallel Processing Instructions: The parallel processing instructions allow for more efficient execution of digital signal processing using the DSP unit. They are 32 bit length, allowing simultaneously in parallel four processes, ALU operations, multiplications or 2 data transfers. The parallel processing instructions are divided into A fields and B fields. The A field defines data transfer instructions; the B field defines ALU operation instructions and multiplication instructions. These instructions can be defined independently, the processes can be independent, and furthermore, they can be executed simultaneously in parallel. Table 2.17 indicates the A field parallel data transfer instructions, and table 2.18 indicates the B field ALU operation instructions and multiplication instructions. A fields instruction is the same as double data transfers in table 2.15. Table 2.17 A Field Parallel Data Transfer Instructions Category Mnemonic 31 30 29 28 27 26 25 X memory data transfers NOPX 1 1 1 1 1 0 0 0 Ax Dx Y memory data transfers MOVX.W MOVX.W MOVX.W @Ax,Dx @Ax+,Dx @Ax+Ix,Dx MOVX.W MOVX.W MOVX.W Da,@Ax Da,@Ax+ Da,@Ax+Ix 24 23 Da 0 NOPY MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy MOVY.W MOVY.W MOVY.W Da,@Ay Da,@Ay+ Da,@Ay+Iy Ay Rev. 2.00 Mar 09, 2006 page 69 of 906 REJ09B0292-0200 Section 2 CPU Category Mnemonic X memory data transfers NOPX Y memory data transfers 22 21 20 19 18 0 0 0 MOVX.W MOVX.W MOVX.W @Ax,Dx @Ax+,Dx @Ax+Ix,Dx 0 0 1 1 1 0 1 MOVX.W MOVX.W MOVX.W Da,@Ax Da,@Ax+ Da,@Ax+Ix 1 0 1 1 1 0 1 NOPY 17 16 15–0 B field 0 0 0 0 MOVY.W MOVY.W MOVY.W @Ay,Dy @Ay+,Dy @Ay+Iy,Dy Dy 0 0 1 1 1 0 1 MOVY.W MOVY.W MOVY.W Da,@Ay Da,@Ay+ Da,@Ay+Iy Da 1 0 1 1 1 0 1 Ax: 0 = R4, 1 = R5 Ay: 0 = R6, 1 = R7 Dx: 0 = X0, 1 = X1 Dy: 0 = Y0, 1 = Y1 Da: 0 = A0, 1 = A1 Rev. 2.00 Mar 09, 2006 page 70 of 906 REJ09B0292-0200 Section 2 CPU Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions Category Mnemonic Imm. shift PSHL #lmm, Dz PSHA #lmm, Dz Reserved Six operand parallel instruction PMULS Se, Sf, Dg Reserved PSUB Sx, Sy, Du PMULS Se, Sf, Dg PADD Sx, Sy, Du PMULS Se, Sf, Dg Three operand instructions Reserved PSUBC Sx, Sy, Dz PADDC Sx, Sy, Dz PCMP Sx, Sy Reserved Reserved Reserved PABS Sx, Dz PRND Sx, Dz PABS Sy, Dz PRND Sy, Dz Reserved 31–27 1 26 0 25–16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A field 0 0 0 0 0 –16 ≤ lmm ≤ +16 Dz 0 0 0 1 0 0 0 0 1 – 32 ≤ lmm ≤ +32 0 0 1 0 1 0 0 Se 0 1 0 1 0:X0 1:X1 0 1 1 0 2:Y0 3:A1 Sf Sx Sy Dg Du 0:Y0 1:Y1 2:X0 3:A1 0:X0 1:X1 2:A0 3:A1 0:Y0 1:Y1 2:M0 3:M1 0:M0 1:M1 2:A0 3:A1 0:X0 1:Y0 2:A0 3:A1 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 1 0 0 Dz 0: (*1) 1: (*1) 2: (*1) 3: (*1) 4: (*1) 5: A1 6: (*1) 7: A0 8: X0 9: X1 A: Y0 B: Y1 C: M0 D: (*1) E: M1 F: (*1) Rev. 2.00 Mar 09, 2006 page 71 of 906 REJ09B0292-0200 Section 2 CPU Category Mnemonic 31–27 26 (if cc) PSHL Sx, Sy, Dz 1 0 Conditional (if cc) PSHA Sx, Sy, Dz three operand (if cc) PSUB Sx, Sy, Dz instructions (if cc) PADD Sx, Sy, Dz 25–16 15 14 13 12 11 10 0 0 0 0 A field 0 1 1 0 1 1 Reserved (if cc) PAND Sx, Sy, Dz (if cc) PXOR Sx, Sy, Dz (if cc) POR Sx, Sy, Dz (if cc) PDEC Sx, Dz 0 0 1 1 0 0 0 1 1 0 1 0 1 0 (if cc) PINC Sx, Dz (if cc) PDEC Sy, Dz (if cc) PINC Sy, Dz (if cc) PCLR Dz (if cc) PDMSB Sx, Dz Reserved (if cc) PDMSB Sy, Dz (if cc) PNEG Sx, Dz (if cc) PCOPY Sx, Dz (if cc) PNEG Sy, Dz (if cc) PCOPY Sy, Dz Reserved 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 (if cc) PLDS Dz, MACH (if cc) PLDS Dz, MACL 1 0 1 1 10:DCT 11:DCF 0 if cc 0 Reserved*2 7 6 5 4 3 2 1 0 01: Uncondition 0 (if cc) PSTS MACH, Dz (if cc) PSTS MACL, Dz Reserved 9 8 if cc 0 0 * 1 * : Don't care Notes: 1. System reserved code 2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction) 2.5 Instruction Set The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a number of CPU instructions for supporting the DSP functions. The instruction set is explained below in terms of each of the three groups. Rev. 2.00 Mar 09, 2006 page 72 of 906 REJ09B0292-0200 Section 2 CPU 2.5.1 CPU Instruction Set Table 2.19 lists the CPU instructions by classification. Table 2.19 Classification of CPU Instructions Operation Classification Types Code Function Data transfer Arithmetic operations 5 21 MOV No. of Instructions Data transfer, immediate data transfer, peripheral 39 module data transfer, structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow 33 CMP/cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double-length multiplication DMULU Unsigned double-length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply/accumulate, double-length multiply/accumulate operation MUL Double-length multiply operation MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow Rev. 2.00 Mar 09, 2006 page 73 of 906 REJ09B0292-0200 Section 2 CPU Operation Classification Types Code Function No. of Instructions Logic operations 14 Shift Branch 6 10 9 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit ROTL One-bit left rotation ROTR One-bit right rotation SHAL One-bit arithmetic left shift 14 SHAR One-bit arithmetic right shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift BF Conditional branch, conditional branch with delay 11 (Branch when T = 0) BT Conditional branch, conditional branch with delay (Branch when T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure Rev. 2.00 Mar 09, 2006 page 74 of 906 REJ09B0292-0200 Section 2 CPU Operation Classification Types Code Function No. of Instructions System control 71 14 Total:65 CLRMAC MAC register clear CLRT T bit clear LDC Load to control register LDRE Load to repeat end register LDRS Load to repeat start register LDS Load to system register NOP No operation RTE Return from exception processing SETRC Repeat count setting SETT T bit set SLEEP Shift into power-down mode STC Storing control register data STS Storing system register data TRAPA Trap exception handling 182 Rev. 2.00 Mar 09, 2006 page 75 of 906 REJ09B0292-0200 Section 2 CPU The instruction codes, operation, and execution states of the CPU instructions are listed by classification with the formats listed in below. Instruction Instruction Code Operation Indicated by mnemonic Indicated in MSB ↔ LSB order Indicates summary of operation Explanation of Symbols Explanation of Symbols Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination mmmm: Source register →, ←: Transfer direction Rm: Source register nnnn: Destination register (xx): Memory operand 0000: R0 M/Q/T: Flag bits in the SR 0001: R1 &: Logical AND of each bit ......... |: Logical OR of each bit 1111: R15 Rn: Destination register iiii: Immediate data ^: Exclusive OR of each bit imm: Immediate data disp: Displacement*2 dddd: Displacement ~: Logical NOT of each bit Execution Cycles T Bit Value when no wait states are inserted*1 Value of T bit after instruction is executed Explanation of Symbols —: No change n: n-bit right shift Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 2. Depending on the instruction’s operand size, scaling is ×1, ×2, or ×4. For details, see the SH-1/SH-2/SH-DSP Software Manual. Rev. 2.00 Mar 09, 2006 page 76 of 906 REJ09B0292-0200 Section 2 CPU Table 2.20 Data Transfer Instructions Instruction Instruction Code MOV #imm,Rn MOV.W Operation Cycles T Bit 1110nnnniiiiiiii imm → Sign extension → Rn 1 — @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign extension → Rn 1 — MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1 — MOV Rm,Rn 0110nnnnmmmm0011 Rm → Rn 1 — MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 — MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1 — MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1 — MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) → Sign extension → Rn 1 — MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) → Sign extension → Rn 1 — MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) → Rn 1 — MOV.B Rm,@–Rn 0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn) 1 — MOV.W Rm,@–Rn 0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn) 1 — MOV.L Rm,@–Rn 0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn) 1 — MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) → Sign extension → Rn,Rm + 1 → Rm 1 — MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → Sign extension → Rn,Rm + 2 → Rm 1 — MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm 1 — MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 → (disp + Rn) 1 — MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 1 — MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 1 — MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) → Sign extension → R0 1 — MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → Sign extension → R0 1 — MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 1 — MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) 1 — MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 — Rev. 2.00 Mar 09, 2006 page 77 of 906 REJ09B0292-0200 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign extension → Rn 1 — MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign extension → Rn 1 — MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 — MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (disp + GBR) 1 — MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1 — MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 1 — MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign extension → R0 1 — MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign extension → R0 1 — MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 1 — MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0 1 — MOVT Rn 0000nnnn00101001 T → Rn 1 — SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → Swap the bottom two bytes → Rn 1 — SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → Swap upper and lower words → Rn 1 — XTRCT 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn → Rn 1 — Rm,Rn Rev. 2.00 Mar 09, 2006 page 78 of 906 REJ09B0292-0200 Section 2 CPU Table 2.21 Arithmetic Instructions Instruction Instruction Code Operation Cycles T Bit ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1 — ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1 — ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T → Rn, Carry → T 1 Carry ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm → Rn, Overflow → T 1 Overflow CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 → T 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn ≥ Rm with unsigned data, 1 → T 1 Comparison result CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ Rm with signed 1 data, 1 → T Comparison result CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 → T 1 Comparison result CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 → T 1 Comparison result CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 → T 1 Comparison result CMP/PZ Rn 0100nnnn00010001 If Rn ≥ 0, 1 → T 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm contain an identical byte, 1→T 1 Comparison result DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn/Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB 1 of Rm → M, M ^ Q → T Calculation result 0000000000011001 0 → M/Q/T 0 DIV0U 1 Rev. 2.00 Mar 09, 2006 page 79 of 906 REJ09B0292-0200 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit 4* — DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 2 to DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 2 to 4* — DT 0100nnnn00010000 Rn – 1 → Rn, when Rn is 0, 1 → T When Rn is nonzero, 0→T 1 Comparison result EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is signextended → Rn 1 — EXTS.W Rm,Rn 0110nnnnmmmm1111 A word in Rm is signextended → Rn 1 — EXTU.B Rm,Rn 0110nnnnmmmm1100 A byte in Rm is zeroextended → Rn 1 — EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zeroextended → Rn 1 — MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits 3/(2 to 4)* — MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits 3/(2)* — MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL, 32 × 32 → 32 bits 2 to 4* — MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits 1 to 3* — MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 1 to 3* — NEG Rm,Rn 0110nnnnmmmm1011 0–Rm → Rn 1 — NEGC Rm,Rn 0110nnnnmmmm1010 0–Rm–T → Rn, Borrow → T 1 Borrow Rn Rev. 2.00 Mar 09, 2006 page 80 of 906 REJ09B0292-0200 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit SUB Rm,Rn 0011nnnnmmmm1000 Rn–Rm → Rn 1 — SUBC Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T → Rn, Borrow → T 1 Borrow SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn, Underflow → T 1 Underflow Note: * The normal number of execution cycles. The number in parentheses is the number of execution cycles in the case of contention with preceding or following instructions. Table 2.22 Logic Operation Instructions Instruction Instruction Code Operation Cycles T Bit AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm → Rn 1 — AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 — AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → (R0 + GBR) 3 — NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 — OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 — OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 — OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm → (R0 + GBR) 3 — TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T, 1 → MSB of (Rn) 4 Test result TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm, if the result is 0, 1 → T 1 Test result TST #imm,R0 11001000iiiiiiii R0 & imm, if the result is 0, 1 → T 1 Test result TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm, if the 3 result is 0, 1 → T Test result XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 — XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 — XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → (R0 + GBR) 3 — Rev. 2.00 Mar 09, 2006 page 81 of 906 REJ09B0292-0200 Section 2 CPU Table 2.23 Shift Instructions Instruction Instruction Code Operation Cycles T Bit ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB ROTR Rn 0100nnnn00000101 LSB → Rn → T 1 LSB ROTCL Rn 0100nnnn00100100 T ← Rn ← T 1 MSB ROTCR Rn 0100nnnn00100101 T → Rn → T 1 LSB SHAL Rn 0100nnnn00100000 T ← Rn ← 0 1 MSB SHAR Rn 0100nnnn00100001 MSB → Rn → T 1 LSB SHLL Rn 0100nnnn00000000 T ← Rn ← 0 1 MSB SHLR Rn 0100nnnn00000001 0 → Rn → T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn2 → Rn 1 — SHLL8 Rn 0100nnnn00011000 Rn8 → Rn 1 — SHLL16 Rn 0100nnnn00101000 Rn16 → Rn 1 — Rev. 2.00 Mar 09, 2006 page 82 of 906 REJ09B0292-0200 Section 2 CPU Table 2.24 Branch Instructions Instruction Instruction Code Operation Cycles T Bit — BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC, if T = 1, nop 3/1* BF/S label 10001111dddddddd Delayed branch, if T = 0, disp × 2 + PC → PC, if T = 1, nop 2/1* — BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC, if T = 0, nop 3/1* — BT/S label 10001101dddddddd Delayed branch, if T = 1, disp × 2 + PC → PC, if T = 0, nop 2/1* — BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 2 — BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC 2 — BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 2 — BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 2 — JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2 — JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 2 — 0000000000001011 Delayed branch, PR → PC 2 — RTS Note: * One state when it does not branch. Rev. 2.00 Mar 09, 2006 page 83 of 906 REJ09B0292-0200 Section 2 CPU Table 2.25 System Control Instructions Instruction Instruction Code Operation Cycles T Bit CLRMAC 0000000000101000 0 → MACH, MACL 1 — CLRT 0000000000001000 0→T 1 0 LDC Rm,SR 0100mmmm00001110 Rm → SR 1 LSB LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1 — LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1 — LDC Rm,MOD 0100mmmm01011110 Rm → MOD 1 — LDC Rm,RE 0100mmmm01111110 Rm → RE 1 — LDC Rm,RS 0100mmmm01101110 Rm → RS 1 — LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3 LSB LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3 — LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3 — LDC.L @Rm+,MOD 0100mmmm01010111 (Rm) → MOD, Rm + 4 → Rm 3 — LDC.L @Rm+,RE 0100mmmm01110111 (Rm) → RE, Rm + 4 → Rm 3 — LDC.L @Rm+,RS 0100mmmm01100111 (Rm) → RS, Rm + 4 → Rm 3 — LDRE @(disp,PC) 10001110dddddddd disp × 2 + PC → RE 1 — LDRS @(disp,PC) 10001100dddddddd disp × 2 + PC → RS 1 — LDS Rm,MACH 0100mmmm00001010 Rm → MACH 1 — LDS Rm,MACL 0100mmmm00011010 Rm → MACL 1 — LDS Rm,PR 0100mmmm00101010 Rm → PR 1 — LDS Rm,DSR 0100mmmm01101010 Rm → DSR 1 — LDS Rm,A0 0100mmmm01111010 Rm → A0 1 — LDS Rm,X0 0100mmmm10001010 Rm → X0 1 — LDS Rm,X1 0100mmmm10011010 Rm → X1 1 — LDS Rm,Y0 0100mmmm10101010 Rm → Y0 1 — LDS Rm,Y1 0100mmmm10111010 Rm → Y1 1 — LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → Rm 1 — LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → Rm 1 — LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1 — Rev. 2.00 Mar 09, 2006 page 84 of 906 REJ09B0292-0200 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit LDS.L @Rm+,DSR 0100mmmm01100110 (Rm) → DSR, Rm + 4 → Rm 1 — LDS.L @Rm+,A0 0100mmmm01110110 (Rm) → A0, Rm + 4 → Rm 1 — LDS.L @Rm+,X0 0100mmmm10000110 (Rm) → X0, Rm + 4 → Rm 1 — LDS.L @Rm+,X1 0100mmmm10010110 (Rm) → X1, Rm + 4 → Rm 1 — LDS.L @Rm+,Y0 0100mmmm10100110 (Rm) → Y0, Rm + 4 → Rm 1 — LDS.L @Rm+,Y1 0100mmmm10110110 (Rm) → Y1, Rm + 4 → Rm 1 — NOP 0000000000001001 No operation 1 — RTE 0000000000101011 Delayed branch, stack area → PC/SR 4 LSB 0100mmmm00010100 RE–RS operation result (repeat status) → RF1, RF0 1 — 1 1 SETRC Rm Rm[11:0] → RC (SR[27:16]) SETRC #imm 10000010iiiiiiii RE–RS operation result (repeat status) → RF1, RF0 imm → RC (SR[23:16]), 0 → SR[27:24] SETT 0000000000011000 1→T 1 1 SLEEP 0000000000011011 Sleep 3* — STC SR,Rn 0000nnnn00000010 SR → Rn 1 — STC GBR,Rn 0000nnnn00010010 GBR → Rn 1 — STC VBR,Rn 0000nnnn00100010 VBR → Rn 1 — STC MOD,Rn 0000nnnn01010010 MOD → Rn 1 — STC RE,Rn 0000nnnn01110010 RE → Rn 1 — STC RS,Rn 0000nnnn01100010 RS → Rn 1 — STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 2 — STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 2 — STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, VBR → (Rn) 2 — STC.L MOD,@–Rn 0100nnnn01010011 Rn–4 → Rn, MOD → (Rn) 2 — STC.L RE,@–Rn 0100nnnn01110011 Rn–4 → Rn, RE → (Rn) 2 — STC.L RS,@–Rn 0100nnnn01100011 Rn–4 → Rn, RS → (Rn) 2 — Rev. 2.00 Mar 09, 2006 page 85 of 906 REJ09B0292-0200 Section 2 CPU Instruction Instruction Code Operation Cycles T Bit STS MACH,Rn 0000nnnn00001010 MACH → Rn 1 — STS MACL,Rn 0000nnnn00011010 MACL → Rn 1 — STS PR,Rn 0000nnnn00101010 PR → Rn 1 — STS DSR,Rn 0000nnnn01101010 DSR → Rn 1 — STS A0,Rn 0000nnnn01111010 A0 → Rn 1 — STS X0,Rn 0000nnnn10001010 X0 → Rn 1 — STS X1,Rn 0000nnnn10011010 X1 → Rn 1 — STS Y0,Rn 0000nnnn10101010 Y0 → Rn 1 — STS Y1,Rn 0000nnnn10111010 Y1 → Rn 1 — STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1 — STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1 — STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn) 1 — STS.L DSR,@–Rn 0100nnnn01100010 Rn–4 → Rn, DSR → (Rn) 1 — STS.L A0,@–Rn 0100nnnn01110010 Rn–4 → Rn, A0 → (Rn) 1 — STS.L X0,@–Rn 0100nnnn10000010 Rn–4 → Rn, X0 → (Rn) 1 — STS.L X1,@–Rn 0100nnnn10010010 Rn–4 → Rn, X1 → (Rn) 1 — STS.L Y0,@–Rn 0100nnnn10100010 Rn–4 → Rn, Y0 → (Rn) 1 — STS.L Y1,@–Rn 0100nnnn10110010 Rn–4 → Rn, Y1 → (Rn) 1 — TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm × 4 + VBR) → PC 8 — Note: * The number of execution cycles before the chip enters sleep mode. Rev. 2.00 Mar 09, 2006 page 86 of 906 REJ09B0292-0200 Section 2 CPU Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles listed in the tables are minimum values. In practice, the number of execution cycles increases under such conditions as 1) when the instruction fetch is in contention with a data access, 2) when the destination register of a load instruction (memory → register) is the same as the register used by the next instruction, 3) when the branch destination address of a branch instruction is a 4n + 2 address. CPU Instructions That Support DSP Functions: A number of system control instructions have been added to the CPU core instructions to support DSP functions. The RS, RE and MOD registers have been added to support repeat control and modulo addressing, and the repeat counter (RC) has been added to the status register (SR). The LDC and STC instructions have been added in order to access the aforementioned. The LDS and STS instructions have been added in order to access the DSP registers DSR, A0, X0, X1, Y0 and Y1. The SETRC instruction has been added to set the repeat counter (RC, bits 27 to 16) and repeat flags (RF1, RF0, bits 3 and 2) of the SR register. When the SETRC instruction operand is immediate, the 8-bit immediate data is stored in bits 23 to 16 of the SR register and bits 27 to 24 are cleared to 0. When the operand is a register, bits 11 to 0 (12 bits) of the register are stored in bits 27 to 16 of the SR register. Additionally, the status of 1 instruction repeat (00), 2 instruction repeat (01), 3 instruction repeat (11) or 4 instruction or greater repeat (10) is set from the RS and RE set values. In addition to the LDC instruction, the LDRS and LDRE instructions have been added for establishing the repeat start and repeat end addresses in the RS and RE registers. The added instructions are listed in table 2.26. Rev. 2.00 Mar 09, 2006 page 87 of 906 REJ09B0292-0200 Section 2 CPU Table 2.26 Added CPU Instructions Instruction Code Operation Cycles T Bit LDC Rm,MOD 0100mmmm01011110 Rm→MOD 1 — LDC Rm,RE 0100mmmm01111110 Rm→RE 1 — LDC Rm,RS 0100mmmm01101110 Rm→RS 1 — LDC.L @Rm+,MOD 0100mmmm01010111 (Rm)→MOD,Rm+4→Rm 3 — LDC.L @Rm+,RE 0100mmmm01110111 (Rm)→RE,Rm+4→Rm 3 — LDC.L @Rm+,RS 0100mmmm01100111 (Rm)→RS,Rm+4→Rm 3 — STC MOD,Rn 0000nnnn01010010 MOD→Rn 1 — STC RE,Rn 0000nnnn01110010 RE→Rn 1 — STC RS,Rn 0000nnnn01100010 RS→Rn 1 — STC.L MOD,@-Rn 0100nnnn01010011 Rn–4→Rn,MOD→(Rn) 2 — STC.L RE,@-Rn 0100nnnn01110011 Rn–4→Rn,RE→(Rn) 2 — STC.L RS,@-Rn 0100nnnn01100011 Rn–4→Rn,RS→(Rn) 2 — LDS Rm,DSR 0100mmmm01101010 Rm→DSR 1 — LDS.L @Rm+,DSR 0100mmmm01100110 (Rm)→DSR,Rm+4→Rm 1 — LDS Rm,A0 0100mmmm01111010 Rm→A0 1 — LDS.L @Rm+,A0 0100mmmm01110110 (Rm)→A0,Rm+4→Rm 1 — LDS Rm,X0 0100mmmm10001010 Rm→X0 1 — LDS.L @Rm+,X0 0100mmmm10000110 (Rm)→X0,Rm+4→Rm 1 — LDS Rm,X1 0100mmmm10011010 Rm→X1 1 — LDS.L @Rm+,X1 0100mmmm10010110 (Rm)→X1,Rm+4→Rm 1 — LDS Rm,Y0 0100mmmm10101010 Rm→Y0 1 — LDS.L @Rm+,Y0 0100mmmm10100110 (Rm)→Y0,Rm+4→Rm 1 — LDS Rm,Y1 0100mmmm10111010 Rm→Y1 1 — LDS.L @Rm+,Y1 0100mmmm10110110 (Rm)→Y1,Rm+4→Rm 1 — STS DSR,Rn 0000nnnn01101010 DSR→Rn 1 — STS.L DSR,@-Rn 0100nnnn01100010 Rn–4→Rn,DSR→(Rn) 1 — STS A0,Rn 0000nnnn01111010 A0→Rn 1 — STS.L A0,@-Rn 0100nnnn01110010 Rn–4→Rn,A0→(Rn) 1 — STS X0,Rn 0000nnnn10001010 X0→Rn 1 — STS.L X0,@-Rn 0100nnnn10000010 Rn–4→Rn,X0→(Rn) 1 — STS X1,Rn 0000nnnn10011010 X1→Rn 1 — Rev. 2.00 Mar 09, 2006 page 88 of 906 REJ09B0292-0200 Section 2 CPU Instruction Code Operation Cycles T Bit STS.L X1,@-Rn 0100nnnn10010010 Rn–4→Rn,X1→(Rn) 1 — STS Y0,Rn 0000nnnn10101010 Y0→Rn 1 — STS.L Y0,@-Rn 0100nnnn10100010 Rn–4→Rn,Y0→(Rn) 1 — STS Y1,Rn 0000nnnn10111010 Y1→Rn 1 — STS.L Y1,@-Rn 0100nnnn10110010 Rn–4→Rn,Y1→(Rn) 1 — SETRC Rm 0100mmmm00010100 Rm[11:0]→RC (SR[27:16]) 1 — SETRC #imm 10000010iiiiiiii imm→RC(SR[23:16]), 0→SR[27:24] 1 — LDRS @(disp,PC) 10001100dddddddd disp × 2+PC→RS 1 — LDRE @(disp,PC) 10001110dddddddd disp × 2+PC→RE 1 — 2.5.2 DSP Data Transfer Instruction Set Table 2.27 lists the DSP data transfer instructions by classification. Table 2.27 Classification of DSP Data Transfer Instructions Classification Types Double 4 datatransferinstr uctions Single data transfer instructions 1 Total: 5 Operation Code Function No. of Instructions NOPX X memory no operation 14 MOVX X memory data transfer NOPY Y memory no operation MOVY Y memory data transfer MOVS Single data transfer 16 Total: 30 The data transfer instructions are divided into two groups, double data transfers and single data transfers. Double data transfers can be combined with DSP operation instructions to perform DSP parallel processing. The parallel processing instructions are 32 bit length, and the double data transfer instructions are incorporated into their A fields. Double data transfers that are not parallel processing instructions are 16 bit length, as are the single data transfer instructions. The X memory and Y memory can be accessed simultaneously in parallel in double data transfers. One instruction each is designated from among the X and Y memory data accesses. The Ax Rev. 2.00 Mar 09, 2006 page 89 of 906 REJ09B0292-0200 Section 2 CPU pointer is used to access X memory; the Ay pointer is used to access Y memory. Double data transfers can only access X, Y memory. Single data transfers can be accessed from any area. Single data transfers use the Ax pointer and two other pointers as an As pointer. Table 2.28 Double Data Transfer Instructions (X Memory Data) Instruction Operation Code Cycles DC Bit NOPX No Operation 1111000*0*0*00** 1 — MOVX.W @Ax,Dx (Ax)→MSW of Dx,0→LSW of Dx 111100A*D*0*01** 1 — MOVX.W @Ax+,Dx (Ax)→MSW of Dx,0→LSW of Dx,Ax+2→Ax 111100A*D*0*10** 1 — MOVX.W @Ax+Ix,Dx (Ax)→MSW of Dx,0→LSW of Dx,Ax+Ix→Ax 111100A*D*0*11** 1 — MOVX.W Da,@Ax MSW of Da→(Ax) 111100A*D*1*01** 1 — MOVX.W Da,@Ax+ MSW of Da→(Ax),Ax+2→Ax 111100A*D*1*10** 1 — MOVX.W Da,@Ax+Ix MSW of Da→(Ax),Ax+Ix→Ax 111100A*D*1*11** 1 — Table 2.29 Double Data Transfer Instructions (Y Memory Data) Instruction Operation Code Cycles DC Bit NOPY No Operation 111100*0*0*0**00 1 — MOVY.W @Ay,Dy (Ay)→MSW of Dy,0→LSW of Dy 111100*A*D*0**01 1 — MOVY.W @Ay+,Dy (Ay)→MSW of Dy,0→LSW of Dy, Ay+2→Ay 111100*A*D*0**10 1 — MOVY.W @Ay+Iy,Dy (Ay)→MSW of Dy,0→LSW of Dy, Ay+Iy→Ay 111100*A*D*0**11 1 — MOVY.W Da,@Ay MSW of Da→(Ay) 111100*A*D*1**01 1 — MOVY.W Da,@Ay+ MSW of Da→(Ay),Ay+2→Ay 111100*A*D*1**10 1 — MOVY.W Da,@Ay+Iy MSW of Da→(Ay),Ay+Iy→Ay 111100*A*D*1**11 1 — Rev. 2.00 Mar 09, 2006 page 90 of 906 REJ09B0292-0200 Section 2 CPU Table 2.30 Single Data Transfer Instructions Instruction Operation Code Cycles DC Bit MOVS.W @-As,Ds As–2→As,(As)→MSW of Ds,0→LSW of Ds 111101AADDDD0000 1 — MOVS.W @As,Ds (As)→MSW of Ds,0→LSW of Ds 111101AADDDD0100 1 — MOVS.W @As+,Ds (As)→MSW of Ds,0→LSW of Ds, As+2→As 111101AADDDD1000 1 — MOVS.W @As+Ix,Ds (As)→MSW of Ds,0→LSW of Ds, As+Ix→As 111101AADDDD1100 1 — MOVS.W Ds,@-As As–2→As,MSW of Ds→(As)* 111101AADDDD0001 1 — MOVS.W Ds,@As MSW of Ds→(As)* MSW of Ds→(As)*,As+2→As 111101AADDDD0101 1 — 111101AADDDD1001 1 — MOVS.W Ds,@As+Is MSW of Ds→(As)*,As+Is→As 111101AADDDD1101 1 — MOVS.L @-As,Ds As–4→As,(As)→Ds 111101AADDDD0010 1 — MOVS.L @As,Ds (As)→Ds 111101AADDDD0110 1 — MOVS.L @As+,Ds (As)→Ds,As+4→As 111101AADDDD1010 1 — MOVS.L @As+Is,Ds (As)→Ds,As+Is→As 111101AADDDD1110 1 — MOVS.L Ds, @-As As–4→As,Ds→(As)* 111101AADDDD0011 1 — MOVS.L Ds,@As Ds→(As)* Ds→(As)*,As+4→As 111101AADDDD0111 1 — 111101AADDDD1011 1 — Ds→(As)*,As+Is→As 111101AADDDD1111 1 — MOVS.W Ds,@As+ MOVS.L Ds,@As+ MOVS.L Ds,@As+Is Note: * When guard bit registers A0G and A1G are specified for the source operand Ds, data is sign-extended before being transferred. Rev. 2.00 Mar 09, 2006 page 91 of 906 REJ09B0292-0200 Section 2 CPU Table 2.31 shows the correspondence between the DSP data transfer operands and registers. CPU core registers are used as pointer addresses indicating memory addresses. Table 2.31 Correspondence between DSP Data Transfer Operands and Registers SH (CPU Core) Registers R1 R2 (As2) R3 (As3) R4 (Ax0) (As0) R5 (Ax1) (As0) R6 (Ay0) R7 (Ay1) R8 (Ix) (Is) R9 (Iy) — — — — Yes Yes — — — — — — — — — — — — Yes — Dx — — — — — — — — — — Ay — — — — — — Yes Yes — — Iy — — — — — — — — — Yes Dy — — — — — — — — — — Da — — — — — — — — — — As — — Yes Yes Yes Yes — — — — Ds — — — — — — — — — — Operand R0 Ax Ix (Is) DSP Registers Operand X0 X1 Y0 Y1 M0 M1 A0 A1 A0G A1G Ax — — — — — — — — — — Ix (Is) — — — — — — — — — — Dx Yes Yes — — — — — — — — Ay — — — — — — — — — — Iy — — — — — — — — — — Dy — — Yes Yes — — — — — — Da — — — — — — Yes Yes — — As — — — — — — — — — — Ds Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note: Yes indicates that the register can be set. Rev. 2.00 Mar 09, 2006 page 92 of 906 REJ09B0292-0200 Section 2 CPU 2.5.3 DSP Operation Instruction Set DSP operation instructions are digital signal processing instructions processed by the DSP unit. These instructions use 32-bit instruction codes, and multiple instructions are executed in parallel. The instruction codes are divided into an A field and a B field; parallel data transfer instructions are designated in the A field, and single or double data operation instructions are designated in the B field. Instructions can be independently designated and execution can also be carried out independently. A parallel data transfer instruction designated in the A field is exactly the same as a double data transfer instruction. The B field data operation instructions are divided into three groups: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. Table 2.32 lists the instruction formats of the DSP operation instructions. Each of the operands can be independently selected from the DSP registers. Table 2.33 shows the correspondence between the DSP operation instruction operands and registers. Table 2.32 DSP Operation Instruction Formats Classification Instruction Forms Double data operation instructions (6 operands) Conditional single data operation instructions 3 operands 2 operands Instruction ALUop. Sx, Sy, Du PADD PMULS, MLTop. Se, Sf, Dg PSUB PMULS ALUop. Sx, Sy, Dz PADD, PAND, POR, DCT ALUop. Sx, Sy, Dz PSHA, PSHL, PSUB, PXOR DCF ALUop. Sx, Sy, Dz ALUop. Sx, Dz DCT ALUop. Sx, Dz DCF ALUop. Sx, Dz PCOPY, PDEC, PDMSB, PINC, PLDS, PSTS, PNEG ALUop. Sy, Dz DCT ALUop. Sy, Dz DCF ALUop. Sy, Dz 1 operand ALUop. Dz DCT ALUop. Dz PCLR, PSHA #imm, PSHL #imm DCF ALUop. Dz Unconditional single data operation instructions 3 operands ALUop. Sx, Sy, Du PADDC, PSUBC, MLTop. Se, Sf, Dg PMULS 2 operands ALUop. Sx, Dz PCMP, PABS, PRND ALUop. Sy, Dz ALUop. Sx, Sy 1 operand ALUop. Dz PSHA #imm, PSHL #imm Rev. 2.00 Mar 09, 2006 page 93 of 906 REJ09B0292-0200 Section 2 CPU Table 2.33 Correspondence between DSP Instruction Operands and Registers ALU and BPU Instructions Multiplication Instructions Register Sx Sy Dz Du Se Sf Dg A0 Yes — Yes Yes — — Yes A1 Yes — Yes Yes Yes Yes Yes M0 — Yes Yes — — — Yes M1 — Yes Yes — — — Yes X0 Yes — Yes Yes Yes Yes — X1 Yes — Yes — Yes — — Y0 — Yes Yes Yes Yes Yes — Y1 — Yes Yes — — Yes — When writing parallel instructions, write the B field instructions first, then write the A field instructions: PADD A0,M0,A0 PMULS X0,Y0,M0 DCF PINC X1,A1 PCMP X1,M0 MOVX.W @R4+,X0 MOVY.W @R6+,Y0[;] MOVX.W A0,@R5+R8 MOVY.W @R7+,Y0[;] MOVX.W @R4+R8 [NOPY][;] Text in brackets ([]) can be omitted. The no operation instructions NOPX and NOPY can be omitted. Semicolons (;) are used to demarcate instruction lines, but can be omitted. If semicolons are used, the space after the semicolon can be used for comments. The individual status codes (DC, N, Z, V, GT) of the DSR register are always updated by unconditional ALU operation instructions and shift operation instructions. Conditional instructions do not update the status codes, even if the conditions have been met. Multiplication instructions also do not update the status codes. DC bit definitions are determined by the specifications of the CS bits in the DSR register. Table 2.34 lists the DSP operation instructions by classification. Rev. 2.00 Mar 09, 2006 page 94 of 906 REJ09B0292-0200 Section 2 CPU Table 2.34 Classification of DSP Instructions Classification Instruction Types ALU arith- ALU fixed decimal 11 metic point operation operation instructions instructions instructions Function PABS Absolute value operation PADD Addition PADD PMULS Addition and signed multiplication PADDC Addition with carry PCLR Clear PCMP Compare PCOPY Copy PNEG Invert sign PSUB Subtraction PSUB PMULS Subtraction and signed multiplication No. of Instructions 28 PSUBC Subtraction with borrow PDEC Decrement PINC Increment 1 PDMSB MSB detection 6 1 PRND Rounding 2 3 PAND Logical AND 9 ALU integer operation instructions 2 MSB detection instruction Rounding operation instruction ALU logical operation instructions Operation Code POR Logical OR PXOR Logical exclusive OR 12 Fixed decimal point multiplication instruction 1 PMULS Signed multiplication 1 Shift Arithmetic shift operation instruction 1 PSHA Arithmetic shift 4 Logical shift operation instruction 1 PSHL Logical shift 4 2 PLDS System register load 12 PSTS Store from system register System control instructions Total 23 Total 78 Rev. 2.00 Mar 09, 2006 page 95 of 906 REJ09B0292-0200 Section 2 CPU 2.5.4 Various Operation Instructions ALU Arithmetic Operation Instructions: Tables 2.35–2.44 list various operation instructions. Table 2.35 ALU Fixed Point Operation Instructions Instruction Operation Code Cycles DC Bit PABS Sx,Dz If Sx≥0,Sx→Dz 111110********** 1 Update If Sx channel 1) 1 Round-robin (Top priority shifts to bottom after each transfer. The priority for the first DMA transfer after a reset is channel 1 > channel 0) (Initial value) Rev. 2.00 Mar 09, 2006 page 475 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in the DMAC. When the AE bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it and then write 0. Operation is performed up to the DMAC transfer being executed when the address error occurred. AE is initialized to 0 by a reset and in standby mode. It retains its value when the module standby function is used. Bit 2: AE Description 0 No DMAC address error To clear the AE bit, read 1 from it and then write 0 1 Address error by DMAC (Initial value) Bit 1—NMI Flag Bit (NMIF): This flag indicates that an NMI interrupt has occurred. When the NMIF bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the DMA channel control register (CHCR) and the DME bit are set to 1. To clear the NMIF bit, read 1 from it and then write 0. Operation is completed up to the end of the DMAC transfer being executed when NMI was input. When the NMI interrupt is input while the DMAC is not operating, the NMIF bit is set to 1. The NMIF bit is initialized to 0 by a reset or in the standby mode. It retains its value when the module standby function is used. Bit 1: NMIF Description 0 No NMIF interrupt To clear the NMIF bit, read 1 from it and then write 0 1 NMIF interrupt has occurred (Initial value) Bit 0—DMA Master Enable Bit (DME): Enables or disables DMA transfers on all channels. A DMA transfer becomes enabled when the DE bit in the CHCR and the DME bit are set to 1. For this to be effective, the TE bit in CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are aborted. DME is initialized to 0 by a reset and in standby mode. It retains its value when the module standby function is used. Bit 0: DME Description 0 DMA transfers disabled on all channels 1 DMA transfers enabled on all channels Rev. 2.00 Mar 09, 2006 page 476 of 906 REJ09B0292-0200 (Initial value) Section 11 Direct Memory Access Controller (DMAC) 11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer-end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request. A transfer can be in either single address mode or dual address mode. The bus mode can be either burst or cycle-steal. 11.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (TCR), DMA channel control registers (CHCR), DMA vector number registers (VCRDMA), DMA request/response selection control registers (DRCR), and DMA operation register (DMAOR) are initialized (initializing sets each register so that ultimately the condition (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) is satisfied), the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) 2. When a transfer request occurs and transfer is enabled, the DMAC transfers 1 transfer unit of data. (In auto-request mode, the transfer begins automatically after register initialization. The TCR value will be decremented by 1.) The actual transfer flows vary depending on the address mode and bus mode. 3. When the specified number of transfers have been completed (when TCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt request is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Figure 11.2 shows a flowchart illustrating this procedure. Rev. 2.00 Mar 09, 2006 page 477 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, TCR, CHCR, VCRDMA, DRCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Has a transfer request been generated?*1 *2 No *3 Yes Bus mode, transfer request mode, DREQ detection method? Transfer TCR-1 → TCR, SAR, and DAR updated *4 No TCR = 0? 16-byte transfer in progress? Yes DEI interrupt request (when IE = 1) NMIF = 1, or AE = 1, or DE = 0, or DME = 0? *5 NMIF = 1, No or AE = 1, or DE = 0, or DME = 0? Yes No Transfer aborted Yes TE = 1 TE = 1 End transfer End normally Notes: 1. In auto-request mode, the transfer will start when the NMIF, AE, and TE bits are all 0 and the DE and DME bits are then set to 1. 2. Cycle-steal mode. 3. In burst mode, DREQ = edge detection (external request), or auto-request mode in burst mode. 4. 16-byte transfer cycle in progress. 5. End of a 16-byte transfer cycle. Figure 11.2 DMA Transfer Flow Rev. 2.00 Mar 09, 2006 page 478 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 11.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The request mode is selected with the AR bit in DMA channel control registers 0 and 1 (CHCR0, CHCR1) and the RS0, RS1, RS2, RS3 and RS4 bits in DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1). Table 11.3 Selecting the DMA Transfer Request Using the AR and RS Bits CHCR DRCR AR RS4 RS3 RS2 RS1 RS0 Request Mode Resource Selection 0 0 0 0 0 0 Module request mode DREQ (external request) 1 0 1 SCIF channel 1 RXI 1 0 SCIF channel 1 TXI 0 0 1 SCIF channel 2 RXI 1 0 SCIF channel 2 TXI 1 0 1 1 1 0 1 1 * * 0 TPU TGI0A 1 TPU TGI0B 0 TPU TGI0C 1 TPU TGI0D 0 SIOF RDFI 1 0 SIOF TDEI 1 0 1 SIO channel 1 RDFI 1 0 SIO channel 1 TDEI 0 0 1 SIO channel 2 RDFI 1 0 SIO channel 2 TDEI * * * Auto-request mode Note: * Don’t care Auto-Request Mode: When there is no transfer request signal from an external source (as in a memory-to-memory transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0 and CHCR1 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bits in CHCR0 and CHCR1 and the NMIF and AE bits in DMAOR are all 0). Rev. 2.00 Mar 09, 2006 page 479 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) External Request Mode: In this mode a transfer is started by a transfer request signal (DREQn) from an external device. Choose one of the modes shown in table 11.4 according to the application system. When DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon input of a DREQn signal. Table 11.4 Selecting External Request Modes with the TA and AM Bits CHCR TA 0 1 AM Transfer Address Mode Acknowledge Mode Source Destination Any* Any* 0 Dual address mode DACKn output in read cycle Any* 1 Dual address mode DACKn output in write cycle Any* 0 Single address mode Data transferred from memory to device External memory or External device memory-mapped with DACK external device 1 Single address mode Data transferred from device to memory External device with DACK External memory or memory-mapped external device Note: * External memory, memory-mapped external device, and on-chip peripheral module (excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC). Choose to detect DREQn either by the falling edge or by level using the DS and DL bits in CHCR0 and CHCR1 (DS = 0 is level detection, DS = 1 is edge detection; DL = 0 is active-low, DL = 1 is active-high). The source of the transfer request does not have to be the data transfer source or destination. When 0 (level detection) is set to the DS bit of CHCR0 and CHCR1, set the TB bit to 0 (cyclesteal mode) and set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word unit), or 10 (long word unit). When 0 is set to the DS bit of CHCR0 and CHCR1, when 1 (burst mode) is set to the TB bit of CHCR0 and CHCR1, and when 11 (16 byte unit) is set to the TS1 and TS0 bits of CHCR1 and CHCR1, operation is not guaranteed. Rev. 2.00 Mar 09, 2006 page 480 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Table 11.5 Selecting the External Request Signal with the DS and DL Bits CHCR DS DL External Request 0 0 Low-level detection (can only be set in cycle-steal mode) 1 High-level detection (can only be set in cycle-steal mode) 0 Falling-edge detection 1 Rising-edge detection 1 On-Chip Module Request Mode: In this mode, transfers are started by a transfer request signal (interrupt request signal) from an on-chip peripheral module. Transfer request signals include SCIF, SIOF or SIO receive-data-full interrupts (RXI, RDFI), SCIF, SIOF or SIO transmit-dataempty interrupts (TXI, TDEI), and TPU general registers (table 11.6). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), DMA transfer starts upon input of a transfer request signal. When RXI or RDFI (transfer request due to an SCIF, SIOF or SIO receive-data-full condition) is set as a transfer request, the transfer source must be the receive data register of the corresponding module (SCFRDR or SIRDR). When TXI or TDEI (transfer request due to an SCIF, SIOF or SIO transmit-data-empty condition) is set as a transfer request, the transfer destination must be the transmit data register of the corresponding module (SCFTDR or SITDR). These restrictions do not apply to TPU transfer requests. When on-chip module request mode is used, an access size permitted by the peripheral module register used as the transfer source or transfer destination must be set in bits TS1 and TS0 of CHCR0 and CHCR1. Rev. 2.00 Mar 09, 2006 page 481 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Table 11.6 Selecting On-Chip Peripheral Module Request Mode with the AR and RS Bits AR DMA DMA Transfer Transfer Request Request RS4 RS3 RS2 RS1 RS0 Source Signal Transfer Source 0 0 0 1 1 0 1 0 0 1 1 0 Bus Mode DREQ Setting Cyclesteal Edge, active-low SCFTDR1 Cyclesteal Edge, active-low 0 1 SCIF channel 1 RXI receiver SCFRDR1 Any 1 0 SCIF channel 1 TXI transmitter Any 0 1 SCIF channel 2 RXI receiver SCFRDR2 Any 1 0 SCIF channel 2 TXI transmitter 0 0 TPU channel 0A 1 Cyclesteal Edge, active-low Any SCFTDR2 Cyclesteal Edge, active-low TGI0A Any (excluding on-chip RAM) Any Cycle(excluding steal on-chip RAM) Edge, active-low TPU channel 0B TGI0B Any (excluding on-chip RAM) Any Cycle(excluding steal on-chip RAM) Edge, active-low 0 TPU channel 0C TGI0C Any (excluding on-chip RAM) Any Cycle(excluding steal on-chip RAM) Edge, active-low 1 TPU channel 0D TGI0D Any (excluding on-chip RAM) Any Cycle(excluding steal on-chip RAM) Edge, active-low 0 1 SIOF receiver RDFI SIRDR Any Cyclesteal Edge, active-low 1 0 SIOF transmitter TDEI Any SITDR Cyclesteal Edge, active-low 0 1 SIO channel 1 receiver RDFI SIRDR1 Any Cyclesteal Edge, active-low 1 0 SIO channel 1 transmitter TDEI Any SITDR1 Cyclesteal Edge, active-low 0 1 SIO channel 2 receiver RDFI SIRDR2 Any Cyclesteal Edge, active-low 1 0 SIO channel 2 transmitter TDEI Any SITDR2 Cyclesteal Edge, active-low 1 1 Transfer Destination Rev. 2.00 Mar 09, 2006 page 482 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) For outputting transfer request from the SCIF, SIOF, SIO, and TPU, the corresponding interrupt enable bits must be set to output the interrupt signals. Note that transfer request signals from onchip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip peripheral module is specified as the transfer request source, set the priority level values in the interrupt priority level registers (IPRC–IPRE) of the interrupt controller (INTC) at or below the levels set in the I3–I0 bits of the CPU’s status register so that the CPU does not accept the interrupt request signal. With the DMA transfer request signals in table 11.6, when DMA transfer is performed a DMA transfer request (interrupt request) from any module will be cleared at the first transfer. 11.3.3 Channel Priorities When the DMAC receives simultaneous transfer requests on two channels, it selects a channel according to a predetermined priority order. There is a choice of two priority modes, fixed or round-robin. The mode is selected by the priority bit, PR, in the DMA operation register (DMAOR). Fixed Priority Mode: In this mode, the relative channel priority levels are fixed. When PR is set to 0, channel 0 has higher priority than channel 1. Figure 11.3 shows an example of a transfer in burst mode. DREQ0 DREQ1 Bus cycle Channel 0 destination CPU CPU Channel 0 destination Channel 1 destination CPU Channel 0 source Channel 0 source Channel 1 source Figure 11.3 Fixed Mode DMA Transfer in Burst Mode (Dual Address, DREQn Falling-Edge Detection) In cycle-steal mode, once a channel 0 request is accepted, channel 1 requests are also accepted until the next request is accepted, which makes more effective use of the bus cycle. If requests come simultaneously for channel 0 and channel 1 when DMA operation is starting, the first is transmitted with channel 0, and thereafter channel 1 and channel 0 transfers are performed alternately. Rev. 2.00 Mar 09, 2006 page 483 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) DREQ0 DREQ1 Bus cycle Channel 0 source CPU CPU CPU Channel 1 source CPU Channel 0 destination Channel 0 source CPU Channel 1 destination Figure 11.4 Fixed Mode DMA Transfer in Cycle-Steal Mode (Dual Address, DREQn Low-Level Detection) Round-Robin Mode: Switches the priority of channel 0 and channel 1, shifting their ability to receive transfer requests. Each time one transfer ends on one channel, the priority shifts to the other channel. The channel on which the transfer just finished is assigned low priority. After reset, channel 1 has higher priority than channel 0. Figure 11.5 shows how the priority changes when channel 0 and channel 1 transfers are requested simultaneously and another channel 0 transfer is requested after the first two transfers end. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 1 and 0. 2. Channel 1 has the higher priority, so the channel 1 transfer begins first (channel 0 waits for transfer). 3. When the channel 1 transfer ends, channel 1 becomes the lower-priority channel. 4. The channel 0 transfer begins. 5. When the channel 0 transfer ends, channel 0 becomes the lower-priority channel. 6. A channel 0 transfer is requested. 7. The channel 0 transfer begins. 8. When the channel 0 transfer ends, channel 0 is already the lower-priority channel, so the order remains the same. Rev. 2.00 Mar 09, 2006 page 484 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Transfer requests Waiting channel 1. Requests occur in channels 0 and 1 DMAC operation Channel priority order 2. Channel 1 transfer starts 0 3. Channel 1 transfer ends 1>0 Priority changes 0>1 4. Channel 0 transfer starts None 5. Channel 0 transfer ends 7. Channel 0 transfer starts 6. Request occurs in channel 0 None 8. Channel 0 transfer ends Priority changes 1>0 Waiting for transfer request Priority does not change 1>0 Figure 11.5 Channel Priority in Round-Robin Mode Rev. 2.00 Mar 09, 2006 page 485 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 11.3.4 DMA Transfer Types It can operate in single address mode or dual address mode, as defined by how many bus cycles the DMAC takes to access the transfer source and transfer destination. The actual transfer operation timing varies with the DMAC bus mode used: cycle-steal mode or burst mode. The DMAC supports all the transfers shown in table 11.7. Table 11.7 Supported DMA Transfers Destination External Device with DACK External Memory On-Chip Memory-Mapped Peripheral External Device Module External device with DACK Not available Single Single Not available Not available External memory Single Dual Dual Dual Memory-mapped external device Single Dual Dual Dual* Dual* On-chip peripheral module Not available Dual* Dual* Dual* Dual* On-chip memory Not available Dual Dual Dual* Dual Source On-Chip Memory Dual Single: Single address mode Dual: Dual address mode Note: * Access size permitted by peripheral module register used as transfer source or transfer destination (excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC). Address Modes: • Single Address Mode In single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACKn signal while the other is accessed by address. In this mode, the DMAC performs the DMA transfer in one bus cycle by simultaneously outputting a transfer request acknowledge DACKn signal to one external device to access it, while outputting an address to the other end of the transfer. Figure 11.6 shows an example of a transfer between external memory and external device with DACK. That data is written in external memory in the same bus cycle while the external device outputs data to the data bus. Rev. 2.00 Mar 09, 2006 page 486 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) External address bus External data bus Chip External memory DMAC External device with DACK DACKn DREQn : Data flow Figure 11.6 Data Flow in Single Address Mode Two types of transfers are possible in single address mode: 1) transfers between external devices with DACK and memory-mapped external devices; and 2) transfers between external devices with DACK and external memory. For both of them, transfer must be requested by the external request signal (DREQn). For the combination of the specifiable setting to perform data transfer using an external request (DREQn), see table 11.9. Figure 11.7 shows the DMA transfer timing for single address mode. Rev. 2.00 Mar 09, 2006 page 487 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) CKIO Address output to external memory space A24–A0 CS Write strobe signal to external memory space WE Data output from external device with DACK DACK signal (active low) to external device with DACK D31–D0 DACKn BS a. External device with DACK to external memory space CKIO Address output to external memory space A24–A0 CS Read strobe signal to external memory space RD Data output from external memory space D31–D0 DACK signal (active low) to external device with DACK DACKn BS b. External memory space to external device with DACK Figure 11.7 DMA Transfer Timing in Single Address Mode Rev. 2.00 Mar 09, 2006 page 488 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) • Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selectable) by address. The source and destination can be located externally or internally. The DMAC accesses the source in the read cycle and the destination in the write cycle, so the transfer is performed in two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 11.8 shows an example of a transfer between two external memories in which data is read from one external memory in the read cycle and written to the other external memory in the following write cycle. External data bus Chip 2 DMAC External memory External memory 1 : Data flow 1: Read cycle 2: Write cycle Figure 11.8 Data Flow in Dual Address Mode In dual address mode transfers, external memory and memory-mapped external devices can be mixed without restriction. Specifically, this enables transfers between the following:  Transfer between external memory and external memory  Transfer between external memory and memory-mapped external device  Transfer between memory-mapped external device and memory-mapped external device  Transfer between external memory and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)*  Transfer between memory-mapped external device and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)*  Transfer between on-chip memory and on-chip memory  Transfer between on-chip memory and memory-mapped external device  Transfer between on-chip memory and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Rev. 2.00 Mar 09, 2006 page 489 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC)  Transfer between on-chip memory and external memory  Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, EDMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC)* Note: * Access size permitted by peripheral module register used as transfer source or transfer destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC). Transfer requests can be auto-request, external requests, or on-chip peripheral module requests. If the transfer request source is the SCIF, SIOF or SIO, an SCIF, SIOF or SIO register, respectively, must be the transfer destination or transfer source (see table 11.6). For the combination of the specifiable setting to perform data transfer using an external request (DREQn), see table 11.9. Dual address mode outputs DACKn in either the read cycle or write cycle. The acknowledge/transfer mode bit (AM) of the DMA channel control registers 0 and 1 (CHCR0 and 1) specifies whether DACK is output in either the read cycle or the write cycle. Figure 11.9 shows the DMA transfer timing in dual address mode. CKIO A24–A0 Address output to external memory space CS RD Read strobe signal to external memory space WE Write strobe signal to external memory space D31–D0 DACKn I/O data of external memory space DMAC acknowledge signal (active-low) BS Figure 11.9 DMA Transfer Timing in Dual Address Mode (External Memory Space → External Memory Space, DACKn Output in Read Cycle) Rev. 2.00 Mar 09, 2006 page 490 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TB bits in CHCR0 and CHCR1. • Cycle-Steal Mode In cycle-steal mode, the bus right is given to another bus master each time the DMAC completes one transfer. When another transfer request occurs, the bus right is retrieved from the other bus master and another transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. (in the case of 16-byte transfer in dual address mode, the DMAC continues to hold the bus) Cycle-steal mode can be used with all categories of transfer destination, transfer source, and transfer request source. (with the exception of transfers between on-chip peripheral modules) The CPU may take the bus twice when an acknowledge signal is output during the write cycle or in single address mode. Figure 11.10 shows an example of DMA transfer timing in cyclesteal mode. The transfer conditions for the example in the figure are as shown below. When the transfer request source is an external request mode with level detection in the cyclesteal mode, set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word unit), or 01 (longword unit). If the TS1 and TS0 bits of CHCR0 and CHCR1 are set to 11 (16byte transfer), operation is not guaranteed. • Dual address mode • DREQn level detection DREQn Bus right returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC Read Write CPU Figure 11.10 DMA Transfer Timing in Cycle-Steal Mode (Dual Address Mode, DREQn Low Level Detection) Rev. 2.00 Mar 09, 2006 page 491 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) • Burst Mode In burst mode, once the DMAC gets the bus, the transfer continues until the transfer end condition is satisfied. When external request mode is used with level detection of the DREQ pin, however, negating DREQ will pass the bus to the other bus master after completion of the bus cycle of the DMAC that currently has an acknowledged request, even if the transfer end conditions have not been satisfied. When the transfer request source is an on-chip peripheral module, however, cycle-steal mode is always used. Figure 11.11 shows an example of DMA transfer timing in burst mode. The transfer conditions for the example in the figure are as shown below. • Single address mode • DREQn level detection DREQn Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC CPU CPU CPU Figure 11.11 DMA Transfer Timing in Burst Mode (Single Address, DREQn Falling-Edge Detection) Refreshes cannot be performed during a burst transfer, so ensure that the number of transfers satisfies the refresh request period when a memory requiring refreshing is used. When the transfer request source is an external request (DREQn) in burst mode, set the DS bit of CHCR0 and CHCR1 to 1 (edge detection). If the DS bits of CHCR0 and CHCR1 are set to 0 (level detection), operation is not guaranteed. Rev. 2.00 Mar 09, 2006 page 492 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Relationship of Request Modes and Bus Modes by DMA Transfer Category: Table 11.8 shows the relationship between request modes, bus modes, etc., by DMA transfer category. Table 11.8 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Single Dual Transfer Range 3 Request Mode* Bus Transfer 7 Mode* Size (Byte) Between external memory and external device with DACK External B/C 1/2/4/16* Between external device with DACK, and memory mapped external device External B/C 1/2/4/16* Between external memories External B/C 1/2/4/16* Automatic B/C 1/2/4/16 Internal peripheral 1 module* C 1/2/4 External B/C 1/2/4/16* Automatic B/C 1/2/4/16 Internal peripheral 1 module* C 1/2/4 B/C 1/2/4/16* Automatic B/C 1/2/4/16 Internal peripheral 1 module* C 1/2/4 External B/C Automatic B/C 1/2/4* 4 1/2/4* Internal peripheral 2 module* C 1/2/4* External B/C Between external memory and memory mapped external device Between memory mapped external devices External Between external memory and internal peripheral module 8 8 8 8 8 4 4 Automatic B/C 1/2/4* 4 1/2/4* Internal peripheral 2 module* C 1/2/4* Between internal memories Automatic B/C 1/2/4/16 Between internal memory and memory 5 mapped external device* External B/C 1/2/4/16* Between memory mapped external device and internal peripheral module 4 4 8 Automatic B/C 1/2/4/16 Internal peripheral 1 module* C 1/2/4 Rev. 2.00 Mar 09, 2006 page 493 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Address Mode Dual Transfer Range 3 Request Mode* Bus Transfer 7 Mode* Size (Byte) Between internal memory and internal peripheral module Automatic B/C Internal peripheral 2 module* C 1/2/4* 4 1/2/4* Between internal memory and external 6 memory* External B/C 1/2/4/16* Automatic B/C 1/2/4/16 Internal peripheral 1 module* C 1/2/4 Automatic B/C Internal peripheral 2 module* C 1/2/4* 4 1/2/4* Between internal peripheral modules 4 8 4 Notes: B: Burst mode C: Cycle steal mode 1. For on-chip peripheral module requests, do not specify SCIF, SIOF and SIO as a transfer request source. 2. When the transfer request source is SCIF, SIOF or SIO, the transfer source or transfer destination must be SCIF, SIOF and SIO, respectively. 3. When the request mode is set to internal peripheral module request, set the DS bit and the DL bit of CHCR0 and CHCR1 to 1 and 0, respectively (detection at the falling edge of DREQn). In addition, the bus mode can only be set to cycle-steal mode. 4. Specify the access size that is allowed by the internal peripheral-module registers, which are a transfer source or a transfer destination. 5. When transferring data from internal memory to a memory mapped external device, set DACKn to write-time output. When transferring from a memory mapped external device to internal memory, set DACKn to read-time output. 6. When transferring data from internal memory to external memory, set DACKn to writetime output. When transferring from external memory to internal memory, set DACKn to read-time output. 7. When B (burst mode) is set in the external request mode, set the DS bits of CHCR0 and CHCR1 to 1 (edge detection). If they are set to 0 (level detection), operation cannot be guaranteed. 8. Transfer in units of 16 bytes is enabled only when edge detection has been specified. If transfer is attempted in units of 16 bytes when level detection has been specified, operation cannot be guaranteed. Rev. 2.00 Mar 09, 2006 page 494 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Table 11.9 shows the combinations of request mode, bus mode, and address mode that can be specified in the external request mode. Table 11.9 Combinations of Request Mode, Bus Mode, and Address Mode Specifiable in the External Request Mode Dual Address Mode Cycle-Steal Mode Burst Mode Cycle-Steal Mode Byte — O — O Word — O — O Longword — O — O 16-byte unit — — — — Byte O O O O Word O O O O Longword O O O O 16-byte unit O O O O Request Mode External request Level 1 detection* Edge 2 detection* Single Address Mode Burst Mode Notes: O: Can be set —: Cannot be set 1. The same for high-level and low-level detection. 2. The same for rising-edge detection and falling-edge detection. Bus Mode and Channel Priority: When a given channel (1) is transferring in burst mode and there is a transfer request to a channel (0) with a higher priority, the transfer of the channel with higher priority (0) will begin immediately. When channel 0 is also operating in the burst mode, the channel 1 transfer will continue as soon as the channel 0 transfer has completely finished. When channel 0 is in cycle-steal mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, but the bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the CPU. This example is illustrated in Figure 11.12. Bus state CPU DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1 ch0 CPU DMAC ch1 Burst mode ch1 ch1 ch0 DMAC ch1/ch0 bus right transfers CPU ch0 DMAC ch1 Burst mode CPU Figure 11.12 Bus Status when Multiple Channels are Operating (when priority order is ch0 > ch1, ch1 is set to burst mode, and ch0 to cycle-steal mode) Rev. 2.00 Mar 09, 2006 page 495 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 11.3.5 Number of Bus Cycles The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. For details, see section 7, Bus State Controller (BSC). 11.3.6 DMA Transfer Request Acknowledge Signal Output Timing DMA transfer request acknowledge signal DACKn is output synchronous to the DMA address output specified by the channel control register AM bit of the address bus. Normally, the acknowledge signal becomes valid when DMA address output begins, and becomes invalid 0.5 cycles before the address output ends. (See figure 11.13.) The output timing of the acknowledge signal varies with the settings of the connected memory space. The output timing of acknowledge signals in the memory spaces is shown in figure 11.13. Clock DACKn (Active high) Address bus 0.5 cycles CPU DMAC Figure 11.13 Example of DACKn Output Timing Acknowledge Signal Output when External Memory Is Set as Ordinary Memory Space: The timing at which the acknowledge signal is output is the same in the DMA read and write cycles specified by the AM bit (figures 11.14 and 11.15). When DMA address output begins, the acknowledge signal becomes valid; 0.5 cycles before address output ends, it becomes invalid. If a wait is inserted in this period and address output is extended, the acknowledge signal is also extended. Rev. 2.00 Mar 09, 2006 page 496 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) T1 TW T2 Clock DACKn (Active high) Address bus 0.5 cycles DMAC read Invalid write DMAC write CPU CPU DMAC read 1 wait inserted Basic timing Figure 11.14 DACKn Output in Ordinary Space Accesses (AM = 0) Clock DACKn (Active high) Address bus DMAC read Invalid DMAC write write Invalid write CPU Basic timing DMAC read DMAC write 1 wait inserted Figure 11.15 DACKn Output in Ordinary Space Accesses (AM = 1) In a longword access of a 16-bit external device (figure 11.16) or an 8-bit external device (figure 11.17), or a word access of an 8-bit external device (figure 11.18), the lower and upper addresses are output 2 and 4 times in each DMAC access in order to align the data. For all of these addresses, the acknowledge signal becomes valid simultaneous with the start of output and the signal becomes invalid 0.5 cycles before the address output ends. When multiple addresses are output in a single access to align data for synchronous DRAM, DRAM, or burst ROM, an acknowledge signal is output to those addresses as well. Rev. 2.00 Mar 09, 2006 page 497 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) Address bus CPU H *1 DMAC read H *2 DMAC read L Invalid write DMAC write Basic timing Notes: 1. H: MSB side 2. L: LSB side Figure 11.16 DACKn Output in Ordinary Space Accesses (AM = 0, Longword Access to 16-Bit External Device) Clock DACKn (Active high) Address bus DMAC read HH DMAC read HL DMAC read LH DMAC read LL CPU Basic timing Figure 11.17 DACKn Output in Ordinary Space Accesses (AM = 0, Longword Access to 8-Bit External Device) Clock DACKn (Active high) Address bus Invalid write CPU DMAC read H DMAC read L DMAC write Basic timing Figure 11.18 DACKn Output in Ordinary Space Accesses (AM = 0, Word Access to 8-Bit External Device) Rev. 2.00 Mar 09, 2006 page 498 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Acknowledge Signal Output when External Memory Is Set as Synchronous DRAM: When external memory is set as synchronous DRAM, DACKn output becomes valid simultaneously with the start of the DMA address, and becomes invalid when the address output ends. When external memory is set as synchronous DRAM auto-precharge and AM = 0, the acknowledge signal is output across the row address, read command, wait and read address of the DMAC read (figure 11.19). Since the synchronous DRAM read has only burst mode, during a single read an invalid address is output; the acknowledge signal, however, is output on the same timing (figure 11.20). At this time, the acknowledge signal is extended until the write address is output after the invalid read. A synchronous DRAM burst read is performed in the case of 16-byte transfer. As 16-byte transfer is enabled only in auto-request mode and in external request mode with edge detection, when using on-chip peripheral module requests or external request mode with level detection, byte, word, or longword should be set as the transfer unit. Operation is not guaranteed if a 16-byte unit is set when using on-chip peripheral module requests or external request mode with level detection. When AM = 1, the acknowledge signal is output across the row address and column address of the DMAC write (figure 11.21). Clock DACKn (Active high) Read command Row address Address bus CPU Read 1 Read 2 Read 3 Read 4 DMAC read (basic timing) Figure 11.19 DACKn Output in Synchronous DRAM Burst Read (Auto-Precharge, AM = 0) Rev. 2.00 Mar 09, 2006 page 499 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) Address bus Read command Row address Row Column address address Read CPU Invalid read DMAC read (basic timing) DMAC write (basic timing) Figure 11.20 DACKn Output in Synchronous DRAM Single Read (Auto-Precharge, AM = 0) Clock DACKn (Active high) Row Column address address Address bus DMAC write (basic timing) Figure 11.21 DACKn Output in Synchronous DRAM Write (Auto-Precharge, AM = 1) Rev. 2.00 Mar 09, 2006 page 500 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a burst read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.22). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.23). Clock DACKn (Active high) Read command Address bus CPU Read 1 Read 2 Read 3 Read 4 DMAC read (basic timing) Figure 11.22 DACKn Output in Synchronous DRAM Burst Read (Bank Active, Same Row Address, AM = 0) Clock DACKn (Active high) Address bus PreRead Row charge address command CPU Read 1 Read 2 Read 3 Read 4 DMAC read (basic timing) Figure 11.23 DACKn Output in Synchronous DRAM Burst Read (Bank Active, Different Row Address, AM = 0) Rev. 2.00 Mar 09, 2006 page 501 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a single read the acknowledge signal is output across the read command, wait and read address when the row address is the same as the previous address output (figure 11.24). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, read command, wait and read address (figure 11.25). Since the synchronous DRAM read has only burst mode, during a single read an invalid address is output; the acknowledge signal is output on the same timing. At this time, the acknowledge signal is extended until the write address is output after the invalid read. Clock DACKn (Active high) Address bus Read command CPU Read Row Column address address Invalid read DMAC read (basic timing) DMAC write (basic timing) Figure 11.24 DACKn Output in Synchronous DRAM Single Read (Bank Active, Same Row Address, AM = 0) Clock DACKn (Active high) Address bus Row address PreRead charge command Read CPU Row Column address address Invalid read DMAC read (basic timing) DMAC write (basic timing) Figure 11.25 DACKn Output in Synchronous DRAM Single Read (Bank Active, Different Row Address, AM = 0) Rev. 2.00 Mar 09, 2006 page 502 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) When external memory is set as bank active synchronous DRAM, during a write the acknowledge signal is output across the wait and column address when the row address is the same as the previous address output (figure 11.26). When the row address is different from the previous address, the acknowledge signal is output across the precharge, row address, wait and column address (figure 11.27). Clock DACKn (Active high) Address bus Column address DMAC write (basic timing) Figure 11.26 DACKn Output in Synchronous DRAM Write (Bank Active, Same Row Address, AM = 1) Clock DACKn (Active high) Row Column Precharge address address Address bus DMAC write (basic timing) Figure 11.27 DACKn Output in Synchronous DRAM Write (Bank Active, Different Row Address, AM = 1) Rev. 2.00 Mar 09, 2006 page 503 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) • Synchronous DRAM one-cycle write When a one-cycle write is performed to synchronous DRAM, the DACKn signal is synchronized with the rising edge of the clock. A request by the request signal is accepted while the clock is high during DACKn output. Transfer Width Byte/Word/Longword 1 Transfer* DREQn Detection Method Level Detection Transfer bus mode 2 Cycle-steal mode* DACKn output timing Write DACK Transfer address mode Single mode Bus cycle Basic bus cycle Notes: 1. Do not set a 16-byte unit; operation is not guaranteed if this setting is made. 2. Cycle-steal mode must be set when DREQ is level-detected. Clock Bus cycle CPU DREQn (Active high) CPU DMAC1 CPU DMAC2 CPU DMAC3 CPU Blind zone 1st acceptance DACKn (Active high) 2nd acceptance 3rd acceptance DACK1 DACK2 4th acceptance .... DACK3 RAS CAS RD/WR WEn/DQMxx Figure 11.28 (a) Synchronous DRAM One-Cycle Write Timing Transfer Width Byte/Word/Longword Transfer DREQn Detection Method Edge Detection* Transfer bus mode Burst mode DACKn output timing Write DACK Transfer address mode Single mode Bus cycle Basic bus cycle Note: * Edge detection must be set when burst mode is selected as the transfer bus mode. Rev. 2.00 Mar 09, 2006 page 504 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock Bus cycle CPU DREQn (Active high) CPU DMAC1 DMAC2 DMAC3 DMAC4 CPU CPU Blind zone .... Acceptance DACKn (Active high) DACK1 DACK2 DACK3 DACK4 RAS CAS RD/WR WEn/DQMxx Figure 11.28 (b) Synchronous DRAM One-Cycle Write Timing Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory is set as DRAM and a row address is output during a read or write, the acknowledge signal is output across the row address and column address (figures 11.29–11.31). Clock DACKn (Active high) Address bus Row Precharge address Column address DMAC read or write (basic timing) Figure 11.29 DACKn Output in Normal DRAM Accesses (AM = 0 or 1) Rev. 2.00 Mar 09, 2006 page 505 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock DACKn (Active high) Address bus Column address DMAC read or write (basic timing) Figure 11.30 DACKn Output in DRAM Burst Accesses (Same Row Address, AM = 0 or 1) Clock DACKn (Active high) PreRow charge address Address bus Column address DMAC read or write (basic timing) Figure 11.31 DACKn Output in DRAM Burst Accesses (Different Row Address, AM = 0 or 1) Rev. 2.00 Mar 09, 2006 page 506 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Acknowledge Signal Output When External Memory Is Set as Burst ROM: When external memory is set as burst ROM, the acknowledge signal is output synchronous to the DMA address (no dual writes allowed) (figure 11.32). Clock DACKn (Active high) Address bus DMAC cycle DMAC cycle DMAC (1 wait state) Figure 11.32 DACKn Output in Nibble Accesses of Burst ROM 11.3.7 DREQn Pin Input Detection Timing In external request mode, DREQn pin signals are usually detected at the falling edge of the clock pulse (CKIO). When a request is detected, a DMAC bus cycle is produced four cycles later at the earliest and a DMA transfer performed. After the request is detected, the timing of the next input detection varies with the bus mode, address mode, DREQn input detection, and the memory connected. DREQn Pin Input Detection Timing in Cycle-Steal Mode: In cycle-steal mode, once a request is detected from the DREQn pin, the request signal is not detected until DACKn signal output in the next external bus cycle. In cycle-steal mode, request detection is performed from DACKn signal output until a request is detected. Once a request has been accepted, it cannot be canceled midway. The timing from the detection of a request until the next time requests are detectable is shown below. • Cycle-Steal Mode Edge Detection When transfer control is performed using edge detection, perform DREQn/DACKn handshaking as shown in figure 11.33, and perform DREQn input control so that there is a one-to-one relationship between DREQn and DACKn. Operation is not guaranteed if DREQn is input before the corresponding DACKn is output. Rev. 2.00 Mar 09, 2006 page 507 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) If the DACKn signal is output a number of times, the first DACKn signal for the input DREQn signal indicates the request acceptance start timing, and subsequently each clock edge is sampled. Clock Bus cycle DREQn (Rising-edge detection) CPU CPU DMAC DMAC CPU CPU 2nd acceptance 1st acceptance DMAC DMAC 3rd acceptance DACKn (Active high) Figure 11.33 DREQn/DACKn Handshaking Transfer Width Byte/Word/Longword DREQn Detection Method Transfer bus mode Cycle-steal mode DACKn output timing Read DACK/write DACK Transfer address mode Dual/single mode Bus cycle Basic bus cycle Edge Detection Clock Bus cycle DREQn (Active high) CPU CPU DMAC CPU Blind zone 1st acceptance 2nd acceptance DACKn (Active high) Requests acceptable Figure 11.34 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection Rev. 2.00 Mar 09, 2006 page 508 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock Bus cycle DREQn (Active high) CPU DMAC H CPU DMAC L Blind zone 1st 2nd acceptance acceptance DACKn (Active high) DACK H DACK L Figure 11.35 When a16-Bit External Device is Connected (Edge Detection) Clock Bus cycle DREQn (Active high) DACKn (Active high) CPU CPU DMAC HH DMAC HL DMAC LH DMAC LL Blind zone 1st 2nd acceptance acceptance DACK HH Blind zone DACK HL DACK LH DACK LL Figure 11.36 When an 8-Bit External Device is Connected (Edge Detection) Rev. 2.00 Mar 09, 2006 page 509 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) • Cycle-Steal Mode Edge Detection—16-Bit Transfer With 16-byte transfer, the first request signal is the first transfer request, and the second transfer request is accepted when the next request signal is accepted. The third and fourth requests are accepted in the same way. Transfer Width 16-Byte Transfer DREQn Detection Method Transfer bus mode Cycle-steal mode DACKn output timing Read DACK/write DACK Transfer address mode Dual/single mode Bus cycle Basic bus cycle Edge Detection Clock Bus cycle DREQn (Active high) CPU CPU DMAC*1 DMAC*2 DMAC*3 DMAC*4 DMA Blind zone 2nd 1st acceptance acceptance DACKn (Active high) DACK*1 DACK*2 DACK*3 DACK*4 Note: * n is the nth 16-byte transfer. Figure 11.37 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Edge Detection (16-Byte Transfer Setting) • Cycle-Steal Mode Level Detection In level detection mode, too, a request cannot be canceled once accepted. Transfer Width Byte/Word/Longword* DREQn Detection Method Transfer bus mode Cycle-steal mode DACKn output timing Read DACK/write DACK Transfer address mode Dual/single mode Bus cycle Basic bus cycle Level Detection Note: * Do not set a 16-byte unit; operation is not guaranteed if this setting is made. Rev. 2.00 Mar 09, 2006 page 510 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock Bus cycle CPU DREQn (Active high) CPU DMAC Blind zone 1st acceptance CPU Blind zone 2nd acceptance DACKn (Active high) Requests acceptable Figure 11.38 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Level Detection (Byte/Word/Longword Setting) Clock Bus cycle DREQn (Active high) DACKn (Active high) CPU CPU DMAC H Blind zone 1st acceptance DMAC L Blind zone 2nd acceptance DACK H DACK L Figure 11.39 When a 16-Bit External Device is Connected (Level Detection) Rev. 2.00 Mar 09, 2006 page 511 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Clock Bus cycle DREQn (Active high) CPU CPU DMAC HH DMAC HL DMAC LH DMAC LL Blind zone Blind zone 1st acceptance DACKn (Active high) 2nd acceptance DACK HH DACK HL DACK LH DACK LL Figure 11.40 When an 8-Bit External Device is Connected (Level Detection) DREQn Pin Input Detection Timing in Burst Mode: In burst mode, only edge detection is valid for DREQn input. Operation is not guaranteed if level detection is set. With edge detection of DREQn input, once a request is detected, DMA transfer continues until the transfer end condition is satisfied, regardless of the state of the DREQn pin. Request detection is not performed during this time. When the transfer start conditions are fulfilled after the end of transfer, request detection is performed again every cycle. Clock Bus cycle Bus DREQn (Active high) CPU CPU DMAC1 DMAC2 DMAC3 DMAC4 CPU Blind zone Acceptance DACKn (Active high) Figure 11.41 DREQn Pin Input Detection Timing in Burst Mode with Edge Detection Rev. 2.00 Mar 09, 2006 page 512 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 11.3.8 DMA Transfer End The DMA transfer ending conditions vary when channels end individually and when both channels end together. Conditions for Channels Ending Individually: When either of the following conditions is met, the transfer will end in the relevant channel only: The DMA transfer count register (TCR) value becomes 0. The DMA enable bit (DE) of the DMA channel control register (CHCR) is cleared to 0. • Transfer end when TCR = 0 When the TCR value becomes 0, the DMA transfer for that channel ends and the transfer-end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has already been set, a DMAC interrupt (DEI) request is sent to the CPU. For 16-byte transfer, set the number of transfers × 4. Operation is not guaranteed if an incorrect value is set. A 16-byte transfer is valid only in auto-request mode or in external request mode with edge detection. When using an external request with level detection or on-chip peripheral module request, do not specify a 16-byte transfer. • Transfer end when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfers in the affected channel are halted. The TE bit is not set when this happens. Conditions for Both Channels Ending Simultaneously: Transfers on both channels end when either of the following conditions is met: The NMIF (NMI flag) bit or AE (address error flag) bit in DMAOR is set to 1. The DMA master enable (DME) bit is cleared to 0 in DMAOR. • Transfer end when NMIF = 1 or AE = 1 in DMAOR When an NMI interrupt or DMAC address error occurs and the NMIF or AE bit is set to 1 in DMAOR, all channels stop their transfers. The DMA source address register (SAR), destination address register (DAR), and transfer count register (TCR) are all updated by the transfer immediately preceding the halt. When this transfer is the final transfer, TE = 1 and the transfer ends. To resume transfer after NMI interrupt exception handling or address error exception handling, clear the appropriate flag bit. When the DE bit is then set to 1, the transfer on that channel will restart. To avoid this, keep its DE bit at 0. In dual address mode, DMA transfer will be halted after the completion of the following write cycle even when the address error occurs in the initial read cycle. SAR, DAR and TCR are updated by the final transfer. Rev. 2.00 Mar 09, 2006 page 513 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) • Transfer end when DME = 0 in DMAOR Clearing the DME bit in DMAOR forcibly aborts the transfers on both channels at the end of the current bus cycle. When the transfer is the final transfer, TE = 1 and the transfer ends. 11.3.9 BH Pin Output Timing Purpose of New Specifications for BH: BH When the SH7616 is connected to the PCI bus as an external bus, Grew logic must be used externally because the SH7616 is not equipped with a PCI bus interface. The PCI bus uses burst transfer principally, and performance is poor if data is transferred in small increments. Due to these properties of the PCI bus, it is necessary to use Grew logic externally to compare the present address and the next address and determine whether burst transfer is possible. However, the size of the external Grew logic increases if address comparisons are required, and there is also the possibility that delays may interfere with timing requirements. The specifications for BH have therefore been updated in order to solve these problems. Now if burst transfer is possible using the present address this information is passed to the external Grew logic. This provides enhanced support for PCI bus connections. Register Settings When Using BH Pin: BH is output from only when the 16-byte transfer mode is selected using the DMAC built into the SH7616. However, it is not output when SDRAM or DRAM are accessed. When using the 16-byte transfer mode, specify auto-request mode or the external request mode with edge detection. If external request mode with level detection or onchip module request mode is specified, operation is not guaranteed. To use BH, the settings for the CHCR0 register or CHCR1 register in the on-chip DMAC of the SH7616 must be as shown in figure 11.43. BH is not output unless the settings for the CHCR0 register or CHCR1 register are as indicated in figure 11.42. Rev. 2.00 Mar 09, 2006 page 514 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) Bit 31 Bit name — Setting 0 Bit 15 Bit name DM1 Setting 0 30 — 0 14 DM0 1 29 28 27 26 25 — — — — — 0 0 0 0 0 13 12 11 10 9 SM1 SM0 TS1 TS0 AR 0 1 1 1 * 24 — 0 8 AM 23 — 0 7 AL 22 — 0 6 DS 21 — 0 5 DL 20 — 0 4 TB 19 — 0 3 TA 18 — 0 2 IE 17 — 0 1 TE * * * * * * * * 16-byte unit (four long words transferred) Source address is incremented Destination address is incremented 16 — 0 0 DE 1 DMA transfer allowed * Don't care Figure 11.42 Register Settings When Using BH Summary of BH Timing: Figure 11.43 is a summary of the BH output timing. External bus cycle CPU DMAC read 0 DMAC read 1 DMAC read 2 DMAC read 3 DMAC write 0 DMAC write 1 DMAC write 2 DMAC write 3 CPU BH Figure 11.43 Summary of BH Output Timing Rev. 2.00 Mar 09, 2006 page 515 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 11.4 Usage Examples 11.4.1 Example of DMA Data Transfer Between SCIF and External Memory In this example data received by the serial communication interface with FIFO (SCIF) is sent to external memory using DMAC channel 1. Table 11.10 lists the transfer conditions and register setting values. Table 11.10 Transfer Conditions and Register Setting Values for Data Transfer Between On-chip SCIF and External Memory Transfer Condition Register Setting Value Transfer source: SCFRDR1 in SCIF SAR1 H'FFFFFCCC Transfer destination: External memory (word space) DAR1 Transfer destination address Number of transfers: 64 TCR1 H'0040 Transfer destination address: Increment CHCR1 H'4045 DMAOR H'0001 Transfer source address: Fixed Bus mode: Cycle-steal Transfer unit: Byte DEI interrupt request at end of transfer DE = 1 Channel priority: Fixed (0 > 1) DME = 1 Transfer request source (transfer request signal): SCIF DRCR1 (RXI) H'05 Note: Make sure the SCIF settings have interrupts enabled and the appropriate CPU interrupt level. 11.5 Usage Notes 1. DMA request/response selection control registers 0 and 1 (DRCR0 and DRCR1) should be accessed in bytes. All other registers should be accessed in longword units. 2. Before rewriting the registers in the DMAC (CHCR0, CHCR1, DRCR0, DRCR1), first clear the DE bit to 0 in the CHCR register for the specified channel, or clear the DME bit in DMAOR to 0. 3. When the DMAC is not operating, the NMIF bit in DMAOR is set even when an NMI interrupt is input. 4. The DMAC cannot access the cache memory. Rev. 2.00 Mar 09, 2006 page 516 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 5. Before changing the frequency or changing to standby mode, set the DME bit of DMAOR to 0 and stop operation of the DMAC. 6. Do not use the DMAC, BSC, UBC, E-DMAC, and EtherC for on-chip peripheral module transfers. 7. Do not access the cache (address array, data array, associative purge area). 8. Note that when level detection of the request signal is used in single address mode, the request signal may be detected before DACKn is output. 9. When Eφ exceeds 31.25 MHz, do not use transfer involving DACKn output on ordinary space for word or longword access with an 8-bit bus width, or longword access with a 16-bit bus width. 10. When DMA transfer is performed in response to a DMA transfer request signal from a peripheral module, if clearing of the DMA transfer request signal from the peripheral module by the DMA transfer is not completed before the next transfer request signal from that module, subsequent DMA transfers may not be possible. 11. The following restrictions apply when using dual address mode for 16-byte transfer in cyclesteal mode: a. When external request and level detection are set, do not input DREQn during cycles in which DACKn is not active after the start of DMA transfer. b. When external request DREQ edge detection is set, if DREQn is input continuously the DMAC continues to operate without insertion of a CPU cycle. (However, a CPU cycle will begin if there is no request from DREQn.) Bus cycle CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU (R) (R) (R) (R) (W) (W) (W) (W) (R) (R) (R) (R) (W) (W) (W) (W) DACKn (active high) DREQn (active high) * DACK output in read cycle Bus cycle CPU CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU DMA DMA DMA DMA DMA DMA DMA DMA CPU (R) (R) (R) (R) (W) (W) (W) (W) (R) (R) (R) (R) (W) (W) (W) (W) DACKn (active high) * DREQn (active high) DACK output in write cycle Note: * In addition to CPU cycles, E-DMAC cycles may be inserted in some cases. Rev. 2.00 Mar 09, 2006 page 517 of 906 REJ09B0292-0200 Section 11 Direct Memory Access Controller (DMAC) 12. When setting DMAC channel 0 to cycle-steal mode, and channel 1 to cycle-steel mode, dual address mode or built-in peripheral module request, set the priority mode to priority order fixed mode. 13. When SDRAM is connected, set the upper limit of external bus frequency in DMA single address mode transfers to 31.25 MHz. 14. In the dual address mode, bits TS1 and TS0 (transfer size) in CHCR0 and CHCR1 should be cleared to 00 (byte unit setting) if a destination address as been set in internal memory. Rev. 2.00 Mar 09, 2006 page 518 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Section 12 16-Bit Free-Running Timer (FRT) 12.1 Overview A single-channel, 16-bit free-running timer (FRT) is included on-chip. The FRT is based on a 16-bit free-running counter (FRC) and can output two types of independent waveforms. The FRT can also measure the width of input pulses and the cycle of external clocks. 12.1.1 Features The FRT has the following features: • Choice of four counter input clocks The counter input clock can be selected from three internal clocks (Pφ/8, Pφ/32, Pφ/128) and an external clock (enabling external event counting). • Two independent comparators Two waveform outputs can be generated. • Input capture Choice of rising edge or falling edge • Counter clear specification The counter value can be cleared by compare match A. • Four interrupt sources Two compare match sources, one input capture source, and one overflow source can issue requests independently. Rev. 2.00 Mar 09, 2006 page 519 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the FRT. Internal clock φ/8 φ/32 φ/128 FTCI Clock select Clock OCRA (H/L) Compare match A Comparator A Overflow FTOB FRC (H/L) Clear FTI Control logic Compare match B Comparator B OCRB (H/L) Capture FICR (H/L) FTCSR TIER TCR TOCR ICI OCIA OCIB OVI OCRA,B: FRC: FICR: FTCSR: TIER: TCR: TOCR: Bus interface FTOA Interrupt signals Output compare registers A,B (16 bits) Free-running counter (16 bits) Input capture register (16 bits) Free-running timer control/status register (8 bits) Timer interrupt enable register (8 bits) Timer control register (8 bits) Timer output compare control register (8 bits) Figure 12.1 FRT Block Diagram Rev. 2.00 Mar 09, 2006 page 520 of 906 REJ09B0292-0200 Module data bus Internal data bus Section 12 16-Bit Free-Running Timer (FRT) 12.1.3 Pin Configuration Table 12.1 lists FRT I/O pins and their functions. Table 12.1 Pin Configuration Channel Pin I/O Function Counter clock input pin FTCI I FRC counter clock input pin Output compare A output pin FTOA O Output pin for output compare A Output compare B output pin FTOB O Output pin for output compare B Input capture input pin FTI I Input pin for input capture 12.1.4 Register Configuration Table 12.2 shows the FRT register configuration. Table 12.2 Register Configuration Register Abbreviation R/W Initial Value Address Timer interrupt enable register TIER R/W H'01 HFFFFFE10 Free-running timer control/status register FTCSR 1 R/(W)* H'00 HFFFFFE11 Free-running counter H FRC H R/W H'00 HFFFFFE12 Free-running counter L FRC L R/W H'00 HFFFFFE13 Output compare register A H OCRA H R/W H'FF Output compare register A L OCRA L R/W H'FF HFFFFFE14* 2 HFFFFFE15* Output compare register B H OCRB H R/W H'FF Output compare register B L OCRB L R/W H'FF HFFFFFE14* 2 HFFFFFE15* Timer control register TCR R/W H'00 HFFFFFE16 Timer output compare control register TOCR R/W H'E0 HFFFFFE17 Input capture register H FICR H R H'00 HFFFFFE18 Input capture register L FICR L R H'00 HFFFFFE19 2 2 Notes: Use byte-size access for all registers. 1. Bits 7 to 1 are read-only. The only value that can be written is a 0, which is used to clear flags. Bit 0 can be read or written. 2. OCRA and OCRB have the same address. The OCRS bit in TOCR is used to switch between them. Rev. 2.00 Mar 09, 2006 page 521 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.2 Register Descriptions 12.2.1 Free-Running Counter (FRC) Bit: 15 14 13 … 3 2 1 0 … Initial value: R/W: 0 0 0 … 0 0 0 0 R/W R/W R/W … R/W R/W R/W R/W FRC is a 16-bit read/write register. It increments upon input of a clock. The input clock can be selected using clock select bits 1 and 0 (CKS1, CKS0) in TCR. FRC can be cleared upon compare match A. When FRC overflows (H'FFFF → H'0000), the overflow flag (OVF) in FTCSR is set to 1. FRC can be read or written to by the CPU, but because it is 16 bits long, data transfers involving the CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more detailed information. FRC is initialized to H'0000 by a reset, in standby mode, and when the module standby function is used. 12.2.2 Output Compare Registers A and B (OCRA and OCRB) Bit: 15 14 13 … 3 2 1 0 … Initial value: R/W: 1 1 1 … 1 1 1 1 R/W R/W R/W … R/W R/W R/W R/W OCR is composed of two 16-bit read/write registers (OCRA and OCRB). The contents of OCR are always compared to the FRC value. When the two values are the same, the output compare flags in FTCSR (OCFA and OCFB) are set to 1. When the OCR and FRC values are the same (compare match), the output level values set in the output level bits (OLVLA and OLVLB) are output to the output compare pins (FTOA and FTOB). After a reset, FTOA and FTOB output 0 until the first compare match occurs. Because OCR is a 16-bit register, data transfers involving the CPU are performed via a temporary register (TEMP). See section 12.3, CPU Interface, for more detailed information. Rev. 2.00 Mar 09, 2006 page 522 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) OCR is initialized to H'FFFF by a reset, in standby mode, and when the module standby function is used. 12.2.3 Input Capture Register (FICR) Bit: 15 14 13 … 3 2 1 0 Initial value: 0 0 0 … 0 0 0 0 R/W: R R R … R R R R … FICR is a 16-bit read-only register. When a rising edge or falling edge of the input capture signal (FTI pin) is detected, the current FRC value is transferred to FICR. At the same time, the input capture flag (ICF) in FTCSR is set to 1. The edge of the input signal can be selected using the input edge select bit (IEDG) in TCR. Because FICR is a 16-bit register, data transfers involving the CPU are performed via a temporary register (TEMP). See Section 12.3, CPU Interface, for more detailed information. To ensure that the input capture operation is reliably performed, set the pulse width of the input capture input signal to six system clocks (φ) or more. FICR is initialized to H'0000 by a reset, in standby mode, and when the module standby function is used. 12.2.4 Timer Interrupt Enable Register (TIER) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ICIE — — — OCIAE OCIBE OVIE — 0 0 0 0 0 0 0 1 R/W R R R R/W R/W R/W R TIER is an 8-bit read/write register that controls enabling of all interrupt requests. TIER is initialized to H'01 by a reset, in standby mode, and when the module standby function is used. Bit 7—Input Capture Interrupt Enable (ICIE): Selects enabling/disabling of the ICI interrupt request when the input capture flag (ICF) in FTCSR is set to 1. Bit 7: ICIE Description 0 Interrupt request (ICI) caused by ICF disabled 1 Interrupt request (ICI) caused by ICF enabled (Initial value) Rev. 2.00 Mar 09, 2006 page 523 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects enabling/disabling of the OCIA interrupt request when the output compare flag A (OCFA) in FTCSR is set to 1. Bit 3: OCIAE Description 0 Interrupt request (OCIA) caused by OCFA disabled 1 Interrupt request (OCIA) caused by OCFA enabled (Initial value) Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects enabling/disabling of the OCIB interrupt request when the output compare flag B (OCFB) in FTCSR is set to 1. Bit 2: OCIBE Description 0 Interrupt request (OCIB) caused by OCFB disabled 1 Interrupt request (OCIB) caused by OCFB enabled (Initial value) Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects enabling/disabling of the OVI interrupt request when the overflow flag (OVF) in FTCSR is set to 1. Bit 1: OVIE Description 0 Interrupt request (OVI) caused by OVF disabled 1 Interrupt request (OVI) caused by OVF enabled (initial value) Bit 0—Reserved: This bit is always read as 1. The write value should always be 1. 12.2.5 Free-Running Timer Control/Status Register (FTCSR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ICF — — — OCFA OCFB OVF CCLRA 0 0 0 0 0 0 0 0 R R/(W)* R/(W)* R/(W)* R/W R/(W)* R R Note: * For bits 7, and 3 to 1, the only value that can be written is 0 (to clear the flags). FTCSR is an 8-bit register that selects counter clearing and controls interrupt request signals. FTCSR is initialized to H'00 by a reset, in standby mode, and when the module standby function is used. See section 12.4, Operation, for the timing. Rev. 2.00 Mar 09, 2006 page 524 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Bit 7—Input Capture Flag (ICF): Status flag that indicates that the FRC value has been sent to FICR by the input capture signal. This flag is cleared by software and set by hardware. It cannot be set by software. Bit 7: ICF Description 0 [Clearing condition] When ICF is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value is sent to FICR by the input capture signal Bits 6 to 4—Reserved: These bits always read 0. The write value should always be 0. Bit 3—Output Compare Flag A (OCFA): Status flag that indicates when the values of the FRC and OCRA match. This flag is cleared by software and set by hardware. It cannot be set by software. Bit 3: OCFA Description 0 [Clearing condition] When OCFA is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value becomes equal to OCRA Bit 2—Output Compare Flag B (OCFB): Status flag that indicates when the values of FRC and OCRB match. This flag is cleared by software and set by hardware. It cannot be set by software. Bit 2: OCFB Description 0 [Clearing condition] When OCFB is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value becomes equal to OCRB Rev. 2.00 Mar 09, 2006 page 525 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Bit 1—Timer Overflow Flag (OVF): Status flag that indicates when FRC overflows (from H'FFFF to H'0000). This flag is cleared by software and set by hardware. It cannot be set by software. Bit 1: OVF Description 0 [Clearing condition] When OVF is read while set to 1, and then 0 is written to it (Initial value) 1 [Setting condition] When the FRC value changes from H'FFFF to H'0000 Bit 0—Counter Clear A (CCLRA): Selects whether or not to clear FRC on compare match A (signal indicating match of FRC and OCRA). Bit 0: CCLRA Description 0 FRC clear disabled 1 FRC cleared on compare match A 12.2.6 (Initial value) Timer Control Register (TCR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IEDG — — — — — CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W TCR is an 8-bit read/write register that selects the input edge for input capture and selects the input clock for FRC. TCR is initialized to H'00 by a reset, in standby mode, and when the module standby function is used. Bit 7—Input Edge Select (IEDG): Selects whether to capture the input capture input (FTI) on the falling edge or rising edge. Bit 7: IEDG Description 0 Input captured on falling edge 1 Input captured on rising edge (Initial value) Bits 6 to 2—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 526 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Bits 1 and 0—Clock Select (CKS1, CKS0): These bits select whether to use an external clock or one of three internal clocks for input to FRC. The external clock is counted at the rising edge. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Internal clock: count at φ/8 1 Internal clock: count at φ/32 0 Internal clock: count at φ/128 1 External clock: count at rising edge 1 12.2.7 (Initial value) Timer Output Compare Control Register (TOCR) Bit: 7 6 5 4 3 2 1 0 — — — OCRS — — OLVLA OLVLB Initial value: 1 1 1 0 0 0 0 0 R/W: R R R R/W R R R/W R/W TOCR is an 8-bit read/write register that selects the output level for output compare and controls switching between access of output compare registers A and B. TOCR is initialized to H'E0 by a reset, in standby mode, and when the module standby function is used. Bits 7 to 5—Reserved: These bits are always read as 1. The write value should always be 1. Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address. The OCRS bit controls which register is selected when reading/writing to this address. It does not affect the operation of OCRA and OCRB. Bit 4: OCRS Description 0 OCRA register selected 1 OCRB register selected (Initial value) Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0. Bit 1—Output Level A (OLVLA): Selects the level output to the output compare A output pin upon compare match A (signal indicating match of FRC and OCRA). Bit 1: OLVLA Description 0 0 output on compare match A 1 1 output on compare match A (Initial value) Rev. 2.00 Mar 09, 2006 page 527 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Bit 0—Output Level B (OLVLB): Selects the level output to the output compare B output pin upon compare match B (signal indicating match of FRC and OCRB). Bit 0: OLVLB Description 0 0 output on compare match B 1 1 output on compare match B 12.3 (Initial value) CPU Interface FRC, OCRA, OCRB, and FICR are 16-bit registers. The data bus width between the CPU and FRT, however, is only 8 bits. Access of these three types of registers from the CPU therefore needs to be performed via an 8-bit temporary register called TEMP. The following describes how these registers are read from and written to: • Writing to 16-bit Registers The upper byte is written, which results in the upper byte of data being stored in TEMP. The lower byte is then written, which results in 16 bits of data being written to the register when combined with the upper byte value in TEMP. • Reading from 16-bit Registers The upper byte of data is read, which results in the upper byte value being transferred to the CPU. The lower byte value is transferred to TEMP. The lower byte is then read, which results in the lower byte value in TEMP being sent to the CPU. When registers of these three types are accessed, two byte accesses should always be performed, first to the upper byte, then the lower byte. If only the upper byte or lower byte is accessed, the data will not be transferred properly. Figure 12.2 and 12.3 show the flow of data when FRC is accessed. Other registers function in the same way. When reading OCRA and OCRB, however, both upper and lower-byte data is transferred directly to the CPU without passing through TEMP. Rev. 2.00 Mar 09, 2006 page 528 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) (Write to upper byte) CPU (H'AA) upper byte Data bus within module Bus interface TEMP (H'AA) FRC H ( ) FRC L ( ) (Write to lower byte) CPU (H'55) lower byte Data bus within module Bus interface TEMP (H'AA) FRC H (H'AA) FRC L (H'55) Figure 12.2 FRC Access Operation (CPU Writes H'AA55 to FRC) Rev. 2.00 Mar 09, 2006 page 529 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) (Read from upper byte) CPU (H'AA) upper byte Data bus within module Bus interface TEMP (H'55) FRC H (H'AA) FRC L (H'55) (Read from lower byte) CPU (H'55) lower byte Data bus within module Bus interface TEMP (H'AA) FRC H ( ) FRC L ( ) Figure 12.3 FRC Access Operation (CPU Reads H'AA55 from FRC) Rev. 2.00 Mar 09, 2006 page 530 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.4 Operation 12.4.1 FRC Count Timing The FRC increments on clock input (internal or external). Internal Clock Operation: Set the CKS1 and CKS0 bits in TCR to select which of the three internal clocks created by dividing system clock φ (φ/8, φ/32, φ/128) is used. Figure 12.4 shows the timing. Pφ Internal clock FRC input clock FRC N–1 N N+1 Figure 12.4 Count Timing (Internal Clock Operation) External Clock Operation: Set the CKS1 and CKS0 bits in TCR to select the external clock. External clock pulses are counted on the rising edge. The pulse width of the external clock must be at least 6 system clocks (φ). A smaller pulse width will result in inaccurate operation. Figures 12.5 shows the timing. Pφ External clock input pin FRC input clock FRC N+1 N Figure 12.5 Count Timing (External Clock Operation) Rev. 2.00 Mar 09, 2006 page 531 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.4.2 Output Timing for Output Compare When a compare match occurs, the output level set in the OLVL bit in TOCR is output from the output compare output pins (FTOA, FTOB). Figure 12.6 shows the timing for output of output compare A. Pφ FRC N N+1 OCRA N N Compare match A signal N Clear* OLVLA Output compare A output pin FTOA Note: * ↓ Indicates instruction execution by software Figure 12.6 Output Timing for Output Compare A 12.4.3 FRC Clear Timing FRC can be cleared on compare match A. Figure 12.7 shows the timing. Pφ Compare match A signal FRC N H'0000 Figure 12.7 Compare Match A Clear Timing Rev. 2.00 Mar 09, 2006 page 532 of 906 REJ09B0292-0200 N+1 Section 12 16-Bit Free-Running Timer (FRT) 12.4.4 Input Capture Input Timing Either the rising edge or falling edge can be selected for input capture input using the IEDG bit in TCR. Figure 12.8 shows the timing when the rising edge is selected (IEDG = 1). Pφ Input capture input pin Input capture signal Figure 12.8 Input Capture Signal Timing (Normal) When the input capture signal is input when FICR is read (upper-byte read), the input capture signal is delayed by one cycle of Pφ. Figure 12.9 shows the timing. FICR upper-byte read cycle Pφ Input capture input pin Input capture signal Figure 12.9 Input Capture Signal Timing (Input Capture Input when FICR is Read) Rev. 2.00 Mar 09, 2006 page 533 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.4.5 Input Capture Flag (ICF) Setting Timing Input capture input sets the input capture flag (ICF) to 1 and simultaneously transfers the FRC value to FICR. Figure 12.10 shows the timing. Pφ Input capture signal ICF FRC N FICR N Figure 12.10 ICF Setting Timing 12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing The compare match signal output (when OCRA or OCRB matches the FRC value) sets output compare flag OCFA or OCFB to 1. The compare match signal is generated in the last state in which the values matched (at the timing for updating the count value that matched the FRC). After OCRA or OCRB matches the FRC, no compare match is generated until the next increment occurs. Figure 12.11 shows the timing for setting OCFA and OCFB. Rev. 2.00 Mar 09, 2006 page 534 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Pφ FRC N OCRA, OCRB N N+1 Compare match signal OCFA, OCFB Figure 12.11 OCF Setting Timing 12.4.7 Timer Overflow Flag (OVF) Setting Timing FRC overflow (from H'FFFF to H'0000) sets the timer overflow flag (OVF) to 1. Figure 12.12 shows the timing. Pφ FRC H'FFFF H'0000 Overflow signal OVF Figure 12.12 OVF Setting Timing Rev. 2.00 Mar 09, 2006 page 535 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.5 Interrupt Sources There are four FRT interrupt sources of three types (ICI, OCIA/OCIB, and OVI). Table 12.3 lists the interrupt sources and their priorities after a reset is cleared. The interrupt enable bits in TIER are used to enable or disable the interrupt bits. Each interrupt request is sent to the interrupt controller independently. See section 5, Interrupt Controller (INTC), for more information about priorities and the relationship to interrupts other than those of the FRT. Table 12.3 FRT Interrupt Sources and Priorities Interrupt Source Description Priority ICI Interrupt by ICF High OCIA, OCIB Interrupt by OCFA or OCFB OVI Interrupt by OVF ↑ ↓ Low 12.6 Example of FRT Use Figure 12.13 shows an example in which pulses with a 50% duty factor and arbitrary phase relationship are output. The procedure is as follows: 1. Set the CCLRA bit in FTCSR to 1. 2. The OLVLA and OLVLB bits are inverted by software whenever a compare match occurs. FRC Counter clear H'FFFF OCRA OCRB H'0000 FTOA FTOB Figure 12.13 Example of Pulse Output Rev. 2.00 Mar 09, 2006 page 536 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.7 Usage Notes Note that the following contention and operations occur when the FRT is operating: 12.7.1 Contention between FRC Write and Clear When a counter clear signal is generated with the timing shown in figure 12.14 during the write cycle for the lower byte of FRC, writing does not occur to the FRC, and the FRC clear takes priority. FRC lower-byte write cycle Pφ Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 12.14 Contention between FRC Write and Clear Rev. 2.00 Mar 09, 2006 page 537 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.7.2 Contention between FRC Write and Increment When an increment occurs with the timing shown in figure 12.15 during the write cycle for the lower byte of FRC, no increment is performed and the counter write takes priority. FRC lower-byte write cycle Pφ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 12.15 Contention between FRC Write and Increment Rev. 2.00 Mar 09, 2006 page 538 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.7.3 Contention between OCR Write and Compare Match When a compare match occurs with the timing shown in figure 12.16, during the write cycle for the lower byte of OCRA or OCRB, the OCR write takes priority and the compare match signal is disabled. FRC lower-byte write cycle Pφ Address OCR address Internal write signal FRC N N+1 OCR N M Write data Compare match signal Disabled Figure 12.16 Contention between OCR and Compare Match Rev. 2.00 Mar 09, 2006 page 539 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) 12.7.4 Internal Clock Switching and Counter Operation FRC will sometimes begin incrementing because of the timing of switching between internal clocks. Table 12.4 shows the relationship between internal clock switching timing (CKS1 and CKS0 bit rewrites) and FRC operation. When an internal clock is used, the FRC clock is generated when the falling edge of an internal clock (created by dividing the system clock (φ)) is detected. When a clock is switched to high before the switching and to low after switching, as shown in case 3 in table 12.4, the switchover is considered a falling edge and an FRC clock pulse is generated, causing FRC to increment. FRC may also increment when switching between an internal clock and an external clock. Table 12.4 Internal Clock Switching and FRC Operation No. Timing of Rewrite of CKS1 and CKS0 Bits 1 Low-to-low switch FRC Operation Clock before switching Clock after switching FRC clock FRC N N+1 Rewrite of CKS bit 2 Low-to-high switch Clock before switching Clock after switching FRC clock FRC N N+1 N+2 Rewrite of CKS bit Rev. 2.00 Mar 09, 2006 page 540 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) No. Timing of Rewrite of CKS1 and CKS0 Bits 3 High-to-low switch FRC Operation Clock before switching Clock after switching FRC clock FRC N N+1 N+2 Rewrite of CKS bit 4 High-to-high switch Clock before switching Clock after switching FRC clock FRC N N+1 N+2 Rewrite of CKS bit Note: Because the switchover is considered a falling edge, FRC starts counting up. 12.7.5 Timer Output (FTOA, FTOB) During a power-on reset, the timer outputs (FTOA, FTOB) will be unreliable until the oscillation stabilizes. The initial value is output after the oscillation settling time has elapsed. Rev. 2.00 Mar 09, 2006 page 541 of 906 REJ09B0292-0200 Section 12 16-Bit Free-Running Timer (FRT) Rev. 2.00 Mar 09, 2006 page 542 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) 13.1 Overview A single-channel watchdog timer (WDT) is provided on-chip for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used when recovering from standby mode, in modifying a clock frequency, and in clock pause mode. 13.1.1 Features The WDT includes the following features. • Can be switched between watchdog timer mode and interval timer mode. • WDTOVF output in watchdog timer mode The WDTOVF signal is output externally when the counter overflows, and a simultaneous internal reset of the chip can also be selected (either a power-on reset or manual reset can be specified). • Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. • Used when standby mode is cleared or the clock frequency is changed, and in clock pause mode. • Choice of eight counter input clocks Rev. 2.00 Mar 09, 2006 page 543 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the WDT. Overflow Interrupt control Clock WDTOVF Internal reset signal* Clock select Reset control φ/4 φ/128 φ/256 φ/512 φ/1024 φ/2048 φ/8192 φ/16384 Internal clock RSTCSR WTCNT WTCSR Bus interface Module bus Interna bus ITI (Interrupt request signal) WDT φ: See figure 3.1, Block Diagram of Clock Pulse Generator Circuit. WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by a register setting. The type of reset can be selected (power-on or manual reset). Figure 13.1 WDT Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in watchdog timer mode Rev. 2.00 Mar 09, 2006 page 544 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 Register Configuration Address Name Abbreviation R/W Initial Value Write* Read* 1 2 Watchdog timer WTCSR control/status register R/(W)* H'18 H'FFFFFE80 H'FFFFFE80 Watchdog timer counter WTCNT R/W H'00 H'FFFFFE80 H'FFFFFE81 Reset control/status register RSTCSR R/(W)* H'1D H'FFFFFE82 H'FFFFFE83 3 3 Notes: 1. Write by word access. It cannot be written by byte or longword access. 2. Read by byte access. The correct value cannot be read by word or longword access. 3. Only 0 can be written in bit 7 to clear the flag. 13.2 Register Descriptions 13.2.1 Watchdog Timer Counter (WTCNT) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: WTCNT is an 8-bit read/write register. The method of writing to WTCNT differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. When the timer enable bit (TME) in the watchdog timer control/status register (WTCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in WTCSR. When the value of WTCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit in WTCSR. WTCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized in standby mode, when the clock frequency is changed, or in clock pause mode. Rev. 2.00 Mar 09, 2006 page 545 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.2.2 Watchdog Timer Control/Status Register (WTCSR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W R R R/W R/W R/W Note: * Only 0 can be written in bit 7, to clear the flag. The watchdog timer control/status register (WTCSR) is an 8-bit read/write register. The method of writing to WTCSR differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. Its functions include selecting the timer mode and clock source. Bits 7 to 5 are initialized to 000 by a reset, in standby mode, when the clock frequency is changed, and in clock pause mode. Bits 2 to 0 are initialized to 000 by a reset, but are not initialized in standby mode, when the clock frequency is changed, or in clock pause mode. Bit 7—Overflow Flag (OVF): Indicates that WTCNT has overflowed from H'FF to H'00 in interval timer mode. It is not set in watchdog timer mode. Bit 7: OVF Description 0 No overflow of WTCNT in interval timer mode (Initial value) Cleared by reading OVF, then writing 0 in OVF 1 WTCNT overflow in interval timer mode Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When WTCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT IT Description 0 Interval timer mode: interval timer interrupt (ITI) request to the CPU when WTCNT overflows (Initial value) 1 Watchdog timer mode: WDTOVF signal output externally when WTCNT overflows. Section 13.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when WTCNT overflows in watchdog timer mode Rev. 2.00 Mar 09, 2006 page 546 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) Bit 5—Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description 0 Timer disabled: WTCNT is initialized to H'00 and count-up stops (Initial value) 1 Timer enabled: WTCNT starts counting. A WDTOVF signal or interrupt is generated when WTCNT overflows Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1. Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to WTCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). Description Overflow Interval* (φ φ = 60 MHz) Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source 0 0 φ/4 (Initial value) 17.0 µs 1 φ/128 544 µs 0 φ/256 1.1 ms 1 φ/512 2.2 ms 0 0 φ/1024 4.4 ms 1 φ/2048 8.7 ms 1 0 φ/8192 34.8 ms 1 φ/16384 69.6 ms 0 1 1 Note: * The overflow interval listed is the time from when the WTCNT begins counting at H'00 until an overflow occurs. 13.2.3 Reset Control/Status Register (RSTCSR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 WOVF RSTE RSTS — — — — — 0 0 0 1 1 1 0 1 R/(W)* R/W R/W R R R R R Note: * Only 0 can be written in bit 7, to clear the flag. RSTCSR is an 8-bit read/write register that controls output of the reset signal generated by watchdog timer counter (WTCNT) overflow and selects the internal reset signal type. The method Rev. 2.00 Mar 09, 2006 page 547 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1D by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1D in standby mode, when the clock frequency is changed, and in clock pause mode. Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed (from H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode. Bit 7: WOVF Description 0 No WTCNT overflow in watchdog timer mode (Initial value) Cleared by reading WOVF, then writing 0 in WOVF 1 Set by WTCNT overflow in watchdog timer mode Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if WTCNT overflows in watchdog timer mode. Bit 6: RSTE Description 0 Not reset when WTCNT overflows 1 Reset when WTCNT overflows (Initial value) LSI not reset internally, but WTCNT and WTCSR reset within WDT Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if WTCNT overflows in watchdog timer mode. Bit 5: RSTS Description 0 Power-on reset 1 Manual reset (Initial value) Bits 4 to 2, bit 0—Reserved: These bits are always read as 1. The write value should always be 1. Bit 1— Reserved: This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 548 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.2.4 Notes on Register Access The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that they are more difficult to write. The procedures for writing and reading these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by byte or longword transfer instructions. WTCNT and WTCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for WTCNT) or H'A5 (for WTCSR) (figure 13.2). This transfers the write data from the lower byte to WTCNT or WTCSR. Writing to WTCNT 15 Address: H'FFFFFE80 8 7 H'5A 0 Write data Writing to WTCSR 15 Address: H'FFFFFE80 8 7 H'A5 0 Write data Figure 13.2 Writing to WTCNT and WTCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFFE82. It cannot be written by byte or longword transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Rev. 2.00 Mar 09, 2006 page 549 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) Writing 0 to the WOVF bit 15 Address: H'FFFFFE82 8 7 H'A5 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'FFFFFE82 8 7 H'5A 0 Write data Figure 13.3 Writing to RSTCSR Reading from WTCNT, WTCSR, and RSTCSR: WTCNT, WTCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFFE80 for WTCSR, H'FFFFFE81 for WTCNT, and H'FFFFFE83 for RSTCSR. 13.3 Operation 13.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits in WTCSR to 1. Software must prevent WTCNT overflow by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. Thus, WTCNT will not overflow while the system is operating normally, but if WTCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output (figure 13.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 512 φ clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneously with the WDTOVF signal when WTCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit. The internal reset signal is output for 2048 φ clock cycles. If a reset due to the input signal from the RES pin and a reset due to WDT overflow occur simultaneously, the RES reset takes priority and the WOVF bit in RSTCSR is cleared to 0. Rev. 2.00 Mar 09, 2006 page 550 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) WTCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in WTCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 in WTCNT WDTOVF and internal reset generated WDTOVF signal 512 φ clocks Internal reset signal* 2048 φ clocks WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal is generated only when the RSTE bit is set to 1. Figure 13.4 Operation in Watchdog Timer Mode Rev. 2.00 Mar 09, 2006 page 551 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in WTCSR. An interval timer interrupt (ITI) is generated each time the watchdog timer counter (WTCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5). WTCNT value H'FF Overflow Overflow Overflow Overflow ITI ITI ITI ITI H'00 Time WT/IT = 0 TME = 1 ITI: Interval timer interrupt request generation Figure 13.5 Operation in Interval Timer Mode 13.3.3 Operation when Standby Mode is Cleared The watchdog timer has a special function to clear standby mode with an NMI interrupt. When using standby mode, set the WDT as described below. Transition to Standby Mode: The TME bit in WTCSR must be cleared to 0 to stop the watchdog timer counter before it enters standby mode. The chip cannot enter standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in WTCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 22, Electrical Characteristics, for the oscillation settling time. Recovery from Standby Mode: When an NMI request signal is received in standby mode the clock oscillator starts running and the watchdog timer starts counting at the rate selected by bits CKS2 to CKS0 before standby mode was entered. When WTCNT overflows (changes from H'FF to H'00) the system clock (φ) is presumed to be stable and usable; clock signals are supplied to the entire chip and standby mode ends. For details on standby mode, see section 21, Power Down Modes. Rev. 2.00 Mar 09, 2006 page 552 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.3.4 Timing of Overflow Flag (OVF) Setting In interval timer mode, when WTCNT overflows, the OVF flag in WTCSR is set to 1 and an interval timer interrupt (ITI) is requested (figure 13.6). WTCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of OVF Setting 13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting When WTCNT overflows the WOVF flag in RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be generated for the entire chip (figure 13.7). WTCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 13.7 Timing of WOVF Setting Rev. 2.00 Mar 09, 2006 page 553 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.4 Usage Notes 13.4.1 Contention between WTCNT Write and Increment If a count-up pulse is generated at the timing shown in figure 13.8 during a watchdog timer counter (WTCNT) write cycle, the write takes priority and the timer counter is not incremented (figure 13.8). Address WTCNT address Internal write signal WTCNT input clock WTCNT N M Counter write data Figure 13.8 Contention between WTCNT Write and Increment 13.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode The WDT may not operate correctly if it is switched between watchdog timer mode and interval timer mode while it is running. To ensure correct operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between watchdog timer mode and interval timer mode. Rev. 2.00 Mar 09, 2006 page 554 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) 13.4.4 System Reset with WDTOVF If a WDTOVF signal is input to the RES pin, the device cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. Chip Reset input Reset signal to entire system RES WDTOVF Figure 13.9 Example of Circuit for System Reset with WDTOVF Signal 13.4.5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not reset internally when a WTCNT overflow occurs, but WTCNT and WTCSR in the WDT will reset. When using sleep mode, do not use internal reset. Instead, use the RES pin for resetting. (See section13.4.4, System Reset with WDTOVF.) Internal reset can be used only when sleep mode is not used. Rev. 2.00 Mar 09, 2006 page 555 of 906 REJ09B0292-0200 Section 13 Watchdog Timer (WDT) Rev. 2.00 Mar 09, 2006 page 556 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Section 14 Serial Communication Interface with FIFO (SCIF) 14.1 Overview The SH7616 is equipped with a two-channel serial communication interface with built-in FIFO buffers (SCIF: SCI with FIFO). The SCIF can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). An on-chip Infrared Data Association (IrDA) interface based on the IrDA 1.0 system is also provided, enabling infrared communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 14.1.1 Features The SCIF has the following features: • Choice of synchronous or asynchronous serial communication mode  Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data communication formats. • Data length: 7 or 8 • Stop bit length: 1 or 2 bits • Parity: Even/odd/none • Multiprocessor bit: 1 or 0 • Receive error detection: Parity, overrun, and framing errors • Automatic break detection Rev. 2.00 Mar 09, 2006 page 557 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF)  Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data communication format. • Data length: 8 bits • Receive error detection: Overrun errors • IrDA 1.0 compliance • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. In addition, the transmitter and receiver both have a 16-stage FIFO buffer structure, enabling continuous serial data transmission and reception. (However, IrDA communication is carried out in half-duplex mode.) • Built-in baud rate generator allows a choice of bit rates. • Choice of transmit/receive clock source: internal clock from baud rate generator or external clock from SCK pin • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. The transmit-FIFO-data-empty and receive-FIFO-data-full interrupts can activate the on-chip DMAC to execute data transfer. • When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. • Choice of LSB-first or MSB-first mode • In asynchronous mode, operation can be selected on a base clock of 4, 8, or 16 times the bit rate. • Built-in modem control functions (RTS and CTS) Rev. 2.00 Mar 09, 2006 page 558 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.1.2 Block Diagrams Bus interface A block diagram of the SCIF is shown in figure 14.1, and a diagram of the IrDA block in figure 14.2. Module data bus SCFRDR (16-stage) RxD SCRSR SCFTDR (16-stage) SCFDR Internal data bus SCBRR SCFCR Pφ SC1SSR SC2SSR SCSCR SCTSR Baud rate generator SCSMR SCFER SCIMR Transmission/ reception control TxD Parity generation Pφ/4 Pφ/16 Pφ/64 Clock Parity check External clock SCK BRI TxI RxI ERI SCIF Legend SCRSR: SCFRDR: SCTSR: SCFTDR: SCSMR: SCSCR: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SC1SSR: SC2SSR: SCBRR: SCFCR: SCFDR: SCFER: SCIMR: IrDA/SCI switchover (to IrDA block) Serial status 1 register Serial status 2 register Bit rate register FIFO control register FIFO data count register FIFO error register IrDA mode register Figure 14.1 Block Diagram of SCIF Rev. 2.00 Mar 09, 2006 page 559 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Clock input SCK TxD TxD Modulation unit Transmit clock SCIF RxD Demodulation unit RxD IrDA IrDA/SCIF switchover Figure 14.2 Diagram of IrDA Block 14.1.3 Pin Configuration The SCIF has the serial pins shown in table 14.1. Table 14.1 SCIF Pins Channel Name Abbreviation I/O Function 1 Serial clock pin SCK1 Input/ output Clock input/output Receive data pin RxD1 Input Receive data input Transmit data pin TxD1 Output Transmit data output Transmit request pin RTS Output Transmit request 2 Transmit enable pin CTS Input Transmit enable Serial clock pin SCK2 Input/ output Clock input/output Receive data pin RxD2 Input Receive data input Transmit data pin TxD2 Output Transmit data output Rev. 2.00 Mar 09, 2006 page 560 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.1.4 Register Configuration The SCIF has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode/synchronous mode and the IrDA communication mode, the data format and the bit rate, and to perform transmitter/receiver control. Table 14.2 SCIF Registers Channel Name Abbreviation R/W Initial Value Address 1 Serial mode register SCSMR1 R/W H'00 H'FFFFFCC0 8 Bit rate register SCBRR1 R/W H'FF H'FFFFFCC2 8 Serial control register SCSCR1 R/W H'00 H'FFFFFCC4 8 Transmit FIFO data register SCFTDR1 W Serial status 1 register SC1SSR1 Serial status 2 register SC2SSR1 — * R/(W) H'0060 R/(W)* H'20 Receive FIFO data register SCFRDR1 R Undefined H'FFFFFCCC 8 FIFO control register SCFCR1 R/W H'00 H'FFFFFCCE 8 FIFO data count register SCFDR1 R H'0000 H'FFFFFCD0 16 FIFO error register SCFER1 R H'0000 H'FFFFFCD2 16 2 Access Size H'FFFFFCC6 8 H'FFFFFCC8 16 H'FFFFFCCA 8 IrDA mode register SCIFMR1 R/W H'00 H'FFFFFCD4 8 Serial mode register SCSMR2 R/W H'00 H'FFFFFCE0 8 Bit rate register SCBRR2 R/W H'FF H'FFFFFCE2 8 Serial control register SCSCR2 R/W H'00 H'FFFFFCE4 8 Transmit FIFO data register SCFTDR2 W Serial status 1 register SC1SSR2 Serial status 2 register SC2SSR2 — * R/(W) H'0060 R/(W)* H'20 Receive FIFO data register SCFRDR2 R Undefined H'FFFFFCEC 8 FIFO control register SCFCR2 R/W H'00 H'FFFFFCEE 8 FIFO data count register SCFDR2 R H'0000 H'FFFFFCF0 16 FIFO error register SCFER2 R H'0000 H'FFFFFCF2 16 IrDA mode register SCIMR2 R/W H'00 H'FFFFFCF4 8 H'FFFFFCE6 8 H'FFFFFCE8 16 H'FFFFFCEA 8 Note: * Only 0 can be written, to clear flags. Use byte access on registers with an access size of 8, and word access on registers with an access size of 16. Rev. 2.00 Mar 09, 2006 page 561 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2 Register Descriptions With the exception of the IrDA mode register (SCIMR) and bits 6 to 3 (ICK3 to ICK0) of the serial mode register (SCSMR), IrDA communication mode settings are the same as for asynchronous mode. 14.2.1 Receive Shift Register (SCRSR) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — The receive shift register (SCRSR) is the register used to receive serial data. The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the LSB (bit 0) or MSB (bit 7), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO data register (SCFRDR) automatically. SCRSR cannot be read or written to directly. 14.2.2 Receive FIFO Data Register (SCFRDR) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R The receive FIFO data register (SCFRDR) is a 16-stage FIFO register (8 bits per stage) that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO data register is full (16 data bytes). SCFRDR is a read-only register, and cannot be written to. If a read is performed when there is no receive data in the receive FIFO data register, an undefined value will be returned. When the receive FIFO data register is full of receive data, subsequent serial data is lost. Rev. 2.00 Mar 09, 2006 page 562 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.3 Transmit Shift Register (SCTSR) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — The transmit shift register (SCTSR) is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the TxD pin starting with the LSB (bit 0) or MSB (bit 7). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be read or written to directly. 14.2.4 Transmit FIFO Data Register (SCFTDR) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W The transmit FIFO data register (SCFTDR) is a 16-stage FIFO register (8 bits per stage) that stores data for serial transmission. When the SCIF detects that SCTSR is empty, it transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. Serial transmission is performed continuously until there is no transmit data left in SCFTDR. SCFTDR is a write-only register, and cannot be read. The next data cannot be written when SCFTDR is filled with 16 bytes of transmit data. Data written in this case is ignored. Rev. 2.00 Mar 09, 2006 page 563 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.5 Serial Mode Register (SCSMR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/A CHR/ ICK3 PE/ ICK2 O/E/ ICK1 STOP/ ICK0 MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The serial mode register (SCSMR) is an 8-bit register used to set the SCIF’s serial communication format and select the baud rate generator clock source. In IrDA communication mode, it is used to select the output pulse width. SCSMR can be read or written to by the CPU at all times. SCSMR is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bit 7—Communication Mode (C/A): Selects asynchronous mode or synchronous mode as the SCIF operating mode. In IrDA communication mode, this bit must be cleared to 0. Bit 7: C/A A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) Bit 6—Character Length (CHR)/IrDA Clock Select 3 (ICK3): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR Description 0 8-bit data 1 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register (SCFTDR) is not transmitted. In IrDA communication mode, bit 6 is the IrDA clock select 3 (ICK3) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Rev. 2.00 Mar 09, 2006 page 564 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 5—Parity Enable (PE)/IrDA Clock Select 2 (ICK2): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit addition and checking disabled Parity bit addition and checking enabled* 1 (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. In IrDA communication mode, bit 5 is the IrDA clock select 2 (ICK2) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Bit 4—Parity Mode (O/E)/IrDA Clock Select 1 (ICK1): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/E E Description 0 Even parity* 2 Odd parity* 1 1 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. In IrDA communication mode, bit 4 is the IrDA clock select 1 (ICK1) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Rev. 2.00 Mar 09, 2006 page 565 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Stop Bit Length (STOP)/IrDA Clock Select 0 (ICK0): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP Description 0 1 stop bit* 2 2 stop bits* 1 1 (Initial value) Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. In IrDA communication mode, bit 3 is the IrDA clock select 0 (ICK0) bit, enabling appropriate clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6, Operation in IrDA Mode, for details. Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode and IrDA mode. For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the builtin baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64, according to the setting of bits CKS1 and CKS0. Rev. 2.00 Mar 09, 2006 page 566 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) For the relationship between the clock source, the bit rate register setting, and the baud rate, see section 14.2.9, Bit Rate Register (SCBRR). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Pφ clock 1 Pφ/4 clock 1 0 Pφ/16 clock 1 Pφ/64 clock (Initial value) Note: Pφ = peripheral clock 14.2.6 Serial Control Register (SCSCR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE — CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R/W The serial control register (SCSCR) performs enabling or disabling of SCIF transmit/receive operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the transmit/receive clock source. SCSCR can be read or written to by the CPU at all times. SCSCR is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when, after serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR falls to or below the transmit trigger set number, and the TDFE flag is set to 1 in the serial status 1 register (SC1SSR). Bit 7: TIE Description 0 Transmit-FIFO-data-empty interrupt (TXI) request disabled* 1 Transmit-FIFO-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. When transmit data is written to SCFTDR using the on-chip DMAC, the TDFE flag is cleared automatically. Rev. 2.00 Mar 09, 2006 page 567 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-FIFO-data-full interrupt (RXI) request and receive-error interrupt (ERI) request when, after serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), the number of data bytes in SCFRDR reaches or exceeds the receive trigger set number, and the RDF flag is set to 1 in SC1SSR. Bit 6: RIE Description 0 Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) 1 Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: * RXI, ERI, and BRI interrupt requests can be cleared by reading 1 from the RDF or DR flag, the FER, PER, ORER, or ER flag, or the BRK flag, then clearing the flag to 0, or by clearing the RIE bit to 0. With the RDF flag, read receive data from SCFRDR until the number of receive data bytes is less than the receive trigger set number, then read 1 from the RDF flag and clear it to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE Description 0 Transmission disabled* 2 Transmission enabled* 1 1 (Initial value) Notes: 1. The TDRE flag in SC1SSR is fixed at 1. 2. Serial transmission is started when transmit data is written to SCFTDR in this state. Serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description 0 Reception disabled* 2 Reception enabled* 1 1 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDF, DR, FER, PER, ORER, ER, and BRK flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR settings must be made to decide the reception format before setting the RE bit to 1. Rev. 2.00 Mar 09, 2006 page 568 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1. The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0. Bit 3: MPIE Description 0 Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] • When the MPIE bit is cleared to 0 • 1 When data with MPB = 1 is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDF and FER in SC1SSR and ORER in SC2SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * Receive data transfer from SCRSR to SCFRDR, receive error detection, and setting of the RDF and FER in SC1SSR and ORER flags in SC2SSR, is not performed. When receive data with MPB = 1 is received, the MPB flag in SC2SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI (when the RIE bit in SCSCR is set to 1) and FER and ORER flag setting is enabled. Bit 2—Reserved: This bit is always read as 0. The write value should always be 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCIF clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The function of the SCK pin should be selected with the pin function controller (PFC). The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCIF’s operating mode with SCSMR. For details of clock source selection, see table 14.9 in section 14.3, Operation. Rev. 2.00 Mar 09, 2006 page 569 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as input pin (input 1 signal ignored)* Synchronous mode Internal clock/SCK pin functions as serial clock 1 output* Asynchronous mode Internal clock/SCK pin functions as clock output* Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock input* Synchronous mode External clock/SCK pin functions as serial clock input 1 *4 1 Notes: 1. 2. 3. 4. 14.2.7 2 3 Initial value Outputs a clock with a frequency of 16/8/4 times the bit rate. Inputs a clock with a frequency of 16/8/4 times the bit rate. Don’t care Serial Status 1 Register (SC1SSR) Bit: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR Initial value: R/W: 0 1 1 0 0 0 0 0 R/(W)* R R/(W)* R/(W)* R R R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. The serial status 1 register (SC1SSR) is a 16-bit register in which the lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SC1SSR can be read or written to at all times. However, 1 cannot be written to the ER, TDFE, BRK, RDF, and DR status flags. Also note that in order to clear these flags to 0, they must first be read as 1. The TEND, FER, and PER flags are read-only and cannot be modified. Rev. 2.00 Mar 09, 2006 page 570 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) SC1SSR is initialized to H'0084 by a reset, by the module standby function, and in standby mode. Bits 15 to 12—Parity Error Count 3 to 0 (PER3 to PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data in the receive FIFO data register. These bits are cleared by reading all the receive data in the receive FIFO data register, or by setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty state. Bits 11 to 8—Framing Error Count 3 to 0 (FER3 to FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data in the receive FIFO data register. These bits are cleared by reading all the receive data in the receive FIFO data register, or by setting the RFRST bit to 1 in SCFCR and resetting the receive FIFO data register to the empty state. Bit 7—Receive Error (ER) Bit 7: ER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When 0 is written to ER after reading ER = 1 A framing error, parity error, or overrun error occurred during reception [Setting conditions] • When the SCIF checks whether the stop bit at the end of the receive data is 2 1 when reception ends, and the stop bit is 0* • When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in the serial mode register (SCSMR) • When the next serial receive operation is completed while there are 16 receive data bytes in SCFRDR Notes: 1. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a framing error or parity error occurs, the receive data is still transferred to SCFRDR, and reception is then halted or continued according to the setting of the EI bit. When an overrun error occurs, the receive data is not transferred to SCFRDR and reception cannot be continued. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev. 2.00 Mar 09, 2006 page 571 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description 0 Transmission is in progress [Clearing condition] When data is written to SCFTDR while TE = 1 1 Transmission has been ended (Initial value) [Setting conditions] • In a reset or in standby mode • When the TE bit in SCSCR is 0 • When there is no transmit data in SCFTDR on transmission of the last bit of a 1-byte serial transmit character Bit 5—Transmit Data FIFO Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR), and transmit data can be written to SCFTDR. Bit 5: TDFE Description 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] 1 • When transmit data exceeding the transmit trigger set number is written to SCFTDR, and 0 is written to TDFE after reading TDFE = 1 • When transmit data exceeding the transmit trigger set number is written to SCFTDR by the on-chip DMAC The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number (Initial value) [Setting conditions] • In a reset or in standby mode • When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* Note: * As SCFTDR is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 0 is {16 – (transmit trigger set number)}. Data written in excess of this will be ignored. The number of data bytes in SCFTDR is indicated by the upper 8 bits of SCFDR. Rev. 2.00 Mar 09, 2006 page 572 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK Description 0 A break signal has not been received (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When 0 is written to BRK after reading BRK = 1 A break signal has been received [Setting condition] When data with a framing error is received, and a framing error also occurs in the next receive data (all space “0”) Note: When a break is detected, transfer to SCFRDR of the receive data (H'00) following detection is halted. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed. Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR). Bit 3: FER Description 0 There is no framing error in the receive data read from SCFRDR (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When there is no framing error in SCFRDR read data There is a framing error in the receive data read from SCFRDR [Setting condition] When there is a framing error in SCFRDR read data Bit 2—Parity Error (PER): In asynchronous mode, indicates a parity error in the data read from the receive FIFO data register (SCFRDR). Bit 2: PER Description 0 There is no parity error in the receive data read from SCFRDR (Initial value) [Clearing conditions] • In a reset or in standby mode • When there is no parity error in SCFRDR read data 1 There is a parity error in the receive data read from SCFRDR [Setting condition] When there is a parity error in SCFRDR read data Rev. 2.00 Mar 09, 2006 page 573 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). Bit 1: RDF Description 0 The number of receive data bytes in SCFRDR is less than the receive trigger set number (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number, and 0 is written to RDF after reading RDF = 1 • When SCFRDR is read by the on-chip DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR contains at least the receive trigger set number of receive data bytes Note: SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR is indicated by the lower 8 bits of SCFDR. Rev. 2.00 Mar 09, 2006 page 574 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived for at least 16 etu after the stop bit of the last data received. Bit 0: DR Description 0 Reception is in progress or has ended normally and there is no receive data left in SCFRDR (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When 0 is written to DR after all the remaining receive data has been 1 read* No further receive data has arrived, and SCFRDR contains fewer than the receive trigger set number of data bytes [Setting condition] When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 16 etu after the stop bit 2 of the last data received* Notes: 1. All remaining receive data should be read before clearing the DR flag. 2. Equivalent to 1.6 frames when using an 8-bit, 1-stop-bit format. etu: Elementary time unit = sec/bit 14.2.8 Serial Status 2 Register (SC2SSR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TLM RLM N1 N0 MPB MPBT EI ORER 0 0 1 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/(W)* Note: * Only 0 can be written, to clear the flag. The serial status 2 register (SC2SSR) is an 8-bit register. SC2SSR can be read or written to at all times. However, 1 cannot be written to the ORER flag. Also note that in order to clear this flag to 0, they must first be read as 1. SC2SSR is initialized to H'20 by a reset, by the module standby function, and in standby mode. Rev. 2.00 Mar 09, 2006 page 575 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 7—Transmit LSB/MSB-First Select (TLM): Selects LSB-first or MSB-first mode in data transmission. Bit 7: TLM Description 0 LSB-first transmission 1 MSB-first transmission (Initial value) Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data reception. Bit 6: RLM Description 0 LSB-first reception 1 MSB-first reception (Initial value) Bits 5 and 4—Clock Bit Rate Ratio (N1, N0): These bits select the ratio of the base clock to the bit rate. Bit 5: N1 Bit 4: N0 Description 0 0 SCIF operates on base clock of 4 times the bit rate 1 SCIF operates on base clock of 8 times the bit rate 0 SCIF operates on base clock of 16 times the bit rate 1 Setting prohibited 1 (Initial value) Bit 3—Multiprocessor bit (MPB): When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. The MPB flag is read-only and cannot be modified. Bit 3: MPB Description 0 Data with a 0 multiprocessor bit has been received* (Initial value) 1 Data with a 1 multiprocessor bit has been received * Note: Retains its previous state when the RE bit is cleared to 0 while using a multiprocessor format. Bit 2—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. Rev. 2.00 Mar 09, 2006 page 576 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) The MPBT bit setting is invalid in synchronous mode and IrDA mode, when a multiprocessor format is not used, and when the operation is not transmission. Bit 2: MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted (Initial value) Bit 1—Receive Data Error Ignore Enable (EI): Selects whether or not the receive operation is to be continued when a framing error or parity error occurs in receive data (ER = 1). Bit 1: EI Description 0 Receive operation is halted when framing error or parity error occurs during reception (ER = 1) (Initial value) 1 Receive operation is continued when framing error or parity error occurs during reception (ER = 1) Note: When EI = 0, only the last data in SCFRDR is treated as data containing an error. When EI = 1, receive data is sent to SCFRDR even if it contains an error. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1 • In a reset or in standby mode • When 0 is written to ORER after reading ORER = 1 An overrun error occurred during reception* 2 [Setting condition] When the next serial receive operation is completed while there are 16 receive data bytes in SCFRDR Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Also, serial transmission cannot be continued in synchronous mode. Rev. 2.00 Mar 09, 2006 page 577 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.9 Bit Rate Register (SCBRR) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: The bit rate register (SCBRR) is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in the serial mode register (SCSMR). SCBRR can be read or written to by the CPU at all times. SCBRR is initialized to H'FF by a reset, by the module standby function, and in standby mode. The SCBRR setting is found from the following equations. Asynchronous mode: N= N= N= Pφ 64 × 22n–1 × B Pφ 32 × 22n–1 × B Pφ 16 × 22n–1 × B × 106 – 1 (When operating on a base clock of 16 times the bit rate) × 106 – 1 (When operating on a base clock of 8 times the bit rate) × 106 – 1 (When operating on a base clock of 4 times the bit rate) Synchronous mode: N= Where B: N: Pφ: n: Pφ 8 × 22n–1 × B × 106 – 1 Bit rate (bits/s) SCBRR setting for baud rate generator (0 ≤ N ≤ 255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0, 1, 2, or 3) (See the table below for the relation between n and the clock.) Rev. 2.00 Mar 09, 2006 page 578 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) SCSMR Settings n Clock CKS1 CKS0 0 Pφ 0 0 1 Pφ/4 2 Pφ/16 3 Pφ/64 1 1 0 1 The bit rate error in asynchronous mode is found from the following equations: Error (%) = Pφ × 106 (N + 1) × B × 64 × 22n–1 – 1 × 100 (When operating on a base clock of 16 times the bit rate) Error (%) = Pφ × 106 (N + 1) × B × 32 × 22n–1 – 1 × 100 (When operating on a base clock of 8 times the bit rate) Error (%) = Pφ × 106 (N + 1) × B × 16 × 22n–1 – 1 × 100 (When operating on a base clock of 4 times the bit rate) Table 14.3 shows sample SCBRR settings in asynchronous mode, and table 14.4 shows sample SCBRR settings in synchronous mode. In both tables, the values are for operation on a base clock of 16 times the bit rate. Rev. 2.00 Mar 09, 2006 page 579 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.3 Examples of Bit Rates and SCBRR Settings in Asynchronous Mode Pφ φ (MHz) 2 2.097152 2.4576 3 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 –18.62 0 1 –14.67 0 1 0.00 — — — Pφ φ (MHz) 3.6864 4 4.9152 5 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 Rev. 2.00 Mar 09, 2006 page 580 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Pφ φ (MHz) 6 6.144 7.37288 8 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99 Pφ φ (MHz) 9.8304 10 12 12.288 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00 Rev. 2.00 Mar 09, 2006 page 581 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Pφ φ (MHz) 14.7456 Bit Rate (Bits/s) n N Error (%) 16 n N 30 Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 132 0.13 150 2 191 0.00 2 207 0.16 3 97 –0.35 300 2 95 0.00 2 103 0.16 2 194 0.16 600 1 191 0.00 1 207 0.16 2 97 –0.35 1200 1 95 0.00 1 103 0.16 1 194 0.16 2400 0 191 0.00 0 207 0.16 1 97 –0.35 4800 0 95 0.00 0 103 0.16 0 194 0.16 9600 0 47 0.00 0 51 0.16 0 97 –0.35 19200 0 23 0.00 0 25 0.16 0 48 –0.35 31250 0 14 –1.70 0 15 0.00 0 29 0.00 38400 0 11 0.00 0 12 0.16 0 23 1.73 Rev. 2.00 Mar 09, 2006 page 582 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.4 Examples of Bit Rates and SCBRR Settings in Synchronous Mode Pφ φ (MHz) 4 8 16 32 Bit Rate (Bits/s) n N n N n N n N 110 — — — — — — — — 250 2 249 3 124 3 249 — — 500 2 124 2 249 3 124 3 249 1k 1 249 2 124 2 249 3 124 2.5 k 1 99 1 199 2 99 2 199 5k 0 199 1 99 1 199 2 99 10 k 0 99 0 199 1 99 1 199 25 k 0 39 0 79 0 159 1 79 50 k 0 19 0 39 0 79 0 159 100 k 0 9 0 19 0 39 0 79 250 k 0 3 0 7 0 15 0 31 500 k 0 1 0 3 0 7 0 15 1M 0 0* 0 1 0 3 0 7 0 0* 0 1 0 3 2M Note: As far as possible, the setting should be made so that the error is within 1%. Legend Blank: No setting is available. —: A setting is available but error occurs. * Continuous transmission/reception is not possible. Rev. 2.00 Mar 09, 2006 page 583 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.5 shows the maximum bit rate for various frequencies in asynchronous mode when using the baud rate generator. Tables 14.6 and 14.7 show the maximum bit rates when using external clock input. Table 14.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ φ (MHz) Maximum Bit Rate (Bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.66080 614400 0 0 20 625000 0 0 24 750000 0 0 24.57600 768000 0 0 28 896875 0 0 30 937500 0 0 Rev. 2.00 Mar 09, 2006 page 584 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 30 7.5000 468750 Table 14.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) Pφ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 30 5.0 5000000.0 Rev. 2.00 Mar 09, 2006 page 585 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.10 FIFO Control Register (SCFCR) Bit: Initial value: R/W: 7 RTRG1 0 R/W 6 RTRG0 0 R/W 5 TTRG1 0 R/W 4 TTRG0 0 R/W 3 MCE 0 R/W 2 TFRST 0 R/W 1 RFRST 0 R/W 0 LOOP 0 R/W The FIFO control register (SCFCR) performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can be read or written to at all times. SCFCR is initialized to H'00 by a reset, by the module standby function, and in standby mode. Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status 1 register (SC1SSR). The RDF flag is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 Bit 6: RTRG0 0 0 1 0 1 1 Receive Trigger Number 1* 4 8 14 Note: * Initial value Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status 1 register (SC1SSR). The TDFE flag is set when the number of transmit data bytes in the transmit FIFO data register (SCFTDR) is equal to or less than the trigger set number shown in the following table. Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number 0 8 (8)* 1 4 (12) 1 0 2 (14) 1 1 (15) Note: * Initial value. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set. 0 Rev. 2.00 Mar 09, 2006 page 586 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit 3—Modem Control Enable (MCE): Enables or disables the CTS and RTS modem control signals. Bit 3: MCE Description 0 Modem signals disabled* 1 Modem signals enabled (Initial value) Note: * CTS is fixed at active-0 regardless of the input value, and RTS output is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST Description 0 Reset operation disabled 1 Reset operation enabled (Initial value) Note: A reset operation is performed in the event of a reset, module standby, or in standby mode. Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST Description 0 Reset operation disabled 1 Reset operation enabled (Initial value) Note: A reset operation is performed in the event of a reset, module standby, or in standby mode. Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD) and receive input pin (RxD), enabling loopback testing. Bit 0: LOOP Description 0 Loopback test disabled 1 Loopback test enabled (Initial value) Rev. 2.00 Mar 09, 2006 page 587 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.11 FIFO Data Count Register (SCFDR) The FIFO data count register (SCFDR) is a 16-bit register that indicates the number of data bytes stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR). The upper 8 bits show the number of transmit data bytes in SCFTDR, and the lower 8 bits show the number of receive data bytes in SCFRDR. SCFDR can be read by the CPU at all times. SCFDR is initialized to H'00 by a reset, by the module standby function, and in standby mode. It is also initialized to H'00 by setting the TFRST and RFRST bits to 1 in SCFCR to reset SCFTDR and SCFRDR to the empty state. Upper 8 bits: 15 14 13 12 11 10 9 8 — — — T4 T3 T2 T1 T0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bits 15 to 13—Reserved: These bits are always read as 0. The write value should always be 0. Bits 12 to 8—Transmit FIFO Data Count 4 to 0 (T4 to T0): These bits show the number of untransmitted data bytes in SCFTDR. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR is full of transmit data. The value is cleared to H'00 by transmitting all the data, as well as by the above initialization conditions. Lower 8 bits: 7 6 5 4 3 2 1 0 — — — R4 R3 R2 R1 R0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bits 4 to 0—Receive FIFO Data Count 4 to 0 (R4 to R0): These bits show the number of receive data bytes in SCFRDR. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR is full of receive data. The value is cleared to H'00 by reading all the receive data from SCFRDR, as well as by the above initialization conditions. Rev. 2.00 Mar 09, 2006 page 588 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.2.12 FIFO Error Register (SCFER) The FIFO error register (SCFER) indicates the data location at which a parity error or framing error occurred in receive data stored in the receive FIFO data register (SCFRDR). SCFER can be read at all times. Upper 8 bits: 15 14 13 12 11 10 9 8 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Lower 8 bits: 7 6 5 4 3 2 1 0 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bits 15 to 0—Error Data Flags 15 to 0 (ED15 to ED0): These flags indicate the data location in the receive FIFO data register at which an error occurred. When data in the nth stage of the buffer contains an error, the nth bit is set to 1. Note that this register is not cleared by setting the RFRST bit to 1 in SCFCR. Bits 15 to 0: ED15 to ED0 Description 0 No parity or framing error in data in corresponding stage of register FIFO (Initial value) 1 Parity or framing error present in data in corresponding stage of register FIFO Note: A reset operation is performed in the event of a reset, when the module standby function is used, or in standby mode. These flags are also cleared by reading the data in which the parity error or framing error occurred from SCFRDR. 14.2.13 IrDA Mode Register (SCIMR) The IrDA mode register (SCIFMR) allows selection of the IrDA mode and the IrDA output pulse width, and inversion of the IrDA receive data polarity. SCIMR can be read and written to at all times. SCIMR is initialized to H'00 by a reset, by the module standby function, and inop standby mode. Rev. 2.00 Mar 09, 2006 page 589 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IRMOD PSEL RIVS — — — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R R Bit 7—IrDA Mode (IRMOD): Selects operation as an IrDA serial communication interface. Bit 7: IRMOD Description 0 Operation as SCIF is selected Operation as IrDA is selected* 1 (Initial value) Note: * When operation as an IrDA interface is selected, bit 7 (C/A) of the serial mode register (SCSMR) must be cleared to 0. Bit 6—Output Pulse Width Select (PSEL): Selects either 3/16 of the bit length set by bits ICK3 to ICK0 in the serial mode register (SCSMR), or 3/16 of the bit length corresponding to the selected baud rate, as the IrDA output pulse width. The setting is shown together with bits 6 to 3 (ICK3 to ICK0) of the serial mode register (SCSMR). Serial Mode Register (SCSMR) SCIMR Bit 6: ICK3 Bit 5: ICK2 Bit 4: ICK1 Bit 3: ICK0 Bit 2: PSEL ICK3 ICK2 ICK1 ICK0 1 Pulse width: 3/16 of bit length set in bits ICK3 to ICK0 Don’t care Don’t care Don’t care Don’t care 0 Pulse width: 3/16 of bit length set in SCBRR (Initial value) Description Note: A fixed clock pulse signal, IRCLK, must be generated by multiplying the Pφ clock by 1/2 N + 2 (where N is determined by the value set in ICK3 to ICK0). For details, see section 14.3.6 Pulse Width Selection. Bit 5—IrDA Receive Data Inverse (RIVS): Allows inversion of the receive data polarity to be selected in IrDA communication. Bit 5: RIVS Description 0 Receive data polarity inverted in reception 1 Receive data polarity not inverted in reception (Initial value) Note: Make the selection according to the characteristics of the IrDA modulation/demodulation module. Bits 4 to 0—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 590 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.3 Operation 14.3.1 Overview The SCIF can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. An IrDA block is also provided, enabling infrared communication conforming to IrDA 1.0 to be executed by connecting an infrared transmission/reception unit. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed. Selection of asynchronous, synchronous, or IrDA mode and the transmission format is made by means of the serial mode register (SCSMR) and IrDA mode register (SCIMR) as shown in table 14.8. The SCIF clock source is determined by a combination of the C/A bit in SCSMR, the IRMOD bit in SCIMR, and the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 14.9. • Asynchronous Mode  Data length: Choice of 7 or 8 bits  Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transmit/receive format and character length)  Detection of framing, parity, and overrun errors, receive FIFO data full and receive data ready conditions, and breaks, during reception  Detection of transmit FIFO data empty condition during transmission  Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on a clock with a frequency of 16, 8, or 4 times the bit rate of the baud rate generator, and can output this operating clock. When external clock is selected: A clock with a frequency of 16, 8, or 4 times the bit rate must be input (the built-in baud rate generator is not used). • Synchronous Mode  Transmit/receive format: Fixed 8-bit data  Detection of overrun errors during reception  Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and can output a serial clock to external devices. Rev. 2.00 Mar 09, 2006 page 591 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) When external clock is selected: The on-chip baud rate generator is not used, and the SCIF operates on the input serial clock. • IrDA Mode  IrDA 1.0 compliance  Data length: 8 bits  Stop bit length: 1 bit  Protection function to prevent receiver being affected during transmission  Clock source: Internal clock Table 14.8 SCSMR and SCIMR Settings for Serial Transmit/Receive Format Selection SCIMR SCSMR Settings SCIF Transmit/Receive Format Bit 7: IRMOD Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: C/A A CHR MP PE STOP Mode 0 0 0 0 0 0 1 1 Data Length MP Bit Asynchronous 8-bit mode data Absent Parity Bit Absent 1 bit 2 bits 0 Present 1 bit 1 1 0 2 bits 0 7-bit data 1 1 Absent 1 bit 2 bits 0 Present 1 bit 1 0 1 1 Stop Bit Length 2 bits * 0 Asynchronous 8-bit mode (multi- data processor format) Present Absent 1 bit * 1 * 0 * 1 * * Synchronous mode 8-bit data Absent Absent None 2 bits 7-bit data 1 bit 2 bits 0 1 * * 1 0 ICK3 ICK2 ICK1 ICK0 IrDA mode 8-bit data Absent Absent 1 bit 1 * * * Setting prohibited — — — * Note: An asterisk in the table means “Don’t care.” Rev. 2.00 Mar 09, 2006 page 592 of 906 REJ09B0292-0200 — Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.9 SCSMR and SCSCR Settings for SCIF Clock Source Selection SCSMR SCSCR Setting Bit 7: C/A A Bit 1: CKE1 Bit 0: CKE0 0 0 0 SCIF Transmit/Receive Clock Mode Asynchronous mode Clock Source SCK Pin Function Internal SCIF does not use SCK pin 1 1 Outputs clock with frequency of 16/8/4 times bit rate 0 External Inputs clock with frequency of 16/8/4 times bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 1 1 Synchronous mode 0 1 14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.3 shows the general format for asynchronous serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCIF monitors the line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (LSB-first or MSB-first order selectable), a parity bit or multiprocessor bit (high or low level), and finally one or two stop bits (high level). Rev. 2.00 Mar 09, 2006 page 593 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In asynchronous mode, the SCIF performs synchronization at the falling edge of the start bit in reception. The SCIF samples the data on the eighth (fourth, second) pulse of a clock with a frequency of 16 (8, 4) times the length of one bit, so that the transfer data is latched at the center of each bit. 1 Serial data (LSB) 0 Start bit 1 bit D0 Idle state (mark state) 1 (MSB) D1 D2 D3 D4 D5 D6 D7 Transmit/receive data 7 or 8 bits 0/1 1 Parity bit Stop bit(s) 1 bit, or none 1 or 2 bits 1 One unit of transfer data (character or frame) Figure 14.3 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits, LSB-First Transfer) Transmit/Receive Format: Table 14.10 shows the transmit/receive formats that can be used in asynchronous mode. Any of 12 transmit/receive formats can be selected by means of settings in the serial mode register (SCSMR). Rev. 2.00 Mar 09, 2006 page 594 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.10 Serial Transmit/Receive Formats (Asynchronous Mode) SCSMR Settings Serial Transmit/Receive Format and Frame Length CHR PE MP STOP 1 0 0 S 8-bit data STOP 1 S 8-bit data STOP STOP 0 S 8-bit data P STOP 1 S 8-bit data P STOP STOP 0 S 8-bit data STOP 1 S 8-bit data STOP STOP 0 S 7-bit data P STOP 1 S 7-bit data P STOP STOP 0 S 8-bit data MPB STOP * 1 S 8-bit data MPB STOP STOP * 0 S 7-bit data MPB STOP * 1 S 7-bit data MPB STOP STOP 0 0 1 1 0 1 0 1 * 1 2 3 4 5 6 7 8 9 10 11 12 Note: An asterisk in the table means “Don’t care.” Legend S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 2.00 Mar 09, 2006 page 595 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 14.9. When an external clock is input at the SCK pin, the input clock frequency should be 16, 8, or 4 times the bit rate used. When the SCIF is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is 16, 8, or 4 times the bit rate. Data Transmit/Receive Operations • SCIF Initialization (Asynchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in SCSCR, then initialize the SCIF as described below. When the operating mode, communication format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of the serial status 1 register (SC1SSR), the transmit FIFO data register (SCFTDR), or the receive FIFO data register (SCFRDR). The TE bit should not be cleared to 0 until all transmit data has been transmitted and the TEND flag has been set in SC1SSR. It is possible to clear the TE bit to 0 during transmission, but the data being transmitted will go to the high-impedance state after TE is cleared. Also, before starting transmission by setting TE again, the TFRST bit should first be set to 1 in SCFCR to reset SCFTDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 14.4 shows a sample SCIF initialization flowchart. Rev. 2.00 Mar 09, 2006 page 596 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, and MPIE, and bits TE and RE, to 0. When clock output is selected in asynchronous mode, it is output immediately after SCSCR settings are made. Select input or output for the SCK pin with the PFC. Initialization Clear TE and RE bits to 0 in SCSCR Set TFRST and RFRST bits to 1 in SCFCR Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) 1 2. Set the transmit/receive format in SCSMR. When using IrDA mode, also set SCIFMR. Set transmit/receive format in SCSMR 2 3. Write a value corresponding to the bit rate into the bit rate register (SCBRR). (Not necessary if an external clock is used.) Set value in SCBRR 3 Wait 1-bit interval elapsed? No Yes Set RTRG1–0 and TTRG1–0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE or RE bit to 1 in SCSCR, and set RIE, TIE, and MPIE bits 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, TIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. 4 End Figure 14.4 Sample SCIF Initialization Flowchart • Serial Data Transmission (Asynchronous Mode) Figure 14.5 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Rev. 2.00 Mar 09, 2006 page 597 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1 Initialization Start of transmission Read TDFE bit in SC1SSR 2 No TDFE = 1? Yes 3 No Yes Read TEND bit in SC1SSR No TEND = 1? Yes No Break output? Yes 2. SCIF status check and transmit data write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR) and clear the TDFE bit to 0 after reading TDFE = 1. The TEND bit is cleared automatically when transmission is started by writing transmit data. The number of data bytes that can be written is {16 – (transmit trigger set number)}. Write {16 – (transmit trigger set number)} bytes of transmit data to SCFTDR, and clear TDFE bit to 0 in SC1SSR after reading TDFE = 1 All data transmitted? 1. PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. 4 Clear DR to 0 Clear TE bit to 0 in SCSCR, and set TxD pin as output port with PFC 3. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE bit to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. (Checking and clearing of the TDFE bit is automatic when the DMAC is activated by a transmit-FIFOdata-empty interrupt (TXI) request, and data is written to SCFTDR.) 4. Break output at the end of serial transmission: To output a break in serial transmission, clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR, and set the TxD pin as an output port with the PFC. In steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in SCFTDR indicated in the upper 8 bits of the FIFO data count register (SCFDR). End of transmission Figure 14.5 Sample Serial Transmission Flowchart Rev. 2.00 Mar 09, 2006 page 598 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO control register (SCFCR) during transmission, the TDFE flag is set. If the TE bit setting in the serial control register (SCSCR) is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first or MSB-first order according to the setting of the TLM bit in SC2SSR. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the stop bit. If there is data in SCFTDR, it is transferred to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in the serial status 1 register (SC1SSR), the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Figure 14.6 shows an example of the operation for transmission in asynchronous mode. Rev. 2.00 Mar 09, 2006 page 599 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1 Serial data Start bit Data 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt request TXI interrupt request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame Figure 14.6 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit, LSB-First Transfer) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 14.7 shows an example of the operation when modem control is used. Start bit Serial data 0 Parity Stop bit bit D0 D1 D7 0/1 Start bit 0 D0 D1 CTS Drive high at this point before stop bit Figure 14.7 Example of Operation Using Modem Control (CTS CTS) CTS Rev. 2.00 Mar 09, 2006 page 600 of 906 REJ09B0292-0200 D7 0/1 Section 14 Serial Communication Interface with FIFO (SCIF) • Serial Data Reception (Asynchronous Mode) Figure 14.8 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Initialization 1 1. PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC. 2. Receive error handling and break detection: Read ER, BRK, FER, PER, and DR in SC1SSR, and ORER in SC2SSR, to check whether a receive error has occurred. If a receive error has occurred, read the Read ER, BRK, FER, PER, ER, BRK, FER, PER, and DR flags in and DR bits in SC1SSR, and 2 SC1SSR and the ORER flag in SC2SSR ORER bit in SC2SSR to identify the error. After performing the appropriate error handling, ensure that the ORER, BRK, DR, and ER bits are all ER ∨ BRK ∨ Yes cleared to 0. Reception cannot be FER ∨ PER ∨ DR ∨ resumed if the ORER bit is set to 1. The ORER = 1? setting of the EI bit in SC2SSR determines whether reception is Error handling No continued or halted when any of PER3–0 or FER3–0 is set to 1. In the case of a framing error, a break 3 Read RDF flag in SC1SSR can be detected by reading the value of the RxD pin. Start of reception No RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR No All data received? Yes Clear RE bit to 0 in SCSCR End of reception 4 3. SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR) and clear the RDF bit to 0. Transition of the RDF bit from 0 to 1 can also be identified by means of an RXI interrupt. 4. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, and write 0 to the RDF flag after reading 1 from it. The number of receive data bytes in SCFRDR can be ascertained by reading the lower bits of the FIFO data count register (SCFDR). (The RDF bit is cleared automatically when the DMAC is activated by an RXI interrupt and the SCFRDR value is read.) Figure 14.8 Sample Serial Reception Flowchart (1) Rev. 2.00 Mar 09, 2006 page 601 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SC1SSR. Error handling No ORER = 1? Yes 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the H'00 break data in which a framing error occurred is stored as the last data in SCFRDR. Overrun error handling No BRK = 1? Yes Clear RE bit to 0 in SCSCR No DR = 1? Yes Read receive data from SCFRDR No 1 FER = 1? Yes Framing error handling No 2 PER = 1? Yes Parity error handling No All data read? Yes Clear ORER, BRK, DR, and ER flags to 0 End Figure 14.8 Sample Serial Reception Flowchart (2) Rev. 2.00 Mar 09, 2006 page 602 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order or MSB-to-LSB order according to the setting of the RLM bit in SC2SSR. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Parity check: The SCIF checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/E bit in the serial mode register (SCSMR). b. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. d. Break check: The SCIF checks that the BRK flag is 0, indicating no break. If all the above checks are passed, the receive data is stored in SCFRDR. If a receive error is detected in the error check, the operation is as shown in table 14.11. Note: No further receive operations can be performed when an overrun error has occurred. The setting of the EI bit in SC2SSR determines whether reception is continued or halted when a framing error or parity error occurs. Also, as the RDF flag is not set to 1 when receiving, the error flags must be cleared to 0. 4. If the RIE bit setting in SCSCR is 1 when the RDF or DR flag is set to 1, a receive-FIFO-datafull interrupt (RXI) is requested. If the RIE bit setting in SCSCR is 1 when the ORER, PER, or FER flag is set to 1, a receiveerror interrupt (ERI) is requested. If the RIE bit setting in SCSCR is 1 when the BRK flag is set to 1, a break-receive interrupt (BRI) is requested. Rev. 2.00 Mar 09, 2006 page 603 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Next serial receive operation is Receive data is not transferred completed while there are 16 from SCRSR to SCFRDR receive data bytes in SCFRDR Framing error FER Stop bit is 0 Receive data is transferred from SCRSR to SCFRDR Parity error PER Received data parity differs from that (even or odd) set in SCSMR Receive data is transferred from SCRSR to SCFRDR Figure 14.9 shows an example of the operation for reception in asynchronous mode. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) RDF FER RXI interrupt request Data read and RDF flag cleared to 0 by RXI interrupt handler ERI interrupt request due to framing error One frame Figure 14.9 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit, LSB-First Transfer) 5. When modem control is enabled, the RTS signal is output when SCFRDR is empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR is full and reception is not possible. Figure 14.10 shows an example of the operation when modem control is used. Rev. 2.00 Mar 09, 2006 page 604 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Start bit Serial data 0 Parity bit D0 D1 D2 D7 0/1 Start bit 1 0 RTS Figure 14.10 Example of Operation Using Modem Control (RTS RTS) RTS 14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial communication line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving stations skip the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, each receiving stations compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 14.11 shows an example of inter-processor communication using a multiprocessor format. Rev. 2.00 Mar 09, 2006 page 605 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: Receiving station specification (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID Legend MPB: Multiprocessor bit Figure 14.11 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Transmit/Receive Formats: There are four transmit/receive formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 14.10. Clock: See the section on asynchronous mode. Data Transmit/Receive Operations • SCI Initialization See the section on asynchronous mode. • Multiprocessor Serial Data Transmission Figure 14.12 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCIF for transmission. Rev. 2.00 Mar 09, 2006 page 606 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1 Initialization Start of transmission Read TDFE bit in SC1SSR 2 No TDFE = 1? Yes Write {16 – (transmit trigger set number)} bytes of transmit data to SCFTDR, and set MPBT in SC2SSR Clear TDFE and TEND flags to 0 No End of transmission? 3 Yes Read TEND bit in SC2SSR No TEND = 1? Yes Clear DR to 0 Clear TE bit to 0 in SCSCR, and set TxD pin as output port with PFC 2. SCIF status check and transmit data write: Read the serial status 1 register (SC1SSR) and check that the TDFE bit is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR). Set the MPBT bit to 0 or 1 in SC1SSR. Finally, clear the TDFE and TEND flags to 0 after reading 1 from them. The number of data bytes that can be written is {16 – (transmit trigger set number)}. 3. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE bit to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE bit to 0. (Checking and clearing of the TDFE bit is automatic when the DMAC is activated by a transmit-FIFO-data-empty interrupt (TXI) request, and data is written to SCFTDR.) 4. Break output at the end of serial transmission: To output a break in serial transmission, clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR, and set the TxD pin as an output port with the PFC. No Break output? Yes 1. PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. 4 In steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in SCFTDR indicated in the upper 8 bits of the FIFO data count register (SCFDR). End of transmission Figure 14.12 Sample Multiprocessor Serial Transmission Flowchart Rev. 2.00 Mar 09, 2006 page 607 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to SCFTDR, the SCIF transfers the data to SCTSR and starts transmitting. Check that the TDFE flag is set to 1 in SC1SSR before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR during transmission, the TDFE flag is set to 1. If the TIE bit setting in SCSCR is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first or MSB-first order according to the setting of the TLM bit in SC2SSR. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the stop bit. If there is data in SCFTDR, it is transferred to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in SC1SSR, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Figure 14.13 shows an example of SCIF operation for transmission using a multiprocessor format. Rev. 2.00 Mar 09, 2006 page 608 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1 Serial data Start bit 0 Multiproces- Stop Start sor bit bit bit Data D0 D1 D7 0/1 1 0 Multiproces- Stop sor bit bit D0 D1 D7 0/1 1 1 Idle state (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler One frame Figure 14.13 Example of SCIF Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer) • Multiprocessor Serial Data Reception Figure 14.14 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCIF for reception. Rev. 2.00 Mar 09, 2006 page 609 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Initialization 1. PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC. 1 Start of reception 2. ID reception cycle: Set the MPIE bit to 1 in SCSCR. Set MPIE bit to 1 in SCSCR Read ER, BRK, FER, and DR bits in SC1SSR, and ORER bit in SC2SSR BRK ∨ DR ∨ ER ∨ ORER = 1? 2 Yes No Read RDF flag in SC1SSR No RDF = 1? 3 Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR No This station’s ID? 4 Yes Read BRK and DR bits in SC1SSR, and ER bit in SC2SSR BRK ∨ DR ∨ ER = 1? Yes No Read RDF flag in SC1SSR RDF = 1? Yes Read receive data from SCFRDR No No 5 3. SCIF status check, ID reception and comparison: Read SC1SSR and check that the RDF bit is set to 1, then read the receive data in the receive FIFO data register (SCFRDR) and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDF bit to 0. If the data is this station’s ID, clear the RDF bit to 0. 4. Receive error handling and break detection: Read the ER, BRK, FER, and DR flags in SC1SSR and the ORER flag in SC2SSR to check whether a receive error has occurred. If a receive error has occurred, read the ER, BRK, FER, and DR flags in SC1SSR and the ORER flag in SC2SSR to identify the error. After performing the appropriate error handling, ensure that ER, BRK, DR, and ORER are all cleared to 0. The setting of the EI bit in SC2SSR determines whether reception is continued or halted when the ORER bit is set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 5. SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR). All data received? Yes Error handling Clear RE bit to 0 in SCSCR End of reception Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 2.00 Mar 09, 2006 page 610 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error has occurred in the receive data read from SCFRDR can be ascertained from the FER bit in SC1SSR. Error handling No ORER = 1? 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a framing error occurred is stored. However, note that the H'00 break data in which a framing error occurred is stored as the last data in SCFRDR. Yes Overrun error handling No BRK = 1? Yes Clear RE bit to 0 in SCSCR No DR = 1? Yes Read receive data from SCFRDR No 1 FER = 1? Yes Framing error handling No 2 All data read? Yes Clear ORER, BRK, DR, and ER flags to 0 End Figure 14.14 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00 Mar 09, 2006 page 611 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Figure 14.15 shows an example of SCIF operation for multiprocessor format reception. Start bit 1 Serial data 0 Stop Start bit Data (Data1) MPB bit Data (ID1) D0 D1 D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDF SCFRDR value ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler As data is not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and SCFRDR retains its state (a) Data does not match station’s ID Start bit 1 Serial data 0 Stop Start bit Data (Data2) MPB bit Data (ID2) D0 D1 D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDF SCFRDR value ID2 ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler As data matches this station’s ID, reception continues and data is received by RXI interrupt handler Data2 MPIE bit set to 1 again (b) Data matches station’s ID Figure 14.15 Example of SCIF Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit, LSB-First Transfer) Rev. 2.00 Mar 09, 2006 page 612 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication using a common clock. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14.16 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don’t care Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t care Note: * High except in continuous transmission/reception Figure 14.16 Data Format in Synchronous Communication (Example of LSB-First Transfer) In synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In serial communication, each character is output starting with the LSB and ending with the MSB, or vice versa, according to the setting of the TLM bit in the serial status 2 register (SC2SSR). After the last data is output, the communication line remains in the state of the last data. In synchronous mode, the SCIF receives data in synchronization with the rise of the serial clock. Rev. 2.00 Mar 09, 2006 page 613 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Transmit/Receive Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 14.9. When the SCIF is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. In receive-only operation, however, the SCIF receives two characters as one unit, and so a 16-pulse serial clock is output. To perform single-character receive operations, an external clock should be selected as the clock source. Transmit/Receive Operations • SCIF Initialization (Synchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as described below. When the operating mode, communication format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDFE flag is set to 1 and the transmit shift register (SCTSR) is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDF, PER, FER, and ORER flags, or the receive FIFO data register (SCFRDR). Figure 14.17 shows a sample SCIF initialization flowchart. Rev. 2.00 Mar 09, 2006 page 614 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, MPIE, TE, and RE to 0. Initialization Clear TE and RE bits to 0 in SCSCR 2. Set the transmit/receive format in the serial mode register (SCSMR). 3. Write a value corresponding to the bit rate into the bit rate register (SCBRR). (Not necessary if an external clock is used.) Clear TFRST and RFRST bits to 1 in SCFCR Set RIE, TIE, MPIE, CKE1, and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) 1 Set data transmit/receive format in SCSMR 2 Set value in SCBRR 3 4. Wait at least one bit interval, then set the TE bit or RE bit to 1 in SCSCR. Also set the RIE, TIE, and MPIE bits. Setting the TE and RE bits simultaneously enables the TxD and RxD pins to be used. Wait 1-bit interval elapsed? No Yes Set RTRG1–0 bits and TTRG1–0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set TE or RE bit to 1 in SCSCR, and set RIE, TIE, and MPIE bits 4 End Figure 14.17 Sample SCIF Initialization Flowchart Rev. 2.00 Mar 09, 2006 page 615 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) • Serial Data Transmission (Synchronous Mode) Figure 14.18 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Initialization 1 Start of transmission Read TDFE flag in SC1SSR TDFE = 1? 2 No Yes Write transmit data to SCFTDR and clear TDFE flag to 0 in SC1SSR All data transmitted? 1. PFC initialization: Set the TxD pin, and the SCK pin if necessary, with the PFC. 2. SCIF status check and transmit data write: Read SC1SSR and check that TDFE =1, then write transmit data to the transmit FIFO data register (SCFTDR) and clear the TDFE flag to 0. 3. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. No 3 Yes Read TEND flag in SC1SSR TEND = 1? No Yes Clear TE bit to 0 in SCSCR End Figure 14.18 Sample Serial Transmission Flowchart Rev. 2.00 Mar 09, 2006 page 616 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written to the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR), and starts transmitting. Check that the TDFE flag is set to 1 in the serial status 1 register (SC1SSR) before writing transmit data to SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set number)}. 2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit operations are performed continually until there is no transmit data left in SCFTDR. If the number of data bytes in SCFTDR falls to or below the transmit trigger number set in the FIFO control register (SCFCR) during transmission, the TDFE flag is set. If the TIE bit setting in the serial control register (SCSCR) is 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) is requested. When clock output mode has been set, the SCIF outputs eight serial clock pulses for one unit of data. When use of an external clock has been specified, data is output in synchronization with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) or MSB (bit 7) according to the setting of the TLM bit in the serial status 2 register (SC2SSR). 3. The SCIF checks for transmit data in SCFTDR at the timing for sending the last bit. If there is transmit data in SCFTDR, it is transferred to SCTSR and then serial transmission of the next frame is started. If there is no transmit data in SCFTDR, the TEND flag is set to 1 in the serial status 1 register (SC1SSR), the last bit is sent, and then the transmit data pin (TxD) holds its state. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 14.19 shows an example of SCIF operation in transmission. Rev. 2.00 Mar 09, 2006 page 617 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Transfer direction Serial clock MSB LSB Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 14.19 Example of SCIF Transmit Operation (Example of LSB-First Transfer) • Serial Data Reception (Synchronous Mode) Figure 14.20 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When changing the operating mode from asynchronous to synchronous without resetting SCFRDR and SCFTDR by means of SCIF initialization, be sure to check that the ORER, PER3 to PER0, and FER3 to FER0 flags are all cleared to 0. The RDF flag will not be set if any of flags FER3 to FER0 or PER3 to PER0 are set to 1, and neither transmit nor receive operations will be possible. Rev. 2.00 Mar 09, 2006 page 618 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Initialization 1. PFC initialization: Set the RxD pin, and the SCK pin if necessary, with the PFC. 1 Start of reception 2. Receive error handling: If a receive error occurs, read the ORER flag in SC2SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Read ORER flag in SC2SSR Yes ORER = 1? No 2 Error handling Read RDF flag in SC1SSR No 3 RDF = 1? Yes Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR No All data received? Yes Clear RE bit to 0 in SCSCR 4 3. SCIF status check and receive data read: Read the serial status 1 register (SC1SSR) and check that RDF = 1, then read receive data from the receive FIFO data register (SCFRDR) and clear the RDF flag to 0. Transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 4. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of data bytes from SCFRDR, and write 0 to the RDF flag after reading 1 from it. The number of receive data bytes in SCFRDR can be ascertained by reading the lower 8 bits of the FIFO data count register (SCFDR). (The RDF bit is cleared automatically when the DMAC is activated by an RXI interrupt and the SCFRDR value is read.) End of reception Figure 14.20 Sample Serial Reception Flowchart (1) Rev. 2.00 Mar 09, 2006 page 619 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag to 0 in SC2SSR End Figure 14.20 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in the receive shift register (SCRSR) in LSB-to-MSB order or MSB-to-LSB order according to the setting of the RLM bit in SC2SSR. After reception, the SCIF checks whether the receive data can be transferred from SCRSR to the receive FIFO data register (SCFRDR). If this check is passed, the receive data is stored in SCFRDR. If a receive error is detected in the error check, the operation is as shown in table 14.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit setting in the serial control register (SCSCR) is 1 when the RDF flag is set to 1, a receive-FIFO-data-full interrupt (RXI) is requested. If the RIE bit setting in SCRSR is 1 when the ORER flag is set to 1, a receive-error interrupt (ERI) is requested. Figure 14.21 shows an example of SCIF operation in reception. Rev. 2.00 Mar 09, 2006 page 620 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDF ORER RXI interrupt request Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler RXI interrupt request ERI interrupt request due to overrun error One frame Figure 14.21 Example of SCIF Receive Operation (Example of LSB-First Transfer) • Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 14.22 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCIF for transmission and reception. Rev. 2.00 Mar 09, 2006 page 621 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 1. PFC initialization: Set the TxD and RxD pins, and the SCK pin if necessary, with the PFC. 1 Initialization Start of transmission/ reception Read TDFE flag in SC1SSR No 2. SCIF status check and transmit data write: Read SC1SSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR and clear the TDFE flag to 0. Transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. 2 TDFE = 1? 3. Receive error handling: If a receive error occurs, read the ORER flag in SC2SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Yes Write transmit data to SCFTDR and clear TDRE flag to 0 in SC1SSR Read ORER flag in SC2SSR Yes ORER = 1? 3 No Error handling Read RDF flag in SC1SSR No RDF = 1? Yes No Read receive data from SCFRDR, and clear RDF flag to 0 in SC1SSR 4 All data transferred? 5 Yes Clear TE and RE bits to 0 in SCSCR 4. SCIF status check and receive data read: Read SC1SSR and check that the RDF flag is set to 1, then read receive data from SCFRDR and clear the RDF flag to 0. Transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 5. Serial transmission/reception continuation procedure: To continue serial transmission/reception, finish reading the RDF flag, reading SCFRDR, and clearing the RDF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR and clear the TDFE flag to 0. Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, first clear the TE bit and RE bit to 0, then set the TE bit and RE bit to 1 simultaneously. End of transmission/ reception Figure 14.22 Sample Flowchart for Serial Data Transmission and Reception Rev. 2.00 Mar 09, 2006 page 622 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.5 Use of Transmit/Receive FIFO Buffers The SCIF has independent 16-stage FIFO buffers for transmission and reception. The configuration of these buffers is shown in figure 14.23. TxD RxD SCTSR SCRSR P P F P/G SCFTDR 1st stage 2nd stage 3rd stage SCFRDR 1st stage 2nd stage 3rd stage Error counter SC1SSR PER3–PER0 FER3–FER0 16th stage 16th stage Data counter SCFER ED15–ED0 SCFDR T3–T0 R3–R0 Transmit data writes by CPU or DMAC Receive data reads by CPU or DMAC Figure 14.23 Transmit/Receive FIFO Configuration Rev. 2.00 Mar 09, 2006 page 623 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) In Serial Data Transmit Operations: In transmission, when transmit data is written to the transmit FIFO by the CPU or DMAC and the TE bit is set to 1 in the serial control register (SCSCR), the data is first transferred to the transmit shift register (SCTSR) in the order of writing to the transmit FIFO, a parity bit is added by the parity generator (P/G), and then serial data is transmitted from the TxD pin. Each time data is written into the transmit FIFO, the value in bits T4 to T0 in the FIFO data count register (SCFDR) is incremented, and each time data is transferred to SCTSR the value in bits T4 to T0 is decremented. The current number of data bytes in the transmit FIFO can thus be found by reading bits T4 to T0 in SCFDR. A value of H'10 in bits T4 to T0 means that data has been written into all 16 stages of the transmit FIFO. If additional data is written to the FIFO in this state, bits T4 to T0 will not be incremented and the written data will be lost. When the transmit trigger number is set and transmit data is written to the FIFO by the DMAC, care must be taken not to write data exceeding the number of empty bytes in SCFTDR indicated by the FIFO control register (SCFCR) (see section 14.2.10). In Serial Data Receive Operations: In reception, serial data input from the RxD pin is first captured in the receive shift register (SCRSR) in the order specified by the RLM bit in the serial status 2 register (SC2SSR). A parity bit check is carried out, and if there is a parity error the P (parity error) flag for that data is set to 1. A stop bit check is also performed, and if a framing error is found the F (framing error) flag for that data is set to 1. The receive FIFO buffer has a 10-bit configuration, with the P and F flags for each 8-bit data unit stored together with that data. • Receive FIFO Control in Normal Operation Receive data held in the receive FIFO buffer is read by the CPU or DMAC. Each time data is transferred from SCRSR to the receive FIFO, the value in bits R4 to R0 in SCFDR is incremented, and each time the CPU or DMAC reads receive data from the receive FIFO, the value in bits R4 to R0 is decremented. The current number of data bytes in the receive FIFO can thus be found by reading bits R4 to R0 in SCFDR. A value of H'10 in bits R4 to R0 means that receive data has been transferred to all 16 stages of the receive FIFO. If the next serial receive operation is completed before the CPU or DMAC reads data from the receive FIFO, an overrun error will result and the serial data will be lost. If receive FIFO data is read when the value of bits R4 to R0 is H'00, an undefined value will be returned. Rev. 2.00 Mar 09, 2006 page 624 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) • Receive FIFO Control in Error Data Reception When data is transferred from SCRSR to the receive FIFO, the P and F flags are also transferred. If either of these flags is set to 1, the error counter is incremented and the corresponding bit (PER3 to PER0, FER3 to FER0) is updated in the serial status 1 register (SC1SSR). The error counter is decremented if the P or F flag is 1 when data in the receive FIFO is read by the CPU or DMAC. The settings of the P and F flags for the read receive data are also reflected in the PER and FER flags in SC1SSR. PER and FER are set when data containing a parity error or framing error is read from the receive FIFO; they are not set when serial data containing a parity error or framing error is received from the RxD pin. PER and FER are cleared when data with no parity error or framing error is read from the receive FIFO. This data is transferred to the receive FIFO even if it contains a parity error or framing error. Whether or not the receive operation is to be continued at this point can be specified with the EI bit in SC2SSR. If the EI bit is set to 1, specifying continuation of the receive operation, receive data is still transferred sequentially to the receive FIFO after an error occurs. The stage of the 16-stage FIFO buffer in which the data with the error is located can be determined by reading bits ED15 to ED0 in the FIFO error register (SCFER). When the receive trigger number is set and receive data is read from the receive FIFO by the DMAC, care must be taken not to read data exceeding the receive trigger number indicated by the FIFO control register (SCFCR) (see section 14.2.10). • Receive FIFO Control by DR Flag When a number of data bytes equal to or exceeding the receive trigger number have been received, a receive data read request is issued to the CPU or DMAC by means of an RXI interrupt (RDF only). However, an RXI interrupt is not requested if all reception has been completed with fewer than the receive trigger number of data bytes having been received. In this case, the DR flag is set and an ERI interrupt is requested 16 etu after reception of the last data is completed. The CPU should therefore read bits R4 to R0 in SCFDR to find the number of data bytes left in the receive FIFO, and read all the data in the FIFO. Note: With an 8-bit, 1-stop-bit format, one etu is equivalent to 1.6 frames. etu: Elementary time unit = sec/bit Rev. 2.00 Mar 09, 2006 page 625 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.3.6 Operation in IrDA Mode In IrDA mode, the waveform of TxD/RxD transmit/receive data is modified to comply with the IrDA 1.0 infrared communication specification. This makes it possible to carry out infrared transmission and reception conforming to the IrDA 1.0 standard by connecting an infrared transmission/reception transceiver/receiver. In the IrDA 1.0 specification, communication is initially executed at 9600 bps, and then the transfer rate can be changed as required. However, the communication speed is not changed automatically in this module. When executing communication, therefore, it is necessary to check the communication speed and have the appropriate speed set in this module by software. Note: In IrDA mode, reception is not possible when the TE bit is set to 1 (enabling communication) in the serial control register (SCSCR). When performing reception, the TE bit in SCSCR must be cleared to 0. Transmission: In the case of a serial output signal (UART frame) from the SCIF, the waveform is corrected and the signal is converted to an IR frame serial output signal by the IrDA module as shown in figure 14.24. When the serial data is 0, if the PSEL bit is 0 in the IrDA mode register (SCIMR) a pulse of 3/16 the IR frame bit width is generated and output, and if the PSEL bit is 1 a pulse of 3/16 the bit width of the bit rate set in bits ICK3 to 0 in the serial mode register (SCSMR) is generated and output. When the serial data is 1, a pulse is not output. An infrared LED is driven by a signal demodulated to a 3/16 width. Reception: Pulses of 3/16 the received IR frame bit width are converted to UART frames after demodulation as shown in figure 14.24. Demodulation to 0 is executed for pulse output and demodulation to 1 when there is no pulse output. Rev. 2.00 Mar 09, 2006 page 626 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) UART frame Start bit Stop bit Data 0 1 0 1 0 0 1 1 0 1 Transmission Reception IR frame Start bit Stop bit Data 0 1 0 1 0 0 1 1 0 1 3/16 bit cycle pulse width Bit cycle Figure 14.24 IrDA Mode Transmit/Receive Operations Pulse Width Selection: In transmission, the IR frame pulse width can be selected as either 3/16 of the transmission bit rate or a smaller pulse width by means of the PSEL bit in the IrDA mode register (SCIMR). The SCIF includes a baud rate generator that generates the transmit frame bit rate and a baud rate generator that generates the IRCLK signal for varying the pulse width. When the PSEL bit is cleared to 0 in SCIMR, a width of 3/16 the bit rate set in the bit rate register (SCBRR) is output as the IR frame pulse width. As the pulse width is the direct infrared emission time; if the user wishes to minimize the pulse width in order to reduce power consumption, the PSEL bit should be set to 1 in SCIMR and a setting should also be made in bits ICK3 to ICK0 in the serial mode register (SCSMR) to generate the IRCLK signal, resulting in output with the minimum settable pulse width. Rev. 2.00 Mar 09, 2006 page 627 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) The minimum IR frame pulse width must be 3/16 of the 115.2 kbps bit rate (= 1.63 µsec). With this minimum pulse width, IRCLK = 921.6 kHz, and so the setting for bits ICK3 to ICK0 to give the minimum settable pulse width is given by the following equation. N≥ Pφ 2 × IRCLK –1 Pφ: Operating clock frequency IRCLK: 921.6 kHz (fixed) N: Set value of ICK3 to ICK0 (0 ≤ N ≤ 15) For example, when Pφ = 20 MHz, N = 10. Table 14.12 shows the settings of bits ICK3 to ICK0 that can be used to obtain the minimum pulse width for various operating frequencies. Rev. 2.00 Mar 09, 2006 page 628 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Table 14.12 Bits ICK3 to ICK0 and Operating Frequencies in IrDA mode (When PSEL = 1) Setting of Bits ICK3 to ICK0 in SCSMR Operating Frequency Pφ φ (MHz) ICK3 ICK2 ICK1 ICK0 2 0 0 0 0 3 1 5 1 6 1 8 1 0 10 0 1 12 1 14 16 0 0 1 1 0 0 18 0 1 20 1 0 21 1 22 1 23 1 0 24 1 25 26 0 1 1 0 27 0 28 1 Rev. 2.00 Mar 09, 2006 page 629 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 14.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: the break interrupt (BRI) request, receive-error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and transmit-FIFO-data-empty interrupt (TXI) request. Table 14.13 shows the interrupt sources and their relative priorities. The interrupt sources can be enabled or disabled with the TIE or RIE bit in SCSCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDFE flag is set to 1 in the serial status 1 register (SC1SSR), a TXI interrupt is requested. A TXI interrupt request can activate the DMAC to perform data transfer. The TDFE bit is cleared to 0 automatically when all writes to the transmit FIFO data register (SCFTDR) by the DMAC are completed. When the RDF flag is set to 1 in SC1SSR, an RXI interrupt is requested. An RXI interrupt request can activate the DMAC to perform data transfer. The RDF bit is cleared to 0 automatically when all receive FIFO data register (SCFRDR) reads by the DMAC are completed. When the ER flag is set to 1, an ERI interrupt is requested. The DMAC cannot be activated by an ERI interrupt request. When the BRK flag is set to 1, a BRI interrupt is requested. The DMAC cannot be activated by a BRI interrupt request. A TXI interrupt indicates that transmit data can be written, and an RXI interrupt indicates that there is receive data in SCFRDR. Table 14.13 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Receive error (ER) Not possible High RXI Receive data full (RDF) or data ready (DR) Possible (RDF only) ↑ BRI Break (BRK) Not possible ↓ TXI Transmit data FIFO empty (TDFE) Possible Rev. 2.00 Mar 09, 2006 page 630 of 906 REJ09B0292-0200 Low Section 14 Serial Communication Interface with FIFO (SCIF) 14.5 Usage Notes The following points should be noted when using the SCIF. SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status 1 register (SC1SSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SC1SSR and SC2SSR is as shown in table 14.14. If there is an overrun error, data is not transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), and the receive data is lost. Table 14.14 SC1SSR/SC2SSR Status Flags and Transfer of Receive Data SC1SSR/SC2SSR Status Flags Receive Errors RDF ORER FER PER Receive Data Transfer SCRSR → SCFRDR Overrun error 1 1 0 0 × Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 × Overrun error + parity error 1 1 0 1 × Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 × Notes: O: Receive data is transferred from SCRSR to SCFRDR. × : Receive data is not transferred from SCRSR to SCFRDR. Rev. 2.00 Mar 09, 2006 page 631 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues, so if the FER and BRK flags are cleared to 0 they will be set to 1 again. Sending a Break Signal: The TxD pin is a general I/O pin whose input/output direction and level are determined by the I/O port data register (DR) and the control register (CR) of the pin function controller (PFC). This fact can be used to send a break signal. The DR value substitutes for the mark state until the PFC setting is made. The initial setting should therefore be as an output port outputting 1. To send a break signal during serial transmission, clear DR, then set the TxD pin as an output port with the PFC. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when any of the receive error flags (ORER, PER3 to PER0, FER3 to FER0) is set to 1, even if the TDFE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCIF operates on a base clock with a frequency of 16, 8, or 4 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth, fourth, or second base clock pulse. The timing is shown in figure 14.25. Rev. 2.00 Mar 09, 2006 page 632 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.25 Receive Data Sampling Timing in Asynchronous Mode (Using base clock with frequency of 16 times the transfer rate, sampled in 8th clock cycle) The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = 0.5 – M: N: D: L: F: 1 D – 0.5 (1 + F) × 100% – (L – 0.5) F – 2N N ................. ............ (1) Receive margin (%) Ratio of clock frequency to bit rate (N = 16, 8, or 4) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5, F = 0, and N = 16: M = (0.5 – 1/(2 × 16)) × 100% = 46.875%...................................................................................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using Synchronous External Clock Mode • Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1. • Only set both TE and RE to 1 when external clock SCK is 1. Rev. 2.00 Mar 09, 2006 page 633 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) • In reception, note that if RE is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDF will be set to 1 but copying to SCFRDR will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDF will be set to 1 but copying to SCFRDR will not be possible. When Using the DMAC: When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 Pφ clock cycles after SCFTDR is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 Pφ cycles after SCFTDR is updated. (See figure 14.26.) When performing SCFRDR reads by the DMAC, be sure to set the relevant SCIF receive-FIFOdata-full interrupt (RXI) as an activation source. SCK t TDFE TXD D0 D1 D2 D3 D4 D5 D6 Figure 14.26 Example of Synchronous Transmission by DMAC SCFRDR Reading and the RDF Flag: The RDF flag in the serial status 1 register (SC1SSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after receive data has been read to reduce the number of data bytes in SCFRDR to less than the trigger number. Rev. 2.00 Mar 09, 2006 page 634 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). SCFRDR Reading when Overrun Occurs: If a receive operation is continued despite the fact that the receive FIFO data register (SCFRDR) contains 16 bytes of data, overrun will occur. If SCFRDR is read in this state, the data that caused the overrun is read in the 17th read. The value returned in the 18th and subsequent reads will be undefined. Also note that, from the first SCFRDR read onward, the number of receive data bytes in SCFRDR indicated by the lower 8 bits of the FIFO data count register (SCFDR) is one more than the actual number of receive data bytes. Rev. 2.00 Mar 09, 2006 page 635 of 906 REJ09B0292-0200 Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 Mar 09, 2006 page 636 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Section 15 Serial I/O with FIFO (SIOF) 15.1 Overview The serial I/O with FIFO functions mainly as an interface between the chip and a codec or modem analog front-end. 15.1.1 Features The serial I/O has the following features: • Full-duplex operation Independent transmit/receive registers and independent transmit/receive clocks • Primary data transmit/receive FIFO/Double-buffered transmit/receive ports Continuous data transmission/reception possible • Interval transfer mode and continuous transfer mode • Memory-mapped receive data register, transmit data register, serial control register, and serial status register, receive control data register, transmit control data register, FIFO control register, FIFO data count register With the exception of SIRSR and SITSR, these registers are memory-mapped and can be accessed by a MOV instruction. • Choice of 8- or 16-bit data length • Data transfer communication by means of polling or interrupts Data transfer can be monitored by polling the receive data register full flag (RDRF), the receive data register empty flag (RDRE), the receive control data register full flag (RCD), and the transmit control data register empty flag (TCD). Interrupt requests can be generated during data transfer by setting the receive interrupt request flag and the transmit interrupt request flag. • Either MSB-first or LSB transfer can be selected for data I/O operations. Figure 15.1 shows a block diagram of the serial I/O with FIFO. Rev. 2.00 Mar 09, 2006 page 637 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) 16bits Peripheral bus SISTR SICTR SIFCR SIFDR SIRDR SITDR SIRCDR SITCDR Bit counter I/O control unit MSB/LSB Conversion circuit selector SIRSR MSB/LSB Conversion circuit SITSR Serial I/O with FIFO module (SIOF) SRXD SIRDR: SIRCDR: SIRSR: SITDR: SITCDR: SRCK SRS STS STCK SITSR: SISTR: SICTR: SIFCR: SIFDR: Receive data register Receive control data register Receive shift register Transmit data register Transmit control data register STXD Transmit shift register Serial status register Serial control register FIFO control register FIFO data count register Figure 15.1 SIOF Block Diagram Table 15.1 shows the functions of the external pins. Table 15.1 Serial I/O with FIFO (SIOF) External Pins Name Pin I/O Function Serial receive data input pin SRxD0 Input Serial data input port Serial receive clock input pin SRCK0 Input Serial receive clock port Serial reception synchronization input pin SRS0 Input Serial reception synchronization input port Serial transmit data output pin STxD0 Output Serial data output port Serial transmit clock input pin STCK0 Input Serial transmit clock port I/O Serial transmission synchronization input/output port Serial transmission synchronization STS0 input/output pin Rev. 2.00 Mar 09, 2006 page 638 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) 15.2 Register Configuration Table 15.2 shows the SIOF’s registers. Table 15.2 Register Configuration Register Abbreviation R/W Initial Value Address Access Size (Bits) Receive shift register SIRSR0 — — — — Receive data register SIRDR0 R Not H'FFFFFC00 specified 8, 16, 32 Transmit shift register SITSR0 — — — — Transmit data register SITDR0 R/W H'0000 H'FFFFFC02 8, 16, 32 Serial control register SICTR0 R/W H'0000 H'FFFFFC04 8, 16, 32 Serial status register SISTR0 R/(W)* H'0002 H'FFFFFC06 8, 16, 32 Receive control data register SIRCDR R H'0000 H'FFFFFC0C 8, 16, 32 Transmit control data register SITCDR R/W H'0000 H'FFFFFC0E 8, 16, 32 FIFO control register SIFCR R/W H'0000 H'FFFFFC08 8, 16, 32 R H'0000 H'FFFFFC0A 8, 16, 32 FIFO data count register SIFDR Note: * Only 0 should be written, to clear flags (after reading 1 from the flag). 15.2.1 Receive Shift Register (SIRSR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: — — — ... — — — — R/W: — — — ... — — — — SIRSR is a 16-bit register used to receive serial data. The data is fetched in MSB first from the SRxD pin in synchronization with the fall of the serial receive clock (SRCK), and is shifted into SIRSR. The data length is set by the transmit/receive data length select bit (DL) in the corresponding serial control register (SICTR). If the DL bit is cleared to 0 (data length 8 bits), the receive data is fetched to the lower 8 bits, and the upper 8 bits are cleared to 0. When data transfer to SIRSR is completed, the data contents are automatically transferred to the receive data register (SIRDR), and the receive data register full flag (RDRF) is set in the serial status register (SISTR), based on the settings of the receive FIFO watermark bits (RFWM3 to RFWM0) in SIFCR. Rev. 2.00 Mar 09, 2006 page 639 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) When transfer of control data to SIRSR is completed, the data contents are automatically transferred to the receive control data register (SIRCDR), and the receive control data register full flag (RCD) is set in SISTR. If the next data word input operation ends before the RDRF flag is cleared, an overrun error occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent to the interrupt controller (INTC). The data in SIRSR overwrites the data in SIRDR. If SIRCDR contains valid control data, SIRCDR is overwritten after the next control data input operation completes. 15.2.2 Receive Data Register (SIRDR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R SIRDR is a 16-bit x 16-stage FIFO register that stores primary receive data. When primary data is transferred from SIRSR to SIRDR, the receive data register full flag (RDRF) is set in the serial status register (SISTR), based on the settings of RFWM3 to RFWM0 in SIFCR. If the receive interrupt enable flag (RIE) is set in SICTR, a receive-data-full interrupt (RDFI) request is sent to the interrupt controller (INTC) and the DMA controller (DMAC). When the flag is cleared, this interrupt request signal is not generated. When SIRDR is read by the DMAC, the RDRF flag is cleared automatically if the value is less than or equal to the setting of bits RFWM3 to RFWM0 in SIFCR. When SIRDR is reset, its status is empty. The status of SIRDR is also empty when the value of the receive FIFO data registry reset bit (RFRST) in SIFCR is 1. Note: Do not read from SIRDR when it contains no primary receive data (when the value of the receive data register data count bits 4 to 0 (R4 to R0) in the FIFO data count register (SIFDR) is 00000). Rev. 2.00 Mar 09, 2006 page 640 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) 15.2.3 Transmit Shift Register (SITSR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: — — — ... — — — — R/W: — — — ... — — — — SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in MSB-first or LSB-first order, based on the LM bit in SIFCR, in synchronization with the rising edge of the serial transmit clock (STCK), and output from the serial transmit data STXD pin. The transfer data length is set by the DL bit in SICTR. The transmit mode bit (TRMD) in SIFCR controls the LSB of the transmitted primary data or control data. When the TRMD bit is cleared to 0 and the DL bit is cleared to 0 (8-bit data length), the lower 8 bits in the transmit data register (SITDR) are output. When the DL bit is set to 1 (16-bit data length), all 16 bits in SITDR are output. Setting the TRMD bit to 1 causes the LSB of the primary data to be output as 0. Performing write access to the transmit control data register (SITCDR) in this case, if the DL bit is cleared to 0, causes the lower 8 bits in SITDR to be output, with the LSB as 1, after which the lower 8 bits in SITCDR are output. If the DL bit is set to 1, all 16 bits in SITDR are output, with the LSB as 1, after which all 16 bits in SITCDR are output. When transmit primary data with a value less than or equal to the transmit FIFO watermark bits (TFWM3 to TFWM0) in SIFCR is transferred from SITDR to SITSR, the transmit data register empty flag (TDRE) is set in SISTR. If output of the next primary data begins when the amount of transmit primary data in SITDR is 0, an underrun error occurs, the transmit underrun error flag (TERR) in SISTR is set, and an error interrupt request is sent to the INTC. 15.2.4 Transmit Data Register (SITDR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: W W W ... W W W W SITDR is a 16-bit x 16-stage FIFO register that stores primary transmit data. Data should be written to SITDR when the transmit data register empty flag (TDRE) is set to 1 in SISTR. If data is written to SITDR when TDRE is 0, a SITDR overflow may occur. When transmit primary data Rev. 2.00 Mar 09, 2006 page 641 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) with a value less than or equal to the setting of TFWM3 to TFWM0 in SIFCR is transferred from SITDR to SITSR, TDRE is set in SISTR. If at this point the transmit interrupt enable flag (TIE) is set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and DMAC. If TIE is cleared, this interrupt request is not generated. When the DMAC writes to SITDR data with a value greater than the setting of TFWM3 to TFWM0 in SIFCR, the TDRE flag is cleared automatically. The TDRE flag is set only by hardware. When SITDR is reset, its status is empty. The status of SITDR is also empty when the value of the transmit FIFO data registry reset bit (TFRST) in SITDR is 1. Note: Do not write to SITDR when it is full of primary transmit data (when the value of the transmit data register data count bits 4 to 0 (T4 to T0) in SIFDR is 10000). Data should be written to SITDR in the size specified by the setting of the DL bit in SICTR. Always set the TE bit to 1 before writing to this register. 15.2.5 Serial Control Register (SICTR) Bit: 15 14 13 12 11 10 9 8 — — — — — DMACE TCIE RCIE Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — TM SE DL TIE RIE TE RE Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to H'0000 by a reset. When modifying bit 4, 5, 6,or 10 (DMACE, TM, SE, or DL), TE and RE (bit 1, 0) should be cleared to 0 beforehand. Bits 15 to 11—Reserved: These bits are always read as 0. The write value should always be 0. Bit 10—DMAC Activation Enable (DMACE): Specifies whether the DMAC is activated by interrupts triggered by the RDRF and TDRE bits in SISTR. Set this bit to 1 if SIRCDR and SITCDR are used. This will cause interrupts triggered by the RDRF and TDRE bits in SISTR to be processed by the DMAC and interrupts triggered by the RCD and TCD bits in SISTR to be processed by the CPU. Rev. 2.00 Mar 09, 2006 page 642 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Clear this bit to 0 if SIRCDR and SITCDR are not used, or if all interrupts triggered by the RDRF, TDRE, RCD and TCD bits in SISTR are to be processed by the CPU. The initial value of this bit is 0. Bit 10: DMACE Description 0 DMAC is activated by RDRF and TDRE interrupts 1 DMAC is not activated by RDRF and TDRE interrupts (Initial value) Bit 9—Transmit-Control-Data-Register-Empty Interrupt Enable (TCIE): Enables the transmitcontrol-data-register-empty interrupt. The initial value of this bit is 0. Bit 9: TCIE Description 0 Transmit-control-data-register-empty interrupt disabled 1 Transmit-control-data-register-empty interrupt enabled (Initial value) Bit 8—Receive-Control-Data-Register-Full Interrupt Enable (RCIE): Enables the receive-controldata-register-full interrupt. The initial value of this bit is 0. Bit 8: RCIE Description 0 Receive-control-data-register-full interrupt disabled 1 Receive-control-data-register-full interrupt enabled (Initial value) Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Bit 6—Transfer Mode Control (TM): Specifies whether the transmission synchronization signal is to be input from an external source or generated internally by the chip. When this flag is cleared, the transmission synchronization signal is STS pin input. When this flag is set, the transmission synchronization signal is generated by the chip, and is output to an external device from the STS pin. This bit does not affect reception. Bit 6: TM Description 0 External signal input from STS pin is used as transmission start indication (Initial value) 1 Internal signal output from STS pin is used as transmission start indication Note: If the transmit mode bit (TRMD) in SIFCR is set to 1, this bit must be cleared to 0. If TM is set to 1 and SE is set to 1 (interval mode), output of the sync signal stops at the point at which bits T4 to T0 in SIFDR are cleared to 0 (data count of transmit data register is zero). If TE remains set to 1 and data is written to SITDR, output of the sync signal resumes when the value of T4 to T0 in SIFDR becomes H'01 or above. Rev. 2.00 Mar 09, 2006 page 643 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 5—Synchronization Signal Enable (SE): Specifies whether the synchronization signals are to be used for all serial data transfers, or only for the first transfer. When this bit is cleared to 0, the synchronization signals (SRS and STS) are necessary only for the first data transfer, and are not required for subsequent transfers. When this bit is set to 1, the synchronization signals are necessary for all data transfers. Bit 5: SE Description 0 Continuous mode: SRS and STS are used only for the first data transfer (Initial value) 1 Interval mode: SRS and STS are used for all data transfers Note: If TRMD in SIFCR is set to 1, this bit must be cleared to 1. When TM is cleared to 0 and SE is cleared to 0, after data is input SRS/STS once nothing further should be input to SRS/STS between the start and completion of transmission/receiving (transmit FIFO empty/receive FIFO full). Bit 4—Transmit/Receive Data Length Select (DL): Specifies the serial I/O module’s transfer data length. The initial value of this bit is 0, indicating an 8-bit data length. When an 8-bit data length is specified, the lower 8 bits in the receive shift register, receive data register, transmit shift register, transmit data register, receive control data register, and transmit control data register are used. Bit 4: DL Description 0 8-bit transfer data length 1 16-bit transfer data length (Initial value) Bit 3—Transmit Interrupt Enable (TIE): Enables the transmit-data-empty interrupt. The initial value of this bit is 0. Bit 3: TIE Description 0 Transmit interrupt disabled 1 Transmit interrupt enabled (Initial value) Bit 2—Receive Interrupt Enable (RIE): Enables the receive-data-full interrupt. The initial value of this bit is 0. Bit 2: RIE Description 0 Receive interrupt disabled 1 Receive interrupt enabled Rev. 2.00 Mar 09, 2006 page 644 of 906 REJ09B0292-0200 (Initial value) Section 15 Serial I/O with FIFO (SIOF) Bit 1—Enables data transmission. When this flag is cleared, the STXD pin goes to the highimpedance state. When TM is set to 1, the STS pin also goes to the high-impedance state. Bit 1: TE Description 0 Transmission disabled: STxD pin goes to high-impedance state (Initial value) When TM is set to 1, STS pin goes to high-impedance state 1 Transmission enabled Bit 0—Receive Enable (RE): Enables data reception. Bit 0: RE Description 0 Reception disabled 1 Reception enabled 15.2.6 (Initial value) Serial Status Register (SISTR) Bit: 15 14 ... 9 8 ... 4 — — ... TCD RCD ... — Initial value: 0 0 ... 1 0 R/W: R R 0 ... * * ... R/(W) R/(W) ... R 3 2 1 TERR RERR TDRE 0 RDRF 0 0 1 0 * * * R/(W) R/(W) R/(W) R/(W)* Note: * Only 0 should be written, to clear the flag. SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to H'0002 by a reset. When the TFRST bit in SIFCR is set to 1, the TERR and TDRE bits are also initialized. When the RFRST bit in SIFCR is set to 1, the RERR and RDRF bits are also initialized. Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 645 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 9—Transmit Control Data Register Empty (TCD): This flag indicates when SITCDR is empty and can be written to. Bit 9: TCD Description 0 SITCDR transmit data is valid TCD is cleared to 0 in the following cases: 1 SITCDR transmit data is invalid • When 0 is written to TCD after reading TCD = 1 (Initial value) TCD is set to 1 in the following cases: • After data is transferred from SITCDR to SITSR • When the processor is reset Bit 8—Receive Control Data Register Full (RCD): This flag indicates when SIRCDR is in wait status. Bit 8: RCD Description 0 SIRCDR receive data is invalid RCD is cleared to 0 in the following cases: 1 • When 0 is written to RCD after reading RCD = 1 • When the processor is reset (Initial value) SIRCDR transmit data is valid RCD is set to 1 in the following cases: • After control data has been received normally and data has been transferred from SIRSR to SIRCDR Bit 7 to 4—Reserved: This bit is always read as 0. The write value should always be 0. Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit underrun. Bit 3: TERR Description 0 Transmission is in progress, or has ended normally (Initial value) [Clearing conditions] • When 0 is written to the TERR bit after reading TERR = 1 • When the TFRST bit in SIFCR is set to 1 • When the processor enters the reset state 1 A transmit underrun error has occurred • When the amount of primary transmit data in SITDR is 0 and data is transferred from SITDR to SITSR using a transmit operation Rev. 2.00 Mar 09, 2006 page 646 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun. Bit 2: RERR Description 0 Reception is in progress, or has ended normally (Initial value) [Clearing conditions] 1 • When 0 is written to the RERR bit after reading RERR = 1 • When the RFRST bit in SIFCR is set to 1 • When the processor enters the reset state A receive overrun error has occurred RERR is set to 1 in the following cases: • When the amount of primary receive data in SIRDR is 16 and the next primary data receive operation completes Bit 1—Transmit Data Register Empty (TDRE): Flag that indicates that primary data has been transferred from SITDR to SITSR and the amount of data inside SITDR is less than or equal to the setting of TFWM3 to TFWM0 in SIFCR. Bit 1: TDRE Description 0 Indicates that primary send data exceeding the transmit FIFO watermark setting has been written to SITDR TDRE is cleared to 0 in the following cases: 1 • When primary send data exceeding the setting of the transmit FIFO watermark bits has been written to SITDR and 0 is written to TDRE after reading TDRE = 1 • When the DMAC has written primary send data exceeding the setting of the transmit FIFO watermark bits to SITDR Indicates that the amount of primary send data in SITDR is less than or equal to the transmit FIFO watermark setting (Initial value) TDRE is set to 1 in the following cases: • When the amount of primary send data in SITDR is less than or equal to the transmit FIFO watermark setting • When the TFRST bit in SIFCR is set to 1 • When the processor is reset Rev. 2.00 Mar 09, 2006 page 647 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 0—Receive Data Register Full (RDRF): Flag that indicates that SIRDR receive data is waiting. Bit 0: RDRF Description 0 Indicates that the amount of primary receive data in SIRDR is less than the receive FIFO watermark setting (Initial value) RDRF is cleared to 0 in the following cases: 1 • When the received primary data in SIRDR has been read to the point that the amount of remaining data is less than the receive FIFO watermark setting and 0 is written to RDRF after reading RDRF = 1 • When the DMAC has read the received primary data in SIRDR to the point that the amount of remaining data is less than the receive FIFO watermark setting • When the RFRST bit in SIFCR is set to 1 • When the processor is reset Indicates that the amount of primary receive data in SIRDR is greater than or equal to the receive FIFO watermark setting RDRF is set to 1 in the following cases: • 15.2.7 When the received primary data stored in SIRDR is greater than or equal to the receive FIFO watermark setting Receive Control Data Register (SIRCDR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R SIRCDR is a register that stores receive control data. Received data is stored in SIRCDR as receive control data, synchronized with the timing used for transmission of transmit control data from SITCDR. The RCD bit in SISTR is set at the same time as control data is being transferred from SIRSR to SIRCDR. When the RCIE pin in SICTR is set, a receive-control-data-full interrupt request (RDFI) is sent to the INTC. No interrupt request signal is issued if the flag is cleared. SIRCDR is initialized to H'0000 by a reset. If the DL bit is cleared to 0 (data length 8 bits), the received control data is fetched to the lower 8 bits, and the upper 8 bits are cleared to 0. Rev. 2.00 Mar 09, 2006 page 648 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) 15.2.8 Transmit Control Data Register (SITCDR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SITCDR is a register that stores transmit control data. Data should be written to SITCDR when the TCD bit is set to 1 in SISTR (SITCDR transmit data invalid). If data is written to SITCDR when TCD in SISTR is cleared to 0, the previous data will be overwritten. After writing transmit control data to SITCDR, 1 should be read from TCD in SISTR and then 0 written to it. This makes the transmit data in SITCDR valid and causes the transmit control data to be transmitted. After TRMD in SIFCR is set to 1 transmission starts, a read interrupt is issued to SITCDR. STS goes high and primary data bit 0 is transmitted as 1. When STS next goes high the control data stored in SITCDR is transferred to SITSR. If the TCD bit is 0 at this point, and TCD bit is set to 1. After this the control data previously transferred from SITCDR to SITSR is transmitted. If the TRMD bit is cleared to 0, no control data is transmitted even if data is written to SITCDR. If the TCD bit in SISTR is set to 1 and the TCIE bit in SICTR is set to 1, a transmit-control-dataempty interrupt (TDEI0) request is sent to the INTC. If the flag is cleared, this interrupt request is not generated. The TCD bit in SISTR is set only by hardware. SITCDR is initialized to H'0000 by a reset. 15.2.9 FIFO Control Register (SIFCR) Bit: 15 14 13 12 11 10     TRMD LM Initial value: 0 0 0 0 0 0 9 RFR ST 0 8 7 6 5 4 3 2 1 0 TFR RFWM RFWM RFWM RFWM TFWM TFWM TFWM TFWM ST 3 2 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SIFCR is a register used to perform software resets and to make threshold settings for SIRDR and SITDR. Rev. 2.00 Mar 09, 2006 page 649 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) It also contains a bit used to select LSB first or MSB first when transmitting and receiving to match the connected codec, as well as a bit for controlling the LSB for transmitted primary data and control data. SIFCR is initialized to H'0000 by a reset. Note that the TE and RE bits in SICTR must be cleared to 0 before changing the values of bits 11 to 10 and 7 to 0 (TRMD, LM, RFWM3 to RFWM0, TFWM3 to TFWM0). Bit 15 to 12—Reserved: These bits are always read as 0. The write value should always be 0. Bit 11—Transfer Mode (TRMD): Controls the LSB (bit 0) for transmitted primary data and control data. Bit 11: TRMD Description 0 Value stored in SITDR is always transmitted as LSB of primary data (Initial value) 1 LSB of primary data is always transmitted as 0 However, the LSB is 1 when the primary data immediately precedes control data Note: If the TRMD bit is set to 1, in SICTR the TM bit (STS pin input) should be cleared to 0, the SE bit (interval mode) set to 1, and the LM bit (transmit/receive MSB format) cleared to 0. The sync signal output from the connected codec should be input to pins STS and SRS. The serial clock output from the connected codec should be input to pins STCK and SRCK. Bit 10—LSB/MSB First Select (LM): Used to select LSB first or MSB first for transmitting and receiving. Bit 10: LM Description 0 MSB first for transmitting and receiving 1 LSB first for transmitting and receiving (Initial value) Note: This bit must be cleared to 0 if the TRMD bit is set to 1. Bit 9—Receive FIFO Data Register Reset (RFRST): Invalidates the primary receive data in SIRDR and resets it to empty status. Also initializes the RERR and RDRF bits in SISTR. Note that SICTR is not initialized, so receiving continues if the RE bit is set to 1. Bit 9: RFRST Description 0 Reset disabled 1 Reset enabled Note: (Initial value) Reset status persists while this bit is set to 1. Clear this bit to 0 to cancel reset status. Rev. 2.00 Mar 09, 2006 page 650 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 8—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in SITDR and resets it to empty status. Also initializes the TERR and TDRE bits in SISTR. Note that SICTR is not initialized, so transmitting continues if the TE bit is set to 1. Bit 8: TFRST Description 0 Reset disabled 1 Reset enabled (Initial value) Note: Reset status persists while this bit is set to 1. Clear this bit to 0 to cancel reset status. Bit 7 to 4—Receive FIFO Watermark (RFWM3 to RFWM0): These bits are used to make threshold settings, which are used to set the RDRF bit in SISTR. When the amount of primary receive data in SIRDR is equal to or greater than the watermark setting, as shown in the table below, the RDRF bit is set to 1. Bit 7: RFWM3 Bit 6: RFWM2 Bit 5: RFWM1 Bit 4: RFWM0 Watermark setting 0 0 0 0 1 1 2 0 3 1 4 0 5 1 6 1 0 7 1 8 0 0 9 1 10 0 11 1 12 0 13 1 14 0 15 1 16 1 1 1 0 0 1 1 0 1 (Initial value) Rev. 2.00 Mar 09, 2006 page 651 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Bit 3 to 0— Transmit FIFO Watermark (TFWM3 to TFWM0): These bits are used to make threshold settings, which are used to set the TDRE bit in SISTR. When the amount of primary send data in SITDR is less than or equal to the watermark setting, as shown in the table below, the TDRE bit is set to 1. Bit 3: TFWM3 Bit 2: TFWM2 Bit 1: TFWM1 Bit 0: TFWM0 Watermark setting 0 0 0 0 0 1 1 0 2 1 3 0 0 4 1 5 1 0 6 1 7 0 8 1 9 0 10 1 11 0 12 1 13 0 14 1 15 1 1 1 0 0 1 1 0 1 Rev. 2.00 Mar 09, 2006 page 652 of 906 REJ09B0292-0200 (Initial value) Section 15 Serial I/O with FIFO (SIOF) 15.2.10 FIFO Data Count Register (SIFDR) Bit: 15  14  13  12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R4 R3 R2 R1 R0 7 6 5 4 3 2 1 0    T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 R R R R R R R R SIFDR is a register that indicates the amount of primary data stored in SIRDR and SITDR. The upper 8 bits indicate the amount of primary receive data stored in SIRDR, and the lower 8 bits indicate the amount of primary transmit data stored in SITDR. SIFDR is initialized to H'0000 by a reset. Also, it can be initialized to H'0000 by setting bits RFRST and TFRST of SIFCR to 1. Bit 15 to 13—Reserved: These bits are always read as 0. Bit 12 to 8—Receive Data Register Data Count Bits 4 to 0 (R4 to R0): These bits indicate the amount of primary receive data stored in SIRDR. When the value of bits R4 to R0 is H'00 there is no primary receive data stored in SIRDR, and when the value is H'10 SIRDR is full. In addition to the initialized status mentioned above, bits R4 to R0 can be cleared to H'00 by reading all the primary receive data from SIRDR. Bit 7 to 5—Reserved: These bits are always read as 0. Bit 4 to 0—Transmit Data Register Data Count Bits 4 to 0 (T4 to T0): These bits indicate the amount of untransmitted primary data stored in SITDR. When the value of bits T4 to T0 is H'00 there is no primary transmit data waiting to be transmitted, and when the value is H'10 SITDR is full. In addition to the initialized status mentioned above, bits T4 to T0 can be cleared to H'00 by transmitting all the primary transmit data. Rev. 2.00 Mar 09, 2006 page 653 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) 15.3 Operation 15.3.1 Input when TRMD = 0 in SIFCR Figure 15.2 shows interval transfer mode (SE set to 1 in SICTR) with MSB first (LM cleared to 0 in SIFCR). Figure 15.3 shows continuous transfer mode (SE cleared to 0 in SICTR) with MSB first (LM cleared to 0 in SIFCR). Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received RDRF Synchronous internal clock SIRDR SIRSR A[7:0] A[7] Undefined A[7:6] A[7:1] A[7:0] B[7] SRCK SRS SRXD A[7] A[6] A[5] A[0] Invalid Note: DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.2 Reception: Interval Transfer Mode/MSB First Rev. 2.00 Mar 09, 2006 page 654 of 906 REJ09B0292-0200 B[7] B[6] Section 15 Serial I/O with FIFO (SIOF) Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received RDRF Synchronous internal clock SIRDR SIRSR A[7:0] A[7] Undefined A[7:6] A[7:1] A[7:0] B[7] B[7:6] B[7:5] SRCK SRS SRXD A[7] A[6] A[5] A[0] B[7] B[6] B[5] B[4] Note: DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.3 Reception: Continuous Transfer Mode/MSB First Rev. 2.00 Mar 09, 2006 page 655 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Figure 15.4 shows interval transfer mode (SE set to 1 in SICTR) with LSB first (LM set to 1 in SIFCR). Figure 15.5 shows continuous transfer mode (SE cleared to 0 in SICTR) with LSB first (LM set to 1 in SIFCR). Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received RDRF Synchronous internal clock SIRDR SIRSR A[7:0] A[0] Undefined A[0:1] A[0:6] A[0:7] B[0] SRCK SRS SRXD A[0] A[1] A[2] A[7] Invalid B[0] B[1] Note: DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.4 Reception: Interval Transfer Mode/LSB First Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received RDRF Synchronous internal clock SIRDR SIRSR A[7:0] A[0] Undefined A[0:1] A[0:6] A[0:7] B[0] B[0:1] B[0:2] SRCK SRS SRXD A[0] A[1] A[2] A[7] B[0] B[1] Note: DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.5 Reception: Continuous Transfer Mode/LSB First Rev. 2.00 Mar 09, 2006 page 656 of 906 REJ09B0292-0200 B[2] B[3] Section 15 Serial I/O with FIFO (SIOF) 15.3.2 Output when TRMD = 0 in SIFCR Figure 15.6 shows interval transfer mode when TM is cleared to 0 in SICTR and with MSB first. Figure 15.7 shows continuous transfer mode when TM is cleared to 0 in SICTR and with MSB first. Figure 15.8 shows interval transfer mode when TM is set to 1 in SICTR and with MSB first. Figure 15.9 shows continuous transfer mode when TM is set to 1 in SICTR and with MSB first. Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[7:0] C[6:0] D[7:0] C[5:0] C[0] E[7:0] D[7:0] D[6:0] STCK STS STXD C[7] C[6] C[5] C[0] D[7] D[6] Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.6 Transmission: Interval Transfer Mode (TM = 0 Mode)/MSB First Rev. 2.00 Mar 09, 2006 page 657 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[7:0] C[6:0] D[7:0] C[5:0] C[0] E[7:0] D[7:0] D[6:0] D[5:0] D[4:0] STCK STS STXD C[7] C[6] C[5] C[0] D[7] D[6] D[5] D[4] Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.7 Transmission: Continuous Transfer Mode (TM = 0 Mode)/MSB First Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[7:0] C[6:0] D[7:0] C[5:0] C[1:0] E[7:0] C[0] D[7:0] D[6:0] D[5:0] STCK STS STXD C[7] C[6] C[5] C[1] C[0] D[7] D[6] Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.8 Transmission: Interval Transfer Mode (TM = 1 Mode)/MSB First Rev. 2.00 Mar 09, 2006 page 658 of 906 REJ09B0292-0200 D[5] Section 15 Serial I/O with FIFO (SIOF) Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[7:0] C[6:0] D[7:0] C[5:0] C[0] E[7:0] D[7:0] D[6:0] D[5:0] D[4:0] STCK STS STXD C[7] C[6] C[5] C[0] D[7] D[6] D[5] D[4] Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode LM = 0: MSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.9 Transmission: Continuous Transfer Mode (TM = 1 Mode)/MSB First Figure 15.10 shows interval transfer mode when TM is cleared to 0 in SICTR and with LSB first. Figure 15.11 shows continuous transfer mode when TM is cleared to 0 in SICTR and with LSB first. Figure 15.12 shows interval transfer mode when TM is set to 1 in SICTR and with LSB first. Figure 15.13 shows continuous transfer mode when TM is set to 1 in SICTR and with LSB first. Rev. 2.00 Mar 09, 2006 page 659 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[0:7] C[1:7] D[7:0] C[2:7] E[7:0] C[7] D[0:7] D[1:7] STCK STS STXD C[0] C[1] C[2] C[7] D[0] D[1] Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.10 Transmission: Interval Transfer Mode (TM = 0 Mode)/LSB First Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[0:7] C[1:7] D[7:0] C[2:7] C[7] E[7:0] D[0:7] D[1:7] D[2:7] D[3:7] STCK STS STXD C[0] C[1] C[2] C[7] D[0] D[1] D[2] D[3] Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer in start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.11 Transmission: Continuous Transfer Mode (TM = 0 Mode)/LSB First Rev. 2.00 Mar 09, 2006 page 660 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[0:7] C[1:7] D[7:0] C[2:7] C[6:7] E[7:0] C[7] D[0:7] D[1:7] D[2:7] STCK STS STXD C[0] C[1] C[2] C[6] C[7] D[0] D[1] D[2] Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.12 Transmission: Interval Transfer Mode (TM = 1 Mode)/LSB First Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR TDRE Synchronous internal clock SITDR C[7:0] SITSR Undefined D[7:0] C[0:7] C[1:7] D[7:0] C[2:7] C[7] E[7:0] D[0:7] D[1:7] D[2:7] D[3:7] STCK STS STXD C[0] C[1] C[2] C[7] D[0] D[1] D[2] D[3] Note: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode LM = 1: LSB first TRMD = 0: LSB of transmitted primary data is value in SITDR Figure 15.13 Transmission: Continuous Transfer Mode (TM = 1 Mode)/LSB First 15.3.3 Output when TRMD = 1 in SIFCR Figure 15.14 shows output timing when TM is set to 1 in SIFTR. Rev. 2.00 Mar 09, 2006 page 661 of 906 REJ09B0292-0200 Rev. 2.00 Mar 09, 2006 page 662 of 906 REJ09B0292-0200 Undefined Figure 15.14 Transmission: TRMD = 1 Mode Undefined D[7:0] D[6] Z[7:0] E[7:0] D[6:0] D[7] D[7:0] A[6] A[0] A[7:1] Invalid A[7:0] A[7:0] B[7] B[7] B[6] D[0] D[0] E[7:0] Z[7:0] E[7:0] E[7] E[6] E[6:0] F[7:0] Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR A[7] A[7] Note: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode LM = 0: MSB first TRMD = 1: LSB of transmitted primary data is 0 STXD STS STCK SITSR SITCDR SITDR TDRE Synchronous internal clock SRXD SRS SRCK SIRSR SIRCDR SIRDR RDRF Synchronous internal clock E[0] E[0] B[0] B[7:1] Z[7:0] F[7:0] Invalid B[7:0] Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received Z[7:0] B[7:0] Z[7] Z[6:0] C[7] C[7] Z[6] C[6] C[7:1] Z[0] Z[0] Z[7:0] F[7:0] C[0] C[7:0] Invalid C[7:0] B[7:0] F[7:0] Section 15 Serial I/O with FIFO (SIOF) Section 15 Serial I/O with FIFO (SIOF) 15.4 SIOF Interrupt Sources and DMAC Each SIOF channel has four interrupt sources: the receive-overrun-error interrupt (RERI0) request, transmit-underrun-error interrupt (TERI0) request, receive-data-full interrupt/receive-control-dataregister-full interrupt (RDFI0) request, and transmit-data-empty interrupt/transmit-control-dataregister-empty interrupt (TDEI0) request. Table 15.3 shows the interrupt sources and their relative priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE, RCIE, TIE, and TCIE bits, respectively, in SICTR. The RERI0 and TERI0 interrupts cannot be disabled. An RDFI0 interrupt request is generated when the RDRF bit is set to 1 or the RCD bit is set to 1 in SISTR. The DMACE bit should be cleared to 0 in SICTR to have interrupts triggered by both the RDRF bit and the RCD bit processed by the CPU. In this case the CPU should process interrupts after reading SISTR and determining which bit triggered them. Set the DMACE bit to 1 in SICTR to have interrupts triggered by the RDRF bit processed by the DMAC and interrupts triggered by the RCD bit processed by the CPU. In addition, the priority of interrupts from SIOF should be set to a high level in order to activate the interrupt controller (INTC). This will cause interrupts triggered by the RDRF bit to be sent to the DMAC and interrupts triggered by the RCD bit to be sent to the INTC. The data in SIRDR is read and if the amount of primary data is less than the setting of bits RFWM3 to RFWM0 in SIFCR, RDRF is automatically cleared to 0. Interrupts triggered by the RCD bit cannot be processed by the DMAC. An TDEI0 interrupt request is generated when the TDRE bit is set to 1 or the TCD bit is set to 1 in SISTR. The DMACE bit should be cleared to 0 in SICTR to have interrupts triggered by both the TDRE bit and the TCD bit processed by the CPU. In this case the CPU should process interrupts after reading SISTR and determining which bit triggered them. Set the DMACE bit to 1 in SICTR to have interrupts triggered by the TDRE bit processed by the DMAC and interrupts triggered by the TCD bit processed by the CPU. In addition, the priority of interrupts from SIOF should be set to a high level in order to activate the INTC. This will cause interrupts triggered by the TDRE bit to be sent to the DMAC and interrupts triggered by the TCD bit to be sent to the INTC. The DMAC writes data to SIRDR and if the amount of primary data is equal to or greater than the setting of bits TFWM3 to TFWM0 in SIFCR, TDRE is automatically cleared to 0. Interrupts triggered by the TCD bit cannot be processed by the DMAC. When the RERR bit is set to 1 in SISTR, an RERI0 interrupt request is generated. When the TERR bit is set to 1 in SISTR, a TERI0 interrupt request is generated. Rev. 2.00 Mar 09, 2006 page 663 of 906 REJ09B0292-0200 Section 15 Serial I/O with FIFO (SIOF) Channel interrupt priority levels are set by means of the IRPE register, as described in section 5, Interrupt Controller (INTC). Table 15.3 SIOF Interrupt Sources Interrupt Source Description DMAC Activation Priority RERI0 Receive overrun error (RERR) Not possible High TERI0 Transmit underrun error (TERR) ↑ RDFI0 Receive data register full (RDRF)/ Receive Control Data Register Full (RCD) Not possible Possible* TDEI0 Transmit data register empty (TDRE)/ Transmit Control Data Register Empty (TCD) Possible* ↓ Low Note: * The interrupt sources that can activate the DMAC are receive data full (RDRF) and transmit data empty (TDRE). It is not possible for receive control data full (RCD) or transmit control data empty (TCD) to activate the DMAC. The DMAC should be used to process RDRF and TDRE interrupts when using SIRCDR and SITCDR, and the DMACE bit must be set to 1 in SICTR when using the CPU to process RCD and TCD interrupts. The DMACE bit should be cleared to 0 in SICTR if neither SIRCDR nor SITCDR is used and both RDRF and TDRE interrupts as well as RCD and TCD interrupts are to be processed by the CPU. Rev. 2.00 Mar 09, 2006 page 664 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) Section 16 Serial I/O (SIO) 16.1 Overview A two-channel simple synchronous serial I/O is provided on-chip. The serial I/O functions mainly as an interface between the chip and a codec or modem analog front-end. 16.1.1 Features The serial I/O has the following features: • Full-duplex operation Independent transmit/receive registers and independent transmit/receive clocks • Double-buffered transmit/receive ports Continuous data transmission/reception possible • Interval transfer mode and continuous transfer mode • Memory-mapped receive register, transmit register, control register, and status register With the exception of SIRSR and SITSR, these registers are memory-mapped and can be accessed by a MOV instruction. • Choice of 8- or 16-bit data length • Data transfer communication by means of polling or interrupts Data transfer can be monitored by polling the receive data register full flag (RDRF) and transmit data register empty flag (TDRE) in the serial status register. Interrupt requests can be generated during data transfer by setting the receive interrupt request flag and transmit interrupt request flag. • MSB-first transfer between SIO and data I/O Figure 16.1 shows a block diagram of the serial I/O. Rev. 2.00 Mar 09, 2006 page 665 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) Peripheral bus 16 SISTR SIRDR SITDR SICTR Bit counter I/O control unit SIRSR MSB SITSR MSB LSB LSB Serial I/O module (SIO) SRxD SIRDR: SIRSR: SISTR: SICTR: SITDR: SITSR: SRCK SRS STS STCK Receive data register Receive shift register Serial status register Serial control register Transmit data register Transmit shift register Figure 16.1 SIO Block Diagram Rev. 2.00 Mar 09, 2006 page 666 of 906 REJ09B0292-0200 STxD Section 16 Serial I/O (SIO) Table 16.1 shows the functions of the external pins. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 16.1 Serial I/O (SIO) External Pins Channel Name Pin I/O Function 1 Serial receive data input pin SRxD1 Input Serial data input port 1 Serial receive clock input pin SRCK1 Input Serial receive clock port 1 Serial reception synchronization input pin SRS1 Input Serial reception synchronization input port 1 Serial transmit data output pin STxD1 Output Serial data output port 1 Serial transmit clock input pin STCK1 Input Serial transmit clock port 1 Serial transmission synchronization input/output pin STS1 I/O Serial transmission synchronization input/output port 1 Serial receive data input pin SRxD2 Input Serial data input port 2 Serial receive clock input pin SRCK2 Input Serial receive clock port 2 Serial reception synchronization input pin SRS2 Input Serial reception synchronization input port 2 Serial transmit data output pin STxD2 Output Serial data output port 2 Serial transmit clock input pin STCK2 Input Serial transmit clock port 2 Serial transmission synchronization input/output pin STS2 I/O Serial transmission synchronization input/output port 2 2 Note: In a reset, all pins are initialized to the high-impedance state. Rev. 2.00 Mar 09, 2006 page 667 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.2 Register Configuration Table 16.2 shows the SIO’s registers. As the channels are independent, the channel numbers are omitted from the signal names in the rest of this section. Table 16.2 Register Configuration Channel Register Abbreviation R/W Initial Value Address Access Size (Bits) 1 Receive shift register 1 SIRSR1 — — — — Receive data register 1 SIRDR1 R H'0000 H'FFFFFC10 8, 16, 32 Transmit shift register 1 SITSR1 — — — Transmit data register 1 SITDR1 R/W H'0000 H'FFFFFC12 8, 16, 32 Serial control register 1 SICTR1 R/W H'0000 H'FFFFFC14 8, 16, 32 Serial status register 1 SISTR1 R/(W)* H'0002 H'FFFFFC16 8, 16, 32 Receive shift register 2 SIRSR2 — — — Receive data register 2 SIRDR2 R H'0000 H'FFFFFC20 8, 16, 32 Transmit shift register 2 SITSR2 — — — Transmit data register 2 SITDR2 R/W H'0000 H'FFFFFC22 8, 16, 32 Serial control register 2 SICTR2 R/W H'0000 H'FFFFFC24 8, 16, 32 Serial status register 2 SISTR2 R/(W)* H'0002 H'FFFFFC26 8, 16, 32 2 Note: * Only 0 should be written, to clear flags (after reading 1 from the flag). Rev. 2.00 Mar 09, 2006 page 668 of 906 REJ09B0292-0200 — — — Section 16 Serial I/O (SIO) 16.2.1 Receive Shift Register (SIRSR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: — — — ... — — — — R/W: — — — ... — — — — SIRSR is a 16-bit register used to receive serial data. The data is fetched in MSB first from the SRxD pin in synchronization with the fall of the serial receive clock (SRCK), and is shifted into SIRSR. The data length is set by the transmit/receive data length select bit (DL) in the corresponding serial control register (SICTR). When data transfer to SIRSR is completed, the data contents are automatically transferred to the receive data register (SIRDR), and the receive data register full flag (RDRF) is set in the serial status register (SISTR). If the next data word input operation ends before the RDRF flag is cleared, an overrun error occurs, the receive overrun error flag (RERR) is set in SISTR, and an overrun error signal is sent to the interrupt controller (INTC). The data in SIRSR overwrites the data in SIRDR. 16.2.2 Receive Data Register (SIRDR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R SIRDR is a 16-bit register that stores serial receive data. When data is transferred from SIRSR to SIRDR, the receive data register full flag (RDRF) is set in the serial status register (SISTR). If the receive interrupt enable flag (RIE) is set in SICTR, a receive-data-full interrupt (RDFI) request is sent to the interrupt controller (INTC) and the DMA controller (DMAC). When the flag is cleared, this interrupt request signal is not generated. When SIRDR is read by the DMAC, the RDRF flag is cleared automatically. SIRDR is initialized to H'0000 by a reset. Rev. 2.00 Mar 09, 2006 page 669 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.2.3 Transmit Shift Register (SITSR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: — — — ... — — — — R/W: — — — ... — — — — SITSR is a 16-bit register used to transmit serial data. The contents of this register are shifted in MSB-first order in synchronization with the rising edge of the serial transmit clock (STCK), and output from the STxD pin. The transfer data length is set by the transmit/receive data length select bit (DL) in the serial control register (SICTR). When the DL bit is cleared to 0 (8-bit data length), the lower 8 bits of SITDR are output. When the serial transmission synchronization signal (STS) goes high, or the last data transmission ends without the synchronization enable (SE) bit being set in SICTR, the contents of the transmit data register (SITDR) are transferred to SITSR, and if TDRE is 0, TDRE is then set. If output of the next data begins before TDRE is cleared, an overrun error occurs, the transmit overrun error flag (TERR) is set in SISTR, and a transmit overrun error interrupt request is sent to the INTC. 16.2.4 Transmit Data Register (SITDR) Bit: 15 14 13 ... 3 2 1 0 ... Initial value: R/W: 0 0 0 ... 0 0 0 0 R/W R/W R/W ... R/W R/W R/W R/W SITDR is a 16-bit register that stores serial transmit data. Data should be written to SITDR when the transmit data register empty flag (TDRE) is set to 1 in SISTR. If data is written to SITDR when TDRE is 0, the previous data will be overwritten. When STS goes high or data output from transmit shift register SITSR ends with the SE bit cleared to 0 in SICTR, the data in SITDR is automatically transferred to SITSR, and if TDRE is 0, TDRE is then set. If the transmit interrupt enable flag (TIE) is set, a transmit-data-empty interrupt (TDEI) request is sent to the INTC and DMAC. When TIE is cleared, this interrupt request is not generated. When the DMAC writes to SITDR, the TDRE flag is cleared automatically. The TDRE flag is set only by hardware. SITDR is initialized to H'0000 by a reset. Rev. 2.00 Mar 09, 2006 page 670 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.2.5 Serial Control Register (SICTR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — TM SE DL TIE RIE TE RE Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W SICTR is a 16-bit register used to set parameters for serial port control. SICTR is initialized to H'0000 by a reset. When modifying bit 4, 5, or 6 (TM, SE, or DL), TE and RE should be cleared to 0 beforehand. Bits 15 to 7—Reserved: These bits are always read as 0. The write value should always be 0. Bit 6—Transfer Mode Control (TM): Specifies whether the transmission synchronization signal is to be input from an external source or generated internally by the chip. When this flag is cleared, the transmission synchronization signal is STS pin input. When this flag is set, the transmission synchronization signal is generated by the chip, and is output to an external device from the STS pin. This bit does not affect reception. Bit 6: TM Description 0 External signal input from STS pin is used as transmission start indication (Initial value) Internal signal output from STS pin is used as transmission start indication 1 Bit 5—Synchronization Signal Enable (SE): Specifies whether the synchronization signals are to be used for all serial data transfers, or only for the first transfer. When this bit is cleared to 0, the synchronization signals (SRS and STS) are necessary only for the first data transfer, and are not required for subsequent transfers. When this bit is set to 1, the synchronization signals are necessary for all data transfers. Bit 5: SE Description 0 Continuous mode: SRS and STS are used only for the first data transfer (Initial value) Interval mode: SRS and STS are used for all data transfers 1 Rev. 2.00 Mar 09, 2006 page 671 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) Bit 4—Transmit/Receive Data Length Select (DL): Specifies the serial I/O module’s transfer data length. The initial value of this bit is 0, indicating an 8-bit data length. When an 8-bit data length is specified, the lower 8 bits of each I/O register are used. Bit 4: DL Description 0 8-bit transfer data length 1 16-bit transfer data length (Initial value) Bit 3—Transmit Interrupt Enable (TIE): Enables the transmit-data-empty interrupt. The initial value of this bit is 0. Bit 3: TIE Description 0 Transmit interrupt disabled 1 Transmit interrupt enabled (Initial value) Bit 2—Receive Interrupt Enable (RIE): Enables the receive-data-full interrupt. The initial value of this bit is 0. Bit 2: RIE Description 0 Receive interrupt disabled 1 Receive interrupt enabled (Initial value) Bit 1—Transmit Enable (TE): Enables data transmission. When this flag is cleared, the STxD, STCK, and STS pins go to the high-impedance state. Bit 1: TE Description 0 Transmission disabled: STxD, STCK, and STS pins go to high-impedance state (Initial value) 1 Transmission enabled Bit 0—Receive Enable (RE): Enables data reception. When this flag is cleared, the SRxD, SRCK, and SRS pins go to the high-impedance state. Bit 0: RE Description 0 Reception disabled: SRxD, SRCK, and SRS pins go to high-impedance state (Initial value) 1 Reception enabled Rev. 2.00 Mar 09, 2006 page 672 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.2.6 Serial Status Register (SISTR) Bit: 15 14 ... 4 3 2 1 0 — — ... — TERR RERR TDRE RDRF Initial value: 0 0 ... 0 0 0 1 0 R/W: R R ... R R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 should be written, to clear the flag. SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to H'0002 by a reset. Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0. Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit underrun. Bit 3: TERR Description 0 Transmission is in progress, or has ended normally (Initial value) [Clearing conditions] 1 • When 0 is written to the TERR bit after reading TERR = 1 • When the processor enters the reset state A transmit underrun error has occurred TERR is set to 1 if data transmission is started while TDRE = 1 Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun. Bit 2: RERR Description 0 Reception is in progress, or has ended normally (Initial value) [Clearing conditions] 1 • When 0 is written to the RERR bit after reading RERR = 1 • When the processor enters the reset state A receive overrun error has occurred RERR is set to 1 if data reception ends while RDRF = 1 Rev. 2.00 Mar 09, 2006 page 673 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) Bit 1—Transmit Data Register Empty (TDRE): Flag that indicates that the SITDR register is empty and the next data can be written. Bit 1: TDRE Description 0 SITDR transmit data is valid [Clearing conditions] 1 • When 0 is written to the TDRE bit after reading TDRE = 1 • When the DMAC writes data to SITDR SITDR transmit data is invalid (Initial value) TDRE is set to 1 in the following cases: • When data is transferred from SITDR to SITSR • When the TE bit is cleared to 0 in the serial control register (SICTR) • When the processor enters the reset state Bit 0—Receive Data Register Full (RDRF): Flag that indicates that SIRDR receive data is waiting. Bit 0: RDRF Description 0 SIRDR receive data is invalid (Initial value) [Clearing conditions] 1 • When the DMAC reads data from SIRDR • When 1 is read from RDRF and 0 is written • When the RE bit is cleared to 0 in the serial control register (SICTR) • When the processor enters the reset state SIRDR receive data is valid RDRF is set to 1 when serial data reception ends normally and the data is transferred from SIRSR to SIRDR Rev. 2.00 Mar 09, 2006 page 674 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.3 Operation 16.3.1 Input Figure 16.2 shows interval transfer mode (SE set to 1 in SICTR), and figure 16.3 shows continuous transfer mode (SE cleared to 0 in SICTR). RDRF synchronous internal clock SIRDR SIRSR A[7:0] Undefined A[7] A[7:6] A[7:1] A[7:0] B[7] SRCK SRS SRxD A[7] A[6] A[5] A[1] A[0] Invalid B[7] Notes: DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode Figure 16.2 Reception: Interval Transfer Mode RDRF synchronous internal clock SIRDR SIRSR A[7:0] Undefined A[7] A[7:6] A[7:1] A[7:0] B[7] B[7:6] B[7:5] SRCK SRS SRxD A[7] A[6] A[5] A[1] A[0] B[7] B[6] B[5] Notes: DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode Figure 16.3 Reception: Continuous Transfer Mode Rev. 2.00 Mar 09, 2006 page 675 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) 16.3.2 Output Figure 16.4 shows interval transfer mode (SE set to 1 in SICTR) when TM is cleared to 0 in SICTR. Figure 16.5 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is cleared to 0 in SICTR. Figure 16.6 shows interval transfer mode (SE set to 1 in SICTR) when TM is set to 1 in SICTR. Figure 16.7 shows continuous transfer mode (SE cleared to 0 in SICTR) when TM is set to 1 in SICTR. TDRE synchronous internal clock SITDR SITSR Data C Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] STCK STS STxD C[7] C[6] C[5] C[1] C[0] Invalid Notes: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode Figure 16.4 Transmission: Interval Transfer Mode (TM = 0 Mode) Rev. 2.00 Mar 09, 2006 page 676 of 906 REJ09B0292-0200 D[7] Section 16 Serial I/O (SIO) TDRE synchronous internal clock SITDR SITSR Data C Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0] STCK STS C[7] STxD C[6] C[5] C[1] C[0] D[7] D[6] D[5] Notes: TM = 0: STS is input DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode Figure 16.5 Transmission: Continuous Transfer Mode (TM = 0 Mode) TDRE synchronous internal clock SITDR SITSR Data C Undefined C[7:0] Data D C[6:0] C[5:0] C[0] D[7:0] D[6:0] STCK STS STxD C[7] C[6] C[5] C[1] C[0] Invalid D[7] Notes: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 1: Synchronous transfer in start signal mode Figure 16.6 Transmission: Interval Transfer Mode (TM = 1 Mode) Rev. 2.00 Mar 09, 2006 page 677 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) TDRE synchronous internal clock SITDR SITSR Data C Undefined C[7:0] C[6:0] C[5:0] C[0] D[7:0] D[6:0] D[5:0] D[4:0] STCK STS STxD C[7] C[6] C[5] C[1] C[0] D[7] D[6] Notes: TM = 1: STS is output DL = 0: 8-bit data transfer SE = 0: Asynchronous transfer, no start signal mode Figure 16.7 Transmission: Continuous Transfer Mode (TM = 1 Mode) Rev. 2.00 Mar 09, 2006 page 678 of 906 REJ09B0292-0200 D[5] Section 16 Serial I/O (SIO) 16.4 SIO Interrupt Sources and DMAC Each SIO channel has four interrupt sources: the receive-overrun-error interrupt (RERI) request, transmit-underrun-error interrupt (TERI) request, receive-data-full interrupt (RDFI) request, and transmit-data-empty interrupt (TDEI) request. Table 16.3 shows the interrupt sources and their relative priorities. The RDFI and TDEI interrupts are enabled by the RIE and TIE bits, respectively, in SICTR. The RERI and TERI interrupts cannot be disabled. An RDFI interrupt request is generated when the RDRF bit is set to 1 in SISTR. RDFI can activate the DMA controller (DMAC) to read the data in SIRDR. RDRF is cleared to 0 automatically when the DMAC reads data from SIRDR. A TDEI interrupt request is generated when the TDRE bit is set to 1 in SISTR. TDEI can activate the DMAC to write the next data to SITDR. TDRE is cleared to 0 automatically when the DMAC writes data to SITDR. When TDEI and RDFI interrupt requests are handled by the DMAC, and not by the interrupt controller, a low priority level should be given to interrupts from the SIO to prevent the interrupt controller from operating. When the RERR bit is set to 1 in SISTR, an RERI interrupt request is generated. When the TERR bit is set to 1 in SISTR, a TERI interrupt request is generated. Channel interrupt priority levels are set by means of the IRPE register, as described in section 5, Interrupt Controller (INTC). Table 16.3 SIO Interrupt Sources Interrupt Source Description DMAC Activation Priority RERI Receive overrun error (RERR) Not possible High TERI Transmit underrun error (TERR) Not possible ↑ RDFI Receive data register full (RDRF) Possible ↓ TDEI Transmit data register empty (TDRE) Possible Low Rev. 2.00 Mar 09, 2006 page 679 of 906 REJ09B0292-0200 Section 16 Serial I/O (SIO) Rev. 2.00 Mar 09, 2006 page 680 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Section 17 16-Bit Timer Pulse Unit (TPU) 17.1 Overview An on-chip 16-bit timer pulse unit (TPU) is provided that comprises three 16-bit timer channels. 17.1.1 Features The TPU has the following features: • Maximum 8-pulse input/output • A total of eight timer general registers (TGRs) are provided (four for channel 0 and two each for channels 1, and 2).  Each register can be set independently as an output compare/input capture register.  TGRC and TGRD for channel 0 can be used as buffer registers • Choice of seven or eight counter input clocks for each channel • The following operations can be set for each channel:  Waveform output by compare match: Selection of 0, 1, or toggle output  Input capture function: Choice of rising edge, falling edge, or both edge detection  Counter clear operation: Counter clearing possible by compare match or input capture  Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation  PWM mode: Any PWM output duty can be set maximum of 7-phase PWM output possible by combination with synchronous operation • Buffer operation settable for channel 0  Input capture register double-buffering possible  Automatic rewriting of output compare register possible • Phase counting mode settable independently for each of channels 1, and 2  Two-phase encoder pulse up/down-count possible • Fast access via internal 16-bit bus  Fast access is possible via a 16-bit bus interface • 13 interrupt sources  For channel 0 four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently Rev. 2.00 Mar 09, 2006 page 681 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU)  For channels 1, and 2, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently • Automatic transfer of register data  Block transfer, 1-word data transfer, and 1-byte data transfer possible by direct memory access controller (DMAC) activation Table 17.1 lists the functions of the TPU. Table 17.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Count clock Pφ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC General registers TGR0A TGR0B TGR1A TGR1B TGR2A TGR2B General registers/ buffer registers TGR0C TGR0D — — I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture Compare 0 output match 1 output output Toggle output O O O O O O O O Input capture function O O O Synchronous operation O O O PWM mode O O O Phase counting mode — O O Buffer operation O — — Notes: O : Possible — : Not possible Rev. 2.00 Mar 09, 2006 page 682 of 906 REJ09B0292-0200 O Section 17 16-Bit Timer Pulse Unit (TPU) Item Channel 0 DMAC activation TGR compare match or — input capture Interrupt sources Channel 1 Channel 2 — 5 sources 4 sources 4 sources • • • • • • • Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow • • • Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow • • • Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow Note: — : Not possible Rev. 2.00 Mar 09, 2006 page 683 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.2 Block Diagram Bus interface Timer Control Register Timer Mode Register Timer I/O Control Register Timer Interrupt Enable Register Timer Status Register Timer Counter Timer General Register Timer Start Register Timer Synchro Register Figure 17.1 TPU Block Diagram Rev. 2.00 Mar 09, 2006 page 684 of 906 REJ09B0292-0200 TGRD TGRB TGRB TGRB Internal data bus TGRC TCNT TGRA TCNT TGRA TCNT TGRA Module data bus TSR TIER TSR TIER TSR TIER TIOR TIOR TIORH TIORL Common Control logic TMDR TCR TMDR Channel 1 Channel 2 TCR: TMDR: TIOR: TIER: TSR: TCNT: TGR: TSTR: TSYR: TCR Channel 2: Channel 0 Channel 1: I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Control logic for channels 0 to 2 Channel 0: TMDR External clock: TCLKA TCLKB TCLKC TCLKD TCR Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 TSTR TSYR Figure 17.1 shows a block diagram of the TPU. Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.3 Pin Configuration Table 17.2 shows the pin configuration of the TPU. Table 17.2 Pin Configuration Channel Name Abbreviation I/O Function All Clock input A TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) Clock input C TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) Clock input D TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input) Input capture/output compare match A0 TIOCA0 I/O TGR0A input capture input/output compare output/PWM output pin Input capture/output compare match B0 TIOCB0 I/O TGR0B input capture input/output compare output/PWM output pin Input capture/output compare match C0 TIOCC0 I/O TGR0C input capture input/output compare output/PWM output pin Input capture/output compare match D0 TIOCD0 I/O TGR0D input capture input/output compare output/PWM output pin Input capture/output compare match A1 TIOCA1 I/O TGR1A input capture input/output compare output/PWM output pin Input capture/output compare match B1 TIOCB1 I/O TGR1B input capture input/output compare output/PWM output pin Input capture/output compare match A2 TIOCA2 I/O TGR2A input capture input/output compare output/PWM output pin Input capture/output compare match B2 TIOCB2 I/O TGR2B input capture input/output compare output/PWM output pin 0 1 2 Rev. 2.00 Mar 09, 2006 page 685 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.1.4 Register Configuration Table 17.3 shows the register configuration of the TPU. Table 17.3 Register Configuration Channel Name 0 1 Abbreviation R/W Initial Value Address Access size (Bits) Timer control register 0 TCR0 R/W H'00 H'FFFFFC50 8,16 Timer mode register 0 TMDR0 R/W H'C0 H'FFFFFC51 8,16 Timer I/O control register 0H TIOR0H R/W H'00 H'FFFFFC52 8,16 Timer I/O control register 0L TIOR0L R/W H'00 H'FFFFFC53 8,16 Timer interrupt enable TIER0 register 0 R/W H'40 H'FFFFFC54 8,16 Timer status register 0 TSR0 R/(W)* H'C0 H'FFFFFC55 8,16 Timer counter 0 TCNT0 R/W H'0000 H'FFFFFC56 16 Timer general register TGR0A 0A R/W H'FFFF H'FFFFFC58 16 Timer general register TGR0B 0B R/W H'FFFF H'FFFFFC5A 16 Timer general register TGR0C 0C R/W H'FFFF H'FFFFFC5C 16 Timer general register TGR0D 0D R/W H'FFFF H'FFFFFC5E 16 Timer control register 1 TCR1 R/W H'00 H'FFFFFC60 8,16 Timer mode register 1 TMDR1 R/W H'C0 H'FFFFFC61 8,16 Timer I/O control register 1 TIOR1 R/W H'00 H'FFFFFC62 8,16 Timer interrupt enable TIER1 register 1 R/W H'40 H'FFFFFC64 8,16 Timer status register 1 TSR1 R/(W)* H'C0 H'FFFFFC65 8,16 Timer counter 1 TCNT1 R/W H'0000 H'FFFFFC66 16 Timer general register TGR1A 1A R/W H'FFFF H'FFFFFC68 16 Timer general register TGR1B 1B R/W H'FFFF H'FFFFFC6A 16 Rev. 2.00 Mar 09, 2006 page 686 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Channel Name 2 All Abbreviation R/W Initial Value Address Access size (Bits) Timer control register 2 TCR2 R/W H'00 H'FFFFFC70 8, 16 Timer mode register 2 TMDR2 R/W H'C0 H'FFFFFC71 8, 16 Timer I/O control register 2 TIOR2 R/W H'00 H'FFFFFC72 8, 16 Timer interrupt enable register 2 TIER2 R/W H'40 H'FFFFFC74 8, 16 Timer status register 2 TSR2 R/(W)* H'C0 H'FFFFFC75 8, 16 Timer counter 2 TCNT2 R/W H'0000 H'FFFFFC76 16 Timer general register 2A TGR2A R/W H'FFFF H'FFFFFC78 16 Timer general register 2B TGR2B R/W H'FFFF H'FFFFFC7A 16 Timer start register TSTR R/W H'00 H'FFFFFC40 8, 16 Timer synchro register TSYR R/W H'00 H'FFFFFC41 8, 16 Note: * Only 0 can be written, to clear the flags. 17.2 Register Descriptions 17.2.1 Timer Control Register (TCR) Channel 0: TCR0 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 1: TCR1 Channel 2: TCR2 Bit: 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Rev. 2.00 Mar 09, 2006 page 687 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) The TCR registers are 8-bit registers that control the TCNT channels. The TPU has three TCR registers, one for each of channels 0 to 2. The TCR registers are initialized to H'00 by a reset. TCNT operation should be stopped when making TCR settings. Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Channel Bit 7: CCLR2 Bit 6: CCLR1 Bit 5: CCLR0 Description 0 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input 2 capture* 1 TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* 1 1 0 1 (Initial value) Channel Bit 6: Bit 7: 3 Reserved* CCLR1 Bit 5: CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 1 (Initial value) Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1and 2. It is always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 688 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When a both-edges count is selected, a clock divided by two from the input clock can be selected. (e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting mode is used on channels 1, and 2, this setting is ignored and the phase counting mode setting has priority. Bit 4: CKEG1 Bit 3: CKEG0 Description 0 0 Count at rising edge 1 Count at falling edge — Count at both edges 1 (Initial value) Note: Internal clock edge selection is valid when the input clock is Pφ/4 or slower. If Pφ/1 is selected for the input clock, this setting is ignored and a rising-edge count is selected. Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 17.4 shows the clock sources that can be set for each channel. Table 17.4 TPU Clock Sources Internal Clock External Clock Channel Pφ φ/1 Pφ φ/4 Pφ φ/16 Pφ φ/64 Pφ φ/256 Pφ φ/1024 TCLKA TCLKB TCLKC TCLKD 0 O O O O O O 1 O O O O O O 2 O O O O O O O O O O O Notes: O: Setting Blank: No setting Channel Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description 0 0 0 0 Internal clock: counts on Pφ/1 1 Internal clock: counts on Pφ/4 0 Internal clock: counts on Pφ/16 1 Internal clock: counts on Pφ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 (Initial value) Rev. 2.00 Mar 09, 2006 page 689 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Channel Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description 1 0 0 0 Internal clock: counts on Pφ/1 1 Internal clock: counts on Pφ/4 1 0 Internal clock: counts on Pφ/16 1 Internal clock: counts on Pφ/64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on Pφ/256 1 Setting prohibited 1 1 (Initial value) Note: This setting is ignored when channel 1 is in phase counting mode. Channel Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description 2 0 0 0 Internal clock: counts on Pφ/1 1 Internal clock: counts on Pφ/4 1 0 Internal clock: counts on Pφ/16 1 Internal clock: counts on Pφ/64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on Pφ/1024 1 1 (Initial value) Note: This setting is ignored when channel 2 is in phase counting mode. 17.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Bit: 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value: 1 1 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Channel 1: TMDR1 Channel 2: TMDR2 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 1 R 1 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Rev. 2.00 Mar 09, 2006 page 690 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset. TCNT operation should be stopped when making TMDR settings. Bits 7 and 6—Reserved: These bits are always read as 1. The write value should always be 1. Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5: BFB Description 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation (Initial value) Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4: BFA Description 0 TGRA operates normally 1 TGRA and TGRC used together for buffer operation (Initial value) Rev. 2.00 Mar 09, 2006 page 691 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3: 1 MD3* Bit 2: 2 MD2* Bit 1: MD1 Bit 0: MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 * — 1 1 1 * * (Initial value) *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. 17.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 0: TIOR0L Bit: Initial value: R/W: Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 2.00 Mar 09, 2006 page 692 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized to H'00 by a reset. Note that TIOR is affected by the TMDR setting. The initial output specified by TIOR becomes valid when the counter is halted (i.e. when the CST bit is cleared to 0 in TSTR). In PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. TIOR0H Channel Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 0 1 1 0 1 1 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 TGR0B is Output disabled output Initial output is 0 compare output register 1 * * * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is Capture input Input capture at rising edge input source is Input capture at falling edge capture TIOCB0 pin Input capture at both edges register Setting prohibited *: Don’t care Rev. 2.00 Mar 09, 2006 page 693 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR0L Channel Bit 7: Bit 6: Bit 5: Bit 4: IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 0 1 0 1 1 1 TGR0D Output disabled isoutput Initial output is 0 compare output 1 register* 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 1 * * * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D is Capture input Input capture at rising edge input source is Input capture at falling edge capture TIOCD0 pin 1 Input capture at both edges register* Setting prohibited *: Don’t care Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar 09, 2006 page 694 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR1 Channel Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 1 0 0 0 0 1 1 0 1 1 0 1 TGR1B is Output disabled output Initial output is 0 compare output register 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is Capture input Input capture at rising edge input source is Input capture at falling edge capture TIOCB1 pin Input capture at both edges register Setting prohibited *: Don’t care TIOR2 Channel Bit 7: Bit 6: Bit 5: Bit 4: IOB3 IOB2 IOB1 IOB0 Description 2 0 0 0 0 1 1 0 1 1 0 1 TGR2B is Output disabled output Initial output is 0 compare output register 0 Output disabled 1 Initial output is 1 output 0 1 1 * 0 0 1 1 * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR2B is Capture input input source is capture TIOCB2 pin register Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care Rev. 2.00 Mar 09, 2006 page 695 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. TIOR0H Channel Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 0 1 0 1 1 1 TGR0A is Output disabled output Initial output is 0 compare output register 0 0 Output disabled 1 1 0 Initial output is 1 output 1 1 0 0 0 1 1 1 * * * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0A is Capture input Input capture at rising edge input source is Input capture at falling edge capture TIOCA0 pin Input capture at both edges register Setting prohibited *: Don’t care Rev. 2.00 Mar 09, 2006 page 696 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR0L Channel Bit 3: Bit 2: Bit 1: Bit 0: IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 0 1 1 0 TGR0C is Output disabled output Initial output is 0 compare output 1 register* 1 1 0 1 Output disabled 1 Initial output is 1 output 1 1 0 0 0 1 1 1 * * * 0 output at compare match 1 output at compare match Toggle output at compare match 0 0 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match TGR0C is Capture input input source is capture TIOCC0 pin 1 register* Input capture at rising edge Input capture at falling edge Input capture at both edges Setting prohibited *: Don’t care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00 Mar 09, 2006 page 697 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TIOR1 Channel Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 1 0 0 0 0 1 1 0 1 1 0 1 TGR1A is Output disabled output Initial output is 0 compare output register 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is Capture input Input capture at rising edge input source is Input capture at falling edge capture TIOCA1 pin Input capture at both edges register Setting prohibited *: Don’t care TIOR2 Channel Bit 3: Bit 2: Bit 1: Bit 0: IOA3 IOA2 IOA1 IOA0 Description 2 0 0 0 0 1 1 0 1 1 0 1 TGR2A is Output disabled output Initial output is 0 compare output register 0 Output disabled 1 Initial output is 1 output 0 1 1 * 0 0 1 1 * (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR2A is Capture input input source is capture TIOCA2 pin register Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care Rev. 2.00 Mar 09, 2006 page 698 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Bit: 7 6 5 4 3 2 1 0 — — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 1 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — TCIEU TCIEV — — TGIEB TGIEA Initial value: 0 1 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W R/W Channel 1: TIER1 Channel 2: TIER2 Bit: The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset. Bit 7—Reserved: This bit is always read as 0. The write value should always be 0. Bit 6—Reserved: This bit is always read as 1. The write value should always be 1. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5: TCIEU Description 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4: TCIEV Description 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled (Initial value) Rev. 2.00 Mar 09, 2006 page 699 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1, and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3: TGIED Description 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled (Initial value) Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2: TGIEC Description 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1: TGIEB Description 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled (Initial value) Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0: TGIEA Description 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled Rev. 2.00 Mar 09, 2006 page 700 of 906 REJ09B0292-0200 (Initial value) Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.5 Timer Status Register (TSR) Channel 0: TSR0 Bit: 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value: 1 1 0 0 0 0 0 0 R/W: R R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flags. Channel 1: TSR1 Channel 2: TSR2 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA 1 1 0 0 0 0 0 0 R R/(W)* R/(W)* R R/(W)* R/(W)* R R Note: * Only 0 can be written, to clear the flags. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, and 2. In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7: TCFD Description 0 TCNT counts down 1 TCNT counts up (Initial value) Bit 6—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 701 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5: TCFU Description 0 [Clearing condition] (Initial value) When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4: TCFV Description 0 [Clearing condition] (Initial value) When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3: TGFD Description 0 [Clearing conditions] 1 (Initial value) • When DMAC is activated by TGID interrupt while DRCR setting in DMAC is TGI0D • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Rev. 2.00 Mar 09, 2006 page 702 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2: TGFC Description 0 [Clearing conditions] 1 (Initial value) • When DMAC is activated by TGIC interrupt while DRCR setting in DMAC is TGI0C • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1: TGFB Description 0 [Clearing conditions] 1 (Initial value) • When DMAC is activated by TGIB interrupt while DRCR setting in DMAC is TGI0B • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Rev. 2.00 Mar 09, 2006 page 703 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0: TGFA Description 0 [Clearing conditions] 1 17.2.6 (Initial value) • When DMAC is activated by TGIA interrupt while DRCR setting in DMAC is TGI0A • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode. In other cases they function as up-counters. The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Rev. 2.00 Mar 09, 2006 page 704 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.2.7 Timer General Register (TGR) Bit: 15 14 13 12 11 10 9 8 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 8 TGR registers, four for channel 0 and two each for channels 1, and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA–TGRC and TGRB–TGRD. 17.2.8 Timer Start Register (TSTR) Bit: 7 6 5 4 3 2 1 0 — — — — — CST2 CST1 CST0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TSTR is initialized to H'00 by a reset. TCNT counter operation should be stopped when setting the operating mode in TMDR or the TCNT count clock in TCR. Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 705 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Bits 2 to 0—Counter Start 2 to 0 (CST2 to CST0): These bits select operation or stoppage for TCNT. Bit n: CSTn Description 0 TCNTn count operation is stopped 1 TCNTn performs count operation (Initial value) Note: n = 2 to 0 If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops, but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 17.2.9 Timer Synchronous Register (TSYR) Bit: 7 6 5 4 3 2 1 0 — — — — — SYNC2 SYNC1 SYNC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset. Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Bits 2 to 0—Timer Synchro 2 to 0 (SYNC2 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels* , and 2 synchronous clearing through counter clearing on another channel* are possible. 1 Bit n: SYNCn Description 0 TCNTn operates independently (Initial value) TCNT presetting/clearing is unrelated to other channels TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 1 Notes: n = 2 to 0 1. To set synchronous operation, the SYNC bits for two channels at least must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev. 2.00 Mar 09, 2006 page 706 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.3 Interface to Bus Master 17.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 17.2. Internal data bus H Bus master L Module data bus Bus interface TCNTH TCNTL Figure 17.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] 17.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Rev. 2.00 Mar 09, 2006 page 707 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of 8-bit register access operation are shown in figures 17.3, 17.4, and 17.5. Internal data bus H Bus master L Module data bus Bus interface TCR Figure 17.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 17.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 17.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] Rev. 2.00 Mar 09, 2006 page 708 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.4 Operation 17.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: The TCNT counter for a channel designated for synchronous operation by means of TSYR performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the counter clear bits in TCR for channels designated for synchronous operation. Buffer Operation • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. • When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, and 2. When phase counting mode is set, the corresponding TCLK pin functions as the clock input, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. Rev. 2.00 Mar 09, 2006 page 709 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 17.6 shows an example of the count operation setting procedure. 1 Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. 2 For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. 3 Designate the TGR selected in [2] as an output compare register by means of TIOR. 4 Set the periodic counter cycle in the TGR selected in (2). 5 Set the CST bit in TSTR to 1 to start the count operation. Operation selection Select counter clock 1 Periodic counter Free-running counter Select counter clearing source 2 Select output compare register 3 Set period 4 Start count operation 5 Start count operation 5 Figure 17.6 Example of Counter Operation Setting Procedure Rev. 2.00 Mar 09, 2006 page 710 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 17.7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 17.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 2.00 Mar 09, 2006 page 711 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Figure 17.8 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 17.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 17.9 shows an example of the setting procedure for waveform output by compare match 1 Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. Output selection Select waveform output mode 1 2 Set the timing for compare match generation in TGR. Set output timing 2 Start count operation 3 3 Set the CST bit in TSTR to 1 to start the count operation. Figure 17.9 Example of Setting Procedure for Waveform Output by Compare Match Rev. 2.00 Mar 09, 2006 page 712 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Examples of waveform output operation Figure 17.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 17.10 Example of 0 Output/1 Output Operation Figure 17.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 17.11 Example of Toggle Output Operation Rev. 2.00 Mar 09, 2006 page 713 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. • Example of input capture operation setting procedure Figure 17.12 shows an example of the input capture operation setting procedure. 1 Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. Input selection Select input capture input 1 Start count 2 2 Set the CST bit in TSTR to 1 to start the count operation. Figure 17.12 Example of Input Capture Operation Setting Procedure Rev. 2.00 Mar 09, 2006 page 714 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Example of input capture operation Figure 17.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 17.13 Example of Input Capture Operation Rev. 2.00 Mar 09, 2006 page 715 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 17.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation 1 Synchronous presetting Set TCNT Synchronous clearing 2 Clearing source generation channel? No Yes Select counter clearing source 3 Set synchronous counter clearing 4 Start count 5 Start count 5 1 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. 2 When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. 3 Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. 4 Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. 5 Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 17.14 Example of Synchronous Operation Setting Procedure Rev. 2.00 Mar 09, 2006 page 716 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 17.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 17.4.5, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A Time H'0000 TIOC0A TIOC1A TIOC2A Figure 17.15 Example of Synchronous Operation Rev. 2.00 Mar 09, 2006 page 717 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.4 Buffer Operation Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 17.5 shows the register combinations used in buffer operation. Table 17.5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 17.16. Compare match signal Buffer register Timer general register Comparator Figure 17.16 Compare Match Buffer Operation Rev. 2.00 Mar 09, 2006 page 718 of 906 REJ09B0292-0200 TCNT Section 17 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 17.17. Input capture signal Timer general register Buffer register TCNT Figure 17.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 17.18 shows an example of the buffer operation setting procedure. Buffer operation 1 Designate TGR as an input capture register or output compare register by means of TIOR. Select TGR function 1 Set buffer operation 2 Start count 3 2 Designate TGR for buffer operation with bits BFA and BFB in TMDR. 3 Set the CST bit in TSTR to 1 to start the count operation. Figure 17.18 Example of Buffer Operation Setting Procedure Rev. 2.00 Mar 09, 2006 page 719 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation • When TGR is an output compare register Figure 17.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 17.4.5, PWM Modes. TCNT value TGR0B H'0520 H'0450 H'0200 TGR0A Time H'0000 TGR0C H'0200 H'0450 H'0520 Transfer TGR0A H'0200 H'0450 TIOCA Figure 17.19 Example of Buffer Operation (1) Rev. 2.00 Mar 09, 2006 page 720 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register Figure 17.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 TGRA TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 17.20 Example of Buffer Operation (2) 17.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. Rev. 2.00 Mar 09, 2006 page 721 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • PWM mode 1 PWM output is generated by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3–IOA0 and IOC3–IOC0 in TIOR is performed in response to compare match A and C, and the output specified by bits IOB3–IOB0 and IOD3–IOD0 in TIOR in response to compare match B and D, from pins TIOCA and TIOCC. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified by TIOR is performed in response to a compare match. Also, when the counter is cleared by a synchronization register compare match, pin output values are the initial values set in TIOR. If the set values of the period and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 17.6. Table 17.6 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 0 TGR0A TIOCA0 TIOCA0 TGR0B TGR0C TIOCB0 TIOCC0 TGR0D 1 TGR1A 2 TGR2A TIOCD0 TIOCA1 TGR1B TGR2B TIOCC0 TIOCA1 TIOCB1 TIOCA2 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 2.00 Mar 09, 2006 page 722 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 17.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock Select counter clearing source Select waveform output level Set TGR 1 1 Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. 2 2 Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. 3 3 Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. 4 4 Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. 5 Select the PWM mode with bits MD3 to MD0 in TMDR. Set PWM mode 5 Start count 6 6 Set the CST bit in TSTR to 1 to start the count operation. Figure 17.21 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 17.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 output is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. Rev. 2.00 Mar 09, 2006 page 723 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 17.22 Example of PWM Mode Operation (1) Figure 17.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers, to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 17.23 Example of PWM Mode Operation (2) Rev. 2.00 Mar 09, 2006 page 724 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Figure 17.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 TIOCA 100% duty 0% duty Figure 17.24 Example of PWM Mode Operation (3) Rev. 2.00 Mar 09, 2006 page 725 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 17.7 shows the correspondence between external clock pins and channels. Table 17.7 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 17.25 shows an example of the phase counting mode setting procedure. 1 Select phase counting mode with bits MD3 to MD0 in TMDR. Phase counting mode Select phase counting mode 1 Start count 2 2 Set the CST bit in TSTR to 1 to start the count operation. Figure 17.25 Example of Phase Counting Mode Setting Procedure Rev. 2.00 Mar 09, 2006 page 726 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 17.26 shows an example of phase counting mode 1 operation, and table 17.8 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 17.26 Example of Phase Counting Mode 1 Operation Table 17.8 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level Notes: : Rising edge : Falling edge Rev. 2.00 Mar 09, 2006 page 727 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 2 Figure 17.27 shows an example of phase counting mode 2 operation, and table 17.9 summarizes the TCNT up/down-count conditions. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Up-count Down-count Time Figure 17.27 Example of Phase Counting Mode 2 Operation Table 17.9 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count High level Don’t care Low level Don’t care Notes: High level Don’t care Low level Down-count : Rising edge : Falling edge Rev. 2.00 Mar 09, 2006 page 728 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 3 Figure 17.28 shows an example of phase counting mode 3 operation, and table 17.10 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 17.28 Example of Phase Counting Mode 3 Operation Table 17.10 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count High level Down-count Low level Don’t care Notes: High level Don’t care Low level Don’t care : Rising edge : Falling edge Rev. 2.00 Mar 09, 2006 page 729 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 4 Figure 17.29 shows an example of phase counting mode 4 operation, and table 17.11 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 17.29 Example of Phase Counting Mode 4 Operation Table 17.11 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level Don’t care High level High level Down-count Low level High level Low level Notes: : Rising edge : Falling edge Rev. 2.00 Mar 09, 2006 page 730 of 906 REJ09B0292-0200 Don’t care Section 17 16-Bit Timer Pulse Unit (TPU) 17.5 Interrupts 17.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller (INTC). Table 17.12 lists the TPU interrupt sources. Table 17.12 TPU Interrupts Channel Interrupt Source Description DMAC Activation 0 TGI0A TGR0A input capture/compare match Possible High TGI0B TGR0B input capture/compare match Possible ↑ TGI0C TGR0C input capture/compare match Possible TGI0D TGR0D input capture/compare match Possible TCI0V TCNT0 overflow Not possible TGI1A TGR1A input capture/compare match Not possible TGI1B TGR1B input capture/compare match Not possible TCI1V TCNT1 overflow Not possible TCI1U TCNT1 underflow Not possible TGI2A TGR2A input capture/compare match Not possible TGI2B TGR2B input capture/compare match Not possible TCI2V TCNT2 overflow Not possible ↓ TCI2U TCNT2 underflow Not possible Low 1 2 Priority Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 2.00 Mar 09, 2006 page 731 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 8 input capture/compare match interrupts, four for channel 0, and two each for channels 1, and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a particular channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 17.5.2 DMAC Activation The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 11, Direct Memory Access Controller (DMAC). A total of four TPU input capture/compare match interrupts can be used as DMAC activation sources for channel 0. Rev. 2.00 Mar 09, 2006 page 732 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.6 Operation Timing 17.6.1 Input/Output Timing TCNT Count Timing: Figure 17.30 shows TCNT count timing in internal clock operation, and figure 17.31 shows TCNT count timing in external clock operation. Pφ Internal clock Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 17.30 Count Timing in Internal Clock Operation Pφ External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 17.31 Count Timing in External Clock Operation Rev. 2.00 Mar 09, 2006 page 733 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 17.32 shows output compare output timing. Pφ TCNT input clock N TCNT N+1 N TGR Compare match signal TIOC pin Figure 17.32 Output Compare Output Timing Input Capture Signal Timing: Figure 17.33 shows input capture signal timing. Pφ Input capture input Input capture signal TCNT N N+1 N+2 N TGR Figure 17.33 Input Capture Input Signal Timing Rev. 2.00 Mar 09, 2006 page 734 of 906 REJ09B0292-0200 N+2 Section 17 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 17.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 17.35 shows the timing when counter clearing by input capture occurrence is specified. Pφ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 17.34 Counter Clear Timing (Compare Match) Pφ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 17.35 Counter Clear Timing (Input Capture) Rev. 2.00 Mar 09, 2006 page 735 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 17.36 and 17.37 show the timing in buffer operation. Pφ n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 17.36 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 17.37 Buffer Operation Timing (Input Capture) Rev. 2.00 Mar 09, 2006 page 736 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 17.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. Pφ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 17.38 TGI Interrupt Timing (Compare Match) Rev. 2.00 Mar 09, 2006 page 737 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 17.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. Pφ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 17.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 17.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 17.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. Pφ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 17.40 TCIV Interrupt Setting Timing Rev. 2.00 Mar 09, 2006 page 738 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Pφ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 17.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 17.42 shows the timing for status flag clearing by the CPU, and figure 17.43 shows the timing for status flag clearing by the DMAC. TSR write cycle T1 T2 Pφ Address TSR address Write signal Status flag Interrupt request signal Figure 17.42 Timing for Status Flag Clearing by CPU Rev. 2.00 Mar 09, 2006 page 739 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) DMAC read cycle T1 DMAC write cycle T1 T2 T2 Pφ Source address Address Destination address Status flag Interrupt request signal Figure 17.43 Timing for Status Flag Clearing by DMAC Activation 17.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 17.44 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifference Overlap ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 17.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 2.00 Mar 09, 2006 page 740 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where Pφ (N + 1) f : Counter frequency Pφ : Peripheral module clock N : TGR set value Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 17.45 shows the timing in this case. TCNT write cycle T1 T2 Pφ TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 17.45 Contention between TCNT Write and Clear Operations Rev. 2.00 Mar 09, 2006 page 741 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 17.46 shows the timing in this case. TCNT write cycle T1 T2 Pφ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 17.46 Contention between TCNT Write and Increment Operations Rev. 2.00 Mar 09, 2006 page 742 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 17.47 shows the timing in this case. TGR write cycle T1 T2 Pφ TGR address Address Write signal Compare match signal Inhibited TCNT N N+1 TGR N M TGR write data Figure 17.47 Contention between TGR Write and Compare Match Rev. 2.00 Mar 09, 2006 page 743 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 17.48 shows the timing in this case. TGR write cycle T1 T2 Pφ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M M Figure 17.48 Contention between Buffer Register Write and Compare Match Rev. 2.00 Mar 09, 2006 page 744 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data before input capture transfer. Figure 17.49 shows the timing in this case. TGR read cycle T1 T2 Pφ TGR address Address Read signal Input capture signal TGR Internal data bus N M N Figure 17.49 Contention between TGR Read and Input Capture Rev. 2.00 Mar 09, 2006 page 745 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 17.50 shows the timing in this case. TGR write cycle T1 T2 Pφ TGR address Address Write signal Input capture signal TCNT M M TGR Figure 17.50 Contention between TGR Write and Input Capture Rev. 2.00 Mar 09, 2006 page 746 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 17.51 shows the timing in this case. Buffer register write cycle T1 T2 Pφ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 17.51 Contention between Buffer Register Write and Input Capture Rev. 2.00 Mar 09, 2006 page 747 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 17.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Pφ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Disabled TCFV Figure 17.52 Contention between Overflow and Counter Clearing Rev. 2.00 Mar 09, 2006 page 748 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 17.53 shows the operation timing in the case of contention between a TCNT write and overflow. TCNT write cycle T1 T2 Pφ TCNT address Address Write signal TCNT TCFV flag TCNT write data H'FFFF M Disabled Figure 17.53 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the Chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 2.00 Mar 09, 2006 page 749 of 906 REJ09B0292-0200 Section 17 16-Bit Timer Pulse Unit (TPU) 17.8 Usage Notes 17.8.1 Clearing Flags in TSR0 to TSR2 When bits TCFV, TGFD, TGFC, TGFB, and TGFA in TSR0, and bits TCFU, TCFV, TGFB, and TGFA in TSR1 and TSR2, are cleared, it may happen that the interrupt request in the internal logic cannot be cleared although the flag is cleared. In this case, if interrupt acceptance is enabled, another interrupt will be generated. Either of the following measures should therefore be taken when clearing flags in TSR0 to TSR2. 1. Execute clearing while the TPU timer is counting up. 2. If clearing when the TPU timer is stopped, write 0 to the flag again after executing clearing. 17.8.2 DMA Transfer by TPU0 When DMA transfer is performed by means of TPU channel 0 compare match or input capture, internal logic interrupt requests (transfer requests) may not be cleared correctly. Therefore, it may not be possible to execute DMA transfer when a subsequent transfer request is generated by TPU channel 0 compare match or input capture. Either of the following measures should therefore be taken when performing DMA transfer by means of TPU channel 0 compare match or input capture. 1. Do not set on-chip RAM as the DMA transfer source or destination. 2. When on-chip RAM has not been set as the DMA transfer source or destination, execute the transfer while the TPU channel 0 timer is counting up. Rev. 2.00 Mar 09, 2006 page 750 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Section 18 User Debug Interface (H-UDI) 18.1 Overview The user debug interface (H-UDI) provides data transfer and interrupt request functions. The HUDI performs serial transfer by means of external signal control. 18.1.1 Features The H-UDI has the following features conforming to the IEEE 1149.1 standard. • Five test signals (TCK, TDI, TDO, TMS, and TRST) • TAP controller • Instruction register • Data register • Bypass register • Boundary scan register The H-UDI has seven instructions. • Bypass mode Test mode conforming to IEEE 1149.1 • EXTEST mode Test mode corresponding to IEEE1149.1. • SAMPLE/PRELOAD mode Test mode corresponding to IEEE1149.1. • CLAMP mode Test mode corresponding to IEEE1149.1. • HIGHZ mode Test mode corresponding to IEEE1149.1. • IDCODE mode Test mode corresponding to IEEE1149.1. • H-UDI interrupt H-UDI interrupt request to INTC This chip does not support test modes other than bypass mode. Rev. 2.00 Mar 09, 2006 page 751 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.1.2 H-UDI Block Diagram Figure 18.1 shows a block diagram of the H-UDI. TCK TMS TAP controller Internal bus controller H-UDI interrupt signal TRST TDI Decoder SDDRH 16 SDDRL SDIDR TDO Mux SDIR: SDSR: SDDRH: SDDRL: SDBPR: SDBSR: Instruction register Status register Data register H Data register L Bypass register Boundary scan register TCK: TMS: TRST: TDI: TDO: SDIDR: Test clock Test mode select Test reset Test data input Test data output ID code register Figure 18.1 H-UDI Block Diagram Rev. 2.00 Mar 09, 2006 page 752 of 906 REJ09B0292-0200 Peripheral bus SDSR Shift register SDBSR SDBPR SDIR Section 18 User Debug Interface (H-UDI) 18.1.3 Pin Configuration Table 18.1 shows the H-UDI pin configuration. Table 18.1 Pin Configuration Pin Name Abbreviation I/O Function Test clock TCK Input Test clock input Test mode select TMS Input Test mode select input signal Test data input TDI Input Serial data input Test data output TDO Output Serial data output Test reset TRST Input Test reset input signal 18.1.4 Register Configuration Table 18.2 shows the H-UDI registers. Table 18.2 Register Configuration Register Abbreviation 1 R/W* 2 Initial Value* Address Access Size (Bits) Instruction register SDIR R H'E000 H'FFFFFCB0 8/16/32 Status register SDSR R/W H'0701 H'FFFFFCB2 8/16/32 Data register H SDDRH R/W Undefined H'FFFFFCB4 8/16/32 Data register L SDDRL R/W Undefined H'FFFFFCB6 8/16/32 Bypass register SDBPR — — — — Boundary scan register SDBSR — — — — ID code register SDIDR — H'0005200F — — Notes: 1. Indicates whether the register can be read/written to by the CPU. 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual) or in standby mode. Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit register to which TDI and TDO are connected in bypass mode. The boundary scan register (SDBSR) is a 330-bit register, and is connected to TDI and TDO in the SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via Rev. 2.00 Mar 09, 2006 page 753 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed from the CPU. Table 18.3 shows the kinds of serial transfer possible with each register. Table 18.3 H-UDI Register Serial Transfer Register Serial Input Serial Output SDIR Possible Possible SDSR Impossible Possible SDDRH Possible Possible SDDRL Possible Possible SDBPR Possible Possible SDBSR Possible Possible SDIDR Impossible Possible 18.2 External Signals 18.2.1 Test Clock (TCK) The test clock pin (TCK) provides an independent clock supply to the H-UDI. As the clock input to TCK is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should be input (for details, see section 22, Electrical Characteristics). If no clock is input, TCK is fixed at 1 by internal pull-up. 18.2.2 Test Mode Select (TMS) The test mode select pin (TMS) is sampled on the rise of TCK. TMS controls the internal state of the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up. 18.2.3 Test Data Input (TDI) The test data input pin (TDI) performs serial input of instructions and data for H-UDI registers. TDI is sampled on the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up. Rev. 2.00 Mar 09, 2006 page 754 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.2.4 Test Data Output (TDO) The test data output pin (TDO) performs serial output of instructions and data from H-UDI registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to the high-impedance state. 18.2.5 Test Reset (TRST TRST) TRST The test reset pin (TRST) initializes the H-UDI asynchronously. If no signal is input, TRST is fixed at 1 by internal pull-up. 18.3 Register Descriptions 18.3.1 Instruction Register (SDIR) Bit: 15 14 13 12 11 10 9 8 TS3 TS2 TS1 TS0 — — — — Initial value: 1 1 1 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI instructions can be transferred to SDIR by serial input from TDI. SDIR can be initialized by the TRST signal, but is not initialized by a reset or in standby mode. SDIR defines 4 valid bits for instruction. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR. Operation is not guaranteed if a reserved instruction is set in this register. Bits 15 to 12—Test Set Bits (TS3–TS0): Table 18.4 shows the instruction configuration. Rev. 2.00 Mar 09, 2006 page 755 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Table 18.4 Instruction Configuration Bit 15: TS3 Bit 14: TS2 Bit 13: TS1 Bit 12: TS0 Description 0 0 0 0 EXTEST mode 1 Reserved 0 CLAMP mode 1 HIGHZ mode 0 SAMPLE/PRELOAD mode 1 Reserved 1 0 Reserved 1 Reserved 0 0 Reserved 1 Reserved 0 H-UDI interrupt 1 Reserved 0 0 Reserved 1 Reserved 1 0 IDCODE mode 1 BYPASS mode 1 1 1 0 0 1 1 (Initial value) Bits 11 to 0—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 756 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.3.2 Status Register (SDSR) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — SDTRF Initial value: 0 0 0 0 0 0 0 1 R/W: R R R R R R R R/W The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. Output from TDO is possible for SDSR, but serial data cannot be written to SDSR via TDI. The SDTRF bit is output by means of a 1-bit shift. In the case of a 2-bit shift, the SDTRF bit is first output, followed by a reserved bit. SDSR is initialized by TRST signal input, but is not initialized by a reset or in standby mode. Bits 15 to 1—Reserved: Bits 15 to 11 and 7 to 1 are always read as 0, and the write value should always be 0. Bits 10 to 8 are always read as 1, and the write value should always be 1. Bit 0—Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reset by the TRST signal , but is not initialized by a reset or in standby mode. Bit 0: SDTRF Description 0 Serial transfer to SDDR has ended, and SDDR can be accessed 1 Serial transfer to SDDR in progress (Initial value) Rev. 2.00 Mar 09, 2006 page 757 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.3.3 Data Register (SDDR) The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each of which has the following configuration. Bit: 15 14 13 12 11 10 9 8 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is connected to TDO and TDI for serial data transfer to and from an external device. 32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the last 32 bits will be stored in SDDR. Serial data is input starting from the MSB of SDDR (bit 15 of SDDRH), and output starting from the LSB (bit 0 of SDDRL). This register is not initialized by a reset, in standby mode, or by the TRST signal. 18.3.4 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit shift register. In bypass mode, SDBPR is connected to TDI and TDO, and the chip is excluded from the board test when a boundary scan test is conducted. SDBPR cannot be read or written to by the CPU. 18.3.5 Boundary scan register (SDBSR) The boundary scan register (SDBSR), a shift register that controls the I/O terminals of this LSI, is provided on the PAD. Using the EXTEST mode or the SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. For SDBSR, read/write by the CPU cannot be performed. Rev. 2.00 Mar 09, 2006 page 758 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Table 18.5 shows the relationship between the terminals of the LSI and the boundary scan register. Table 18.5 Correspondence between Pins and Boundary Scan Register Bits Pin No. Pin Name Input/Output Bit No. D0 Input 329 Output 328 Output enable 327 Input 326 Output 325 Output enable 324 Input 323 Output 322 Output enable 321 Input 320 Output 319 Output enable 318 Input 317 Output 316 Output enable 315 Input 314 from TDI 34 36 37 38 39 40 41 43 44 46 D1 D2 D3 D4 D5 D6 D7 D8 D9 Output 313 Output enable 312 Input 311 Output 310 Output enable 309 Input 308 Output 307 Output enable 306 Input 305 Output 304 Output enable 303 Input 302 Output 301 Output enable 300 Rev. 2.00 Mar 09, 2006 page 759 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 47 D10 Input 299 Output 298 48 49 51 53 54 55 56 57 59 D11 D12 D13 D14 D15 D16 D17 D18 D19 Output enable 297 Input 296 Output 295 Output enable 294 Input 293 Output 292 Output enable 291 Input 290 Output 289 Output enable 288 Input 287 Output 286 Output enable 285 Input 284 Output 283 Output enable 282 Input 281 Output 280 Output enable 279 Input 278 Output 277 Output enable 276 Input 275 Output 274 Output enable 273 Input 272 Output 271 Output enable 270 Rev. 2.00 Mar 09, 2006 page 760 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 62 D20 Input 269 Output 268 63 64 65 68 70 71 72 73 74 D21 D22 D23 D24 D25 D26 D27 D28 D29 Output enable 267 Input 266 Output 265 Output enable 264 Input 263 Output 262 Output enable 261 Input 260 Output 259 Output enable 258 Input 257 Output 256 Output enable 255 Input 254 Output 253 Output enable 252 Input 251 Output 250 Output enable 249 Input 248 Output 247 Output enable 246 Input 245 Output 244 Output enable 243 Input 242 Output 241 Output enable 240 Rev. 2.00 Mar 09, 2006 page 761 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 75 D30 Input 239 Output 238 77 D31 80 A0 82 A1 83 A2 84 A3 85 A4 86 87 88 A5 A6 A7 90 A8 92 A9 93 94 A10 A11 Output enable 237 Input 236 Output 235 Output enable 234 Output 233 Output enable 232 Output 231 Output enable 230 Output 229 Output enable 228 Output 227 Output enable 226 Output 225 Output enable 224 Output 223 Output enable 222 Output 221 Output enable 220 Output 219 Output enable 218 Output 217 Output enable 216 Output 215 Output enable 214 Output 213 Output enable 212 Output 211 Output enable 210 Rev. 2.00 Mar 09, 2006 page 762 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 95 A12 Output 209 Output enable 208 96 97 A13 A14 98 A15 100 A16 102 A17 103 A18 104 A19 105 106 107 A20 A21 A22 108 A23 111 A24 Output 207 Output enable 206 Output 205 Output enable 204 Output 203 Output enable 202 Output 201 Output enable 200 Output 199 Output enable 198 Output 197 Output enable 196 Output 195 Output enable 194 Output 193 Output enable 192 Output 191 Output enable 190 Output 189 Output enable 188 Output 187 Output enable 186 Output 185 Output enable 184 115 WAIT Input 183 117 RAS Output 182 Output enable 181 118 CAS Output 180 Output enable 179 Rev. 2.00 Mar 09, 2006 page 763 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 119 DQMUU/WE3 Output 178 Output enable 177 120 121 DQMUL/WE2 DQMLU/WE1 122 DQMLL/WE0 123 CAS3 124 CAS2 125 CAS1 126 CAS0 127 128 129 CKE RD REFOUT 131 BS 133 RD/WR 134 135 CS0 CS1 Output 176 Output enable 175 Output 174 Output enable 173 Output 172 Output enable 171 Output 170 Output enable 169 Output 168 Output enable 167 Output 166 Output enable 165 Output 164 Output enable 163 Output 162 Output enable 161 Output 160 Output enable 159 Output 158 Output enable 157 Output 156 Output enable 155 Output 154 Output enable 153 Output 152 Output enable 151 Output 150 Output enable 149 Rev. 2.00 Mar 09, 2006 page 764 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 136 CS2 Output 148 Output enable 147 137 138 CS3 CS4 139 BUSHIZ 140 BH Output 146 Output enable 145 Output 144 Output enable 143 Input 142 Output 141 Output enable 140 141 DREQ1 Input 139 142 DREQ0 Input 138 143 DACK1 Output 137 Output enable 136 144 DACK0 Output 135 Output enable 134 145 BRLS Input 133 148 BGR Output 132 Output enable 131 151 152 153 154 PB15 PB14 PB13 PB12 Input 130 Output 129 Output enable 128 Input 127 Output 126 Output enable 125 Input 124 Output 123 Output enable 122 Input 121 Output 120 Output enable 119 Rev. 2.00 Mar 09, 2006 page 765 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 156 PB11 Input 118 Output 117 Output enable 116 Input 115 Output 114 Output enable 113 Input 112 158 159 160 161 162 163 164 165 166 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 Output 111 Output enable 110 Input 109 Output 108 Output enable 107 Input 106 Output 105 Output enable 104 Input 103 Output 102 Output enable 101 Input 100 Output 99 Output enable 98 Input 97 Output 96 Output enable 95 Input 94 Output 93 Output enable 92 Input 91 Output 90 Output enable 89 Rev. 2.00 Mar 09, 2006 page 766 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 168 PB1 Input 88 Output 87 Output enable 86 Input 85 Output 84 Output enable 83 Input 82 170 171 172 173 174 175 176 177 178 PB0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 Output 81 Output enable 80 Input 79 Output 78 Output enable 77 Input 76 Output 75 Output enable 74 Input 73 Output 72 Output enable 71 Input 70 Output 69 Output enable 68 Input 67 Output 66 Output enable 65 Input 64 Output 63 Output enable 62 Input 61 Output 60 Output enable 59 Rev. 2.00 Mar 09, 2006 page 767 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 180 PA5 Input 58 Output 57 Output enable 56 Input 55 Output 54 Output enable 53 Output 52 Output enable 51 Input 50 Output 49 Output enable 48 Input 47 Output 46 Output enable 45 Input 44 Output 43 Output enable 42 182 PA4 183 CKPO 184 PA2 185 186 PA1 PA0 187 RX–ER Input 41 188 RX–DV Input 40 189 COL Input 39 190 CRS Input 38 192 RX–CLK Input 37 194 ERXD0 Input 36 195 ERXD1 Input 35 196 ERXD2 Input 34 197 ERXD3 Input 33 198 MDIO Input 32 Output 31 Output enable 30 199 MDC Output 29 Output enable 28 Rev. 2.00 Mar 09, 2006 page 768 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 201 TX–CLK Input 27 203 TX–EN Output 26 Output enable 25 204 ETXD0 Output 24 Output enable 23 Output 22 Output enable 21 205 206 207 208 ETXD1 ETXD2 ETXD3 TX–ER Output 20 Output enable 19 Output 18 Output enable 17 Output 16 Output enable 15 1 IRL3 Input 14 2 IRL2 Input 13 3 IRL1 Input 12 4 IRL0 Input 11 5 NMI Input 10 13 MD4 Input 9 14 MD3 Input 8 15 MD2 Input 7 16 MD1 Input 6 17 MD0 Input 5 24 CKPREQ/CKM Input 4 25 CKPACK Output 3 Output enable 2 Output 1 Output enable 0 27 IVECF to TDO Note: The output enable signals are active-low. When an output enable signal is driven low, the corresponding pin is driven. The exception is the output enable signal for the MDIO pin, which is active-high. Rev. 2.00 Mar 09, 2006 page 769 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.3.6 ID code register (SDIDR) The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'0005200F, which is a fixed code, from TDO. However, no serial data can be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed. 31 28 0000 Version (4 bits) 27 0001 12 0000 0101 Part Number (16 bits) Rev. 2.00 Mar 09, 2006 page 770 of 906 REJ09B0292-0200 0010 11 0000 1 0000 111 Manufacture Identify (11 bits) 0 1 Fixed Code (1 bit) Section 18 User Debug Interface (H-UDI) 18.4 Operation 18.4.1 TAP Controller Figure 18.2 shows the internal states of TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 0 1 1 Run-test/idle 1 Select-DR-scan Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Capture-IR 0 0 Shift-IR 1 1 Exit1-IR 0 0 Pause-IR 1 0 1 0 0 Exit2-DR 1 Exit2-IR 1 Update-DR 1 0 Update-IR 1 0 Figure 18.2 TAP Controller State Transitions Rev. 2.00 Mar 09, 2006 page 771 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.4.2 H-UDI Interrupt and Serial Transfer When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR. Control of data input/output between an external device and the H-UDI is performed by monitoring the SDTRF bit in SDSR externally and internally. Internal SDTRF bit monitoring is carried out by having SDSR read by the CPU. The H-UDI interrupt and serial transfer procedure is as follows. 1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated. 2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally. After output of SDTRF = 1 from TDO is observed, serial data is transferred to SDDR. 3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be accessed by the CPU. After SDDR has been accessed, SDDR serial transfer is enabled by setting the SDTRF bit to 1 in SDSR. 4. Serial data transfer between an external device and the H-UDI can be carried out by constantly monitoring the SDTRF bit in SDSR externally and internally. Figures 18.3, 18.4, and 18.5 show the timing of data transfer between an external device and the H-UDI. Rev. 2.00 Mar 09, 2006 page 772 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) Instruction SDTRF 1 Serial data Input/ output Input 0 1 H-UDI interrupt request Shift disabled SDTRF (in SDSR)*1 Shift enabled Shift enabled SDSR and SDDR MUX*2 SDDR access state SDSR Shift SDDR SDDR SDSR CPU Shift CPU SDSR serial transfer (monitoring) Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer data input/output to SDDR is possible. 1 SDDR is shift-disabled. SDDR access by the CPU is enabled. 2 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0. Conditions: • SDTRF = 1 — When TRST = 0 — When the CPU writes 1 — In bypass mode • SDTRF = 0 — End of SDDR shift access in serial transfer 2. SDSR/SDDR (Update-DR state) internal MUX switchover timing • Switchover from SDSR to SDDR: On completion of serial transfer in which SDTRF = 1 is output from TDO • Switchover from SDDR to SDSR: On completion of serial transfer to SDDR Figure 18.3 Data Input/Output Timing Chart (1) Rev. 2.00 Mar 09, 2006 page 773 of 906 REJ09B0292-0200 TDO Bit 0 SDTRF Rev. 2.00 Mar 09, 2006 page 774 of 906 REJ09B0292-0200 Bit 0 Select-DR Bit 31 Bit 31 SDTRF Figure 18.5 Data Input/Output Timing Chart (3) Bit 0 TRST TMS Bit 0 Bit 31 TDI Bit 31 Update-DR Exit1-DR Shift-DR Capture-DR Select-DR Update-DR Exit1-DR Shift-DR Capture-DR TS0 Update-DR Exit1-DR Shift-DR Capture-DR Select-DR Update-DR Exit1-DR Shift-DR Capture-DR Select-DR Test-Logic-Reset Update-DR Run-Test/Idle Exit1-DR Shift-DR Capture-DR Select-DR Update-IR Exit1-IR Shift-IR Capture-IR Select-IR Select-DR Run-Test/Idle Test-Logic-Reset Section 18 User Debug Interface (H-UDI) TCK TRST TMS TDI TS3 TDO SDTRF Figure 18.4 Data Input/Output Timing Chart (2) TCK Section 18 User Debug Interface (H-UDI) 18.4.3 H-UDI Reset The H-UDI can be reset in two ways. • The H-UDI is reset when the TRST signal is held at 0. • When TRST = 1, the H-UDI can be reset by inputting at least five TCK clock cycles while TMS = 1. 18.5 Boundary Scan The H-UDI pins can be placed in the boundary scan mode stipulated by IEEE1149.1 by setting a command in SDIR. 18.5.1 Supported Instructions The SH7616 supports the three essential instructions defined in IEEE1149.1 (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from the SH7616’s internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, the SH7616’s input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. The SH7616’s system circuits are not affected by execution of this instruction. The instruction code is 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of the SH7616. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). Rev. 2.00 Mar 09, 2006 page 775 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) EXTEST: This instruction is provided to test external circuitry when the SH7616 is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. CLAMP: When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. The instruction code is 0010. HIGHZ: When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. The instruction code is 0010. IDCODE: When the IDCODE instruction is enabled, the value of the ID code register is output from TDO with LSB first when the TAP controller is in the Shift-DR state. While this instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. The instruction code is 0010. Rev. 2.00 Mar 09, 2006 page 776 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) 18.5.2 Notes on Use 1. Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CKIO, CAP1, CAP2). 2. Boundary scan mode does not cover reset-related signals (RES, ASEMODE). 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. Fix the ASEMODE pin high. 18.6 Usage Notes • A reset must always be executed by driving the TRST signal to 0, regardless of whether or not the H-UDI is to be activated. TRST must be held low for 20 TCK clock cycles. For details, see section 22, Electrical Characteristics. • The registers are not initialized in standby mode. If TRST is set to 0 in standby mode, bypass mode will be entered. • The frequency of TCK must be lower than that of the peripheral module clock (Pφ). For details, see section 22, Electrical Characteristics. • In data transfer, data input/output starts with the LSB. Figure 18.6 shows serial data input/output. • When data that exceeds the number of bits of the register connected between TDI and TDO is serially transferred, the serial data that exceeds the number of register bits and output from TDO is the same as that input from TDI. • If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer should then be retried, regardless of the transfer operation. • TDO is output at the falling edge of TCK when one of six instructions defined in IEEE1149.1 is selected. Otherwise, it is output at the rising edge of TCK. Rev. 2.00 Mar 09, 2006 page 777 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) • SDIR and SDSR serial data input/output In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-IR, data input from TDI is written to SDIR, but not to SDSR. TDI TDI Bit 31 Shift register SDIR Bit 0 Bit 15 Bit 15 . . . Bit 0 Bit 31 Shift register Bit 15 . . . SDIR Bit 16 SDSR TDO Bit 15 . . . TDI input data Bit 16 SDIR Bit 0 Bit 15 SDSR SDSR Bit 0 Bit 0 Capture-IR TDO Figure 18.6 Serial Data Input/Output (1) Rev. 2.00 Mar 09, 2006 page 778 of 906 REJ09B0292-0200 Update-IR Section 18 User Debug Interface (H-UDI) • SDDRH and SDDRL serial data input/output (1) In H-UDI interrupt mode, before SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDSR and SDIR are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-DR, TDI input data is not written to any register. TDI Bit 31 Shift register Bit 15 . . . SDIR Bit 16 Bit 15 Bit 15 . . . SDSR Bit 0 TDO SDIR Bit 0 SDSR Bit 0 Capture-DR (2) In H-UDI interrupt mode, after SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDDRH and SDDRL are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDDRL and bits 0 to 15 of SDDRH are output in that order from TDO. Data input from TDI is written to SDDRH and SDDRL in Update-DR. TDI TDI Bit 31 Shift register SDDRH Bit 0 Bit 15 Bit 15 . . . Bit 0 Bit 31 Shift register TDI input data Bit 16 Bit 15 . . . Bit 0 TDO SDDRH Bit 0 Bit 15 SDDRL Bit 0 Capture-DR Bit 15 . . . SDDRH Bit 16 SDDRL TDO Bit 15 . . . SDDRL Bit 0 Update-DR Figure 18.6 Serial Data Input/Output (2) Rev. 2.00 Mar 09, 2006 page 779 of 906 REJ09B0292-0200 Section 18 User Debug Interface (H-UDI) • SDIDR serial data input/output In IDCODE mode, SDIDR is captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 31 of SDIDR are output in that order from TDO. In Update-DR, data input from TDI is not written to any register. TDI Bit 31 Shift register . . . . SDIDR Bit 0 TDO Bit 15 SDIDR Bit 0 Capture-DR Figure 18.6 Serial Data Input/Output (3) Rev. 2.00 Mar 09, 2006 page 780 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Section 19 Pin Function Controller (PFC) 19.1 Overview The pin function controller (PFC) consists of registers to select multiplexed pin functions and input/output direction. The pin function and input/output direction can be selected for individual pins regardless of the operating mode of the chip. Table 19.1 shows the chip’s multiplex pins. Rev. 2.00 Mar 09, 2006 page 781 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Table 19.1 Multiplex Pins Function 1 [00]* Function 2 [01]* Function 3 [10]* Function 4 [11]* Signal Port Name I/O Related Signal Module Name I/O Related Signal Module Name I/O Related Signal Module Name I/O Related Module A PA13 I/O Port SRCK0 I SIO0 — — — — — — A PA12 I/O Port SRS0 I SIO0 — — — — — — A PA11 I/O Port SRXD0 I SIO0 — — — — — — A PA10 I/O Port STCK0 I SIO0 — — — — — — A PA9 I/O Port STS0 I/O SIO0 — — — — — — A PA8 I/O Port STXD0 O SIO0 — — — — — — A WDTOVF O WDT PA7 I/O Port — — — — — — A PA6 I/O Port FTCI I FRT — — — — — — A PA5 I/O Port FTI I FRT — — — — — — A PA4 I/O Port FTOA O FRT — — — — — — A CKPO O Port FTOB O FRT — — — — — — A PA2 I/O Port LNKSTA I EtherC — — — — — — A PA1 I/O Port EXOUT O EtherC — — — — — — A PA0 I/O Port CAMSEN I EtherC — — — — — — B PB15 I/O Port — — — SCK1 I/O SCIF1 — — — B PB14 I/O Port — — — RXD1 I SCIF1 — — — B PB13 I/O Port — — — TXD1 O SCIF1 — — — B PB12 I/O Port SRCK2 I SIO2 RTS O SCIF1 STATS1 O BSC B PB11 I/O Port SRS2 I SIO2 CTS I SCIF1 STATS0 O BSC B PB10 I/O Port SRXD2 I SIO2 TIOCA1 I/O TPU1 — — — B PB9 I/O Port STCK2 I SIO2 TIOCB1 I/O TPU1 — — — B PB8 I/O Port STS2 I/O SIO2 TIOCA2 I/O TPU2 — — — B PB7 I/O Port STXD2 O SIO2 TIOCB2 I/O TPU2 — — — B PB6 I/O Port SRCK1 I SIO1 SCK2 I/O SCIF2 — — — B PB5 I/O Port SRS1 I SIO1 RXD2 I SCIF2 — — — B PB4 I/O Port SRXD1 I SIO1 TXD2 O SCIF2 — — — B PB3 I/O Port STCK1 I SIO1 TIOCA0 I/O TPU2 — — — B PB2 I/O Port STS1 I/O SIO1 TIOCB0 I/O TPU2 — — — B PB1 I/O Port STXD1 O SIO1 TIOCC0 I/O TPU2 — — — B PB0 I/O Port — — — TIOCD0 I/O TPU2 WOL O EtherC Notes: In the initial state, function 1 is selected. * The initial value is "input." The figures in brackets indicate the settings of the mode bits (MD1, MD0) in the PFC to select multiplexed functions in port A[0:13] and port B[0:15]. Rev. 2.00 Mar 09, 2006 page 782 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) 19.2 Register Configuration Table 19.2 shows the PFC registers. Table 19.2 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port A control register PACR R/W H'0000 H'FFFFFC80 8, 16 Port A I/O register PAIOR R/W H'0000 H'FFFFFC82 8, 16 Port B control register PBCR R/W H'0000 H'FFFFFC88 8, 16 Port B I/O register PBIOR R/W H'0000 H'FFFFFC8A 8, 16 Port B control register 2 PBCR2 R/W H'0000 H'FFFFFC8E 8, 16 19.3 Register Descriptions 19.3.1 Port A Control Register (PACR) Bit: 15 14 — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit: 13 12 11 10 9 8 PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port A control register (PACR) is a 16-bit read/write register that selects the functions of the 14 multiplex pins in port A. PACR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Bits 15 and 14—Reserved: These bits are always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 783 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Bit 13—PA13 Mode Bit (PA13MD): Selects the function of pin PA13/SRCK0. Bit 13: PA13MD Description 0 General input/output (PA13) 1 SIOF serial receive clock input (SRCK0) (Initial value) Bit 12—PA12 Mode Bit (PA12MD): Selects the function of pin PA12/SRS0. Bit 12: PA12MD Description 0 General input/output (PA12) 1 SIOF serial receive synchronous input (SRS0) (Initial value) Bit 11—PA11 Mode Bit (PA11MD): Selects the function of pin PA11/SRXD0. Bit 11: PA11MD Description 0 General input/output (PA11) 1 SIOF serial receive data (SRXD0) (Initial value) Bit 10—PA10 Mode Bit (PA10MD): Selects the function of pin PA10/STCK0. Bit 10: PA10MD Description 0 General input/output (PA10) 1 SIOF serial transmit clock (STCK0) (Initial value) Bit 9—PA9 Mode Bit (PA9MD): Selects the function of pin PA9/STS0. Bit 9: PA9MD Description 0 General input/output (PA9) 1 SIOF serial transmit synchronous input/output (STS0) (Initial value) Bit 8—PA8 Mode Bit (PA8MD): Selects the function of pin PA8/STXD0. Bit 8: PA8MD Description 0 General input/output (PA8) 1 SIOF serial transmit data output (STXD0) Rev. 2.00 Mar 09, 2006 page 784 of 906 REJ09B0292-0200 (Initial value) Section 19 Pin Function Controller (PFC) Bit 7—PA7 Mode Bit (PA7MD): Selects the function of pin WDTOVF/PA7. Bit 7: PA7MD Description 0 WDT overflow signal output (WDTOVF)* 1 General input/output (PA7) (Initial value) Note: * WDTOVF is an output pin after a reset, so care is required when using this pin as a general input port (PA7). Bit 6—PA6 Mode Bit (PA6MD): Selects the function of pin PA6/FTCI. Bit 6: PA6MD Description 0 General input/output (PA6) 1 FRT clock input (FTCI) (Initial value) Bit 5—PA5 Mode Bit (PA5MD): Selects the function of pin PA5/FTI. Bit 5: PA5MD Description 0 General input/output (PA5) 1 FRT input capture input (FTI) (Initial value) Bit 4—PA4 Mode Bit (PA4MD): Selects the function of pin PA4/FTO4. Bit 4: PA4MD Description 0 General input/output (PA4) 1 FRT output compare output (FTOA) (Initial value) Bit 3—PA3 Mode Bit (PA3MD): Selects the function of pin CKPO/FTOB. Bit 3: PA3MD Description 0 Peripheral module clock output (CKPO) 1 FRT output compare output (FTOB) (Initial value) Bit 2—PA2 Mode Bit (PA2MD): Selects the function of pin PA2/LNKSTA. Bit 2: PA2MD Description 0 General input/output (PA2) 1 EtherC rink status input (LNKSTA) (Initial value) Rev. 2.00 Mar 09, 2006 page 785 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Bit 1—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/EXOUT. Bit 1: PA1MD Description 0 General input/output (PA1) 1 EtherC general external output (EXOUT) (Initial value) Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0. Bit 0: PA0MD Description 0 General input/output (PA0) 1 EtherC CAM sense input (CAMSEN) 19.3.2 (Initial value) Port A I/O Register (PAIOR) Bit: 15 14 13 12 — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 R/W: 10 9 8 PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR PA7IOR PA6IOR PA5IOR PA4IOR Initial value: 11 — PA2IOR PA1IOR PA0IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W The port A I/O register (PAIOR) is a 16-bit read/write register that selects the input/output direction of the 14 multiplex pins in port A. Bits PA13IOR to PA4IOR and PA2IOR to PA0IOR correspond to individual pins in port A. PAIOR is enabled when port A pins function as general input pins (PA13 to PA4 and PA2 to PA0), and disabled otherwise. When port A pins function as PA13 to PA4 and PA2 to PA0, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Rev. 2.00 Mar 09, 2006 page 786 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) 19.3.3 Port B Control Registers (PBCR, PBCR2) The port B control registers (PBCR and PBCR2) are 16-bit read/write registers that select the functions of the 16 multiplex pins in port B. PBCR selects the functions of the pins for the upper 8 bits in port B, and PBCR2 selects the functions of the pins for the lower 8 bits in port B. PBCR and PBCR2 are initialized to H'0000 by a power-on reset. They are not initialized by a manual reset or in standby mode or sleep mode. Port B Control Register (PBCR) Bit: 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Bits 15 and 14—PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/SCK1. Bit 15: PB15MD1 Bit 14: PB15MD0 Description 0 0 General input/output (PB15) 1 Reserved 0 SCIF1 serial clock input/output (SCK1) 1 Reserved 1 (Initial value) Rev. 2.00 Mar 09, 2006 page 787 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Bits 13 and 12—PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/RXD1. Bit 13: PB14MD1 Bit 12: PB14MD0 Description 0 0 General input/output (PB14) 1 Reserved 0 SCIF1 serial data input (RXD1) 1 Reserved 1 (Initial value) Bits 11 and 10—PB13 Mode Bits 1 and 0 (PB13MD1, PB13MD0): These bits select the function of pin PB13/TXD1. Bit 11: PB13MD1 Bit 10: PB13MD0 Description 0 0 General input/output (PB13) 1 Reserved 0 SCIF1 serial data output (TXD1) 1 Reserved 1 (Initial value) Bits 9 and 8—PB12 Mode Bits 1 and 0 (PB12MD1, PB12MD0): These bits select the function of pin PB12/SRCK2/RTS/STATS1. Bit 9: PB12MD1 Bit 8: PB12MD0 Description 0 0 General input/output (PB12) 1 SIO2 serial receive clock input (SRCK2) 0 SCIF1 transmit request (RTS) 1 BSC status 1 output (STATS1) 1 (Initial value) Bits 7 and 6—PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the function of pin PB11/SRS2/CTS/STATS0. Bit 7: PB11MD1 Bit 6: PB11MD0 Description 0 0 General input/output (PB11) 1 SIO2 serial receive synchronous input (SRS2) 0 SCIF1 transmit permission (CTS) 1 BSC status 0 output (STATS0) 1 Rev. 2.00 Mar 09, 2006 page 788 of 906 REJ09B0292-0200 (Initial value) Section 19 Pin Function Controller (PFC) Bits 5 and 4—PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/SRXD2/TIOCA1. Bit 5: PB10MD1 Bit 4: PB10MD0 Description 0 0 General input/output (PB10) 1 SIO2 serial receive data input (SRXD2) 0 TPU1 input capture input/output compare output (TIOCA1) 1 Reserved 1 (Initial value) Bits 3 and 2—PB9 Mode Bits 1 and 0 (PB9MD1, PB9MD0): These bits select the function of pin PB9/STCK2/TIOCB1, TCLKC. Bit 3: PB9MD1 Bit 2: PB9MD0 Description 0 0 General input/output (PB9) 1 SIO2 serial transmit clock input (STCK2) 1 0 TPU1 input capture input/output compare output (TIOCB1)* 1 Reserved (Initial value) Note: * Timer clock input C (TCLKC) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR. Bits 1 and 0—PB8 Mode Bits 1 and 0 (PB8MD1, PB8MD0): These bits select the function of pin PB8/STS2/TIOCA2. Bit 1: PB8MD1 Bit 0: PB8MD0 Description 0 0 General input/output (PB8) 1 SIO2 serial transmit synchronous input/output (STS2) 0 TPU2 input capture input/output compare output (TIOCA2) 1 Reserved 1 (Initial value) Rev. 2.00 Mar 09, 2006 page 789 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Port B Control Register 2 (PBCR2) Bit: 15 14 13 12 11 10 9 8 PB7 MD1 PB7 MD0 PB6 MD1 PB6 MD0 PB5 MD1 PB5 MD0 PB4 MD1 PB4 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB3 MD1 PB3 MD0 PB2 MD1 PB2 MD0 PB1 MD1 PB1 MD0 PB0 MD1 PB0 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: Bits 15 and 14—PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/STXD2/TIOCB2, TCLKD. Bit 15: PB7MD1 Bit 14: PB7MD0 Description 0 0 General input/output (PB7) 1 SIO2 serial transmit data output (STXD2) 0 TPU2 input capture input/output compare output (TIOCB2)* 1 Reserved 1 (Initial value) Note: * Timer clock input D (TCLKD) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR. Bits 13 and 12—PB6 Mode Bits 1 and 0 (PB6MD1, PB6MD0): These bits select the function of pin PB6/SRCK1/SCK2. Bit 13: PB6MD1 Bit 12: PB6MD0 Description 0 0 General input/output (PB6) 1 SIO1 serial receive clock input (SRCK1) 1 0 SCIF2 serial clock input/output (SCK2) 1 Reserved Rev. 2.00 Mar 09, 2006 page 790 of 906 REJ09B0292-0200 (Initial value) Section 19 Pin Function Controller (PFC) Bits 11 and 10—PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/SRS1/RXD2. Bit 11: PB5MD1 Bit 10: PB5MD0 Description 0 0 General input/output (PB5) 1 SIO1 serial receive synchronous input (SRS1) 0 SCIF2 serial data input (RXD2) 1 Reserved 1 (Initial value) Bits 9 and 8—PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin PB4/SRXD1/TXD2. Bit 9: PB4MD1 Bit 8: PB4MD0 Description 0 0 General input/output (PB4) 1 SIO1 serial receive data input (SRXD1) 0 SCIF2 serial data output (TXD2) 1 Reserved 1 (Initial value) Bits 7 and 6—PB3 Mode Bits 1 and 0 (PB3MD1, PB3MD0): These bits select the function of pin PB3/STCK1/TIOCA0. Bit 7: PB3MD1 Bit 6: PB3MD0 Description 0 0 General input/output (PB3) 1 SIO1 serial transmit clock input (STCK1) 0 TPU0 input capture input/output compare output (TIOCA0) 1 Reserved 1 (Initial value) Bits 5 and 4—PB2 Mode Bits 1 and 0 (PB2MD1, PB2MD0): These bits select the function of pin PB2/STS1/TIOCB0. Bit 5: PB2MD1 Bit 4: PB2MD0 Description 0 0 General input/output (PB2) 1 SIO1 serial transmit synchronous input/output (STS1) 0 TPU0 input capture input/output compare output (TIOCB0) 1 Reserved 1 (Initial value) Rev. 2.00 Mar 09, 2006 page 791 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Bits 3 and 2—PB1 Mode Bits 1 and 0 (PB1MD1, PB1MD0): These bits select the function of pin PB1/STXD1/TIOCC0/TCLKA. Bit 3: PB1MD1 Bit 2: PB1MD0 Description 0 0 General input/output (PB1) 1 SIO1 serial transmit data output (STXD1) 0 TPU0 input capture input/output compare output (TIOCC0)* 1 Reserved 1 (Initial value) Note: * Timer clock input A (TCLKA) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR. Bits 1 and 0—PB0 Mode Bits 1 and 0 (PB0MD1, PB0MD0): These bits select the function of pin PB0/TIOCD0/TCLKB. Bit 1: PB0MD1 Bit 0: PB0MD0 Description 0 0 General input/output (PB0) 1 Reserved 1 0 TPU0 input capture input/output compare output (TIOCD0)* 1 EtherC Wake-On-LAN output (WOL) (Initial value) Note: * Timer clock input B (TCLKB) is selected when the TPU phase counting mode is set, or according to the setting of bits TPSC2 to TPSC0 in TCR. Rev. 2.00 Mar 09, 2006 page 792 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) 19.3.4 Port B I/O Register (PBIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B I/O register (PBIOR) is a 16-bit read/write register that selects the input/output direction of the 16 multiplex pins in port B. Bits PB15IOR to PB0IOR correspond to individual pins in port B. PBIOR is enabled when port B pins function as general input pins (PB15 to PB0), and disabled otherwise. When port B pins function as PB15 to PB0, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Rev. 2.00 Mar 09, 2006 page 793 of 906 REJ09B0292-0200 Section 19 Pin Function Controller (PFC) Rev. 2.00 Mar 09, 2006 page 794 of 906 REJ09B0292-0200 Section 20 I/O Ports Section 20 I/O Ports 20.1 Overview This chip has two ports, designated A and B. Port A is a 14-bit input/output port, and port B is a 16-bit input/output port. The port pins are multiplexed as general input/output and other functions. (The function of multiplexed multiplex pins is selected by means of the pin function controller (PFC).) Ports A and B are each provided with a data register for storing pin data. 20.2 Port A Port A is an input/output port with the 14 pins shown in figure 20.1. Of the 14 pins, the CKPO pin has no port data register bit, and is multiplexed as an internal clock pin. PA13 (input/output) / SRCK0 Port A (input) PA12 (input/output) / SRS0 (input) PA11 (input/output) / SRXD0 (input) PA10 (input/output) / STCK0 (input) PA9 (input/output) / STS0 (input/output) PA8 (input/output) / STXD0 WDTOVF* (output) / PA7 (output) (input/output) PA6 (input/output) / FTCI (input) PA5 (input/output) / FTI (input) PA4 (input/output) / FTOA CKPO (output) / FTOB (output) (output) PA2 (input/output) / LNKSTA (input) PA1 (input/output) / EXOUT (output) PA0 (input/output) Note: * The fact that the WDTOVF pin is set to output mode after a reset must be noted when it is to be used as a general I/O port (PA7). Figure 20.1 Port A Rev. 2.00 Mar 09, 2006 page 795 of 906 REJ09B0292-0200 Section 20 I/O Ports 20.2.1 Register Configuration The port A register is shown in table 20.1. Table 20.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port A data register PADR R/W H'0000 H'FFFFFC84 8, 16 20.2.2 Port A Data Register (PADR) Bit: 15 14 — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: 13 12 11 10 9 PA13DR PA12DR PA11DR PA10DR PA9DR 8 PA8DR 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR — PA2DR PA1DR PA0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W The port A data register (PADR) is a 16-bit read/write register that stores port A data. Bits 15, 14, and 3 are reserved: they always read 0, and the write value should always be 0. Bits PA13DR to PA0DR correspond to pins PA13 to PA0. When a pin functions as a general output, if a value is written to PADR, that value is output directly from the pin, and if PADR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is read the pin state, not the register value, is returned directly. If a value is written to PADR, although that value is written into PADR it does not affect the pin state. Table 20.2 summarizes port A data register read/write operations. PADR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Rev. 2.00 Mar 09, 2006 page 796 of 906 REJ09B0292-0200 Section 20 I/O Ports Table 20.2 Port A Data Register (PADR) Read/Write Operations PAIOR Pin Function Read Write 0 General input Pin state Value is written to PADR, but does not affect pin state Other than general input Pin state Value is written to PADR, but does not affect pin state General output PADR value Write value is output from pin Other than general output PADR value Value is written to PADR, but does not affect pin state 1 20.3 Port B Port B is an input/output port with the 16 pins shown in figure 20.2. Port B PB15 (input/output) / Reserved / SCK1 (input/output) PB14 (input/output) / Reserved / RXD1 (input) PB13 (input/output) / Reserved / TXD1 (output) PB12 (input/output) / SRCK2 (input) / RTS (output) / STATS1 (output) PB11 (input/output) / SRS2 / CTS (input) / STATS0 (output) (input) PB10 (input/output) / SRXD2 (input) / TIOCA1 (input/output) PB9 (input/output) / STCK2 (input) / TIOCB1 (input/output) PB8 (input/output) / STS2 (input/output) / TIOCA2 (input/output) PB7 (input/output) / STXD2 (output) / TIOCB2 (input/output) PB6 (input/output) / SRCK1 (input) / SCK2 (input/output) PB5 (input/output) / SRS1 (input) / RXD2 (input) PB4 (input/output) / SRXD1 (input) / TXD2 (output) PB3 (input/output) / STCK1 (input) / TIOCA0 (input/output) PB2 (input/output) / STS1 (input/output) / TIOCB0 (input/output) PB1 (input/output) / STXD1 (output) / TIOCD0 (input/output) PB0 (input/output) / Reserved / TIOCD0 (input/output) / WOL (output) Figure 20.2 Port B 20.3.1 Register Configuration Table 20.3 shows the port B register. Rev. 2.00 Mar 09, 2006 page 797 of 906 REJ09B0292-0200 Section 20 I/O Ports Table 20.3 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port B data register PBDR R/W H'0000 H'FFFFFC8C 8, 16 20.3.2 Port B Data Register (PBDR) Bit: 15 14 13 12 11 10 9 PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR Initial value: R/W: Bit: Initial value: R/W: 8 PB8DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B data register (PBDR) is a 16-bit read/write register that stores port B data. Bits PB15DR to PB0DR correspond to pins PB15 to PB0. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR it does not affect the pin state. Table 20.4 shows port B data register read/write operations. PBDR is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode or sleep mode. Table 20.4 Port B Data Register (PBDR) Read/Write Operations PBIOR Pin Function Read Write 0 General input Pin state Value is written to PBDR, but does not affect pin state Other than general input Pin state Value is written to PBDR, but does not affect pin state General output PBDR value Write value is output from pin Other than general output PBDR value Value is written to PBDR, but does not affect pin state 1 Rev. 2.00 Mar 09, 2006 page 798 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Section 21 Power-Down Modes 21.1 Overview This chip has a module standby function (which reduces power consumption by selectively halting operation of unnecessary modules among the on-chip peripheral modules and the DSP unit), a sleep mode (which halts CPU functions), and a standby mode (which halts all functions). 21.1.1 Power-Down Modes The following modes and function are provided as power-down modes: 1. Sleep mode 2. Standby mode 3. Module standby function (UBC, DMAC, DSP, FRT, SCIF1–2, TPU, SIOF, SIO1–2) Table 21.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Rev. 2.00 Mar 09, 2006 page 799 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Table 21.1 Power-Down Modes State Mode Sleep mode On-Chip Oscillation Circuit, Transition E-DMAC, CPU, Condition EtherC Cache DSP SLEEP Runs instruction executed with SBY bit set to 0 in SBYCR1 Module MSTP bit Runs standby for relevant function module is set to 1 21.1.2 Canceling Procedure 1. Interrupt 2. DMA address error 3. Poweron reset 4. Manual reset 1. NMI Halted Halted Halted, UBC: Halted, Held or interrupt and and register high register values held impedance 2. Powervalues Other than on reset held 3. Manual UBC: Halted reset Runs When Runs When an FRT, and 1. Clear MSTP bit MSTP MSTP bit is SCIF1, 2 to 0 is 1, 1, the clock pins are the clock supply to initialized, 2. Powersupply is the relevant and others on reset halted module is operate 3. Manual halted reset Halted Halted Standby SLEEP Halted mode instruction executed with SBY bit set to 1 in SBYCR1 BSC UBC, DMAC, FRT, SCIF1–2, TPU, SIOF, SIO1–2 Pins Runs Runs Runs Register Table 21.2 shows the register configuration. Table 21.2 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Standby control register 1 SBYCR1 R/W H'00 H'FFFFFE91 8 Standby control register 2 SBYCR2 R/W H'00 H'FFFFFE93 8 Rev. 2.00 Mar 09, 2006 page 800 of 906 REJ09B0292-0200 Section 21 Power-Down Modes 21.2 Register Descriptions 21.2.1 Standby Control Register 1 (SBYCR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 SBY HIZ MSTP5 MSTP4 MSTP3 — MSTP1 — (UBC) (DMAC) (DSP) 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R (FRT) Standby control register 1 (SBYCR1) is an 8-bit read/write register that sets the power-down mode. SBYCR is initialized to H'00 by a reset. Bit 7—Standby (SBY): Specifies transition to standby mode. To enter the standby mode, halt the WDT (set the TME bit in WTCSR to 0) and set the SBY bit. Bit 7: SBY Description 0 Executing a SLEEP instruction puts the chip into sleep mode 1 Executing a SLEEP instruction puts the chip into standby mode (Initial value) Bit 6—Port High Impedance (HIZ): Selects whether output pins are set to high impedance or retain the output state in standby mode. When HIZ = 0 (initial state), the specified pin retains its output state. When HIZ = 1, the pin goes to the high-impedance state. See Appendix B.1, Pin States during Resets, Power-Down States and Bus Release State, for which pins are controlled. Bit 6: HIZ Description 0 Pin state retained in standby mode 1 Pin goes to high impedance in standby mode (Initial value) Bit 5—Module Stop 5 (MSTP5): Specifies halting the clock supply to the user break controller (UBC). When the MSTP5 bit is set to 1, the supply of the clock to the UBC is halted. When the clock halts, the UBC registers retain their pre-halt state. Do not set this bit while the UBC is running. Bit 5: MSTP5 Description 0 UBC running 1 Clock supply to UBC halted (Initial value) Rev. 2.00 Mar 09, 2006 page 801 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Bit 4—Module Stop 4 (MSTP4): Specifies halting the clock supply to the DMAC. When MSTP4 bit is set to 1, the supply of the clock to the DMAC is halted. When the clock halts, the DMAC retains its pre-halt state. When MSTP4 is cleared to 0 and the DMAC begins running again, its starts operating from its pre-halt state. Set this bit while the DMAC is halted; this bit cannot be set while the DMAC is operating (transferring data). Bit 4: MSTP4 Description 0 DMAC running 1 Clock supply to DMAC halted (Initial value) Bit 3—Module Stop 3 (MSTP3): Specifies halting the clock supply to the DSP unit. When the MSTP3 bit is set to 1, the supply of the clock to the DSP unit is halted. When the clock halts, the operation result prior to the halt is retained. This bit should be set when the DSP unit is halted. When the DSP unit is halted, no instructions with a DSP register, MACH, or MACL as an operand can be used. Bit 3: MSTP3 Description 0 DSP running 1 Clock supply to DSP halted (Initial value) Bit 2—Reserved: This bit is always read as 0. The write value should always be 0. Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the 16-bit free-running timer (FRT). When the MSTP1 bit is set to 1, the supply of the clock to the FRT is halted. When the clock halts, all FRT registers are initialized except the FRT interrupt vector register in INTC, which holds its previous value. When MSTP1 is cleared to 0 and the FRT begins running again, its starts operating from its initial state. Bit 1: MSTP1 Description 0 FRT running 1 Clock supply to FRT halted Bit 0—Reserved: This bit is always read as 0. The write value should always be 0. Rev. 2.00 Mar 09, 2006 page 802 of 906 REJ09B0292-0200 (Initial value) Section 21 Power-Down Modes 21.2.2 Standby Control Register 2 (SBYCR2) Bit: 7 6 — — 5 4 3 MSTP11 MSTP10 MSTP9 (TPU) (SIO2) (SIO1) 2 1 0 MSTP8 MSTP7 MSTP6 (SIOF) (SCIF2) (SCIF1) Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Standby control register 2 (SBYCR2) is an 8-bit read/write register that sets the power-down mode state. SBYCR2 is initialized to H'00 by a reset. Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0. Bit 5—Module Stop 11 (MSTP11): Specifies halting the clock supply to the 16-bit timer pulse unit (TPU). When the MSTP11 bit is set to 1, the supply of the clock to the TPU is halted. When the clock halts, the TPU retains its pre-halt state, and the TPU interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP11 is cleared to 0 and the clock supply to the TPU is resumed, the TPU starts operating again. Bit 5: MSTP11 Description 0 TPU running 1 Clock supply to TPU halted (Initial value) Bit 4—Module Stop 10 (MSTP10): Specifies halting the clock supply to SIO channel 2. When the MSTP10 bit is set to 1, the supply of the clock to SIO channel 2 is halted. When the clock halts, SIO channel 2 retains its pre-halt state, and the SIO channel 2 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP10 is cleared to 0 and the clock supply to SIO channel 2 is restarted, operation starts again. Bit 4: MSTP10 Description 0 SIO channel 2 running 1 Clock supply to SIO channel 2 halted (Initial value) Rev. 2.00 Mar 09, 2006 page 803 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Bit 3—Module Stop 9 (MSTP9): Specifies halting the clock supply to SIO channel 1. When the MSTP9 bit is set to 1, the supply of the clock to SIO channel 1 is halted. When the clock halts, SIO channel 1 retains its pre-halt state, and the SIO channel 1 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP9 is cleared to 0 and the clock supply to SIO channel 1 is restarted, operation starts again. Bit 3: MSTP9 Description 0 SIO channel 1 running 1 Clock supply to SIO channel 1 halted (Initial value) Bit 2—Module Stop 8 (MSTP8): Specifies halting the clock supply to SIOF. When the MSTP8 bit is set to 1, the supply of the clock to SIOF is halted. When the clock halts, SIOF retains its pre-halt state, and the SIOF interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP8 is cleared to 0 and the clock supply to SIOF is restarted, operation starts again. Bit 2: MSTP8 Description 0 SIOF running 1 Clock supply to SIOF halted (Initial value) Bit 1—Module Stop 7 (MSTP7): Specifies halting the clock supply to SCIF2. When the MSTP7 bit is set to 1, the supply of the clock to SCIF2 is halted. When the clock halts, the SCIF2 registers are initialized, but the SCIF2 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP7 is cleared to 0 and SCIF2 begins running again, it starts operating from its initial state. Bit 1: MSTP7 Description 0 SCIF2 running 1 Clock supply to SCIF2 halted (Initial value) Bit 0—Module Stop 6 (MSTP6): Specifies halting the clock supply to SCIF1. When the MSTP6 bit is set to 1, the supply of the clock to SCIF1 is halted. When the clock halts, the SCIF1 registers are initialized, but the SCIF1 interrupt vector register in the INTC retains its pre-halt value. Therefore, when MSTP6 is cleared to 0 and SCIF1 begins running again, it starts operating from its initial state. Bit 0: MSTP6 Description 0 SCIF1 running 1 Clock supply to SCIF1 halted Rev. 2.00 Mar 09, 2006 page 804 of 906 REJ09B0292-0200 (Initial value) Section 21 Power-Down Modes 21.3 Sleep Mode 21.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the SBY bit in SBYCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode. 21.3.2 Canceling Sleep Mode Sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset. Cancellation by an Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. Sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU’s status register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. Cancellation by a DMA Address Error: If a DMA address error occurs, sleep mode is canceled and DMA address error exception handling is executed. Cancellation by a Power-On Reset: A power-on reset cancels sleep mode. Cancellation by a Manual Reset: A manual reset cancels sleep mode. 21.4 Standby Mode 21.4.1 Transition to Standby Mode To enter standby mode, set the SBY bit to 1 in SBYCR1, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. The NMI interrupt cannot be accepted when the SLEEP instruction is executed, or for the following five cycles. In standby mode, the clock supply to all on-chip peripheral modules is halted as well as the CPU. CPU register contents are held, and some on-chip peripheral modules are initialized. Rev. 2.00 Mar 09, 2006 page 805 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Table 21.3 Register States in Standby Mode Registers with Undefined Contents Module Registers Initialized Registers that Retain Data Interrupt controller (INTC) — All registers — User break controller (UBC) — All registers — Bus state controller (BSC) — All registers — • DMA source — address registers 0 and 1 DMA operation register • DMA destination address registers 0 and 1 • DMA transfer count registers 0 and 1 • DMA request/ response selection control registers 0 and 1 • Vector number setting registers DMA0 and DMA1 Direct memory access controller (DMAC) DMA channel control register 0, 1 Watchdog timer (WDT) Bits 7–5 of the timer control/status register Bits 2–0 of the timer control/status register Reset control/status register Timer counter All registers — — Serial communication interface All registers with FIFO (SCIF1–2) — — 16-bit free-running timer (FRT) — Serial I/O with FIFO (SIOF) — All registers — Serial I/O (SIO1–2) — All registers — User debug interface (H-UDI) — All registers — 16-bit timer pulse unit (TPU) — All registers — Pin function controller (PFC) — All registers — Ethernet controller direct memory access controller (EDMAC) All registers — — Ethernet controller (EtherC) All registers — — Others — Standby control register — 1, 2 Frequency modification register Rev. 2.00 Mar 09, 2006 page 806 of 906 REJ09B0292-0200 Section 21 Power-Down Modes 21.4.2 Canceling Standby Mode Standby mode is canceled by an NMI interrupt, a power-on reset, or a manual reset. Cancellation by an NMI Interrupt: When a rising edge or falling edge is detected in the NMI signal, after the elapse of the time set in the WDT timer control/status register, clocks are supplied to the entire chip, standby mode is canceled, and NMI exception handling begins. Insure that the interval set for the WDT is at least as long as the oscillation stabilization time. When standby mode is canceled by a falling edge in the NMI signal, insure that the NMI pin goes high when standby mode is entered (when the clock is halted), and goes low on recovering from standby mode (when the clock starts after oscillation has stabilized). The low level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin. When standby mode is canceled by a rising edge in the NMI signal, insure that the NMI pin goes low when standby mode is entered (when the clock is halted), and goes high on recovering from standby mode (when the clock starts after oscillation has stabilized). The high level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin. Cancellation by a Power-On Reset: A power-on reset cancels standby mode. Cancellation by a Manual Reset: A manual reset cancels standby mode. 21.4.3 Standby Mode Cancellation by NMI Interrupt The following example describes moving to the standby mode upon the fall of the NMI signal and clearing the standby mode when the NMI signal rises. Figure 21.1 shows the timing. When the NMI pin level changes from high to low after the NMI edge select bit (NMIE) of the interrupt control register (ICR) has been set to 0 (detect falling edge), an NMI interrupt is accepted. When the NMIE bit is set to 1 (detect rising edge) by the NMI exception service routine, the standby bit (SBY) of the standby control register 1 (SBYCR1) is set to 1 and a SLEEP instruction is executed, the standby mode is entered. The standby mode is cleared the next time the NMI pin level changes from low level to high level. The high level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin. Rev. 2.00 Mar 09, 2006 page 807 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Oscillator CKIO (output) NMI NMIE SBY Oscillation settling time NMI exception handling WDT set time Standby mode Exception service routine, SBY = 1, SLEEP instruction Start of oscillation NMI exception handling Figure 21.1 Standby Mode Cancellation by NMI Interrupt 21.4.4 Clock Pause Function When the clock is input from the CKIO pin, the clock frequency can be modified or the clock stopped. The CKPREQ/CKM pin is provided for this purpose. Note that clock pauses are not accepted while the watchdog timer (WDT) is operating (i.e. when the timer enable bit (TME) in the WDT’s timer control/status register (WTCSR) is 1). When the clock pause request function is used, the standby bit (SBY) in the standby control register 1 (SBYCR1) must be set to 1 before inputting the request signal. The clock pause function is used as described below. 1. Set the TME bit in the watchdog timer’s WTCSR register to 0, and set the SBY bit in SBYCR1 to 1. 2. Apply a low level to the CKPREQ/CKM pin. 3. When the chip enters the standby state internally, a low level is output from the CKPACK pin. 4. After confirming that the CKPACK pin has gone low, perform clock halting or frequency modification. 5. To cancel the clock pause state (standby state), apply a high level to the CKPREQ/CKM pin. (Inside the chip , the standby state is canceled by detecting a rising edge at the CKPREQ/CKM pin.) Rev. 2.00 Mar 09, 2006 page 808 of 906 REJ09B0292-0200 Section 21 Power-Down Modes 6. When PLL circuit 1 is operational, the WDT starts counting up inside the chip. When PLL circuit 1 is halted, the WDT is not activated. 7. When the internal clock stabilizes, the CKPACK pin goes high, giving external notification that the chip can be operated. The standby state, all on-chip peripheral module states, and all pin states during clock pause are the same as in the normal standby mode. Figure 21.2 shows the timing chart for the clock pause function. Frequency modification CKIO input CKPREQ/CKM input Clock pause request cancellation CKPACK output WDT count-up Clock pause acceptance processing Normal state Clock pause state Figure 21.2 Clock Pause Function Timing Chart (PLL Circuit 1 Operating) Rev. 2.00 Mar 09, 2006 page 809 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Figure 21.3 shows the clock pause function timing chart when the PLL circuit is halted. Frequency modification CKIO input CKPREQ/ CKM input Clock pause request cancellation CKPACK output Clock pause acceptance processing Clock pause state Normal state Figure 21.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted) The clock pause state can be canceled by means of NMI input, in the same way as the normal standby state. The clock pause request should be canceled within four CKIO clock cycles after NMI input. Figure 21.4 shows the timing chart for clock pause state cancellation by means of NMI input (in the case of rising edge detection). Rev. 2.00 Mar 09, 2006 page 810 of 906 REJ09B0292-0200 Section 21 Power-Down Modes Frequency modification Max. 4 cycles CKIO input CKPREQ/ CKM input Clock pause request cancellation NMI input NMI interrupt CKPACK output Clock pause acceptance processing Clock pause state Normal state Figure 21.4 Clock Pause Function Timing Chart (Cancellation by NMI Input) 21.4.5 Notes on Standby Mode 1. When the chip enters standby mode during use of the cache, disable the cache before making the mode transition. Initialize the cache beforehand when the cache is used after returning to standby mode. The contents of the on-chip RAM are not retained in standby mode when cache is used as on-chip RAM. 2. If an on-chip peripheral register is written in the 10 clock cycles before the chip transits to standby mode, read the register before executing the SLEEP instruction. 3. When using clock mode 0, 1, or 2, the CKIO pin is the clock output pin. Note the following when standby mode is used in these clock modes. When standby mode is canceled by NMI, an unstable clock is output from the CKIO pin during the oscillation settling time after NMI input. This also applies to clock output in the case of cancellation by a power-on reset or manual reset. Power-on reset and manual reset input should be continued for a period at least equal to for the oscillation settling time. 4. Before entering the standby mode, stop operation of the internal DMAC (E-DMAC or DMAC). Rev. 2.00 Mar 09, 2006 page 811 of 906 REJ09B0292-0200 Section 21 Power-Down Modes 21.5 Module Standby Function 21.5.1 Transition to Module Standby Function By setting one of bits MSTP11–MSTP3, MSTP1 to 1 in standby control register 1 or 2, the supply of the clock to the corresponding on-chip peripheral module or DSP unit can be halted. This function can be used to reduce the power consumption. Do not perform read/write operations for a module in module standby mode. With the module standby function, the external pins of the DMAC and SIO0–SIO2 on-chip peripheral modules retain their states prior to halting, as do DMAC, DSP, and SIO0–SIO2 registers. The external pins of the FRT, SCIF1–2, and TPU are reset and all their registers are initialized. An on-chip peripheral module corresponding to a module standby bit must not be switched to the module standby state while it is running. Also, interrupts from a module placed in the module stop state should be disabled. 21.5.2 Clearing the Module Standby Function Clear the module standby function by clearing the MSTP11–MSTP3, MSTP1 bits, or by a poweron reset or manual reset. Rev. 2.00 Mar 09, 2006 page 812 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 shows the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage (internal) VCC –0.3 to +4.2 V Power supply voltage (5 V I/O) PVCC –0.3 to +7.0 V Input voltage (excluding 5 V I/O) Vin –0.3 to Vcc +0.3 V Input voltage (5 V I/O) Vin –0.3 to PVcc +0.3 V Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes: 1. Permanent damage to the chip may result if the maximum ratings are exceeded. 2. When powering on, turn on the 5 V I/O power supply (PVCC) after, or at the same time as, the internal power supply (VCC). When powering off, cut Vcc after, or at the same time as, PVCC. Rev. 2.00 Mar 09, 2006 page 813 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.2 DC Characteristics Tables 22.2 and 22.3 show the DC characteristics. Table 22.2 DC Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Input high voltage Input low voltage Symbol Min V VCC × 0.9 — VCC + 0.3 Both 3.3 V and 5 V 2.6 — PVCC + 0.3 V EXTAL, CKIO VCC × 0.9 — VCC + 0.3 V Other input pins VCC × 0.7 — VCC + 0.3 V RES, NMI, VIL MD4 to MD0, TRST, CKPREQ/CKM –0.3 — VCC × 0.1 V PB14/RXD1, PB5/SRS1/RXD2 –0.3 — 0.8 V – — — 0.8 V + 4.0 — — V PVCC = 5 V ±0.5 V 2.6 — — V Other than above VT – VT 0.3 — — V lin — 1.0 µA VT VT + VT + Input leakage current Unit Test Conditions RES, NMI, VIH MD4 to MD0, TRST, CKPREQ/CKM Other input pins Schmitt trigger input voltage Typ Max All input pins – — Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V Three-state All I/O and output leakage pins (off status) current lTSI Output high voltage VOH Both 3.3 V and 5 V — 1.0 µA Vin = 0.5 to VCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V Other output pins Output low Both 3.3 V and 5 V voltage Other output pins — VOL Rev. 2.00 Mar 09, 2006 page 814 of 906 REJ09B0292-0200 PVCC – 0.7 — — V IOH = –200 µA VCC – 0.5 — — V IOH = –200 µA VCC – 1.0 — — V IOH = –1 mA — — 0.6 V IOL = 1.6 mA — — 0.4 V IOL = 1.6 mA Section 22 Electrical Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Pin CAP1, CAP2 capacitance Other input pins Cin Typ Max Unit Test Conditions — — 40 pF — — 15 pF Current Normal operation dissipation lcc — — 350 mA 3.6 V, CPU operating clock = 62.5 MHz, DMAC used — — 300 mA 3.6 V, CPU operating clock = 62.5 MHz, DMAC not used Sleep mode — — 250 mA 3.6 V, CPU operating clock = 62.5 MHz, peripheral modules not used Standby mode — — 990 µA Ta = 25°C Note: Do not leave the PLLVcc and PLLVss pins open when the PLL circuit is not used. Connect the PLLVcc pin to Vcc and the PLLVss pin to Vss. Table 22.3 Permissible Output Currents Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max Unit Permissible output low current (per pin) IOL — — 2.0 mA Permissible output low current (total) ∑IOL — — 80 mA Permissible output high current (per pin) –IOH — — 2.0 mA Permissible output high current (total) ∑(–IOH) — — 25 mA Note: To protect chip reliability, do not exceed the output current values in table 22.3. Rev. 2.00 Mar 09, 2006 page 815 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3 AC Characteristics In principle, input is synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 22.4 Maximum Operating Frequencies Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Operating frequency Symbol Min Typ Max Unit Notes f 1 — 62.5 MHz tIcyc External bus (SDRAM not used) 1 — 31.25 tEcyc External bus (SDRAM used) 1 — 62.5 tEcyc Peripheral modules 1 — 31.25 tPcyc CPU, DSP Rev. 2.00 Mar 09, 2006 page 816 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.1 Clock Timing Table 22.5 Clock Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure EXTAL clock input frequency fEX 1 31.25 MHz 22.1 EXTAL clock input cycle time tEXcyc 1000 ns EXTAL clock input low-level pulse width tEXL 32 1 2 8* , 12* — ns EXTAL clock input high-level pulse width tEXH 8* , 12* — ns EXTAL clock input rise time tEXR — 4 ns EXTAL clock input fall time tEXF — 4 ns CKIO clock input frequency fCKI 1 31.25 MHz CKIO clock input cycle time tCKIcyc 1000 ns CKIO clock input low-level pulse width tCKIL 32 3 4 8* , 12* — ns CKIO clock input high-level pulse width tCKIH 3 4 8* , 12* — ns CKIO clock input rise time tCKIR — 4 ns CKIO clock input fall time tCKIF 4 ns 1 2 22.2 CKIO clock output frequency fOP — 5 6 1* , 8* CKIO clock output cycle time tcyc 16 1000* , 6 125* ns CKIO clock output low-level pulse width tCKOL 3 — ns CKIO clock output high-level pulse width tCKOH 3 — ns CKIO clock rise time tCKOR — 5 ns CKIO clock fall time tCKOF — 5 ns Power-on oscillation stabilization time tOSC1 10 — ms 22.4 Standby recovery oscillation stabilization time 1 tOSC2 10 — ms 22.5 Standby recovery oscillation stabilization time 2 tOSC3 10 — ms 22.6 PLL synchronization stabilization time tPLL 1 — ms 22.7 Notes: 1. 2. 3. 4. 5. 6. 62.5 MHz 5 22.3 When PLL circuit 2 is operating When PLL circuit 2 is not used When PLL circuit 1 is operating When PLL circuit 1 is not used When PLL circuit 1 and 2 are not used When PLL circuit 1 or 2 is operating Rev. 2.00 Mar 09, 2006 page 817 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics tEXcyc tEXH EXTAL* (input) VIH 1/2 VCC tEXL VIH VIL VIL tEXF VIH 1/2 VCC tEXR Note: * When clock is input from EXTAL pin Figure 22.1 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCC VIH tCKIL VIH VIL VIL VIH 1/2 VCC tCKIR tCKIF Figure 22.2 CKIO Clock Input Timing tcyc tCKOH CKIO (output) 1/2VCC VOH tCKOL VOH VOL VOL tCKOF Figure 22.3 CKIO Clock Output Timing Rev. 2.00 Mar 09, 2006 page 818 of 906 REJ09B0292-0200 VOH 1/2VCC tCKOR Section 22 Electrical Characteristics Stable oscillation CKIO, internal clock Vcc min Vcc tRESW tOSC1 RES Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.4 Power-On Oscillation Stabilization Time at Power-On Stable oscillation Standby CKIO, internal clock tRESW tOSC2 RES Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.5 Oscillation Stabilization Time after Standby Recovery (Recovery by RES) RES Rev. 2.00 Mar 09, 2006 page 819 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Stable oscillation Standby CKIO, internal clock tOSC3 NMI Note: Oscillation stabilization time when using on-chip crystal oscillator Figure 22.6 Oscillation Stabilization Time after Standby Recovery (Recovery by NMI) Stable oscillation Change of oscillation frequency Stable oscillation EXTAL or CKIO PLL synchronization tPLL Internal clock Figure 22.7 PLL Synchronization Stabilization Time Rev. 2.00 Mar 09, 2006 page 820 of 906 REJ09B0292-0200 PLL synchronization Section 22 Electrical Characteristics 22.3.2 Control Signal Timing Table 22.6 Control Signal Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure RES rise and fall time tRESr, tRESf — 200 ns 22.8 RES pulse width tRESW 20 — tPcyc NMI reset setup time tNMIRS tPcyc + 10 — ns NMI reset hold time tNMIRH tPcyc + 10 — ns NMI rise and fall time RES setup time* tNMIr, tNMIf — 200 ns tRESS 3tEcyc + 40 — ns NMI setup time* tNMIS 40 — ns IRL3–IRL0 setup time* tIRLS 30 — ns NMI hold time tNMIH 20 — ns IRL3–IRL0 hold time* tIRLH 20 — ns BRLS setup time tBLSS 10 — ns BRLS hold time tBLSH 5 — ns BGR delay time tBGRD — 15 ns Bus tri-state delay time tBOFF 0 35 ns Bus buffer on time tBON 0 35 ns 22.9 22.10 Note: * The RES, NMI, and IRL3–IRL0 signals are asynchronous inputs. If the setup times shown here are observed, a transition is judged to have occurred at the fall of the clock; if the setup times cannot be observed, recognition may be delayed until the next fall of the clock. tRESf VIH RES VIH VIL tNMIr tNMIf NMI tRESr tNMIRS VIL tNMIRH tRESW VIH VIH VIL VIL Figure 22.8 Reset Input Timing Rev. 2.00 Mar 09, 2006 page 821 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics CKIO tRESS VIH RES VIL tNMIH tNMIS VIH NMI tIRLH VIL tIRLS VIH IRL3–IRL0 VIL Figure 22.9 Interrupt Signal Input Timing CKIO tBLSH tBLSS tBLSH BRLS (input) tBLSS tBGRD tBGRD BGR (output) tBOFF RD, RD/WR, RAS, CAS, CSn, WEn, BS, IVECF tBOFF A24–A0, D31–D0 Figure 22.10 Bus Release Timing Rev. 2.00 Mar 09, 2006 page 822 of 906 REJ09B0292-0200 tBON tBON Section 22 Electrical Characteristics 22.3.3 Bus Timing Table 22.7 PLL-On Bus Timing [Modes 0 and 4] (1) Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Address delay time tAD 1 Max Unit Figure 14 ns 22.11, 12, 15, 16, 18, 20, 22, 24 to 28, 30 to 34, 37 to 40, 42 to 44 BS delay time tBSD — 15 ns 22.11, 12, 15, 16, 18, 20, 22, 24, 25, 28, 30, 31, 33, 34, 39, 42 to 44 CS delay time 1 tCSD1 1 14 ns 22.11, 12, 15, 16, 18, 20, 22 to 25, 28, 30 to 34, 39, 41, 42 CS delay time 2 tCSD2 — 14 ns 22.11, 12, 33, 34, 39, 42 Read/write delay time tRWD 1 14 ns 22.11, 12, 15 ,16, 18, 20 to 22, 24, 25, 28 to 34, 39, 42 to 44 Read strobe delay time 1 tRSD1 — 14 ns 22.11, 12, 15, 16, 22, 30, 33, 34, 37, 39, 40, 42 to 44 Read data setup time 1 tRDS1 8 — ns 22.11, 33, 37, 42 to 44 Read data setup time 2 (EDO) tRDS2 8 — ns 22.39, 40 Read data setup time 3 (SDRAM) tRDS3 6.5 — ns 22.15, 16 Read data hold time 2 tRDH2 0 — ns 22.11, 42 Read data hold time 4 (SDRAM) tRDH4 2 — ns 22.15, 16 Read data hold time 5 (DRAM) tRDH5 0 — ns 22.33, 37 Read data hold time 6 (EDO) tRDH6 3 — ns 22.39, 40 Read data hold time 7 (EDO) tRDH7 1 — ns 22.39 Read data hold time 8 (interrupt vector) tRDH8 2 — ns 22.43, 44 Write enable delay time 1 tWED1 — 14 ns 22.11, 12 Write data delay time 1 (except Eø: Iø = 1:1) tWDD1 — 22 ns 22.12, 22, 24, 26, 34, 38 Write data delay time 2 (Eø: Iø = 1:1) tWDD2 — 12 ns 22.25, 27 Write data hold time 1 tWDH1 2 — ns 22.12, 22, 24 to 27, 34, 38 Data buffer on time tDON — 15 ns 22.12, 22, 24, 25, 34 Data buffer off time tDOF — 15 ns 22.12, 22, 24, 25, 34 Rev. 2.00 Mar 09, 2006 page 823 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min DACK delay time 1 tDACD1 — DACK delay time 2 tDACD2 — 14 ns 22.11, 12, 33, 34, 37 to 40, 42 WAIT setup time tWTS 10 — ns 22.13, 14, 35, 36, 42 to 45 WAIT hold time tWTH 5 — ns 22.13, 14, 35, 36, 42 to 45 RAS delay time 1 (SDRAM) tRASD1 1 14 ns 22.15 to 18, 20 to 25, 28 to 32 RAS delay time 2 (DRAM, EDO) tRASD2 — 14 ns 22.33, 34, 39, 41 RAS delay time 3 (EDO) tRASD3 — 14 ns 22.39 CAS delay time 1 (SDRAM) tCASD1 1 14 ns 22.15, 16, 17, 18, 22 to 28, 30 to 32, 42 CAS delay time 2 (DRAM) tCASD2 — 14 ns 22.33, 34, 37 to 41 DQM delay time tDQMD 1 14 ns 22.15, 16, 18 to 20, 22, 24 to 29 CKE delay time tCKED 1 14 ns 22.32 OE delay time 1 tOED1 — 14 ns 22.39 OE delay time 2 tOED2 — 14 ns 22.39 IVECF delay time tIVD — 15 ns 22.43, 44 Row address setup time tASR 0 — ns 22.33, 34, 39 Column address setup time tASC 0 — ns 22.33, 34, 37, 38, 39 Data input setup time tDS 0 — ns 22.34, 38 Read/write address setup time tAS 0 — ns 22.11, 12 REFOUT delay time tREFOD — 15 ns 22.46 Rev. 2.00 Mar 09, 2006 page 824 of 906 REJ09B0292-0200 Max Unit Figure 14 ns 22.11, 12, 15, 18, 20, 22, 24, 25, 28, 33, 34, 37 to 40, 42 Section 22 Electrical Characteristics Table 22.7 PLL-On Bus Timing [Modes 0 and 4] (2) Conditions: VCC = PLLVCC = 3.3 V ±5%, PVCC = 5.0 V ±5%/3.3 V ±5%, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –5 to +70°C, SDRAM bus cycle Item Symbol Min Max Unit Figure Read data setup time 3 (SDRAM) tRDS3 6.5 — ns 22.15, 16 Read data hold time 4 (SDRAM) tRDH4 1.5 — ns 22.15, 16 Write data delay time 2 (Eø: Iø = 1:1) tWDD2 — 9.5 ns 22.25, 27 Write data hold time 1 tWDH1 2 — ns 22.25, 27 Address delay time tAD 4 11 ns 22.15, 16, 18, 20, 22, 24, 25, 26, 27, 28, 30, 31, 32 CS delay time 1 tCSD1 2.5 9.5 ns 22.15, 16, 18, 20, 22, 23, 24, 25, 28, 30, 31, 32 Read/write delay time tRWD 2.5 9.5 ns 22.15, 16, 18, 20, 21, 22, 24, 25, 28, 29, 30, 31, 32 DQM delay time tDQMD 2.5 9.5 ns 22.15, 16, 18, 19, 20, 22, 24, 25, 26, 27, 28, 29 RAS delay time 1 (SDRAM) tRASD1 2.5 9.5 ns 22.15, 16, 17, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 CAS delay time 1 (SDRAM) tCASD1 2.5 9.5 ns 22.15, 16, 17, 18, 22, 23, 24, 25, 26, 27, 28, 30, 31, 32 CKE delay time tCKED 2.5 9.5 ns 22.32 Rev. 2.00 Mar 09, 2006 page 825 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 T2 CKIO tAD tAD tAS A24–A0 tBSD tBSD BS tCSD2 tCSD1 CSn tRWD tRWD RD/WR tRSD1 tRSD1 RD WEn ⋅ DQMxx tWED1 tWED1 tRDH2*1 tRDS1 D31–D0 tDACD1 tDACD2 DACKn*2 WAIT RAS CAS ⋅ OE CKE Notes: 1. tRDH2 is measured from the rise of CSn or RD, whichever comes first. 2. DACKn waveform when active-high is specified Figure 22.11 Basic Read Cycle (No Wait) Rev. 2.00 Mar 09, 2006 page 826 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 T2 CKIO tAD tAD A24–A0 tBSD tAS tBSD BS tCSD2 tCSD1 CSn tRWD tRWD RD/WR tRSD1 tRSD1 RD tWED1 tWED1 WEn ⋅ DQMxx tWDD1 tDOF tWDH1 tDON D31–D0 tDACD1 tDACD2 DACKn* WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.12 Basic Write Cycle (No Wait) Rev. 2.00 Mar 09, 2006 page 827 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 Tw T2 CKIO A24–A0 BS CSn RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn* tWTS tWTH WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.13 Basic Bus Cycle (1 Wait Cycle) Rev. 2.00 Mar 09, 2006 page 828 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 Tw Twx T2 CKIO A24–A0 BS CSn RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn* tWTS tWTH tWTS tWTH WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.14 Basic Bus Cycle (External Wait Input) Rev. 2.00 Mar 09, 2006 page 829 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tr Tc Td1 Td2 Td3 Td4 Tde CKIO tAD tAD Address upper bits tAD Address lower bits tBSD tBSD BS tCSD1 tCSD1 CSn tRWD tRWD RD/WR tRSD1 RD WEn ⋅ DQMxx tDQMD tDQMD tRDS3 tRDH4 tRDS3 tRDH4 tRDS3 tRDH4 tRDS3 tRDH4 D31–D0 tDACD1 tDACD1 DACKn*2 WAIT tRASD1 tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS · OE tCASD1 *1 CKE Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.15 Synchronous DRAM Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, Burst = 4) Rev. 2.00 Mar 09, 2006 page 830 of 906 REJ09B0292-0200 tCASD1 Section 22 Electrical Characteristics Tr Tc Td1 Td2 Td3 Td4 Tde CKIO tAD tAD Address upper bits tAD Address lower bits tBSD tBSD tCSD1 tCSD1 BS CSn tRWD tRWD RD/WR tRSD1 RD tDQMD tDQMD WEn ⋅ DQMxx tRDS3 tDQMD tRDH4 D31–D0 DACKn*2 WAIT tRASD1 tRASD1 tRASD1 RAS CAS ⋅ OE tCASD1 tCASD1 tCASD1 tCASD1 *1 CKE Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.16 Synchronous DRAM Single Read Bus Cycle (RCD = 1 Cycle, CAS Latency = 1 Cycle, Burst = 4) Rev. 2.00 Mar 09, 2006 page 831 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tr Trw Tc Tw tCASD1 tCASD1 Td1 Td2 Td3 Td4 TdE CKIO Address upper bits Address lower bits BS CSn RD/WR RD ⋅ WEn DQMxx D31–D0 DACKn*2 WAIT tRASD1 tRASD1 RAS CAS–OE *1 CKE Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.17 Synchronous DRAM Read Bus Cycle (RCD = 2 Cycles, CAS Latency = 2 Cycles, Burst = 4) Rev. 2.00 Mar 09, 2006 page 832 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tnop Tc Td1 Td2 Td3 Td4 Tde CKIO tAD Address upper bits Address lower bits tBSD BS tCSD1 CSn tRWD RD/WR RD tDQMD WEn ⋅ DQMxx D31–D0 tDACD1 DACKn* WAIT tRASD1 RAS tCASD1 tCASD1 tCASD1 tCASD1 CAS CKE Note: * DACKn waveform when active-high is specified Figure 22.18 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 1 Cycle) Rev. 2.00 Mar 09, 2006 page 833 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics TC TW Td1 Td2 Td3 Td4 Tde CKIO Address upper bits Address lower bits BS CSn RD/WR RD tDQMD WEn ⋅ DQMxx D31–D0 DACKn* WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.19 Synchronous DRAM Read Bus Cycle (Bank Active, Same Row Access, CAS Latency = 2 Cycles) Rev. 2.00 Mar 09, 2006 page 834 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc Td1 Td2 Td3 Td4 Tde CKIO tAD Address upper bits tAD Address lower bits tBSD BS tCSD1 CSn tRWD tRWD RD/WR RD tDQMD WEn ⋅ DQMxx D31–D0 tDACD1 DACKn* WAIT tRASD1 tRASD1 RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.20 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle, CAS Latency = 1 Cycle) Rev. 2.00 Mar 09, 2006 page 835 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tpw Tr Tc Td1 Tde CKIO Address upper bits Address lower bits BS CSn tRWD RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn* WAIT tRASD1 tRASD1 RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.21 Synchronous DRAM Read Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 1 Cycle, CAS Latency = 1 Cycle) Rev. 2.00 Mar 09, 2006 page 836 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tr Tc Tap CKIO tAD tAD Address upper bits tAD Address lower bits tBSD tBSD tCSD1 tCSD1 BS tCSD1 CSn *1 tRWD tRWD tRWD RD/WR tRSD1 RD tDQMD tDQMD tWDD1 tDON tDOF tWDH1 tDACD1 tDACD1 WEn ⋅ DQMxx D31–D0 tDACD1 *1 DACKn*2 WAIT tRASD1 tRASD1 tRASD1 tRASD1 tCASD1 tCASD1 tCASD1 RAS CAS ⋅ OE *1 CKE Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.22 Synchronous DRAM Write Bus Cycle (RASD = 0, RCD = 1 Cycle, TRWL = 1 Cycle) Rev. 2.00 Mar 09, 2006 page 837 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tr Trw Tc Trwl Tap CKIO Address upper bits Address lower bits BS tCSD1 CSn RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn*2 WAIT tRASD1 RAS tRASD1 tCASD1 CAS ⋅ OE *1 *1 CKE Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is accessed. 2. DACKn waveform when active-high is specified Figure 22.23 Synchronous DRAM Write Bus Cycle (RASD = 0, RCD = 2 Cycles, TRWL = 2 Cycles) Rev. 2.00 Mar 09, 2006 page 838 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tc CKIO tAD tAD tBSD tBSD tCSD1 tCSD1 tRWD tRWD tDQMD tDQMD Address upper bits Address lower bits BS CSn RD/WR RD WEn ⋅ DQMxx tWDD1 tDOF tDON tWDH1 D31–D0 tDACD1 tDACD1 DACKn* WAIT tRASD1 RAS tCASD1 tCASD1 CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.24 Synchronous DRAM Write Bus Cycle (Bank Active, Same Row Access, Iφ φ:Eφ φ other than 1:1) Rev. 2.00 Mar 09, 2006 page 839 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tc CKIO tAD tAD tBSD tBSD tCSD1 tCSD1 tRWD tRWD tDQMD tDQMD tWDD2 tDOF tDON tWDH1 Address upper bits Address lower bits BS CSn RD/WR RD WEn ⋅ DQMxx D31–D0 tDACD1 tDACD1 DACKn* WAIT tRASD1 RAS tCASD1 tCASD1 CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.25 Synchronous DRAM Write Cycle (Bank Active, Same Row Access, Iφ φ:Eφ φ = 1:1) Rev. 2.00 Mar 09, 2006 page 840 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tc Tc CKIO tAD Address upper bits Address lower bits BS CSn RD/WR RD tDQMD WEn ⋅ DQMxx tWDD1 tWDH1 D31–D0 DACKn* WAIT RAS tCASD1 tCASD1 CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.26 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Iφ φ:Eφ φ other than 1:1) Rev. 2.00 Mar 09, 2006 page 841 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tc Tc CKIO tAD Address upper bits Address lower bits BS CSn RD/WR RD tDQMD WEn ⋅ DQMxx tWDD2 tWDH1 D31–D0 DACKn* WAIT RAS tCASD1 tCASD1 CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.27 Synchronous DRAM Continuous Write Cycle (Bank Active, Same Row Access, Iφ φ:Eφ φ = 1:1) Rev. 2.00 Mar 09, 2006 page 842 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc CKIO tAD Address upper bits Address lower bits tBSD BS tCSD1 CSn tRWD tRWD tDQMD tDQMD RD/WR RD WEn ⋅ DQMxx D31–D0 tDACD1 DACKn* WAIT tRASD1 RAS tCASD1 CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.28 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 1 Cycle, RCD = 1 Cycle) Rev. 2.00 Mar 09, 2006 page 843 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tpw Tr Trw Tc CKIO Address upper bits Address lower bits BS CSn tRWD RD/WR RD tDQMD WEn ⋅ DQMxx D31–D0 DACKn* WAIT tRASD1 tRASD1 RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.29 Synchronous DRAM Write Bus Cycle (Bank Active, Different Row Access, TRP = 2 Cycles, RCD = 2 Cycles) Rev. 2.00 Mar 09, 2006 page 844 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Trr Trc1 Trc2 Tre CKIO Address upper bits tAD tAD Address lower bits tBSD BS tCSD1 tCSD1 CSn tRWD tRWD RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn WAIT tRASD1 tRASD1 tCASD1 tCASD1 tRSD1 RAS CAS ⋅ OE CKE Note: An auto-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP. Figure 22.30 Synchronous DRAM Auto-Refresh Cycle (TRAS = 4 Cycles) Rev. 2.00 Mar 09, 2006 page 845 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Trr Trc1 Trc2 Tre CKIO Address upper bits tAD tAD Address lower bits tBSD BS tCSD1 CSn tRWD tRWD RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn WAIT tRASD1 RAS tCASD1 CAS ⋅ OE CKE Figure 22.31 Synchronous DRAM Auto-Refresh Cycle (Shown from Precharge Cycle, TRP = 1 Cycle, TRAS = 4 Cycles) Rev. 2.00 Mar 09, 2006 page 846 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Trr Trc1 Trc2 Tre Trc1 Tre CKIO Address upper bits tAD tAD Address lower bits BS tCSD1 tCSD1 CSn tRWD RD/WR RD WEn ⋅ DQMxx D31–D0 DACKn WAIT tRASD1 tRASD1 tRASD1 RAS CAS ⋅ OE tCASD1 tCASD1 tCKED tCKED CKE Note: A self-refresh cycle is always preceded by a precharge cycle. The number of cycles between the two is determined by the number of cycles specified by TRP. Figure 22.32 Synchronous DRAM Self-Refresh Cycle (TRAS = 3) Rev. 2.00 Mar 09, 2006 page 847 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 CKIO tAD tAD Address upper bits tASR tAD Address lower bits tBSD BS tCSD1 tCSD2 CSn tRWD tRWD RD/WR tRSD1 tRSD1 tRSD1 RD tCASD2 tCASD2 tCASD2 CASxx tRDH5*1 tASC tRDS1 D31–D0 tDACD1 tDACD2 DACKn*2 WAIT tRASD2 tRASD2 tRASD2 RAS CAS ⋅ OE CKE Notes: 1. tRDH5 is measured from the rise of RD or CASxx, whichever comes first. 2. DACKn waveform when active-high is specified Figure 22.33 DRAM Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 848 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 CKIO tAD tAD Address upper bits tASR tAD Address lower bits tBSD BS tCSD2 tCSD1 CSn tRWD tRWD RD/WR tRSD1 RD tASC tCASD2 tCASD2 CASxx tCASD2 tWDD1 tDON tDOF tWDH1 tDS D31–D0 tDACD2 tDACD1 DACKn* WAIT tRASD2 tRASD2 tRASD2 RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.34 DRAM Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 849 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tpw Tr Trw Tc1 Tw Tc2 CKIO Address upper bits Address lower bits BS CSn RD/WR RD CASxx D31–D0 DACKn* tWTS WAIT RAS CAS OE ⋅ CKE Note: * DACKn waveform when active-high is specified Figure 22.35 DRAM Bus Cycle (TRP = 2 Cycles, RCD = 2 Cycles, 1 Wait) Rev. 2.00 Mar 09, 2006 page 850 of 906 REJ09B0292-0200 tWTH Section 22 Electrical Characteristics Tp Tr Tc1 Tw Twx Tc2 CKIO Address upper bits Address lower bits BS CSn RD/WR RD CASxx D31–D0 DACKn* tWTS tWTH tWTS tWTH WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.36 DRAM Bus Cycle (TRP = 1 Cycle, RCD = 1 Cycle, External Wait Input) Rev. 2.00 Mar 09, 2006 page 851 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CKIO Address upper bits tAD tAD Address lower bits BS CSn RD/WR tRSD1 tRSD1 RD tCASD2 tCASD2 CASxx tRDH5*1 tASC tASC tRDH5*1 tRDS1 tRDS1 D31–D0 tDACD2 tDACD1 DACKn*2 WAIT RAS CAS ⋅ OE CKE Notes: 1. tRDH5 is measured from the rise of RD or CASxx, whichever comes first. 2. DACKn waveform when active-high is specified Figure 22.37 DRAM Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 852 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CKIO Address upper bits tAD Address lower bits BS CSn RD/WR RD tASC tCASD2 tCASD2 CASxx tWDD1 tDS tWDH1 tDS D31–D0 tDACD1 tDACD2 DACKn* WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.38 DRAM Burst Write Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 853 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 CKIO tAD tAD Address upper bits tASR tAD Address lower bits tBSD BS tCSD1 tCSD2 CSn tRWD tRWD RD/WR tRSD1 tRSD1 tRSD1 RD tCASD2 tCASD2 tCASD2 CASxx tASC tRDS2 tRDH6 D31–D0 tDACD1 tRDH7*2 tDACD2 DACKn*1 WAIT tRASD2 tRASD2 tRASD3 tOED1 tOED2 RAS CAS ⋅ OE tOED1 CKE Notes: 1. DACKn waveform when active-high is specified 2. tRDH7 is measured from the rise of RAS or CAS · OE, whichever comes first. Figure 22.39 EDO Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 854 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 CKIO Address upper bits tAD Address lower bits BS CSn RD/WR tRSD1 tRSD1 RD tCASD2 tCASD2 CASxx tASC tRDS2 tRDH6 tRDS2 tRDH6 D31–D0 tDACD1 tDACD2 DACKn* WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.40 EDO Burst Read Cycle (TRP = 1 Cycle, RCD = 1 Cycle, No Wait) Rev. 2.00 Mar 09, 2006 page 855 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Tp Trr Trc1 Trc2 Tre CKIO Address upper bits Address lower bits BS tCSD1 tCSD1 CSn RD/WR RD tCASD2 tCASD2 tCASD2 CASxx D31–D0 DACKn WAIT tRASD2 tRASD2 tRASD2 RAS CAS ⋅ OE CKE Figure 22.41 DRAM CAS-Before-RAS RAS Refresh Cycle CAS (TRP = 1 Cycle, TRAS = 2 Cycles) Rev. 2.00 Mar 09, 2006 page 856 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 TW T2 TW T2 CKIO tAD tAD tAD A24–A0 tBSD tBSD tBSD tBSD BS tCSD1 tCSD2 CSn tRWD tRWD RD/WR tRSD1 tRSD1 tRSD1 tRSD1 RD tCASD1 tCASD1 CASxx tRDH2 tRDH2 tRDS1 tRDS1 D31–D0 tDACD1 tDACD1 tDACD2 tDACD2 DACKn* tWTS tWTH tWTS tWTH WAIT RAS CAS ⋅ OE CKE Note: * DACKn waveform when active-high is specified Figure 22.42 Burst ROM Read Cycle (Wait = 1) Rev. 2.00 Mar 09, 2006 page 857 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 T2 T3 T4 CKIO tAD tAD A3–A0 tBSD tBSD BS tIVD tIVD IVECF tRWD tRWD RD/WR tRSD1 tRSD1 RD tRDH8 tRSD1 D7–D0 tWTS tWTH WAIT Figure 22.43 Interrupt Vector Fetch Cycle (No Wait, Iφ φ:Eφ φ = 1:1) Rev. 2.00 Mar 09, 2006 page 858 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics T1 T2 CKIO tAD tAD A3–A0 tBSD tBSD BS tIVD tIVD IVECF tRWD RD/WR tRSD1 tRSD1 RD tRSD1 tRDH8 D7–D0 tWTS tWTH WAIT Figure 22.44 Interrupt Vector Fetch Cycle (No Wait, Iφ φ:Eφ φ other than 1:1) Rev. 2.00 Mar 09, 2006 page 859 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics TW T1 T2 CKIO A3–A0 BS IVECF RD/WR RD D7–D0 tWTS tWTH tWTS tWTH WAIT Figure 22.45 Interrupt Vector Fetch Cycle (External Wait Input, Iφ φ:Eφ φ other than 1:1) CKIO tREFOD REFOUT Figure 22.46 REFOUT Delay Time Rev. 2.00 Mar 09, 2006 page 860 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.4 Direct Memory Access Controller Timing Table 22.8 Direct Memory Access Controller Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure DREQ0, DREQ1 setup time tDRQS 10 — ns 22.47 DREQ0, DREQ1 hold time tDRQH 5 — ns CKIO tDRQS tDRQH DREQ0, DREQ1 Figure 22.47 DREQ0, DREQ1 Input Timing Rev. 2.00 Mar 09, 2006 page 861 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.5 Free-Running Timer Timing Table 22.9 Free-Running Timer Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure Output compare output delay time tFOCD — 100 ns 22.48, 22.49 Input capture input setup time (tEcyc:tPcyc = 1:1) tFICS 50 — ns 22.48 Input capture input setup time (tEcyc:tPcyc = 1:2) tFICS tcyc + 50 — ns 22.49 Input capture input setup time (tEcyc:tPcyc = 1:4) tFICS 3tcyc + 50 — ns 22.49 Input capture input hold time tFICH 50 — ns 22.48, 22.49 Timer clock input setup time (tEcyc:tPcyc = 1:1) tFCKS 50 — ns 22.50 Timer clock input setup time (tEcyc:tPcyc = 1:2) tFCKS tcyc + 50 — ns 22.51 Timer clock input setup time (tEcyc:tPcyc = 1:4) tFCKS 3tcyc + 50 — ns 22.51 Timer clock pulse width (single edge specified) tFCKWH 4.5 — tPcyc 22.50, 22.51 Timer clock pulse width (both edges specified) tFCKWL 8.5 — tPcyc CKIO tFOCD FTOA, FTOB tFICS FTI Figure 22.48 FRT Input/Output Timing (tEcyc:tPcyc = 1:1) Rev. 2.00 Mar 09, 2006 page 862 of 906 REJ09B0292-0200 tFICH Section 22 Electrical Characteristics CKIO tFOCD FTOA, FTOB tFICS tFICH FTI Figure 22.49 FRT Input/Output Timing (tEcyc:tPcyc other than 1:1) CKIO tFCKS FTCI tFCKWH tFCKWL Figure 22.50 FRT Clock Input Timing (tEcyc:tPcyc = 1:1) CKIO tFCKS FTCI tFCKWL tFCKWH Figure 22.51 FRT Clock Input Timing (tEcyc:tPcyc other than 1:1) Rev. 2.00 Mar 09, 2006 page 863 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.6 Serial Communication Interface Timing Table 22.10 Serial Communication Interface Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure Input clock cycle tscyc 4 — tPcyc 22.52 Input clock cycle (synchronous mode) tscyc 6 — tPcyc 22.53 Input clock pulse width tSCKW 0.4 0.6 tcscyc 22.52 Transmit data delay time (synchronous mode) tTXD — 100 ns 22.53 Receive data setup time (synchronous mode) tRXS 100 — ns Receive data hold time (synchronous mode) tRXH 100 — ns RTS delay time tRTSD — 100 ns CTS setup time (synchronous mode) tCTSS 100 — ns CTS hold time (synchronous mode) tCTSH 100 — ns tSCKW SCK SCK1 SCK2 tscyc Figure 22.52 Input Clock Input/Output Timing Rev. 2.00 Mar 09, 2006 page 864 of 906 REJ09B0292-0200 22.54 Section 22 Electrical Characteristics tscyc SCK tTXD TxD (transmit data) tRXS tRXH RxD (receive data) Figure 22.53 SCI Input/Output Timing (Synchronous Mode) tscyc SCK1 tRTSD RTS tCTSS tCTSH CTS Figure 22.54 RTS and CTS Input/Output Timing Rev. 2.00 Mar 09, 2006 page 865 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics Table 22.11 16-Bit Timer-Pulse Unit Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure Timer output delay time tTOCD — 100 ns 22.55, 22.56 Timer input setup time (tEcyc:tPcyc = 1:1) tTICS 50 — ns Timer input setup time (tEcyc:tPcyc = 1:2) tTICS tcyc + 50 — ns Timer input setup time (tEcyc:tPcyc = 1:4) tTICS 3tcyc + 50 — ns Timer clock input setup time (tEcyc:tPcyc = 1:1) tTCKS 50 — ns Timer clock input setup time (tEcyc:tPcyc = 1:2) tTCKS tcyc + 50 — ns Timer clock input setup time (tEcyc:tPcyc = 1:4) tTCKS 3tcyc + 50 — ns Timer clock pulse width Single edge specified tTCKWH 1.5 — tcyc Both edges specified tTCKWL 2.5 — CKIO tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0–TIOCA2, TIOCB0–TIOCB2, TIOCC0, TIOCD0 Figure 22.55 TPU Input/Output Timing (tEcyc:tPcyc = 1:1) Rev. 2.00 Mar 09, 2006 page 866 of 906 REJ09B0292-0200 22.55, 22.56 22.57 Section 22 Electrical Characteristics CKIO tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0–TIOCA2, TIOCB0–TIOCB2, TIOCC0, TIOCD0 Figure 22.56 TPU Input/Output Timing (tEcyc:tPcyc other than 1:1) CKIO tTCKS tTCKS TCLKA–TCLKD tTCKWL tTCKWH Figure 22.57 TPU Clock Input Timing Rev. 2.00 Mar 09, 2006 page 867 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.7 Watchdog Timer Timing Table 22.12 Watchdog Timer Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD — 70 ns 22.58, 22.59 CKIO tWOVD tWOVD WDTOVF Figure 22.58 Watchdog Timer Output Timing (tEcyc:tPcyc = 1:1) CKIO tWOVD tWOVD WDTOVF Figure 22.59 Watchdog Timer Output Timing (tEcyc:tPcyc other than 1:1) Rev. 2.00 Mar 09, 2006 page 868 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.8 Serial I/O with FIFO / Serial I/O Timing Table 22.13 Serial I/O with FIFO / Serial I/O Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure SRCK0, STCK0 clock input cycle time tSFcyc — 2 tPcyc 22.60 SRCKn, STCKn clock input cycle time (n = 1 or 2) tSIcyc tPcyc or* 66.7 — ns SRCK0, STCK0 clock input low-level width tSFWL 0.4 × tSFcyc — ns SRCKn, STCKn clock input low-level width (n = 1 or 2) tWL 0.4 × tSIcyc — ns SRCK0, STCK0 clock input high-level width tSFWH 0.4 × tSFcyc — ns SRCKn, STCKn clock input high-level width tWH (n = 1 or 2) 0.4 × tSIcyc — ns SRS input setup time tRSS 15 — ns SRS input hold time tRSH 10 — ns SRXD input setup time tSRDS 15 — ns SRXD input hold time tSRDH 10 — ns STS0 input setup time tSFTSS 1 — tPcyc STSn input setup time (n = 1 or 2) tTSS 15 — ns STS input hold time tTSH 10 — ns STS output delay time tTSD 0 20 ns 22.63 STXD output delay time tTDD 0 20 ns 22.62, 22.63 22.61 22.62 Note: * Specified as tPcyc or 66.7, whichever is greater. Rev. 2.00 Mar 09, 2006 page 869 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics [SIOF] tSFcyc tSFWL STCK0, SRCK0 tSFWH [SIO] tSIcyc tWL STCKn, SRCKn tWH n = 1 or 2 Figure 22.60 SIOF / SIO Input Clock Timing SRCKn (input) tRSS tRSH tSRDS tSRDH SRSn (input) SRXDn (input) n = 0, 1, or 2 Figure 22.61 SIOF / SIO Receive Timing Rev. 2.00 Mar 09, 2006 page 870 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics [SIOF] STCK0 (input) tSFTSS tTSH STS0 (input) tTDD tTDD tTDD tTDD STXD0 (output) [SIO] STCKn (input) tTSS tTSH STSn (input) STXDn (output) n = 1, or 2 Figure 22.62 SIOF / SIO Transmit Timing (TMn = 0 Mode) STCKn (input) tTSD tTSD STSn (output) tTDD tTDD STXDn (output) n = 0, 1, or 2 Figure 22.63 SIOF / SIO Transmit Timing (TMn = 1 Mode) Rev. 2.00 Mar 09, 2006 page 871 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.9 User Debug Interface Timing Table 22.14 User Debug Interface Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure TCK clock input cycle time ttcyc tPcyc or* 66.7 ns — ns 22.64 TCK clock input high-level width tTCKH 0.4 0.6 ttcyc TCK clock input low-level width tTCKL 0.4 0.6 ttcyc TRST pulse width tTRSW 20 — ttcyc TRST setup time tTRSS 40 — ns TMS setup time tTMSS 30 — ns TMS hold time tTMSH 10 — ns TDI setup time tTDIS 30 — ns TDI hold time tTDIH 10 — ns TDO delay time tTDOD 0 30 ns Note: * Specified as tPcyc or 66.7, whichever is greater. ttcyc tTCKH tTCKL TCK Figure 22.64 H-UDI Clock Timing TCK tTRSS tTRSS TRST tTRSW Figure 22.65 H-UDI TRST Timing Rev. 2.00 Mar 09, 2006 page 872 of 906 REJ09B0292-0200 22.65 22.66 Section 22 Electrical Characteristics TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD tTDOD TDO Figure 22.66 H-UDI Input/Output Timing 22.3.10 I/O Port Timing Table 22.15 I/O Port Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Max Unit Figure Port output data delay time tPWD — 50 ns 22.67, 22.68 Port input data setup time (tEcyc:tPcyc = 1:1) tPRS 50 — ns 22.67 Port input data setup time (tEcyc:tPcyc = 1:2) tPRS tcyc + 50 — ns 22.68 Port input data setup time (tEcyc:tPcyc = 1:4) tPRS 3tcyc + 50 — ns Port input data hold time tPRH 50 — ns 22.67, 22.68 Rev. 2.00 Mar 09, 2006 page 873 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics CKIO tPRS PA0–PA13 PB0–PB15 (read) tPRH tPWD PA0–PA13 PB0–PB15 (write) Figure 22.67 I/O Port Input/Output Timing (tEcyc:tPcyc = 1:1) CKIO tPRS PA0–PA13 PB0–PB15 (read) tPRH tPWD PA0–PA13 PB0–PB15 (write) Figure 22.68 I/O Port Input/Output Timing (tEcyc:tPcyc ≠ 1:1) Rev. 2.00 Mar 09, 2006 page 874 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.3.11 Ethernet Controller Timing Table 22.16 Ethernet Controller Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max Unit Figure TX-CLK cycle time tTcyc 2.4 — — tcyc 22.69 TX-EN output delay time tTENd 3 — 20 ns ETXD[3:0] output delay time tETDd 3 — 20 ns CRS setup time tCRSs 10 — — ns CRS hold time tCRSh 10 — — ns COL setup time tCOLs 10 — — ns COL hold time tCOLh 10 — — ns RX-CLK cycle time tRcyc 2.4 — — tcyc RX-DV setup time tRDVs 10 — — ns RX-DV hold time tRDVh 3 — — ns ERXD[3:0] setup time tERDs 10 — — ns ERXD[3:0] hold time tERDh 3 — — ns RX-ER setup time tRERs 10 — — ns RX-ER hold time tRERh 3 — — ns MDIO setup time tMDIOs 10 — — ns MDIO hold time tMDIOh 10 — — ns MDIO output data hold time* tMDIOdh 5 — 18 ns 22.74 WOL output delay time tWOLd 1 — 18 ns 22.75 EXOUT output delay time tEXOUTd 1 — 28 ns 22.76 CAMSEN setup time tCAMs 10 — — ns 22.77 CAMSEN hold time tCAMh 3 — — ns 22.70 22.71 22.72 22.73 Note: * The user must ensure that the code satisfies this condition. Rev. 2.00 Mar 09, 2006 page 875 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics TX–CLK tTENd TX–EN tETDd Preamble ETXD[3:0] SFD DATA CRC TX–ER tCRSh tCRSs CRS COL Figure 22.69 MII Send Timing (Normal Operation) TX–CLK TX–EN Preamble ETXD[3:0] JAM TX–ER CRS tCOLs tCOLh COL Figure 22.70 MII Send Timing (Case of Conflict) RX–CLK tRDVs tRDVh tERDh RX–DV tERDs ERXD[3:0] Preamble SFD DATA CRC RX–ER Figure 22.71 MII Receive Timing (Normal Operation) Rev. 2.00 Mar 09, 2006 page 876 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics RX–CLK RX–DV ERXD[3:0] Preamble SFD DATA tRERs XXXX tRERh RX–ER Figure 22.72 MII Receive Timing (Case of Error) MDC tMDIOh tMDIOs MDIO Figure 22.73 MDIO Input Timing MDC tMDIOdh MDIO Figure 22.74 MDIO Output Timing RX–CLK tWOLd WOL Figure 22.75 WOL Output Timing CKIO tEXOUTd EXOUT Figure 22.76 EXOUT Output Timing Rev. 2.00 Mar 09, 2006 page 877 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics RX–CLK RX–DV Preamble ERXD[3:0] SFD Dest Address Source Address tCAMS DATA tCAMh CAMSEN Figure 22.77 CAMSEN Input Timing 22.3.12 STATS, BH, BH and BUSHiZ Signal Timing Table 22.17 STATS, BH, BH and BUSHiZ Signal Timing Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PVCC ≥ VCC, VSS = PVSS = PLLVSS = 0 V, Ta = –20 to +75°C Item Symbol Min Typ Max Unit Figure STAS1 and STAS0 output delay time tSTATd — — 16 ns 22.77 BH output rising edge delay time tBHNrd — — 16 ns 22.78 BH output falling edge delay time tBHNfd — — 16 ns BUSHiZ setup time tBHIZs 7 — — ns BUSHiZ hold time tBHIZh 8 — — ns Output delay time of target pins tBHIZd — — 16 ns 22.79 CKI0 Address CPU CPU E-DMAC E-DMAC E-DMAC E-DMAC G-DMAC CSn tSTATd STATS1, 0 Figure 22.78 STATS Output Timing Rev. 2.00 Mar 09, 2006 page 878 of 906 REJ09B0292-0200 G-DMAC G-DMAC G-DMAC Section 22 Electrical Characteristics CKI0 Read0 Address CPU G-DMAC tBHNfd Read1 Read2 Read3 G-DMAC G-DMAC G-DMAC Write0 Write1 G-DMAC G-DMAC Write2 Write3 G-DMAC G-DMAC CPU tBHNrd BH Figure 22.79 BH Output Timing CKI0 WAIT tBHIZs tBHIZh BUSHiZ tBHIZd Target Pins Figure 22.80 BUSHiZ Bus Timing Rev. 2.00 Mar 09, 2006 page 879 of 906 REJ09B0292-0200 Section 22 Electrical Characteristics 22.4 AC Characteristic Test Conditions The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (Vcc = 3.3 to 3.6 V) • Input pulse level: Vss to 3.0 V (Vss to Vcc for RES, TRST, EXTAL, CKIO, MD0–MD4, and NMI) • Input rise/fall time: 1 ns The output load circuit is shown in figure 22.81. IOL SH7616 output pin DUT output CL V VREF IOH CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is as follows: 30 pF: CKIO, A24–A0, D31–D0, BS, RD, CS4–CS0, DQMUU/WE3–DQMLL/WE0, CAS3–CAS0, RAS, CAS/OE, DACK1, DACK0 50 pF: All other pins IOL and IOH values are as shown in table 22.3, Permissible Output Currents. Figure 22.81 Output Load Circuit Rev. 2.00 Mar 09, 2006 page 880 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Appendix A On-Chip Peripheral Module Registers A.1 Addresses On-chip peripheral module register addresses and bit names are shown in the following table. 16bit registers and 32-bit registers are shown, respectively, in two and four lines of 8 bits. Address Register Name H'FFFFFC00 SIRDR Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SIOF H'FFFFFC01 H'FFFFFC02 SITDR H'FFFFFC03 H'FFFFFC04 SICTR H'FFFFFC05 H'FFFFFC06 SISTR H'FFFFFC07 H'FFFFFC08 SIFCR H'FFFFFC09 H'FFFFFC0A SIFDR H'FFFFFC0B H'FFFFFC0C — — — — — DMACE TCIE RCIE — TM SE DL TIE RIE TE RE — — — — — — TCD RCD — — — — TERR RERR TDRE RDRF — — — — TRMD LM RFRST TFRST RFWM3 RFWM2 RFWM1 RFWM0 TFWM3 TFWM2 TFWM1 TFWM0 — — — R4 R3 R2 R1 R0 — — — T4 T3 T2 T1 T0 SIRCDR H'FFFFFC0D H'FFFFFC0E SITCDR H'FFFFFC0F H'FFFFFC10 SIRDR1 SIO1 H'FFFFFC11 H'FFFFFC12 SITDR1 H'FFFFFC13 H'FFFFFC14 SICTR1 H'FFFFFC15 H'FFFFFC16 SISTR1 H'FFFFFC17 H'FFFFFC18 to H'FFFFFC1F — — — — — — — — — — TM SE DL TIE RIE TE RE — — — — — — — — — — — — TERR RERR TDRE RDRF — — — — — — — — — Rev. 2.00 Mar 09, 2006 page 881 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name H'FFFFFC20 SIRDR2 Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SIO2 H'FFFFFC21 H'FFFFFC22 SITDR2 H'FFFFFC23 H'FFFFFC24 SICTR2 — — — — — — — — — TM SE DE TIE RIE TE RE SISTR2 — — — — — — — — — — — — TERR RERR TDRE RDRF H'FFFFFC28 to H'FFFFFC3F — — — — — — — — — — H'FFFFFC40 TSTR — — — — — CST2 CST1 CST0 TPU H'FFFFFC41 TSYR — — — — — SYNC2 SYNC1 SYNC0 H'FFFFFC42 to H'FFFFFC4F — — — — — — — — — — H'FFFFFC50 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU H'FFFFFC25 H'FFFFFC26 H'FFFFFC27 H'FFFFFC51 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0 H'FFFFFC52 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FFFFFC53 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FFFFFC54 TIER0 — — — TCIEV TGIED TGIEC TGIEB TGIEA H'FFFFFC55 TSR0 — — — TCFV TGFD TGFC TGFB TGFA H'FFFFFC56 TCNT0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FFFFFC57 H'FFFFFC58 TGR0A H'FFFFFC59 H'FFFFFC5A TGR0B H'FFFFFC5B H'FFFFFC5C TGR0C H'FFFFFC5D H'FFFFFC5E TGR0D H'FFFFFC5F H'FFFFFC60 TCR1 H'FFFFFC61 TMDR1 — — — — MD3 MD2 MD1 MD0 H'FFFFFC62 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FFFFFC63 — — — — — — — — — H'FFFFFC64 TIER1 — — TCIEU TCIEV — — TGIEB TGIEA H'FFFFFC65 TSR1 TCFD — TCFU TCFV — — TGFB TGFA Rev. 2.00 Mar 09, 2006 page 882 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name H'FFFFFC66 TCNT1 Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TPU H'FFFFFC67 H'FFFFFC68 TGR1A H'FFFFFC69 H'FFFFFC6A TGR1B H'FFFFFC6B H'FFFFFC6C to H'FFFFFC6F — — — — H'FFFFFC70 TCR2 — CCLR1 CCLR0 H'FFFFFC71 TMDR2 — — — H'FFFFFC72 TIOR2 IOB3 IOB2 IOB1 H'FFFFFC73 — — — — H'FFFFFC74 TIER2 — — H'FFFFFC75 TSR2 TCFD H'FFFFFC76 TCNT2 — — — — — — — CKEG1 CKEG0 TPSC2 — MD3 MD2 TPSC1 TPSC0 TPU MD1 MD0 IOB0 IOA3 — — IOA2 IOA1 IOA0 — — TCIEU TCIEV — — — TGIEB TGIEA — TCFU TCFV — — TGFB TGFA — — — — — — — — PFC H'FFFFFC77 H'FFFFFC78 TGR2A H'FFFFFC79 H'FFFFFC7A TGR2B H'FFFFFC7B H'FFFFFC7C to H'FFFFFC7F — H'FFFFFC80 PACR H'FFFFFC81 H'FFFFFC82 PAIOR H'FFFFFC83 H'FFFFFC84 PADR H'FFFFFC85 — — PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD PA7MD PA6MD PA5MD PA1MD PA0MD — — PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR PA7IOR PA6IOR PA5IOR — — PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR — PA2DR PA1DR PA0DR — — — — — — — PA4MD PA4IOR PA3MD — PA2MD PA2IOR PA1IOR PA0IOR I/O port H'FFFFFC86 to H'FFFFFC87 — — H'FFFFFC88 PBCR PB15MD PB15MD PB14MD PB14MD PB13MD PB13MD PB12MD PB12MD PFC 1 0 1 0 1 0 1 0 H'FFFFFC89 H'FFFFFC8A H'FFFFFC8B — PB11MD PB11MD PB10MD PB10MD PB9MD1 PB9MD0 PB8MD1 PB8MD0 1 0 1 0 PBIOR PB15IOR PB14IOR PB13IOR PB12IOR PB11IOR PB10IOR PB9IOR PB8IOR PB7IOR PB0IOR PB6IOR PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR Rev. 2.00 Mar 09, 2006 page 883 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 0 Module H'FFFFFC8C PBDR PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR I/O port PB7DR PB6DR PB2DR PB0DR H'FFFFFC8D H'FFFFFC8E PBCR2 H'FFFFFC8F H'FFFFFC90 to H'FFFFFCAF Bit 5 PB5DR Bit 4 PB4DR Bit 3 PB3DR Bit 2 Bit 1 PB1DR PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PFC PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 — — — — — — — — — — H'FFFFF CB0 SDIR TS3 TS2 TS1 TS0 — — H'FFFFF CB1 — — — — — — — — H-UDI — — H'FFFFF CB2 SDSR — — — — — — — — H'FFFFF CB3 — — — — — — — SDTRF H'FFFFF CB8 — to H'FFFFF CBF — — — — — — — — — H'FFFF FCC0 SCBRR1 C/A CHR/ICK PE/ICK1 3 O/E/ICK1 STOP/ ICK0 MP CKS1 CKS0 SCIF1 H'FFFF FCC1 — — — — — — — — — H'FFFF FCC3 — — — — — — — — — H'FFFF FCC4 SCSCR1 TIE RIE TE RE MPIE — CKE1 CKE0 H'FFFF FCC5 — — — — — — — — — — — — — — — — — H'FFFF FCC8 SC1SSR1 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 H'FFFF FCC9 TEND TDFE BRK FER PER RDF DR H'FFFF FCCA SC2SSR1 TLM RLM N1 N0 MPB MPBT EI ORER H'FFFF FCCB — — — — — — — — H'FFFFF CB4 SDDRH H'FFFFF CB5 H'FFFFF CB6 SDDRL H'FFFFF CB7 H'FFFF FCC2 SCBRR1 H'FFFF FCC6 SCFTDR1 H'FFFF FCC7 — ER — H'FFFF FCCC SCFRDR1 H'FFFF FCCD — — — — — — — — — H'FFFF FCCE SCFCR1 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP H'FFFF FCCF — — — — — — — — — H'FFFF FCD0 SCFDR1 — — — T4 T3 T2 T1 T0 H'FFFF FCD1 — — — R4 R3 R2 R1 R0 Rev. 2.00 Mar 09, 2006 page 884 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FCD2 SCFER1 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 SCIF1 H'FFFF FCD3 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 H'FFFF FCD4 SCIMR1 IRMOD PSEL RIVS — — — — — H'FFFF FCD5 — to H'FFFF FCDF — — — — — — — — — H'FFFF FCE0 SCSMR2 C/A CHR/ICK PE/ICK2 3 O/E/ICK1 STOP/ ICK0 MP CKS1 CKS0 SCIF2 H'FFFF FCE1 — — — — — — — — — H'FFFF FCE3 — — — — — — — — — H'FFFF FCE4 SCSCR2 TIE RIE TE RE MPIE — CKE1 CKE0 H'FFFF FCE5 — — — — — — — — — H'FFFF FCE2 SCBRR2 H'FFFF FCE6 SCFTDR2 H'FFFF FCE7 — — — — — — — — H'FFFF FCE8 SC1SSR2 PER3 — PER2 PER1 PER0 FER3 FER2 FER1 FER0 H'FFFF FCE9 TEND TDFE BRK FER PER RDF DR H'FFFF FCEA SC2SSR2 TLM RLM N1 N0 MPB MPBT EI ORER H'FFFF FCEB — — — — — — — — — H'FFFF FCED — — — — — — — — — H'FFFF FCEE SCFCR2 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP H'FFFF FCEF — — — — — — — — — H'FFFF FCF0 SCFDR2 — — — T4 T3 T2 T1 T0 H'FFFF FCF1 — — — R4 R3 R2 R1 R0 H'FFFF FCF2 SCFER2 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 H'FFFF FCF3 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 H'FFFF FCF4 SCIMR2 IRMOD PSEL RIVS — — — — — H'FFFF FCF5 — to H'FFFF FCFF — — — — — — — — ER H'FFFF FCEC SCFRDR2 — Rev. 2.00 Mar 09, 2006 page 885 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD00 EDMR — — — — — — — — E-DMAC H'FFFF FD01 — — — — — — — — H'FFFF FD02 — — — — — — — — H'FFFF FD03 — — DL1 DL0 — — — SWR — — — — — — — — H'FFFF FD05 — — — — — — — — H'FFFF FD06 — — — — — — — — H'FFFF FD04 EDTRR H'FFFF FD07 — — — — — — — TR — — — — — — — — H'FFFF FD09 — — — — — — — — H'FFFF FD0A — — — — — — — — H'FFFF FD0B — — — — — — — RR H'FFFF FD08 EDRRR H'FFFF FD0C TDLAR TDLA31 TDLA30 TDLA29 TDLA28 TDLA27 TDLA26 TDLA25 TDLA24 H'FFFF FD0D TDLA23 TDLA22 TDLA21 TDLA20 TDLA19 TDLA18 TDLA17 TDLA16 H'FFFF FD0E TDLA15 TDLA14 TDLA13 TDLA12 TDLA11 TDLA10 TDLA9 TDLA8 H'FFFF FD0F TDLA7 TDLA6 TDLA5 TDLA4 TDLA3 TDLA2 TDLA1 TDLA0 RDLA31 RDLA30 RDLA29 RDLA28 RDLA27 RDLA26 RDLA25 RDLA24 H'FFFF FD11 RDLA23 RDLA22 RDLA21 RDLA20 RDLA19 RDLA18 RDLA17 RDLA16 H'FFFF FD12 RDLA15 RDLA14 RDLA13 RDLA12 RDLA11 RDLA10 RDLA9 RDLA8 H'FFFF FD13 RDLA7 RDLA6 RDLA5 RDLA4 RDLA3 RDLA2 RDLA1 RDLA0 — — — — — — — RFCOF H'FFFF FD15 — ECI TC TDE TFUF FR RDE RFOF H'FFFF FD16 — — — ITF CND DLC CD TRO H'FFFF FD10 H'FFFF FD14 RDLAR EESR H'FFFF FD17 RMAF — RFAR RRF RTLF RTSF PRE CERF — — — — — — — RFCOFIP H'FFFF FD19 — ECIIP TCIP TDEIP TFUFIP FRIP RDEIP RFOFIP H'FFFF FD1A — — — ITFIP CNDIP DLCIP CDIP TROIP H'FFFF FD1B RMAFIP — RFARIP RRFIP RTLFIP RTSFIP PREIP CERFIP H'FFFF FD1C TRSCER — — — — — — — — H'FFFF FD1D — — — — — — — — H'FFFF FD1E — — — ITFCE CNDCE DLCCE CDCE TROCE H'FFFF FD1F RMAFCE — H'FFFF FD18 EESIPR RFARCE RRFCE Rev. 2.00 Mar 09, 2006 page 886 of 906 REJ09B0292-0200 RTLFCE RTSFCE PRECE CERFCE Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD20 RMFCR — — — — — — — — E-DMAC — — — — — — — — H'FFFF FD21 H'FFFF FD22 MFC15 MFC14 MFC13 MFC12 MFC11 MFC10 MFC9 MFC8 H'FFFF FD23 MFC7 MFC6 MFC5 MFC4 MFC3 MFC2 MFC1 MFC0 — — — — — — — — H'FFFF FD25 — — — — — — — — H'FFFF FD26 — — — — — TFT10 TFT9 TFT8 TFT7 TFT6 TFT5 TFT4 TFT3 TFT2 TFT1 TFT0 — — — — — — — — H'FFFF FD29 — — — — — — — — H'FFFF FD2A — — — — — TFD2 TFD1 TFD0 H'FFFF FD2B — — — — — RFD2 RFD1 RFD0 H'FFFF FD2C RCR — — — — — — — — H'FFFF FD2D — — — — — — — — H'FFFF FD2E — — — — — — — — H'FFFF FD2F — — — — — — — RNC — — — — — — — — H'FFFF FD31 — — — — — — — — H'FFFF FD32 — — — — — — — — H'FFFF FD33 — — — — FEC AEC EDH — H'FFFF FD34 — to H'FFFF FD3F — — — — — — — — H'FFFF FD40 RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24 H'FFFF FD41 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16 H'FFFF FD42 RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA9 RBWA8 H'FFFF FD24 TFTR H'FFFF FD27 H'FFFF FD28 H'FFFF FD30 FDR EDOCR RBWAR H'FFFF FD43 RBWA7 RBWA6 RBWA5 RBWA4 RBWA3 RBWA2 RBWA1 RBWA0 RDFA31 RDFA30 RDFA29 RDFA28 RDFA27 RDFA26 RDFA25 RDFA24 H'FFFF FD45 RDFA23 RDFA22 RDFA21 RDFA20 RDFA19 RDFA18 RDFA17 RDFA16 H'FFFF FD46 RDFA15 RDFA14 RDFA13 RDFA12 RDFA11 RDFA10 RDFA9 RDFA8 H'FFFF FD47 RDFA7 RDFA6 RDFA5 RDFA4 RDFA3 RDFA2 RDFA1 RDFA0 H'FFFF FD44 RDFAR Rev. 2.00 Mar 09, 2006 page 887 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD48 — to H'FFFF FD4B — — — — — — — — E-DMAC H'FFFF FD4C TBRAR TBRA31 TBRA30 TBRA29 TBRA28 TBRA27 TBRA26 TBRA25 TBRA24 H'FFFF FD4D TBRA23 TBRA22 TBRA21 TBRA20 TBRA19 TBRA18 TBRA17 TBRA16 H'FFFF FD4E TBRA15 TBRA14 TBRA13 TBRA12 TBRA11 TBRA10 TBRA9 TBRA8 H'FFFF FD4F TBRA7 TBRA6 TBRA5 TBRA4 TBRA3 TBRA2 TBRA1 TBRA0 TDFA31 TDFA30 TDFA29 TDFA28 TDFA27 TDFA26 TDFA25 TDFA24 H'FFFF FD51 TDFA23 TDFA22 TDFA21 TDFA20 TDFA19 TDFA18 TDFA17 TDFA16 H'FFFF FD52 TDFA15 TDFA14 TDFA13 TDFA12 TDFA11 TDFA10 TDFA9 TDFA8 H'FFFF FD50 TDFAR H'FFFF FD53 TDFA7 TDFA6 TDFA5 TDFA4 TDFA3 TDFA2 TDFA1 TDFA0 H'FFFF FD54 — to H'FFFF FD5F — — — — — — — — H'FFFF FD60 — — — — — — — — H'FFFF FD61 — — — — — — — — H'FFFF FD62 — — — PRCEF — — MPDE — H'FFFF FD63 — RE TE — ILB ELB DM PRM — — — — — — — — H'FFFF FD65 — — — — — — — — H'FFFF FD66 — — — — — — — — H'FFFF FD67 — — — — — LCHNG MPD ICD — — — — — — — — H'FFFF FD69 — — — — — — — — H'FFFF FD6A — — — — — — — H'FFFF FD6B — — — — — LCHNGIP MPDIP ICDIP H'FFFF FD6C PIR — — — — — — — — H'FFFF FD6D — — — — — — — — H'FFFF FD6E — — — — — — — — H'FFFF FD6F — — — — MDI MDO MMD MMC H'FFFF FD64 H'FFFF FD68 H'FFFF FD70 ECMR ECSR ECSIPR MAHR — MA47 MA46 MA45 MA44 MA43 MA42 MA41 MA40 H'FFFF FD71 MA39 MA38 MA37 MA36 MA35 MA34 MA33 MA32 H'FFFF FD72 MA31 MA30 MA29 MA28 MA27 MA26 MA25 MA24 H'FFFF FD73 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 Rev. 2.00 Mar 09, 2006 page 888 of 906 REJ09B0292-0200 EtherC Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD74 MALR — — — — — — — — EtherC — — — — — — — — H'FFFF FD75 H'FFFF FD76 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 H'FFFF FD77 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 — — — — — — — — H'FFFF FD79 — — — — — — — — H'FFFF FD7A — — — — RFL11 RFL10 RFL9 RFL8 H'FFFF FD78 RFLR H'FFFF FD7B RFL7 RFL6 RFL5 RFL4 RFL3 RFL2 RFL1 RFL0 H'FFFF FD7C PSR — — — — — — — — H'FFFF FD7D — — — — — — — — H'FFFF FD7E — — — — — — — — H'FFFF FD7F — — — — — — — LMON H'FFFF FD80 — — — — — — — — H'FFFF FD81 — — — — — — — — H'FFFF FD82 TROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9 TROC8 H'FFFF FD83 TROC7 TROC6 TROC5 TROC4 TROC3 TROC2 TROC1 TROC0 — — — — — — — — H'FFFF FD85 — — — — — — — — H'FFFF FD86 COLDC15 COLDC14 COLDC13 COLDC12 COLDC11 COLDC10 COLDC9 COLDC8 H'FFFF FD87 COLDC7 COLDC6 COLDC5 COLDC4 COLDC3 COLDC2 COLDC1 COLDC0 — — — — — — — — H'FFFF FD89 — — — — — — — — H'FFFF FD8A LCC15 LCC14 LCC13 LCC12 LCC11 LCC10 LCC9 LCC8 H'FFFF FD84 H'FFFF FD88 TROCR CDCR LCCR H'FFFF FD8B LCC7 LCC6 LCC5 LCC4 LCC3 LCC2 LCC1 LCC0 H'FFFF FD8C CNDCR — — — — — — — — H'FFFF FD8D — — — — — — — — H'FFFF FD8E CNDC15 CNDC14 CNDC13 CNDC12 CNDC11 CNDC10 CNDC9 CNDC8 H'FFFF FD8F CNDC7 CNDC6 CNDC5 CNDC4 CNDC3 CNDC2 CNDC1 CNDC0 H'FFFF FD90 — — — — — — — — H'FFFF FD91 IFLCR — — — — — — — — H'FFFF FD92 IFLC15 IFLC14 IFLC13 IFLC12 IFLC11 IFLC10 IFLC9 IFLC8 H'FFFF FD93 IFLC7 IFLC6 IFLC5 IFLC4 IFLC3 IFLC2 IFLC1 IFLC0 Rev. 2.00 Mar 09, 2006 page 889 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FD94 CEFCR — — — — — — — — EtherC H'FFFF FD95 — — — — — — — — H'FFFF FD96 CEFC15 CEFC14 CEFC13 CEFC12 CEFC11 CEFC10 CEFC9 CEFC8 H'FFFF FD97 CEFC7 CEFC6 CEFC5 CEFC4 CEFC3 CEFC2 CEFC1 CEFC0 — — — — — — — — H'FFFF FD99 — — — — — — — — H'FFFF FD9A FREC15 FREC14 FREC13 FREC12 FREC11 FREC10 FREC9 FREC8 H'FFFF FD9B FREC7 H'FFFF FD98 FRECR FREC6 FREC5 FREC4 FREC3 FREC2 FREC1 FREC0 H'FFFF FD9C TSFRCR — — — — — — — — H'FFFF FD9D — — — — — — — — H'FFFF FD9E TSFC15 TSFC14 TSFC13 TSFC12 TSFC11 TSFC10 TSFC9 TSFC8 H'FFFF FD9F TSFC7 TSFC6 TSFC5 TSFC4 TSFC3 TSFC2 TSFC1 TSFC0 H'FFFF FDA0 TLFRCR — — — — — — — — H'FFFF FDA1 — — — — — — — — H'FFFF FDA2 TLFC15 TLFC14 TLFC13 TLFC12 TLFC11 TLFC10 TLFC9 TLFC8 H'FFFF FDA3 TLFC7 TLFC6 TLFC5 TLFC4 TLFC3 TLFC2 TLFC1 TLFC0 H'FFFF FDA4 RFCR — — — — — — — — H'FFFF FDA5 — — — — — — — — H'FFFF FDA6 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 H'FFFF FDA7 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 H'FFFF FDA8 MAFCR — — — — — — — — H'FFFF FDA9 — — — — — — — — H'FFFF FDAA MAFC15 MAFC14 MAFC13 MAFC12 MAFC11 MAFC10 MAFC9 MAFC8 H'FFFF FDAB MAFC7 MAFC6 MAFC5 MAFC4 MAFC3 MAFC2 MAFC1 MAFC0 H'FFFF FDAC — to H'FFFF FDB3 — — — — — — — — — H'FFFF FDB4 SCDCR COSDC 31 COSDC 30 COSDC 29 COSDC 28 COSDC 27 COSDC 26 COSDC 25 COSDC 24 EtherC H'FFFF FDB5 COSDC 23 COSDC 22 COSDC 21 COSDC 20 COSDC 19 COSDC 18 COSDC 17 COSDC 16 H'FFFF FDB6 COSDC 15 COSDC 14 COSDC 13 COSDC 12 COSDC 11 COSDC 10 COSDC9 COSDC8 H'FFFF FDB7 COSDC7 COSDC6 COSDC5 COSDC4 COSDC3 COSDC2 COSDC1 COSDC0 Rev. 2.00 Mar 09, 2006 page 890 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name H'FFFF FDB8 — to H'FFFF FE0F Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — — — FRT H'FFFFFE10 TIER ICIE — — — OCIAE OCIBE OVIE — H'FFFFFE11 FTCSR ICF — — — OCFA OCFB OVF CCLRA H'FFFFFE12 FRC H H'FFFFFE13 FRC L H'FFFFFE14 OCRA H OCRB H H'FFFFFE15 OCRA L OCRB L H'FFFFFE16 TCR IEDG — — — — — CKS1 CKS0 H'FFFFFE17 TOCR — — — OCRS — — OLVLA OLVLB H'FFFFFE18 FICR H — — — — — — — — H'FFFFFE19 FICR L H'FFFFFE1A to H'FFFFFE3F — H'FFFFFE40 IPRD H'FFFFFE41 H'FFFFFE42 VCRE — TG0AV6 TG0AV5 TG0AV4 TG0AV3 TG0AV2 TG0AV1 TG0AV0 — TG0BV6 TG0BV5 TG0BV4 TG0BV3 TG0BV2 TG0BV1 TG0BV0 VCRF — TG0CV6 TG0CV5 TG0CV4 TG0CV3 TG0CV2 TG0CV1 TG0CV0 — TG0DV6 TG0DV5 TG0DV4 TG0DV3 TG0DV2 TG0DV1 TG0DV0 VCRG — TC0VV6 TC0VV5 TC0VV4 TC0VV3 TC0VV2 TC0VV1 TC0VV0 — — — — — — — — H'FFFFFE45 H'FFFFFE46 H'FFFFFE47 H'FFFFFE48 VCRH — TG1AV6 TG1AV5 TG1AV4 TG1AV3 TG1AV2 TG1AV1 TG1AV0 — TG1BV6 TG1BV5 TG1BV4 TG1BV3 TG1BV2 TG1BV1 TG1BV0 — TC1VV6 TC1VV5 TC1VV4 TC1VV3 TC1VV2 TC1VV1 TC1VV0 — TC1UV6 TC1UV5 TC1UV4 TC1UV3 TC1UV2 TC1UV1 TC1UV0 — TG2AV6 TG2AV5 TG2AV4 TG2AV3 TG2AV2 TG2AV1 TG2AV0 — TG2BV6 TG2BV5 TG2BV4 TG2BV3 TG2BV2 TG2BV1 TG2BV0 VCRK — TC2VV6 TC2VV5 TC2VV4 TC2VV3 TC2VV2 TC2VV1 TC2VV0 — TC2UV6 TC2UV 5 TC2UV4 TC2UV3 TC2UV2 TC2UV1 TC2UV0 VCRL — SER1V6 SER1V5 SER1V4 SER1V3 SER1V2 SER1V1 SER1V0 — SRX1V6 SRX1V5 SRX1V4 SRX1V3 SRX1V2 SRX1V1 SER1V0 — SBR1V6 SBR1V5 SBR1V4 SBR1V3 SBR1V2 SBR1V1 SBR1V0 — STX1V6 STX1V5 STX1V4 STX1V3 STX1V2 STX1V1 STX1V0 H'FFFFFE49 H'FFFFFE4A VCRI H'FFFFFE4B H'FFFFFE4C VCRJ H'FFFFFE4D H'FFFFFE4E H'FFFFFE4F H'FFFFFE50 H'FFFFFE51 H'FFFFFE52 H'FFFFFE53 TPU0IP3 TPU0IP2 TPU0IP1 TPU0IP0 TPU1IP3 TPU1IP2 TPU1IP1 TPU1IP0 INTC TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0 H'FFFFFE43 H'FFFFFE44 — VCRM Rev. 2.00 Mar 09, 2006 page 891 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFE54 VCRN — SER2V6 SER2V5 SER2V4 SER2V3 SER2V2 SER2V1 SER2V0 INTC — SRX2V6 SRX2V5 SRX2V4 SRX2V3 SRX2V2 SRX2V1 SRX2V0 VCRO — SBR2V6 SBR2V5 SBR2V4 SBR2V3 SBR2V2 SBR2V1 SBR2V0 — STX2V6 STX2V5 STX2V4 STX2V3 STX2V2 STX2V1 STX2V0 — — — — — — — — INTC H'FFFFFE55 H'FFFFFE56 H'FFFFFE57 H'FFFFFE58 to H'FFFFFE5F — — H'FFFFFE60 IPRB EEEEFRTIP3 DMACIP3 DMACIP2 DMACIP1 DMACIP0 FRTIP2 FRTIP1 FRTIP0 H'FFFFFE61 H'FFFFFE62 — — — — — — — — VCRA — EINV6 EINV5 EINV4 EINV3 EINV2 EINV1 EINV0 — — — — — — — — VCRB — — — — — — — — — — — — — — — — H'FFFFFE63 H'FFFFFE64 H'FFFFFE65 H'FFFFFE66 VCRC — FICV6 FICV5 FICV4 FICV3 FICV2 FICV1 FICV0 — FOCV6 FOCV5 FOCV4 FOCV3 FOCV2 FOCV1 FOCV0 VCRD — FOVV6 FOVV5 FOVV4 FOVV3 FOVV2 FOVV1 FOVV0 — — — — — — — — — — — — — — — — — — DMAC H'FFFFFE67 H'FFFFFE68 H'FFFFFE69 H'FFFFFE6A to H'FFFFFE70 H'FFFFFE71 DRCR0 — — — RS4 RS3 RS2 RS1 RS0 H'FFFFFE72 DRCR1 — — — RS4 RS3 RS2 RS1 RS0 H'FFFFFE73 to H'FFFFFE7F — — — — — — — — — — H'FFFFFE80 WTCSR OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT H'FFFFFE81 WTCNT H'FFFFFE82 — — — — — — — — — H'FFFFFE83 RSTCSR WOVF RSTE RSTS — — — — — H'FFFFFE84 to H'FFFFFE8F — — — — — — — — — — H'FFFFFE90 FMR PLL2ST PLL1ST CKIOST — FR3 FR2 FR1 FR0 On-chip oscillation circuit H'FFFFFE91 SBYCR1 SBY HIZ MSTP5 MSTP4 MSTP3 — MSTP1 — Powerdown state H'FFFFFE92 CCR W1 W0 WB CP TW H'FFFFFE93 SBYCR2 — — MSTP11 MSTP10 MSTP9 Rev. 2.00 Mar 09, 2006 page 892 of 906 REJ09B0292-0200 OD ID CE CACHE MSTP8 MSTP7 MSTP6 Powerdown state Appendix A On-Chip Peripheral Module Registers Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFE94 to H'FFFFFEBF — — — — — — — — — — H'FFFFFEC0 IPRE SCF2IP3 SCF2IP2 SCF2IP1 SCF2IP0 SIOFIP3 SIOFIP2 SIOFIP1 SIOFIP0 INTC SIO1IP3 SIO1P2 SIO2IP2 SIO2IP1 SIO2IP0 VCRP — RER0V6 RER0V5 RER0V4 RER0V3 RER0V2 RER0V1 RER0V0 — TER0V6 TER0V5 TER0V4 TER0V3 TER0V2 TER0V1 TER0V0 — RDF0V6 RDF0V5 RDF0V4 RDF0V3 RDF0V2 RDF0V1 RDF0V0 — TDE0V6 TDE0V5 TDE0V4 TDE0V3 TDE0V2 TDE0V1 TDE0V0 — RER1V6 RER1V5 RER1V4 RER1V3 RER1V2 RER1V1 RER1V0 — TER1V6 TER1V5 TER1V4 TER1V3 TER1V2 TER1V1 TER1V0 — RDF1V6 RDF1V5 RDF1V4 RDF1V3 RDF1V2 RDF1V1 RDF1V0 — TDE1V6 TDE1V5 TDE1V4 TDE1V3 TDE1V2 TDE1V1 TDE1V0 — RER2V6 RER2V5 RER2V4 RER2V3 RER2V2 RER2V1 RER2V0 — TER2V6 TER2V5 TER2V4 TER2V3 TER2V2 TER2V1 TER2V0 — RDF2V6 RDF2V5 RDF2V4 RDF2V3 RDF2V2 RDF2V1 RDF2V0 — TDE2V6 TDE2V5 TDE2V4 TDE2V3 TDE2V2 TDE2V1 TDE2V0 Address H'FFFFFEC1 H'FFFFFEC2 H'FFFFFEC3 H'FFFFFEC4 VCRQ H'FFFFFEC5 H'FFFFFEC6 VCRR H'FFFFFEC7 H'FFFFFEC8 VCRS H'FFFFFEC9 H'FFFFFECA VCRT H'FFFFFECB H'FFFFFECC VCRU H'FFFFFECD SIO2P1 SIO1IP0 SIO2IP3 H'FFFFFECE to H'FFFFFEDF — — — — — — — — — — H'FFFFFEE0 ICR NMIL — — — — — — NMIE INTC — — — — — — EXIMD VECMD IPRA — — — — DMACIP3 DMACIP2 DMACIP1 DMACIP0 WDTIP3 WDTIP2 WDTIP1 WDTIP0 — H'FFFFFEE1 H'FFFFFEE2 H'FFFFFEE3 H'FFFFFEE4 VCRWDT — — WITV6 WITV5 WITV4 WITV3 WITV2 WITV1 WITV0 BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0 IPRC IRQ0IP3 IRQ0IP2 IRQ0IP1 IRQ0IP0 IRQ1IP3 IRQ1IP2 IRQ1IP1 IRQ1IP0 IRQ2IP3 IRQ2IP2 IRQ2IP1 IRQ2IP0 IRQ3IP3 IRQ3IP2 IRQ3IP1 IRQ3IP0 IRQCSR IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S IRL3PS IRL2PS IRL1PS IRL0PS IRQ3F IRQ2F IRQ1F IRQ0F H'FFFFFEE7 H'FFFFFEE8 — — H'FFFFFEE5 H'FFFFFEE6 — H'FFFFFEE9 H'FFFFFEEA to H'FFFFFEFF — — — — — — — — — — H'FFFF FF00 BARAH BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 UBC BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 H'FFFF FF01 H'FFFF FF02 H'FFFF FF03 BARAL Rev. 2.00 Mar 09, 2006 page 893 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 H'FFFF FF04 BAMRAH BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 UBC H'FFFF FF05 H'FFFF FF06 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMRAL H'FFFF FF07 H'FFFF FF08 Bit 6 BBRA H'FFFF FF09 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 — — — — — — — — CPA1 CPA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 H'FFFF FF0A to H'FFFF FF0F — — — — — — — — — — H'FFFF FF10 BRFR SVF PID2 PID1 PID0 — — — — UBC DVF — — — — — — — H'FFFF FF11 H'FFFF FF12 to H'FFFF FF13 — — — — — — — — — — H'FFFF FF14 BRSRH BSA31 BSA30 BSA29 BSA28 BSA27 BSA26 BSA25 BSA24 UBC BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 H'FFFF FF15 H'FFFF FF16 BRSRL BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 BDA31 BDA30 BDA29 DA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 H'FFFF FF1B BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 H'FFFF FF1C — to H'FFFF FF1F — — — — — — — — — H'FFFF FF20 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 UBC BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 H'FFFF FF17 H'FFFF FF18 BRDRH H'FFFF FF19 H'FFFF FF1A BRDRL BARBH H'FFFF FF21 H'FFFF FF22 BARBL H'FFFF FF23 H'FFFF FF24 BAMRBH H'FFFF FF25 H'FFFF FF26 BAMRBL H'FFFF FF27 H'FFFF FF28 H'FFFF FF29 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BBRB BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 — — — — — — — — CPB1 CPB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 Rev. 2.00 Mar 09, 2006 page 894 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FF2A to H'FFFF FF2F — — — — — — — — — — H'FFFF FF30 BRCRH CMFCA CMFPA — — PCTE PCBA — — UBC CMFCB CMFPB — SEQ1 SEQ0 PCBB — — CMFCC CMFPC ETBEC — DBEC PCBC — — CMFCD CMFPD ETBED — DBED PCBD — — Address H'FFFF FF31 H'FFFF FF32 BRCRL H'FFFF FF33 H'FFFF FF34 to H'FFFF FF3F — — — — — — — — — — H'FFFFFF40 BARCH BAC31 BAC30 BAC29 BAC28 BAC27 BAC26 BAC25 BAC24 UBC BAC23 BAC22 BAC21 BAC20 BAC19 BAC18 BAC17 BAC16 BAC15 BAC14 BAC13 BAC12 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 H'FFFFFF41 H'FFFFFF42 BARCL H'FFFFFF43 H'FFFFFF44 BAMRCH H'FFFFFF45 H'FFFFFF46 BAMRCL H'FFFFFF47 H'FFFFFF48 BAMC31 BAMC30 BAMC29 BAMC28 BAMC27 BAMC26 BAMC25 BAMC24 BAMC23 BAMC22 BAMC21 BAMC20 BAMC19 BAMC18 BAMC17 BAMC16 BBRC H'FFFFFF49 BAMC15 BAMC14 BAMC13 BAMC12 BAMC11 BAMC10 BAMC9 BAMC8 BAMC7 BAMC6 BAMC5 BAMC4 BAMC3 BAMC2 BAMC1 BAMC0 — — — — — — — — CPC1 CPC0 IDC1 IDC0 RWC1 RWC0 SZC1 SZC0 H'FFFFFF4A to H'FFFFFF4F — — — — — — — — — — H'FFFF FF50 BDRCH BDC31 BDC30 BDC29 BDC28 BDC27 BDC26 BDC25 BDC24 UBC BDC23 BDC22 BDC21 BDC20 BDC19 BDC18 BDC17 BDC16 BDRCL BDC15 BDC14 BDC13 BDC12 BDC11 BDC10 BDC9 BDC8 BDC7 BDC6 BDC5 BDC4 BDC3 BDC2 BDC1 BDC0 H'FFFF FF51 H'FFFF FF52 H'FFFF FF53 H'FFFF FF54 BDMRCH H'FFFF FF55 H'FFFF FF56 BDMC23 BDMC22 BDMC21 BDMC20 BDMC19 BDMC18 BDMC17 BDMC16 BDMRCL BDMC15 BDMC14 BDMC13 BDMC12 BDMC11 BDMC10 BDMC9 BDMC8 BDMC7 BDMC6 BDMC5 BDMC4 BDMC3 BDMC2 BDMC1 BDMC0 BETRC — — — — ETRC11 ETRC10 ETRC9 ETRC8 ETRC7 ETRC6 ETRC5 ETRC4 ETRC3 ETRC2 ETRC1 ETRC0 — — — — — — — — — H'FFFF FF57 H'FFFF FF58 H'FFFF FF59 H'FFFF FF5A to H'FFFF FF5F BDMC31 BDMC30 BDMC29 BDMC28 BDMC27 BDMC26 BDMC25 BDMC24 — Rev. 2.00 Mar 09, 2006 page 895 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Address Register Name Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFF FF60 BARDH BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 UBC H'FFFF FF61 BAD23 BAD22 BAD21 BAD20 BAD19 BAD18 BAD17 BAD16 H'FFFF FF62 BARDL BAD15 BAD14 BAD13 BAD12 BAD11 BAD10 BAD9 BAD8 H'FFFF FF63 BAD7 BAD6 BAD5 BAD4 BAD3 BAD2 BAD1 BAD0 H'FFFF FF64 BAMRDH BAMD31 BAMD30 BAMD29 BAMD28 BAMD27 BAMD26 BAMD25 BAMD24 H'FFFF FF65 BAMD23 BAMD22 BAMD21 BAMD20 BAMD19 BAMD18 BAMD17 BAMD16 H'FFFF FF66 BAMRDL BAMD15 BAMD14 BAMD13 BAMD12 BAMD11 BAMD10 BAMD9 BAMD8 H'FFFF FF67 BAMD7 BAMD6 BAMD5 BAMD4 BAMD3 BAMD2 BAMD1 BAMD0 H'FFFF FF68 BBRD — — — — — — XYED XYSD H'FFFF FF69 CPD1 CPD0 IDD1 IDD0 RWD1 RWD0 SZD1 SZD0 H'FFFF FF6A — to H'FFFF FF6F — — — — — — — — — H'FFFF FF70 BDRDH BDD31 BDD30 BDD29 BDD28 BDD27 BDD26 BDD25 BDD24 UBC H'FFFF FF71 BDD23 BDD22 BDD21 BDD20 BDD19 BDD18 BDD17 BDD16 H'FFFF FF72 BDRDL BDD15 BDD14 BDD13 BDD12 BDD11 BDD10 BDD9 BDD8 H'FFFF FF73 BDD7 BDD6 BDD5 BDD4 BDD3 BDD2 BDD1 BDD0 H'FFFF FF74 BDMRDH BDMD31 BDMD30 BDMD29 BDMD28 BDMD27 BDMD26 BDMD25 BDMD24 H'FFFF FF75 BDMD23 BDMD22 BDMD21 BDMD20 BDMD19 BDMD18 BDMD17 BDMD16 H'FFFF FF76 BDMRDL BDMD15 BDMD14 BDMD13 BDMD12 BDMD11 BDMD10 BDMD9 BDMD8 BDMD7 BDMD6 BDMD5 BDMD4 BDMD3 BDMD1 BDMD0 BETRD — — — — ETRD11 ETRD10 ETRD9 ETRD8 ETRD7 ETRD6 ETRD5 ETRD4 ETRD3 ETRD2 ETRD1 ETRD0 — — — — — — — — H'FFFF FF77 H'FFFF FF78 H'FFFF FF79 H'FFFF FF7A to H'FFFF FF7F — H'FFFFFF80 SAR0 H'FFFFFF81 H'FFFFFF82 H'FFFFFF83 H'FFFFFF84 DAR0 H'FFFFFF85 H'FFFFFF86 H'FFFFFF87 Rev. 2.00 Mar 09, 2006 page 896 of 906 REJ09B0292-0200 BDMD2 — DMAC Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFF88 TCR0 — — — — — — — — DMAC CHCR0 — H'FFFFFF89 H'FFFFFF8A H'FFFFFF8B H'FFFFFF8C — — — — — — — H'FFFFFF8D — — — — — — — — H'FFFFFF8E DM1 DM0 SM1 SM0 TS1 TS0 AR AM AL DS DL TB TA IE TE DE TCR1 — — — — — — — — CHCR1 — H'FFFFFF8F H'FFFFFF90 SAR1 H'FFFFFF91 H'FFFFFF92 H'FFFFFF93 H'FFFFFF94 DAR1 H'FFFFFF95 H'FFFFFF96 H'FFFFFF97 H'FFFFFF98 H'FFFFFF99 H'FFFFFF9A H'FFFFFF9B H'FFFFFF9C — — — — — — — H'FFFFFF9D — — — — — — — — H'FFFFFF9E DM1 DM0 SM1 SM0 TS1 TS0 AR AM H'FFFFFF9F AL DS DL TB TA IE TE DE H'FFFFFFA0 VCRDMA0 — — — — — — — — H'FFFFFFA1 — — — — — — — — H'FFFFFFA2 — — — — — — — — H'FFFFFFA3 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 H'FFFFFFA4 to H'FFFFFFA7 — — — — — — — — — — H'FFFFFFA8 VCRDMA1 — — — — — — — — DMAC H'FFFFFFA9 — — — — — — — — H'FFFFFFAA — — — — — — — — H'FFFFFFAB VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 — — — — — — — — H'FFFFFFAC to H'FFFFFFAF — — Rev. 2.00 Mar 09, 2006 page 897 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFFB0 DMAOR — — — — — — — — DMAC H'FFFFFFB1 — — — — — — — — H'FFFFFFB2 — — — — — — — — H'FFFFFFB3 — — — — PR AE NMIF DME H'FFFFFFB4 to H'FFFFFFBF — — — — — — — — — — H'FFFFFFC0 WCR2 A4WD1 A4WD0 — A4WM A3WM A2WM A1WM A0WM BSC — — — — IW41 IW40 W41 W40 — — — — — — — — — A4SW2 A4SW1 A4SW0 — A4HW1 A4HW0 BSC H'FFFFFFC1 H'FFFFFFC2 to H'FFFFFFC3 — H'FFFFFFC4 WCR3 H'FFFFFFC5 — — A3SHW1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0 H'FFFFFFC6 to H'FFFFFFDF — — — — — H'FFFFFFE0 BCR1 — A4LW1 A4LW0 A1LW1 A1LW0 H'FFFFFFE1 — — — — — A2ENDIA BSTROM — N AHLW1 AHLW0 BSC A0LW1 A0LW0 A4ENDIA DRAM2 N DRAM1 DRAM0 H'FFFFFFE2 to H'FFFFFFE3 — — — — — — — — — — H'FFFFFFE4 BCR2 — — — — — — A4SZ1 A4SZ0 BSC H'FFFFFFE5 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 — — H'FFFFFFE6 to H'FFFFFFE7 — — — — — — — — — — H'FFFFFFE8 WCR1 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 BSC W31 W30 W21 W20 W11 W10 W01 W00 H'FFFFFFE9 H'FFFFFFEA to H'FFFFFFEB — — — — — — — — — — H'FFFFFFEC MCR TRP0 RCD0 TRWL0 TRAS1 TRAS0 BE RASD TRWL1 BSC AMX2 SZ AMX1 AMX0 RFSH RMD TRP1 RCD1 H'FFFFFFEE to H'FFFFFFEF — — — — — — — — — — H'FFFFFFF0 RTCSR — — — — — — — — BSC CMF CMIE CKS2 CKS1 CKS0 RRC2 RRC1 RRC0 H'FFFFFFED H'FFFFFFF1 Rev. 2.00 Mar 09, 2006 page 898 of 906 REJ09B0292-0200 Appendix A On-Chip Peripheral Module Registers Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFFF2 to H'FFFFFFF3 — — — — — — — — — — H'FFFFFFF4 RTCNT — — — — — — — — BSC H'FFFFFFF6 to H'FFFFFFF7 — — — — — — — — — — H'FFFFFFF8 RTCOR — — — — — — — — BSC H'FFFFFFFA to H'FFFFFFFB — — — — — — — — — — H'FFFFFFFC BCR3 BSC Address H'FFFFFFF5 H'FFFFFFF9 H'FFFFFFFD H'FFFFFFFE to H'FFFFFFFF — — — — — A4LW2 AHLW2 A1LW2 A0LW2 DSWW1 DSWW0 — — — BASEL EDO BWE — — — — — — — — — Rev. 2.00 Mar 09, 2006 page 899 of 906 REJ09B0292-0200 Appendix B Pin States Appendix B Pin States B.1 Pin States in Reset, Power-Down State, and Bus-Released State Pin State Manual Reset Power-Down State PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode BusReleased State Bus control A24–A0 O O Z Z Z O Z D31–D0 Z IO Z Z Z IO Z CS4–CS0 H O Z H H H Z RD/WR H O Z H H H Z RAS H O Z H H H Z CAS/OE H O Z H H H Z WAIT Z I Z Z Z I Ignored BS H O Z H H H Z RD H O Z H H H Z BGR H O O H H O O Pin Type Interrupt Pin Name BRLS Z I I Z Z I I CKE H O H O O O H DQMUU/WE3 H O Z H H H Z DQMUL/WE2 H O Z H H H Z DQMLU/WE1 H O Z H H H Z DQMLL/WE0 H O Z H H H Z REFOUT L O O L Z O O CAS3–CAS0 H O Z H H H Z BH H O Z H H H Z BUSHiZ Z I Z Z Z I Ignored NMI I I I I I I I IRL3–IRL0 Z Z Z I I I I IVECF H H H H Z H H Rev. 2.00 Mar 09, 2006 page 900 of 906 REJ09B0292-0200 Appendix B Pin States Pin State Manual Reset Power-Down State Pin Type Pin Name PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode Clock XTAL O* O* O* O* O* O* O* EXTAL I* I* I* I* I* I* I* CKIO IO* IO* IO* IO* IO* IO* IO* CKPACK H H H H H H H CKPREQ/CKM I I I I I I I PLLCAP2, PLLCAP1 IO IO IO IO IO IO IO DREQ1, DREQ0 Z Z Z Z Z I I DACK1, DACK0 H H H K Z O O System RES I I I I I I I control MD4–MD0 I I I I I I I Port, PB15/SCK1 Z IO/Z IO/Z K Z IO IO Internal PB14/RXD1 Z IO/Z IO/Z K Z IO/I IO/I peripheral PB13/TXD1 Z IO/Z IO/Z K Z IO/O IO/O module PB12/SRCK2/RTS/ STATS1 Z IO/Z/Z/O IO/Z/Z/O K/K/K/O Z IO/I/O/O IO/I/O/O PB11/SRS2/CTS/ STATS0 Z IO/Z/Z/O IO/Z/Z/O K/K/K/O Z IO/I/I/O IO/I/I/O PB10/SRXD2/TIOCA1 Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/IO IO/I/IO PB9/STCK2/TIOCB1, TCLKC Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/IO IO/I/IO PB8/STS2/TIOCA2 Z IO/Z/Z IO/Z/Z K/K/K Z IO/IO/IO IO/IO/IO PB7/STXD2/TIOCB2, TCLKD Z IO/Z/Z IO/Z/Z K/K/K Z IO/O/IO IO/O/IO PB6/SRCK1/SCK2 Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/IO IO/I/IO PB5/SRS1/RXD2 Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/I IO/I/I PB4/SRXD1/TXD2 Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/O IO/I/O PB3/STCK1/TIOCA0 Z IO/Z/Z IO/Z/Z K/K/K Z IO/I/IO IO/I/IO PB2/STS1/TIOCB0 Z IO/Z/Z IO/Z/Z K/K/K Z IO/IO/IO IO/IO/IO PB1/STXD1/TIOCC0, TCLKA Z IO/Z/Z IO/Z/Z K/K/K Z IO/O/IO IO/O/IO DMAC BusReleased State Rev. 2.00 Mar 09, 2006 page 901 of 906 REJ09B0292-0200 Appendix B Pin States Pin State Manual Reset Power-Down State PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode BusReleased State Pin Type Pin Name Port, Internal PB0/TIOCD0, TCLKB/WOL Z IO/Z/O IO/Z/O K/K/O Z IO/IO/O IO/IO/O peripheral PA13/SRCK0 Z IO/Z IO/Z K/K Z IO/I IO/I module HUDI PA12/SRS0 Z IO/Z IO/Z K/K Z IO/I IO/I PA11/SRXD0 Z IO/Z IO/Z K/K Z IO/I IO/I PA10/STCK0 Z IO/Z IO/Z K/K Z IO/I IO/I PA9/STS0 Z IO/Z IO/Z K/K Z IO/IO IO/IO PA8/STXD0 Z IO/Z IO/Z K/K Z IO/O IO/O WDTOVF/PA7 H H/IO H/IO O/K O/Z O/IO O/IO PA6/FTCI Z IO/Z IO/Z K Z IO/I IO/I PA5/FTI Z IO/Z IO/Z K Z IO/I IO/I PA4/FTOA Z IO/L IO/L K Z IO/O IO/O CKPO/FTOB H H/L H/L K Z O/O O/O PA2/LNKSTA Z IO/I IO/I K Z IO/I IO/I PA1/EXOUT Z IO/O IO/O K Z IO/O IO/O PA0/CAMSEN Z IO/I IO/I K Z IO/I IO/I TRST I I I I I I I TCK I I I I I I I TMS I I I I I I I TDI I I I I I I I TDO O O O O O O O ASEMODE I I I I I I I Rev. 2.00 Mar 09, 2006 page 902 of 906 REJ09B0292-0200 Appendix B Pin States Pin State Manual Reset Power-Down State Pin Type Pin Name PowerStandby Standby On Bus Bus Mode Mode Sleep Reset Acquired Released (HIZ = 0) (HIZ = 1) Mode EtherC TX-CLK I I I I I I I TX-EN O O O O O O O TX-ER O O O O O O O ETXD–ETXD0 O O O O O O O CRS I I I I I I I COL I I I I I I I MDC O O O O O O O MDIO IO IO IO IO IO IO IO RX-CLK I I I I I I I RX-DV I I I I I I I RX-ER I I I I I I I ERXD–ERXD0 I I I I I I I I: O: H: L: Z: K: BusReleased State Input Output High-level output Low-level output High-impedance state Input pins are in the high-impedance state; output pins maintain their previous state. Notes: In sleep mode, if the DMAC is operating the address/data bus and bus control signals vary according to the operation of the DMAC. (The same applies when refreshing is performed.) * Depends on the clock mode (CKPREQN, MD2–MD0 setting). Rev. 2.00 Mar 09, 2006 page 903 of 906 REJ09B0292-0200 Appendix C Product Lineup Appendix C Product Lineup Table C.1 SH7616 Product Lineup Abbreviation Voltage Operating Frequency Mark Code Package SH7616 3.3 V 62.5 MHz HD6417616SF PLQP0208KA-A Rev. 2.00 Mar 09, 2006 page 904 of 906 REJ09B0292-0200 Appendix D Package Dimensions Appendix D Package Dimensions Figure D.1 shows the PLQP0208KA-A package dimensions. JEITA Package Code P-LQFP208-28x28-0.50 RENESAS Code PLQP0208KA-A Previous Code FP-208C/FP-208CV MASS[Typ.] 2.7g HD *1 D 156 105 157 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 104 bp c c1 HE 2 E b1 Terminal cross section ZE Reference Symbol 53 208 1 52 c A2 Index mark A ZD F θ A1 L L1 e *3 y bp x M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 28 28 1.40 29.8 30.0 30.2 29.8 30.0 30.2 1.70 0.05 0.10 0.15 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0˚ 8˚ 0.5 0.08 0.08 1.25 1.25 0.4 0.5 0.6 1.0 Figure D.1 Package Dimensions (PLQP0208KA-A) Rev. 2.00 Mar 09, 2006 page 905 of 906 REJ09B0292-0200 Appendix D Package Dimensions Rev. 2.00 Mar 09, 2006 page 906 of 906 REJ09B0292-0200 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7616 Publication Date: 1st Edition, November 2001 Rev.2.00, March 09, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.0 SH7616 Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0292-0200