HD6417751RBP200

To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Renesas Technology Corp. Hitachi SuperH
RISC engine SH7751 Series SH7751, SH7751R Hardware Manual ADE-602-201B Rev. 3.0 4/11/2002 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Preface The SH-4 (SH7751 Series (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA. Target Readers: This manual is designed for use by people who design application systems using the SH7751 or SH7751R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. This hardware manual contains revisions related to the addition of R-mask functionality. Be sure to check the text for the updated content. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the SH7751 and SH7751R. The SH-4 Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual. How to Use the Book:
To understand general functions  Read the manual from the beginning. The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order.
To understanding CPU functions  Refer to the separate SH-4 Programming Manual. Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.hitachisemiconductor.com/) Rev. 3.0, 04/02, page iii of xxxviii 

User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Series Hardware Manual This manual SH-4 Programming Manual ADE-602-156 User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Hitachi Embedded Workshop User’s Manual ADE-702-201 Rev. 3.0, 04/02, page iv of xxxviii Contents Section 1 1.1 1.2 1.3 1.4 Overview ........................................................................................................... SH7751 Series Features..................................................................................................... Block Diagram .................................................................................................................. Pin Arrangement ............................................................................................................... Pin Functions..................................................................................................................... 1.4.1 Pin Functions (256-Pin QFP) ............................................................................... 1.4.2 Pin Functions (256-Pin BGA) .............................................................................. Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Programming Model ...................................................................................... Data Formats ..................................................................................................................... Register Configuration ...................................................................................................... 2.2.1 Privileged Mode and Banks ................................................................................. 2.2.2 General Registers ................................................................................................. 2.2.3 Floating-Point Registers ....................................................................................... 2.2.4 Control Registers.................................................................................................. 2.2.5 System Registers .................................................................................................. Memory-Mapped Registers ............................................................................................... Data Format in Registers ................................................................................................... Data Formats in Memory .................................................................................................. Processor States................................................................................................................. Processor Modes................................................................................................................ Section 3 3.1 3.2 3.3 3.4 Memory Management Unit (MMU) ......................................................... Overview ........................................................................................................................... 3.1.1 Features ................................................................................................................ 3.1.2 Role of the MMU ................................................................................................. 3.1.3 Register Configuration ......................................................................................... 3.1.4 Caution ................................................................................................................. Register Descriptions......................................................................................................... Address Space ................................................................................................................... 3.3.1 Physical Address Space........................................................................................ 3.3.2 External Memory Space ....................................................................................... 3.3.3 Virtual Address Space .......................................................................................... 3.3.4 On-Chip RAM Space ........................................................................................... 3.3.5 Address Translation.............................................................................................. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode.................... 3.3.7 Address Space Identifier (ASID).......................................................................... TLB Functions................................................................................................................... 3.4.1 Unified TLB (UTLB) Configuration.................................................................... 1 1 10 11 13 13 24 35 35 36 36 39 41 43 44 46 47 47 48 49 51 51 51 51 54 54 55 58 58 61 62 63 63 64 64 65 65 Rev. 3.0, 04/02, page v of xxxviii 3.5 3.6 3.7 3.4.2 Instruction TLB (ITLB) Configuration ................................................................ 3.4.3 Address Translation Method ................................................................................ MMU Functions ................................................................................................................ 3.5.1 MMU Hardware Management ............................................................................. 3.5.2 MMU Software Management............................................................................... 3.5.3 MMU Instruction (LDTLB) ................................................................................. 3.5.4 Hardware ITLB Miss Handling............................................................................ 3.5.5 Avoiding Synonym Problems .............................................................................. MMU Exceptions .............................................................................................................. 3.6.1 Instruction TLB Multiple Hit Exception .............................................................. 3.6.2 Instruction TLB Miss Exception .......................................................................... 3.6.3 Instruction TLB Protection Violation Exception.................................................. 3.6.4 Data TLB Multiple Hit Exception........................................................................ 3.6.5 Data TLB Miss Exception.................................................................................... 3.6.6 Data TLB Protection Violation Exception ........................................................... 3.6.7 Initial Page Write Exception ................................................................................ Memory-Mapped TLB Configuration ............................................................................... 3.7.1 ITLB Address Array............................................................................................. 3.7.2 ITLB Data Array 1 ............................................................................................... 3.7.3 ITLB Data Array 2 ............................................................................................... 3.7.4 UTLB Address Array ........................................................................................... 3.7.5 UTLB Data Array 1.............................................................................................. 3.7.6 UTLB Data Array 2.............................................................................................. Section 4 4.1 4.2 4.3 4.4 69 69 72 72 72 72 73 74 75 75 75 76 77 78 79 79 80 81 82 83 83 85 86 Caches ................................................................................................................ 87 Overview ........................................................................................................................... 87 4.1.1 Features ................................................................................................................ 87 4.1.2 Register Configuration ......................................................................................... 88 Register Descriptions......................................................................................................... 89 Operand Cache (OC) ......................................................................................................... 91 4.3.1 Configuration ....................................................................................................... 91 4.3.2 Read Operation..................................................................................................... 94 4.3.3 Write Operation.................................................................................................... 95 4.3.4 Write-Back Buffer................................................................................................ 97 4.3.5 Write-Through Buffer .......................................................................................... 97 4.3.6 RAM Mode .......................................................................................................... 97 4.3.7 OC Index Mode.................................................................................................... 99 4.3.8 Coherency between Cache and External Memory ............................................... 99 4.3.9 Prefetch Operation................................................................................................ 99 Instruction Cache (IC) ....................................................................................................... 99 4.4.1 Configuration ....................................................................................................... 99 4.4.2 Read Operation..................................................................................................... 102 4.4.3 IC Index Mode ..................................................................................................... 102 Rev. 3.0, 04/02, page vi of xxxviii 4.5 4.6 4.7 Memory-Mapped Cache Configuration (SH7751) ............................................................ 103 4.5.1 IC Address Array ................................................................................................. 103 4.5.2 IC Data Array ....................................................................................................... 104 4.5.3 OC Address Array ................................................................................................ 105 4.5.4 OC Data Array ..................................................................................................... 106 Memory-Mapped Cache Configuration (SH7751R) ......................................................... 107 4.6.1 IC Address Array ................................................................................................. 108 4.6.2 IC Data Array ....................................................................................................... 109 4.6.3 OC Address Array ................................................................................................ 110 4.6.4 OC Data Array ..................................................................................................... 111 4.6.5 Summary of Memory-Mapped OC Addresses ..................................................... 112 Store Queues ..................................................................................................................... 113 4.7.1 SQ Configuration ................................................................................................. 113 4.7.2 SQ Writes ............................................................................................................. 113 4.7.3 Transfer to External Memory ............................................................................... 113 4.7.4 Determination of SQ Access Exception ............................................................... 115 4.7.5 SQ Read (SH7751R only) .................................................................................... 115 4.7.6 SQ Usage Notes ................................................................................................... 116 Section 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Exceptions......................................................................................................... 119 Overview ........................................................................................................................... 119 5.1.1 Features ................................................................................................................ 119 5.1.2 Register Configuration ......................................................................................... 119 Register Descriptions......................................................................................................... 120 Exception Handling Functions .......................................................................................... 121 5.3.1 Exception Handling Flow..................................................................................... 121 5.3.2 Exception Handling Vector Addresses................................................................. 121 Exception Types and Priorities.......................................................................................... 122 Exception Flow ................................................................................................................. 125 5.5.1 Exception Flow .................................................................................................... 125 5.5.2 Exception Source Acceptance .............................................................................. 126 5.5.3 Exception Requests and BL Bit............................................................................ 128 5.5.4 Return from Exception Handling ......................................................................... 128 Description of Exceptions ................................................................................................. 128 5.6.1 Resets ................................................................................................................... 129 5.6.2 General Exceptions .............................................................................................. 134 5.6.3 Interrupts .............................................................................................................. 148 5.6.4 Priority Order with Multiple Exceptions.............................................................. 151 Usage Notes....................................................................................................................... 152 Restrictions........................................................................................................................ 153 Section 6 6.1 Floating-Point Unit ........................................................................................ 155 Overview ........................................................................................................................... 155 Rev. 3.0, 04/02, page vii of xxxviii 6.2 6.3 6.4 6.5 6.6 Data Formats ..................................................................................................................... 155 6.2.1 Floating-Point Format .......................................................................................... 155 6.2.2 Non-Numbers (NaN)............................................................................................ 157 6.2.3 Denormalized Numbers........................................................................................ 158 Registers ............................................................................................................................ 159 6.3.1 Floating-Point Registers ....................................................................................... 159 6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................. 161 6.3.3 Floating-Point Communication Register (FPUL)................................................. 162 Rounding ........................................................................................................................... 162 Floating-Point Exceptions ................................................................................................. 163 Graphics Support Functions .............................................................................................. 164 6.6.1 Geometric Operation Instructions ........................................................................ 164 6.6.2 Pair Single-Precision Data Transfer ..................................................................... 166 Section 7 7.1 7.2 7.3 Instruction Set .................................................................................................. 167 Execution Environment..................................................................................................... 167 Addressing Modes............................................................................................................. 169 Instruction Set ................................................................................................................... 173 Section 8 8.1 8.2 8.3 Pipelining .......................................................................................................... 187 Pipelines ............................................................................................................................ 187 Parallel-Executability ........................................................................................................ 194 Execution Cycles and Pipeline Stalling............................................................................. 198 Section 9 9.1 9.2 9.3 9.4 9.5 Power-Down Modes ...................................................................................... 215 Overview ........................................................................................................................... 215 9.1.1 Types of Power-Down Modes.............................................................................. 215 9.1.2 Register Configuration ......................................................................................... 217 9.1.3 Pin Configuration ................................................................................................. 217 Register Descriptions......................................................................................................... 218 9.2.1 Standby Control Register (STBCR) ..................................................................... 218 9.2.2 Peripheral Module Pin High Impedance Control ................................................. 220 9.2.3 Peripheral Module Pin Pull-Up Control ............................................................... 220 9.2.4 Standby Control Register 2 (STBCR2) ................................................................ 221 9.2.5 Clock Stop Register 00 (CLKSTP00) .................................................................. 222 9.2.6 Clock Stop Clear Register 00 (CLKSTPCLR00) ................................................. 223 Sleep Mode........................................................................................................................ 224 9.3.1 Transition to Sleep Mode ..................................................................................... 224 9.3.2 Exit from Sleep Mode .......................................................................................... 224 Deep Sleep Mode .............................................................................................................. 224 9.4.1 Transition to Deep Sleep Mode............................................................................ 224 9.4.2 Exit from Deep Sleep Mode................................................................................. 225 Pin Sleep Mode ................................................................................................................. 225 Rev. 3.0, 04/02, page viii of xxxviii 9.6 9.7 9.8 9.9 9.5.1 Transition to Pin Sleep Mode............................................................................... 225 9.5.2 Exit from Pin Sleep Mode .................................................................................... 225 Standby Mode ................................................................................................................... 225 9.6.1 Transition to Standby Mode ................................................................................. 225 9.6.2 Exit from Standby Mode ...................................................................................... 226 9.6.3 Clock Pause Function........................................................................................... 227 Module Standby Function ................................................................................................. 227 9.7.1 Transition to Module Standby Function............................................................... 227 9.7.2 Exit from Module Standby Function.................................................................... 228 Hardware Standby Mode................................................................................................... 229 9.8.1 Transition to Hardware Standby Mode ................................................................ 229 9.8.2 Exit from Hardware Standby Mode ..................................................................... 229 9.8.3 Usage Notes.......................................................................................................... 230 STATUS Pin Change Timing............................................................................................ 230 9.9.1 In Reset................................................................................................................. 230 9.9.2 In Exit from Standby Mode.................................................................................. 231 9.9.3 In Exit from Sleep Mode ...................................................................................... 233 9.9.4 In Exit from Deep Sleep Mode............................................................................. 236 9.9.5 Hardware Standby Mode Timing ......................................................................... 238 Section 10 Clock Oscillation Circuits ............................................................................ 241 10.1 Overview ........................................................................................................................... 241 10.1.1 Features ................................................................................................................ 241 10.2 Overview of CPG .............................................................................................................. 243 10.2.1 Block Diagram of CPG ........................................................................................ 243 10.2.2 CPG Pin Configuration ........................................................................................ 246 10.2.3 CPG Register Configuration ................................................................................ 246 10.3 Clock Operating Modes..................................................................................................... 247 10.4 CPG Register Description ................................................................................................. 249 10.4.1 Frequency Control Register (FRQCR) ................................................................. 249 10.5 Changing the Frequency.................................................................................................... 251 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)............ 251 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)............. 251 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)....................... 252 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off) ...................... 252 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio................................ 252 10.6 Output Clock Control ........................................................................................................ 253 10.7 Overview of Watchdog Timer........................................................................................... 253 10.7.1 Block Diagram ..................................................................................................... 253 10.7.2 Register Configuration ......................................................................................... 254 10.8 WDT Register Descriptions .............................................................................................. 254 10.8.1 Watchdog Timer Counter (WTCNT) ................................................................... 254 10.8.2 Watchdog Timer Control/Status Register (WTCSR) ........................................... 255 Rev. 3.0, 04/02, page ix of xxxviii 10.8.3 Notes on Register Access ..................................................................................... 257 10.9 Using the WDT ................................................................................................................. 258 10.9.1 Standby Clearing Procedure................................................................................. 258 10.9.2 Frequency Changing Procedure ........................................................................... 258 10.9.3 Using Watchdog Timer Mode.............................................................................. 259 10.9.4 Using Interval Timer Mode.................................................................................. 259 10.10 Notes on Board Design...................................................................................................... 260 Section 11 Realtime Clock (RTC) .................................................................................. 263 11.1 Overview ........................................................................................................................... 263 11.1.1 Features ................................................................................................................ 263 11.1.2 Block Diagram ..................................................................................................... 264 11.1.3 Pin Configuration ................................................................................................. 265 11.1.4 Register Configuration ......................................................................................... 265 11.2 Register Descriptions......................................................................................................... 267 11.2.1 64 Hz Counter (R64CNT) .................................................................................... 267 11.2.2 Second Counter (RSECCNT)............................................................................... 267 11.2.3 Minute Counter (RMINCNT) .............................................................................. 268 11.2.4 Hour Counter (RHRCNT) .................................................................................... 268 11.2.5 Day-of-Week Counter (RWKCNT) ..................................................................... 269 11.2.6 Day Counter (RDAYCNT) .................................................................................. 270 11.2.7 Month Counter (RMONCNT).............................................................................. 270 11.2.8 Year Counter (RYRCNT) .................................................................................... 271 11.2.9 Second Alarm Register (RSECAR)...................................................................... 272 11.2.10 Minute Alarm Register (RMINAR) ..................................................................... 272 11.2.11 Hour Alarm Register (RHRAR) ........................................................................... 273 11.2.12 Day-of-Week Alarm Register (RWKAR) ............................................................ 273 11.2.13 Day Alarm Register (RDAYAR) ......................................................................... 274 11.2.14 Month Alarm Register (RMONAR)..................................................................... 275 11.2.15 RTC Control Register 1 (RCR1) .......................................................................... 275 11.2.16 RTC Control Register 2 (RCR2) .......................................................................... 277 11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only) .................................................................................................. 280 11.3 Operation........................................................................................................................... 281 11.3.1 Time Setting Procedures ...................................................................................... 281 11.3.2 Time Reading Procedures .................................................................................... 282 11.3.3 Alarm Function .................................................................................................... 284 11.4 Interrupts ........................................................................................................................... 285 11.5 Usage Notes....................................................................................................................... 285 11.5.1 Register Initialization ........................................................................................... 285 11.5.2 Carry Flag and Interrupt Flag in Standby Mode................................................... 285 11.5.3 Crystal Oscillator Circuit...................................................................................... 285 Rev. 3.0, 04/02, page x of xxxviii Section 12 Timer Unit (TMU) ......................................................................................... 287 12.1 Overview ........................................................................................................................... 287 12.1.1 Features ................................................................................................................ 287 12.1.2 Block Diagram ..................................................................................................... 288 12.1.3 Pin Configuration ................................................................................................. 288 12.1.4 Register Configuration ......................................................................................... 289 12.2 Register Descriptions......................................................................................................... 290 12.2.1 Timer Output Control Register (TOCR) .............................................................. 290 12.2.2 Timer Start Register (TSTR) ................................................................................ 291 12.2.3 Timer Start Register 2 (TSTR2) ........................................................................... 292 12.2.4 Timer Constant Registers (TCOR) ....................................................................... 293 12.2.5 Timer Counters (TCNT)....................................................................................... 293 12.2.6 Timer Control Registers (TCR)............................................................................ 294 12.2.7 Input Capture Register (TCPR2) .......................................................................... 297 12.3 Operation........................................................................................................................... 298 12.3.1 Counter Operation ................................................................................................ 298 12.3.2 Input Capture Function......................................................................................... 301 12.4 Interrupts ........................................................................................................................... 302 12.5 Usage Notes....................................................................................................................... 303 12.5.1 Register Writes..................................................................................................... 303 12.5.2 TCNT Register Reads .......................................................................................... 303 12.5.3 Resetting the RTC Frequency Divider ................................................................. 303 12.5.4 External Clock Frequency .................................................................................... 303 Section 13 Bus State Controller (BSC) ......................................................................... 305 13.1 Overview ........................................................................................................................... 305 13.1.1 Features ................................................................................................................ 305 13.1.2 Block Diagram ..................................................................................................... 307 13.1.3 Pin Configuration ................................................................................................. 308 13.1.4 Register Configuration ......................................................................................... 310 13.1.5 Overview of Areas ............................................................................................... 311 13.1.6 PCMCIA Support................................................................................................. 314 13.2 Register Descriptions......................................................................................................... 318 13.2.1 Bus Control Register 1 (BCR1)............................................................................ 318 13.2.2 Bus Control Register 2 (BCR2)............................................................................ 326 13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only) ............................................... 327 13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only) ............................................... 329 13.2.5 Wait Control Register 1 (WCR1) ......................................................................... 331 13.2.6 Wait Control Register 2 (WCR2) ......................................................................... 334 13.2.7 Wait Control Register 3 (WCR3) ......................................................................... 342 13.2.8 Memory Control Register (MCR) ........................................................................ 344 13.2.9 PCMCIA Control Register (PCR) ........................................................................ 350 13.2.10 Synchronous DRAM Mode Register (SDMR)..................................................... 352 Rev. 3.0, 04/02, page xi of xxxviii 13.2.11 Refresh Timer Control/Status Register (RTCSR) ................................................ 354 13.2.12 Refresh Timer Counter (RTCNT) ........................................................................ 356 13.2.13 Refresh Time Constant Register (RTCOR).......................................................... 357 13.2.14 Refresh Count Register (RFCR)........................................................................... 358 13.2.15 Notes on Accessing Refresh Control Registers .................................................... 358 13.3 Operation........................................................................................................................... 359 13.3.1 Endian/Access Size and Data Alignment ............................................................. 359 13.3.2 Areas .................................................................................................................... 366 13.3.3 SRAM Interface ................................................................................................... 370 13.3.4 DRAM Interface................................................................................................... 378 13.3.5 Synchronous DRAM Interface............................................................................. 393 13.3.6 Burst ROM Interface ............................................................................................ 419 13.3.7 PCMCIA Interface ............................................................................................... 422 13.3.8 MPX Interface ...................................................................................................... 433 13.3.9 Byte Control SRAM Interface.............................................................................. 451 13.3.10 Waits between Access Cycles .............................................................................. 455 13.3.11 Bus Arbitration..................................................................................................... 457 13.3.12 Master Mode ........................................................................................................ 460 13.3.13 Slave Mode........................................................................................................... 461 13.3.14 Cooperation between Master and Slave ............................................................... 461 13.3.15 Notes on Usage..................................................................................................... 462 Section 14 Direct Memory Access Controller (DMAC) .......................................... 463 14.1 Overview ........................................................................................................................... 463 14.1.1 Features ................................................................................................................ 463 14.1.2 Block Diagram (SH7751)..................................................................................... 466 14.1.3 Pin Configuration (SH7751) ................................................................................ 467 14.1.4 Register Configuration (SH7751) ........................................................................ 468 14.2 Register Descriptions......................................................................................................... 470 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........................................... 470 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 471 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......................... 472 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 473 14.2.5 DMA Operation Register (DMAOR) ................................................................... 481 14.3 Operation........................................................................................................................... 483 14.3.1 DMA Transfer Procedure..................................................................................... 483 14.3.2 DMA Transfer Requests....................................................................................... 486 14.3.3 Channel Priorities................................................................................................. 490 14.3.4 Types of DMA Transfer ....................................................................................... 493 14.3.5 Number of Bus Cycle States and
 Pin Sampling Timing........................... 502 14.3.6 Ending DMA Transfer ......................................................................................... 516 14.4 Examples of Use................................................................................................................ 519 Rev. 3.0, 04/02, page xii of xxxviii 14.5 14.6 14.7 14.8 14.9 14.4.1 Examples of Transfer between External Memory and an External Device with DACK .......................................................................................................... 519 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 520 14.5.1 Operation.............................................................................................................. 520 14.5.2 Pins in DDT Mode ............................................................................................... 522 14.5.3 Transfer Request Acceptance on Each Channel................................................... 525 14.5.4 Notes on Use of DDT Module ............................................................................. 547 Configuration of the DMAC (SH7751R) .......................................................................... 550 14.6.1 Block Diagram of the DMAC .............................................................................. 550 14.6.2 Pin Configuration (SH7751R).............................................................................. 551 14.6.3 Register Configuration (SH7751R)...................................................................... 552 Register Descriptions (SH7751R) ..................................................................................... 555 14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7)........................................... 555 14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7) .................................. 555 14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7) ......................... 556 14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7) ................................... 556 14.7.5 DMA Operation Register (DMAOR) ................................................................... 559 Operation (SH7751R)........................................................................................................ 562 14.8.1 Channel Specification for a Normal DMA Transfer ............................................ 562 14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 562 14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 562 14.8.4 Clearing Request Queues by DTR Format ........................................................... 563 14.8.5 Interrupt-Request Codes....................................................................................... 564 Usage Notes....................................................................................................................... 567 Section 15 Serial Communication Interface (SCI) ..................................................... 569 15.1 Overview ........................................................................................................................... 569 15.1.1 Features ................................................................................................................ 569 15.1.2 Block Diagram ..................................................................................................... 571 15.1.3 Pin Configuration ................................................................................................. 572 15.1.4 Register Configuration ......................................................................................... 572 15.2 Register Descriptions......................................................................................................... 573 15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 573 15.2.2 Receive Data Register (SCRDR1)........................................................................ 573 15.2.3 Transmit Shift Register (SCTSR1)....................................................................... 574 15.2.4 Transmit Data Register (SCTDR1) ...................................................................... 574 15.2.5 Serial Mode Register (SCSMR1) ......................................................................... 575 15.2.6 Serial Control Register (SCSCR1) ....................................................................... 577 15.2.7 Serial Status Register (SCSSR1) .......................................................................... 581 15.2.8 Serial Port Register (SCSPTR1)........................................................................... 585 15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 589 15.3 Operation........................................................................................................................... 597 15.3.1 Overview .............................................................................................................. 597 Rev. 3.0, 04/02, page xiii of xxxviii 15.3.2 Operation in Asynchronous Mode........................................................................ 599 15.3.3 Multiprocessor Communication Function ............................................................ 609 15.3.4 Operation in Synchronous Mode.......................................................................... 618 15.4 SCI Interrupt Sources and DMAC..................................................................................... 627 15.5 Usage Notes....................................................................................................................... 628 Section 16 Serial Communication Interface with FIFO (SCIF) ............................. 633 16.1 Overview ........................................................................................................................... 633 16.1.1 Features ................................................................................................................ 633 16.1.2 Block Diagram ..................................................................................................... 635 16.1.3 Pin Configuration ................................................................................................. 636 16.1.4 Register Configuration ......................................................................................... 636 16.2 Register Descriptions......................................................................................................... 637 16.2.1 Receive Shift Register (SCRSR2) ........................................................................ 637 16.2.2 Receive FIFO Data Register (SCFRDR2)............................................................ 637 16.2.3 Transmit Shift Register (SCTSR2)....................................................................... 638 16.2.4 Transmit FIFO Data Register (SCFTDR2) .......................................................... 638 16.2.5 Serial Mode Register (SCSMR2) ......................................................................... 639 16.2.6 Serial Control Register (SCSCR2) ....................................................................... 641 16.2.7 Serial Status Register (SCFSR2) .......................................................................... 644 16.2.8 Bit Rate Register (SCBRR2) ................................................................................ 650 16.2.9 FIFO Control Register (SCFCR2)........................................................................ 651 16.2.10 FIFO Data Count Register (SCFDR2) ................................................................. 654 16.2.11 Serial Port Register (SCSPTR2)........................................................................... 655 16.2.12 Line Status Register (SCLSR2)............................................................................ 662 16.3 Operation........................................................................................................................... 663 16.3.1 Overview .............................................................................................................. 663 16.3.2 Serial Operation.................................................................................................... 664 16.4 SCIF Interrupt Sources and the DMAC ............................................................................ 675 16.5 Usage Notes....................................................................................................................... 676 Section 17 Smart Card Interface ...................................................................................... 679 17.1 Overview ........................................................................................................................... 679 17.1.1 Features ................................................................................................................ 679 17.1.2 Block Diagram ..................................................................................................... 680 17.1.3 Pin Configuration ................................................................................................. 681 17.1.4 Register Configuration ......................................................................................... 681 17.2 Register Descriptions......................................................................................................... 682 17.2.1 Smart Card Mode Register (SCSCMR1).............................................................. 682 17.2.2 Serial Mode Register (SCSMR1) ......................................................................... 683 17.2.3 Serial Control Register (SCSCR1) ....................................................................... 684 17.2.4 Serial Status Register (SCSSR1) .......................................................................... 685 17.3 Operation........................................................................................................................... 686 Rev. 3.0, 04/02, page xiv of xxxviii 17.3.1 Overview .............................................................................................................. 686 17.3.2 Pin Connections.................................................................................................... 687 17.3.3 Data Format.......................................................................................................... 688 17.3.4 Register Settings................................................................................................... 689 17.3.5 Clock .................................................................................................................... 691 17.3.6 Data Transfer Operations ..................................................................................... 694 17.4 Usage Notes....................................................................................................................... 701 Section 18 I/O Ports ............................................................................................................ 707 18.1 Overview ........................................................................................................................... 707 18.1.1 Features ................................................................................................................ 707 18.1.2 Block Diagrams.................................................................................................... 708 18.1.3 Pin Configuration ................................................................................................. 715 18.1.4 Register Configuration ......................................................................................... 718 18.2 Register Descriptions......................................................................................................... 719 18.2.1 Port Control Register A (PCTRA) ....................................................................... 719 18.2.2 Port Data Register A (PDTRA) ............................................................................ 720 18.2.3 Port Control Register B (PCTRB) ........................................................................ 720 18.2.4 Port Data Register B (PDTRB) ............................................................................ 722 18.2.5 GPIO Interrupt Control Register (GPIOIC) ......................................................... 722 18.2.6 Serial Port Register (SCSPTR1)........................................................................... 723 18.2.7 Serial Port Register (SCSPTR2)........................................................................... 725 Section 19 Interrupt Controller (INTC) ......................................................................... 729 19.1 Overview ........................................................................................................................... 729 19.1.1 Features ................................................................................................................ 729 19.1.2 Block Diagram ..................................................................................................... 729 19.1.3 Pin Configuration ................................................................................................. 731 19.1.4 Register Configuration ......................................................................................... 731 19.2 Interrupt Sources ............................................................................................................... 732 19.2.1 NMI Interrupt ....................................................................................................... 732 19.2.2 IRL Interrupts....................................................................................................... 733 19.2.3 On-Chip Peripheral Module Interrupts................................................................. 735 19.2.4 Interrupt Exception Handling and Priority ........................................................... 736 19.3 Register Descriptions......................................................................................................... 739 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ............................................... 739 19.3.2 Interrupt Control Register (ICR) .......................................................................... 740 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00).................................... 742 19.3.4 Interrupt Factor Register 00 (INTREQ00) ........................................................... 743 19.3.5 Interrupt Mask Register 00 (INTMSK00) ............................................................ 744 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00)........................................... 745 19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 bit allocation............................. 746 19.4 INTC Operation................................................................................................................. 747 Rev. 3.0, 04/02, page xv of xxxviii 19.4.1 Interrupt Operation Sequence............................................................................... 747 19.4.2 Multiple Interrupts................................................................................................ 749 19.4.3 Interrupt Masking with MAI Bit .......................................................................... 749 19.5 Interrupt Response Time ................................................................................................... 750 Section 20 User Break Controller (UBC) ..................................................................... 751 20.1 Overview ........................................................................................................................... 751 20.1.1 Features ................................................................................................................ 751 20.1.2 Block Diagram ..................................................................................................... 752 20.2 Register Descriptions......................................................................................................... 754 20.2.1 Access to UBC Registers ..................................................................................... 754 20.2.2 Break Address Register A (BARA) ..................................................................... 755 20.2.3 Break ASID Register A (BASRA) ....................................................................... 756 20.2.4 Break Address Mask Register A (BAMRA) ........................................................ 756 20.2.5 Break Bus Cycle Register A (BBRA) .................................................................. 757 20.2.6 Break Address Register B (BARB) ...................................................................... 759 20.2.7 Break ASID Register B (BASRB) ....................................................................... 759 20.2.8 Break Address Mask Register B (BAMRB)......................................................... 759 20.2.9 Break Data Register B (BDRB) ........................................................................... 759 20.2.10 Break Data Mask Register B (BDMRB) .............................................................. 760 20.2.11 Break Bus Cycle Register B (BBRB)................................................................... 761 20.2.12 Break Control Register (BRCR)........................................................................... 761 20.3 Operation........................................................................................................................... 763 20.3.1 Explanation of Terms Relating to Accesses ......................................................... 763 20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 764 20.3.3 User Break Operation Sequence........................................................................... 765 20.3.4 Instruction Access Cycle Break............................................................................ 766 20.3.5 Operand Access Cycle Break ............................................................................... 767 20.3.6 Condition Match Flag Setting .............................................................................. 768 20.3.7 Program Counter (PC) Value Saved..................................................................... 768 20.3.8 Contiguous A and B Settings for Sequential Conditions...................................... 769 20.3.9 Usage Notes.......................................................................................................... 770 20.4 User Break Debug Support Function................................................................................. 771 20.5 Examples of Use................................................................................................................ 773 20.6 User Break Controller Stop Function ................................................................................ 775 20.6.1 Transition to User Break Controller Stopped State .............................................. 775 20.6.2 Cancelling the User Break Controller Stopped State ........................................... 775 20.6.3 Examples of Stopping and Restarting the User Break Controller ........................ 776 Section 21 Hitachi User Debug Interface (H-UDI).................................................... 777 21.1 Overview ........................................................................................................................... 777 21.1.1 Features ................................................................................................................ 777 21.1.2 Block Diagram ..................................................................................................... 777 Rev. 3.0, 04/02, page xvi of xxxviii 21.1.3 Pin Configuration ................................................................................................. 779 21.1.4 Register Configuration ......................................................................................... 780 21.2 Register Descriptions......................................................................................................... 781 21.2.1 Instruction Register (SDIR).................................................................................. 781 21.2.2 Data Register (SDDR).......................................................................................... 782 21.2.3 Bypass Register (SDBPR).................................................................................... 782 21.2.4 Interrupt Factor Register (SDINT) ....................................................................... 783 21.2.5 Boundary Scan Register (SDBSR) ....................................................................... 783 21.3 Operation........................................................................................................................... 798 21.3.1 TAP Control ......................................................................................................... 798 21.3.2 H-UDI Reset......................................................................................................... 799 21.3.3 H-UDI Interrupt.................................................................................................... 799 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) ............................. 800 21.4 Usage Notes....................................................................................................................... 800 Section 22 PCI Controller (PCIC)................................................................................... 801 22.1 Overview ........................................................................................................................... 801 22.1.1 Features ................................................................................................................ 801 22.1.2 Block Diagram ..................................................................................................... 803 22.1.3 Pin Configuration ................................................................................................. 804 22.1.4 Register Configuration ......................................................................................... 805 22.2 PCIC Register Descriptions............................................................................................... 811 22.2.1 PCI Configuration Register 0 (PCICONF0)......................................................... 811 22.2.2 PCI Configuration Register 1 (PCICONF1)......................................................... 812 22.2.3 PCI Configuration Register 2 (PCICONF2)......................................................... 817 22.2.4 PCI Configuration Register 3 (PCICONF3)......................................................... 819 22.2.5 PCI Configuration Register 4 (PCICONF4)......................................................... 821 22.2.6 PCI Configuration Register 5 (PCICONF5)......................................................... 823 22.2.7 PCI Configuration Register 6 (PCICONF6)......................................................... 825 22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10) ...................................................................................................... 827 22.2.9 PCI Configuration Register 11 (PCICONF11)..................................................... 828 22.2.10 PCI Configuration Register 12 (PCICONF12)..................................................... 829 22.2.11 PCI Configuration Register 13 (PCICONF13)..................................................... 830 22.2.12 PCI Configuration Register 14 (PCICONF14)..................................................... 831 22.2.13 PCI Configuration Register 15 (PCICONF15)..................................................... 832 22.2.14 PCI Configuration Register 16 (PCICONF16)..................................................... 834 22.2.15 PCI Configuration Register 17 (PCICONF17)..................................................... 836 22.2.16 Reserved Area ...................................................................................................... 838 22.2.17 PCI Control Register (PCICR) ............................................................................. 839 22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0]) .................................................. 842 22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0]) .............................................. 844 22.2.20 PCI Interrupt Register (PCIINT) .......................................................................... 846 Rev. 3.0, 04/02, page xvii of xxxviii 22.3 22.4 22.5 22.6 22.2.21 PCI Interrupt Mask Register (PCIINTM)............................................................. 848 22.2.22 PCI Address Data Register at Error (PCIALR).................................................... 850 22.2.23 PCI Command Data Register at Error (PCICLR)................................................. 851 22.2.24 PCI Arbiter Interrupt Register (PCIAINT)........................................................... 853 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) ............................................. 855 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ............................................... 856 22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT)...................................... 857 22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0]) ........................ 858 22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) ..... 859 22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0])................................ 860 22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0]) .............................................. 862 22.2.32 PIO Address Register (PCIPAR).......................................................................... 865 22.2.33 Memory Space Base Register (PCIMBR) ............................................................ 867 22.2.34 I/O Space Base Register (PCIIOBR).................................................................... 868 22.2.35 PCI Power Management Interrupt Register (PCIPINT) ....................................... 870 22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM).......................... 871 22.2.37 PCI Clock Control Register (PCICLKR) ............................................................. 872 22.2.38 PCIC-BSC Registers ............................................................................................ 873 22.2.39 Port Control Register (PCIPCTR) ........................................................................ 874 22.2.40 Port Data Register (PCIPDTR) ............................................................................ 877 22.2.41 PIO Data Register (PCIPDR) ............................................................................... 878 Description of Operation ................................................................................................... 879 22.3.1 Operating Modes .................................................................................................. 879 22.3.2 PCI Commands .................................................................................................... 880 22.3.3 PCIC Initialization................................................................................................ 881 22.3.4 Local Register Access .......................................................................................... 882 22.3.5 Host Functions...................................................................................................... 882 22.3.6 PCI Bus Arbitration in Non-host Mode................................................................ 885 22.3.7 PIO Transfers ....................................................................................................... 885 22.3.8 Target Transfers ................................................................................................... 888 22.3.9 DMA Transfers .................................................................................................... 891 22.3.10 Transfer Contention within PCIC......................................................................... 897 22.3.11 PCI Bus Basic Interface ....................................................................................... 898 Endians .............................................................................................................................. 910 22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules .......................... 910 22.4.2 Endian Control for Local Bus .............................................................................. 912 22.4.3 Endian Control in DMA Transfers ....................................................................... 912 22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write)................... 914 22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write) ................................... 917 22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write) . 917 Resetting............................................................................................................................ 919 Interrupts ........................................................................................................................... 920 22.6.1 Interrupts from PCIC to CPU ............................................................................... 920 Rev. 3.0, 04/02, page xviii of xxxviii 22.7 22.8 22.9 22.10 22.11 22.6.2 Interrupts from External PCI Devices .................................................................. 921 22.6.3  .................................................................................................................... 921 Error Detection .................................................................................................................. 922 PCIC Clock ....................................................................................................................... 922 Power Management........................................................................................................... 923 22.9.1 Power Management Overview ............................................................................. 923 22.9.2 Stopping the Clock ............................................................................................... 924 22.9.3 Compatibility with Standby and Sleep ................................................................. 927 Port Functions ................................................................................................................... 927 Version Management ........................................................................................................ 928 Section 23 Electrical Characteristics .............................................................................. 929 23.1 Absolute Maximum Ratings.............................................................................................. 929 23.2 DC Characteristics............................................................................................................. 930 23.3 AC Characteristics............................................................................................................. 948 23.3.1 Clock and Control Signal Timing ........................................................................ 950 23.3.2 Control Signal Timing.......................................................................................... 961 23.3.3 Bus Timing........................................................................................................... 964 23.3.4 Peripheral Module Signal Timing ..................................................................... 1015 23.3.5 AC Characteristic Test Conditions.................................................................... 1027 23.3.6 Change in Delay Time Based on Load Capacitance ......................................... 1028 Appendix A Address List .............................................................................................. 1031 Appendix B Package Dimensions .............................................................................. 1039 Appendix C Mode Pin Settings ................................................................................... 1041 Appendix D Pin Functions............................................................................................ 1044 D.1 D.2 Pin States ........................................................................................................................ 1044 Handling of Unused Pins................................................................................................ 1048 Appendix E Synchronous DRAM Address Multiplexing Tables.................... 1050 Appendix F Instruction Prefetching and Its Side Effects .................................... 1061 Appendix G Power-On and Power-Off Procedures .............................................. 1062 Appendix H List of Models .......................................................................................... 1063 Rev. 3.0, 04/02, page xix of xxxviii Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Block Diagram of SH7751 Series Functions ................................................... Pin Arrangement (256-Pin QFP)...................................................................... Pin Arrangement (256-Pin BGA) .................................................................... Data Formats.................................................................................................... CPU Register Configuration in Each Processor Mode .................................... General Registers ............................................................................................. Floating-Point Registers................................................................................... Data Formats In Memory................................................................................. Processor State Transitions .............................................................................. Role of the MMU............................................................................................. MMU-Related Registers .................................................................................. Physical Address Space (MMUCR.AT = 0) .................................................... P4 Area ............................................................................................................ External Memory Space................................................................................... Virtual Address Space (MMUCR.AT = 1) ...................................................... UTLB Configuration........................................................................................ Relationship between Page Size and Address Format ..................................... ITLB Configuration ......................................................................................... Flowchart of Memory Access Using UTLB .................................................... Flowchart of Memory Access Using ITLB...................................................... Operation of LDTLB Instruction ..................................................................... Memory-Mapped ITLB Address Array ........................................................... Memory-Mapped ITLB Data Array 1.............................................................. Memory-Mapped ITLB Data Array 2.............................................................. Memory-Mapped UTLB Address Array.......................................................... Memory-Mapped UTLB Data Array 1 ............................................................ Memory-Mapped UTLB Data Array 2 ............................................................ Cache and Store Queue Control Registers (CCR)............................................ Configuration of Operand Cache (SH7751) .................................................... Configuration of Operand Cache (SH7751R).................................................. Configuration of Write-Back Buffer................................................................ Configuration of Write-Through Buffer .......................................................... Configuration of Instruction Cache (SH7751) ................................................. Configuration of Instruction Cache (SH7751R) .............................................. Memory-Mapped IC Address Array ................................................................ Memory-Mapped IC Data Array...................................................................... Memory-Mapped OC Address Array .............................................................. Memory-Mapped OC Data Array .................................................................... Memory-Mapped IC Address Array ................................................................ Memory-Mapped IC Data Array...................................................................... Memory-Mapped OC Address Array .............................................................. Memory-Mapped OC Data Array .................................................................... Rev. 3.0, 04/02, page xx of xxxviii 10 11 12 35 38 40 42 47 49 53 55 59 60 61 62 65 66 69 70 71 73 81 82 83 84 85 86 89 92 93 97 97 100 101 104 105 106 107 109 110 111 112 Figure 4.16 Figure 5.1 Figure 5.2 Figure 5.3 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 8.1 Figure 8.2 Figure 8.3 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 10.1(1) Figure 10.1(2) Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Store Queue Configuration .............................................................................. Register Bit Configurations ............................................................................. Instruction Execution and Exception Handling ............................................... Example of General Exception Acceptance Order .......................................... Format of Single-Precision Floating-Point Number ........................................ Format of Double-Precision Floating-Point Number....................................... Single-Precision NaN Bit Pattern..................................................................... Floating-Point Registers................................................................................... Basic Pipelines ................................................................................................. Instruction Execution Patterns ......................................................................... Examples of Pipelined Execution .................................................................... STATUS Output in Power-On Reset ............................................................... STATUS Output in Manual Reset ................................................................... STATUS Output in Standby  Interrupt Sequence ........................................ STATUS Output in Standby  Power-On Reset Sequence ............................ STATUS Output in Standby  Manual Reset Sequence ................................ STATUS Output in Sleep  Interrupt Sequence ............................................ STATUS Output in Sleep  Power-On Reset Sequence ................................ STATUS Output in Sleep  Manual Reset Sequence .................................... STATUS Output in Deep Sleep  Interrupt Sequence ................................... STATUS Output in Deep Sleep  Power-On Reset Sequence....................... STATUS Output in Deep Sleep  Manual Reset Sequence ........................... Hardware Standby Mode Timing (When CA = Low in Normal Operation) ... Hardware Standby Mode Timing (When CA = Low in WDT Operation)....... Timing When Power Other than VDD-RTC is Off ......................................... Timing When VDD-RTC Power is Off  On ................................................ Block Diagram of CPG (SH7751) ................................................................... Block Diagram of CPG (SH7751R)................................................................. Block Diagram of WDT................................................................................... Writing to WTCNT and WTCSR .................................................................... Points for Attention when Using Crystal Resonator ........................................ Points for Attention when Using PLL Oscillator Circuit ................................. Block Diagram of RTC.................................................................................... Examples of Time Setting Procedures ............................................................. Examples of Time Reading Procedures ........................................................... Example of Use of Alarm Function ................................................................. Example of Crystal Oscillator Circuit Connection .......................................... Block Diagram of TMU................................................................................... Example of Count Operation Setting Procedure .............................................. TCNT Auto-Reload Operation......................................................................... Count Timing when Operating on Internal Clock............................................ Count Timing when Operating on External Clock........................................... Count Timing when Operating on On-Chip RTC Output Clock ..................... 113 120 125 127 155 156 158 160 188 189 201 230 231 231 232 233 233 234 235 236 236 237 238 239 239 240 243 244 253 257 260 261 264 281 283 284 286 288 299 299 300 300 301 Rev. 3.0, 04/02, page xxi of xxxviii Figure 12.7 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19(1) Figure 13.19(2) Figure 13.19(3) Figure 13.19(4) Figure 13.20 Figure 13.21 Figure 13.22 Figure 13.23 Figure 13.24 Figure 13.25 Figure 13.26 Figure 13.27 Figure 13.28 Figure 13.29 Figure 13.30 Figure 13.31 Figure 13.32 Figure 13.33 Operation Timing when Using Input Capture Function................................... Block Diagram of BSC .................................................................................... Correspondence between Virtual Address Space and External Memory Space External Memory Space Allocation ................................................................. Example of 
Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) ...................................................... Writing to RTCSR, RTCNT, RTCOR, and RFCR .......................................... Basic Timing of SRAM Interface .................................................................... Example of 32-Bit Data Width SRAM Connection......................................... Example of 16-Bit Data Width SRAM Connection......................................... Example of 8-Bit Data Width SRAM Connection........................................... SRAM Interface Wait Timing (Software Wait Only) ...................................... SRAM Interface Wait State Timing (Wait State Insertion by 
Signal).... SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) .... Example of DRAM Connection (32-Bit Data Width, Area 3)......................... Basic DRAM Access Timing........................................................................... DRAM Wait State Timing ............................................................................... DRAM Burst Access Timing ........................................................................... DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) ..................... Burst Access Timing in DRAM EDO Mode ................................................... DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)............................................................. DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)............................................................. DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, Anw = 0) .................................................................... DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, Anw = 0) .................................................................... CAS-Before-RAS Refresh Operation .............................................................. DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ....... DRAM Self-Refresh Cycle Timing ................................................................. Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... Basic Timing for Synchronous DRAM Burst Read......................................... Basic Timing for Synchronous DRAM Single Read ....................................... Basic Timing for Synchronous DRAM Burst Write ........................................ Basic Timing for Synchronous DRAM Single Write ...................................... Burst Read Timing........................................................................................... Burst Read Timing (RAS Down, Same Row Address).................................... Burst Read Timing (RAS Down, Different Row Addresses) .......................... Burst Write Timing .......................................................................................... Burst Write Timing (Same Row Address) ....................................................... Burst Write Timing (Different Row Addresses) .............................................. Rev. 3.0, 04/02, page xxii of xxxviii 302 307 311 313 330 359 371 372 373 374 375 376 377 378 380 381 382 383 384 385 386 387 388 389 390 392 394 396 398 399 401 403 404 405 406 407 408 Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle ............................................................................................. 410 Figure 13.35 Auto-Refresh Operation................................................................................... 411 Figure 13.36 Synchronous DRAM Auto-Refresh Timing .................................................... 412 Figure 13.37 Synchronous DRAM Self-Refresh Timing ...................................................... 413 Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 415 Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ............... 416 Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) 417 Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM .................................. 418 Figure 13.41 Burst ROM Basic Access Timing .................................................................... 420 Figure 13.42 Burst ROM Wait Access Timing ..................................................................... 421 Figure 13.43 Burst ROM Wait Access Timing ..................................................................... 421 Figure 13.44 Example of PCMCIA Interface........................................................................ 426 Figure 13.45 Basic Timing for PCMCIA Memory Card Interface ....................................... 427 Figure 13.46 Wait Timing for PCMCIA Memory Card Interface......................................... 428 Figure 13.47 PCMCIA Space Allocation.............................................................................. 429 Figure 13.48 Basic Timing for PCMCIA I/O Card Interface................................................ 430 Figure 13.49 Wait Timing for PCMCIA I/O Card Interface ................................................. 431 Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface........................ 432 Figure 13.51 Example of 32-Bit Data Width MPX Connection ........................................... 434 Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) .......................................... 435 Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) ..................................... 436 Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) ......................................... 437 Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) .................................... 438 Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait)............................................ 439 Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control)..................................... 440 Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait) ........................................... 441 Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control).................................... 442 Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)............................................................................. 443 Figure 13.61 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)............................................................................. 444 Rev. 3.0, 04/02, page xxiii of xxxviii Figure 13.62 Figure 13.63 Figure 13.64 Figure 13.65 Figure 13.66 Figure 13.67 Figure 13.68 Figure 13.69 Figure 13.70 Figure 13.71 Figure 13.72 Figure 13.73 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)............................................................................. 445 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)............................................................................. 446 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 447 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 448 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 449 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) .......................................................................... 450 Example of 52-Bit Data Width Byte Control SRAM....................................... 451 Byte Control SRAM Basic Read Cycle (No Wait) .......................................... 452 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)................. 453 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) ................................................................................................................ 454 Waits between Access Cycles.......................................................................... 456 Arbitration Sequence ....................................................................................... 459 Block Diagram of DMAC................................................................................ 466 DMAC Transfer Flowchart.............................................................................. 485 Round Robin Mode.......................................................................................... 491 Example of Changes in Priority Order in Round Robin Mode ........................ 492 Data Flow in Single Address Mode ................................................................. 494 DMA Transfer Timing in Single Address Mode ............................................. 495 Operation in Dual Address Mode .................................................................... 496 Example of Transfer Timing in Dual Address Mode....................................... 497 Example of DMA Transfer in Cycle Steal Mode............................................. 498 Example of DMA Transfer in Burst Mode ...................................................... 498 Bus Handling with Two DMAC Channels Operating ..................................... 502 Dual Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Level Detection), DACK (Read Cycle) .............................................. 505 Dual Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Edge Detection), DACK (Read Cycle) ............................................... 506 Dual Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection), DACK (Read Cycle) .............................................. 507 Rev. 3.0, 04/02, page xxiv of xxxviii Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32 Figure 14.33 Figure 14.34 Figure 14.35 Figure 14.36 Figure 14.37 Figure 14.38 Figure 14.39 Dual Address Mode/Burst Mode External Bus  External Bus/
 (Edge Detection), DACK (Read Cycle) ............................................... 508 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)  External Bus..................................................................................................... 509 Dual Address Mode/Cycle Steal Mode External Bus  On-Chip SCI (Level Detection) ............................................................................................. 510 Single Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Level Detection) ............................................................................................. 511 Single Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Edge Detection) .............................................................................................. 512 Single Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection) ............................................................................................. 513 Single Address Mode/Burst Mode External Bus  External Bus/
 (Edge Detection) .............................................................................................. 514 Single Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM: Row Hit Write) ................................................................................................ 515 On-Demand Transfer Mode Block Diagram.................................................... 520 System Configuration in On-Demand Data Transfer Mode ............................ 522 Data Transfer Request Format ......................................................................... 523 Single Address Mode/Synchronous DRAM  External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS latency=3, TPC=3)........................................................................................... 526 Single Address Mode/External Device  Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1, TRWL=2, TPC=1) ........................................................................................... 527 Dual Address Mode/Synchronous DRAM SRAM Longword Transfer ...... 528 Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529 Single Address Mode/Burst Mode/External Device  External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .................................... 529 Single Address Mode/Burst Mode/External Bus  External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer ............................................... 530 Single Address Mode/Burst Mode/External Device  External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer ............................................... 531 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 532 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) .......................................................................................................... 533 Read from Synchronous DRAM Precharge Bank............................................ 534 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)................ 534 Read from Synchronous DRAM (Row Hit)..................................................... 535 Write to Synchronous DRAM Precharge Bank ............................................... 535 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) ................... 536 Rev. 3.0, 04/02, page xxv of xxxviii Figure 14.40 Figure 14.41 Figure 14.42 Figure 14.43 Figure 14.44 Figure 14.45 Figure 14.46 Figure 14.47 Figure 14.48 Figure 14.49 Figure 14.50 Figure 14.51 Figure 14.52 Figure 14.53 Figure 14.54 Figure 14.55 Figure 14.56 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Write to Synchronous DRAM (Row Hit) ........................................................ Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .................................... DDT Mode Setting........................................................................................... Single Address Mode/Burst Mode/Edge Detection/ External Device  External Bus Data Transfer.............................................................................. Single Address Mode/Burst Mode/Level Detection/ External Bus  External Device Data Transfer ....................................................................................... Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus  External Device Data Transfer ............................ Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device  External Bus Data Transfer ............................ Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus........................................................ Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus  External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus ................................................................................... Single Address Mode/Burst Mode/External Bus  External Device Data Transfer/Direct Data Transfer Request to Channel 2....................................... Single Address Mode/Burst Mode/External Device  External Bus Data Transfer/Direct Data Transfer Request to Channel 2....................................... Single Address Mode/Burst Mode/External Bus  External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 . Single Address Mode/Burst Mode/External Device  External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 . Block Diagram of the DMAC.......................................................................... DTR Format (Transfer Request Format) (SH7751R) ...................................... Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer .................................... Single Address Mode/Cycle Steal Mode/External Bus  External Device/ 32-Byte Block Transfer/On-Demand Data Transfer on Channel 4.................. Block Diagram of SCI ..................................................................................... SCK Pin ........................................................................................................... TxD Pin............................................................................................................ RxD Pin............................................................................................................ Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)...................................................................................... Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) ..................................................................................... Sample SCI Initialization Flowchart................................................................ Sample Serial Transmission Flowchart............................................................ Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)............................................. Rev. 3.0, 04/02, page xxvi of xxxviii 536 537 538 538 539 539 540 541 542 543 544 545 546 550 560 565 566 571 58 7 588 588 599 601 602 603 605 Figure 15.10 Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Figure 15.19 Figure 15.20 Figure 15.21 Figure 15.22 Figure 15.23 Figure 15.24 Figure 15.25 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9 Figure 16.10 Figure 16.11 Figure 16.11 Figure 16.12 Figure 16.13 Figure 16.14 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Sample Serial Reception Flowchart (1) ........................................................... Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ................................................................................................... Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)..................................... Sample Multiprocessor Serial Transmission Flowchart................................... Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ................................................................... Sample Multiprocessor Serial Reception Flowchart (1) .................................. Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ................................................................... Data Format in Synchronous Communication ................................................. Sample SCI Initialization Flowchart................................................................ Sample Serial Transmission Flowchart............................................................ Example of SCI Transmit Operation ............................................................... Sample Serial Reception Flowchart (1) ........................................................... Example of SCI Receive Operation ................................................................. Sample Flowchart for Serial Data Transmission and Reception...................... Receive Data Sampling Timing in Asynchronous Mode................................. Example of Synchronous Transmission by DMAC......................................... Block Diagram of SCIF ................................................................................... MD8/RTS2 Pin ................................................................................................ MD7/CTS2 Pin ................................................................................................ MD1/TxD2 Pin ................................................................................................ MD2/RxD2 Pin ................................................................................................ MD0/SCK2 Pin................................................................................................ Sample SCIF Initialization Flowchart.............................................................. Sample Serial Transmission Flowchart............................................................ Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) ................................................................................................... Example of Operation Using Modem Control (CTS2) .................................... Sample Serial Reception Flowchart (1) ........................................................... Sample Serial Reception Flowchart (2) ........................................................... Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ................................................................................................... Example of Operation Using Modem Control (RTS2) .................................... Receive Data Sampling Timing in Asynchronous Mode................................. Block Diagram of Smart Card Interface .......................................................... Schematic Diagram of Smart Card Interface Pin Connections ........................ Smart Card Interface Data Format ................................................................... TEND Generation Timing ............................................................................... Sample Start Character Waveforms ................................................................. Difference in Clock Output According to GM Bit Setting .............................. 606 609 610 612 614 615 617 618 620 621 622 623 625 626 630 631 635 658 659 660 660 661 667 668 670 670 671 672 674 674 677 680 687 688 690 691 693 Rev. 3.0, 04/02, page xxvii of xxxviii Figure 17.7 Figure 17.8 Figure 17.9 Figure 17.10 Figure 17.11 Figure 17.12 Figure 17.13 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Figure 18.10 Figure 19.1 Figure 19.2 Figure 19.3 Figure 20.1 Figure 20.2 Figure 21.1 Figure 21.2 Figure 21.3 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 22.8 Figure 22.9 Figure 22.10 Figure 22.11 Figure 22.12 Figure 22.13 Figure 22.14 Figure 22.15 Figure 22.16 Figure 22.17 Figure 22.18 Sample Initialization Flowchart ....................................................................... Sample Transmission Processing Flowchart.................................................... Sample Reception Processing Flowchart ......................................................... Receive Data Sampling Timing in Smart Card Mode...................................... Retransfer Operation in SCI Receive Mode..................................................... Retransfer Operation in SCI Transmit Mode ................................................... Procedure for Stopping and Restarting the Clock............................................ 16-Bit Port A.................................................................................................... 16-Bit Port B.................................................................................................... SCK Pin ........................................................................................................... TxD Pin............................................................................................................ RxD Pin............................................................................................................ MD1/TxD2 Pin ................................................................................................ MD2/RxD2 Pin ................................................................................................ MD0/SCK2 Pin................................................................................................ MD7/CTS2 Pin ................................................................................................ MD8/RTS2 Pin ................................................................................................ Block Diagram of INTC .................................................................................. Example of IRL Interrupt Connection ............................................................. Interrupt Operation Flowchart ......................................................................... Block Diagram of User Break Controller ........................................................ User Break Debug Support Function Flowchart .............................................. Block Diagram of H-UDI Circuit .................................................................... TAP Control State Transition Diagram............................................................ H-UDI Reset .................................................................................................... PCIC Block Diagram ....................................................................................... PIO Memory Space Access.............................................................................. PIO I/O Space Access ...................................................................................... Local Address Space Accessing Method ......................................................... Example of DMA Transfer Control Register Settings ..................................... Example of DMA Transfer Flowchart ............................................................. Master Write Cycle in Host Mode (Single) ..................................................... Master Read Cycle in Host Mode (Single) ...................................................... Master Memory Write Cycle in Non-Host Mode (Burst) ................................ Master Memory Read Cycle in Non-Host Mode (Burst) ................................. Target Read Cycle in Non-Host Mode (Single)............................................... Target Write Cycle in Non-Host Mode (Single).............................................. Target Memory Read Cycle in Host Mode (Burst).......................................... Target Memory Write Cycle in Host Mode (Burst) ......................................... Master Memory Write Cycle in Host Mode (Burst, With Stepping) ............... Target Memory Read Cycle in Host Mode (Burst, With Stepping)................. Endian Conversion Modes for Peripheral Bus................................................. Peripheral Bus  PCI Bus Data Alignment.................................................... Rev. 3.0, 04/02, page xxviii of xxxviii 695 697 699 701 702 703 704 708 709 710 711 711 712 712 713 714 715 730 733 748 752 772 778 798 799 803 887 888 889 893 895 899 900 901 902 904 905 906 907 908 909 910 911 Figure 22.19 Figure 22.20 Figure 22.21(1) Figure 22.21(2) Figure 22.22 Figure 22.23 Endian Control for Local Bus .......................................................................... 912 Data Alignment at DMA Transfer ................................................................... 913 Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............ 915 Data Alignment at Target Memory Transfer (Little-Endian Local Bus).......... 916 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) . 917 Data Alignment at Target Configuration Transfer (Both Big Endian and Little Endian) ............................................................... . 918 Figure 23.1 EXTAL Clock Input Timing............................................................................ 956 Figure 23.2(1) CKIO Clock Output Timing ............................................................................ 956 Figure 23.2(2) CKIO Clock Output Timing ............................................................................ 956 Figure 23.3 Power-On Oscillation Settling Time................................................................ 957 Figure 23.4 Standby Return Oscillation Settling Time (Return by   or  ).. 957 Figure 23.5 Power-On Oscillation Settling Time................................................................ 958 Figure 23.6 Standby Return Oscillation Settling Time (Return by   or  ).. 958 Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) ........................... 959 Figure 23.8 Standby Return Oscillation Settling Time (Return by  –) ................ 959 Figure 23.9 PLL Synchronization Settling Time in Case of     or NMI Interrupt................................................................................................... 960 Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt ......................... 960 Figure 23.11 Control Signal Timing ..................................................................................... 963 Figure 23.12 Pin Drive Timing for Standby Mode ............................................................... 963 Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) ............................................... 968 Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ................................ 969 Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) 970 Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1)........................................................................... 971 Figure 23.17 Burst ROM Bus Cycle (No Wait) .................................................................... 972 Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) .............................................................. 973 Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1)........................................................................................... 974 Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ................... 975 Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)......................... 976 Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) .......................... 977 Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD [1:0] = 01, CAS Latency = 3) ...................................................... 978 Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) ...... 979 Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3) ................................................................................. 980 Rev. 3.0, 04/02, page xxix of xxxviii Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ...................... 981 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)........................ 982 Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD [1:0] = 01, TRWL [2:0] = 010).................................................... 983 Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010).... 984 Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL [2:0] = 010)............................................................................... 985 Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) ..... 986 Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001) 987 Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001).................. 988 Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)................... 989 Figure 23.34(b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)...................... 990 Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 ................................. 991 Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)................ 992 Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001)................ 993 Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001)................ 994 Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)...................................... 995 Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000)............................................ 996 Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000)............................................ 997 Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ........ 998 Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) ........ 999 Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)...................................... 1000 Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)..................................... 1001 Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)..................................... 1002 Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 000, TRC [2:0] = 001) ............................................................. 1003 Rev. 3.0, 04/02, page xxx of xxxviii Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) ............................................................. 1004 Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)........................... 1005 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait.................................................................................................................. 1006 Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait.................................................................................................................. 1007 Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing).............. 1008 Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) .................................... 1009 Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) .................................... 1010 Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait + One External Wait).................................................................................................. 1011 Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control) ................................................................................................... 1012 Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) ..................... 1013 Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01) ................ 1014 Figure 23.59 TCLK Input Timing......................................................................................... 1019 Figure 23.60 RTC Oscillation Settling Time at Power-On ................................................... 1019 Figure 23.61 SCK Input Clock Timing ................................................................................. 1019 Figure 23.62 SCI I/O Synchronous Mode Clock Timing...................................................... 1019 Figure 23.63 I/O Port Input/Output Timing .......................................................................... 1020 Figure 23.64(a)
/DRAK Timing ..................................................................................... 1020 Figure 23.64(b)
/ Input Timing and  Output Timing .................................... 1020 Figure 23.65 TCK Input Timing ........................................................................................... 1021 Figure 23.66   Hold Timing........................................................................................ 1021 Rev. 3.0, 04/02, page xxxi of xxxviii Figure 23.67 Figure 23.68 Figure 23.69 Figure 23.70 Figure 23.71 Figure 23.72 Figure 23.73 Figure 23.74 Figure 23.75 Figure B.1 Figure B.2 Figure F.1 Figure G.1 H-UDI Data Transfer Timing .......................................................................... 1021 Pin Break Timing............................................................................................. 1021 NMI Input Timing ........................................................................................... 1022 PCI Clock Input Timing................................................................................... 1025 Output Signal Timing ...................................................................................... 1025 Output Signal Timing ...................................................................................... 1026 I/O Port Input/Output Timing .......................................................................... 1027 Output Load Circuit ......................................................................................... 1028 Load CapacitanceDelay Time........................................................................ 1029 Package Dimensions (256-pin QFP)................................................................ 1039 Package Dimensions (256-pin BGA)............................................................... 1040 Instruction Prefetch.......................................................................................... 1061 Power-On and Power-Off Procedures.............................................................. 1062 Rev. 3.0, 04/02, page xxxii of xxxviii Tables Table 1.1 Table 1.2 Table 1.3 Table 2.1 Table 3.1 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 7.1 Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Table 7.10 Table 7.11 Table 7.12 Table 8.1 Table 8.2 Table 8.3 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 10.2 Table 10.3(1) Table 10.3(2) Table 10.4 Table 10.5 Table 11.1 Table 11.2 SH7751 Series Features...................................................................................... Pin Functions...................................................................................................... Pin Functions...................................................................................................... Initial Register Values ........................................................................................ MMU Registers .................................................................................................. Cache Features (SH7751)................................................................................... Cache Features (SH7751R) ................................................................................ Store Queue Features ......................................................................................... Cache Control Registers..................................................................................... Exception-Related Registers .............................................................................. Exceptions .......................................................................................................... Types of Reset.................................................................................................... Floating-Point Number Formats and Parameters ............................................... Floating-Point Ranges ........................................................................................ Addressing Modes and Effective Addresses ...................................................... Notation Used in Instruction List ....................................................................... Fixed-Point Transfer Instructions....................................................................... Arithmetic Operation Instructions...................................................................... Logic Operation Instructions.............................................................................. Shift Instructions ................................................................................................ Branch Instructions ............................................................................................ System Control Instructions ............................................................................... Floating-Point Single-Precision Instructions...................................................... Floating-Point Double-Precision Instructions .................................................... Floating-Point Control Instructions.................................................................... Floating-Point Graphics Acceleration Instructions ............................................ Instruction Groups.............................................................................................. Parallel-Executability ......................................................................................... Execution Cycles................................................................................................ Status of CPU and Peripheral Modules in Power-Down Modes ........................ Power-Down Mode Registers............................................................................. Power-Down Mode Pins .................................................................................... State of Registers in Standby Mode ................................................................... CPG Pins ............................................................................................................ CPG Register...................................................................................................... Clock Operating Modes (SH7751)..................................................................... Clock Operating Modes (SH7751R) .................................................................. FRQCR Settings and Internal Clock Frequencies .............................................. WDT Registers................................................................................................... RTC Pins ............................................................................................................ RTC Registers .................................................................................................... 2 13 24 37 54 87 88 88 88 119 122 130 156 157 169 173 174 176 178 179 180 181 183 184 184 185 194 198 205 216 217 217 226 246 246 247 247 248 254 265 265 Rev. 3.0, 04/02, page xxxiii of xxxviii Table 11.3 Table 12.1 Table 12.2 Table 12.3 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Table 13.11 Table 13.12 Table 13.13 Table 13.14 Table 13.15 Table 13.16 Table 13.17 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Table 14.16 Table 14.17 Table 14.18 Table 14.19 Table 15.1 Crystal Oscillator Circuit Constants (Recommended Values) ........................... TMU Pins ........................................................................................................... TMU Registers ................................................................................................... TMU Interrupt Sources ...................................................................................... BSC Pins ............................................................................................................ BSC Registers .................................................................................................... External Memory Space Map............................................................................. PCMCIA Interface Features............................................................................... PCMCIA Support Interfaces .............................................................................. Idle Insertion between Accesses......................................................................... When MPX Interface is Set (Areas 0 to 6)......................................................... 32-Bit External Device/Big-Endian Access and Data Alignment ...................... 16-Bit External Device/Big-Endian Access and Data Alignment ...................... 8-Bit External Device/Big-Endian Access and Data Alignment ........................ 32-Bit External Device/Little-Endian Access and Data Alignment ................... 16-Bit External Device/Little-Endian Access and Data Alignment ................... 8-Bit External Device/Little-Endian Access and Data Alignment ..................... Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing Example of Correspondence between SH7751 Series and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) ......... Cycles in Which Pipelined Access Can Be Used ............................................... Relationship between Address and CE When Using PCMCIA Interface .......... DMAC Pins ........................................................................................................ DMAC Pins in DDT Mode ................................................................................ DMAC Registers ................................................................................................ Selecting External Request Mode with RS Bits ................................................. Selecting On-Chip Peripheral Module Request Mode with RS Bits .................. Supported DMA Transfers ................................................................................. Relationship between DMA Transfer Type, Request Mode, and Bus Mode ..... External Request Transfer Sources and Destinations in Normal Mode ............. External Request Transfer Sources and Destinations in DDT Mode ................. Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings ............................................ Usable SZ, ID, and MD Combination in DDT Mode......................................... DMAC Pins ........................................................................................................ DMAC Pins in DDT Mode ................................................................................ Register Configuration ....................................................................................... Channel Selection by DTR Format (DMAOR.DBL = 1)................................... Notification of Transfer Channel in Eight-Channel DDT Mode........................ Function of  ............................................................................................. DTR Format for Clearing Request Queues ........................................................ DMAC Interrupt-Request Codes........................................................................ SCI Pins.............................................................................................................. Rev. 3.0, 04/02, page xxxiv of xxxviii 285 288 289 303 308 310 312 314 315 333 341 360 361 362 363 364 365 379 395 409 424 467 468 468 487 489 493 499 500 501 519 524 551 552 553 560 563 563 564 565 572 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 15.6 Table 15.7 Table 15.8 Table 15.9 Table 15.10 Table 15.11 Table 15.12 Table 15.13 Table 16.1 Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Table 17.5 Table 17.6 Table 17.7 Table 17.8 Table 17.9 Table 18.1 Table 18.2 Table 18.3 Table 18.4 Table 19.1 Table 19.2 Table 19.3 Table 19.4 Table 19.5 Table 19.6 Table 19.7 Table 19.8 Table 20.1 Table 21.1 Table 21.2 SCI Registers...................................................................................................... Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode................ Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)........................................................................................ Maximum Bit Rate with External Clock Input (Asynchronous Mode).............. Maximum Bit Rate with External Clock Input (Synchronous Mode) ................ SCSMR1 Settings for Serial Transfer Format Selection .................................... SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection...................... Serial Transfer Formats (Asynchronous Mode) ................................................. Receive Error Conditions ................................................................................... SCI Interrupt Sources ......................................................................................... SCSSR1 Status Flags and Transfer of Receive Data.......................................... SCIF Pins............................................................................................................ SCIF Registers.................................................................................................... SCSMR2 Settings for Serial Transfer Format Selection .................................... SCSCR2 Settings for SCIF Clock Source Selection .......................................... Serial Transfer Formats ...................................................................................... SCIF Interrupt Sources....................................................................................... Smart Card Interface Pins................................................................................... Smart Card Interface Registers........................................................................... Smart Card Interface Register Settings .............................................................. Values of n and Corresponding CKS1 and CKS0 Settings ................................ Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)... Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ................ Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ........ Register Settings and SCK Pin State .................................................................. Smart Card Mode Operating States and Interrupt Sources................................. 32-Bit General-Purpose I/O Port Pins ................................................................ SCI I/O Port Pins................................................................................................ SCIF I/O Port Pins.............................................................................................. I/O Port Registers ............................................................................................... INTC Pins........................................................................................................... INTC Registers...................................................................................................  – Pins and Interrupt Levels................................................................ Interrupt Exception Handling Sources and Priority Order ................................. Interrupt Request Sources and IPRA–IPRD Registers ....................................... Interrupt Request Sources and INTPRI00 Register............................................ Bit Allocation ..................................................................................................... Interrupt Response Time .................................................................................... UBC Registers.................................................................................................... H-UDI Pins......................................................................................................... H-UDI Registers................................................................................................. 572 591 594 595 596 596 598 598 600 608 627 628 636 636 663 664 665 675 681 681 689 691 692 692 692 693 700 715 717 717 718 731 731 734 737 740 743 746 750 753 779 780 Rev. 3.0, 04/02, page xxxv of xxxviii Table 21.3 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 Table 23.1 Table 23.2 Table 23.3 Table 23.4 Table 23.5 Table 23.6 Table 23.7 Table 23.8 Table 23.9 Table 23.10 Table 23.11 Table 23.12 Table 23.13 Table 23.14 Table 23.15 Table 23.16 Table 23.17 Table 23.18 Table 23.19 Table 23.20 Table 23.21 Table 23.22 Table 23.23 Table 23.24 Table 23.25 Table 23.26 Table 23.27 Structure of Boundary Scan Register ................................................................. Pin Configuration ............................................................................................... List of PCI Configuration Registers ................................................................... PCI Configuration Register Configuration......................................................... List of PCIC Local Registers.............................................................................. List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)............................. Memory Space Base Address Register (BASE0)............................................... Memory Space Base Address Register (BASE1)............................................... Operating Modes ................................................................................................ PCI Command Support ...................................................................................... Access Size......................................................................................................... DMA Transfer Access Size and Endian Conversion Mode ............................... Target Transfer Access Size and Endian Conversion Mode .............................. Interrupts ............................................................................................................ Method of Stopping Clock per Operating Mode ................................................ Absolute Maximum Ratings............................................................................... DC Characteristics (HD6417751RBP240)......................................................... DC Characteristics (HD6417751RF240) ........................................................... DC Characteristics (HD6417751RBP200)......................................................... DC Characteristics (HD6417751RF200) ........................................................... DC Characteristics (HD6417751BP167) ........................................................... DC Characteristics (HD6417751BP167I) .......................................................... DC Characteristics (HD6417751F167) .............................................................. DC Characteristics (HD6417751F167I)............................................................. DC Characteristics (HD6417751VF133) ........................................................... Permissible Output Currents .............................................................................. Clock Timing (HD6417751RBP240)................................................................. Clock Timing (HD6417751RF240) ................................................................... Clock Timing (HD6417751RBP200)................................................................. Clock Timing (HD6417751RF200) ................................................................... Clock Timing (HD6417751BP167(I), HD6417751F167(I)).............................. Clock Timing (HD6417751VF133) ................................................................... Clock and Control Signal Timing (HD6417751RBP240).................................. Clock and Control Signal Timing (HD6417751RF240) .................................... Clock and Control Signal Timing (HD6417751RBP200).................................. Clock and Control Signal Timing (HD6417751RF200) .................................... Clock and Control Signal Timing (HD6417751BP167, HD6417751F167, HD6417751BP167I, HD6417751F167I) ........................................................... Clock and Control Signal Timing (HD6417751VF133) .................................... Control Signal Timing (1) .................................................................................. Control Signal Timing (2) .................................................................................. Bus Timing (1) ................................................................................................... Bus Timing (2) ................................................................................................... Rev. 3.0, 04/02, page xxxvi of xxxviii 784 804 806 807 808 818 824 826 879 880 911 913 914 920 925 929 930 932 934 936 938 940 942 944 946 948 948 948 949 949 949 949 950 951 952 953 954 955 961 962 964 966 Table 23.28 Table 23.29 Table 23.30 Table 23.31 Table 23.32 Table 23.33 Table 23.34 Table A.1 Table C.1 Table C.2 Table C.3 Table C.4 Table C.5 Table C.6 Table C.7 Table D.1 Table D.2 Table D.3 Table D.4 Table H.1 Peripheral Module Signal Timing (1)................................................................. 1015 Peripheral Module Signal Timing (2)................................................................. 1017 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) ...................... 1023 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2) ...................... 1024 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1)....................................................................................... 1026 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2)....................................................................................... 1026 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) ........................................................................................... 1027 Address List........................................................................................................ 1031 Clock Operating Modes (SH7751)..................................................................... 1041 Clock Operating Modes (SH7751R) .................................................................. 1041 Area 0 Memory Map and Bus Width ................................................................. 1042 Endian ................................................................................................................ 1042 Master/Slave....................................................................................................... 1042 Clock Input......................................................................................................... 1042 PCI Mode ........................................................................................................... 1043 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common) .............................................................................................. 1044 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable). 1046 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) 1047 Handling of Pins When PCI is Not Used ........................................................... 1049 SH7751 Series Models ....................................................................................... 1063 Rev. 3.0, 04/02, page xxxvii of xxxviii Rev. 3.0, 04/02, page xxxviii of xxxviii Section 1 Overview 1.1 SH7751 Series Features The SH7751 Series microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. The SuperH * RISC engine is a Hitachi-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set.

The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry fullassociative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB. The SH7751 Series also feature a bus state controller (BSC) that can be directly coupled to DRAM (page/EDO) and synchronous DRAM without external circuitry. Also, because of its builtin functions, such as PCI bus controller, timers, and serial communications functions, required for multimedia and OA equipment, use of the SH7751 Series enable a dramatic reduction in system costs. The features of the SH7751 Series are summarized in table 1.1. Note: * SuperH is a trademark of Hitachi, Ltd. Rev. 3.0, 04/02, page 1 of 1064 Table 1.1 SH7751 Series Features Item Features LSI
Operating frequency: 240 MHz* /200 MHz* /167 MHz* /133 MHz*
Performance: 1 1 2 2  430 MIPS (240 MHz), 360 MIPS (200 MHz)  300 MIPS (167 MHz), 240 MIPS (133 MHz)  1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz)  1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
Superscalar architecture: Parallel execution of two instructions
Packages: 256-pin QFP, 256-pin BGA
External buses (SH buses)  Separate 26-bit address and 32-bit data buses  External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency
External bus (PCI bus):  32-bit address/data multiplexing  Selection of internal clock or external PCI-dedicated clock Rev. 3.0, 04/02, page 2 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features CPU
Original Hitachi SuperH architecture
32-bit internal data bus
General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers
RISC-type instruction set (upward-compatible with SuperH Series)  Fixed 16-bit instruction length for improved code efficiency  Load-store architecture  Delayed branch instructions  Conditional execution  C-based instruction set
Superscalar architecture (providing simultaneous execution of two instructions) including FPU
Instruction execution time: Maximum 2 instructions/cycle
Virtual address space: 4 Gbytes (448-Mbyte external memory space)
Space identifier ASIDs: 8 bits, 256 virtual address spaces
On-chip multiplier
Five-stage pipeline Rev. 3.0, 04/02, page 3 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features FPU
On-chip floating-point coprocessor
Supports single-precision (32 bits) and double-precision (64 bits)
Supports IEEE754-compliant data types and exceptions
Two rounding modes: Round to Nearest and Round to Zero
Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754
Floating-point registers: 32 bits  16 words  2 banks (single-precision  16 words or double-precision  8 words)  2 banks
32-bit CPU-FPU floating-point communication register (FPUL)
Supports FMAC (multiply-and-accumulate) instruction
Supports FDIV (divide) and FSQRT (square root) instructions
Supports FLDI0/FLDI1 (load constant 0/1) instructions
Instruction execution times  Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision)  Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only.
3-D graphics instructions (single-precision only):  4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency)  4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency)
Five-stage pipeline Rev. 3.0, 04/02, page 4 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features Clock pulse generator (CPG)
Choice of main clock  SH7751: 1/2, 1, 3, or 6 times EXTAL  SH7751R: 1, 6, or 12 times EXTAL
Clock modes: (Maximum frequency: Varies with models)  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock  Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock  Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
Power-down modes  Sleep mode  Deep sleep mode  Pin sleep mode  Standby mode  Hardware standby mode  Module standby function Memory management unit (MMU)
Single-channel watchdog timer
4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
Single virtual mode and multiple virtual memory mode
Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
4-entry fully-associative TLB for instructions
64-entry fully-associative TLB for instructions and operands
Supports software-controlled replacement and random-counter replacement algorithm
TLB contents can be accessed directly by address mapping Rev. 3.0, 04/02, page 5 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features Cache memory [SH7751]
Instruction cache (IC)  8 kbytes, direct mapping  256 entries, 32-byte block length  Normal mode (8-kbyte cache)  Index mode
Operand cache (OC)  16 kbytes, direct mapping  512 entries, 32-byte block length  Normal mode (16-kbyte cache)  Index mode  RAM mode (8-kbyte cache + 8-kbyte RAM)  Choice of write method (copy-back or write-through) Cache memory [SH7751R]
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping (usable as on-chip memory)
Store queue (32 bytes  2 entries)
Instruction cache (IC)  16 kbytes, 2-way set associative  256 entries/way, 32-byte block length  Cache-double-mode (16-kbyte cache)  Index mode  SH7751-compatible mode (8 kbytes, direct mapping)
Operand cache (OC)  32 kbytes, 2-way set associative  512 entries/way, 32-byte block length  Cache-double-mode (32-kbyte cache)  Index mode  RAM mode (16-kbyte cache + 16-kbyte RAM)  Choice of write method (copy-back or write-through)  SH7751-compatible mode (16 kbytes, direct mapping)
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping (usable as on-chip memory)
Store queue (32 bytes  2 entries) Rev. 3.0, 04/02, page 6 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features Interrupt controller (INTC)
Five independent external interrupts (NMI, IRL3 to IRL0)
15-level signed external interrupts: IRL3 to IRL0
On-chip peripheral module interrupts: Priority level can be set for each module
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size can all be set as break conditions
Supports sequential break function
Supports external memory access User break controller (UBC) Bus state controller (BSC)  32/16/8-bit external data bus
External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area:  Bus size (8, 16, or 32 bits)  Number of wait cycles (hardware wait function also supported)  Direct connection of DRAM, synchronous DRAM, and burst ROM possible by setting space type  Supports fast page mode and DRAM EDO  Supports PCMCIA interface  Chip select signals (
 to

) output for relevant areas DRAM/synchronous DRAM refresh functions  Programmable refresh interval  Supports CAS-before-RAS refresh mode and self-refresh mode
DRAM/synchronous DRAM burst access function
Big endian or little endian mode can be set Rev. 3.0, 04/02, page 7 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features Direct memory access controller (DMAC)
Physical address DMA controller  SH7751: 4-channel  SH7751R: 8-channel
Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
Address modes:  1-bus-cycle single address mode  2-bus-cycle dual address mode Timer unit (TMU)
Transfer requests: External, on-chip peripheral module, or auto-requests
Bus modes: Cycle-steal or burst mode
Supports on-demand data transfer mode (external bus 32 bit)
5-channel auto-reload 32-bit timer Input-capture function on one channel
Selection from 7 counter input clocks in 3 of 5 channels and from 5 counter input clocks on remaining 2 of 5 channels Realtime clock (RTC)
On-chip clock and calendar functions
Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution (cycle interrupts) Serial communication interface (SCI, SCIF)
Two full-duplex communication channels (SCI, SCIF)
Channel 1 (SCI):  Choice of asynchronous mode or synchronous mode  Supports smart card interface
Channel 2 (SCIF):  Supports asynchronous mode  Separate 16-byte FIFOs provided for transmitter and receiver Rev. 3.0, 04/02, page 8 of 1064 Table 1.1 SH7751 Series Features (cont) Item Features PCI bus controller (PCIC)
3 PCI bus controller (Rev.2.1-compatible)*  32-bit bus  33 MHz/66 MHz support
PCI master/slave support
PCI host function support  Built-in bus arbiter
4 built-in PCI-dedicated DMAC (direct memory access controller) channels  Each channel equipped with 64-byte FIFO
Selection of built-in clock or external PCI-dedicated clock
Interrupt requests can be sent to CPU Product lineup Abbreviation Voltage Operating Frequency Model No. Package SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA HD6417751F167 256-pin QFP SH7751R 1.5 V 133 MHz HD6417751VF133 1.5 V 240 MHz HD6417751RBP240 256-pin BGA HD6417751RF240 256-pin QFP HD6417751RBP200 256-pin BGA HD6417751RF200 256-pin QFP 200 MHz Note: *1 SH7751R only *2 SH7751 only *3 Some items are not compatible with PCI 2.1. For more information, see section 22.1.1, Features. Rev. 3.0, 04/02, page 9 of 1064 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the SH7751 Series. Cache and TLB controller 64-bit data (store) O cache 32-bit data CPG UTLB 32-bit data ITLB Upper 32-bit data FPU Lower 32-bit data 29-bit address I cache 32-bit data (store) UBC 32-bit data (load) 32-bit address (data) 32-bit data (instructions) 32-bit address (instructions) CPU SCI (SCIF) RTC Peripheral address bus Peripheral data bus INTC BSC DMAC TMU PCIC 32-bit data 32-bit data Address 32-bit data Address (PCI)DMAC External (SH) bus interface 32-bit PCI address/ data 26-bit SH bus address 32-bit SH bus data BSC: CPG: DMAC: FPU: INTC: ITLB: UTLB: RTC: SCI: SCIF: TMU: UBC: PCIC: Bus state controller Clock pulse generator Direct memory access controller Floating-point unit Interrupt controller Instruction TLB (translation lookaside buffer) Unified TLB (translation lookaside buffer) Realtime clock Serial communication interface Serial communication interface with FIFO Timer unit User break controller PCI bus controller Figure 1.1 Block Diagram of SH7751 Series Functions Rev. 3.0, 04/02, page 10 of 1064 , AD30 AD31 AD21 AD22 AD23 C/ AD24 AD25 AD26 AD27 AD28 AD29 , C/ AD16 AD17 AD18 AD19 AD20 AD11 AD12 AD13 AD14 AD15 C/ PAR , , 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 AD2 AD3 AD4 AD5 AD6 AD7 ,, ,, , , C/ AD8 AD9 AD10 Pin Arrangement AD0 AD1 1.3 , , , , VDDQ (IO) VSSQ (IO) ,, ,, , / / PCICLK IDSEL , , /MD9 /MD10 / / A25 A24 A23 A22 A21 A20 A19 A18 , D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 , D19 D18 D17 D16 /DQM3 /DQM2 A17 A16 A15 A14 , A13 A12 / TMS TCK VDD-PLL2 VSS-PLL2 VDD-PLL1 VSS-PLL1 VDD-CPG VSS-CPG XTAL EXTAL VSS (internal) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 A4 A5 A6 A7 A8 A9 A10 A11 /BRKACK TDO , A0 A1 A2 A3 STATUS0 STATUS1 VDD (internal) Reserved / CKE DACK0 DACK1 DRAK0 DRAK1 D11 D12 D13 D14 D15 /DQM0 /DQM1 RD/ CKIO Reserved AUDATA2 AUDATA3 Reserved MD3/ MD4/ MD5 , ,, (Top view) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 AUDATA0 AUDATA1 QFP256 D0 MD2/RXD2 RXD TCLK MD8/ SCK MD1/TXD2 MD0/SCK2 MD7/ AUDSYNC AUDCK / TXD TDI NMI / / MD6/ 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XTAL2 EXTAL2 VDD-RTC VSS-RTC CA Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. Figure 1.2 Pin Arrangement (256-Pin QFP) Rev. 3.0, 04/02, page 11 of 1064 1 2 3 4 5 6 7 8 A 9 10 11 12 13 14 15 16 17 18 19 20 ,, , ,, ,, , ,, ,, ,, ,, * B , C D E F G H J K ,,, ,,, ,, ,, ,, ,, ,, BGA256 (Top view) L M N P R ,, T U ,, V W Y , ,, ,, ,, VDDQ(IO) VSS (internal) VDD-CPG/RTC VSSQ(IO) VDD-PLL1/2 VSS-CPG/RTC VDD (internal) VSS-PLL1/2 NC Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used. * May be connected to VSSQ. Figure 1.3 Pin Arrangement (256-Pin BGA) Rev. 3.0, 04/02, page 12 of 1064 1.4 Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name I/O Function 1 TMS I Mode (H-UDI) 2 TCK I Clock (H-UDI) 3 VDDQ Power IO VDD 4 VSSQ Power IO GND 5 TDI I Data in (H-UDI) O Chip select 0 O Chip select 1 O Chip select 4 O Chip select 5 O Chip select 6 O Bus start O D7–D0 select signal Reset SRAM SDRAM PCMCIA MPX 12




  / 13  O D15-D8 select signal 14 D0 I/O Data 15 VDDQ Power IO VDD 16 VSSQ Power IO GND 17 VDD Power Internal VDD 18 VSS Power Internal GND 19 D1 I/O Data A1 20 D2 I/O Data A2 21 D3 I/O Data A3 22 D4 I/O Data A4 23 D5 I/O Data A5 24 D6 I/O Data A6 25 D7 I/O Data A7 6 7 8 9 10 11




 ( )  DRAM  ( ) ( )

 ( ) 




 ( )  A0 Rev. 3.0, 04/02, page 13 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 26 D8 I/O Data Reset SRAM DRAM SDRAM PCMCIA A8 MPX 27 D9 I/O Data A9 28 D10 I/O Data A10 29 VDDQ Power IO VDD 30 VSSQ Power IO GND 31 D11 I/O Data A11 32 D12 I/O Data A12 33 D13 I/O Data A13 34 D14 I/O Data A14 35 D15 I/O Data A15 36
/ O D7–D0 select signal O D15–D8 select signal Read/write DQM0 37
/ DQM1 38 RD/ O 39 CKIO O 40 Reserved 41 VDDQ Power IO VDD 42 VSSQ Power IO GND 43 Reserved 44 /
/  O 45 CKE O DQM1 RD/ RD/ RD/ CKIO Do not connect Read/
/  
 Clock output enable  O VDD Power Internal VDD VSS
 Clock output 47   CKE    (
)

 Power Internal GND 50

 O Chip select 3 51 A0 O Address 52 A1 O Address 53 A2 O Address 54 A3 O Address 55 VDDQ Power IO VDD 49 DQM0 Do not connect 46 48
 O Chip select 2 Rev. 3.0, 04/02, page 14 of 1064

 (
)

 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O 56 VSSQ Power IO GND 57 A4 O Address 58 A5 O Address 59 A6 O Address 60 A7 O Address 61 A8 O Address 62 A9 O Address 63 A10 O Address 64 A11 O Address 65 A12 O Address 66 A13 O Address 67 VDDQ Power IO VDD 68 VSSQ Power IO GND 69 A14 O Address 70 A15 O Address 71 A16 O Address 72 A17 O Address 73
/ O D23–D16 select signal O D31–D24 select signal DQM2 74
/ DQM3 Function Reset SRAM DRAM SDRAM
 DQM2
 DQM3 PCMCIA MPX 75 D16 I/O Data A16 76 D17 I/O Data A17 77 D18 I/O Data A18 78 D19 I/O Data A19 79 VDDQ Power IO VDD 80 VSSQ Power IO GND 81 VDD Power Internal VDD 82 VSS Power Internal GND 83 D20 I/O Data A20 84 D21 I/O Data A21 85 D22 I/O Data A22 86 D23 I/O Data A23 Rev. 3.0, 04/02, page 15 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 87 D24 I/O Data Reset SRAM DRAM SDRAM PCMCIA A24 MPX 88 D25 I/O Data A25 89 D26 I/O Data 90 D27 I/O Data 91 D28 I/O Data 92 D29 I/O Data 93 VDDQ Power IO VDD 94 VSSQ Power IO GND 95 D30 I/O Data ACCSIZE1 96 D31 I/O Data ACCSIZE2 97 VDD Power Internal VDD 98 VSS Power Internal GND 99 A18 O Address 100 A19 O Address 101 A20 O Address 102 A21 O Address 103 A22 O Address 104 A23 O Address 105 VDDQ Power IO VDD 106 VSSQ Power IO GND 107 A24 O Address 108 A25 O Address O D23–D16 select signal O D31–D24 select signal 109 110 / 
 / 
 111 VDD Power Internal VDD 112 VSS Power Internal GND 114  
  115 
  113 I Sleep O Bus grant (host function) O Bus grant (host function) Rev. 3.0, 04/02, page 16 of 1064 ACCSIZE0  
  
 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 116 
  O Bus grant (host function) 117 
 I* Bus request (host function) 118 
/ I* Bus request (host function)/ mode MD10 119 VDDQ Power IO VDD 120 VSSQ Power IO GND 121 
/ I* Bus request (host function)/ mode I Configuration device select O Interrupt (async) MD9 122 IDSEL 123  124 
 125 PCICLK O Reset output I PCI input clock 126 
 /  O Bus grant (host function)/ bus request 127 
/  I Bus request (host function) /bus grant 128 Reset SRAM DRAM SDRAM PCMCIA MPX MD10 MD9  I/O System error 129 AD31 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 130 AD30 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 131 VDDQ Power IO VDD (Port) (Port) (Port) (Port) (Port) 132 VSSQ Power IO GND 133 AD29 I/O PCI address/ data/port Rev. 3.0, 04/02, page 17 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. I/O Function SRAM DRAM SDRAM PCMCIA MPX 134 AD28 Pin Name I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 135 AD27 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 136 AD26 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 137 AD25 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 138 AD24 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 139 C/  I/O Command/byte enable 140 AD23 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 141 AD22 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 142 AD21 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 143 VDDQ Power IO VDD 144 VSSQ Power IO GND 145 VDD Power Internal VDD Reset 146 VSS Power Internal GND 147 AD20 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 148 AD19 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 149 AD18 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 150 AD17 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 151 AD16 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 152 C/  I/O Command/ byte enable I/O Bus cycle I/O Initiator ready I/O Target read 153 154 155 
   Rev. 3.0, 04/02, page 18 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 156  I/O Device select 157 VDDQ 158 VSSQ Reset SRAM DRAM SDRAM PCMCIA MPX Power IO VDD Power IO GND 159 
 I/O Transaction stop 160 

 I/O Exclusive access 161  I/O Parity error 162 PAR I/O Parity 163 C/  I/O Command/ byte enable 164 AD15 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 165 AD14 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 166 AD13 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 167 AD12 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 168 AD11 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 169 VDDQ Power IO VDD 170 VSSQ Power IO GND 171 AD10 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 172 AD9 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 173 AD8 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 174 C/  I/O Command/ byte enable 175 VDD Power Internal VDD 176 VSS Power Internal GND 177 AD7 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 178 AD6 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) Rev. 3.0, 04/02, page 19 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. I/O Function SRAM DRAM SDRAM PCMCIA MPX 179 AD5 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 180 AD4 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 181 AD3 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 182 AD2 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 183 VDDQ Power I/O VDD 184 VSSQ Power I/O GND 185 AD1 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 186 AD0 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I Interrupt 0 I Interrupt 1 I Interrupt 2 I Interrupt 3 187 188 189 190 Pin Name     191 VSSQ Power I/O GND 192 VDDQ Power I/O VDD 193 XTAL2 O RTC crystal resonator pin 194 EXTAL2 I RTC crystal resonator pin 195 VDD-RTC Power RTC VDD 196 VSS-RTC Power RTC GND 197 CA I Hardware standby I Reset I Reset (H-UDI) I Manual reset I Nonmaskable interrupt 199   200  198 201 NMI Rev. 3.0, 04/02, page 20 of 1064 Reset  Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 202 
/  O Bus acknowledge/ bus request 203 / 
 I Bus request/bus acknowledge 204 MD6/ 205   I I Bus ready O SCI data output 207 VDDQ Power IO VDD 208 VSSQ Power IO GND 209 VDD Power Internal VDD 210 VSS Power Internal GND 211 MD2/RXD2 I Mode/SCIF data input 212 RXD I SCI data input 213 TCLK I/O RTC/TMU clock 215 SCK SRAM DRAM SDRAM Mode/ MD6 (PCMCIA) 206 TXD 214 MD8/ I/O Reset Mode/SCIF data control (RTS) PCMCIA MPX     MD2 RXD2 RXD2 RXD2 RXD2 RXD2 MD8      I/O SCIF clock 216 MD1/TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 MD0/SCK2 I/O Mode/SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 Mode/SCIF data control (CTS) MD7




 218 MD7/
 I/O 219 AUDSYNC 220 AUDCK AUD sync AUD clock 221 VDDQ Power IO VDD 222 VSSQ Power IO GND 223 AUDATA0 AUD data 224 AUDATA1 AUD data Rev. 3.0, 04/02, page 21 of 1064 Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not connect 230 MD3/
 I/O 231 MD4/
 I/O 232 MD5 I DRAM SDRAM PCMCIA MD3
 Mode/ PCMCIA-CE MD4
 Mode MD5 Power IO VDD 234 VSSQ Power IO GND 235 DACK0 O DMAC0 bus acknowledge 236 DACK1 O DMAC1 bus acknowledge 237 DRAK0 O DMAC0 request acknowledge 238 DRAK1 O DMAC1 request acknowledge 239 VDD Power Internal VDD 240 VSS Power Internal GND 241 STATUS0 O Status 242 STATUS1 O Status 243  I Request from DMAC0 244  I Request from DMAC1 245  / I/O Pin break/ acknowledge (H-UDI) O Data out (H-UDI) 246 TDO SRAM Mode/ PCMCIA-CE 233 VDDQ BRKACK Reset Rev. 3.0, 04/02, page 22 of 1064 MPX Table 1.2 Pin Functions (cont) Memory Interface No. Pin Name I/O Function 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1 Power PLL1 VDD 252 VSS-PLL1 Power PLL1 GND 253 VDD-CPG Power CPG VDD 254 VSS-CPG Power CPG GND 255 XTAL O Crystal resonator 256 EXTAL I External input clock/crystal resonator I: O: I/O: Power: Reset SRAM DRAM SDRAM PCMCIA MPX Input Output Input/output Power supply Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum. 2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. 3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used. 4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. 5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D. * I/O attribute is I/O when used as a port. Rev. 3.0, 04/02, page 23 of 1064 1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface No. Pin Number Pin Name I/O Function 1 B3 TMS I Mode (H-UDI) 2 C4 TCK I Clock (H-UDI) 3 G3 VDDQ Power IO VDD 4 F2 VSSQ Power IO GND 5 D4 TDI I Data in (H-UDI) 6 B1 O Chip select 0 7 C2 O Chip select 1 8 C1 O Chip select 4 9 D3 O Chip select 5 10 D2 O Chip select 6 11 D1 O Bus start 12 E4 O D7–D0 select signal 13 E3




  /   O D15–D8 select signal 14 E2 D0 I/O Data 15 G2 VDDQ Power IO VDD 16 L4 VSSQ Power IO GND Reset SRAM




 ( )   DRAM ( ) SDRAM ( ) PCMCIA

 ( )  MPX




 ( )  A0 17 G4 VDD Power Internal VDD 18 F4 VSS Power Internal GND 19 E1 D1 I/O Data A1 20 F3 D2 I/O Data A2 21 F1 D3 I/O Data A3 22 G1 D4 I/O Data A4 23 H4 D5 I/O Data A5 24 H3 D6 I/O Data A6 25 H2 D7 I/O Data A7 26 H1 D8 I/O Data A8 27 J4 D9 I/O Data A9 Rev. 3.0, 04/02, page 24 of 1064 Table 1.3 Pin Functions (cont) Memory Interface Pin Number Pin Name I/O Function 28 J3 D10 I/O Data 29 K3 VDDQ Power IO VDD 30 L3 VSSQ Power IO GND 31 J2 D11 I/O Data A11 32 J1 D12 I/O Data A12 33 K4 D13 I/O Data A13 34 K2 D14 I/O Data A14 No. 35 K1 D15 I/O Data 36 L2
/ O D7–D0 select signal 37 M4 O D15–D8 select signal DQM0
/ DQM1 38 M3 RD/ O Read/write 39 M1 CKIO O Clock output 40 M2 NC 41 P3 VDDQ Power IO VDD 42 L1 VSSQ Power IO GND 43 N3 NC 44 P1 45 N2 46 N1  O  47 P4 VDD Power Internal VDD 48 R4 VSS Power Internal GND 49 N4 O Chip select 2 50 R3

 O Chip select 3 51 R1 A0 O Address 52 T4 A1 O Address 53 T3 A2 O Address 54 T2 A3 O Address 55 P2 VDDQ Power IO VDD /
/  CKE Reset SRAM DRAM SDRAM PCMCIA MPX A10 A15
 DQM0
 DQM1 RD/ RD/ RD/ CKIO Do not connect Do not connect O O Read/
/  
 Clock output enable   CKE

   (
)

 (
)

 Rev. 3.0, 04/02, page 25 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name I/O Function 56 R2 VSSQ Power IO GND 57 T1 A4 O Address 58 U4 A5 O Address 59 U3 A6 O Address 60 U2 A7 O Address 61 U1 A8 O Address 62 V2 A9 O Address 63 V1 A10 O Address 64 W1 A11 O Address 65 Y1 A12 O Address 66 Y2 A13 O Address 67 V7 VDDQ Power IO VDD 68 V3 VSSQ Power IO GND 69 W3 A14 O Address 70 Y3 A15 O Address 71 V4 A16 O Address 72 W4 A17 O Address 73 Y4
/ O D23–D16 select signal O D31–D24 select signal DQM2 74 U5
/ DQM3 Reset SRAM DRAM SDRAM
 DQM2
 DQM3 PCMCIA MPX 75 V5 D16 I/O Data A16 76 W5 D17 I/O Data A17 77 Y5 D18 I/O Data A18 78 V6 D19 I/O Data A19 79 W7 VDDQ Power IO VDD 80 W2 VSSQ Power IO GND 81 U7 VDD Power Internal VDD 82 U6 VSS Power Internal GND 83 Y6 D20 I/O Data A20 84 Y7 D21 I/O Data A21 85 U8 D22 I/O Data A22 86 V8 D23 I/O Data A23 Rev. 3.0, 04/02, page 26 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name I/O Function 87 W8 D24 I/O Data A24 88 Y8 D25 I/O Data A25 89 U9 D26 I/O Data 90 V9 D27 I/O Data 91 W9 D28 I/O Data 92 Y9 D29 I/O Data 93 V10 VDDQ Power IO VDD 94 W6 VSSQ Power IO GND 95 W10 D30 I/O Data ACCSIZE1 96 Y10 D31 I/O Data ACCSIZE2 97 U10 VDD Power Internal VDD 98 U11 VSS Power Internal GND 99 V11 A18 O Address 100 Y11 A19 O Address 101 U12 A20 O Address 102 V12 A21 O Address 103 W12 A22 O Address 104 Y12 A23 O Address 105 V14 VDDQ Power IO VDD 106 W11 VSSQ Power IO GND 107 U13 A24 O Address 108 V13 A25 O Address 109 W13 O D23–D16 select signal 110 Y13 O D31–D24 select signal 111 U14 VDD Power Internal VDD 112 U15 VSS Power Internal GND 113 Y14 Sleep V15  
  I 114 O Bus grant (host function) 115 Y15 
  O Bus grant (host function) / 
 / 
 Reset SRAM DRAM SDRAM PCMCIA MPX ACCSIZE0  
  
 Rev. 3.0, 04/02, page 27 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name 116 U16 117 118 I/O Function 
  O Bus grant (host function) V16 
 I* W16 
/ 1 Bus request (host function) I* 1 Bus request (host function)/ mode MD10 119 W14 VDDQ Power IO VDD 120 W15 VSSQ Power IO GND Y16 
/ 121 1 I* Bus request (host function)/ mode I Configuration device select O Interrupt (async) O Reset output I PCI input clock O Bus grant (host function)/ bus request I Bus request (host function)/ bus grant MD9 IDSEL Reset SRAM DRAM SDRAM PCMCIA MPX MD10 MD9 122 U17 123 V17 124 W17  
 125 Y17 PCICLK 126 W18 127 Y18 128 Y19  I/O System error 129 Y20 AD31 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 130 W20 AD30 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 131 P18 VDDQ Power IO VDD 132 V18 VSSQ Power IO GND 133 V19 AD29 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 134 V20 AD28 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 135 U18 AD27 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 
 /  
/  Rev. 3.0, 04/02, page 28 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name I/O Function 136 U20 AD26 I/O 137 T17 AD25 138 T18 139 Reset SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD24 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) U19 C/  I/O PCI address/ data/port 140 T20 AD23 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 141 R18 AD22 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 142 T19 AD21 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 143 N19 VDDQ Power IO VDD 144 W19 VSSQ Power IO GND 145 P17 VDD Power Internal VDD 146 R17 VSS Power Internal GND 147 R20 AD20 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 148 P20 AD19 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 149 P19 AD18 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 150 N20 AD17 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 151 N17 AD16 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 152 N18 C/  I/O Command/ byte enable 153 M20 I/O Bus cycle 154 M19 I/O Initiator ready 155 M18 I/O Target read 156 M17 
    I/O Device select 157 L18 VDDQ Power IO VDD Rev. 3.0, 04/02, page 29 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name I/O 158 R19 Power IO GND 159 L20 I/O Transaction stop 160 L19 I/O Exclusive access 161 L17 
 

  I/O Parity error 162 K20 PAR I/O Parity 163 K18 C/  I/O Command/ byte enable 164 J20 AD15 I/O 165 J19 AD14 166 J18 167 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD13 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) J17 AD12 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 168 H20 AD11 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 169 G18 VDDQ Power IO VDD 170 K17 VSSQ Power IO GND 171 H19 AD10 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 172 G20 AD9 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 173 H18 AD8 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 174 H17 C/  I/O Command/ byte enable 175 G17 VDD Power Internal VDD 176 F17 VSS Power Internal GND 177 F18 AD7 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 178 F20 AD6 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 179 E20 AD5 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) VSSQ Function Rev. 3.0, 04/02, page 30 of 1064 Reset Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name I/O Function 180 E19 AD4 I/O 181 E18 AD3 182 D20 183 SRAM DRAM SDRAM PCMCIA MPX PCI address/ data/port (Port) (Port) (Port) (Port) (Port) I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) AD2 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) G19 VDDQ Power I/O VDD 184 K19 VSSQ Power I/O GND 185 D19 AD1 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 186 D18 AD0 I/O PCI address/ data/port (Port) (Port) (Port) (Port) (Port) 187 E17 I Interrupt 0 188 C20 I Interrupt 1 189 C19 I Interrupt 2 190 B20     I Interrupt 3 191 B18 NC 192 D17 VDDQ Power I/O VDD 193 A20 XTAL2 O RTC crystal resonator pin 194 A19 EXTAL2 I RTC crystal resonator pin 195 A18 VDD-RTC Power RTC VDD 196 B19 VSS-RTC Power RTC GND 197 B17 CA I Hardware standby 198 A17 Reset C16 I Reset (H-UDI) 200 B16    I 199 I Manual reset 201 D16 NMI I Nonmaskable interrupt 202 A16 O Bus acknowledge/ bus request 
/  Do not connect * Reset 2  Rev. 3.0, 04/02, page 31 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name 203 B15 204 C15 205 206 / 
 I/O Function I Bus request/bus acknowledge Mode/ (PCMCIA) MD6/ I A15   I Bus ready A14 TXD O SCI data output 207 B14 VDDQ Power IO VDD 208 F19 VSSQ Power IO GND 209 D14 VDD Power Internal VDD 210 D15 VSS Power Internal GND 211 D13 MD2/ RXD2 I Mode/SCIF data input 212 C13 RXD I SCI data input 213 B13 TCLK I/O RTC/TMU clock 214 A13 MD8/ I/O Mode/SCIF data control (RTS)  Reset SRAM DRAM SDRAM PCMCIA MPX  MD6    MD2 RXD2 RXD2 RXD2 RXD2 RXD2 MD8      215 D12 SCK I/O SCIF clock 216 B11 MD1/ TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2 217 C12 MD0/ SCK2 I/O Mode/SCIF clock MD0 SCK2 SCK2 SCK2 SCK2 SCK2 218 A12 MD7/ I/O Mode/SCIF data control (CTS) MD7





 219 B12 AUDSYNC AUD sync 220 A11 AUDCK AUD clock 221 C14 VDDQ Power 222 C18 VSSQ Power 223 C10 AUDATA0 224 A10 AUDATA1 225 D11 VDD Power Internal VDD 226 D10 VSS Power Internal GND IO VDD IO GND AUD data AUD data Rev. 3.0, 04/02, page 32 of 1064 Table 1.3 Pin Functions (cont) Memory Interface No. Pin Number Pin Name 227 B9 AUDATA2 AUD data 228 D9 AUDATA3 AUD data 229 C9 NC Do not connect 230 A9 MD3/
 I/O Mode/ PCMCIA-CE MD3
 231 D8 MD4/
 I/O Mode/ PCMCIA-CE MD4
 232 C8 MD5 I Mode MD5 233 C11 VDDQ Power IO VDD 234 C17 VSSQ Power IO GND 235 B8 DACK0 O DMAC0 bus acknowledge 236 A8 DACK1 O DMAC1 bus acknowledge 237 B7 DRAK0 O DMAC0 request acknowledge 238 A7 DRAK1 O DMAC1 request acknowledge 239 D7 VDD Power Internal VDD 240 D6 VSS Power Internal GND 241 C6 STATUS0 O Status 242 B6 STATUS1 O Status 243 A6  I Request from DMAC0 244 C5  I Request from DMAC1 245 D5  / I/O Pin break/ acknowledge (H-UDI) O Data out (H-UDI) I/O BRKACK 246 B4 TDO Function 247 C7 VDDQ Power IO VDD 248 B10 VSSQ Power IO GND 249 A5 VDD-PLL2 Power PLL2 VDD Reset SRAM DRAM SDRAM PCMCIA MPX Rev. 3.0, 04/02, page 33 of 1064 Table 1.3 Pin Functions (cont) Memory Interface Pin Number Pin Name I/O Function 250 B5 VSS-PLL2 Power PLL2 GND 251 A4 VDD-PLL1 Power PLL1 VDD 252 C3 VSS-PLL1 Power PLL1 GND No. 253 A3 VDD-CPG Power CPG VDD 254 B2 VSS-CPG Power CPG GND 255 A2 XTAL O Crystal resonator 256 A1 EXTAL I External input clock/crystal resonator I: O: I/O: Power: Reset SRAM DRAM SDRAM PCMCIA MPX Input Output Input/output Power supply Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum. 2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used. 3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used. 4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used. 5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D. *1 I/O attribute is I/O when used as a port. *2 May be connected to VSSQ. Rev. 3.0, 04/02, page 34 of 1064 Section 2 Programming Model 2.1 Data Formats The data formats handled by the SH7751 Series are shown in figure 2.1. 7 0 Byte (8 bits) 15 0 Word (16 bits) 31 0 Longword (32 bits) 31 30 Single-precision floating-point (32 bits) 63 62 Double-precision floating-point (64 bits) 22 s exp s 51 exp 0 fraction 0 fraction Figure 2.1 Data Formats Rev. 3.0, 04/02, page 35 of 1064 2.2 Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH7751 Series has two processor modes, user mode and privileged mode. The SH7751 Series normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode. Rev. 3.0, 04/02, page 36 of 1064 Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, R8–R15 Undefined Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, I3–I0 = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC, SGR, DBR Undefined VBR H'00000000 System registers Floating-point registers MACH, MACL, PR, FPUL Undefined PC H'A0000000 FPSCR H'00040001 FR0–FR15, XF0–XF15 Undefined Note: * Initialized by a power-on reset and manual reset. The register configuration in each processor mode is shown in figure 2.2. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. Rev. 3.0, 04/02, page 37 of 1064 31 0 31 0 31 0 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SR SSR SR SSR GBR MACH MACL PR GBR MACH MACL PR VBR GBR MACH MACL PR VBR PC PC SPC PC SPC SGR SGR DBR (a) Register configuration in user mode R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) DBR R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: *1 The R0 register is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. *2 Banked registers *3 Banked registers Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. *4 Banked registers Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processor Mode Rev. 3.0, 04/02, page 38 of 1064 2.2.2 General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH7751 Series has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1– R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7751 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
R0_BANK0–R7_BANK0 In user mode (SR.MD = 0), R0–R7 are always assigned to R0_BANK0–R7_BANK0. In privileged mode (SR.MD = 1), R0–R7 are assigned to R0_BANK0–R7_BANK0 only when SR.RB = 0.
R0_BANK1–R7_BANK1 In user mode, R0_BANK1–R7_BANK1 cannot be accessed. In privileged mode, R0–R7 are assigned to R0_BANK1–R7_BANK1 only when SR.RB = 1. Rev. 3.0, 04/02, page 39 of 1064 SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Programming Note: As the user’s R0–R7 are assigned to R0_BANK0–R7_BANK0, and after an exception or interrupt R0–R7 are assigned to R0_BANK1–R7_BANK1, it is not necessary for the interrupt handler to save and restore the user’s R0–R7 (R0_BANK0–R7_BANK0). After a reset, the values of R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15 are undefined. Rev. 3.0, 04/02, page 40 of 1064 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Floating-point registers, FPRn_BANKi (32 registers) FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0, FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0, FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0, FPR15_BANK0 FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1, FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1, FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1, FPR15_BANK1
Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 are assigned to FPR0_BANK0–FPR15_BANK0. When FPSCR.FR = 1, FR0–FR15 are assigned to FPR0_BANK1–FPR15_BANK1.
Double-precision floating-point registers or single-precision floating-point register pairs, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0–XF15 are assigned to FPR0_BANK1–FPR15_BANK1. When FPSCR.FR = 1, XF0–XF15 are assigned to FPR0_BANK0–FPR15_BANK0.
Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} Rev. 3.0, 04/02, page 41 of 1064 
Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF4 XF8 XF12 XF1 XF5 XF9 XF13 XF2 XF6 XF10 XF14 XF3 XF7 XF11 XF15 FPSCR.FR = 0 FV0 FV4 FV8 FV12 FPSCR.FR = 1 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 XF0 XF1 XD2 XF2 XF3 XD4 XF4 XF5 XD6 XF6 XF7 XD8 XF8 XF9 XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 DR0 XMTRX XD0 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 Figure 2.4 Floating-Point Registers Rev. 3.0, 04/02, page 42 of 1064 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 DR0 FV0 DR2 DR4 FV4 DR6 DR8 FV8 DR10 DR12 DR14 FV12 Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined)) 31 30 29 28 27 — MD RB BL 16 15 14 — FD 10 — 9 8 M Q 7 4 IMASK 3 2 — 1 0 S T Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
MD: Processor mode MD = 0: User mode (some instructions cannot be executed, and some resources cannot be accessed) MD = 1: Privileged mode
RB: General register specification bit in privileged mode (set to 1 by a reset, exception, or interrupt) RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1– R7_BANK1 can be accessed using LDC/STC instructions.) RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0– R7_BANK0 can be accessed using LDC/STC instructions.)
BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs while BL = 1, the processor switches to the reset state.
FD: FPU disable bit (cleared to 0 by a reset) FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F*** instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR)
M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.
IMASK: Interrupt mask level Interrupts of a lower level than IMASK are masked. IMASK does not change when an interrupt is generated.
S: Specifies a saturation operation for a MAC instruction.
T: True/false condition or carry/borrow bit Rev. 3.0, 04/02, page 43 of 1064 Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exceptions. Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break handler branch destination address instead of VBR. 2.2.5 System Registers Multiply-and-accumulate register high, MACH (32 bits, initial value undefined) Multiply-and-accumulate register low, MACL (32 bits, initial value undefined) MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction or MUL instruction operation result. Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine return instruction (RTS). Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the executing instruction address. Rev. 3.0, 04/02, page 44 of 1064 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 31 22 21 20 19 18 17 — FR SZ PR DN 12 11 Cause 7 6 Enable 2 1 Flag 0 RM Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
FR: Floating-point register bank FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1– FPR15_BANK1 are assigned to XF0–XF15. FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1– FPR15_BANK1 are assigned to FR0–FR15.
SZ: Transfer size mode SZ = 0: The data size of the FMOV instruction is 32 bits. SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
PR: Precision mode PR = 0: Floating-point instructions are executed as single-precision operations. PR = 1: Floating-point instructions are executed as double-precision operations (the result of instructions for which double-precision is not supported is undefined). Do not set SZ and PR to 1 simultaneously; this setting is reserved. [SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
DN: Denormalization mode DN = 0: A denormalized number is treated as such. DN = 1: A denormalized number is treated as zero.
Cause: FPU exception cause field
Enable: FPU exception enable field
Flag: FPU exception flag field FPU Error (E) Invalid Division Operation (V) by Zero (Z) Overflow Underflow Inexact (O) (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Rev. 3.0, 04/02, page 45 of 1064 When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
RM: Rounding mode RM = 00: Round to Nearest RM = 01: Round to Zero RM = 10: Reserved RM = 11: Reserved
Bits 22 to 31: Reserved Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer between FPU registers and CPU registers is carried out via the FPUL register. Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for double-precision floating-point data load or store operations. In little endian mode, two 32-bit data size moves must be executed, with SZ = 0, to load or store a double-precision floating-point data. 2.3 Memory-Mapped Registers Appendix A shows the control registers mapped to memory. The control registers are doublemapped to the following two memory areas. All registers have two addresses. H'1C00 0000–H'1FFF FFFF H'FC00 0000–H'FFFF FFFF These two areas are used as follows.
H'1C00 0000–H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding filed of the TLB enables access to a memorymapped register. Accessing this area without using the address translation function of the MMU is not guaranteed.
H'FC00 0000–H'FFFF FFFF Access to area H'FC00 0000–H'FFFF FFFF in user mode will cause an address error. Memorymapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Rev. 3.0, 04/02, page 46 of 1064 2.4 Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 Longword 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.5. A 31 7 A+1 23 A+2 15 07 07 A+3 A + 11 A + 10 A + 9 7 0 31 07 0 7 0 15 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Word 0 31 Big endian 15 07 07 0 07 0 0 15 Word 1 0 A+8 7 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 Word 1 Longword 23 31 0 Word 0 Longword 0 Address A + 4 Address A Little endian Figure 2.5 Data Formats In Memory Rev. 3.0, 04/02, page 47 of 1064 Note: The SH7751 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed. 2.6 Processor States The SH7751 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The power-on reset state is entered when the
 pin goes low. The CPU enters the manual reset state if the
 pin is high and the 
 pin is low. For more information on resets, see section 5, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus state controller (BSC) is not initialized in the manual reset state, refreshing operations continue. Refer to the register configurations in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU’s processor state flow is altered by a reset, general exception, or interrupt exception source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC), the status register (SR) contents are saved in the saved status register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are three modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details, see section 9, Power-Down Modes. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. Rev. 3.0, 04/02, page 48 of 1064 From any state when RESET = 0 From any state when RESET = 1 and MRESET = 0 Power-on reset state Manual reset state RESET = 0 Reset state RESET = 1 RESET = 1, MRESET = 1 Exception-handling state Bus request Bus request clearance Interrupt Exception interrupt Bus-released state Bus request Bus request End of exception transition processing Interrupt Bus request clearance Bus request clearance Program execution state SLEEP instruction with STBY bit cleared Sleep mode SLEEP instruction with STBY bit set Standby mode Power-down state Figure 2.6 Processor State Transitions 2.7 Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which can only be accessed in privileged mode. Rev. 3.0, 04/02, page 49 of 1064 Rev. 3.0, 04/02, page 50 of 1064 Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7751 Series can handle 29-bit external memory space from an 8-bit address space identifier and 32-bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH7751 Series. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). The SH7751 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and implement storage protection independently for privileged mode and user mode. 3.1.2 Role of the MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 3.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2)). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a task to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process’s physical memory. Rev. 3.0, 04/02, page 51 of 1064 When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided in hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails—that is, if an exception occurs—switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7751 Series is referred to as virtual address space, and the address space in physical memory as physical address space. Rev. 3.0, 04/02, page 52 of 1064 Physical memory Process 1 Physical memory Process 1 Virtual memory MMU Physical memory Process 1 (1) Process 1 Physical memory (2) Process 1 Virtual memory , ,, ,,,, MMU Physical memory Process 2 Process 2 ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,, ,,, Process 3 Process 3 ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, ,,, (3) ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, ,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,, (4) Figure 3.1 Role of the MMU Rev. 3.0, 04/02, page 53 of 1064 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbreviation R/W Initial 1 Value* P4 2 Address* Page table entry high register PTEH R/W Undefined H'FF00 0000 H'1F00 0000 32 Page table entry low register PTEL R/W Undefined H'FF00 0004 H'1F00 0004 32 Page table entry assistance register PTEA R/W Undefined H'FF00 0034 H'1F00 0034 32 Translation table base register TTB R/W Undefined H'FF00 0008 H'1F00 0008 32 TLB exception address register TEA R/W Undefined H'FF00 000C H'1F00 000C 32 MMU control register MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32 Name Area 7 2 Address* Access Size Notes: *1 The initial value is the value after a power-on reset or manual reset. *2 P4 address is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. 3.1.4 Caution Operation is not guaranteed if an area designated as a reserved area in this manual is accessed. Rev. 3.0, 04/02, page 54 of 1064 3.2 Register Descriptions There are six MMU-related registers. 1. PTEH 31 10 9 VPN 8 7 0 — — ASID 2. PTEL 31 30 29 28 10 9 PPN — — — 8 7 — V SZ 6 5 PR 4 3 2 1 0 SZ C D SH WT 3. PTEA 31 4 3 2 TC 0 SA 4. TTB 31 0 TTB 5. TEA 31 0 Virtual address at which MMU exception or address error occurred 6. MMUCR 31 26 25 24 23 LRUI — — 18 17 16 15 URB — — 10 9 URC 8 7 6 5 4 3 2 1 0 SV — — — — — TI — AT SQMD — indicates a reserved bit: the write value must be 0, and a read will return 0. Figure 3.2 MMU-Related Registers Rev. 3.0, 04/02, page 55 of 1064 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. A branch to the P0, P3, or V0 area which uses the updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions after the PTEH update instruction. 2. Page table entry low register (PTEL): Longword access to PTEL can be performed from H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued. 3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEA is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing PCMCIA access with the MMU off, access is always performed using the values of the SA and TC bits in this register. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The contents of this register are not changed unless a software directive is issued. 4. Translation table base register (TTB): Longword access to TTB can be performed from H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be freely used by software. 5. TLB exception address register (TEA): Longword access to TEA can be performed from H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software. 6. MMU control register (MMUCR): MMUCR contains the following bits: LRUI: Least recently used ITLB URB: UTLB replace boundary URC: UTLB replace counter SQMD: Store queue mode bit SV: Single virtual mode bit TI: TLB invalidate AT: Address translation bit Rev. 3.0, 04/02, page 56 of 1064 Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated by hardware.
LRUI: LRU bits that indicate the ITLB entry for which replacement is to be performed. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. A dash in this table means that updating is not performed. LRUI [5] [4] [3] [2] [1] [0] When ITLB entry 0 is used 0 0 0 — — — When ITLB entry 1 is used 1 — — 0 0 — When ITLB entry 2 is used — 1 — 1 — 0 When ITLB entry 3 is used — — 1 — 1 1 Other than the above — — — — — — When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. An asterisk in this table means “Don’t care”. LRUI [5] [4] [3] [2] [1] [0] ITLB entry 0 is updated 1 1 1 * * * ITLB entry 1 is updated 0 * * 1 1 * ITLB entry 2 is updated * 0 * 0 * 1 ITLB entry 3 is updated * * 0 * 0 0 Other than the above Setting prohibited Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update.
URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. Rev. 3.0, 04/02, page 57 of 1064 
URC: Random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a value is written to URC by software which results in the condition URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction.
SQMD: Store queue mode bit. Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access)
SV: Bit that switches between single virtual memory mode and multiple virtual memory mode. 0: Multiple virtual memory mode 1: Single virtual memory mode When this bit is changed, ensure that 1 is also written to the TI bit.
TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always returns 0 when read.
AT: Address translation enable bit. Specifies MMU enabling or disabling. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. 3.3 Address Space 3.3.1 Physical Address Space The SH7751 Series supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error. Rev. 3.0, 04/02, page 58 of 1064 External memory space H'0000 0000 P0 area Cacheable H'8000 0000 H'A000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000 U0 area Cacheable H'8000 0000 P1 area Cacheable P2 area Non-cacheable Address error H'C000 0000 P3 area Cacheable H'E000 0000 P4 area Non-cacheable Store queue area Privileged mode User mode H'FFFF FFFF Address error H'E000 0000 H'E400 0000 H'FFFF FFFF Figure 3.3 Physical Address Space (MMUCR.AT = 0) When performing access from the CPU to a PCMCIA interface area in the SH7751 Series, access is always performed using the values of the SA and TC bits set in the PTEA register. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct Memory Access Controller. P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR). When the cache is used, with the exception of the P1 area, switching between the copy-back method and the write-through method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3 bits of an address gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area also appears in this area. P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4. Rev. 3.0, 04/02, page 59 of 1064 H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2 H'F800 0000 Reserved area H'FC00 0000 Control register area H'FFFF FFFF Figure 3.4 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit. For details, see section 4.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 4.5.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 4.5.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 3.7.1, ITLB Address Array. The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. Rev. 3.0, 04/02, page 60 of 1064 The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 4.5.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 4.5.4, OC Data Array. The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 3.7.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2. The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. For details, see appendix A, Address List. 3.3.2 External Memory Space The SH7751 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC). H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area) Figure 3.5 External Memory Space Rev. 3.0, 04/02, page 61 of 1064 3.3.3 Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH7751 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual address space. Mapping from virtual address space to 29-bit external memory space is carried out using the TLB. Only when area 7 in external memory space is accessed using virtual address space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical address space. Virtual address space is illustrated in figure 3.6. 256 External memory space 256 Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 U0 area Cacheable Address translation possible Area 6 Area 7 P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible Address error P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Store queue area Privileged mode User mode Address error Figure 3.6 Virtual Address Space (MMUCR.AT = 1) In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto the area of the PCMCIA interface by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Rev. 3.0, 04/02, page 62 of 1064 Here, access to an area of the PCMCIA interface by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with the values of CHCRn, SSAn, CHCRn.DsAn, CHCRn.STC and CHCRn.DTC in the DMAC. For details, see Section 14, Direct Memory Access Controller (DMAC). P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the cacheability bit (C bit) in the TLB is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to the control register area. This enables control registers to be accessed from the U0 area in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for physical address space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces. For details, see section 4.7, Store Queues. 3.3.4 On-Chip RAM Space In the SH7751 Series, half of the operand cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. 3.3.5 Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In the SH7751 Series, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is Rev. 3.0, 04/02, page 63 of 1064 uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception handling routine. In the TLB miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and a particular virtual address may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 3.4.3, Address Translation Method). 3.3.7 Address Space Identifier (ASID) In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish between processes running simultaneously while sharing the virtual address space. Software can set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for processes running simultaneously while using the virtual memory space on an exclusive basis. Notes: (1) In single virtual memory mode of the SH7751 Series, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. (2) In single virtual memory mode of the SH7751, if the UTLB contains address translation information including an ITLB miss address with a different ASID and unshared state (SH bit is 0), SH7751 may hang up or an instruction TLB multiple hit exception may occur during hardware ITLB miss handling (see section 3.5.4, Hardware ITLB Miss Handling). To avoid this, when switching the ASID values (PTEH and ASID) of the current processing, purge the UTLB, or manage the changes of the program instruction addresses in user mode so that no instruction is executed in an address area (including overrun prefetch of instruction) that is registered in the Rev. 3.0, 04/02, page 64 of 1064 UTLB with a different ASID and unshared address translation information. Note that this restriction does not apply to the SH7751R. 3.4 TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the instruction TLB in the event of an ITLB miss Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 3.7 shows the overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure 3.8 shows the relationship between the address format and page size. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Figure 3.7 UTLB Configuration Rev. 3.0, 04/02, page 65 of 1064 • 1-kbyte page Virtual address 10 9 31 VPN 0 Physical address 10 9 28 PPN Offset 0 Offset • 4-kbyte page Virtual address 12 11 31 VPN 0 Physical address 12 11 28 PPN Offset 0 Offset • 64-kbyte page Virtual address 16 15 31 VPN 0 Physical address 16 15 28 PPN Offset 0 Offset • 1-Mbyte page Virtual address 20 19 31 VPN 0 Offset Physical address 20 19 28 PPN 0 Offset Figure 3.8 Relationship between Page Size and Address Format
VPN: Virtual page number For 1-kbyte page: upper 22 bits of virtual address For 4-kbyte page: upper 20 bits of virtual address For 64-kbyte page: upper 16 bits of virtual address For 1-Mbyte page: upper 12 bits of virtual address
ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. Rev. 3.0, 04/02, page 66 of 1064 
SZ: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page
V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset.
PPN: Physical page number Upper 22 bits of the physical address. With a 1-kbyte page, PPN bits [28:10] are valid. With a 4-kbyte page, PPN bits [28:12] are valid. With a 64-kbyte page, PPN bits [28:16] are valid. With a 1-Mbyte page, PPN bits [28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 3.5.5, Avoiding Synonym Problems).
PR: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read only, in privileged mode 01: Can be read and written in privileged mode 10: Can be read only, in privileged or user mode 11: Can be read and written in privileged mode or user mode
C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. Rev. 3.0, 04/02, page 67 of 1064 
D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed
WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0.
SA: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to

 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space
TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2–A5W0) and PCR (A5PCW1–A5PCW0, A5TED2–A5TED0, A5TEH2– A5TEH0) are used 1: WCR2 (A6W2–A6W0) and PCR (A6PCW1–A6PCW0, A6TED2–A6TED0, A6TEH2– A6TEH0) are used Rev. 3.0, 04/02, page 68 of 1064 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries. The address translation information is almost the same as that in the UTLB, but with the following differences: 1. D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB. Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Entry 3 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC Figure 3.9 ITLB Configuration 3.4.3 Address Translation Method Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB. Rev. 3.0, 04/02, page 69 of 1064 Data access to virtual address (VA) VA is in P4 area VA is in P2 area On-chip I/O access 0 VA is in P1 area VA is in P0, U0, or P3 area No CCR.OCE? MMUCR.AT = 1 1 0 Yes CCR.CB? CCR.WT? 0 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) No Yes No VPNs match and ASIDs match and V=1 No VPNs match and V = 1 Yes Yes No Only one entry matches Data TLB miss exception Yes SR.MD? 0 (User) 1 (Privileged) PR? PR? 00 or 01 W Data TLB multiple hit exception 10 11 R/W? R/W? R R 01 or 11 W W D? 0 Data TLB protection violation exception 1 00 or 10 R/W? R/W? R R W Data TLB protection violation exception Initial page write exception C=1 and CCR.OCE = 1 No Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode Memory access (Non-cacheable) Figure 3.10 Flowchart of Memory Access Using UTLB Rev. 3.0, 04/02, page 70 of 1064 Instruction access to virtual address (VA) VA is in P4 area Access prohibited VA is in P2 area VA is in P1 area VA is in P0, U0, or P3 area No 0 MMUCR.AT = 1 CCR.ICE? 1 Yes No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No No VPNs match and V = 1 VPNs match and ASIDs match and V=1 Yes Only one entry matches Hardware ITLB miss handling Search UTLB Match? Yes Yes No Yes Record in ITLB No SR.MD? Instruction TLB miss exception 0 (User) 1 (Privileged) 0 PR? Instruction TLB multiple hit exception 1 Instruction TLB protection violation exception C=1 and CCR.ICE = 1 No Yes Cache access Memory access (Non-cacheable) Figure 3.11 Flowchart of Memory Access Using ITLB Rev. 3.0, 04/02, page 71 of 1064 3.5 MMU Functions 3.5.1 MMU Hardware Management The SH7751 Series supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB, and if the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with MMUCR.LRUI. 3.5.2 MMU Software Management Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 3.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7751 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. Rev. 3.0, 04/02, page 72 of 1064 MMUCR 31 26 25 24 23 LRUI — 18 17 16 15 URB — 10 9 8 7 URC SV 3 2 1 0 — TI — AT SQMD Entry specification PTEL 31 — PTEH 31 10 9 8 7 VPN — 10 9 8 7 6 5 4 3 2 1 0 29 28 PPN — V SZ PR SZ C D SHWT 0 PTEA ASID 4 3 2 31 — TC 0 SA Write Entry 0 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 1 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 2 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC Entry 63 ASID [7:0] VPN [31:10] V PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC UTLB Figure 3.12 Operation of LDTLB Instruction 3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7751 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. Rev. 3.0, 04/02, page 73 of 1064 3.5.5 Avoiding Synonym Problems When 1- or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB or instruction cache. In the SH7751 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after translation may differ from bits [13:10] of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. 1. When address translation information whereby a number of 1-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10] values are the same. 2. When address translation information whereby a number of 4-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12] values are the same. 3. Do not use 1-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. 4. Do not use 4-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above restrictions apply to VPN [25]. Note: When multiple items of address translation information use the same physical memory to provide for future SH Series expansion, ensure that the VPN [20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes. Rev. 3.0, 04/02, page 74 of 1064 3.6 MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions occurs. 3.6.1 Instruction TLB Multiple Hit Exception An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Rev. 3.0, 04/02, page 75 of 1064 Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Rev. 3.0, 04/02, page 76 of 1064 Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. Set the current R15 value in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. Rev. 3.0, 04/02, page 77 of 1064 3.6.5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR, and sets the R15 contents at the time in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. Rev. 3.0, 04/02, page 78 of 1064 3.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. Rev. 3.0, 04/02, page 79 of 1064 3. Sets exception code H'080 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine. Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to URC in the MMUCR register. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.7 Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in the other area. A branch to an area other than the P2 area should be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in physical address space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be Rev. 3.0, 04/02, page 80 of 1064 performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field bits [1:0]. In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0]. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 0 1 0 10 9 8 7 E 10 9 8 7 31 Data field 0 VPN VPN: Virtual page number V: Validity bit E: Entry V 0 ASID ASID: Address space identifier : Reserved bits (0 write value, undefined read value) Figure 3.13 Memory-Mapped ITLB Address Array Rev. 3.0, 04/02, page 81 of 1064 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry is selected by bits [9:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit [6], C by bit [3], and SH by bit [1]. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 31 24 23 Address field 1 1 1 1 0 0 1 1 0 10 9 8 7 31 30 29 28 Data field 10 9 8 7 6 5 4 3 2 1 0 PPN PPN: V: E: SZ: Physical page number Validity bit Entry Page size bits PR: C: SH: : V C PR SZ SH Protection key data Cacheability bit Share status bit Reserved bits (0 write value, undefined read value) Figure 3.14 Memory-Mapped ITLB Data Array 1 Rev. 3.0, 04/02, page 82 of 1064 0 E 3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry is selected by bits [9:8]. In the data field, SA is indicated by bits [2:0], and TC by bit [3]. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 0 1 1 1 10 9 8 7 0 E 4 3 2 0 31 Data field SA TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.15 Memory-Mapped ITLB Data Array 2 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field. Rev. 3.0, 04/02, page 83 of 1064 In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0]. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception results. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB. 31 24 23 Address field 1 1 1 1 0 1 1 0 10 9 8 7 VPN VPN: V: E: D: Virtual page number Validity bit Entry Dirty bit D V 0 ASID ASID: Address space identifier A: Association bit : Reserved bits (0 write value, undefined read value) Figure 3.16 Memory-Mapped UTLB Address Array Rev. 3.0, 04/02, page 84 of 1064 2 1 0 A E 31 30 29 28 Data field 8 7 14 13 3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry is selected by bits [13:8]. In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits [6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0]. The following two kinds of operation can be used on UTLB data array 1: 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 1 1 1 0 14 13 31 30 29 28 Data field 0 10 9 8 7 6 5 4 3 2 1 0 PPN PPN: V: E: SZ: D: 8 7 E Physical page number Validity bit Entry Page size bits Dirty bit V PR: C: SH: WT: : PR C D Protection key data SZ SH WT Cacheability bit Share status bit Write-through bit Reserved bits (0 write value, undefined read value) Figure 3.17 Memory-Mapped UTLB Data Array 1 Rev. 3.0, 04/02, page 85 of 1064 3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry is selected by bits [13:8]. In the data field, TC is indicated by bit [3], and SA by bits [2:0]. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. 24 23 31 Address field 1 1 1 1 0 1 1 1 1 14 13 8 7 0 E 4 3 2 31 Data field SA TC: Timing control bit E: Entry TC SA: Space attribute bits : Reserved bits (0 write value, undefined read value) Figure 3.18 Memory-Mapped UTLB Data Array 2 Rev. 3.0, 04/02, page 86 of 1064 0 Section 4 Caches 4.1 Overview 4.1.1 Features The SH7751 Series has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on-chip RAM. The features of these caches are summarized in table 4.1. The SH7751R incorporates a 16-kbyte instruction cache (IC) for instructions and a 32-kbyte operand cache (OC) for data. Half of the operand cache memory (16 kbytes) can also be used as on-chip RAM. When the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both the IC and OC are set to SH7751 compatible mode. Operation is as shown in table 4.1. When the EMODE bit in the CCR register is set to 1, the cache characteristics are as shown in table 4.2. After a power-on reset or manual reset, the initial value of the EMODE bit is 0. The SH7751 Series supports two 32-byte store queues (SQs) for performing high-speed writes to external memory. SQ features are shown in table 4.3. Table 4.1 Cache Features (SH7751) Item Instruction Cache Operand Cache Capacity 8-kbyte cache 16-kbyte cache or 8-kbyte cache + 8-kbyte RAM Type Direct mapping Direct mapping Line size 32 bytes 32 bytes Entries 256 entry 512 entry Write method Copy-back/write-through selectable Rev. 3.0, 04/02, page 87 of 1064 Table 4.2 Cache Features (SH7751R) Item Instruction Cache Operand Cache Capacity 16-kbyte cache 32-kbyte cache or 16-kbyte cache + 16-kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entry/way 512 entry/way Write method Replace method Table 4.3 Copy-back/write-through selectable LRU (Least Recently Used) algorithm LRU (Least Recently Used) algorithm Store Queue Features Item Store Queues Capacity 2
32 bytes Addresses H'E000 0000 to H'E3FF FFFF Write Store instruction (1-cycle write) Write-back Prefetch instruction (PREF instruction) Access right MMU off: according to MMUCR.SQMD MMU on: according to individual page PR 4.1.2 Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Cache Control Registers Name Abbreviation R/W Initial 1 Value* P4 2 Address* Area 7 2 Address* Access Size Cache control register CCR R/W H'0000 0000 H'FF00 001C H'1F00 001C 32 Queue address control register 0 QACR0 R/W Undefined H'FF00 0038 H'1F00 0038 32 Queue address control register 1 QACR1 R/W Undefined H'FF00 003C H'1F00 003C 32 Notes: *1 The initial value is the value after a power-on or manual reset. *2 P4 address is the address when using the virtual/physical address space P4 area. The area 7 address is the address used when making an access from physical address space area 7 using the TLB. Rev. 3.0, 04/02, page 88 of 1064 4.2 Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. CCR 31 30 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 CB EMODE* IIX ICI ICE OIX ORA OCI WT OCE QACR0 31 5 4 2 1 0 AREA QACR1 5 4 31 2 1 0 AREA Notes: * SH7751R only indicates reserved bits: 0 must be specified in a write; the read value is 0. Figure 4.1 Cache and Store Queue Control Registers (CCR) (1) Cache Control Register (CCR): CCR contains the following bits: EMODE: IIX: ICI: ICE: OIX: ORA: OCI: CB: WT: OCE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.) IC index enable IC invalidation IC enable OC index enable OC RAM enable OC invalidation Copy-back enable Write-through enable OC enable CCR can be accessed by longword-size access from H'FF00001C in the P4 area and H'1F00001C in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. Rev. 3.0, 04/02, page 89 of 1064 
EMODE: Cache-double-mode bit Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the SH7751. The EMODE bit cannot be modified while the cache is in use. 0: SH7751-compatible-mode *1 (Initial value) 1: Cache-double-mode Note: *1 Address allocation in OC index mode and RAM mode is not compatible with that in RAM mode.
IIX: IC index enable bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection
ICI: IC invalidation bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns 0 when read.
ICE: IC enable bit Indicates whether or not the IC is to be used. When address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used
*2 OIX: OC index enable bit 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection Note: *2 In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1.
*3 ORA: OC RAM enable bit When the OC is enabled (OCE = 1), the ORA bit specifies whether the 8 kbytes from entry 128 to entry 255 and from entry 384 to entry 511 of the OC are to be used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0. 0: 16 kbytes used as cache 1: 8 kbytes used as cache, and 8 kbytes as RAM Note: *3 In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1.
OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. Rev. 3.0, 04/02, page 90 of 1064 
CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode
WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode
OCE: OC enable bit Indicates whether or not the OC is to be used. When address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used (2) Queue Address Control Register 0 (QACR0): QACR0 can be accessed by longword-size access from H'FF000038 in the P4 area and H'1F000038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off. (3) Queue Address Control Register 1 (QACR1): QACR1 can be accessed by longword-size access from H'FF00003C in the P4 area and H'1F00003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off. 4.3 Operand Cache (OC) 4.3.1 Configuration The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512 cache lines. Figure 4.2 shows the configuration of the operand cache in the SH7751. Figure 4.3 shows the configuration of the operand cache in the SH7751R. Rev. 3.0, 04/02, page 91 of 1064 Effective address 31 26 25 13 12 11 10 9 RAM area determination OIX [13] ORA [11:5] [12] Longword (LW) selection 22 Entry selection 9 MMU 5 4 3 2 1 0 Address array 0 Tag U Data array 3 V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 511 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Compare Read data Hit signal Figure 4.2 Configuration of Operand Cache (SH7751) Rev. 3.0, 04/02, page 92 of 1064 Write data Effective address 31 26 25 13 12 10 5 4 RAM area determination [12:5] OIX ORA 2 0 Longword (LW) selection [13] Entry selection 22 Address array (way 0, way 1) 9 0 Tag U 3 V Data array (way 0, way 1) LRU LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 MMU 19 511 19 bits Compare Compare way-0 way-1 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Read data 1 bit Write data Hit signal Figure 4.3 Configuration of Operand Cache (SH7751R)
Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. Rev. 3.0, 04/02, page 93 of 1064 
U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 4.5, Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Data field The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset.
LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses (among addresses 13 to 15) can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The LRU bit cannot be read from or written to by software. 4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU:  (3a)
If the tag matches and the V bit is 1
If the tag matches and the V bit is 0  (3b)
If the tag does not match and the V bit is 0  (3b) If the tag does not match, the V bit is 1, and the U bit is 0  (3b)
If the tag does not match, the V bit is 1, and the U bit is 1  (3c)
3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). Rev. 3.0, 04/02, page 94 of 1064 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 3c. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. 4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through If the tag matches and the V bit is 1  (3a)  (3b)
If the tag matches and the V bit is 0  (3c)  (3d)
If the tag does not match and the V bit is 0  (3c)  (3d) If the tag does not match, the V bit is 1, and the U bit is 0  (3c)
If the tag does not match, the V bit is 1, and the U bit is 1  (3e)  (3d)

 (3d) 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address and the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. Rev. 3.0, 04/02, page 95 of 1064 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. A write is also performed to the corresponding external memory using the specified access size. 3c. Cache miss (copy-back/no write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 3d. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. 3e. Cache miss (copy-back/with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory. Rev. 3.0, 04/02, page 96 of 1064 4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7751 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination. Physical address bits [28:5] LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 Figure 4.4 Configuration of Write-Back Buffer 4.3.5 Write-Through Buffer The SH7751 Series has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory. Physical address bits [28:0] LW0 LW1 Figure 4.5 Configuration of Write-Through Buffer 4.3.6 RAM Mode Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. The operand cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511. In SH7751compatible-mode in the SH7751R, the 8 kbytes of operand cache entries 256 to 511 are used as RAM. In cache-double-mode in the SH7751R, the total 16 kbytes of entries 256 to 511 in each way of the operand cache are used as RAM. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadwordsize data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. Note that in the SH7751R, OC index mode cannot be used when RAM mode is used. An example of RAM use is shown below. Here, the 4 kbytes comprising OC entries 128 to 256 are designated as RAM area 1, and the 4 kbytes comprising OC entries 384 to 511 as RAM area 2.
When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 Rev. 3.0, 04/02, page 97 of 1064 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1 : : : RAM areas 1 and 2 then repeat every 8 kbytes up to H'7FFF FFFF. Thus, to secure a continuous 8-kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF can be used, for example.
When OC index mode is on (CCR.OIX = 1) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 1 : : : H'7DFF F000 to H'7DFF FFFF (4 kB): Corresponds to RAM area 1 H'7E00 0000 to H'7E00 0FFF (4 kB): Corresponds to RAM area 2 H'7E00 1000 to H'7E00 1FFF (4 kB): Corresponds to RAM area 2 : : : H'7FFF F000 to H'7FFF FFFF (4 kB): Corresponds to RAM area 2 As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-kbyte RAM area. An example of RAM use in the SH7751R is shown below.
SH7751-compatible-mode (CCR.EMODE = 0) H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area (entries 256 to 511) : : : A shadow of the RAM area occurs every 8 kbytes up to H'7FFF FFFF.
Cache-double-mode (CCR.EMODE = 1) The 8 kbytes of entries 256 to 511 in OC way 0 are used as RAM area 1, and the 8 kbytes of entries 256 to 511 in OC way 1 are used as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 kB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 kB): Corresponds to RAM area 2 : : : A shadow of the RAM area occurs every 16 kbytes up to H'7FFF FFFF. Rev. 3.0, 04/02, page 98 of 1064 4.3.7 OC Index Mode Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. Note that in the SH7751R, RAM mode cannot be used when OC index mode is used. 4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In the SH7751 Series, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: OCBI @Rn Cache invalidation (no write-back) Purge instruction: OCBP @Rn Cache invalidation (with write-back) Write-back instruction: OCBWB @Rn Cache write-back Allocate instruction: MOVCA.L R0,@Rn Cache allocation 4.3.9 Prefetch Operation The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual. Prefetch instruction: PREF @Rn 4.4 Instruction Cache (IC) 4.4.1 Configuration The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32byte data (16 instructions). The instruction cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 256 cache lines. Rev. 3.0, 04/02, page 99 of 1064 Figure 4.6 shows the configuration of the instruction cache in the SH7751. Figure 4.7 shows the configuration of the instruction cache in the SH7751R. Effective address 31 26 25 13 12 11 10 9 5 4 3 2 1 0 [11:5] IIX [12] Longword (LW) selection 22 MMU Entry selection 8 Address array 0 3 Data array Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 19 255 Compare Read data Hit signal Figure 4.6 Configuration of Instruction Cache (SH7751) Rev. 3.0, 04/02, page 100 of 1064 Effective address 31 25 13 12 11 10 5 4 [11:5] 2 0 Longword (LW) selection IIX [12] Entry selection 22 Address array (way 0, way 1) 8 0 3 Data array (way 0, way 1) Tag V LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits LRU MMU 19 255 Compare Compare way-0 way-1 1 bit Read data Hit signal Figure 4.7 Configuration of Instruction Cache (SH7751R)
Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. Rev. 3.0, 04/02, page 101 of 1064 
LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses (among addresses 12 to 15) can register the same data in cache. The LRU bit indicates to which way the entry is to be registered among the two ways. There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The LRU bit cannot be read from or written to by software. 4.4.2 Read Operation When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: • If the tag matches and the V bit is 1  (3a) • If the tag matches and the V bit is 0  (3b) • If the tag does not match and the V bit is 0  (3b) • If the tag does not match and the V bit is 1  (3b) 3a. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 3b. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two areas by means of effective address bit [25], providing efficient use of the cache. Rev. 3.0, 04/02, page 102 of 1064 4.5 Memory-Mapped Cache Configuration (SH7751) To enable the IC and OC to be managed by software, the IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The OC contents can be read and written by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and the access size is always longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. 4.5.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the Rev. 3.0, 04/02, page 103 of 1064 MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 0 0 0 13 12 5 4 3 2 1 0 Entry 31 10 9 Data field Tag A 1 0 V V : Validity bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.8 Memory-Mapped IC Address Array 4.5.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. Rev. 3.0, 04/02, page 104 of 1064 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 31 24 23 13 12 Address field 1 1 1 1 0 0 0 1 5 4 Entry 2 1 0 L 31 0 Data field Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.9 Memory-Mapped IC Data Array 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. The address array bit [3] association bit (A bit) specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to Rev. 3.0, 04/02, page 105 of 1064 the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 1 0 0 14 13 5 4 3 2 1 0 Entry 10 9 31 Data field Tag A 2 1 0 U V V : Validity bit U : Dirty bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.10 Memory-Mapped OC Address Array 4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. Rev. 3.0, 04/02, page 106 of 1064 The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side. 24 23 31 Address field 1 1 1 1 0 1 0 1 14 13 5 4 Entry L 0 31 Data field 2 1 0 Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array 4.6 Memory-Mapped Cache Configuration (SH7751R) To enable the IC and OC to be managed by software, IC contents can be read and written by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least 8 instructions after this MOV instruction. The OC contents can be read and written by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and the access size is always longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified, and read values are undefined. Note that the memory-mapped cache configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751. Rev. 3.0, 04/02, page 107 of 1064 4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bit [3], that is the association bit (A bit), specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way’s tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [13] is ignored. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit in that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an interrupt is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine. Rev. 3.0, 04/02, page 108 of 1064 31 24 23 Address field 1 1 1 1 0 0 0 0 13 12 Entry Way 31 Data field 5 4 3 2 1 0 10 9 A 1 0 V Tag V : Validity bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. Rev. 3.0, 04/02, page 109 of 1064 31 24 23 Address field 1 1 1 1 0 0 0 1 13 12 5 4 Entry 2 1 0 L Way 31 0 Data field Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary of Memory-Mapped OC Addresses. Address field bit [3], that is the association bit (A bit), specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. Rev. 3.0, 04/02, page 110 of 1064 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, each way’s tag stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set in bit [14] is ignored. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit in that way is 1, the U bit and V bit specified in the data field are written into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 24 23 31 Address field 1 1 1 1 0 1 0 0 15 1413 5 4 3 2 1 0 Entry A Way 10 9 31 Data field 2 1 0 U V Tag V : Validity bit U : Dirty bit A : Association bit : Reserved bits (0 write value, undefined read value) Figure 4.14 Memory-Mapped OC Address Array 4.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary of Memory-Mapped OC Addresses. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. Rev. 3.0, 04/02, page 111 of 1064 The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. This write does not set the U bit to 1 on the address array side. 24 23 31 Address field 1 1 1 1 0 1 0 1 15 1413 5 4 Entry 2 1 0 L Way 0 31 Data field Longword data L : Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.15 Memory-Mapped OC Data Array 4.6.5 Summary of Memory-Mapped OC Addresses The memory-mapped OC addresses in cache-double-mode in the SH7751R are summarized below using data area access as an example.
Normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 kB): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 kB): Way 1 (entries 0 to 511) : : : A shadow of the cache area occurs every 32 kbytes up to H'F5FF FFFF.
RAM mode (CCR.ORA = 1) H'F500 0000 to H'F500 1FFF (8 kB): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 kB): Way 1 (entries 0 to 255) : : : A shadow of the cache area occurs every 16 kbytes up to H'F5FF FFFF. Rev. 3.0, 04/02, page 112 of 1064 4.7 Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. When not using the SQs, the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 9, Power-Down Modes, for the procedure for stopping SQ functions. 4.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store queues can be set independently. SQ0 SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1 SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7] 4B 4B 4B 4B 4B 4B 4B 4B Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction on P4 area H'E000 0000 to H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits is as follows: [31:26]: [25:6]: [5]: [4:2]: [1:0] 4.7.3 111000 Don’t care 0/1 LW specification 00 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. Rev. 3.0, 04/02, page 113 of 1064 The SQ transfer destination external address bit [28:0] specification is as shown below, according to whether the MMU is on or off.
When MMU is on The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have no meaning. When a prefetch instruction is issued for the SQ area, address translation is performed and external address bits [28:10] are generated in accordance with the SZ bit specification. For external address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to external is performed to this address.
When MMU is off The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF instruction is issued. The meaning of address bits [31:0] is as follows: [31:26]: 111000 Store queue specification [25:6]: Address External address bits [25:6] [5]: 0/1 0: SQ0 specification 1: SQ1 specification and external address bit [5] [4:2]: [1:0] Don’t care 00 No meaning in a prefetch Fixed at 0 External address bits [28:26], which cannot be generated from the above address, are generated from the QACR0/1 registers. QACR0 [4:2]: External address bits [28:26] corresponding to SQ0 QACR1 [4:2]: External address bits [28:26] corresponding to SQ1 External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. In the SH7751 Series, data transfer to a PCMCIA interface area is always performed using the SA and TC bits in the PTEA register. Rev. 3.0, 04/02, page 114 of 1064 4.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows. If an exception occurs in an SQ write, the SQ contents may be corrupted in the SH7751 (see section 4.7.6, SQ Usage Notes), but the previous values of the SQ contents are guaranteed in the SH7751R. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
When MMU is on Operation is in accordance with the address translation information recorded in the UTLB, and MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read type for transfer from the SQs to external memory (PREF instruction), and a TLB miss exception, protection violation exception, or initial page write exception is generated. However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address error will be flagged in user mode even if address translation is successful.
When MMU is off Operation is in accordance with MMUCR.SQMD. 0: Privileged/user access possible 1: Privileged access possible If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will be flagged. 4.7.5 SQ Read (SH7751R only) In the SH7751R, the SQ contents can be read by a load instruction for addresses H'FF001000 to H'FF00103C in the P4 area in privileged mode. The access size is always longword. [31:6]: [5]: [4:2]: [1:0]: H'FF001000 (store queue specification) 0/1 (0: SQ0 specification, 1: SQ1 specification) LW specification (specification of longword position in SQ0 or SQ1) 00 (fixed to 0) Rev. 3.0, 04/02, page 115 of 1064 4.7.6 SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7751, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below. (1) When SQ data is transferred to external memory within a normal program If a PREF instruction for transfer from an SQ to external memory is included in the three instructions preceding an SQ store instruction, the SQ is updated because the SQ write that should be suppressed when a branch is made to the exception handling routine is executed, and after returning from the exception handling routine the execution order of the PREF instruction and SQ store instruction is reversed, so that erroneous data may be transferred to external memory. (2) When SQ data is transferred to external memory in an exception handling routine If store queue contents are transferred to external memory within an exception handling routine, erroneous data may be transferred to external memory. Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ to external memory PREF instruction ; PREF instruction for transfer from SQ to external memory ; Address of this instruction is saved to SPC when exception occurs. ; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine. Instruction 1 ; May be executed if an SQ store instruction. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; Not executed even if an SQ store instruction. Example 2: When an instruction at which an exception occurs is a branch instruction and a branch is made Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an instruction 1 delay slot instruction and an SQ store instruction. Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 (instruction 1 branch destination) ; May be executed if an SQ store instruction. Instruction 8 ; May be executed if an SQ store instruction. Rev. 3.0, 04/02, page 116 of 1064 Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if an SQ store instruction. Instruction 3 ; May be executed if an SQ store instruction. Instruction 4 ; May be executed if an SQ store instruction. Instruction 5 Both A and B below must be satisfied in order to prevent this bug. A: When a store queue store instruction is executed after a PREF instruction for transfer from that same store queue (SQ0, SQ1) to external memory, (1) and (2) below must be satisfied. 1 (1) Insert three NOP instructions* between the two instructions. (2) Do not place a PREF instruction for transfer from a store queue to external memory in the delay slot of a branch instruction. B: Do not execute a PREF instruction for transfer from a store queue to external memory within an exception handling routine. If the above is executed and there is a store queue store instruction among the four 2 instructions* including the instruction at the address indicated by the SPC, the state of the contents transferred to external memory by the PREF instruction may be that when execution of this store instruction is completed. Notes: *1 If there are other instructions between the two instructions, this bug can be prevented if the total number of other instructions plus NOP instructions is at least three. *2 If the instruction at the address indicated by the SPC is a branch instruction, this also applies to two instructions at the branch destination. Rev. 3.0, 04/02, page 117 of 1064 Rev. 3.0, 04/02, page 118 of 1064 Section 5 Exceptions 5.1 Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control flow to an exception handling routine, etc., is given the generic name of exception handling. SH7751 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1. Table 5.1 Exception-Related Registers Abbreviation R/W Initial Value P4 2 Address* TRAPA exception register TRA R/W Undefined H'FF00 0020 H'1F00 0020 32 Exception event register EXPEVT R/W H'0000 0000/ 1 H'0000 0020* H'FF00 0024 H'1F00 0024 32 Interrupt event register INTEVT R/W Undefined H'FF00 0028 H'1F00 0028 32 Name Area 7 2 Address* Access Size Notes: *1 H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset. *2 P4 address is the address when using the virtual/physical address space P4 area. When making an access from area 7 in the physical address space using the TLB, the three high most bits of the address are ignored. Rev. 3.0, 04/02, page 119 of 1064 5.2 Register Descriptions There are three registers related to exception handling. Addresses are allocated for these, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception is accepted. EXPEVT can also be modified by software. 2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 14bit exception code. The exception code set in INTEVT is that for an interrupt request. The exception code is set automatically by hardware when an exception is accepted. INTEVT can also be modified by software. 3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1. EXPEVT 31 12 11 0 0 Exception code 0 INTEVT 14 13 31 0 0 0 Exception code TRA 10 9 31 0 0 2 1 0 imm 0 0 0: Reserved bits. These bits are always read as 0, and should only be written with 0. imm: 8-bit immediate data of the TRAPA instruction Figure 5.1 Register Bit Configurations Rev. 3.0, 04/02, page 120 of 1064 5.3 Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR) and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register 15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 by an RTE instruction. The basic processing flow is as follows. See section 2, Data Formats and Registers, for the meaning of the individual SR bits. 1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR. 2. The block bit (BL) in SR is set to 1. 3. The mode bit (MD) in SR is set to 1. 4. The register bank bit (RB) in SR is set to 1. 5. In a reset, the FPU disable bit (FD) in SR is cleared to 0. 6. The exception code is written to bits 11–0 of the exception event register (EXPEVT) or to bits 13–0 of the interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins. 5.3.2 Exception Handling Vector Addresses The reset vector address is fixed at H'A000 0000. Exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (P1, P2) should be specified for vector addresses. Rev. 3.0, 04/02, page 121 of 1064 5.4 Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Category Mode Exception Reset General exception Abort type Power-on reset Priority Priority Vector Level Order Address Offset Exception Code 1 1 H'A000 0000 — H’000 Manual reset 1 2 H'A000 0000 — H’020 H-UDI reset 1 1 H'A000 0000 — H’000 Instruction TLB multiple-hit exception 1 3 H'A000 0000 — H’140 Data TLB multiple-hit exception 1 4 H'A000 0000 — H’140 2 0 (VBR/DBR) H'100/— H'1E0 ReUser break before instruction 1 execution execution* type Instruction address error 2 1 (VBR) H'100 H'0E0 Instruction TLB miss exception 2 2 (VBR) H'400 H'040 Instruction TLB protection violation exception 2 3 (VBR) H'100 H'0A0 General illegal instruction exception 2 4 (VBR) H'100 H'180 Slot illegal instruction exception 2 4 (VBR) H'100 H'1A0 General FPU disable exception 2 4 (VBR) H'100 H'800 Slot FPU disable exception 2 4 (VBR) H'100 H'820 Data address error (read) 2 5 (VBR) H'100 H'0E0 Data address error (write) 2 5 (VBR) H'100 H'100 Data TLB miss exception (read) 2 6 (VBR) H'400 H'040 Data TLB miss exception (write) 2 6 (VBR) H'400 H'060 Data TLB protection violation exception (read) 2 7 (VBR) H'100 H'0A0 Data TLB protection violation exception (write) 2 7 (VBR) H'100 H'0C0 FPU exception 2 8 (VBR) H'100 H'120 Initial page write exception Completion Unconditional trap (TRAPA) type User break after instruction 1 execution* Rev. 3.0, 04/02, page 122 of 1064 2 9 (VBR) H'100 H'080 2 4 (VBR) H'100 H'160 2 10 (VBR/DBR) H'100/— H'1E0 Table 5.2 Exceptions (cont) Exception Execution Category Mode Exception Interrupt Completion Nonmaskable interrupt type External IRL3–IRL0 0 interrupts 1 Priority Priority Vector Level Order Address Offset Exception Code 3 — (VBR) H'600 H'1C0 4 *2 (VBR) H'600 H'200 H'220 2 H'240 3 H'260 4 H'280 5 H'2A0 6 H'2C0 7 H'2E0 8 H'300 9 H'320 A H'340 B H'360 C H'380 D H'3A0 E Peripheral TMU0 module TMU1 interrupt (module/ TMU2 source) TUNI0 4 H'3C0 *2 (VBR) H'600 H'400 TUNI1 H'420 TUNI2 H'440 TICPI2 H'460 TMU3 TUNI3 H'B00 TMU4 TUNI4 H'B80 RTC ATI H'480 PRI H'4A0 SCI WDT REF CUI H'4C0 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 ITI H'560 RCMI H'580 ROVI H'5A0 Rev. 3.0, 04/02, page 123 of 1064 Table 5.2 Exceptions (cont) Exception Execution Category Mode Exception Interrupt Completion Peripheral H-UDI H-UDI type module GPIO GPIOI interrupt (module/ DMAC DMTE0 source) DMTE1 4 H'600 H'600 *2 (VBR) H'660 H'680 H'6A0 3 H'780 3 H'7A0 3 H'7C0 3 H'7E0 DMTE5* DMTE6* SCIF Exception Code H'640 DMTE3 DMTE7* Offset H'620 DMTE2 DMTE4* Priority Priority Vector Level Order Address DMAE H'6C0 ERI H'700 RXI H'720 BRI H'740 TXI H'760 PCIC(0) PCISERR H'A00 PCIC(1) PCIERR H'AE0 PCIPWDWN H'AC0 PCIPWON H'AA0 PCIDMA0 H'A80 PCIDMA1 H'A60 PCIDMA2 H'A40 PCIDMA3 H'A20 Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL: Interrupt request level (pins IRL3–IRL0). Module/source: See the sections on the relevant peripheral modules. Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100. *2 The priority order of external interrupts and peripheral module interrupts can be set by software. *3 SH7751R only Rev. 3.0, 04/02, page 124 of 1064 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers may be set automatically by hardware, depending on the exception. For details, see section 5.6, Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, and in the case of instructions in which two data accesses are performed. Reset requested? Yes No Execute next instruction General exception requested? Yes No Interrupt requested? No Is highestYes priority exception re-exception type? Cancel instruction execution No result Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 PC ← (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset)) EXPEVT ← exception code SR. {MD, RB, BL, FD, IMASK} ← 11101111 PC ← H'A000 0000 Figure 5.2 Instruction Execution and Exception Handling Rev. 3.0, 04/02, page 125 of 1064 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3. Rev. 3.0, 04/02, page 126 of 1064 Pipeline flow: Instruction n Instruction n+1 IF ID EX TLB miss (data access) MA WB IF ID EX MA WB General illegal instruction exception Instruction n+2 TLB miss (instruction access) IF ID EX MA WB Instruction n+3 IF ID EX MA WB IF: ID: EX: MA: WB: Instruction fetch Instruction decode Instruction execution Memory access Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling: Program order TLB miss (instruction n) 1 Re-execution of instruction n General illegal instruction exception (instruction n+1) 2 Re-execution of instruction n+1 TLB miss (instruction n+2) 3 Re-execution of instruction n+2 Execution of instruction n+3 4 Figure 5.3 Example of General Exception Acceptance Order Rev. 3.0, 04/02, page 127 of 1064 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU’s internal registers and the registers of the other modules are set to their post-reset state, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 20, User Break Controller. If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 5.5.4 Return from Exception Handling The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction. 5.6 Description of Exceptions The various exception handling operations are described here, covering exception sources, transition addresses, and processor operation when a transition is made. Rev. 3.0, 04/02, page 128 of 1064 5.6.1 Resets (1) Power-On Reset
Sources: 
 pin low level  When the watchdog timer overflows while the WT/ bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Transition address: H'A000 0000
Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the 
 pin and
 pin must be driven low. It is therefore essential to execute a power-on reset and drive the 
 pin low when powering on. If the
 pin is driven high before the 
 pin while both these pins are low, a manual reset may occur after the power-on reset operation. The
 pin must be driven high at the same time as, or after, the 
 pin. Power_on_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev. 3.0, 04/02, page 129 of 1064 (2) Manual Reset
Sources:  
 pin low level and
 pin high level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Transition address: H'A000 0000
Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. Manual_reset() { EXPEVT = H'00000020; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Table 5.3 Types of Reset Reset State Transition Conditions Internal States Type
  CPU Power-on reset — Low Initialized Manual reset Low High Initialized Rev. 3.0, 04/02, page 130 of 1064 On-Chip Peripheral Modules See Register Configuration in each section (3) H-UDI Reset
Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion)
Transition address: H'A000 0000
Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. H-UDI_reset() { EXPEVT = H'00000000; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A0000000; } Rev. 3.0, 04/02, page 131 of 1064 (4) Instruction TLB Multiple-Hit Exception
Source: Multiple ITLB address matches
Transition address: H'A000 0000
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev. 3.0, 04/02, page 132 of 1064 (5) Data TLB Multiple-Hit Exception
Source: Multiple UTLB address matches
Transition address: H'A000 0000
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections. TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'00000140; VBR = H'00000000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A0000000; } Rev. 3.0, 04/02, page 133 of 1064 5.6.2 General Exceptions (1) Data TLB Miss Exception
Source: Address mismatch in UTLB address comparison
Transition address: VBR + H'0000 0400
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'00000040 : H'00000060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev. 3.0, 04/02, page 134 of 1064 (2) Instruction TLB Miss Exception
Source: Address mismatch in ITLB address comparison
Transition address: VBR + H'0000 0400
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions. ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000400; } Rev. 3.0, 04/02, page 135 of 1064 (3) Initial Page Write Exception
Source: TLB is hit in a store access, but dirty bit D = 0
Transition address: VBR + H'0000 0100
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'00000080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 3.0, 04/02, page 136 of 1064 (4) Data TLB Protection Violation Exception
Source: The access does not accord with the UTLB protection information (PR bits) shown below. PR Privileged Mode 00 Only read access possible Access not possible 01 Read/write access possible Access not possible 10 Only read access possible Only read access possible 11 Read/write access possible Read/write access possible
Transition address: VBR + H'0000 0100
Transition operations: User Mode The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'000000A0 : H'000000C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 3.0, 04/02, page 137 of 1064 (5) Instruction TLB Protection Violation Exception
Source: The access does not accord with the ITLB protection information (PR bits) shown below. PR Privileged Mode User Mode 0 Access possible Access not possible 1 Access possible Access possible
Transition address: VBR + H'0000 0100
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 3.0, 04/02, page 138 of 1064 (6) Data Address Error
Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7)  Access to area H'8000 0000–H'FFFF FFFF in user mode
Transition address: VBR + H'0000 0100
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'000000E0: H'00000100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 3.0, 04/02, page 139 of 1064 (7) Instruction Address Error
Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode
Transition address: VBR + H'0000 0100
Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit (MMU). Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'000000E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'00000100; } Rev. 3.0, 04/02, page 140 of 1064 (8) Unconditional Trap
Source: Execution of TRAPA instruction
Transition address: VBR + H'0000 0100
Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm FRm, 1  T Otherwise, 0  T 1111nnnnmmmm0101 — Comparison result FDIV FRm,FRn FRn/FRm  FRn 1111nnnnmmmm0011 — — FLOAT FPUL,FRn (float) FPUL  FRn 1111nnnn00101101 — — FMAC FR0,FRm,FRn FR0*FRm + FRn  FRn 1111nnnnmmmm1110 — — FMUL FRm,FRn FRn*FRm  FRn 1111nnnnmmmm0010 — — FNEG FRn FRn
H'80000000  FRn 1111nnnn01001101 — — FSQRT FRn FRn  FRn 1111nnnn01101101 — — FSUB FRm,FRn FRn – FRm  FRn 1111nnnnmmmm0001 — — FTRC FRm,FPUL (long) FRm  FPUL 1111mmmm00111101 — — Rev. 3.0, 04/02, page 183 of 1064 Table 7.10 Floating-Point Double-Precision Instructions Instruction FABS DRn Operation Instruction Code Privileged T Bit DRn & H'7FFF FFFF FFFF FFFF  DRn 1111nnn001011101 — — FADD DRm,DRn DRn + DRm  DRn 1111nnn0mmm00000 — — FCMP/EQ DRm,DRn When DRn = DRm, 1  T Otherwise, 0  T 1111nnn0mmm00100 — Comparison result FCMP/GT DRm,DRn When DRn > DRm, 1  T Otherwise, 0  T 1111nnn0mmm00101 — Comparison result FDIV DRm,DRn DRn /DRm  DRn 1111nnn0mmm00011 — — FCNVDS DRm,FPUL double_to_ float[DRm]  FPUL 1111mmm010111101 — — FCNVSD FPUL,DRn float_to_ double [FPUL]  DRn 1111nnn010101101 — — FLOAT FPUL,DRn (float)FPUL  DRn 1111nnn000101101 — — FMUL DRm,DRn DRn *DRm  DRn 1111nnn0mmm00010 — — FNEG DRn DRn ^ H'8000 0000 0000 0000  DRn 1111nnn001001101 — — FSQRT DRn DRn  DRn DRn – DRm  DRn (long) DRm  FPUL 1111nnn001101101 — — 1111nnn0mmm00001 — — 1111mmm000111101 — — Instruction Code Privileged T Bit Rm 0100mmmm01101010 — — Rm 0100mmmm01011010 — — 0100mmmm01100110 — — FSUB DRm,DRn FTRC DRm,FPUL Table 7.11 Floating-Point Control Instructions Instruction LDS Rm,FPSCR LDS Rm,FPUL LDS.L @Rm+,FPSCR LDS.L @Rm+,FPUL STS FPSCR,Rn STS FPUL,Rn STS.L FPSCR,@-Rn STS.L FPUL,@-Rn Operation  FPSCR  FPUL (Rm)  FPSCR, Rm+4  Rm (Rm)  FPUL, Rm+4  Rm FPSCR  Rn FPUL  Rn Rn – 4  Rn, FPSCR  (Rn) Rn – 4  Rn, FPUL  (Rn) Rev. 3.0, 04/02, page 184 of 1064 0100mmmm01010110 — — 0000nnnn01101010 — — 0000nnnn01011010 — — 0100nnnn01100010 — — 0100nnnn01010010 — — Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit FMOV DRm,XDn DRm  XDn 1111nnn1mmm01100 — — FMOV XDm,DRn XDm  DRn 1111nnn0mmm11100 — — FMOV XDm,XDn XDm  XDn 1111nnn1mmm11100 — — FMOV @Rm,XDn (Rm)  XDn 1111nnn1mmmm1000 — — FMOV @Rm+,XDn (Rm)  XDn, Rm + 8  Rm 1111nnn1mmmm1001 — — FMOV @(R0,Rm),XDn (R0 + Rm)  XDn 1111nnn1mmmm0110 — — FMOV XDm,@Rn XDm  (Rn) 1111nnnnmmm11010 — — FMOV XDm,@-Rn Rn – 8  Rn, XDm  (Rn) 1111nnnnmmm11011 — — FMOV XDm,@(R0,Rn) XDm  (R0+Rn) 1111nnnnmmm10111 — — FIPR FVm,FVn inner_product [FVm, FVn]  FR[n+3] 1111nnmm11101101 — — FTRV XMTRX,FVn transform_vector [XMTRX, FVn] 1111nn0111111101 — — 1111101111111101 — — 1111001111111101 — —  FVn FRCHG ~FPSCR.FR FSCHG ~FPSCR.SZ  SPFCR.FR  SPFCR.SZ Rev. 3.0, 04/02, page 185 of 1064 Rev. 3.0, 04/02, page 186 of 1064 Section 8 Pipelining The SH7751 Series is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7751 Series. 8.1 Pipelines Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA), and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2 shows the instruction execution patterns. Rev. 3.0, 04/02, page 187 of 1064 1. General Pipeline I D EX • Instruction fetch • Instruction • Operation decode • Issue • Register read • Destination address calculation for PC-relative branch NA • Non-memory data access S • Write-back 2. General Load/Store Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read EX • Address calculation MA • Memory data access S • Write-back 3. Special Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read SX • Operation NA • Non-memory data access S • Write-back 4. Special Load/Store Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read SX • Address calculation MA • Memory data access S • Write-back 5. Floating-Point Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read F1 • Computation 1 F2 • Computation 2 FS • Computation 3 • Write-back 6. Floating-Point Extended Pipeline I D • Instruction fetch • Instruction decode • Issue • Register read F0 • Computation 0 F1 • Computation 1 7. FDIV/FSQRT Pipeline F3 Computation: Takes several cycles Figure 8.1 Basic Pipelines Rev. 3.0, 04/02, page 188 of 1064 F2 • Computation 2 FS • Computation 3 • Write-back 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG I D EX NA S 2. Load/store: 1 issue cycle MOV.[BWL], FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR I D EX MA S 3. GBR-based load/store: 1 issue cycle MOV.[BWL]@(d,GBR) I D SX MA S 4. JMP, RTS, BRAF: 2 issue cycles I D EX D NA EX S NA S SX D MA SX D S NA SX S NA S S NA SX D S NA SX S MA S S NA EX D S NA EX S MA S S NA EX D S NA EX S NA S S NA EX S NA S 5. TST.B: 3 issue cycles I D 6. AND.B, OR.B, XOR.B: 4 issue cycles I D SX D MA SX D 7. TAS.B: 5 issue cycles I D EX D MA EX D S MA EX D 8. RTE: 5 issue cycles I D EX D NA EX D S NA EX D 9. SLEEP: 4 issue cycles I D EX D NA EX D S NA EX D Figure 8.2 Instruction Execution Patterns Rev. 3.0, 04/02, page 189 of 1064 10. OCBI: 1 issue cycle I D EX MA S MA MA S MA 11. OCBP, OCBWB: 1 issue cycle I D EX MA MA MA 12. MOVCA.L: 1 issue cycle I D EX MA S MA MA MA MA MA MA 13. TRAPA: 7 issue cycles I D EX D NA EX D S NA EX D S NA EX D S NA EX D S NA EX D S NA EX 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle I D EX NA SX S SX 15. LDC to GBR: 3 issue cycles I D EX D NA SX D S SX 16. LDC to SR: 4 issue cycles I D EX D NA SX D S SX D SX 17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle I D EX MA SX S SX 18. LDC.L to GBR: 3 issue cycles I D EX D MA SX D S SX Figure 8.2 Instruction Execution Patterns (cont) Rev. 3.0, 04/02, page 190 of 1064 S NA S 19. LDC.L to SR: 4 issue cycles I D EX D MA SX D S SX D SX 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S NA S S NA SX S NA 21. STC.L from SGR: 3 issue cycles I D SX D NA SX D S 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles I D SX D NA SX S MA S S NA SX S MA 23. STC.L from SGR: 3 issue cycles I D SX D NA SX D S 24. LDS to PR, JSR, BSRF: 2 issue cycles I D EX D NA SX S SX 25. LDS.L to PR: 2 issue cycles I D EX D MA SX S SX 26. STS from PR: 2 issue cycles I D SX D NA SX S NA S NA SX S MA S 27. STS.L from PR: 2 issue cycles I D SX D 28. CLRMAC, LDS to MACH/L: 1 issue cycle I D EX NA F1 S F1 F2 FS F2 FS 29. LDS.L to MACH/L: 1 issue cycle I D EX MA F1 S F1 30. STS from MACH/L: 1 issue cycle I D EX NA S Figure 8.2 Instruction Execution Patterns (cont) Rev. 3.0, 04/02, page 191 of 1064 31. STS.L from MACH/L: 1 issue cycle I D EX MA S NA F1 S 32. LDS to FPSCR: 1 issue cycle I D EX F1 F1 33. LDS.L to FPSCR: 1 issue cycle I D EX MA F1 S F1 F1 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W I D EX D NA EX S NA (CPU) S f1 (FPU) f1 f1 f1 F2 FS 35. MAC.W, MAC.L: 2 issue cycles I D EX D MA EX S MA (CPU) S f1 (FPU) f1 f1 f1 F2 FS 36. Single-precision floating-point computation: 1 issue cycle FCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG I D F1 F2 FS 37. Single-precision FDIV/SQRT: 1 issue cycle I D F1 F2 FS F3 F1 F2 FS FS F2 F1 FS F2 38. Double-precision floating-point computation 1: 1 issue cycle FCNVDS, FCNVSD, FLOAT, FTRC I D F1 d F2 F1 FS F2 FS 39. Double-precision floating-point computation 2: 1 issue cycle FADD, FMUL, FSUB I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 Figure 8.2 Instruction Execution Patterns (cont) Rev. 3.0, 04/02, page 192 of 1064 FS 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT D I F1 D F2 F1 FS F2 FS 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT D I F1 d F2 F1 FS F2 F3 F1 F2 F1 FS F2 F1 42. FIPR: 1 issue cycle I D F0 F1 F2 FS F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 FS 43. FTRV: 1 issue cycle D I Notes: F0 d FS F2 F1 FS F2 FS ?? : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel. D : Locks D-stage d : Register read only ?? : Locks, but no operation is executed. f1 : Can overlap another f1, but not another F1. Figure 8.2 Instruction Execution Patterns (cont) Rev. 3.0, 04/02, page 193 of 1064 8.2 Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1. MT Group CLRT CMP/HI Rm,Rn MOV CMP/EQ #imm,R0 CMP/HS Rm,Rn NOP Rm,Rn CMP/EQ Rm,Rn CMP/PL Rn SETT CMP/GE Rm,Rn CMP/PZ Rn TST #imm,R0 CMP/GT Rm,Rn CMP/STR Rm,Rn TST Rm,Rn ADD #imm,Rn MOVT Rn SHLL2 Rn ADD Rm,Rn NEG Rm,Rn SHLL8 Rn ADDC Rm,Rn NEGC Rm,Rn SHLR Rn ADDV Rm,Rn NOT Rm,Rn SHLR16 Rn AND #imm,R0 OR #imm,R0 SHLR2 Rn AND Rm,Rn OR Rm,Rn SHLR8 Rn DIV0S Rm,Rn ROTCL Rn SUB Rm,Rn ROTCR Rn SUBC Rm,Rn 2. EX Group DIV0U DIV1 Rm,Rn ROTL Rn SUBV Rm,Rn DT Rn ROTR Rn SWAP.B Rm,Rn EXTS.B Rm,Rn SHAD Rm,Rn SWAP.W Rm,Rn EXTS.W Rm,Rn SHAL Rn XOR #imm,R0 EXTU.B Rm,Rn SHAR Rn XOR Rm,Rn EXTU.W Rm,Rn SHLD Rm,Rn XTRCT Rm,Rn MOV #imm,Rn SHLL MOVA @(disp,PC),R0 SHLL16 Rn BF disp BRA disp BT disp BF/S disp BSR disp BT/S disp Rn 3. BR Group Rev. 3.0, 04/02, page 194 of 1064 Table 8.1 Instruction Groups (cont) 4. LS Group FABS DRn FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FRn FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FRn FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FRn FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG DRn MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG FRn MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W @(disp,PC),Rn FMOV @Rm,DRn LDS Rm,FPUL MOV.W @(disp,Rm),R0 FMOV @Rm,XDn MOV.B @(disp,GBR),R0 MOV.W @(R0,Rm),Rn FMOV @Rm+,DRn MOV.B @(disp,Rm),R0 MOV.W @Rm,Rn FMOV @Rm+,XDn MOV.B @(R0,Rm),Rn MOV.W @Rm+,Rn FMOV DRm,@(R0,Rn) MOV.B @Rm,Rn MOV.W R0,@(disp,GBR) FMOV DRm,@-Rn MOV.B @Rm+,Rn MOV.W R0,@(disp,Rn) FMOV DRm,@Rn MOV.B R0,@(disp,GBR) MOV.W Rm,@(R0,Rn) FMOV DRm,DRn MOV.B R0,@(disp,Rn) MOV.W Rm,@-Rn FMOV DRm,XDn MOV.B Rm,@(R0,Rn) MOV.W Rm,@Rn FMOV FRm,FRn MOV.B Rm,@-Rn MOVCA.L R0,@Rn FMOV XDm,@(R0,Rn) MOV.B Rm,@Rn OCBI @Rn FMOV XDm,@-Rn MOV.L @(disp,GBR),R0 OCBP @Rn FMOV XDm,@Rn MOV.L @(disp,PC),Rn OCBWB @Rn FMOV XDm,DRn MOV.L @(disp,Rm),Rn PREF @Rn FMOV XDm,XDn MOV.L @(R0,Rm),Rn STS FPUL,Rn FMOV.S @(R0,Rm),FRn MOV.L @Rm,Rn FMOV.S @Rm,FRn MOV.L @Rm+,Rn Rev. 3.0, 04/02, page 195 of 1064 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT DRn FADD FRm,FRn FLOAT FPUL,DRn FSQRT FRn FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV DRm,DRn FRCHG FTRV XMTRX,FVn FDIV FRm,FRn FSCHG Rev. 3.0, 04/02, page 196 of 1064 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR STC SR,Rn BRAF Rm Rm,MACH STC SSR,Rn BSRF Rm LDS LDS Rm,MACL STC VBR,Rn CLRMAC LDS Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L @Rm+,MACL STC.L SPC,@-Rn @Rm+,PR FCMP/GT DRm,DRn LDS.L JMP @Rn LDTLB STC.L SR,@-Rn STC.L SSR,@-Rn JSR @Rn MAC.L @Rm+,@Rn+ STC.L VBR,@-Rn LDC Rm,DBR MAC.W @Rm+,@Rn+ STS FPSCR,Rn LDC Rm,GBR MUL.L Rm,Rn STS MACH,Rn LDC Rm,Rp_BANK MULS.W Rm,Rn STS MACL,Rn LDC Rm,SPC MULU.W Rm,Rn STS PR,Rn LDC Rm,SR OR.B #imm,@(R0,GBR) STS.L LDC Rm,SSR RTE STS.L FPUL,@-Rn LDC Rm,VBR RTS STS.L MACH,@-Rn LDC.L @Rm+,DBR SETS STS.L MACL,@-Rn LDC.L @Rm+,GBR SLEEP STS.L PR,@-Rn LDC.L @Rm+,Rp_BANK STC DBR,Rn TAS.B @Rn LDC.L @Rm+,SPC STC GBR,Rn TRAPA #imm LDC.L @Rm+,SR STC Rp_BANK,Rn TST.B #imm,@(R0,GBR) LDC.L @Rm+,SSR STC SGR,Rn XOR.B #imm,@(R0,GBR) LDC.L @Rm+,VBR STC SPC,Rn FPSCR,@-Rn Rev. 3.0, 04/02, page 197 of 1064 Table 8.2 Parallel-Executability 2nd Instruction 1st Instruction MT EX BR LS FE CO MT O O O O O X EX O X O O O X BR O O X O O X LS O O O X O X FE O O O O X X CO X X X X X X O: Can be executed in parallel X: Cannot be executed in parallel 8.3 Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows:
I-clock: CPU, FPU, MMU, caches
B-clock: External bus controller
P-clock: Peripheral units The frequency ratios of the three clocks are determined with the frequency control register (FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For details of FRQCR, see section 10, Clock Oscillation Circuits. Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or freeze are not considered in this table.
Issue rate: Interval between the issue of an instruction and that of the next instruction
Latency: Interval between the issue of an instruction and the generation of its result (completion)
Instruction execution pattern (see figure 8.2)
Lock stage: Locked pipeline stages(see table 8.3)
Lock start: Interval between the issue of an instruction and the start of locking (see table 8.3)
Lock cycle: Lock time (see table 8.3) Rev. 3.0, 04/02, page 198 of 1064 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction; the only exception is when two instructions are executed in parallel under parallel-executability conditions. Refer to (a) through (d) in figure 8.3 for some simple examples. Latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. When there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles:
(Latency) cycles when there is flow dependency (read-after-write)
(Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write)  Single/double-precision FDIV, FSQRT is the preceding instruction (latency – 1) cycles  The other FE group except above is the preceding instruction (latency – 2) cycles
5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases:  FTRV is the preceding instruction (5 cycles)  A double-precision FADD, FSUB, or FMUL is the preceding instruction (2 cycles) In the case of flow dependency, latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 8.3 (e)).
When a floating-point computation is followed by a floating-point register store, the latency of the floating-point computation may be decreased by 1 cycle.
If there is a load of the shift amount immediately before an SHAD/SHLD instruction, the latency of the load is increased by 1 cycle.
If an instruction with a latency of less than 2 cycles, including write-back to a floating-point register, is followed by a double-precision floating-point instruction, FIPR, or FTRV, the latency of the first instruction is increased to 2 cycles. The number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 8.3. (e)). Output dependency occurs when the destination operands are the same in a preceding FE group instruction and a following LS group instruction. For the stall cycles of an instruction with output dependency, the longest latency to the last writeback among all the destination operands must be applied instead of “latency” (see figure 8.3 (f)). A stall due to output dependency with respect to FPSCR, which reflects the result of a floatingpoint operation, never occurs. For example, when FADD follows FDIV with no dependency between floating-point registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Rev. 3.0, 04/02, page 199 of 1064 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that attempts to use the locked resource is stalled (figure 8.3 (h)). This kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate the interfering instructions. For example, when a load instruction and an ADD instruction that references the loaded value are consecutive, the 2-cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software performance can be improved by such instruction scheduling. Other causes of a stall are as follows.
Instruction TLB miss
Instruction access to external memory (instruction cache miss, etc.)
Data access to external memory (operand cache miss, etc.)
Data access to a memory-mapped control register During the penalty cycles of an instruction TLB miss or external instruction access, no instruction is issued, but execution of instructions that have already been issued continues. The penalty for a data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted until the arrival of the requested data. The number of penalty cycles for instruction and data accesses is largely dependent on the user’s memory subsystems. Rev. 3.0, 04/02, page 200 of 1064 (a) Serial execution: non-parallel-executable instructions SHAD R0,R1 ADD R2,R3 next I I D I 1 issue cycle EX NA EX D 1 stall cycle D S NA EX-group SHAD and EX-group ADD cannot be executed in parallel. Therefore, SHAD is issued first, and the following ADD is recombined with the next instruction. S ... (b) Parallel execution: parallel-executable and no dependency ADD R2,R1 MOV.L @R4,R5 I I D D 1 issue cycle EX NA EX MA EX-group ADD and LS-group MOV.L can be executed in parallel. Overlapping of stages in the 2nd instruction is possible. S S (c) Issue rate: multi-step instruction 4 issue cycles AND.B#1,@(R0,GBR) MOV next R1,R2 I D SX D MA SX D I 4 stall cycles S NA SX D i I S NA SX D ... S MA E S A AND.B and MOV are fetched simultaneously, but MOV is stalled due to resource locking. After the lock is released, MOV is refetched together with the next instruction. S (d) Branch BT/S L_far ADD R0,R1 SUB R2,R3 I I BT/S L_far ADD R0,R1 I I D D I I D D I No stall D D I L_far BT L_skip ADD #1,R0 L_skip: EX EX D NA NA EX S S NA No stall occurs if the branch is not taken. S 2-cycle latency for I-stage of branch destination If the branch is taken, the I-stage of the EX NA S branch destination is stalled for the period EX NA S of latency. This stall can be covered with a 1 stall cycle delay slot instruction which is not parallelI D ... executable with the branch instruction. EX — D NA — ... S — Even if the BT/BF branch is taken, the Istage of the branch destination is not stalled if the displacement is zero. Figure 8.3 Examples of Pipelined Execution Rev. 3.0, 04/02, page 201 of 1064 (e) Flow dependency MOV ADD R0,R1 R2,R1 ADD R2,R1 MOV.L @R1,R1 next MOV.L @R1,R1 ADD R0,R1 next I I D D Zero-cycle latency EX NA S EX NA S I I D i I 1 stall cycle I D I I 1-cycle latency EX NA S EX MA D ... EX D ... The following instruction, ADD, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. ADD and MOV.L are not executed in parallel, since MOV.L references the result of ADD as its destination address. S 2-cycle latency S EX NA 1 stall cycle Because MOV.L and ADD are not fetched simultaneously in this example, ADD is stalled for only 1 cycle even though the latency of MOV.L is 2 cycles. MA S 2-cycle latency 1-cycle increase MOV.L @R1,R1 SHAD R1,R2 next I D I I EX MA D ... S d EX NA S 2 stall cycles Due to the flow dependency between the load and the SHAD/SHLD shift amount, the latency of the load is increased to 3 cycles. 4-cycle latency for FPSCR FADD STS STS FR1,FR2 FPUL,R1 FPSCR,R2 I D I F1 D I F2 EX FS NA S D EX NA S 2 stall cycles 7-cycle latency for lower FR 8-cycle latency for upper FR FADD FMOV FMOV DR0,DR2 FR3,FR5 FR2,FR4 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 I FS F2 D I FR3 write FS FR2 write EX NA S EX D NA 3-cycle latency for upper/lower FR FLOAT FPUL,DR0 FMOV.S FR0,@-R15 I D I D F1 d F2 F1 FS F2 FR1 write FS FR0 write EX MA S Zero-cycle latency 3-cycle increase FLDI1 FIPR FR3 FV0,FV4 I I D D EX NA S d F0 F1 3 stall cycles F2 FS F2 F1 F0 d FS F2 F1 F0 2-cycle latency 1-cycle increase FMOV FTRV @R1,XD14 XMTRX,FV0 I I D D EX MA S d 3 stall cycles F0 d F1 F0 d FS F2 F1 Figure 8.3 Examples of Pipelined Execution (cont) Rev. 3.0, 04/02, page 202 of 1064 FS F2 FS S (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions LDS FLOAT LDS FLOAT R0,FPUL FPUL,FR0 R1,FPUL FPUL,FR1 I FTRC STS FTRC STS FR0,FPUL FPUL,R0 FR1,FPUL FPUL,R1 I D I I D I I EX D D I NA F1 EX D S F2 NA F1 F1 D D I F2 EX F1 D FS F1 F2 FS F3 NA F2 EX FS S F2 S FS NA FS Effectively 1-cycle latency for consecutive FTRC/STS instructions S (f) Output dependency 11-cycle latency FSQRT FR4 I D FMOV FR0,FR4 I D FADD DR0,DR2 F1 FS F1 FS F2 The registers are written-back in program order. 7-cycle latency for lower FR 8-cycle latency for upper FR I FMOV F2 10 stall cycles = latency (11) - 1 I FR0,FR3 D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 FS F2 F1 D FS F2 EX FR3 write FS FR2 write NA S 6 stall cycles = longest latency (8) - 2 (g) Anti-flow dependency FTRV XMTRX,FV0 FMOV @R1,XD0 I I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1 D FS F2 EX FS MA S FS F2 F1 FS F2 FS 5 stall cycles FADD DR0,DR2 FMOV FR4,FR1 I I D F1 d F2 F1 d D FS F2 F1 d EX 2 stall cycles FS F2 F1 d FS F2 F1 NA S Figure 8.3 Examples of Pipelined Execution (cont) Rev. 3.0, 04/02, page 203 of 1064 (h) Resource conflict #1 #2 #3 .................................................. #8 #9 #10 #11 #12 1 cycle/issue FDIV FR6,FR7 I F1 D F2 FS Latency F1 stage locked for 1 cycle F3 F1 I FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 D F1 I D F2 FS F1 F2 F2 FS F1 F2 FS ... : FMAC FR0,FR12,FR13 I D FS 1 stall cycle (F1 stage resource conflict) I FIPR FV8,FV0 FADD FR15,FR4 F0 D D I F1 F2 F1 FS F2 FS SX D NA SX FS F2 F1 d FS F2 F1 1 stall cycle LDS.L @R15+,PR I STC I EX D D MA SX FS SX GBR,R2 D 3 stall cycles I FADD DR0,DR2 I MAC.W @R1+,@R2+ D F2 F1 d FS F2 F1 d 5 stall cycles EX f1 D S EX f1 MA S f1 F2 f1 MA FS F2 S FS EX f1 MA S D I EX f1 D f1 DR4,DR6 F2 f1 D I 3 stall cycles S FS F2 EX f1 D FS MA EX f1 S MA S f1 F2 f1 2 stall cycles FS F2 F1 d FS F2 F1 d FS F2 F1 d FS F2 F1 d Figure 8.3 Examples of Pipelined Execution (cont) Rev. 3.0, 04/02, page 204 of 1064 FS F2 FS f1 stage can overlap preceding f1, but F1 cannot overlap f1. MA 1 stall cycle FADD FS F2 F1 D I MAC.W @R1+,@R2+ MAC.W @R1+,@R2+ F1 d D S NA FS F2 F1 FS F2 F1 FS ... Table 8.3 Execution Cycles Functional Category No. InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction Data transfer 1 instructions 2 EXTS.B Rm,Rn EX 1 1 #1 — — — EXTS.W Rm,Rn EX 1 1 #1 — — — 3 EXTU.B Rm,Rn EX 1 1 #1 — — — 4 EXTU.W Rm,Rn EX 1 1 #1 — — — 5 MOV Rm,Rn MT 1 0 #1 — — — 6 MOV #imm,Rn EX 1 1 #1 — — — 7 MOVA @(disp,PC),R0 EX 1 1 #1 — — — 8 MOV.W @(disp,PC),Rn LS 1 2 #2 — — — 9 MOV.L @(disp,PC),Rn LS 1 2 #2 — — — 10 MOV.B @Rm,Rn LS 1 2 #2 — — — 11 MOV.W @Rm,Rn LS 1 2 #2 — — — 12 MOV.L @Rm,Rn LS 1 2 #2 — — — 13 MOV.B @Rm+,Rn LS 1 1/2 #2 — — — 14 MOV.W @Rm+,Rn LS 1 1/2 #2 — — — 15 MOV.L @Rm+,Rn LS 1 1/2 #2 — — — 16 MOV.B @(disp,Rm),R0 LS 1 2 #2 — — — 17 MOV.W @(disp,Rm),R0 LS 1 2 #2 — — — 18 MOV.L @(disp,Rm),Rn LS 1 2 #2 — — — 19 MOV.B @(R0,Rm),Rn LS 1 2 #2 — — — 20 MOV.W @(R0,Rm),Rn LS 1 2 #2 — — — 21 MOV.L @(R0,Rm),Rn LS 1 2 #2 — — — 22 MOV.B @(disp,GBR),R0 LS 1 2 #3 — — — 23 MOV.W @(disp,GBR),R0 LS 1 2 #3 — — — 24 MOV.L @(disp,GBR),R0 LS 1 2 #3 — — — 25 MOV.B Rm,@Rn LS 1 1 #2 — — — 26 MOV.W Rm,@Rn LS 1 1 #2 — — — 27 MOV.L Rm,@Rn LS 1 1 #2 — — — 28 MOV.B Rm,@-Rn LS 1 1/1 #2 — — — 29 MOV.W Rm,@-Rn LS 1 1/1 #2 — — — 30 MOV.L Rm,@-Rn LS 1 1/1 #2 — — — 31 MOV.B R0,@(disp,Rn) LS 1 1 #2 — — — Rev. 3.0, 04/02, page 205 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction Data transfer 32 instructions 33 MOV.W R0,@(disp,Rn) LS 1 1 #2 — — — MOV.L Rm,@(disp,Rn) LS 1 1 #2 — — — 34 MOV.B Rm,@(R0,Rn) LS 1 1 #2 — — — 35 MOV.W Rm,@(R0,Rn) LS 1 1 #2 — — — 36 MOV.L Rm,@(R0,Rn) LS 1 1 #2 — — — 37 MOV.B R0,@(disp,GBR) LS 1 1 #3 — — — 38 MOV.W R0,@(disp,GBR) LS 1 1 #3 — — — 39 MOV.L R0,@(disp,GBR) LS 1 1 #3 — — — 40 MOVCA.L R0,@Rn LS 1 3–7 #12 MA 4 3–7 41 MOVT Rn EX 1 1 #1 — — — 42 OCBI @Rn LS 1 1–2 #10 MA 4 1–2 43 OCBP @Rn LS 1 1–5 #11 MA 4 1–5 44 OCBWB @Rn LS 1 1–5 #11 MA 4 1–5 45 PREF @Rn LS 1 1 #2 — — — 46 SWAP.B Rm,Rn EX 1 1 #1 — — — 47 SWAP.W Rm,Rn EX 1 1 #1 — — — 48 XTRCT Rm,Rn EX 1 1 #1 — — — ADD Rm,Rn EX 1 1 #1 — — — Fixed-point 49 arithmetic 50 instructions 51 ADD #imm,Rn EX 1 1 #1 — — — ADDC Rm,Rn EX 1 1 #1 — — — 52 ADDV Rm,Rn EX 1 1 #1 — — — 53 CMP/EQ #imm,R0 MT 1 1 #1 — — — 54 CMP/EQ Rm,Rn MT 1 1 #1 — — — 55 CMP/GE Rm,Rn MT 1 1 #1 — — — 56 CMP/GT Rm,Rn MT 1 1 #1 — — — 57 CMP/HI Rm,Rn MT 1 1 #1 — — — 58 CMP/HS Rm,Rn MT 1 1 #1 — — — 59 CMP/PL Rn MT 1 1 #1 — — — 60 CMP/PZ Rn MT 1 1 #1 — — — 61 CMP/STR Rm,Rn MT 1 1 #1 — — — 62 DIV0S EX 1 1 #1 — — — Rm,Rn Rev. 3.0, 04/02, page 206 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. Fixed-point 63 arithmetic 64 instructions 65 InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction DIV0U DIV1 Rm,Rn DMULS.L EX 1 1 #1 — — — EX 1 1 #1 — — — Rm,Rn CO 2 4/4 #34 F1 4 2 66 DMULU.L Rm,Rn CO 2 4/4 #34 F1 4 2 67 DT Rn EX 1 1 #1 — — — 68 MAC.L @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2 69 MAC.W @Rm+,@Rn+ CO 2 2/2/4/4 #35 F1 4 2 70 MUL.L Rm,Rn CO 2 4/4 #34 F1 4 2 71 MULS.W Rm,Rn CO 2 4/4 #34 F1 4 2 72 MULU.W Rm,Rn CO 2 4/4 #34 F1 4 2 73 NEG Rm,Rn EX 1 1 #1 — — — 74 NEGC Rm,Rn EX 1 1 #1 — — — 75 SUB Rm,Rn EX 1 1 #1 — — — 76 SUBC Rm,Rn EX 1 1 #1 — — — 77 Logical 78 instructions 79 SUBV Rm,Rn EX 1 1 #1 — — — AND Rm,Rn EX 1 1 #1 — — — AND #imm,R0 EX 1 1 #1 — — — 80 AND.B #imm,@(R0,GBR) CO 4 4 #6 — — — 81 NOT Rm,Rn EX 1 1 #1 — — — 82 OR Rm,Rn EX 1 1 #1 — — — 83 OR #imm,R0 EX 1 1 #1 — — — 84 OR.B #imm,@(R0,GBR) CO 4 4 #6 — — — 85 TAS.B @Rn 5 5 #7 — — — 86 TST Rm,Rn MT 1 1 #1 — — — 87 TST #imm,R0 MT 1 1 #1 — — — 88 TST.B #imm,@(R0,GBR) CO 3 3 #5 — — — CO 89 XOR Rm,Rn EX 1 1 #1 — — — 90 XOR #imm,R0 EX 1 1 #1 — — — 91 XOR.B #imm,@(R0,GBR) CO 4 4 #6 — — — Rev. 3.0, 04/02, page 207 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. Shift 92 instructions 93 InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction ROTL Rn EX 1 1 #1 — — — ROTR Rn EX 1 1 #1 — — — 94 ROTCL Rn EX 1 1 #1 — — — 95 ROTCR Rn EX 1 1 #1 — — — 96 SHAD Rm,Rn EX 1 1 #1 — — — 97 SHAL Rn EX 1 1 #1 — — — 98 SHAR Rn EX 1 1 #1 — — — 99 SHLD Rm,Rn EX 1 1 #1 — — — 100 SHLL Rn EX 1 1 #1 — — — 101 SHLL2 Rn EX 1 1 #1 — — — 102 SHLL8 Rn EX 1 1 #1 — — — 103 SHLL16 Rn EX 1 1 #1 — — — 104 SHLR Rn EX 1 1 #1 — — — 105 SHLR2 Rn EX 1 1 #1 — — — 106 SHLR8 Rn EX 1 1 #1 — — — 107 SHLR16 Rn EX 1 1 #1 — — — Branch 108 instructions 109 BF disp BR 1 2 (or 1) #1 — — — BF/S disp BR 1 2 (or 1) #1 — — — 110 BT disp BR 1 2 (or 1) #1 — — — 111 BT/S disp BR 1 2 (or 1) #1 — — — 112 BRA disp BR 1 2 #1 — — — 113 BRAF Rn CO 2 3 #4 — — — 114 BSR disp BR 1 2 #14 SX 3 2 115 BSRF Rn CO 2 3 #24 SX 3 2 116 JMP @Rn CO 2 3 #4 — — — 117 JSR @Rn CO 2 3 #24 SX 3 2 118 RTS CO 2 3 #4 — — — Rev. 3.0, 04/02, page 208 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. System 119 control 120 instructions 121 InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction NOP MT 1 0 #1 — — — CLRMAC CO 1 3 #28 F1 3 2 CLRS CO 1 1 #1 — — — 122 CLRT MT 1 1 #1 — — — 123 SETS CO 1 1 #1 — — — 124 SETT 125 TRAPA #imm MT 1 1 #1 — — — CO 7 7 #13 — — — 126 RTE CO 5 5 #8 — — — 127 SLEEP CO 4 4 #9 — — — 128 LDTLB CO 1 1 #2 — — — 129 LDC Rm,DBR CO 1 3 #14 SX 3 2 130 LDC Rm,GBR CO 3 3 #15 SX 3 2 131 LDC Rm,Rp_BANK CO 1 3 #14 SX 3 2 132 LDC Rm,SR CO 4 4 #16 SX 3 2 133 LDC Rm,SSR CO 1 3 #14 SX 3 2 134 LDC Rm,SPC CO 1 3 #14 SX 3 2 135 LDC Rm,VBR CO 1 3 #14 SX 3 2 136 LDC.L @Rm+,DBR CO 1 1/3 #17 SX 3 2 137 LDC.L @Rm+,GBR CO 3 3/3 #18 SX 3 2 138 LDC.L @Rm+,Rp_BANK CO 1 1/3 #17 SX 3 2 139 LDC.L @Rm+,SR CO 4 4/4 #19 SX 3 2 140 LDC.L @Rm+,SSR CO 1 1/3 #17 SX 3 2 141 LDC.L @Rm+,SPC CO 1 1/3 #17 SX 3 2 142 LDC.L @Rm+,VBR CO 1 1/3 #17 SX 3 2 143 LDS Rm,MACH CO 1 3 #28 F1 3 2 144 LDS Rm,MACL CO 1 3 #28 F1 3 2 145 LDS Rm,PR CO 2 3 #24 SX 3 2 146 LDS.L @Rm+,MACH CO 1 1/3 #29 F1 3 2 147 LDS.L @Rm+,MACL CO 1 1/3 #29 F1 3 2 148 LDS.L @Rm+,PR CO 2 2/3 #25 SX 3 2 149 STC DBR,Rn CO 2 2 #20 — — — 150 STC SGR,Rn CO 3 3 #21 — — — Rev. 3.0, 04/02, page 209 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction System 151 control 152 instructions 153 STC GBR,Rn CO 2 2 #20 — — — STC Rp_BANK,Rn CO 2 2 #20 — — — STC SR,Rn CO 2 2 #20 — — — 154 STC SSR,Rn CO 2 2 #20 — — — 155 STC SPC,Rn CO 2 2 #20 — — — 156 STC VBR,Rn CO 2 2 #20 — — — 157 STC.L DBR,@-Rn CO 2 2/2 #22 — — — 158 STC.L SGR,@-Rn CO 3 3/3 #23 — — — 159 STC.L GBR,@-Rn CO 2 2/2 #22 — — — 160 STC.L Rp_BANK,@-Rn CO 2 2/2 #22 — — — 161 STC.L SR,@-Rn CO 2 2/2 #22 — — — 162 STC.L SSR,@-Rn CO 2 2/2 #22 — — — 163 STC.L SPC,@-Rn CO 2 2/2 #22 — — — 164 STC.L VBR,@-Rn CO 2 2/2 #22 — — — 165 STS MACH,Rn CO 1 3 #30 — — — 166 STS MACL,Rn CO 1 3 #30 — — — 167 STS PR,Rn CO 2 2 #26 — — — 168 STS.L MACH,@-Rn CO 1 1/1 #31 — — — 169 STS.L MACL,@-Rn CO 1 1/1 #31 — — — 170 STS.L PR,@-Rn CO 2 2/2 #27 — — — Single171 precision 172 floating-point instructions 173 FLDI0 FRn LS 1 0 #1 — — — FLDI1 FRn LS 1 0 #1 — — — FMOV FRm,FRn LS 1 0 #1 — — — 174 FMOV.S @Rm,FRn LS 1 2 #2 — — — 175 FMOV.S @Rm+,FRn LS 1 1/2 #2 — — — 176 FMOV.S @(R0,Rm),FRn LS 1 2 #2 — — — 177 FMOV.S FRm,@Rn LS 1 1 #2 — — — 178 FMOV.S FRm,@-Rn LS 1 1/1 #2 — — — 179 FMOV.S FRm,@(R0,Rn) LS 1 1 #2 — — — 180 FLDS FRm,FPUL LS 1 0 #1 — — — 181 FSTS FPUL,FRn LS 1 0 #1 — — — Rev. 3.0, 04/02, page 210 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. Single182 precision 183 floating-point instructions 184 185 InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction FABS FRn LS 1 0 #1 — — — FADD FRm,FRn FE 1 3/4 #36 — — — FCMP/EQ FRm,FRn FE 1 2/4 #36 — — — FCMP/GT FRm,FRn FE 1 2/4 #36 — — — 186 FDIV FRm,FRn FE 1 12/13 #37 F3 2 10 F1 11 1 187 FLOAT FPUL,FRn FE 1 3/4 #36 — — — 188 FMAC FR0,FRm,FRn FE 1 3/4 #36 — — — 189 FMUL FRm,FRn FE 1 3/4 #36 — — — 190 FNEG FRn LS 1 0 #1 — — — 191 FSQRT FRn FE 1 11/12 #37 F3 2 9 F1 10 1 192 FSUB FRm,FRn FE 1 3/4 #36 — — — 193 FTRC FRm,FPUL FE 1 3/4 #36 — — — 194 FMOV DRm,DRn LS 1 0 #1 — — — 195 FMOV @Rm,DRn LS 1 2 #2 — — — 196 FMOV @Rm+,DRn LS 1 1/2 #2 — — — 197 FMOV @(R0,Rm),DRn LS 1 2 #2 — — — 198 FMOV DRm,@Rn LS 1 1 #2 — — — 199 FMOV DRm,@-Rn LS 1 1/1 #2 — — — 200 FMOV DRm,@(R0,Rn) LS 1 1 #2 — — — Double201 precision 202 floating-point instructions 203 FABS DRn LS 1 0 #1 — — — FADD DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6 FCMP/EQ DRm,DRn CO 2 3/5 #40 F1 2 2 204 FCMP/GT DRm,DRn CO 2 3/5 #40 F1 2 2 205 FCNVDS DRm,FPUL FE 1 4/5 #38 F1 2 2 206 FCNVSD FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2 207 FDIV DRm,DRn FE 1 (24, 25)/ #41 26 F3 2 23 F1 22 3 F1 2 2 208 FLOAT FPUL,DRn FE 1 (3, 4)/5 #38 F1 2 2 209 FMUL DRm,DRn FE 1 (7, 8)/9 #39 F1 2 6 Rev. 3.0, 04/02, page 211 of 1064 Table 8.3 Execution Cycles (cont) Functional Category No. Double210 precision 211 floating-point instructions 212 213 FPU system 214 control 215 instructions 216 InstrucExecuLock tion Issue tion Group Rate Latency Pattern Stage Start Cycles Instruction FNEG DRn LS 1 0 FSQRT DRn FE 1 (23, 24)/ #41 25 FE 1 (7, 8)/9 #1 #39 — — — F3 2 22 F1 21 3 F1 2 2 F1 2 6 FSUB DRm,DRn FTRC DRm,FPUL FE 1 4/5 #38 F1 2 2 LDS Rm,FPUL LS 1 1 #1 — — — LDS Rm,FPSCR CO 1 4 #32 F1 3 3 LDS.L @Rm+,FPUL CO 1 1/2 #2 — — — 217 LDS.L @Rm+,FPSCR CO 1 1/4 #33 F1 3 3 218 STS FPUL,Rn LS 1 3 #1 — — — 219 STS FPSCR,Rn CO 1 3 #1 — — — 220 STS.L FPUL,@-Rn CO 1 1/1 #2 — — — 221 STS.L FPSCR,@-Rn CO 1 1/1 #2 — — — Graphics 222 acceleration 223 instructions 224 FMOV DRm,XDn LS 1 0 #1 — — — FMOV XDm,DRn LS 1 0 #1 — — — FMOV XDm,XDn LS 1 0 #1 — — — 225 FMOV @Rm,XDn LS 1 2 #2 — — — 226 FMOV @Rm+,XDn LS 1 1/2 #2 — — — 227 FMOV @(R0,Rm),XDn LS 1 2 #2 — — — 228 FMOV XDm,@Rn LS 1 1 #2 — — — 229 FMOV XDm,@-Rm LS 1 1/1 #2 — — — 230 FMOV XDm,@(R0,Rn) LS 1 1 #2 — — — 231 FIPR FVm,FVn FE 1 4/5 #42 F1 3 1 232 FRCHG FE 1 1/4 #36 — — — 233 FSCHG 234 FTRV XMTRX,FVn FE 1 1/4 #36 — — — FE 1 (5, 5, 6, 7)/8 #43 F0 2 4 F1 3 4 Notes: 1. See table 8.1 for the instruction groups. 2. Latency “L1/L2...”: Latency corresponding to a write to each register, including MACH/MACL/FPSCR Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for Rn is 2 cycles. 3. Branch latency: Interval until the branch destination instruction is fetched 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. Rev. 3.0, 04/02, page 212 of 1064 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR. 7. Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2 that for Rn, L3 that for MACH, and L4 that for MACL. 8. Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions: L1 is the latency for MACH, and L2 that for MACL. 9. Execution pattern: The instruction execution pattern number (see figure 8.2) 10. Lock/stage: Stage locked by the instruction 11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction. 12. Lock/cycles: Number of cycles locked Exceptions: 1. When a floating-point computation instruction is followed by an FMOV store, an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floatingpoint computation is decreased by 1 cycle. 2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the latency of the load is increased by 1 cycle. 3. When an LS group instruction with a latency of less than 3 cycles is followed by a double-precision floating-point instruction, FIPR, or FTRV, the latency of the first instruction is increased to 3 cycles. Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2 cycles. 4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an STS.L MACH/MACL, @-Rn instruction, the latency of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is 5 cycles. 5. In the case of consecutive executions of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency is decreased to 2 cycles. 6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn instruction, the latency of the LDS to MACH/MACL is 4 cycles. 7. When an LDS to MACH/MACL is followed by MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency of the LDS to MACH/MACL is 1 cycle. 8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that reads or writes to a floating-point register, the preceding LS group instruction[s] cannot be executed in parallel. 9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction, the latency of the single-precision FTRC instruction is 1 cycle. Rev. 3.0, 04/02, page 213 of 1064 Rev. 3.0, 04/02, page 214 of 1064 Section 9 Power-Down Modes 9.1 Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided:
Sleep mode
Deep sleep mode
Standby mode
Hardware standby mode
Module standby function (TMU, RTC, SCI/SCIF, and DMAC on-chip peripheral modules) Table 9.1 shows the conditions for entering these modes from the program execution state, the status of the CPU and peripheral modules in each mode, and the method of exiting each mode. Rev. 3.0, 04/02, page 215 of 1064 Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status PowerDown Mode Entering Conditions CPG CPU On-chip On-Chip Peripheral Memory Modules Pins External Exiting Memory Method Sleep SLEEP Operating Halted Held instruction (registers executed held) while STBY bit is 0 in STBCR Operating Held Refresh-
Interrupt ing
Reset Deep sleep SLEEP Operating Halted Held instruction (registers executed held) while STBY bit is 0 in STBCR, and DSLP bit is 1 in STBCR2 Operating (DMA halted) Held Selfrefreshing Held Standby SLEEP Halted instruction executed while STBY bit is 1 in STBCR Halted Held (registers held) Halted* Hardware standby Setting CA Halted pin to low level Halted Halted* Module standby Setting Operating Operating Held MSTP bit to 1 in STBCR Undefined Specified modules halted* Selfrefreshing
Interrupt
Reset
Interrupt
Reset
Power-on Highimpedance state Undefined Held Refresh-
Clearing ing MSTP bit to 0 reset
Reset Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). Rev. 3.0, 04/02, page 216 of 1064 9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Standby control register STBCR R/W H'00 H'FFC00004 H'1FC00004 8 Standby control register 2 STBCR2 R/W H'00 H'FFC00010 H'1FC00010 8 R/W H'00000000 H'FE0A0000 H'1E0A0000 32 H'00000000 H'FE0A0008 H'1E0A0008 32 Clock stop register CLKSTP00 Clock stop clear register 9.1.3 CLKSTPCLR00 W Pin Configuration Table 9.3 shows the pins used for power-down mode control. Table 9.3 Power-Down Mode Pins Pin Name Abbreviation I/O Function Processor status 1 STATUS1 Output Processor status 0 STATUS0 Indicate the processor’s operating status (STATUS1, STATUS0). HH: Reset HL: Sleep mode LH: Standby mode LL: Normal operation Sleep request Hardware standby request
 Input A transition to sleep mode is effected by inputting a low-level to the pin. CA Input A transition to hardware standby mode is effected by inputting a low-level to the pin. Notes: H: High level L: Low level Rev. 3.0, 04/02, page 217 of 1064 9.2 Register Descriptions 9.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the
 pin or due to watchdog timer overflow. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 STBY PHZ PPU MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7—Standby (STBY): Specifies a transition to standby mode. Bit 7: STBY Description 0 Transition to sleep mode on execution of SLEEP instruction 1 Transition to standby mode on execution of SLEEP instruction (Initial value) Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module related pins go to the high-impedance state in standby mode. For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control. Bit 6: PHZ Description 0 Peripheral module related pins are in normal state 1 Peripheral module related pins go to high-impedance state (Initial value) Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral module related pins in the input or high-impedance state. For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control. Bit 5: PPU Description 0 Peripheral module related pin pull-up resistors are on 1 Peripheral module related pin pull-up resistors are off Rev. 3.0, 04/02, page 218 of 1064 (Initial value) Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again. Bit 4: MSTP4 Description 0 DMAC operates 1 DMAC clock supply is stopped (Initial value) Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1. Bit 3: MSTP3 Description 0 SCIF operates 1 SCIF clock supply is stopped (Initial value) Bit 2—Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit channel 0 to 2 (TMU) among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2 bit is set to 1. Bit 2: MSTP2 Description 0 TMU channel 0 to 2 operates 1 TMU channel 0 to 2 clock supply is stopped (Initial value) Bit 1—Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock (RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the counters continue to operate. Bit 1: MSTP1 Description 0 RTC operates 1 RTC clock supply is stopped (Initial value) Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is stopped when the MSTP0 bit is set to 1. Rev. 3.0, 04/02, page 219 of 1064 Bit 0: MSTP0 Description 0 SCI operates 1 SCI clock supply is stopped 9.2.2 (Initial value) Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode.
Relevant Pins SCI related pins DMA related pins
SCK MD0/SCK2 TXD MD1/TXD2 MD7/
 MD8/
 DACK0 DRAK0 DACK1 DRAK1 Other Information The setting in this register is invalid when the above pins are used as port output pins. For details of pin states, see Appendix D, Pin Functions. 9.2.3 Peripheral Module Pin Pull-Up Control When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins are pulled up when in the input or high-impedance state.
Relevant Pins SCI related pins MD0/SCK2 MD1/TXD2 MD2/RXD2 MD7/
 MD8/
 SCK RXD DMA related pins TMU related pin     TCLK Rev. 3.0, 04/02, page 220 of 1064 TXD DACK0 DRAK0 DACK1 DRAK1 9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the
 pin or due to watchdog timer overflow. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 DSLP STHZ — — — — MSTP6 MSTP5 0 0 0 0 0 0 0 0 R/W R/W R R R R R/W R/W Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode Bit 7: DSLP Description 0 Transition to sleep mode or standby mode on execution of SLEEP instruction, according to setting of STBY bit in STBCR register (Initial value) 1 Transition to deep sleep mode on execution of SLEEP instruction* Note: * When the STBY bit in the STBCR register is 0 Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0 and 1 pins are set to high-impedance when in hardware standby mode. Bit 6: STHZ Description 0 Sets STATUS0, 1 pins to high-impedance when in hardware standby mode (Initial value) 1 Drives STATUS0, 1 pins to LH when in hardware standby mode Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be guaranteed if 1 is written. These bits are always read as 0. Bit 1—Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable. Bit 1: MSTP6 Description 0 SQ operating 1 Clock supply to SQ stopped (Initial value) Rev. 3.0, 04/02, page 221 of 1064 Bit 0—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller Stop Function for how to set the clock supply. Bit 0: MSTP5 Description 0 UBC operating 1 Clock supply to UBC stopped 9.2.5 (Initial value) Clock Stop Register 00 (CLKSTP00) Clock stop register 00 (CLKSTP00) is a 32-bit readable/writable register that controls the operating clock for peripheral modules. The clock supply is restarted by writing 1 to the corresponding bit in the CLKSTPCLR00 register. Writing 0 to CLKSTP00 will not change the bit value. CLKSTP00 is initialized to H'00000000 by a reset. It is not initialized in standby mode. Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — CSTP2 CSTP1 CSTP0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bits 31 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Clock Stop 2 (CSTP2): Specifies stopping of the peripheral clock supply to the PCI bus controller (PCIC). For details see section 22, PCI Controller (PCIC). Bit 2: CSTP2 Description 0 Peripheral clock is supplied to PCIC 1 Peripheral clock supply to PCIC is stopped Rev. 3.0, 04/02, page 222 of 1064 (Initial value) Bit 1—Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit (TMU) channels 3 and 4. Bit 1: CSTP1 Description 0 Peripheral clock is supplied to TMU channels 3 and 4 1 Peripheral clock supply to TMU channels 3 and 4 is stopped (Initial value) Bit 0—Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt controller (INTC). When this bit is set, PCIC and TMU channel 3 and 4 interrupts are not detected. Bit 0: CSTP0 Description 0 INTC detects PCIC and TMU channel 3 and 4 interrupts 1 INTC does not detect PCIC and TMU channel 3 and 4 interrupts 9.2.6 (Initial value) Clock Stop Clear Register 00 (CLKSTPCLR00) Clock stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that is used to clear corresponding bits in the CLKSTP00 register. Bit: 31 30 29 Initial value: 0 0 0 R/W: W W Bit: 7 Initial value: R/W: ... 11 10 9 8 ... 0 0 0 0 W ... W W W W 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W W W W W W W W ... Bits 31 to 0—Clock Stop Clear: The value of a Clock Stop Clear bit indicates whether the corresponding Clock Stop bit is to be cleared. See section 9.2.5, Clock Stop Register 00 (CLKSTP00), for the correspondence between bits and the clocks stopped. Bits 31 to 0 Description 0 Corresponding Clock Stop bit is not changed 1 Corresponding Clock Stop bit is cleared (Initial value) Rev. 3.0, 04/02, page 223 of 1064 9.3 Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The on-chip peripheral modules continue to operate, and the clock continues to be output from the CKIO pin. In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. 9.3.2 Exit from Sleep Mode Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. The code corresponding to the interrupt source is set in the INTEVT register. Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the
 pin, or a power-on or manual reset executed when the watchdog timer overflows. 9.4 Deep Sleep Mode 9.4.1 Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode. In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a transition to deep sleep mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. Rev. 3.0, 04/02, page 224 of 1064 9.4.2 Exit from Deep Sleep Mode As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. 9.5 Pin Sleep Mode 9.5.1 Transition to Pin Sleep Mode Changing the  pin to the low level causes the SH7751 Series to make a transition to sleep mode. To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is set to 0. 9.5.2 Exit from Pin Sleep Mode Setting the  pin level high causes the SH7751 Series to return to the normal state. The pin sleep mode is also canceled when the conditions specified in section 9.3.2, “Exit From Sleep Mode” are satisfied. In a power-on reset, the  pin should be fixed high. 9.6 Standby Mode 9.6.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU. Clock output from the CKIO pin is also stopped. The CPU and cache register contents are retained. Some on-chip peripheral module registers are initialized. The state of the peripheral module registers in standby mode is shown in table 9.4. Rev. 3.0, 04/02, page 225 of 1064 Table 9.4 State of Registers in Standby Mode Module Initialized Registers Registers That Retain Their Contents Interrupt controller — All registers User break controller — All registers Bus state controller — All registers On-chip oscillation circuits — All registers Timer unit TSTR register* All registers except TSTR Realtime clock — All registers Direct memory access controller — All registers Serial communication interface See Appendix A, Address List See Appendix A, Address List Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer results are not guaranteed if standby mode is entered during transfer. * Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit (TMU)). The procedure for a transition to standby mode is shown below. 1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT. Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to be used for the up-count in bits CKS2–CKS0 in the WTCSR register. 2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction. 3. When standby mode is entered and the chip’s internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. 9.6.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the
 and 
 pins. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, 1 2 IRL* , RTC, or GPIO* interrupt is detected, the WDT starts counting. After the count overflows, clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. The phase of the CKIO pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. Rev. 3.0, 04/02, page 226 of 1064 Notes: *1 Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3– IRL0 level is higher than the SR register I3–I0 mask level). *2 GPIC can be used to cancel standby mode when the RTC clock (32.768 kHz) is operating (when the GPIC level is higher than the SR register I3–I0 mask level). Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the
 pin. The
 pin should be held low until clock oscillation stabilizes. The internal clock continues to be output at the CKIO pin. 9.6.3 Clock Pause Function In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL pin. This function is used as follows. 1. Enter standby mode following the transition procedure described above. 2. When standby mode is entered and the chip’s internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. 3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the STATUS0 pin high. 4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the clock is stopped, input an NMI or IRL interrupt after applying the clock. 5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and STATUS0 pins both go low, and operation is resumed from interrupt exception handling. 9.7 Module Standby Function 9.7.1 Transition to Module Standby Function Setting the MSTP6–MSTP0 and CSTP2–CSTP0 bits in the standby control register, standby control register 2, and clock stop clear register 00 to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules. Rev. 3.0, 04/02, page 227 of 1064 Bit CSTP2 CSTP1 CSTP0 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Description 0 Peripheral clock is supplied to PCIC 1 Peripheral clock supply to PCIC is stopped 0 Peripheral clock is supplied to TMU channels 3 and 4 1 Peripheral clock supply to TMU channels 3 and 4 is stopped 0 INTC detects PCIC and TMU channel 3 and 4 interrupts 1 INTC does not detect PCIC and TMU channel 3 and 4 interrupts 0 SQ operates 1 Clock supplied to SQ is stopped 0 UBC operates 1 Clock supplied to UBC is stopped* 0 DMAC operates 1 Clock supplied to DMAC is stopped* 3 4 0 SCIF operates 1 Clock supplied to SCIF is stopped 0 TMU operates 1 Clock supplied to TMU is stopped, and register is initialized* 0 RTC operates 1 Clock supplied to RTC is stopped* 0 SCI operates 1 Clock supplied to SCI is stopped 1 2 Notes: *1 The register initialized is the same as in standby mode, but initialization is not performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)). *2 The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock (RTC)). *3 For details, see section 20.6, User Break Controller Stop Function. *4 Terminate DMA transfers prior to making the transition to module standby mode. If you make a transition to module standby mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. 9.7.2 Exit from Module Standby Function In the case of the standby control register and standby control register 2, the module standby function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00, the module standby function is exited by writing 1 to the corresponding bit in clock stop clear register 00. The module standby function is not exited by means of a power-on reset via the
 pin or a power-on reset caused by watchdog timer overflow. Rev. 3.0, 04/02, page 228 of 1064 9.8 Hardware Standby Mode 9.8.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1. Interrupts and manual resets are not available; 2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up resistance is off. 3. Even when no power is supplied to power pins other than the RTC power supply pin, the RTC continues to operate. The status of the STATUS pin is determined by the STHZ bit of STBCR2. See section D, Pin Functions, for details of output pin states. Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG status, as follows: 1. In standby mode The clock remains stopped and a transition is made to the hardware standby state. Interrupts and manual resets are disabled, but the output pins remain in the same state as in standby mode. 2. When WDT is operating when standby mode is exited by interrupt Standby mode is momentarily exited, the CPU restarts, and then a transition is made to hardware standby mode. Note that the level of the CA pin must be kept low while in hardware standby mode. 9.8.2 Exit from Hardware Standby Mode In the case of the standby control register and standby control register 2, the module standby function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00, the module standby function is exited by writing 1 to the corresponding bit in clock stop clear register 00. The module standby function is not exited by means of a power-on reset via the
 pin or a power-on reset caused by watchdog timer overflow. Rev. 3.0, 04/02, page 229 of 1064 9.8.3 Usage Notes The CA pin level must be kept high during the power-on oscillation settling period when the RTC power supply is started (figure 9.15). 9.9 STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: Sleep: Standby: Normal: HH (STATUS1 high, STATUS0 high) HL (STATUS1 high, STATUS0 low) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows: Bcyc: Bus clock cycle Pcyc: Peripheral clock cycle 9.9.1 In Reset Power-On Reset CKIO PLL stabilization time STATUS Normal Reset 0–30 Bcyc 0–5 Bcyc Figure 9.1 STATUS Output in Power-On Reset Rev. 3.0, 04/02, page 230 of 1064 Normal Manual Reset CKIO (High) * STATUS Normal Reset Normal 0–30 Bcyc ≥ 0 Bcyc Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset 9.9.2 In Exit from Standby Mode Standby  Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count STATUS Normal Standby Normal Figure 9.3 STATUS Output in Standby  Interrupt Sequence Rev. 3.0, 04/02, page 231 of 1064 Standby  Power-On Reset Oscillation stops Reset CKIO *1 STATUS Normal Standby *2 0–10 Bcyc Reset Normal 0–30 Bcyc Notes: *1 When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time. *2 Undefined Figure 9.4 STATUS Output in Standby  Power-On Reset Sequence Rev. 3.0, 04/02, page 232 of 1064 Standby  Manual Reset Oscillation stops Reset CKIO (High) * Normal STATUS Standby Undefined Reset 0–30 Bcyc 0–20 Bcyc Normal Note: * When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time. Figure 9.5 STATUS Output in Standby  Manual Reset Sequence 9.9.3 In Exit from Sleep Mode Sleep  Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.6 STATUS Output in Sleep  Interrupt Sequence Rev. 3.0, 04/02, page 233 of 1064 Sleep  Power-On Reset Reset CKIO *1 STATUS Normal Sleep *2 0–10 Bcyc Reset Normal 0–30 Bcyc Notes: *1 When sleep mode is exited by means of a power-on reset, hold oscillation stabilization time. *2 Undefined Figure 9.7 STATUS Output in Sleep  Power-On Reset Sequence Rev. 3.0, 04/02, page 234 of 1064 low for the Sleep  Manual Reset Reset CKIO (High) * Normal STATUS Reset Sleep 0–30 Bcyc Note: * Hold Normal 0–30 Bcyc low until STATUS = reset. Figure 9.8 STATUS Output in Sleep  Manual Reset Sequence Rev. 3.0, 04/02, page 235 of 1064 9.9.4 In Exit from Deep Sleep Mode Deep Sleep  Interrupt Interrupt request CKIO STATUS Sleep Normal Normal Figure 9.9 STATUS Output in Deep Sleep  Interrupt Sequence Deep Sleep  Power-On Reset Reset CKIO RESET*1 STATUS Normal Sleep *2 0–10 Bcyc Reset Normal 0–30 Bcyc Notes: *1 When deep sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time. *2 Undefined Figure 9.10 STATUS Output in Deep Sleep  Power-On Reset Sequence Rev. 3.0, 04/02, page 236 of 1064 Deep Sleep  Manual Reset Reset CKIO (High) * STATUS Normal Reset Sleep 0–30 Bcyc Note: * Hold Normal 0–30 Bcyc low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep  Manual Reset Sequence Rev. 3.0, 04/02, page 237 of 1064 9.9.5 Hardware Standby Mode Timing Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the
 pin level low, the clock starts when the CA pin level is switched to high. CKIO CA STATUS Normal*1 Standby*2 0–10 Bcyc Undefined Reset 0–10 Bcyc Waiting for end of bus cycle Notes: *1 Same at sleep and reset *2 High impedance when STBCR2. STHZ = 0 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) Rev. 3.0, 04/02, page 238 of 1064 Interrupt request WDT overflow CKIO CA (High) STATUS Standby Normal Standby* 0–10 Bcyc WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) VDDQ* VDD min VDD CA Min 0s Min 0s Max 50 µs Note: * VDDQ, VDD-CPG Figure 9.14 Timing When Power Other than VDD-RTC is Off Rev. 3.0, 04/02, page 239 of 1064 VDD-RTC Power-on oscillation settling time CA VDD, VDDQ* Min 0s Note: * VDD, VDD-PLL1/2, VDDQ, VDD-CPG Figure 9.15 Timing When VDD-RTC Power is Off  On Rev. 3.0, 04/02, page 240 of 1064 Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer. 10.1.1 Features The CPG has the following features:
Three clocks The CPG can generate independently the CPU clock (I) used by the CPU, FPU, caches, and TLB, the peripheral module clock (P) used by the peripheral modules, and the bus clock (CKIO) used by the external bus interface.
Six clock modes Any of six clock operating modes can be selected, with different combinations of CPU clock, bus clock, and peripheral module clock division ratios after a power-on reset.
Frequency change function PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock, bus clock, and peripheral module clock frequencies to be changed independently. Frequency changes are performed by software in accordance with the settings in the frequency control register (FRQCR).
PLL on/off control Power consumption can be reduced by stopping the PLL circuits during low-frequency operation.
Power-down mode control It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules with the module standby function. Rev. 3.0, 04/02, page 241 of 1064 The WDT has the following features
Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed.
Can be switched between watchdog timer mode and interval timer mode
Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow. Power-on reset or manual reset can be selected.
Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow.
Selection of eight counter input clocks Any of eight clocks can be selected, scaled from the 1 clock of frequency divider 2 shown in figure 10.1. The CPG is described in sections 10.2 to 10.6, and the WDT in sections 10.7 to 10.9. Rev. 3.0, 04/02, page 242 of 1064 10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figures 10.1(1) and 10.1(2) show a block diagram of the CPG in the SH7751 and SH7751R. Oscillator circuit PLL circuit 1 ×6 XTAL Frequency divider 2 ×1 × 1/2 × 1/3 × 1/4 × 1/6 × 1/8 CPU clock (Iø) cycle Icyc Frequency divider 1 Crystal oscillator Peripheral module clock (Pø) cycle Pcyc × 1/2 EXTAL MD8 Bus clock (Bø) cycle Bcyc PLL circuit 2 ×1 CKIO CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Internal bus FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Figure 10.1(1) Block Diagram of CPG (SH7751) Rev. 3.0, 04/02, page 243 of 1064 Oscillator circuit Frequency divider 2 PLL circuit 1 ×6 × 12 XTAL ×1 × 1/2 × 1/3 × 1/4 × 1/6 × 1/8 CPU clock (Iø) cycle Icyc Crystal oscillator Peripheral module clock (Pø) cycle Pcyc EXTAL MD8 Bus clock (Bø) cycle Bcyc PLL circuit 2 ×1 CKIO CPG control unit MD2 MD1 MD0 Clock frequency control circuit Standby control circuit FRQCR STBCR STBCR2 Bus interface Internal bus FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby control register 2 Figure 10.1(2) Block Diagram of CPG (SH7751R) Rev. 3.0, 04/02, page 244 of 1064 The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6 or 12. Starting and stopping is controlled by a frequency control register setting. Control is performed so that the internal clock rising edge phase matches the input clock rising edge phase. PLL Circuit 2: PLL circuit 2, according to the output clock feedback from the CKIO pin, coordinates the phases of the bus clock and the CKIO pin output clock. Starting and stopping is controlled by a frequency control register setting. Crystal Oscillator: This is the oscillator circuit used when a crystal resonator is connected to the XTAL and EXTAL pins. Use of the crystal oscillator can be selected with the MD8 pin. Frequency Divider 1 (SH7751R only): Frequency divider 1 has a function for adjusting the clock waveform duty to 50% by halving the input clock frequency when clock input from the EXTAL pin is supplied internally without using PLL circuit 1. Frequency Divider 2: Frequency divider 2 generates the CPU clock (I), bus clock (B), and peripheral module clock (P). The division ratio is set in the frequency control register. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency by means of the MD pins and frequency control register. Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched and in sleep and standby modes. Frequency Control Register (FRQCR): The frequency control register contains control bits for clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Standby Control Register (STBCR): The standby control register contains power save mode control bits. For further information on the standby control register, see section 9, Power-Down Modes. Standby Control Register 2 (STBCR2): Standby control register 2 contains a power save mode control bit. For further information on standby control register 2, see section 9, Power-Down Modes. Rev. 3.0, 04/02, page 245 of 1064 10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation I/O Function Mode control pins MD0 Input Set clock operating mode XTAL Output Connects crystal resonator EXTAL Input Connects crystal resonator, or used as external clock input pin MD8 Input Selects use/non-use of crystal resonator MD1 MD2 Crystal I/O pins (clock input pins) When MD8 = 0, external clock is input from EXTAL When MD8 = 1, crystal resonator is connected directly to EXTAL and XTAL Clock output pin CKIO Output CKIO enable pin CKE Output Used as external clock output pin Level can also be fixed 0 when CKIO output clock is unstable and in case of synchronous DRAM self-refreshing* Note: * Set to 1 in a power-on reset. For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous DRAM Interface. 10.2.3 CPG Register Configuration Table 10.2 shows the CPG register configuration. Table 10.2 CPG Register Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Frequency control register FRQCR R/W Undefined H'FFC00000 H'1FC00000 16 Rev. 3.0, 04/02, page 246 of 1064 10.3 Clock Operating Modes Tables 10.3(1) and 10.3(2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3(1) Clock Operating Modes (SH7751) External Pin Combination Clock Operating Mode MD2 MD1 0 0 0 1 2 1 3 4 1 0 5 Frequency (vs. Input Clock) MD0 1/2 Frequency Divider PLL2 CPU Clock Bus Clock Peripheral Module Clock PLL1 FRQCR Initial Value 0 Off On On 6 3/2 3/2 H'0E1A 1 0 Off On On 6 1 1 H'0E23 On On On 3 1 1/2 H'0E13 1 Off On On 6 2 1 H'0E13 0 On On On 3 3/2 3/4 H'0E0A 1 Off On On 6 3 3/2 H'0E0A Notes: 1. The clock operating mode is the only factor to determine whether to turn the 1/2 frequency divider on or off. 2. For the frequency range of the input clock, see the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 23.3.1, Clock and Control Signal Timing. Table 10.3(2) Clock Operating Modes (SH7751R) External Pin Combination Frequency (vs. Input Clock) Clock Operating Mode MD2 MD1 MD0 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 0 0 0 On (
12) On 12 3 3 H'0E1A 1 On (
12) On 12 3/2 3/2 H'0E2C 0 On (
6) On 6 2 1 H'0E13 1 2 1 1 On (
12) On 12 4 2 H'0E13 0 0 On (
6) On 6 3 3/2 H'0E0A 1 On (
12) On 1 0 OFF (
6) OFF 3 4 1 5 6 12 6 3 H'0E0A 1 1/2 1/2 H'0808 Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode. 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (fEX) and the CKIO clock output (fOP) in section 23.3.1, Clock and Control Signal Timing. Rev. 3.0, 04/02, page 247 of 1064 Table 10.4 FRQCR Settings and Internal Clock Frequencies Frequency Division Ratio FRQCR (Lower 9 Bits) CPU Clock Bus Clock Peripheral Module Clock 9'h000 1 1 1/2 9'h002 1/4 9'h004 1/8 1/2 9'h008 9'h00a 1/4 9'h00c 1/8 9'h011 1/3 9'h013 1/3 1/6 9'h01a 1/4 9'h01c 1/4 1/8 9'h023 9'h02c 9'h048 1/2 1/2 1/6 1/6 1/8 1/8 1/2 1/2 9'h04a 1/4 9'h04c 1/8 9'h05a 1/4 1/4 9'h063 1/6 1/6 9'h06c 1/8 1/8 1/3 1/3 9'h05c 9'h091 1/8 1/3 9'h093 1/6 9'h0a3 9'h0da 1/4 1/6 1/6 1/4 1/4 9'h0dc 1/8 9'h0ec 1/8 9'h123 1/6 1/6 1/6 9'h16c 1/8 1/8 1/8 Note: Do not set values other than those shown in the table for the lower 9 bits of FRQCR. Rev. 3.0, 04/02, page 248 of 1064 10.4 CPG Register Description 10.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be used on FRQCR. FRQCR is initialized only by a power-on reset via the
 pin. The initial value of each bit is determined by the clock operating mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 — — — — CKOEN 0 0 0 0 1 1 1 — R/W R/W R/W R R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W PLL1EN PLL2EN IFC2 Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0. Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the highimpedance state, operation continues at the operating frequency before this state was entered. When the CKIO pin becomes high-impedance, it is pulled up. Bit 11: CKOEN Description 0 CKIO pin goes to high-impedance state (pulled up*) 1 Clock is output from CKIO pin (Initial value) Note: * It is not pulled up in hardware standby mode. Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off. Bit 10: PLL1EN Description 0 PLL circuit 1 is not used 1 PLL circuit 1 is used (Initial value) Rev. 3.0, 04/02, page 249 of 1064 Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off. Bit 9: PLL2EN Description 0 PLL circuit 2 is not used 1 PLL circuit 2 is used (Initial value) Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 Bit 7: IFC1 Bit 6: IFC0 Description 0 0 0
1 1
1/2 0
1/3 1
1/4 0
1/6 1
1/8 1 1 0 Other than the above Setting prohibited (Do not set) Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 5: BFC2 Bit 4: BFC1 Bit 3: BFC0 Description 0 0 0
1 1
1/2 0
1/3 1
1/4 0
1/6 1
1/8 1 1 0 Other than the above Setting prohibited (Do not set) Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Rev. 3.0, 04/02, page 250 of 1064 Bit 2: PFC2 Bit 1: PFC1 Bit 0: PFC0 Description 0 0 0
1/2 1
1/3 1 1 0 0
1/4 1
1/6 0
1/8 Other than the above 10.5 Setting prohibited (Do not set) Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below. 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off) When PLL circuit 1 is changed from the stopped to started state, a PLL circuit 1 oscillation stabilization time is required. The oscillation stabilization time count is performed by the on-chip WDT. 1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT. The following settings are necessary: WTCSR register TME bit = 0: WDT stopped WTCSR register CKS2–CKS0 bits: WDT count clock division ratio WTCNT counter: Initial counter value 2. Set the PLL1EN bit to 1. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On) When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2. Set the PLL1EN bit to 1. Rev. 3.0, 04/02, page 251 of 1064 3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its upcount from the value set in step 1 above. During this time, also, the internal clock is stopped and an unstable clock is output to the CKIO pin. 5. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2. Set the BFC2–BFC0 bits to the desired value. 3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, clock supply begins within the chip and the processor resumes operation. The WDT stops after overflowing. 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off) If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not performed. 1. Set the BFC2–BFC0 bits to the desired value. 2. The set clock is switched to immediately. 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is not performed. 1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value. 2. The set clock is switched to immediately. Rev. 3.0, 04/02, page 252 of 1064 10.6 Output Clock Control The CKIO pin can be switched between clock output and a high-impedance state by means of the CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is pulled up. 10.7 Overview of Watchdog Timer 10.7.1 Block Diagram Figure 10.2 shows a block diagram of the WDT. WDT Standby release Internal reset request Standby mode Standby control Frequency divider Reset control Clock selection Interrupt request Interrupt control Frequency divider 2 ×1 clock Clock selector Overflow Clock WTCSR WTCNT Bus interface WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 10.2 Block Diagram of WDT Rev. 3.0, 04/02, page 253 of 1064 10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Watchdog timer counter WTCNT R/W* H'00 H'FFC00008 H'1FC00008 R: 8, W: 16* Watchdog timer control/status register WTCSR R/W* H'00 H'FFC0000C H'1FC0000C R: 8, W: 16* Note: * Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte access when reading. 10.8 WDT Register Descriptions 10.8.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that counts up on the selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the
 pin. To write to the WTCNT counter, use a word-size access with the upper byte set to H'5A. To read WTCNT, use a byte-size access. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Rev. 3.0, 04/02, page 254 of 1064 10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the
 pin. It retains its value in an internal reset due to WDT overflow. When used to count the clock stabilization time when exiting standby mode, WTCSR retains its value after the counter overflows. To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read WTCSR, use a byte-size access. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TME WT/
 RSTS WOVF IOVF CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7—Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency. Bit 7: TME Description 0 Up-count stopped, WTCNT value retained 1 Up-count started (Initial value) Bit 6—Timer Mode Select (WT/): Specifies whether the WDT is used as a watchdog timer or interval timer. Bit 6: WT/
 Description 0 Interval timer mode 1 Watchdog timer mode (Initial value) Note: The up-count may not be performed correctly if WT/
 is modified while the WDT is running. Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. Bit 5: RSTS Description 0 Power-on reset 1 Manual reset (Initial value) Rev. 3.0, 04/02, page 255 of 1064 Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description 0 No overflow 1 WTCNT has overflowed in watchdog timer mode (Initial value) Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. Bit 3: IOVF Description 0 No overflow 1 WTCNT has overflowed in interval timer mode (Initial value) Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1 off, and PLL circuit 1 on (6). Note: * When PLL1 is switched on or off, the clock following the switch is used. Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Overflow Period 0 0 0 1/32 41 s 1 1/64 1 1 0 1 (Initial value) 82 s 0 1/128 164 s 1 1/256 328 s 0 1/512 656 s 1 1/1024 1.31 ms 0 1/2048 2.62 ms 1 1/4096 5.25 ms Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the WDT is running. Always stop the WDT before modifying these bits. Rev. 3.0, 04/02, page 256 of 1064 10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction. They cannot be written to with a byte or longword transfer instruction. When writing to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the lower byte containing the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. The write formats are shown in figure 10.3. WTCNT write 15 Address: H'FFC00008 (H'1FC00008) 8 7 H'5A 0 Write data WTCSR write 15 Address: H'FFC0000C (H'1FC0000C) 8 7 H'A5 0 Write data Figure 10.3 Writing to WTCNT and WTCSR Rev. 3.0, 04/02, page 257 of 1064 10.9 Using the WDT 10.9.1 Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the
 pin should be held low until the clock stabilizes.) 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. 3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction. 4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 5. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 6. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on the clock ratio. 10.9.2 Frequency Changing Procedure The WDT is used in a frequency change using the PLL. It is not used when the frequency is changed simply by making a frequency divider switch. 1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the initial value in the WTCNT counter. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. 3. When the frequency control register (FRQCR) is modified, the clock stops. The WDT starts counting. 4. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 5. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on the clock ratio. 6. When re-setting WTCNT immediately after modifying the frequency control register (FRQCR), first read the counter and confirm that its value is as described in step 5 above. Rev. 3.0, 04/02, page 258 of 1064 10.9.3 Using Watchdog Timer Mode 1. Set the WT/ bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode. 3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does not overflow. 4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and generates a reset of the type specified by the RSTS bit. The counter then continues counting. 10.9.4 Using Interval Timer Mode When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. Clear the WT/ bit in the WTCSR register to 0, select the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter. 2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and sends an interval timer interrupt request to INTC. The counter continues counting. Rev. 3.0, 04/02, page 259 of 1064 10.10 Notes on Board Design When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins. CL1 Avoid crossing signal lines CL2 R EXTAL Recommended values CL1 = CL2 = 0–33 pF R = 0Ω XTAL SH7751 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin. Rev. 3.0, 04/02, page 260 of 1064 When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB, and decoupling capacitors CPB and CB, close to the pins. RCB1 VDD-PLL1 Recommended values RCB1 = RCB2 = 10 Ω CPB1 = CPB2 = 10 µF RB = 10 Ω CB = 10 µF CPB1 VSS-PLL1 RCB2 VDD-PLL2 SH7751 Series 1.8 V CPB2 VSS-PLL2 RB VDD-CPG CB 3.3 V VSS-CPG Figure 10.5 Points for Attention when Using PLL Oscillator Circuit Rev. 3.0, 04/02, page 261 of 1064 Rev. 3.0, 04/02, page 262 of 1064 Section 11 Realtime Clock (RTC) 11.1 Overview The SH7751 Series includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features.
Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
1 to 64 Hz timer (binary display) The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider
Start/stop function
30-second adjustment function
Alarm interrupts Comparison with second, minute, hour, day-of-week, day, month, or year (SH7751R only) can be selected as the alarm interrupt condition
Periodic interrupts An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds can be selected
Carry interrupt Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read
Automatic leap year adjustment Rev. 3.0, 04/02, page 263 of 1064 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. ATI PRI CUI RTCCLK RESET, STBY, etc 16.384 kHz Prescaler RTC crystal oscillator 32.768 kHz RTC operation control unit 128 Hz RCR1 RCR2 * Counter unit RCR3 Interrupt control unit R64CNT RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR RYRAR * To registers Bus interface Internal peripheral module bus Note: * SH7751R only Figure 11.1 Block Diagram of RTC Rev. 3.0, 04/02, page 264 of 1064 11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation I/O Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Clock input/clock output TCLK I/O External clock input pin/input capture control input pin/RTC output pin (shared with TMU) Dedicated RTC power supply VDD (RTC) — RTC oscillator power supply pin* Dedicated RTC GND pin VSS (RTC) — RTC oscillator GND pin* Note: * Power must be supplied to the RTC power supply pins even when the RTC is not used. 11.1.4 Register Configuration Table 11.2 summarizes the RTC registers. Table 11.2 RTC Registers Initialization Abbreviation R/W PowerOn Reset 64 Hz counter R64CNT R Counts Counts Counts Undefined H'FFC80000 H'1FC80000 8 Second counter RSECCNT R/W Counts Counts Counts Undefined H'FFC80004 H'1FC80004 8 Minute counter RMINCNT R/W Counts Counts Counts Undefined H'FFC80008 H'1FC80008 8 Hour counter RHRCNT R/W Counts Counts Counts Undefined H'FFC8000C H'1FC8000C 8 Day-ofweek counter RWKCNT R/W Counts Counts Counts Undefined H'FFC80010 H'1FC80010 8 Day counter RDAYCNT R/W Counts Counts Counts Undefined H'FFC80014 H'1FC80014 8 Name Manual Standby Initial Reset Mode Value Area 7 P4 Address Address Access Size Rev. 3.0, 04/02, page 265 of 1064 Table 11.2 RTC Registers (cont) Initialization Power-On Manual Reset Reset Standby Initial Mode Value Area 7 P4 Address Address Month RMONCNT R/W counter Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 Year RYRCNT counter R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16 Second RSECAR alarm register R/W Initialized* Held 1 Held Undefined* H'FFC80020 H'1FC80020 8 Minute RMINAR alarm register R/W Initialized* Held 1 Held Undefined* H'FFC80024 H'1FC80024 8 Hour RHRAR alarm register R/W Initialized* Held 1 Held Undefined* H'FFC80028 H'1FC80028 8 Day-of- RWKAR week alarm register R/W Initialized* Held 1 Held Undefined* H'FFC8002C H'1FC8002C 8 Day RDAYAR alarm register R/W Initialized* Held 1 Held Undefined* H'FFC80030 H'1FC80030 8 Month RMONAR alarm register R/W Initialized* Held 1 Held Undefined* H'FFC80034 H'1FC80034 8 RTC RCR1 control register 1 R/W Initialized Initialized Held RTC RCR2 control register 2 R/W RTC RCR3 control register 5 3* Year RYRAR alarm 5 register* Name Abbreviation R/W Notes: *1 *2 *3 *4 *5 Access Size 1 1 1 1 1 1 H'00* 3 H'FFC80038 H'1FC80038 8 Initialized Initialized* Held H'09* 4 H'FFC8003C H'1FC8003C 8 R/W Initialized Held Held H'00 H'FFC80050 H'1FC80050 8 R/W Held Held Undefined H'FFC80054 H'1FC80054 16 2 Held The ENB bit in each register is initialized. Bits other than the RTCEN bit and START bit are initialized. The value of the CF bit and AF bit is undefined. The value of the PEF bit is undefined. SH7751R only Rev. 3.0, 04/02, page 266 of 1064 11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be read again after first writing 0 to the CF bit in RCR1 to clear it. When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency divider is initialized and R64CNT is initialized to H'00. R64CNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0 and cannot be modified. Bit: 7 6 5 4 3 2 1 0 — 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz Initial value: 0 R/W: R 11.2.2 Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R Second Counter (RSECCNT) RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R69CNT.1Hz bit from 0 to 1) generated once per second by the 64 Hz counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RSECCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 6 — Initial value: 0 R/W: R 5 4 3 10-second units 2 1 0 1-second units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 267 of 1064 11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMINCNT is not initialized by a power-on or manual reset, or in standby mode. Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: 7 6 — Initial value: 0 R/W: R 11.2.4 5 4 3 10-minute units 2 1 0 1-minute units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W Hour Counter (RHRCNT) RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter. The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RHRCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 6 — — Initial value: 0 0 R/W: R R Rev. 3.0, 04/02, page 268 of 1064 5 4 3 10-hour units 2 1 0 1-hour units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W 11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RWKCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 6 5 4 3 2 1 — — — — — Day-of-week code Initial value: 0 0 0 0 0 Undefined Undefined Undefined R/W: R R R R R R/W 0 R/W R/W Day-of-week code 0 1 2 3 4 5 6 Day of week Sun Mon Tue Wed Thu Fri Sat Rev. 3.0, 04/02, page 269 of 1064 11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RDAYCNT is not initialized by a power-on or manual reset, or in standby mode. The setting range for RDAYCNT depends on the month and whether the year is a leap year, so care is required when making the setting. Taking the year counter (RYRCNT) value as the year, leap year calculation is performed according to whether or not the value is divisible by 400, 100, and 4. Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: 7 6 5 — — 10-day units Initial value: 0 0 R/W: R R 11.2.7 4 3 2 1 0 1-day units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Month Counter (RMONCNT) RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded month value in the RTC. It counts on the carry generated once per month by the day counter. The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RMONCNT is not initialized by a power-on or manual reset, or in standby mode. Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev. 3.0, 04/02, page 270 of 1064 Bit: 7 6 5 4 — — — 10-month unit Initial value: 0 0 0 Undefined Undefined Undefined Undefined Undefined R/W: R R R 11.2.8 R/W 3 2 1 0 1-month units R/W R/W R/W R/W Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter. The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag. RYRCNT is not initialized by a power-on or manual reset, or in standby mode. Bit: 15 14 13 12 11 1000-year units 10 9 8 100-year units Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: Bit: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 10-year units 1-year units Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 271 of 1064 11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 6 ENB Initial value: R/W: 0 R/W 5 4 3 2 10-second units 1 0 1-second units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W 11.2.10 Minute Alarm Register (RMINAR) RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCDcoded minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared with the RMINCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not initialized by a power-on or manual reset, or in standby mode. Bit: 7 6 ENB Initial value: R/W: 0 R/W 5 4 3 10-minute units 2 1 0 1-minute units Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Rev. 3.0, 04/02, page 272 of 1064 R/W R/W R/W R/W R/W R/W 11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: Initial value: R/W: 7 6 ENB — 0 0 R/W R 5 4 3 10-hour units 2 1 0 1-hour units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W 11.2.12 Day-of-Week Alarm Register (RWKAR) RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is compared with the RWKCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev. 3.0, 04/02, page 273 of 1064 Bit: 7 6 5 4 3 ENB — — — — Day-of-week code Undefined Undefined Undefined Initial value: R/W: 0 0 0 0 0 R/W R R R R 2 1 R/W 0 R/W R/W Day-of-week code 0 1 2 3 4 5 6 Day of week Sun Mon Tue Wed Thu Fri Sat 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCDcoded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other value is set. The setting range for RDAYAR depends on the month and whether the year is a leap year, so care is required when making the setting. The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not initialized by a power-on or manual reset, or in standby mode. Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0. Bit: Initial value: R/W: 7 6 5 ENB — 10-day units 0 0 R/W R Rev. 3.0, 04/02, page 274 of 1064 4 3 2 1 0 1-day units Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W 11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCDcoded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match. The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are not initialized by a power-on or manual reset, or in standby mode. Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: Initial value: R/W: 7 6 5 4 ENB — — 10-month unit Undefined Undefined Undefined Undefined Undefined 0 0 0 R/W R R R/W 3 2 1 0 1-month units R/W R/W R/W R/W 11.2.15 RTC Control Register 1 (RCR1) RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to enable or disable interrupts for these flags. The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other than CIE and AIE is undefined. In standby mode RCR1 is not initialized, and retains its current value. Bit: 7 6 5 4 3 CF — — CIE AIE 0 0 R/W R/W Initial value: Undefined Undefined Undefined R/W: R/W R R 2 1 0 — — AF Undefined Undefined Undefined R R R/W Rev. 3.0, 04/02, page 275 of 1064 Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again. Bit 7: CF Description 0 No second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Clearing condition] When 0 is written to CF 1 Second counter carry, or 64 Hz counter carry when 64 Hz counter is read [Setting conditions]
Generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read
When 1 is written to CF Bit 4—Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the carry flag (CF) is set to 1. Bit 4: CIE Description 0 Carry interrupt is not generated when CF flag is set to 1 1 Carry interrupt is generated when CF flag is set to 1 (Initial value) Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the alarm flag (AF) is set to 1. Bit 3: AIE Description 0 Alarm interrupt is not generated when AF flag is set to 1 1 Alarm interrupt is generated when AF flag is set to 1 Rev. 3.0, 04/02, page 276 of 1064 (Initial value) Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description 0 Alarm registers and counter values do not match (Initial value) [Clearing condition] When 0 is written to AF 1 Alarm registers and counter values match* [Setting condition] When alarm registers in which the ENB bit is set to 1 and counter values match* Note: * Writing 1 does not change the value. Bits 6, 5, 2, and 1—Reserved. The initial value of these bits is undefined. A write to these bits is invalid, but the write value should always be 0. 11.2.16 RTC Control Register 2 (RCR2) RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second adjustment, and frequency divider RESET and RTC count control. RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value. Bit: 7 6 5 4 3 2 1 0 PEF PES2 PES1 PES0 RTCEN ADJ RESET START 0 0 0 1 0 0 1 R/W R/W R/W R/W R/W R/W R/W Initial value: Undefined R/W: R/W Rev. 3.0, 04/02, page 277 of 1064 Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description 0 Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF 1 Interrupt is generated at interval specified by bits PES2–PES0 [Setting conditions]
Generation of interrupt at interval specified by bits PES2–PES0
When 1 is written to PEF Bits 6 to 4—Periodic Interrupt Enable (PES2–PES0): These bits specify the period for periodic interrupts. Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description 0 0 0 No periodic interrupt generation 1 Periodic interrupt generated at 1/256-second intervals 0 Periodic interrupt generated at 1/64-second intervals 1 Periodic interrupt generated at 1/16-second intervals 0 Periodic interrupt generated at 1/4-second intervals 1 Periodic interrupt generated at 1/2-second intervals 0 Periodic interrupt generated at 1-second intervals 1 Periodic interrupt generated at 2-second intervals 1 1 0 1 (Initial value) Bit 3—Oscillator Enable (RTCEN): Controls the operation of the RTC’s crystal oscillator. Bit 3: RTCEN Description 0 RTC crystal oscillator is halted 1 RTC crystal oscillator is operated Rev. 3.0, 04/02, page 278 of 1064 (Initial value) Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time. This bit always returns 0 if read. Bit 2: ADJ Description 0 Normal clock operation 1 30-second adjustment performed (Initial value) Bit 1—Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit. When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT) are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0). Bit 1: RESET Description 0 Normal clock operation 1 Frequency divider circuits are reset (Initial value) Bit 0—Start Bit (START): Stops and restarts counter (clock) operation. Bit 0: START Description 0 Second, minute, hour, day, day-of-week, month, and year counters are stopped* 1 Second, minute, hour, day, day-of-week, month, and year counters operate normally* (Initial value) Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit. Rev. 3.0, 04/02, page 279 of 1064 11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC’s BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value. Comparison between the counter and the alarm register only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm flag of RCR1 is only set to 1 when the respective values all match. The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a value beyond this range is set here. RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or manual reset, or by the device entering standby mode. Bits 6 to 0 of RCR3 are always read as 0. A write to these bits is invalid. If a value is written to these bits, it should always be 0. RCR3 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 YENB — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R 15 14 13 12 11 10 9 8 RYRAR Bit: 1000 years 100 years Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: Bit: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 10 years 1 year Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W Rev. 3.0, 04/02, page 280 of 1064 R/W R/W R/W R/W R/W R/W 11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Stop clock Reset frequency divider Set second/minute/hour/day/ day-of-week/month/year Start clock operation Set RCR2.RESET to 1 Clear RCR2.START to 0 In any order Set RCR2.START to 1 (a) Setting time after stopping clock Clear carry flag Yes Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Write to counter register Set RYRCNT first and RSECCNT last Carry flag = 1? Read RCR1 register and check CF bit No (b) Setting time while clock is running Figure 11.2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in figure 11.2 (a). The programming for this method is simple, and it is useful for setting all the counters, from second to year. Rev. 3.0, 04/02, page 281 of 1064 The procedure for setting the time while the clock is running is shown in figure 11.2 (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data. The carry flag should therefore be used to check the write status. If the carry flag (RCR1.CF) is set to 1, the write must be repeated. The interrupt function can also be used to determine the carry flag status. 11.3.2 Time Reading Procedures Figure 11.3 shows examples of the time reading procedures. Rev. 3.0, 04/02, page 282 of 1064 Disable carry interrupts Clear carry flag Clear RCR1.CIE to 0 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Yes Carry flag = 1? Read RCR1 register and check CF bit No (a) Reading time without using interrupts Clear carry flag Enable carry interrupts Clear carry flag Set RCR1.CIE to 1 Clear RCR1.CF to 0 (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Yes Interrupt generated? No Disable carry interrupts Clear RCR1.CIE to 0 (b) Reading time using interrupts Figure 11.3 Examples of Time Reading Procedures If a carry occurs while the time is being read, the correct time will not be obtained and the read must be repeated. The procedure for reading the time without using interrupts is shown in figure 11.3 (a), and the procedure using carry interrupts in figure 11.3 (b). The method without using interrupts is normally used to keep the program simple. Rev. 3.0, 04/02, page 283 of 1064 11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Clear alarm flag Enable alarm interrupts Be sure to reset the flag as it may have been set during alarm time setting Set RCR1.AIE to 1 Monitor alarm time (Wait for interrupt or check alarm flag) Figure 11.4 Example of Use of Alarm Function An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year (SH7751R only) value, or a combination of these. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting. When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be detected. The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by writing 0 during this period, it will therefore be set again immediately afterward. This needs to be taken into consideration when writing the program. Rev. 3.0, 04/02, page 284 of 1064 11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2– PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1. A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the carry interrupt enable bit (CIE) is also set to 1. 11.5 Usage Notes 11.5.1 Register Initialization After powering on and making the RCR1 register settings, reset the frequency divider (by setting RCR2.RESET to 1) and make initial settings for all the other registers. 11.5.2 Carry Flag and Interrupt Flag in Standby Mode When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode from standby mode by a reset or interrupt, the flag may not be set to 1. After exiting standby mode, check the counters to judge the flag states if necessary. 11.5.3 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the RTC crystal oscillator circuit in figure 11.5. Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) fosc Cin Cout 32.768 kHz 10–22 pF 10–22 pF Rev. 3.0, 04/02, page 285 of 1064 SH7751 Series VDD-RTC VSS-RTC Rf RD XTAL2 EXTAL2 XTAL Noise filter CRTC Cin Cout RRTC 3.3 V Notes: 1. Select either the Cin or Cout side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value Rf (typ. value) = 10 MΩ, RD (typ. value) = 400 kΩ 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a solidearth board. 4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) 6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. 7. Insert a noise filter in the RTC power supply. Figure 11.5 Example of Crystal Oscillator Circuit Connection Rev. 3.0, 04/02, page 286 of 1064 Section 12 Timer Unit (TMU) 12.1 Overview The SH7751 Series includes an on-chip 32-bit timer unit (TMU) comprising five 32-bit timer channels (channels 0 to 4). 12.1.1 Features The TMU has the following features.
Auto-reload type 32-bit down-counter provided for each channel
Input capture function provided in channel 2
Selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used
32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel
Selection of seven counter input clocks for channels 0 to 2 External clock (TCLK), on-chip RTC output clock, five internal clocks (P/4, P/16, P/64, P/256, P/1024) (P is the peripheral module clock)
Selection of five internal clocks for channels 3 and 4
Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock is selected as the counter input clock; that is, timer operation continues even when the clock has been stopped for the TMU. Timer count operations using an external or internal clock are only possible when a clock is supplied to the timer unit.
Two interrupt sources One underflow source (channels 0 to 4) and one input capture source (channel 2)
DMAC data transfer request capability On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is generated. Rev. 3.0, 04/02, page 287 of 1064 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. TICPI2 RESET, STBY, TUNI0,1 PCLK/4, 16, 64* etc. TMU operation control unit TUNI2 TCLK RTCCLK TUNI3, TUNI4 TCLK control unit Prescaler To chan- To channels nels 0 to 2 0 to 4 TOCR TSTR TSTR2 Ch 0,1 Ch 2 Counter unit TCR Interrupt control unit TCOR Ch 3,4 Interrupt control unit Counter unit TCNT TCR2 TCOR2 TCNT2 Counter unit TCPR2 TCR Interrupt control unit TCOR TCNT Bus interface Internal peripheral module bus Note: * Signals with 1/4, 1/16, and 1/64 the Pφ frequency, supplied to the on-chip peripheral functions. Figure 12.1 Block Diagram of TMU 12.1.3 Pin Configuration Table 12.1 shows the TMU pins. Table 12.1 TMU Pins Pin Name Abbreviation I/O Function Clock input/clock output TCLK I/O External clock input pin/input capture control input pin/RTC output pin (shared with RTC) Rev. 3.0, 04/02, page 288 of 1064 12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Channel Name PowerStandAbbreOn Manual by Area 7 viation R/W Reset Reset Mode Initial Value P4 Address Address Access Size Com- Timer mon output control register TOCR R/W IniIniHeld tialized tialized H'00 H’FFD80000 H'1FD80000 8 Timer start register TSTR R/W IniIniIniH'00 1 tialized tialized tialized* H’FFD80004 H'1FD80004 8 Timer TSTR2 R/W IniHeld start tialized register 2 0 Held H'00 Timer TCOR0 R/W IniIniHeld constant tialized tialized register 0 H'FFFFFFFF H’FFD80008 H'1FD80008 32 2 1 Timer TCNT0 R/W IniIniHeld* counter 0 tialized tialized H'FFFFFFFF H’FFD8000C H'1FD8000C 32 Timer TCR0 control register 0 H'0000 R/W IniIniHeld tialized tialized Timer TCOR1 R/W IniIniHeld constant tialized tialized register 1 H’FFD80010 H'1FD80010 16 H'FFFFFFFF H’FFD80014 H'1FD80014 32 2 2 H'FE100004 H'1E100004 8 Timer TCNT1 R/W IniIniHeld* counter 1 tialized tialized H'FFFFFFFF H’FFD80018 H'1FD80018 32 Timer TCR1 control register 1 H'0000 R/W IniIniHeld tialized tialized Timer TCOR2 R/W IniIniHeld constant tialized tialized register 2 H’FFD8001C H'1FD8001C 16 H'FFFFFFFF H’FFD80020 H'1FD80020 32 2 Timer TCNT2 R/W IniIniHeld* counter 2 tialized tialized H'FFFFFFFF H’FFD80024 H'1FD80024 32 Timer TCR2 control register 2 H'0000 H’FFD80028 H'1FD80028 16 Undefined H’FFD8002C H'1FD8002C 32 Input capture register R/W IniIniHeld tialized tialized TCPR2 R Held Held Held Rev. 3.0, 04/02, page 289 of 1064 Table 12.2 TMU Registers (cont) Initialization Channel Name 3 4 PowerStandAbbreOn Manual by Area 7 viation R/W Reset Reset Mode Initial Value P4 Address Address Access Size Timer TCOR3 R/W IniHeld constant tialized register 3 Held H'FFFFFFFF H'FE100008 H'1E100008 32 Timer TCNT3 R/W IniHeld counter 3 tialized Held H'FFFFFFFF H'FE10000C H'1E10000C 32 Timer TCR3 control register 3 R/W IniHeld tialized Held H'0000 Timer TCOR4 R/W IniHeld constant tialized register 4 Held H'FFFFFFFF H'FE100014 H'1E100014 32 Timer TCNT4 R/W IniHeld counter 4 tialized Held H'FFFFFFFF H'FE100018 H'1E100018 32 Timer TCR4 control register 4 Held H'0000 R/W IniHeld tialized H'FE100010 H'1E100010 16 H'FE10001C H'1E10001C 16 Notes: *1 Not initialized in module standby mode when the input clock is the on-chip RTC output clock. *2 Counts in module standby mode when the input clock is the on-chip RTC output clock. 12.2 Register Descriptions 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. TOCR is initialized to H'00 by a power-on or manual reset, but is not initialized in standby mode. Bit: 7 6 5 4 3 2 1 0 — — — — — — — TCOE Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bits 7 to 1—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Rev. 3.0, 04/02, page 290 of 1064 Bit 0—Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin. Bit 0: TCOE Description 0 Timer clock pin (TCLK) is used as external clock input or input capture control input pin (Initial value) 1 Timer clock pin (TCLK) is used as on-chip RTC output clock output pin* Note: * Low-level output in standby mode; high-impedance output in hardware standby mode. 12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (P). Bit: 7 6 5 4 3 2 1 0 — — — — — STR2 STR1 STR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bits 7 to 3—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 2—Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or stopped. Bit 2: STR2 Description 0 TCNT2 count operation is stopped 1 TCNT2 performs count operation (Initial value) Rev. 3.0, 04/02, page 291 of 1064 Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or stopped. Bit 1: STR1 Description 0 TCNT1 count operation is stopped 1 TCNT1 performs count operation (Initial value) Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped. Bit 0: STR0 Description 0 TCNT0 count operation is stopped 1 TCNT0 performs count operation 12.2.3 (Initial value) Timer Start Register 2 (TSTR2) TSTR2 is an 8-bit readable/writable register that specifies whether the channel 3 and 4 timer counters (TCNT) are operated or stopped. TSTR2 is initialized to H'00 by a power-on reset. TSTR retain their contents in standby mode. When standby mode is entered when the value of either STR3 or STR4 is 1, the count halts when the peripheral module clock stops and restarts when the clock supply is resumed. Bit: 7 6 5 4 3 2 1 0 — — — — — — STR4 STR3 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bits 7 to 2—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 1—Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) is operated or stopped. Bit 1: STR4 Description 0 TCNT4 count operation is stopped 1 TCNT4 performs count operation Rev. 3.0, 04/02, page 292 of 1064 (Initial value) Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) is operated or stopped. Bit 0: STR3 Description 0 TCNT3 count operation is stopped 1 TCNT3 performs count operation 12.2.4 (Initial value) Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are five TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCOR registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode. Bit: 31 30 29 2 1 0 ············· Initial value: R/W: 12.2.5 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W Timer Counters (TCNT) The TCNT registers are 32-bit readable/writable registers. There are five TCNT registers, one for each channel. Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control register (TCR). When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the corresponding timer control register (TCR). At the same time, the timer constant register (TCOR) value is set in TCNT, and the count-down operation continues from the set value. The TCNT registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. Rev. 3.0, 04/02, page 293 of 1064 The TCNT registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode. Bit: 31 30 29 2 1 0 ············· Initial value: R/W: 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W In channels 0 to 2, when the input clock is the on-chip RTC output clock (RTCCLK), TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the input clock is the external clock (TCLK) or internal clock (P), TCNT contents are retained in standby mode. 12.2.6 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for each channel. Each TCR selects the count clock, specifies the edge when an external clock is selected in channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT) underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of interrupt generation in the event of input capture. The TCR registers in channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but are not initialized in standby mode. The TCR registers in channels 3 and 4 are initialized to H'0000 by a power-on reset, but are not initialized by a manual reset or in standby mode. 1. Channel 0 and 1 TCR bit configuration Bit: 15 14 13 12 11 10 9 8 — — — — — — — UNF Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 294 of 1064 2. Channel 2 TCR bit configuration Bit: 15 14 13 12 11 10 9 8 — — — — — — ICPF UNF Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 3. Channel 3 and 4 TCR bit configuration Bit: 15 14 13 12 11 10 9 8 — — — — — — — UNF Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 — — UNIE — — TPSC2 TPSC1 TPSC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R R R/W R/W R/W Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in channel 2 only, that indicates the occurrence of input capture. Bit 9: ICPF Description 0 Input capture has not occurred (Initial value) [Clearing condition] When 0 is written to ICPF 1 Input capture has occurred [Setting condition] When input capture occurs* Note: * Writing 1 does not change the value. Rev. 3.0, 04/02, page 295 of 1064 Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF Description 0 TCNT has not underflowed (Initial value) [Clearing condition] When 0 is written to UNF 1 TCNT has underflowed [Setting condition] When TCNT underflows* Note: * Writing 1 does not change the value. Bits 7 and 6—Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. When the input capture function is used, a data transfer request is sent to the DMAC in the event of input capture. When using the input capture function, the TCLK pin must be designated as an input pin with the TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2). The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished. Bit 7: ICPE1 Bit 6: ICPE0 Description 0 0 Input capture function is not used 1 Reserved (Do not set) 0 Input capture function is used, but interrupt due to input capture (TICPI2) is not enabled 1 (Initial value) Data transfer request is sent to DMAC in the event of input capture 1 Input capture function is used, and interrupt due to input capture (TICPI2) is enabled Data transfer request is sent to DMAC in the event of input capture Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. Rev. 3.0, 04/02, page 296 of 1064 Bit 5: UNIE Description 0 Interrupt due to underflow (TUNI) is not enabled 1 Interrupt due to underflow (TUNI) is enabled (Initial value) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): In channels 0 to 2, these bits select the external clock input edge when an external clock is selected or the input capture function is used. Bit 4: CKEG1 Bit 3: CKEG0 Description 0 0 Count/input capture register set on rising edge 1 Count/input capture register set on falling edge X Count/input capture register set on both rising and falling edges 1 (Initial value) Note: X: 0 or 1 (don’t care) Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): In channels 0 to 2, these bits select the TCNT count clock. When the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. When another clock is selected, the channel does not operate in standby mode. Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description 0 0 0 Counts on P
/4 1 Counts on P
/16 0 Counts on P
/64 1 Counts on P
/256 0 Counts on P
/1024 1 Reserved (Do not set) 0 Counts on on-chip RTC output clock (Do not set in channels 3 and 4) 1 Counts on external clock (Do not set in channels 3 and 4) 1 1 0 1 12.2.7 (Initial value) Input Capture Register (TCPR2) TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the input capture control bits (ICPE1, ICPE0) and clock edge bits (CKEG1, CKEG0) in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0. Rev. 3.0, 04/02, page 297 of 1064 TCPR2 is not initialized by a power-on or manual reset, or in standby mode. Bit: 31 30 29 2 1 0 R R R ············· Initial value: R/W: 12.3 Undefined R R R Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 12.3.1 Counter Operation When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function). Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count operation setting procedure. 1. Select the count clock with bits TPSC2–TPSC0 in the timer control register (TCR). When an external clock in channels 0 to 2 is selected, set the TCLK pin to input mode with the TCOE bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR. 2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR. 3. When the input capture function is used, set the ICPE bits in TCR, including specification of whether the interrupt function is to be used. 4. Set a value in the timer constant register (TCOR). 5. Set the initial value in the timer counter (TCNT). 6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count. Rev. 3.0, 04/02, page 298 of 1064 Operation selection Select count clock 1 Underflow interrupt generation setting 2 When input capture function is used Input capture interrupt generation setting Timer constant register setting 4 Set initial timer counter value 5 Start count 6 3 Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated. Figure 12.2 Example of Count Operation Setting Procedure Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCNT value TCOR value set in TCNT on underflow TCOR H'00000000 Time STR0–STR4 UNF Figure 12.3 TCNT Auto-Reload Operation Rev. 3.0, 04/02, page 299 of 1064 TCNT Count Timing:
Operating on internal clock Any of five count clocks (P/4, P/16, P/64, P/256, or P/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case. Pφ Internal clock N+1 TCNT N N–1 Figure 12.4 Count Timing when Operating on Internal Clock
Operating on external clock In channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2–TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR. Figure 12.5 shows the timing for both-edge detection. Pφ External clock input pin TCNT N+1 N N–1 Figure 12.5 Count Timing when Operating on External Clock
Operating on on-chip RTC output clock In channels 0 to 2, the on-chip RTC output clock can be selected as the timer clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.6 shows the timing in this case. Rev. 3.0, 04/02, page 300 of 1064 RTC output clock TCNT N+1 N N–1 Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input mode. 2. Use bits TPSC2–TPSC0 in the timer control register (TCR) to set an internal clock or the onchip RTC output clock as the timer operating clock. 3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to generated when this function is used. 4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register (TCPR2). This function cannot be used in standby mode. When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. Also, a new DMAC transfer request is not generated until processing of the previous request is finished. Figure 12.7 shows the operation timing when the input capture function is used (with TCLK rising edge detection). Rev. 3.0, 04/02, page 301 of 1064 TCNT value TCOR value set in TCNT on underflow TCOR H'00000000 Time TCLK TCPR2 TCNT value set TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on channels 0 to 4, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (on an individual channel basis) when TCR.UNF = 1 and the channel’s interrupt enable bit is 1. When the input capture function is used and an input capture request is generated, an interrupt is requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits (ICPE1, ICPE0) in TCR2 are 11. The TMU interrupt sources are summarized in table 12.3. Rev. 3.0, 04/02, page 302 of 1064 Table 12.3 TMU Interrupt Sources Channel Interrupt Source Description 0 TUNI0 Underflow interrupt 0 1 TUNI1 Underflow interrupt 1 2 TUNI2 Underflow interrupt 2 TICPI2 Input capture interrupt 2 3 TUNI3 Underflow interrupt 3 4 TUNI4 Underflow interrupt 4 12.5 Usage Notes 12.5.1 Register Writes When performing a TMU register write, timer count operation must be stopped by clearing the start bit (STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2). Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF) and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 12.5.2 TCNT Register Reads When performing a TCNT register read, processing for synchronization with the timer count operation is performed. If a timer count operation and register read processing are performed simultaneously, the TCNT counter value prior to the count-down operation is read by means of the synchronization processing. 12.5.3 Resetting the RTC Frequency Divider When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider should be reset. 12.5.4 External Clock Frequency Ensure that the external clock frequency for any channel does not exceed P/4. Rev. 3.0, 04/02, page 303 of 1064 Rev. 3.0, 04/02, page 304 of 1064 Section 13 Bus State Controller (BSC) 13.1 Overview The functions of the bus state controller (BSC) include division of the external memory space, and output of control signals in accordance with various types of memory and bus interface specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7751 Series and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system. 13.1.1 Features The BSC has the following features:
External memory space is managed as 7 independent areas  Maximum 64 Mbytes for each of areas 0 to 6  Bus width of each area can be set in a register (except area 0, which uses an external pin setting)  Wait state insertion by
 pin  Wait state insertion can be controlled by program  Specification of types of memory connectable to each area  Output the control signals of memory to each area  Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas, or a read access followed by a write access to the same area  Write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to low-speed memory
SRAM interface  Wait state insertion can be controlled by program  Wait state insertion by
 pin Connectable areas: 0 to 6 Settable bus widths: 32, 16, 8
DRAM interface  Row address/column address multiplexing according to DRAM capacity  Burst operation (fast page mode, EDO mode)  CAS-before-RAS refresh and self-refresh  4-CAS byte control for power-down operation  DRAM control signal timing can be controlled by register settings Rev. 3.0, 04/02, page 305 of 1064  Consecutive accesses to the same row address Connectable area: 3 Settable bus widths: 32, 16
Synchronous DRAM interface  Row address/column address multiplexing according to synchronous DRAM capacity  Burst operation  Auto-refresh and self-refresh  Synchronous DRAM control signal timing can be controlled by register settings  Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 32
Burst ROM interface  Wait state insertion can be controlled by program  Burst operation, executing the number of transfers set in a register Connectable areas: 0, 5, 6 Settable bus widths: 32, 16, 8
MPX interface  Address/data multiplexing Connectable areas: 0 to 6 Settable bus widths: 32
Byte control SRAM interface  SRAM interface with byte control Connectable areas: 1, 4 Settable bus widths: 32, 16
PCMCIA interface  Wait state insertion can be controlled by program  Bus sizing function for I/O bus width
Fine refreshing control  Supports refresh operation immediately after self-refresh operation in low-power DRAM by means of refresh counter overflow interrupt function
Refresh counter can be used as interval timer  Interrupt request generated by compare-match  Interrupt request generated by refresh counter overflow Rev. 3.0, 04/02, page 306 of 1064 13.1.2 Block Diagram Bus interface Internal bus Figure 13.1 shows a block diagram of the BSC. WCR1 Wait control unit WCR2 WCR3 Area control unit – – BCR1 BCR2 BCR4* – Memory control unit , CKE , MCR Module bus BCR3* RD/ PCR Interrupt controller Peripheral bus RFCR RTCNT Refresh control unit Comparator RTCOR RTCSR BSC WCR: BCR: MCR: PCR: Wait control register Bus control register Memory control register PCMCIA control register RFCR: RTCNT: RTCOR: RTCSR: Refresh count register Refresh timer count register Refresh time constant register Refresh timer control/status register Note: * SH7751R only Figure 13.1 Block Diagram of BSC Rev. 3.0, 04/02, page 307 of 1064 13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals I/O Description Address bus A25–A0 O Address output Data bus D31–D0 I/O Data input/output Bus cycle start
 O Signal that indicates the start of a bus cycle When setting synchronous DRAM interface or MPX interface: asserted once for a burst transfer For other burst transfers: asserted each data cycle Chip select 6–0 Read/write – RD/  O Chip select signals that indicate the area being accessed  and  are also used as PCMCIA  and 
O Data bus input/output direction designation signal Also used as the DRAM/synchronous DRAM/PCMCIA interface write designation signal Row address strobe Read/column address strobe/ cycle frame Data enable 0   O   signal when setting DRAM/synchronous DRAM interface / /   / O Strobe signal that indicates a read cycle When setting synchronous DRAM interface:   signal When setting MPX interface:   signal O When setting PCMCIA interface:  signal When setting SRAM interface: write strobe signal for D7–D0 Data enable 1  O When setting PCMCIA interface: write strobe signal When setting SRAM interface: write strobe signal for D15–D8 Data enable 2 / O When setting PCMCIA interface:  signal When setting SRAM interface: write strobe signal for D23–D16 Data enable 3 /  O When setting PCMCIA interface:   signal When setting SRAM interface: write strobe signal for D31–D24 Rev. 3.0, 04/02, page 308 of 1064 Table 13.1 BSC Pins (cont) Name Column address strobe 0 Signals I/O Description  /DQM0 O When setting DRAM interface:   signal for D7–D0 When setting synchronous DRAM interface: selection signal for D7–D0 Column address strobe 1  /DQM1 O When setting DRAM interface:   signal for D15–D8 When setting synchronous DRAM interface: selection signal for D15–D8 Column address strobe 2  /DQM2 O When setting DRAM interface:   signal for D23–D16 When setting synchronous DRAM interface: selection signal for D23–D16 Column address strobe 3  /DQM3 O When setting DRAM interface:   signal for D31–D24 When setting synchronous DRAM interface: selection signal for D31–D24 Ready Area 0 MPX interface specification/ 16-bit I/O Clock enable Bus release request Bus use permission Area 0 bus width/PCMCIA card select  MD6/ I Wait state request signal I In power-on reset: Designates area 0 bus as MPX interface (1: SRAM, 0: MPX) When setting PCMCIA interface: 16-bit I/O designation signal. Valid only in little-endian mode. CKE
/
 
/
 MD3/ * MD4/
* 1 O Synchronous DRAM clock enable control signal I Bus release request signal/bus acknowledge signal O Bus use permission signal/bus request I/O In power-on reset: area 0 bus width specification signal 2 Endian switchover MD5 When using PCMCIA:  , 
I Endian specification in a power-on reset MD7/ I/O Indicates master/slave status in a power-on reset DMAC0 acknowledge signal DACK0 O DMAC channel 0 data acknowledge DMAC1 acknowledge signal DACK1 O DMAC channel 1 data acknowledge Master/slave switchover Serial interface  Rev. 3.0, 04/02, page 309 of 1064 Notes: *1 MD3/ input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. *2 MD4/
input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. 13.1.4 Register Configuration The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7751 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing. Table 13.2 BSC Registers Name Abbrevia- R/W tion Initial Value Bus control register 1 BCR1 R/W H'0000 0000 H'FF80 0000 H'1F80 0000 32 BCR2 R/W H'3FFC H'FF80 0004 H'1F80 0004 16 H'FF80 0050 H'1F80 0050 16 Bus control register 2 P4 Address Area 7 Address Access Size 2 BCR3 R/W H'0000 Bus control register 4* 2 BCR4 R/W H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32 Wait state control register 1 WCR1 R/W H'7777 7777 H'FF80 0008 H'1F80 0008 32 Wait state control register 2 WCR2 R/W H'FFFE EFFF H'FF80 000C H'1F80 000C 32 Wait state control register 3 WCR3 R/W H'0777 7777 H'FF80 0010 H'1F80 0010 32 R/W H'0000 0000 H'FF80 0014 H'1F80 0014 32 Bus control register 3* Memory control register MCR PCMCIA control register PCR R/W H'0000 H'FF80 0018 H'1F80 0018 16 Refresh timer control/status register RTCSR R/W H'0000 H'FF80 001C H'1F80 001C 16 Refresh timer counter RTCNT R/W H'0000 H'FF80 0020 H'1F80 0020 16 Refresh time constant counter RTCOR R/W H'0000 H'FF80 0024 H'1F80 0024 16 Refresh count register RFCR R/W H'0000 H'FF80 0028 H'1F80 0028 16 Synchronous DRAM mode registers For area 2 SDMR2 W — H'FF90 xxxx* H'1F90 xxxx For area 3 SDMR3 1 1 H'FF94 xxxx* H'1F94 xxxx Notes: *1 For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR). *2 SH7751R only Rev. 3.0, 04/02, page 310 of 1064 8 13.1.5 Overview of Areas Space Divisions: The architecture of the SH7751 Series provides a 32-bit virtual address space. The virtual address space is divided into five areas according to the upper address value. External memory space comprises a 29-bit address space, divided into eight areas. The virtual address can be allocated to any external address by means of the memory management unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section describes the areas into which the external address is divided. With the SH7751 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (–,  ,  ) are output for each of these areas.  is asserted when accessing area 0, and  when accessing area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as
,  , RD/
, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or 6,  ,   is asserted in addition to  ,  for the byte to be accessed. 256 H'0000 0000 P0 and U0 areas P0 and U0 areas H'8000 0000 P1 area H'A000 0000 H'C000 0000 P2 area P3 area H'E000 0000 Store queue area H'E400 0000 P4 area H'FFFF FFFF Physical address space (MMU off) P1 area P2 area Area 0 ( ) H'0000 0000 Area 1 ( ) H'0400 0000 Area 2 ( ) H'0800 0000 Area 3 ( ) H'0C00 0000 Area 4 ( ) H'1000 0000 Area 5 ( ) H'1400 0000 Area 6 ( ) H'1800 0000 H'1C00 0000 H'1FFF FFFF Area 7 (reserved area) P3 area Store queue area P4 area Virtual address space (MMU on) External memory space Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be mapped onto any external space using the TLB. For details, see section 3, Memory Management Unit (MMU). Figure 13.2 Correspondence between Virtual Address Space and External Memory Space Rev. 3.0, 04/02, page 311 of 1064 Table 13.3 External Memory Space Map Area 0 External Addresses H'00000000– H'03FFFFFF 1 H'04000000– H'07FFFFFF 2 H'08000000– H'0BFFFFFF 3 H'0C000000– H'0FFFFFFF 4 H'10000000– H'13FFFFFF 5 H'14000000– H'17FFFFFF 6 H'18000000– H'1BFFFFFF 5 7* H'1C000000– H'1FFFFFFF Size 64 Mbytes 64 Mbytes 64 Mbytes Connectable Memory SRAM Settable Bus Widths 1 8, 16, 32* 1 Burst ROM 8, 16, 32* MPX 32* SRAM 8, 16, 32* 1 8, 16, 32, 6 64* bits, 32 bytes 2 8, 16, 32, 6 64* bits, 32 bytes 2 8, 16, 32, 6 64* bits, 32 bytes 2 MPX 32* Byte control SRAM 16, 32* SRAM 8, 16, 32* 2 Synchronous DRAM 32* * 2 MPX 32* SRAM 8, 16, 32* 2, 3 Synchronous DRAM 32* * 64 Mbytes 64 Mbytes 64 Mbytes 64 Mbytes DRAM 16, 32* ,* MPX 32* SRAM 8, 16, 32* 2 8, 16, 32, 6 64* bits, 32 bytes 2 2, 3 64 Mbytes Access Size 3 2 2 8, 16, 32, 6 64* bits, 32 bytes 2 8, 16, 32, 6 64* bits, 32 bytes 2 MPX 32* Byte control RAM 16, 32* SRAM 8, 16, 32* 2 2 MPX 32* Burst ROM 8, 16, 32* PCMCIA 8, 16* ,* SRAM 8, 16, 32* 2 2 4 2 2 MPX 32* Burst ROM 8,16, 32* 2 8, 16, 32, 6 64* bits, 32 bytes 2, 4 PCMCIA 8,16* * — — Notes: *1 Memory bus width specified by external pins *2 Memory bus width specified by register *3 With synchronous DRAM interface, bus width is 32 bits only With DRAM interface, bus width is 16 or 32 bits only *4 With PCMCIA interface, bus width is 8 or 16 bits only *5 Do not access a reserved area, as operation cannot be guaranteed in this case *6 A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000). In the case of access to external memory by means of FMOV (FPSCR.SZ = 1), two 32-bit access size transfers are performed. Rev. 3.0, 04/02, page 312 of 1064 Area 0: H'00000000 SRAM/burst ROM/MPX Area 1: H'04000000 SRAM/MPX/byte control SRAM Area 2: H'08000000 SRAM/synchronous DRAM/MPX Area 3: H'0C000000 SRAM/synchronous DRAM/DRAM/ MPX Area 4: H'10000000 SRAM/MPX/byte control SRAM Area 5: H'14000000 SRAM/burst ROM/PCMCIA/MPX Area 6: H'18000000 SRAM/burst ROM/PCMCIA/MPX The PCMCIA interface is for memory and I/O card use Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7751 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, or 32 bits can be selected in a power-on reset by means of the
 pin, using external pins. The relationship between the external pins (MD4 and MD3) and the bus width in a power-on reset is shown below. MD4 MD3 Bus Width 0 0 Reserved 1 8 bits 0 16 bits 1 32 bits 1 When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, or 32 bits can be selected. When byte control SRAM interface is used, a bus width of 16, or 32 bits can be selected. When the MPX interface is used, a bus width of 32 bit can be set. When the DRAM interface is used, a bus width of 16, or 32 bits can be selected with the memory control register (MCR). For the synchronous DRAM interface, set a bus width of 32 bit in the MCR register. When using the PCMCIA interface, set a bus width of 8 or 16 bits. For details, see section 13.3.7, PCMCIA Interface. Rev. 3.0, 04/02, page 313 of 1064 For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.8, Memory Control Register (MCR). The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. 13.1.6 PCMCIA Support The SH7751 Series supports PCMCIA interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1). External memory space areas 5 and 6 support both the IC memory card interface and the I/O card interface. The PCMCIA interface is supported only in little-endian mode. Table 13.4 PCMCIA Interface Features Item Features Access Random access Data bus 8/16 bits Memory type Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Common memory capacity Max. 64 Mbytes Attribute memory capacity Max. 64 Mbytes Others Dynamic bus sizing for I/O bus width, access to PCMCIA interface from address translation areas Rev. 3.0, 04/02, page 314 of 1064 Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface Signal Pin Name I/O Function Ground I/O Card Interface Signal Name I/O Function GND 1 GND 2 D3 I/O Data D3 I/O Data D3 3 D4 I/O Data D4 I/O Data D4 4 D5 I/O Data D5 I/O Data D5 5 D6 I/O Data D6 I/O Data D6 6 D7 I/O Data D7 I/O Data D7 7  I Card enable  I  or  8 A10 I Address A10 I Address A10 9  I Output enable  I Output enable  10 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 I Write enable I Write enable  O Ready/busy O Interrupt request Sensed on port Card enable — 16 / /
 17 VCC Operating power supply VCC Operating power supply — 18 VPP1 Programming power supply VPP1 Programming/ peripheral power supply — 19 A16 I Address A16 I Address A16 20 A15 I Address A15 I Address A15 21 A12 I Address A12 I Address A12 22 A7 I Address A7 I Address A7 23 A6 I Address A6 I Address A6 24 A5 I Address A5 I Address A5 25 A4 I Address A4 I Address A4 26 A3 I Address A3 I Address A3 27 A2 I Address A2 I Address A2 28 A1 I Address A1 I Address A1 15 /  Ground Corresponding SH7751 Series Pin Rev. 3.0, 04/02, page 315 of 1064 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface I/O Function Signal Name I/O Function Corresponding SH7751 Series Pin A0 I A0 I A0 30 D0 I/O Data D0 I/O Data D0 31 D1 I/O Data D1 I/O Data D1 32 D2 I/O Data D2 I/O Data D2 33 * O Write protect  O 16-bit I/O port  34 GND Ground GND Ground — 35 GND Ground GND Ground — Card detection Card detection Sensed on port Signal Pin Name 29 Address Address 36  O  O 37 D11 I/O Data D11 I/O Data D11 38 D12 I/O Data D12 I/O Data D12 39 D13 I/O Data D13 I/O Data D13 40 D14 I/O Data D14 I/O Data D14 41 D15 I/O Data D15 I/O Data D15 42  I Card enable  I Card enable  or 
43 RFSH I Refresh request RFSH I Refresh request 44 RFU I I/O read Output from port 45 RFU Reserved    I I/O write    46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Address A20 I Address A20 50 A21 I Address A21 I Address A21 51 VCC Power supply VCC Power supply — 52 VPP2 Programming power supply VPP2 Programming/ peripheral power supply — 53 A22 I Address A22 I Address A22 54 A23 I Address A23 I Address A23 55 A24 I Address A24 I Address A24 56 A25 I Address A25 I Address A25 Reserved Rev. 3.0, 04/02, page 316 of 1064 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface Signal Pin Name I/O Function 57 RFU 58 RESET 59  60 RFU 61  I Attribute memory space select 62 BVD2 O Battery voltage detection 63 BVD1 O Battery voltage detection 64 D8 65 D9 66 I/O Card Interface Signal Name Reserved RFU I Reset RESET O Wait request I/O Function Corresponding SH7751 Series Pin Reserved — I Reset Output from port O Wait request     O Input acknowledge — I Attribute memory space select  O Digital speech signal Sensed on port  O Card status change Sensed on port I/O Data D8 I/O Data D8 I/O Data D9 I/O Data D9 D10 I/O Data D10 I/O Data D10 67  O Card detection  O Card detection Sensed on port 68 GND Ground GND Ground — Reserved   Note: *  is not supported. Rev. 3.0, 04/02, page 317 of 1064 13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: 31 30 29 28 27 26 25 24 ENDIAN MASTER A0MPX — — DPUP IPUP OPUP 0/1* 0/1* 0/1* 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 — — A1MBC A4MBC BREQEN — Initial value: MEMMPX DMABST Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R R/W R/W Bit: 15 14 13 12 11 10 9 8 HIZMEM HIZCNT A0BST2 A0BST1 A0BST0 A5BST2 A5BST1 A5BST0 Initial value: R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 A6BST2 A6BST1 — A56PCM 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 Note: * These bits sample external pin values in a power-on reset by means of the  pin. Rev. 3.0, 04/02, page 318 of 1064 Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset by means of the
 pin. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN Description 0 In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode for the SH7751 Series 1 In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode for the SH7751 Series Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification external pin (MD7) in a power-on reset by means of the
 pin. The master/slave status of all spaces is determined by this bit. MASTER is a read-only bit. Bit 30: MASTER Description 0 In a power-on reset, the master/slave setting external pin (MD7) is high, designating master mode for the SH7751 Series 1 In a power-on reset, the master/slave setting external pin (MD7) is low, designating slave mode for the SH7751 Series Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type specification external pin (MD6) in a power-on reset by means of the
 pin. The memory type of area 0 is determined by this bit. A0MPX is a read-only bit. Bit 29: A0MPX Description 0 In a power-on reset, the external pin specifying the area 0 memory type (MD6) is high, designating the area 0 as SRAM interface 1 In a power-on reset, the external pin specifying the area 0 memory type (MD6) is low, designating the area 0 as MPX interface Bits 28, 27, 23, 22, 18, and 1—Reserved: These bits are always read as 0, and the write value should always be 0. Bit 26—Data pin Pullup Resistor Control (DPUP): Controls the pullup resistance of the data pins (D31 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected. Bit 26: DPUP Description 0 Sets pullup resistance of data pins (D31 to D0) ON 1 Sets pullup resistance of data pins (D31 to D0) OFF (Initial value) Rev. 3.0, 04/02, page 319 of 1064 Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, 
–
, 
, MD6/, ,
). IPUP is initialized by a power-on reset. Bit 25: IPUP Description 0 Pull-up resistor is on for control input pins (NMI, –,
, MD6/, , ) (Initial value) 1 Pull-up resistor is off for control input pins (NMI, –,
, MD6/, , ) Bit 24—Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor status for control output pins (A[25:0], , ,
, ,  , RD/
,
,  ,  , MD5) when high-impedance. OPUP is initialized by a power-on reset. Bit 24: OPUP Description 0 Pull-up resistor is on for control output pins (A[25:0],  , RD/ ,  ,  , 
, MD5) 1
, , , , (Initial value) Pull-up resistor is off for control output pins (A[25:0],
, , , ,  , RD/ ,  ,  , 
, MD5) Bit 21—Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 21: A1MBC Description 0 Area 1 SRAM is set to normal mode 1 Area 1 SRAM is set to byte control mode (Initial value) Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC Description 0 Area 4 SRAM is set to normal mode 1 Area 4 SRAM is set to byte control mode Rev. 3.0, 04/02, page 320 of 1064 (Initial value) Bit 19—BREQ Enable (BREQEN): Indicates whether external requests and bus requests from PCIC can be accepted. BREQEN is initialized to the external request and bus request from PCIC acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. The bus request from the PCIC is always accepted in a slave mode start up. Bit 19: BREQEN Description 0 External requests and bus requests from PCIC are not accepted (Initial value) 1 External requests and bus requests from PCIC are accepted Bit 17—Area 1 to 6 MPX Bus Specification (MEMMPX): Sets the MPX interface when areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a power-on reset. Bit 17: MEMMPX Description 0 SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) (Initial value) 1 MPX interface is selected when areas 1 to 6 are set as SRAM interface (or burst ROM interface) Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST): Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not performed until the end of the DMAC’s burst transfer. This bit is initialized at a power-on reset. Bit 16: DMABST Description 0 DMAC burst mode transfer priority specification OFF 1 DMAC burst mode transfer priority specification ON (Initial value) Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals (A[25:0], , , RD/
,  ,  ) in standby mode. Bit 15: HIZMEM 0 1 Description The A[25:0],
, , RD/ ,  , and 
signals go to highimpedance (High-Z) in standby mode and when the bus is released (Initial value) The A[25:0],
, , RD/ ,  , and 
signals drive in standby mode Rev. 3.0, 04/02, page 321 of 1064 Bit 14—High Impedance Control (HIZCNT): Specifies the state of the
 and   signals in standby mode and when the bus is released. Bit 14: HIZCNT Description The  , ,  /DQMn, and / /   signals go to highimpedance (Hi-Z) in standby mode and when the bus is released (Initial value) 0 The  , ,  /DQMn, and / /   signals drive in standby mode and when the bus is released 1 Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored. Bit 13: A0BST2 Bit 12: A0BST1 Bit 11: A0BST0 Description 0 0 0 Area 0 is accessed as SRAM interface (Initial value) 1 Area 0 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 0 Area 0 is accessed as burst ROM interface (8 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 Area 0 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 0 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 Rev. 3.0, 04/02, page 322 of 1064 1 Reserved 0 Reserved 1 Reserved Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0 Description 0 0 0 Area 5 is accessed as SRAM interface (Initial value) 1 Area 5 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 0 Area 5 is accessed as burst ROM interface (8 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 Area 5 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 5 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 Reserved 0 Reserved 1 Reserved Note: Clear to 0 when PCMCIA interface is set. Rev. 3.0, 04/02, page 323 of 1064 Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0 Description 0 0 0 Area 6 is accessed as SRAM interface (Initial value) 1 Area 6 is accessed as burst ROM interface (4 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 0 Area 6 is accessed as burst ROM interface (8 consecutive accesses) Can be used with 8-, 16-, or 32-bit bus width 1 Area 6 is accessed as burst ROM interface (16 consecutive accesses) Can only be used with 8- or 16-bit bus width. Do not specify for 32-bit bus width 1 0 0 Area 6 is accessed as burst ROM interface (32 consecutive accesses) Can only be used with 8-bit bus width 1 1 Reserved 0 Reserved 1 Reserved Note: Clear to 0 when PCMCIA is used. Rev. 3.0, 04/02, page 324 of 1064 Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be directly connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description 0 0 1 1 0 1 0 Areas 2 and 3 are accessed as SRAM interface or MPX interface* (Initial value) 1 Reserved (Cannot be set) 0 Area 2 is accessed as SRAM interface or MPX interface*, area 3 is synchronous DRAM interface 1 Areas 2 and 3 are accessed as synchronous DRAM interface 0 Area 2 is accessed as SRAM interface or MPX interface*, area 3 is DRAM interface 1 Reserved (Cannot be set) 0 Reserved (Cannot be set) 1 Reserved (Cannot be set) Note: * Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX bit Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as PCMCIA interface. The setting of these bits has priority over the MEMMPX and AnBST bit settings. Bit 0: A56PCM Description 0 Areas 5 and 6 are accessed as SRAM interface 1 Areas 5 and 6 are accessed as PCMCIA interface* (Initial value) Note: * The MD3 pin is designated for output as the  pin. The MD4 pin is designated for output as the 
pin. Rev. 3.0, 04/02, page 325 of 1064 13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 32-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode. External memory space other than area 0 should not be accessed until register initialization is completed. Bit: 15 14 13 12 11 10 9 8 A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 0/1* 0/1* 1 1 1 1 1 1 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A0SZ0 — PORTEN 1 1 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W — R/W Initial value: Initial value: R/W: Note: * These bits sample the values of the external pins that specify the area 0 bus size. Bits 15 and 14—Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins (MD3 and MD4) that specify the bus size in a power-on reset. They are read-only bits. Bit 15: MD4 Bit 14: MD3 Bus Width 0 0 Reserved (Setting prohibited) 1 8 bits 0 16 bits 1 32 bits 1 Rev. 3.0, 04/02, page 326 of 1064 Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Description 0 0 Reserved (Setting prohibited) 1 Bus width is 8 bits 0 Bus width is 16 bits 1 Bus width is 32 bits 0 Reserved (Setting prohibited) 1 Bus width is 8 bits 0 Bus width is 16 bits 1 Bus width is 32 bits 0 1 1 0 1 (Initial value) Bit 1—Reserved: This bit is always read as 0, and should only be written with 0. Bit 0—Port Function Enable (PORTEN): Specifies whether pins AD31 to AD0 are used as a 32-bit port. However, select PCI-disable mode when using this function. Bit 0: PORTEN Description 0 AD31 to AD0 are not used as a port 1 AD31 to AD0 are used as a port 13.2.3 (Initial value) Bus Control Register 3 (BCR3) (SH7751R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used. BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. No external memory space other than area 0 should be accessed before register initialization has been completed. Rev. 3.0, 04/02, page 327 of 1064 Bit: Bit name: Initial value: 15 14 13 12 11 10 9 8 MEMMODE A1MPX A4MPX — — — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R R Bit: 7 6 5 4 3 2 1 0 R/W: Bit name: — — — — — — — SDBL Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit 15A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by MEMMPX. Bit 15: MEMMODE Description 0 MPX or SRAM interface is selected by MEMMPX 1 MPX or SRAM interface is selected by A1MPX and A4MPX (Initial value) Bits 14, 13MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits specify the types of memory connected to areas 1 and 4. These settings are validated by MEMMODE. Bit 14: A1MPX Description 0 SRAM/byte control SRAM interface is selected for area 1 1 MPX interface is selected for area 1 Bit 13: A4MPX Description 0 SRAM/byte control SRAM interface is selected for area 4 1 MPX interface is selected for area 4 (Initial value) (Initial value) Bit 0Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is used. The burst-length setting is only valid when the bus width is 32 bits. Bit 0: SDBL Description 0 Burst length is 8 1 Burst length is 4 Rev. 3.0, 04/02, page 328 of 1064 (Initial value) 13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only) Bus control register 4 (BCR4) is a register that enables asynchronous input for pins corresponding to individual bits. The BCR4 register is a 32-bit readable/writable register. It is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than when synchronous input is set (ASYNCn = 0)* (see figure 13.4) The timings shown in this section and section 23, Electrical Characteristics, are all for the case where synchronous input is set (ASYNCn = 0). Note: * With the synchronous input setting, ensure that setup and hold times are observed. Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R 4 3 2 1 0 Bit: 7 6 5 — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W ASYNC4 ASYNC3 ASYNC2 ASYNC1 ASYNC0 Bits 31 to 5—Reserved: These bits are always read as 0, and the write value should always be 0. Rev. 3.0, 04/02, page 329 of 1064 Bits 4 to 0—Asynchronous Input: These bits enable asynchronous input for the corresponding pins. Bit 4–0: ASYNCn Description 0 Corresponding pin is synchronous input with respect to CKIO (Initial value) 1 Asynchronous input with respect to CKIO is enabled for corresponding pin Bit 4

 3   2  1  0  T1 Tw Tw Twe T2 CKIO (BCR4.ASYNC0 = 0) (BCR4.ASYNC0 = 1) Figure 13.4 Example of
 Sampling Timing at which BCR4 is Set (Two Wait Cycles are Inserted by WCR2) Rev. 3.0, 04/02, page 330 of 1064 13.2.5 Wait Control Register 1 (WCR1) Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a data bus collision when consecutive memory accesses are performed on memory in different areas, or when a memory write is performed immediately after a read. In the SH7751 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision. WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 31 — 30 29 28 DMAIW2 DMAIW1 DMAIW0 27 26 25 24 — A6IW2 A6IW1 A6IW0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 — A5IW2 A5IW1 A5IW0 — A4IW2 A4IW1 A4IW0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 — A3IW2 A3IW1 A3IW0 — A2IW2 A2IW1 A2IW0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 — A1IW2 A1IW1 A1IW0 — A0IW2 A0IW1 A0IW0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and the write value should always be 0. Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2– DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the Rev. 3.0, 04/02, page 331 of 1064 same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual address transfer, inter-area idle cycles are inserted. Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from external memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the same space. DMAIW2/AnIW2 DMAIW1/AnIW1 DMAIW0/AnIW0 Inserted Idle Cycles 0 0 0 0 1 1 0 2 1 3 0 6 1 9 0 12 1 15 1 1 0 1 Rev. 3.0, 04/02, page 332 of 1064 (Initial value) Table 13.6 Idle Insertion between Accesses Following Cycle Same Area Read Preceding Cycle CPU DMA Read Write
DMA write (device memory)
D D Read Write Different Area CPU DMA CPU DMA CPU DMA MPX MPX Address Address Output Output M M M M M (1) M Write DMA read (memory device) Same Area Different Area M M D D* 1 M 2 M (1) M M M M * M M M M M — M (1) D D D D — D (1) "DMA" in the table indicates DMA single-address transfer. DMA dual-address transfer is in accordance with the CPU. M, D : Idle wait always inserted by WCR1 (M(1): Once cycle inserted in MPX access even if WCR1 is cleared to 0) M : Idle cycles according to setting of AnIW2-AnIW0 (areas 0 to 6) D : Idle cycles according to setting of DMAIW2-DMAIW0 Notes: *1: Inserted when device is switched *2: On the MPX interface, a WCR1 idle wait may be inserted before an access (either read or write) to the same area after a write access. The specific conditions for idle wait insertion in accesses to the same area are shown below. (a) Synchronous DRAM set to RAS down mode (b) Synchronous DRAM accessed by on-chip DMAC Apart from use under above conditions (a) and (b), an idle wait is also inserted between an MPX interface write access and a following access to the same area. Even under the above conditions, an idle wait may be inserted in a same-area access following an interface write access, depending on the synchronous DRAM pipeline access situation. An idle wait is not inserted when the WCR1 register setting is 0. The setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set. When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to 000 and bits A3IW2-A3IW0 to 000. Rev. 3.0, 04/02, page 333 of 1064 13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access. This enables low-speed memory to be connected without using external circuitry. WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 — 1 1 1 1 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R 15 14 13 12 11 10 9 8 A3W2 A3W1 A3W0 — A2W2 A2W1 A2W0 A1W2 1 1 1 0 1 1 1 1 R/W R/W R/W R R/W R/W R/W R/W 7 6 5 4 3 2 1 0 A1W1 A1W0 A0W2 A0W1 A0W0 A0B2 A0B1 A0B0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 334 of 1064 Bits 31 to 29—Area 6 Wait Control (A6W2–A6W0): These bits specify the number of wait states to be inserted for area 6. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 31: A6W2 Bit 30: A6W1 Bit 29: A6W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 0 1 Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer. Description Burst Cycle (Excluding First Cycle) Bit 28: A6B2 Bit 27: A6B1 Bit 26: A6B0 Wait States Inserted from Second Data Access Onward 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 4 Enabled 1 5 Enabled 0 6 Enabled 1 7 (Initial value) Enabled 1 1 0 1  Pin Rev. 3.0, 04/02, page 335 of 1064 Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 25: A5W2 Bit 24: A5W1 Bit 23: A5W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 0 1 Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer. Description Burst Cycle (Excluding First Cycle) Bit 22: A5B2 Bit 21: A5B1 Bit 20: A5B0 Wait States Inserted from Second Data Access Onward 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 4 Enabled 1 5 Enabled 0 6 Enabled 1 7 (Initial value) Enabled 1 1 0 1 Rev. 3.0, 04/02, page 336 of 1064  Pin Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For the case where an MPX interface setting is made, see table 13.7. Description Bit 19: A4W2 Bit 18: A4W1 Bit 17: A4W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 0 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 Bits 16 and 12—Reserved: These bits are always read as 0, and should only be written with 0. Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait states to be inserted for area 3. External wait input is only enabled when the SRAM interface or MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For the case where an MPX interface setting is made, see table 13.7.
When SRAM Interface is Set Description Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 0 1 Rev. 3.0, 04/02, page 337 of 1064 
When DRAM or Synchronous DRAM Interface is Set* Note: * External wait input is always ignored Description Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 DRAM   Assertion Width Synchronous DRAM   Latency Cycles 0 0 0 1 Inhibited 1 2 1* 1 0 3 2 1 4 3 0 0 7 4* 1 10 5* 0 13 Inhibited 1 16 Inhibited 1 1 Note: * Inhibited in RAS down mode Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX interface is used, and is ignored when synchronous DRAM is used. For the case where an MPX interface setting is made, see table 13.7.
When SRAM Interface is Set Description Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 1 0 2 Enabled 1 3 Enabled 0 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 Rev. 3.0, 04/02, page 338 of 1064 
When Synchronous DRAM Interface is Set* 1 Description Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Synchronous DRAM   Latency Cycles 0 0 0 Inhibited 1 1* 0 2 1 3 0 4* 1 5* 0 Inhibited 1 Inhibited 1 1 0 1 2 2 2 Notes: *1 External wait input is always ignored *2 Inhibited in RAS down mode Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1. For the case where an MPX interface setting is made, see table 13.7. Description Bit 8: A1W2 Bit 7: A1W1 Bit 6: A1W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 0 1 Rev. 3.0, 04/02, page 339 of 1064 Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For the case where an MPX interface setting is made, see table 13.7. Description First Cycle Bit 5: A0W2 Bit 4: A0W1 Bit 3: A0W0 Inserted Wait States  Pin 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 6 Enabled 1 9 Enabled 0 12 Enabled 1 15 (Initial value) Enabled 1 1 0 1 Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to be inserted from the second data access onward at the time of setting the burst ROM in a burst transfer. Description Burst Cycle (Excluding First Cycle) Bit 2: A0B2 Bit 1: A0B1 Bit 0: A0B0 Wait States Inserted from Second Data Access Onward 0 0 0 0 Ignored 1 1 Enabled 0 2 Enabled 1 3 Enabled 0 4 Enabled 1 5 Enabled 0 6 Enabled 1 7 (Initial value) Enabled 1 1 0 1 Rev. 3.0, 04/02, page 340 of 1064  Pin Table 13.7 When MPX Interface is Set (Areas 0 to 6) Description Inserted Wait States 1st Data AnW2 AnW1 AnW0 Read Write 2nd Data Onward  Pin 0 0 0 1 0 0 Enabled 1 1 1 0 1 0 2 2 Enabled 1 3 3 Enabled 0 1 0 1 1 Enabled 1 Enabled 1 Enabled 0 2 2 Enabled 1 3 3 Enabled (n = 6 to 0) Rev. 3.0, 04/02, page 341 of 1064 13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry. WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 31 30 29 28 27 26 25 24 — — — — — A6S0 A6H1 A6H0 Initial value: 0 0 0 0 0 1 1 1 R/W: R R R R R R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 — A5S0 A5H1 A5H0 A4RDH* A4S0 A4H1 A4H0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R/W* R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Bit name: — A3S0 A3H1 A3H0 — A2S0 A2H1 A2H0 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 A1RDH* A1S0 A1H1 A0H0 — A0S0 A0H1 A0H0 0 1 1 1 0 1 1 1 R/W* R/W R/W R/W R R/W R/W R/W Initial value: R/W: Note: * These bits can be set only in the SH7751R. Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3 (SH7751) Bits 31 to 27, 23, 15, 11, and 3 (SH7751R) Reserved: These bits are always read as 0, and should only be written with 0. Note: * These bits can be set only in the SH7751R. Rev. 3.0, 04/02, page 342 of 1064 Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface: Bit 4n + 2: AnS0 Waits Inserted in Setup 0 0 1 1 (Initial value) (n = 6 to 0) Bits 4n + 1 and 4n—Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits specify the number of cycles to be inserted in the hold time from negation of the write strobe. When reading, they specify the number of cycles to be inserted in the hold time from the data sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface: Bit 4n + 1: AnH1 0 1 Bit 4n: AnH0 Waits Inserted in Hold 0 0 1 1 0 2 1 3 (Initial value) (n = 6 to 0) Bits 4n+3Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in the SH7751R): When reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when a byte control SRAM setting is made. When reading in area 1 or 4, AnRDH bits specify the number of cycles to be inserted in the hold time from the time at which the data is sampled or from the negation of the read strobe. Valid only for the SRAM interface. Bit 4n + 3: AnRDH Waits Inserted in Hold 0 0 1 1 (Initial value) Rev. 3.0, 04/02, page 343 of 1064 13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies
 and   timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected without using external circuitry. MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE, SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a poweron reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the same values should be written to the other bits so that they remain unchanged. When using DRAM or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is completed. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 RASD MRSET TRC2 TRC1 TRC0 — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R 23 22 21 20 19 18 17 16 TCAS — TPC2 TPC1 TPC0 — RCD1 RCD0 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R R/W R/W 15 14 13 12 11 10 9 8 TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 BE SZ1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SZ0 AMXEXT AMX2 AMX1 AMX0 RFSH RMODE EDO MODE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 344 of 1064 Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface. Bit 31: RASD Description 0 Normal mode 1 RAS down mode (Initial value) Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000 and bits A3IW2–A3IW0 to 000. Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface. Bit 30: MRSET Description 0 All-bank precharge 1 Mode register setting (Initial value) Bits 26 to 24, 22, and 18—Reserved: These bits should only be written with 0. Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled, DRAM: auto- and self-refresh both enabled) Bit 29: TRC2 Bit 28: TRC1 Bit 27: TRC0 RAS Precharge Time Immediately after Refresh 0 0 0 0 1 3 1 0 6 1 9 0 12 1 15 0 18 1 21 1 0 1 (Initial value) Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set. Bit 23: TCAS CAS Negation Period 0 1 1 2 (Initial value) Rev. 3.0, 04/02, page 345 of 1064 Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is set, these bits specify the minimum number of cycles until
 is asserted again after being negated. When the synchronous DRAM interface is set, these bits specify the minimum number of cycles until the next bank active command is output after precharging. RAS Precharge Time Bit 21: TPC2 Bit 20: TPC1 Bit 19: TPC0 DRAM Synchronous DRAM 0 0 0 0 1* (Initial value) 1 1 2 0 2 3 1 3 4* 0 4 5* 1 5 6* 0 6 7* 1 7 8* 1 1 0 1 Note: * Inhibited in RAS down mode Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the
-  assertion delay time. When the synchronous DRAM interface is set, these bits set the bank active-read/write command delay time. Description Bit 17: RCD1 Bit 16: RCD0 DRAM Synchronous DRAM 0 0 2 cycles Reserved (Setting prohibited) 1 3 cycles 2 cycles 0 4 cycles 3 cycles 1 5 cycles 4 cycles* 1 Note: * Inhibited in RAS down mode Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next bank active command is issued after a write cycle. After a write cycle, the next active command is not issued for a period of TPC + TRWL. In RAS down mode, they specify the time until the next precharge command is issued. After a write cycle, the next precharge command is not issued for a period of TRWL. This setting is valid only when synchronous DRAM interface is set. For the setting values and delay time when no command is issued, refer to section 23.3.3, Bus Timing. Rev. 3.0, 04/02, page 346 of 1064 Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time 0 0 0 1 (Initial value) 1 2 0 3* 1 4* 0 5* 1 Reserved (Setting prohibited) 0 Reserved (Setting prohibited) 1 Reserved (Setting prohibited) 1 1 0 1 Note: * Inhibited in RAS down mode Bits 12 to 10—CAS-Before-RAS Refresh
 Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the
 assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for a period of TRC* + TRAS after an auto-refresh command is issued.  /DRAM Command Interval after Synchronous DRAM Refresh Bit 12: TRAS2 Bit 11: TRAS1 Bit 10: TRAS0 Assertion Time 0 0 0 2 4 + TRC* (Initial value) 1 3 5 + TRC 0 4 6 + TRC 1 5 7 + TRC 0 6 8 + TRC 1 7 9 + TRC 0 8 10 + TRC 1 9 11 + TRC 1 1 0 1 Note: * Bits 29 to 27: RAS precharge interval at end of refresh Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In synchronous DRAM access, burst access is always performed regardless of the specification of this bit. The DRAM transfer mode depends on EDOMODE. Rev. 3.0, 04/02, page 347 of 1064 BE EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer 0 0 Single Single 1 Setting prohibited Setting prohibited 0 Single/fast page* Fast page 1 EDO EDO 1 Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM. This setting has priority over the BCR2 register setting. Description Bit 8: SZ1 Bit 7: SZ0 DRAM SDRAM 0 0 Reserved (Setting prohibited) Reserved (Setting prohibited) 1 Reserved (Setting prohibited) Reserved (Setting prohibited) 0 16 bits Reserved (Setting prohibited) 1 32 bits 32 bits 1 Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address multiplexing for DRAM and synchronous DRAM. The address shift value is different for the DRAM interface and the synchronous DRAM interface.
For DRAM Interface: Description Bit 6: AMXEXT Bit 5: AMX2 Bit 4: AMX1 Bit 3: AMX0 0* 0 0 0 8-bit column address product (Initial value) 1 9-bit column address product 1 1 0 1 DRAM 0 10-bit column address product 1 11-bit column address product 0 12-bit column address product 1 Reserved (Setting prohibited) 0 Reserved (Setting prohibited) 1 Reserved (Setting prohibited) Note: * When the DRAM interface is used, clear the AMXEXT bit to 0. Rev. 3.0, 04/02, page 348 of 1064 
For Synchronous DRAM Interface: AMX AMXEXT SZ 0 0 32 1 1 0 1 2 — 3 — 4 — 5 — 6 0 1 7 — Example Synchronous DRAM Configurations BANK (16M: 512k a[21]*  16 bits  2)  2 (16M: 512k  16 bits  2)  2 (16M: 1M  8 bits  2)  4 (16M: 1M  8 bits  2)  4 (64M: 1M  16 bits  4)  2 (64M: 2M  8 bits  4)  4 (64M: 512k  32 bits  4)  1 (64M: 1M  32 bits  2)  1 (64M: 4M  4 bits  4)  8 (256M: 4M  16 bits  4)  2 (16M: 256k  32 bits  2)  1 a[20]* a[22]* a[21]* a[23:22]* a[24:23]* a[22:21]* a[22]* a[25:24]* a[25:24]* a[20]* Note: a[x]: External address, not address pin Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. Bit 2: RFSH Description 0 Refreshing is not performed 1 Refreshing is performed (Initial value) Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CASbefore-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous DRAM, after waiting for the end of any currently executing external bus cycle. All refresh requests for memory in the self-refresh state are ignored. Bit 1: RMODE Description 0 CAS-before-RAS refreshing is performed (when RFSH = 1) 1 Self-refreshing is performed (when RFSH = 1) (Initial value) Rev. 3.0, 04/02, page 349 of 1064 Bit 0—EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of memory other than DRAM. Set this bit to 1 only when DRAM is used. 13.2.9 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the  and  signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6. The  and  signal assertion width is set by the wait control bits in the WCR2 register. PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 15 14 13 12 11 10 9 8 Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2 Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit name: A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Bit 15: A5PCW1 Bit 14: A5PCW0 Waits Inserted 0 0 0 (Initial value) 1 15 0 30 1 50 1 Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Rev. 3.0, 04/02, page 350 of 1064 Bit 13: A6PCW1 Bit 12: A6PCW0 Waits Inserted 0 0 0 (Initial value) 1 15 0 30 1 50 1 Bits 11 to 9—Address-OE/WE Assertion Delay (A5TED2–A5TED0): These bits set the delay time from address output to / assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Bit 11: A5TED2 Bit 10: A5TED1 Bit 9: A5TED0 Waits Inserted 0 0 0 0 (Initial value) 1 1 1 0 2 1 3 0 0 6 1 9 0 12 1 15 1 1 Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay time from address output to / assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0 Waits Inserted 0 0 0 0 (Initial value) 1 1 1 0 2 1 3 0 6 1 9 0 12 1 15 1 0 1 Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address hold delay time from / negation in a write on the connected PCMCIA interface or in an I/O card read. In the case of a memory card read, the address hold delay time from the data sampling timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Rev. 3.0, 04/02, page 351 of 1064 Bit 5: A5TEH2 Bit 4: A5TEH1 Bit 3: A5TEH0 Waits Inserted 0 0 0 0 (Initial value) 1 1 0 2 1 3 0 6 1 9 0 12 1 15 1 1 0 1 Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address hold delay time from / negation in a write on the connected PCMCIA interface or in an I/O card read. In the case of a memory card read, the address hold delay time from the data sampling timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Bit 2: A6TEH2 Bit 1: A6TEH1 Bit 0: A6TEH0 Waits Inserted 0 0 0 0 (Initial value) 1 1 1 0 2 1 3 0 6 1 9 0 12 1 15 1 0 1 13.2.10 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3 synchronous DRAM. Settings for the SDMR register must be made before accessing synchronous DRAM. Rev. 3.0, 04/02, page 352 of 1064 Bit: 15 14 13 12 11 10 9 8 Initial value: — — — — — — — — R/W: W W W W W W W W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W: W W W W W W W W Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register, if the value to be set is “X” and the SDMR register address is “Y”, value “X” is written to the synchronous DRAM mode register by performing a write to address X + Y. When the synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7751 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7751 Series, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right. For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written to the SDMR register. The range of value “X” is H'0000 to H'0FFC. Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF940000 (address “Y”) + H'08C0 (value “X”) (= H'FF9408C0). As a result, H'0230 is written to the SDMR register. The range of value “X” is H'0000 to H'0FFC. The lower 16 bits of the address are set in the synchronous DRAM mode register. The burst length is 4 and 8*. Setting to SDMR writes into the following addresses in byte size. Note: * SH7751R only Bus Width 32 32 4 8* CAS Latency Area 2 Area 3 1 H'FF900048 H'FF940048 2 H'FF900088 H'FF940088 3 H'FF9000C8 H'FF9400C8 1 H'FF90004C H'FF94004C 2 H'FF90008C H'FF94008C 3 H'FF9000CC H'FF9400CC Rev. 3.0, 04/02, page 353 of 1064 For a 32-bit bus: Address 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 LMO LMO LMO WT BL2 BL1 BL0 DE2 DE1 DE0 
10 bits set in case of 32-bit bus width LMODE: RAS-CAS latency BL: Burst length WT: Wrap type (0: Sequential) BL 000: Reserved 001: Reserved 010: 4 011: 8* 100: Reserved 101: Reserved 110: Reserved 111: Reserved LMODE 000: Reserved 001: 1 010: 2 011: 3 100: Reserved 101: Reserved 110: Reserved 111: Reserved Note: * SH7751R only 13.2.11 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — — — Bit: 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Rev. 3.0, 04/02, page 354 of 1064 Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15, Notes on Accessing Refresh Control Registers. Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF Description 0 RTCNT and RTCOR values do not match (Initial value) [Clearing condition] When 0 is written to CMF 1 RTCNT and RTCOR values match [Setting condition] When RTCNT = RTCOR* Note: * If 1 is written, the original value is retained. Bit 6—Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CASbefore-RAS refreshing or auto-refreshing is used. Bit 6: CMIE Description 0 Interrupt requests initiated by CMF are disabled 1 Interrupt requests initiated by CMF are enabled (Initial value) Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO by the specified factor. Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description 0 0 0 Clock input disabled 1 Bus clock (CKIO)/4 0 CKIO/16 1 CKIO/64 0 0 CKIO/256 1 CKIO/1024 1 0 CKIO/2048 1 CKIO/4096 1 1 (Initial value) Rev. 3.0, 04/02, page 355 of 1064 Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF Description 0 RFCR has not overflowed the count limit indicated by LMTS (Initial value) [Clearing condition] When 0 is written to OVF 1 RFCR has overflowed the count limit indicated by LMTS [Setting condition] When RFCR overflows the count limit set by LMTS* Note: * If 1 is written, the original value is retained. Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression of an interrupt request when the OVF flag is set to 1 in RTCSR. Bit 1: OVIE Description 0 Interrupt requests initiated by OVF are disabled 1 Interrupt requests initiated by OVF are enabled (Initial value) Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value exceeds the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description 0 Count limit is 1024 1 Count limit is 512 (Initial value) 13.2.12 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the RTCNT counter is cleared. RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is performed. In standby mode, RTCNT is not initialized, and retains its contents. Rev. 3.0, 04/02, page 356 of 1064 Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — — — Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: 13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are constantly compared, and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh cycle is generated when the CMF bit is set. RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — — — Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Rev. 3.0, 04/02, page 357 of 1064 13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared. RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: 15 14 13 12 11 10 9 8 — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: 13.2.15 Notes on Accessing Refresh Control Registers When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The following procedures should be used for read/write operations. Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a byte transfer instruction. When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits starting from the MSB in the upper byte, and the write data in the remaining bits. Rev. 3.0, 04/02, page 358 of 1064 RTCSR, RTCNT, RTCOR RFCR 15 14 13 12 11 10 9 8 1 0 1 0 0 1 0 1 15 14 13 12 11 10 9 8 1 0 1 0 0 1 7 6 5 4 3 2 1 0 2 1 0 Write data 7 6 5 4 3 Write data Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0. 13.3 Operation 13.3.1 Endian/Access Size and Data Alignment The SH7751 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on reset by means of the
 pin, big-endian mode being set if the MD5 pin is low, and little-endian mode if it is high. A data bus width of 8, 16, or 32 bits can be selected for normal memory, 16 or 32 bits for DRAM, 32 bit for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data alignment is carried out according to the data bus width and endian mode of each device. Accordingly, when the data bus width is narrower than the access size, multiple bus cycles are automatically generated to reach the access size. In this case, access is performed by automatically incrementing addresses to the bus width. For example, when a long word access is performed at the area with an 8-bit bus width in the SRAM interface, each address is incremented one by one, and then access is performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in 32-byte boundary data using waparound. During these transfers, the bus is not released and refresh operation is not performed. In the SH7751 Series, data alignment and data length conversion between the different interfaces is performed automatically. Quadword access is used only in transfer by the DMAC. The relationship between the endian mode, device data length, and access unit, is shown in tables 13.8 to 13.13. Rev. 3.0, 04/02, page 359 of 1064 Data Configuration MSB Byte LSB Data 7–0 MSB Word LSB Data 15–8 Data 7–0 Data 31–24 Data 23–16 MSB Longword LSB Data 15–8 Data 7–0 MSB Quadword LSB Data 63–56 Data 55–48 Data 47–40 Data 39–32 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte
,
,
,
 , , , ,  , DQM3 DQM2 DQM1 DQM0 4n 1 Data 7–0 — — — 4n+1 1 — Data 7–0 — — 4n+2 1 — — Data 7–0 — 4n+3 1 — — — Data 7–0 4n 1 Data 15–8 Data 7–0 — — 4n+2 1 — — Data 15–8 Data 7–0 Asserted Asserted Longword 4n 1 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Asserted Asserted Asserted Asserted Quadword 8n 1 Data 63–56 Data 55–48 Data 47–40 Data 39–32 Asserted Asserted Asserted Asserted 8n+4 2 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Asserted Asserted Asserted Asserted Word Rev. 3.0, 04/02, page 360 of 1064 Asserted Asserted Asserted Asserted Asserted Asserted Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte
,
,
,
 , , , ,  , DQM3 DQM2 DQM1 DQM0 2n 1 — — Data 7–0 — 2n+1 1 — — — Data 7–0 Asserted Word 2n 1 — — Data 15–8 Data 7–0 Asserted Asserted Longword 4n 1 — — Data 31–24 Data 23–16 Asserted Asserted 4n+2 2 — — Data 15–8 Data 7–0 Asserted Asserted 8n 1 — — Data 63–56 Data 55–48 Asserted Asserted 8n+2 2 — — Data 47–40 Data 39–32 Asserted Asserted 8n+4 3 — — Data 31–24 Data 23–16 Asserted Asserted 8n+6 4 — — Data 15–8 Data 7–0 Asserted Asserted Quadword Asserted Rev. 3.0, 04/02, page 361 of 1064 Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0
,
,
,
 , , , ,  , DQM3 DQM2 DQM1 DQM0 Byte n 1 — — — Data 7–0 Asserted Word 2n 1 — — — Data 15–8 Asserted 2n+1 2 — — — Data 7–0 Asserted 4n 1 — — — Data 31–24 Asserted 4n+1 2 — — — Data 23–16 Asserted 4n+2 3 — — — Data 15–8 Asserted 4n+3 4 — — — Data 7–0 Asserted 8n 1 — — — Data 63–56 Asserted 8n+1 2 — — — Data 55–48 Asserted 8n+2 3 — — — Data 47–40 Asserted 8n+3 4 — — — Data 39–32 Asserted 8n+4 5 — — — Data 31–24 Asserted 8n+5 6 — — — Data 23–16 Asserted 8n+6 7 — — — Data 15–8 Asserted 8n+7 8 — — — Data 7–0 Asserted Longword Quadword Rev. 3.0, 04/02, page 362 of 1064 Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Access Size Address No.
,
,
,
 , , , ,  , D23–D16 D15–D8 D7–D0 — — Data 7–0 — — Data 7–0 — 1 — Data 7–0 — — 4n+3 1 Data 7–0 — — — 4n 1 — — Data 15–8 Data 7–0 4n+2 1 Data 15–8 Data 7–0 — — Asserted Asserted Longword 4n 1 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Asserted Asserted Asserted Asserted Quadword 8n 1 Data 31–24 Data 23–16 Data 15–8 Data 7–0 Asserted Asserted Asserted Asserted 8n+4 2 Data 63–56 Data 55–48 Data 47–40 Data 39–32 Asserted Asserted Asserted Asserted Byte Word 4n 1 4n+1 1 4n+2 D31–D24 Strobe Signals DQM3 DQM2 DQM1 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Rev. 3.0, 04/02, page 363 of 1064 Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 Byte
,
,
,
 , , , ,  , DQM3 DQM2 DQM1 DQM0 2n 1 — — — Data 7–0 2n+1 1 — — Data 7–0 — Asserted Word 2n 1 — — Data 15–8 Data 7–0 Asserted Asserted Longword 4n 1 — — Data 15–8 Data 7–0 Asserted Asserted 4n+2 2 — — Data 31–24 Data 23–16 Asserted Asserted 8n 1 — — Data 15–8 Data 7–0 Asserted Asserted 8n+2 2 — — Data 31–24 Data 23–16 Asserted Asserted 8n+4 3 — — Data 47–40 Data 39–32 Asserted Asserted 8n+6 4 — — Data 63–56 Data 55–48 Asserted Asserted Quadword Rev. 3.0, 04/02, page 364 of 1064 Asserted Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0
,
,
,
 , , , ,  , DQM3 DQM2 DQM1 DQM0 Byte n 1 — — — Data 7–0 Asserted Word 2n 1 — — — Data 7–0 Asserted 2n+1 2 — — — Data 15–8 Asserted 4n 1 — — — Data 7–0 Asserted 4n+1 2 — — — Data 15–8 Asserted 4n+2 3 — — — Data 23–16 Asserted 4n+3 4 — — — Data 31–24 Asserted 8n 1 — — — Data 7–0 Asserted 8n+1 2 — — — Data 15–8 Asserted 8n+2 3 — — — Data 23–16 Asserted 8n+3 4 — — — Data 31–24 Asserted 8n+4 5 — — — Data 39–32 Asserted 8n+5 6 — — — Data 47–40 Asserted 8n+6 7 — — — Data 55–48 Asserted 8n+7 8 — — — Data 63–56 Asserted Longword Quadword Rev. 3.0, 04/02, page 365 of 1064 13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set for this area. A bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins MD4 and MD3. For details, see Memory Bus Width in section 13.1.5. When area 0 is accessed, the  signal is asserted. In addition, the
 signal, which can be used as , and write control signals  to , are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). When the burst ROM interface is used, the number of burst cycle transfer states is selected in the range 2 to 9 according to the number of waits. The read/write strobe signal address and the CS setup/hold time can be set, respectively, to 0 or 1 and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register. Area 1: For area 1, external address bits A28 to A26 are 001. SRAM, MPX, and byte control SRAM can be set for this area. A bus width of 8, 16, or 32 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected with bits A1SZ1 and A1SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16 or 32 bits. When area 1 is accessed, the  signal is asserted. In addition, the
 signal, which can be used as , and write control signals  to , are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3 register. Rev. 3.0, 04/02, page 366 of 1064 Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM interface is set, select 32 bit with the SZ bits in the MCR register. For details, see Memory Bus Width in section 13.1.5. When area 2 is accessed, the  signal is asserted. When SRAM interface is set, the
 signal, which can be used as , and write control signals  to , are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3 register. When synchronous DRAM interface is set, the
 and   signals, RD/
signal, and byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed.
,  , and data timing control, and address multiplexing control, can be set using the MCR register. Area 3: For area 3, external address bits A28 to A26 are 011. SRAM, MPX, DRAM, and synchronous DRAM, can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16 or 32 bits can be selected with the SZ bits in the MCR register. When synchronous DRAM interface is set, select 32 bit with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5. When area 3 is accessed, the  signal is asserted. When SRAM interface is set, the
 signal, which can be used as , and write control signals  to , are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). Rev. 3.0, 04/02, page 367 of 1064 The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the
 and   signals, RD/
signal, and byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed. When DRAM interface is set, the
 signal,   to   signals, and RD/
signal are asserted, and address multiplexing is performed.
,  , and data timing control, and address multiplexing control, can be set using the MCR register. Area 4: For area 4, physical address bits A28 to A26 are 100. SRAM, MPX, and byte control SRAM can be set to this area. A bus width of 8, 16, or 32 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected with bits A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16 or 32 bits. For details, see Memory Bus Width in section 13.1.5. When area 4 is accessed, the  signal is asserted, and the
 signal, which can be used as , and write control signals  to , are also asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3 register. Area 5: For area 5, external address bits A28 to A26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of 32 bit should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5. When area 5 is accessed with SRAM interface set, the  signal is asserted. In addition, the
 signal, which can be used as , and write control signals  to , are asserted. When a PCMCIA interface is connected, the  and  signals, the
 signal, which can be used Rev. 3.0, 04/02, page 368 of 1064 as , and the ,  , , and  signals, which can be used as , 
, 
, and
, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3 register. When a PCMCIA interface is used, the address  and  setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. Area 6: For area 6, external address bits A28 to A26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can be selected with bits A6SZ1 and A6SZ0 in BCR2. When MPX interface is set, a bus width of 32 bit should be selected with bits A6SZ1 and A6SZ0 in BCR2. When a PCMCIA interface is set, either 8 or 16 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. For details, see Memory Bus Width in section 13.1.5. When area 6 space is accessed with SRAM interface set, the  signal is asserted. In addition, the
 signal, which can be used as , and write control signals  to , are asserted. When a PCMCIA interface is connected, the  and   signals, the
 signal, which can be used as , and the ,  , , and  signals, which can be used as , 
, 
, and
, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A6W2 to A6W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (
). When the burst function is used, the number of burst cycle transfer states is determined in the range 2 to 9 according to the number of waits. Rev. 3.0, 04/02, page 369 of 1064 The read/write strobe signal address and  setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3 register. When a PCMCIA interface is used, the address  and   setup and hold times with respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in PCR is added to the number of waits set in WCR2. 13.3.3 SRAM Interface Basic Timing: The SRAM interface of the SH7751 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the SRAM timing of normal space accesses. A no-wait normal access is completed in two cycles. The  signal is asserted for one cycle to indicate the start of a bus cycle. The  signal is asserted on the T1 rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation period in case of access at minimum pitch. There is no access size specification when reading. The correct access address is output to the address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the  signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and Data Alignment. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not released during this transfer. Rev. 3.0, 04/02, page 370 of 1064 T1 T2 CKIO A25–A0 RD/ D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) SA: Single address DMA DA: Dual address DMA Figure 13.6 Basic Timing of SRAM Interface Rev. 3.0, 04/02, page 371 of 1064 Figures 13.7, 13.8, and 13.9 show examples of connection to 32-, 16-, and 8-bit data width SRAM. 128k × 8-bit SRAM SH7751 Series •••• A2 A0 •••• •••• I/O7 •••• D31 •••• •••• A16 •••• •••• A18 D24 I/O0 •••• D16 •••• A16 A0 •••• •••• D15 •••• •••• D23 D8 •••• •••• •••• •••• I/O7 D7 I/O0 D0 •••• •••• A16 I/O7 •••• •••• A0 I/O0 •••• •••• A16 A0 •••• •••• I/O7 I/O0 Figure 13.7 Example of 32-Bit Data Width SRAM Connection Rev. 3.0, 04/02, page 372 of 1064 128k × 8-bit SRAM SH7751 Series •••• A1 A0 I/O7 •••• •••• D15 •••• •••• A16 •••• •••• A17 I/O0 D8 •••• D0 A16 •••• •••• •••• D7 A0 •••• •••• I/O7 I/O0 Figure 13.8 Example of 16-Bit Data Width SRAM Connection Rev. 3.0, 04/02, page 373 of 1064 128k × 8-bit SRAM SH7751 Series •••• •••• A16 •••• •••• A16 D0 •••• I/O7 •••• D7 •••• A0 •••• A0 I/O0 Figure 13.9 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 13.2.5, Wait Control Register 2 (WCR2). The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 13.10. Rev. 3.0, 04/02, page 374 of 1064 T1 Tw T2 CKIO A25–A0 RD/ D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.10 SRAM Interface Wait Timing (Software Wait Only) Rev. 3.0, 04/02, page 375 of 1064 When software wait insertion is specified by WCR2, the external wait input
 signal is also sampled.
 signal sampling is shown in figure 13.11. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the
 signal has no effect if asserted in the T1 cycle or the first Tw cycle. The
 signal is sampled on the rising edge of the clock. T1 Tw Twe T2 CKIO A25–A0 RD/ (read) D31–D0 (read) (write) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by
 Signal) Rev. 3.0, 04/02, page 376 of 1064 Read-Strobe Negate Timing (Setting Only Possible in the SH7751R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register. When a byte control SRAM setting is made, AnRDH should be cleared to 0. TS1 T1 Tw Tw Tw Tw T2 TH1 TH2 CKIO A25–A0 RD/ * RD D31–D0 TS1: Setup wait WCR3.AnS (0 to 1) Tw: Access wait WCR2.AnW (0 to 15) TH1, TH2: Hold wait WCR3.AnH (0 to 3) Note: * When AnRDH is set to 1 Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) Rev. 3.0, 04/02, page 377 of 1064 13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM interface. The DRAM interface function can then be used to connect DRAM to the SH7751 Series. 16 or 32 bits can be selected as the interface data width. 2-CAS 16-bit DRAMs can be connected, since   is used to control byte access. Signals used for connection are ,
,   to  , and RD/
.   to   are not used when the data width is 16 bits. In addition to normal read and write access modes, fast page mode is supported for burst access. EDO mode, which enables the DRAM access time to be increased, is supported. 256k × 16-bit DRAM SH7751 Series A2 A0 RD/ D31 D16 •••• •••• I/O15 •••• •••• •••• •••• A8 •••• •••• A10 I/O0 •••• D0 •••• A8 •••• •••• D15 A0 •••• •••• I/O15 I/O0 Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev. 3.0, 04/02, page 378 of 1064 Address Multiplexing: When area 3 is designated as DRAM interface, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7751 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR. The relationship between the AMXEXT and AMX2–0 bits and address multiplexing is shown in table 13.14. The address output pins subject to address multiplexing are A17 to A1. The address signals output by pins A25 to A18 are undefined. Table 13.14 Relationship between AMXEXT and AMX2–0 Bits and Address Multiplexing AMXEXT AMX2 AMX1 AMX0 Number of Column Address Bits Output Timing 0 0 0 0 8 bits Setting 1 1 0 1 1 Other settings 0 0 9 bits 10 bits 11 bits 12 bits Reserved External Address Pins A1–A13 A14 A15 A16 A17 Column address A1–A13 A14 A15 A16 A17 Row address A9–A21 A22 A23 A24 A25 Column address A1–A13 A14 A15 A16 A17 Row address A10–A22 A23 A24 A25 A17 Column address A1–A13 A14 A15 A16 A17 Row address A11–A23 A24 A25 A16 A17 Column address A1–A13 A14 A15 A16 A17 Row address A12–A24 A25 A15 A16 A17 Column address A1–A13 A14 A15 A16 A17 Row address A13–A25 A14 A15 A16 A17 — — — — — — Rev. 3.0, 04/02, page 379 of 1064 Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.14. Tpc is the precharge cycle, Tr the
 assert cycle, Tc1 the   assert cycle, and Tc2 the read data latch cycle. Tr1 Tr2 Tc1 Tc2 Tpc CKIO Address Row Column RD/ D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Notes: IO : DACK device SA : Single address DMA transfer DA : Dual address DMA transfer The DACK is in the high-active setting For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.14 Basic DRAM Access Timing Rev. 3.0, 04/02, page 380 of 1064 Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.15. Additional Tpc cycles (cycles used to secure the
 precharge time) can be inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
 assertion to   assertion can be set to between 2 and 5 by inserting Trw cycles by means of the RCD bit in MCR. Also, the number of cycles from   assertion to the end of the access can be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2. Tr1 Tr2 Trw Tc1 Tcw Tc2 Tpc Tpc CKIO Address Row Column RD/ D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.15 DRAM Wait State Timing Rev. 3.0, 04/02, page 381 of 1064 Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. Normal access or burst access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The timing for burst access using fast page mode is shown in figure 13.16. If the access size exceeds the set bus width, burst access is performed. In a 32-byte transfer, the first access comprises a longword that includes the data requiring access. The remaining accesses are performed on 32-byte boundary data that includes the relevant data. In burst transfer, wraparound writing is performed for 32-byte data. Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tpc CKIO Address Row c1 c2 c8 RD/ D31–D0 (read) d1 D31–D0 (write) d1 d2 d2 d8 d8 DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.16 DRAM Burst Access Timing Rev. 3.0, 04/02, page 382 of 1064 EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the   signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the   signal is asserted while the
 signal is asserted, even if the   signal is negated, data is output to the data bus until the   signal is next asserted. In the SH7751 Series, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM. When EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in figure 13.17, and burst access in figure 13.18. CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in the MCR register. Tr1 Tr2 Tc1 Tc2 Tce Tpc CKIO Address Row Column RD/ D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) Rev. 3.0, 04/02, page 383 of 1064 Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce Tpc CKIO Address Row c1 c2 c8 RD/ D31–D0 (read) d1 d2 d8 DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.18 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7751 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which
 remains asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM
 assert time, the refresh cycle must be decreased to or below the maximum value of tRAS. In RAS down mode, in the event of an access to an address with a different row address, an access to a different area, a refresh request, or a bus release request,
 is negated and the necessary operation is performed. When DRAM access is resumed after this, since this is the start of RAS down mode, the operation starts with row address output. Timing charts are shown in figures 13.19 (1), (2), (3), and (4). Rev. 3.0, 04/02, page 384 of 1064 Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 CKIO Row Address c1 c2 c8 RD/ D31–D0 (read) d1 D31–D0 (write) d1 d2 d8 d2 d8 DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev. 3.0, 04/02, page 385 of 1064 Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 CKIO Address c1 c2 c8 RD/ End of RAS down mode D31–D0 (read) d1 D31–D0 (write) d1 d2 d2 d8 d8 DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev. 3.0, 04/02, page 386 of 1064 Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce CKIO Row Address c1 c2 c8 RD/ D31–D0 (read) d1 d2 d8 DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev. 3.0, 04/02, page 387 of 1064 Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce CKIO c1 Address c2 c8 RD/ End of RAS down mode D31–D0 (read) d1 d2 DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev. 3.0, 04/02, page 388 of 1064 d8 Refresh: The bus state controller includes a function for controlling DRAM refreshing. Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported.
CAS-before-RAS Refresh When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits CKS2–CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and the   pin goes high. If the SH7751 Series external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.20 shows the operation of CAS-before-RAS refreshing. RTCNT cleared to 0 when RTCNT = RTCOR RTCNT value RTCOR-1 Time H'00000000 RTCSR.CKS2–0 Refresh request External bus = 000 ≠ 000 Refresh request cleared by start of refresh cycle CAS-before-RAS refresh cycle Figure 13.20 CAS-Before-RAS Refresh Operation Figure 13.21 shows the timing of the CAS-before-RAS refresh cycle. The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in MCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting of bits TRC2–TRC0 in MCR. Rev. 3.0, 04/02, page 389 of 1064 TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc CKIO A25–A0 RD/ D31–D0 Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)
Self-Refresh The self-refreshing supported by the SH7751 Series is shown in figure 13.22. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR. DRAMs include low-power products (L versions) with a long refresh cycle time (for example, the HM51W4160AL L version has a refresh cycle of 1024 cycles/128 ms compared with 1024 cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as for the normal version is requested only in the case of refreshing immediately following selfrefreshing. To ensure efficient DRAM refreshing, therefore, processing is needed to generate an overflow interrupt and restore the refresh cycle to the proper value, after CAS-before-RAS refreshing has been performed following self-refreshing of an L-version DRAM, using the OVF, OVIE, and LMTS bits in RTCSR and the refresh controller’s refresh count register (RFCR). The necessary procedure is as follows. Rev. 3.0, 04/02, page 390 of 1064 1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is generated. b. Re-set the refresh counter count cycle to the requested short cycle (e.g. 1024 cycles/16 ms), set refresh controller overflow interruption, and clear the refresh controller’s refresh count register (RFCR) to 0. c. Set self-refresh mode. By using this procedure, the refreshing immediately following a self-refresh will be performed in a short cycle, and when adequate refreshing ends, an interrupt is generated and the setting can be restored to the original refresh cycle. CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. When the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the
 and   signals become high-impedance or continue to be output can be controlled by the HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.
Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the   pin is negated (driven high). Therefore, normal refreshing can be performed by having the   pin monitored by a bus master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7751 Series. Rev. 3.0, 04/02, page 391 of 1064 TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc CKIO A25–A0 RD/ D63–D0 Figure 13.22 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus state controller does not perform any special operations for a power-on reset, the necessary poweron sequence must be carried out by the initialization program executed after a power-on reset. Rev. 3.0, 04/02, page 392 of 1064 13.3.5 Synchronous DRAM Interface Direct Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the  signal, it can be connected to external memory space areas 2 and 3 using
 and other control signals in common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 3 is synchronous DRAM interface; if set to 011, areas 2 and 3 are both synchronous DRAM interface. The SH7751 Series supports burst read and burst write operations with a burst length of 4 as a synchronous DRAM operating mode. The data bus width is 32 bit, and the SZ size bits in MCR must be set to 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache fill/copy-back cycle. In write-through area write operations and noncacheable area read/write operations, 16-byte data is read even in a single read because accessing synchronous DRAM is by burst-length 4 burst read/write operations. 16-byte data transfer is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. In the SH7751R, an 8-burst-length burst read/burst write mode is also supported as a synchronous DRAM operating mode. The data bus width is 32 bits, and the SZ size bits in MCR must be set to 11. Burst enable bit BE in MCR is ignored, and a 32-byte burst transfer is performed in a cache fill/copy-back cycle. For write-through area writes and non-cacheable area reads/writes, synchronous DRAM is accessed with an 8-burst-length burst read/write, and therefore 32 bytes of data are read even in the case of a single read. In the case of a single write, 32-byte data transfer is performed but DQMn is not asserted in the case of an unnecessary data transfer. For a description of the case where an 8-burst-length setting is made, see section 13.3.6, Burst ROM Interface. For information on the burst length, see section 13.2.10, Synchronous DRAM Mode Register (SDMR), and section 13.3.5, Power-On Sequence. The control signals for connection of synchronous DRAM are
,  , RD/
,  or , DQM0 to DQM3, and CKE. All the signals other than  and  are common to all areas, and signals other than CKE are valid and latched only when  or  is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low) when the frequency is changed, when the clock is unstable after the clock supply is stopped and restarted, or when self-refreshing is performed, and is always asserted (high) at other times. Commands for synchronous DRAM are specified by
,  , RD/
, and specific address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register setting (MRS). Byte specification is performed by DQM0 to DQM3. A read/write is performed for the byte for which the corresponding DQM signal is low. When the bus width is 32 bits, in big-endian mode DQM3 specifies an access to address 4n, and DQM0 specifies an access to address 4n + 3. In Rev. 3.0, 04/02, page 393 of 1064 little-endian mode, DQM3 specifies an access to address 4n + 3, and DQM0 specifies an access to address 4n. Figure 13.23 shows examples of the connection of 16M  16-bit synchronous DRAMs. SH7751 Series A11–A2 CKIO CKE RD/ D31–D16 DQM3 DQM2 512k × 16-bit × 2-bank synchronous DRAM A9–A0 CLK CKE I/O15–I/O0 DQMU DQML A9–A0 CLK CKE D15–D0 DQM1 DQM0 I/O15–I/O0 DQMU DQML Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2– AMX0 in MCR. Table 13.15 shows the relationship between the address multiplex specification bits and the bits output at the address pins. See Appendix E, Synchronous DRAM Address Multiplexing Tables. The address signals output at address pins A25–A18, A1, and A0 are not guaranteed. When A0, the LSB of the synchronous DRAM address, is connected to the SH7751 Series, it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7751 Series, then connect pin A1 to pin A3. Rev. 3.0, 04/02, page 394 of 1064 Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2–AMX0 = 000, AMXEXT = 0) SH7751 Series Address Pin RAS Cycle Synchronous DRAM Address Pin CAS Cycle Function A13 A21 A21 A11 BANK select bank address A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used Not used Not used A0 Not used Not used Not used Burst Read: The timing chart for a burst read is shown in figure 13.24. In the following example it is assumed that two 512k  16-bit  2-bank synchronous DRAMs are connected, and a 32-bit data width is used. The burst length is 4. After the Tr cycle in which the ACTV command is output, a READ command is issued in the Tc1 cycle and, 4 cycles after that, a READA command is issued and read data is fetched on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle. In the SH7751 Series, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR, and commands are not issued for the synchronous DRAM during this interval. The example in figure 13.24 shows the basic cycle. To connect slower synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by bits RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Rev. 3.0, 04/02, page 395 of 1064 Figure 13.24 Basic Timing for Synchronous DRAM Burst Read Rev. 3.0, 04/02, page 396 of 1064 Row Address Trw c1 Tc1 H/L Tc2 Tc3 Tc4/Td1 c1 c5 H/L Td2 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Row Row Precharge-sel Bank CKIO Tr c2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 Td7 c7 Td8 c8 Tpc In a synchronous DRAM cycle, the  signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command; after that, the data between 16-bit boundaries data that include the missing data are read in a wraparound way. The subsequently issued READA command reads the 16 bytes of data, which is the remainder of the data between 32-byte boundaries. Single Read: With the SH7751 Series, as synchronous DRAM is set to burst read/burst write mode, read data output continues after the required data has been read. To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7751 Series waits for the end of the synchronous DRAM operation. The  signal is asserted only in Td1. There are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1 to Td4. Since such empty cycles increase the memory access time, and tend to reduce program execution speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM specified as the source. Rev. 3.0, 04/02, page 397 of 1064 Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc CKIO Bank Row Precharge-sel Row H/L Address Row c1 RD/ DQMn D31–D0 (read) c1 CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.25 Basic Timing for Synchronous DRAM Single Read Burst Write: The timing chart for a burst write is shown in figure 13.26. In the SH7751 Series, a burst write occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4 cycles later, the WRITA command is issued. In the write cycle, the write data is output at the same time as the write command. In the case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the synchronous DRAM is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. Access starts from 16byte boundary data, and 32-byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data write cycle. Rev. 3.0, 04/02, page 398 of 1064 Figure 13.26 Basic Timing for Synchronous DRAM Burst Write Rev. 3.0, 04/02, page 399 of 1064 c1 c2 c3 c4 c5 c6 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO → memory) CKE BS D31–D0 (write) DQMn CASS RAS RD/WR CSn c5 c1 Tc7 Row Tc6 Address Tc5 H/L Tc4 H/L Tc3 Row Tc2 Precharge-sel Tc1 Row Trw Bank CKIO Tr c7 Tc8 c8 Trw1 Trw1 Tpc Single Write: The basic timing chart for write access is shown in figure 13.27. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In the case of a write with auto-precharge, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the synchronous DRAM until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. The SH7751 Series supports burst-length 4 burst read and burst write operations of synchronous DRAM. A wait cycle is therefore generated even with single write operations. Rev. 3.0, 04/02, page 400 of 1064 Tr Trw Tc1 Tc2 Tc3 Tc4 Trw1 Trw1 Tpc CKIO Bank Row Precharge-sel Row H/L Address Row c1 CSn RD/WR RAS CASS DQMn D31–D0 (write) c1 BS CKE DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.27 Basic Timing for Synchronous DRAM Single Write Rev. 3.0, 04/02, page 401 of 1064 RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command, in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRITA command. When RAS down mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance of the PRE command and the ACTV command is determined by bits TPC2–TPC0 in MCR. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. In this way, it is possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 13.28, a burst read cycle for the same row address in figure 13.29, and a burst read cycle for different row addresses in figure 13.30. Similarly, a burst write cycle without auto-precharge is shown in figure 13.31, a burst write cycle for the same row address in figure 13.32, and a burst write cycle for different row addresses in figure 13.33. When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs the byte specification. As a result, when the READ command is issued in figure 13.28, if the Tc cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be carried out. Therefore, the CAS latency should not be set to 1. When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 13.28 or 13.31, followed by repetition of the cycle in figure 13.29 or 13.32. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 13.30 or 13.33 is executed instead of that in figure 13.29 or 13.32. In RAS down mode, too, a PALL command is issued before a refresh cycle or before bus release due to bus arbitration. Rev. 3.0, 04/02, page 402 of 1064 Figure 13.28 Burst Read Timing Rev. 3.0, 04/02, page 403 of 1064 c3 c4 Td5 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ c5 c1 Row Address Td4 H/L c2 Td3 H/L c1 Tc3 Tc4/Td1 Td2 Row Tc2 Precharge-sel Tc1 Row Trw Bank CKIO Tr c5 Td6 c6 Td7 c7 Td8 c8 Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 CKIO Bank Precharge-sel H/L Address c1 H/L c5 RD/ DQMn D31–D0 (read) c1 c2 c3 c4 c5 c6 c7 CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.29 Burst Read Timing (RAS Down, Same Row Address) Rev. 3.0, 04/02, page 404 of 1064 c8 Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 3.0, 04/02, page 405 of 1064 Row Address c1 Tc1 H/L Tc2 Tc3 Tc4/Td1 c5 Td2 c1 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Row Trw Precharge-sel Tr Row Tpc Bank CKIO Tpr c2 H/L Td3 c3 Td4 c4 Td5 c5 Td6 c6 Td7 c7 Td8 c8 Figure 13.31 Burst Write Timing Rev. 3.0, 04/02, page 406 of 1064 Row Row Precharge-sel Address c1 c1 Tc1 H/L Tc2 c2 Tc3 c3 Tc4 c4 Tc6 H/L c5 c5 Tc5 c6 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO → memory) CKE D31–D0 (read) DQMn RD/ Row Trw Bank CKIO Tr Tc7 c7 Tc8 c8 Trw1 Trw1 Figure 13.32 Burst Write Timing (Same Row Address) Rev. 3.0, 04/02, page 407 of 1064 (Tnop) Tc2 c2 Tc3 c3 Tc4 ↑ Normal write ↓ Single address DMA H/L c1 c1 Tc1 c4 Tc6 H/L c5 c5 Tc5 c6 Tc7 c7 Tc8 c8 Trw1 Trw1 Note: The (Tnop) cycle is inserted only for SA-DMA. The DACKn signal is output as indicated by the solid line. In the case of a normal write, the (Tnop) cycle is deleted and the DACKn signal is output as indicated by the dotted line. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Tnop Trw1 c8 Trw1 c7 Tc8 c6 Tc7 c4 c3 c2 Row c1 c1 H/L Row Row H/L DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. c5 c5 H/L Tc6 Tc5 Tc4 Tc3 Tc2 Tc1 Trw Tr Tpc Tpr Figure 13.33 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally divided into two or four banks, after a READ or WRIT command is issued for one bank it is Rev. 3.0, 04/02, page 408 of 1064 possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch cycle, or during the data write cycle, and so shorten the access cycle. When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously. When an access is made to another row address and the bank is different, the PRE command or ACTV command can be issued during the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACTV command, depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus. Similarly, with a read access following a write access, or a write access following a write access, the PRE, ACTV, READ, or WRIT command is issued during the data write cycle for the preceding access; however, in the case of different row addresses in the same bank, a PRE command cannot be issued, and so in this case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits in MCR, after the end of the last data write cycle. Figure 13.34 shows a burst read cycle for a different bank and row address following a preceding burst read cycle. Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the event of an access to another area. Pipelined access is also discontinued in the event of a refresh cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are shown in table 13.16. In this table, “DMAC dual” indicates transfer in DMAC dual address mode, and “DMAC single”, transfer in DMAC single address mode. Table 13.16 Cycles in Which Pipelined Access Can Be Used Following Access CPU DMAC Dual DMAC Single Preceding Access Read Write Read Write Read Write CPU Read X X O X O O Write X X O X O O DMAC dual DMAC single Read X X X X X X Write O O O X O O Read O O O X O O Write O O O X O O O: Pipelined access possible X: Pipelined access not possible Rev. 3.0, 04/02, page 409 of 1064 b2 a7 a8 b1 c5_B H/L c1_B a6 H/L H/L c1_A Precharge-sel Address a2 a1 c5_A H/L a3 a4 a5 Tc1_B CKE D31–D0 (read) DQMn RD/ Bank CKIO Tc1_A Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev. 3.0, 04/02, page 410 of 1064 Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2– CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the refresh interval specification for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2–CKS0 setting last of all. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 13.36 shows the auto-refresh cycle timing. First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0 in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2– TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh cycle time specification (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual reset. When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is performed subsequent to area 3. RTCNT cleared to 0 when RTCNT = RTCOR RTCNT value RTCOR-1 Time H'00000000 RTCSR.CKS2–0 Refresh request External bus = 000 ≠ 000 Refresh request cleared by start of refresh cycle Auto-refresh cycle Figure 13.35 Auto-Refresh Operation Rev. 3.0, 04/02, page 411 of 1064 TRr1 TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc CKIO RD/ D63–D0 CKE Figure 13.36 Synchronous DRAM Auto-Refresh Timing
Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by bits TRC2–TRC0 in MCR. Self-refresh timing is shown in figure 13.37. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7751 Series standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In the case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared. Rev. 3.0, 04/02, page 412 of 1064 Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset. TRs1 TRs2 TRs3 TRs4 TRs5 Trc Trc Trc CKIO RD/ DQMn D63–D0 CKE Figure 13.37 Synchronous DRAM Self-Refresh Timing
Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the   pin is negated (driven high). Therefore, normal refreshing can be performed by having the   pin monitored by a bus master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7751 Series. Rev. 3.0, 04/02, page 413 of 1064 Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the
,  , and RD/
signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FF900000 + X for area 2 synchronous DRAM, and to address H'FF940000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/burst write, CAS latency 1 to 3, wrap type = sequential, and burst length 4, 8*, supported by the SH7751 Series, arbitrary data is written by byte-size access to the following addresses. Bus Width 32 32 4 8* CAS Latency Area 2 Area 3 1 H'FF900048 H'FF940048 2 H'FF900088 H'FF940088 3 H'FF9000C8 H'FF9400C8 1 H'FF90004C H'FF94004C 2 H'FF90008C H'FF94008C 3 H'FF9000CC H'FF9400CC Note: * SH7751R only The value set in MCR.MRSET is used to select whether a precharge all banks command or a mode register setting command is issued. The timing for the precharge all banks command is shown in figure 13.38(1), and the timing for the mode register setting command in figure 13.38(2). Before mode register, a 200 µs idle time (depending on the memory manufacturer) must be guaranteed after the power required for the synchronous DRAM is turned on. If the reset signal pulse width is greater than this idle time, there is no problem in making the precharge all banks setting immediately. First, a precharge all banks (PALL) command is issued in the TRp1 cycle by performing a write to address H'FF900000 + X or H'FF940000 + X while MCR.MRSET = 0. Next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is achieved automatically while various kinds of initialization are being performed after autorefresh setting, but a way of carrying this out more dependably is to change the RTCOR register value to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X. Rev. 3.0, 04/02, page 414 of 1064 Synchronous DRAM mode register setting should be executed once only after power-on reset and before synchronous DRAM access, and no subsequent changes should be made. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address RD/ D31–D0 CKE (High) Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL) Rev. 3.0, 04/02, page 415 of 1064 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address RD/ D31–D0 CKE (High) Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the 32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register.
Burst Read Figure 13.39 is the timing chart for burst-read operations. For the example shown below, we assume that two synchronous DRAMs of 512k  16 bits  2 banks are connected and are used with a 32-bit data width and a burst length of 8. Following the Tr cycle, during which an ACTV command is output, a READA command is issued during cycle Tc1. During the Td1 to Td8 cycles, the read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the cycle used to wait for auto-precharging, which is triggered by the READA command, to be completed in the synchronous DRAM. During this cycle, no new command that accesses the same bank can be issued. In this LSI, the number of Tpc cycles is determined Rev. 3.0, 04/02, page 416 of 1064 by the setting of the TPC2 to TPC0 bits of the MCR, and no command that operates on the synchronous DRAM is issued during these cycles. Figure 13.39 shows an example of the basic timing of a burst-read. To allow the connection of a lower-speed DRAM, the cycle’s period can be extended by the settings of the bits in WCR2 and MCR. The number of cycles from cycle Tr on which the ACTV command is output to cycle Tc1 on which the READA command is output can be specified by the RCD1 and RCD0 bits in MCR: the number of cycles is 2, 3, or 4 for the setting value of 1, 2, or 3, respectively. When two or more cycles are specified, the Trw cycle, which is for the issuing of NOP commands to the synchronous DRAM, is inserted between the Tr and Tc cycles. The number of cycles from cycle Tc1 on which the READA command is output until cycle Td1, in which the first part of the data to be read is received, can be set by the bits A2W2 to A2W0 and A3W2 to A3W0 of WCR2. These independently select a number of cycles between 1 and 5 for areas 2 and 3. Note that this number of cycles is equal to the number of CAS latency cycles of the synchronous DRAM. Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td4 Td3 Td2 Td5 Td6 Tpc Td8 Td7 CKIO Bank Row Precharge-sel Row H/L Address Row c1 RD/ DQMn D31–D0 (read) c1 c2 c3 c4 c5 c6 c7 c8 CKE DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) Rev. 3.0, 04/02, page 417 of 1064 In a cycle of access to synchronous DRAM, the  signal is asserted for one clock cycle at the beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between the 32-bit boundaries that include the missed data are first read; after that, the data between 32-byte boundaries that include the missed data are read in a wraparound way.
Burst Write Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI, a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the DMAC takes place. In a burst-write operation, a WRITA command that include auto precharging, is issued during the Tc1 cycle that follows the Tr cycle in which the ACTV command is output. During the write cycle, the data to be written is output along with the write command. With a write command that includes an auto precharge, precharging is of the relevant bank of the synchronous DRAM and takes place on completion of the write command, so no new command that accesses the same bank can be issued until precharging has been completed. For this reason, the Trwl cycles are added as a period of waiting for precharging to start after the write command has been issued. This is additional to the precharge-waiting cycle as used in read access. The Trwl cycles delay the issuing of new commands to the same bank. The setting of the TRWL2 to TRWL0 bits of MCR selects the number of Trwl cycles. The data between 32-byte boundaries are written in a wraparound way. Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 CKIO Bank Row Precharge-sel Row H/L Address Row c1 RD/ DQMn D31–D0 (write) c1 c2 c3 c4 c5 c6 c7 c8 CKE DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM Rev. 3.0, 04/02, page 418 of 1064 Tpc 13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a nonzero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.41. Two wait cycles are set. Basically, access is performed in the same way as for SRAM interface, but when the first cycle ends, only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, 16, or 32 with bits A0BST2–A0BST0, A5BST2–A5BST0, or A6BST2– A6BST0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. When 32-bit ROM is connected, 4 or 8 can be set.
 pin sampling is always performed when one or more wait states are set. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 13.42. In a burst ROM interface write operation is performed as SRAM interface. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.43 shows the timing when a burst ROM setting is made, and setup/hold is specified in WCR3. Rev. 3.0, 04/02, page 419 of 1064 T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO A25–A5 A4–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.41 Burst ROM Basic Access Timing Rev. 3.0, 04/02, page 420 of 1064 T1 Tw Twe TB2 TB1 Tw TB2 TB1 Tw TB2 TB1 Tw T2 CKIO A25–A5 A4–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.42 Burst ROM Wait Access Timing TS1 T1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 T2 TH1 CKIO A25–A5 A4–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.43 Burst ROM Wait Access Timing Rev. 3.0, 04/02, page 421 of 1064 13.3.7 PCMCIA Interface In the SH7751 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1). Figure 13.44 shows an example of PCMCIA card connection to the SH7751 Series. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between the SH7751 Series bus interface and the PCMCIA cards. As operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface. When the MMU is on, PCMCIA interface can be set in MMU page units, and there is a choice of 8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 3, Memory Management Unit (MMU), for details of the setting method. When the MMU is off, the setting of bits SA2 to SA0 of PTEA is always used for access. SA2 SA1 0 0 1 1 0 1 SA0 Description 0 Reserved (Setting prohibited) 1 Dynamic I/O bus sizing 0 8-bit I/O space 1 16-bit I/O space 0 8-bit common memory 1 16-bit common memory 0 8-bit attribute memory 1 16-bit attribute memory When the MMU is on, wait cycles in a bus access can be set in MMU page units. See section 3, Memory Management Unit (MMU), for details of the setting method. When the MMU is off, access is always performed according to the setting of the TC bit in PTEA. When TC is cleared to 0, bits A5W2–A5W0 in wait control register 2 (WCR2) and bits A5PCW1–A5PCW0, A5TED2– A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR) are selected. When TC is set to 1, bits A6W2–A6W0 in WCR2 and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in PCR are selected. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. AnPCW1–AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for Rev. 3.0, 04/02, page 422 of 1064 insertion specified by WCR2. AnTED2–AnTED0 can be set to a value from 0 to 15, enabling the address, ,  ,  , and
 setup times with respect to the
 and  signals to be secured. AnTEH2–AnTEH0 can also be set to a value from 0 to 15, enabling the address, ,  ,  , and
 data hold times with respect to the
 and  signals to be secured. Wait cycles between cycles are set with bits A5IW2–A5IW0 and A6IW2–A6IW0 in wait control register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5 or 6): when area 5 is accessed, bits A5IW2–A5IW0 are selected, and when area 6 is accessed, bits A6IW2–A6IW0 are selected. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not released during this operation. Rev. 3.0, 04/02, page 423 of 1064 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface Bus Width (Bits) Read/ Write Access Size Odd/ 1 (Bits)* Even 8 Read 8 16 Write 8 16 16 Read 8 16 Write 8 16 IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Even Don’t care — 1 0 0 Invalid Read data Odd Don’t care — 1 0 1 Invalid Read data Even Don’t care First 1 0 0 Invalid Lower read data Even Don’t care Second 1 0 1 Invalid Upper read data Odd Don’t care — — — — — — Even Don’t care — 1 0 0 Invalid Write data Odd Don’t care — 1 0 1 Invalid Write data Even Don’t care First 1 0 0 Invalid Lower write data Even Don’t care Second 1 0 1 Invalid Upper write data Odd Don’t care — — — — — — Even Don’t care — 1 0 0 Invalid Read data Odd Don’t care — 0 1 1 Read data Invalid Even Don’t care — 0 0 0 Upper read data Lower read data Odd Don’t care — — — — — — Even Don’t care — 1 0 0 Invalid Write data Odd Don’t care — 0 1 1 Write data Invalid Even Don’t care — 0 0 0 Upper write data Lower write data Odd Don’t care — — — — — Rev. 3.0, 04/02, page 424 of 1064 — Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont) Bus Width (Bits) Read/ Write Dynamic Read bus 2 sizing* Access Size Odd/ 1 (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 8 Even 0 — 1 0 0 Invalid Read data Odd 0 — 0 1 1 Read data Invalid Even 0 — 0 0 0 Upper read data Lower read data Odd 0 — — — — — — 8 Even 0 — 1 0 0 Invalid Write data Odd 0 — 0 1 1 Write data Invalid 16 Even 0 — 0 0 0 Upper write data Lower write data Odd 0 — — — — — — 8 Even 1 — 1 0 0 Invalid Read data Odd 1 First 0 1 1 Ignored Invalid Odd 1 Second 1 0 1 Invalid Read data Even 1 First 0 0 0 Invalid Lower read data Even 1 Second 1 0 1 Invalid Upper read data Odd 1 — — — — — — Even 1 — 1 0 0 Invalid Write data Odd 1 First 0 1 1 Invalid Write data Write data 16 Write Read 16 Write 8 16 Odd 1 Second 1 0 1 Invalid Even 1 First 0 0 0 Upper write data Lower write data Even 1 Second 1 0 1 Invalid Upper write data Odd 1 — — — — — — Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address incrementing performed automatically according to the bus width, until the transfer data size is reached. *2 PCMCIA I/O card interface only Rev. 3.0, 04/02, page 425 of 1064 A25–A0 A25–A0 D15–D0 D7–D0 RD/ /( ) /( ) D15–D0 DIR PC card (memory I/O) D15–D8 DIR SH7751 Series / ( ( ) ) ( Card detection circuit ) CD1, CD2 A25–A0 D7–D0 D15–D0 DIR D15–D8 PC card (memory I/O) DIR / Card detection circuit Figure 13.44 Example of PCMCIA Interface Rev. 3.0, 04/02, page 426 of 1064 CD1, CD2 Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA memory card interface, and figure 13.46 shows the wait timing for the PCMCIA memory card interface. Tpcm1 Tpcm2 CKIO A25–A0 RD/ (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.45 Basic Timing for PCMCIA Memory Card Interface Rev. 3.0, 04/02, page 427 of 1064 Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 REG RD/ (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.46 Wait Timing for PCMCIA Memory Card Interface Rev. 3.0, 04/02, page 428 of 1064 Common memory (64 MB) Access by CS5 wait controller Virtual address space Common memory 1 Access by CS6 wait controller Virtual address space External I/O addresses 1 kB page IO 1 IO 1 IO 2 Common memory 2 Card 1 on CS5 Attribute memory I/O space 1 I/O space 2 Attribute memory (64 MB) . . . IO 2 1 kB page Different virtual pages mapped to the same physical page Example of I/O spaces with different cycle times (less than 1 kB) I/O space (64 MB) Card 2 on CS6 . . . The page size can be 1 kB, 4 kB, 64 kB, or 1 MB. Example of PCMCIA interface mapping Figure 13.47 PCMCIA Space Allocation I/O Card Interface Timing: Figures 13.48 and 13.49 show the timing for the PCMCIA I/O card interface. When an I/O card interface access is made to a PCMCIA card, dynamic sizing of the I/O bus width is possible using the  pin. When a 16-bit bus width is set, if the  signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is also performed in the case of byte-size access to address 2n + 1. Figure 13.50 shows the basic timing for dynamic bus sizing. Rev. 3.0, 04/02, page 429 of 1064 Tpci1 Tpci2 CKIO A25–A0 RD/ (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.48 Basic Timing for PCMCIA I/O Card Interface Rev. 3.0, 04/02, page 430 of 1064 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 RD/ (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.49 Wait Timing for PCMCIA I/O Card Interface Rev. 3.0, 04/02, page 431 of 1064 Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w CKIO A25–A1 A0 RD/ ( ) (read) D15–D0 (read) ( ) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 3.0, 04/02, page 432 of 1064 13.3.8 MPX Interface If the MD6 pin is cleared to 0 in a power-on reset by means of the
 pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and MEMMODE, A4MPX, and A1MPX in BCR3. The MPX interface offers a multiplexed address/data type bus protocol, and permits easy connection to an external memory controller chip that uses a single 32-bit multiplexed address/data bus. A bus cycle consists of an address phase and a data phase, with address information output to D25–D0 and the access size output to D31– D29 in the address phase. The  signal is asserted for one cycle to indicate the address phase. The  signal is asserted at the rise of Tm1 and negated after the end of the last data transfer in the data phase. Therefore, a negation period does not occur in the case of minimum pitch access. The 
 signal is asserted at the rise of Tm1 and negated when the last data transfer cycle starts in the data phase. Therefore, an external device for the MPX interface must hold the address information and access size output in the address phase within itself, and peripheral function data input/output for the data phase. For details of access sizes and data alignment, see section 13.3.1, Endian/Access Size and Data Alignment. Values output to address pins A25–A20 are not guaranteed. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on 32-byte boundary data. If the access size exceeds the set bus width in this case, burst access is performed with a number of data cycles following one address output. The bus is not released during this period. D31 D30 0 0 1 1 X D29 Access Size 0 Byte 1 Word 0 Longword 1 Quadword X 32-byte burst X: Don’t care Rev. 3.0, 04/02, page 433 of 1064 SH7751 Series CKIO RD/ D31–D0 MPX device CLK I/O31–I/O0 Figure 13.51 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 bit should be specified in BCR2. For wait control, waits specified by WCR2 and wait insertion by means of the
 pin can be used. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to 0. Rev. 3.0, 04/02, page 434 of 1064 Tm1 Tmd1w Tmd1 CKIO / D31–D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 435 of 1064 Tm1 Tmd1w Tmd1w Tmd1 CKIO / D31–D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) Rev. 3.0, 04/02, page 436 of 1064 Tm1 Tmd1 CKIO / D31–D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 437 of 1064 Tm1 Tmd1w Tmd1w Tmd1 CKIO / D31–D0 A D0 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) Rev. 3.0, 04/02, page 438 of 1064 Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 439 of 1064 A Tmd1w Tmd1 D1 Tmd2 D2 Tmd3 D3 Tmd4 D4 Tmd5 D5 Tmd6 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (DA) RD/ D31–D0 / CKIO Tm1 D6 Tmd7 D7 Tmd8 D8 Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control) Rev. 3.0, 04/02, page 440 of 1064 A Tmd1w Tmd1 D1 Tmd2w Tmd2 D2 Tmd3 D3 Tmd7 Tmd8w D7 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (DA) RD/ D31–D0 / CKIO Tm1 Tmd8 D8 Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait) Rev. 3.0, 04/02, page 441 of 1064 A D1 Tmd1 D2 Tmd2 D3 Tmd3 D4 Tmd4 D5 Tmd5 D6 Tmd6 D7 Tmd7 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (DA) RD/ D31–D0 / CKIO Tm1 D8 Tmd8 Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control) Rev. 3.0, 04/02, page 442 of 1064 A Tmd1w D1 Tmd1 Tmd2w D2 Tmd2 D3 Tmd3 D7 Tmd7 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (DA) RD/ D31–D0 / CKIO Tm1 Tmd8w D8 Tmd8 Tm1 Tmd1w Tmd1 Tmd2 CKIO / D31–D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev. 3.0, 04/02, page 443 of 1064 Tm1 Tmd1w Tmd1w Tmd1 Tmd2 CKIO / D31–D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev. 3.0, 04/02, page 444 of 1064 Tm1 Tmd1 Tmd2 CKIO / D31–D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev. 3.0, 04/02, page 445 of 1064 Tm1 Tmd1w Tmd1w Tmd1 Tmd2 CKIO / D31–D0 A D0 D1 RD/ DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev. 3.0, 04/02, page 446 of 1064 Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 447 of 1064 A Tmd1w Tmd1 D1 Tmd2 D2 Tmd3 D3 Tmd4 D4 Tmd5 D5 Tmd6 Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. DACKn (DA) RD/ D31–D0 / CKIO Tm1 D6 Tmd7 D7 Tmd8 D8 D8 D7 D3 D2 D1 DACKn (DA) RD/ A D31–D0 / CKIO Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Tmd8 Tmd8w Tmd7 Tmd3 Tmd2 Tmd2w Tmd1 Tmd1w Tm1 Figure 13.65 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 448 of 1064 D8 D6 D5 D4 D3 D2 D1 DACKn (DA) RD/ A D31–D0 / CKIO Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. D7 Tmd8 Tmd7 Tmd6 Tmd5 Tmd4 Tmd3 Tmd2 Tmd1 Tm1 Figure 13.66 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 449 of 1064 D8 Tmd8 D3 D2 D1 DACKn (DA) RD/ A D31–D0 / CKIO Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. D7 Tmd8w Tmd7 Tmd3 Tmd2 Tmd2w Tmd1 Tmd1w Tm1 Figure 13.67 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 3.0, 04/02, page 450 of 1064 13.3.9 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte select strobe () in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB. Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are set to MPX mode, MPX mode has priority. The byte control SRAM interface write timing is the same as for the normal SRAM interface. In read operations, the  pin timing is different. In a read access, only the  signal for the byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the  signal, while negation is synchronized with the rise of the CKIO clock, using the same timing as the
 signal. 32-byte transfer is performed consecutively for a total of 32 bytes according to the set bus width. The first access is performed on the data for which there was an access request. The remaining accesses are performed in wrap-around fashion on the data at the 32-byte boundary. The bus is not released during this period. Figure 13.68 shows an example of byte control SRAM connection to the SH7751 Series, and figures 13.69 to 13.71 show examples of byte control SRAM read cycles. SH7751 Series 64k × 16-bit SRAM A18–A3 CSn RD RD/WR D31–D16 WE3 WE2 A15–A0 CS OE WE I/O15–I/O0 UB LB D15–D0 WE1 WE0 A15–A0 CS OE WE I/O15–I/O0 UB LB Figure 13.68 Example of 52-Bit Data Width Byte Control SRAM Rev. 3.0, 04/02, page 451 of 1064 T1 T2 CKIO A25–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 3.0, 04/02, page 452 of 1064 T1 Tw T2 CKIO A25–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 3.0, 04/02, page 453 of 1064 T1 Tw Twe T2 CKIO A25–A0 RD/ D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 454 of 1064 13.3.10 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write, and if there is a possibility of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. Wait cycle insertion consists of inserting idle cycles between access cycles, as shown in section 13.2.5, Wait Control Register 1 (WCR1). When the SH7751 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7751 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed. If there is originally space between accesses, according to the setting of bits AnIW2–AnIW0 (n = 0 to 6) in WCR1, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. When bus arbitration is performed, the bus is released after waits are inserted between cycles. In single address mode DMA transfer, when data transfer is performed from an I/O device to memory the data on the bus is determined by the speed of the I/O device. With a low-speed I/O device, an inter-cycle idle wait equivalent to the output buffer turn-off time must be inserted. Even with high-speed memory, when DMA transfer is considered, it may be necessary to insert an intercycle wait to adjust to the speed of a low-speed device, preventing the memory from being used at full speed. Bits DMAIW2–DMAIW0 in wait control register 1 (WCR1) allow an inter-cycle wait setting to be made when transferring data from an I/O device to memory using single address mode DMA transfer. From 0 to 15 waits can be inserted. The number of waits specified by DMAIW2– DMAIW0 are inserted in single address DMA transfers to all areas. In dual address mode DMA transfer, the normal inter-cycle wait specified by AnIW2–AnIW0 (n = 0 to 6) is inserted. Rev. 3.0, 04/02, page 455 of 1064 T1 T2 Twait T1 T2 Twait T1 T2 A25–A0 RD/ D31–D0 Area m space read Area n space read Area m inter-access wait specification Area n space write Area n inter-access wait specification Figure 13.72 Waits between Access Cycles Rev. 3.0, 04/02, page 456 of 1064 13.3.11 Bus Arbitration The SH7751 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each time an external bus cycle occurs, and the bus is released again at the end of the access. In partialsharing master mode, only area 2 is shared with external devices; slave mode is in effect for area 2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is determined by an external circuit. Master mode and slave mode can be specified by the external mode pins. Partial-sharing master mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the high-impedance state when not being held. In partial-sharing master mode, the bus is constantly driven, and therefore an external buffer is necessary for connection to the master bus. In master mode, it is possible to connect an external device that issues bus requests. Instead of a slave mode chip. In the following description, an external device that issues bus requests is also referred to as a slave. The SH7751 Series has three internal bus masters: the CPU, DMAC, and PCIC. When synchronous DRAM or DRAM is connected and refresh control is performed, refresh requests constitute a fourth bus master. In addition to these are bus requests from external devices in master mode. If requests occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the DMAC, and the CPU. See section 13.3.15, Notes on Usage. To prevent incorrect operation of connected devices when the bus is transferred between master and slave, all bus control signals are negated before the bus is released. When mastership of the bus is received, also, bus control signals begin driving the bus from the negated state. Since signals are driven to the same value by the master and slave exchanging the bus, output buffer collisions can be avoided. By turning off the output buffer on the side releasing the bus, and turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect operation due to external noise in the high-impedance state. Bus transfer is executed between bus cycles. When the bus release request signal (
) is asserted, the SH7751 Series releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal ( ). Rev. 3.0, 04/02, page 457 of 1064 However, bus release is not performed during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is not performed between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When 
 is negated,   is negated and use of the bus is resumed. See appendix D, Pin Functions, for the pin states when the bus is released. When a refresh request is generated, the SH7751 Series performs a refresh operation as soon as the currently executing bus cycle ends. However, refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. Refresh operations are also deferred in the bus-released state. If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued before a refresh cycle occurs or before the bus is released by bus arbitration. As the CPU in the SH7751 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7751 Series. When writing from the CPU, an external write cycle is generated when write-through has been set for the cache in the SH7751 Series, or when an access is made to a cache-off area. There is consequently a delay until the bus is returned. When the SH7751 Series wants to take back the bus in response to an internal memory refresh request, it negates  . On receiving the   negation, the device that asserted the external bus release request negates 
 to release the bus. The bus is thereby returned to the SH7751 Series, which then carries out the necessary processing. Rev. 3.0, 04/02, page 458 of 1064 CKIO Asserted for at least 2 cycles* Negated within 2 cycles HiZ A25–A0 HiZ HiZ RD/ HiZ HiZ Master mode device access / Asserted for at least 2 cycles / Negated within 2 cycles HiZ A25–A0 HiZ HiZ RD/ HiZ HiZ HiZ D31–D0 (read) Slave mode device access Master access Slave access Master access Note: * For the SH7751, refer to the Usage Note in section 13.3.15. Figure 13.73 Arbitration Sequence Rev. 3.0, 04/02, page 459 of 1064 13.3.12 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (
) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal ( ) as soon as the currently executing bus cycle ends. If a bus release request due to a refresh request has not been issued, on receiving the 
 negation (high level) indicating that the slave has released the bus, the processor negates (drives high) the   signal and resumes use of the bus. If a bus request is issued due to a memory refresh request in the bus-released state, the processor negates the bus use permission signal ( ), and on receiving the 
 negation indicating that the slave has released the bus, resumes use of the bus. When the bus is released, all bus interface related output signals and input/output signals go to the high-impedance state, except for the synchronous DRAM interface CKE signal and bus arbitration   signal, and DACK0 and DACK1 which control DMA transfers. With DRAM, the bus is released after precharging is completed. With synchronous DRAM, also, a precharge command is issued for the active bank and the bus is released after precharging is completed. The actual bus release sequence is as follows. First, the bus use permission signal is asserted in synchronization with the rising edge of the clock. The address bus and data bus go to the high-impedance state in synchronization after this   assertion. At the same time, the bus control signals (, ,
, ,
, RD/
,  , and  ) go to the high-impedance state. These bus control signals are negated no later than one cycle before going to high-impedance. Bus request signal sampling is performed on the rising edge of the clock. The sequence for re-acquiring the bus from the slave is as follows. As soon as 
 negation is detected on the rising edge of the clock,   is negated and from next rising edge of the clock, bus control signal driving is started. Driving of the address bus and data bus starts at the next rising edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and data signals are driven. In order to reacquire the bus and start execution of a refresh operation or bus access, the signal must be negated for at least two cycles. 
 If a refresh request is generated when   has been asserted and the bus has been released, the   signal is negated even while the 
 signal is asserted to request the slave to relinquish the bus. When the SH7751 Series is used in master mode, consecutive bus accesses may be Rev. 3.0, 04/02, page 460 of 1064 attempted to reduce the overhead due to arbitration in the case of a slave designed independently by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the   signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the bus-released state is established and the bus arbitration sequence is started from the reset vector fetch. To acquire the bus, the slave device asserts (drives low) the 
 signal in synchronization with the rising edge of the clock. The bus use permission   signal is sampled for assertion (low level) in synchronization with the rising edge of the clock. When   assertion is detected, the bus control signals are driven at the negated level after two cycles. The bus cycle is started at the next rising edge of the clock. The last signal negated at the end of the access cycle is synchronized with the rising edge of the clock. When the bus cycle ends, the 
 signal is negated and the release of the bus is reported to the master. On the next rising edge of the clock, the control signals are set to high-impedance. In order for the slave mode processor to begin access, the   signal must be asserted for at least two cycles. For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of precharging, as in the case of the master. Refresh control is left to the master mode device, and any refresh control settings made in slave mode are ignored. Do not use DRAM/synchronous DRAM RAS down mode in slave mode. Synchronous DRAM mode register settings should be made by the master mode device. Do not use the DMAC’s DDT mode in slave mode. 13.3.14 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. Before DRAM or synchronous DRAM is used, initialization operations must be carried out. Responsibility must also be assigned when a standby operation is performed to implement the power-down state. The design of the SH7751 Series provides for all control, including initialization, refreshing, and standby control, to be carried out by the master mode device. Rev. 3.0, 04/02, page 461 of 1064 If the SH7751 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the 
 enable bit (BCR1.BREQEN) is set to 1. To ensure that the slave processor does not access memory requiring initialization before use, such as DRAM and synchronous DRAM, until initialization is completed, write 1 to the 
 enable bit after initialization ends. Before setting self-refresh mode in standby mode, etc., write 0 to the 
 enable bit to invalidate the 
 signal from the slave. Write 1 to the 
 enable bit only after the master has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode. 13.3.15 Notes on Usage Refresh: Auto refresh operations stop when a transition is made to standby mode or deep-sleep mode. If the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode or deep-sleep mode. Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master mode does not release bus privileges. In systems performing bus arbitration, make the transition to standby mode or deep-sleep mode only after setting the bus privilege release enable bit (BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or deep-sleep mode. Simultaneous Use of Refresh and Bus Arbitration: With the SH7751, when performing bus arbitration using the external device and 
 signal, the following two failures may occur.
When a 
 signal is input from the external device while using DMA transfer or target transfer by the PCIC, and DRAM/synchronous DRAM is set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), bus arbitration may not be performed correctly and this LSI may hang up.
When a 
 signal is input from the external device while DRAM/synchronous DRAM is set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the   signal (low-level) in response to the 
 signal may be for only one cycle at CKIO. Both above phenomena can be avoided by not using the 
 signal. If the 
 signal is to be used, disable refresh operations during normal operation. If refresh operations are required, carry them out at one time with the BREQEN bit in BCR1 cleared to 0. Rev. 3.0, 04/02, page 462 of 1064 Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview The SH7751 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (DMA transfer end notification), external memories, memorymapped external devices, and on-chip peripheral modules (TMU, RTC, SCI, SCIF, CPG, and INTC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip. When using the SH7751R, see section 14.6, Configuration of the DMAC (SH7751R), section 14.7, Register Descriptions (SH7751R), and section 14.8, Operation (SH7751R). 14.1.1 Features The DMAC has the following features.
Four channels (SH7751), eight channels (SH7751R)
Physical address space
Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
Maximum of 16 M (16,777,216) transfers
Choice of single or dual address mode  Single address mode: Either the transfer source or the transfer destination (external device) is accessed by a DACK signal while the other is accessed by address. One data transfer is completed in one bus cycle.  Dual address mode: Both the transfer source and transfer destination are accessed by address. Values set in DMAC internal registers indicate the accessed address for both the transfer source and the transfer destination. Two bus cycles are required for one data transfer.
Choice of bus mode: cycle steal mode or burst mode
Two types of DMAC channel priority ranking:  Fixed priority mode: Channel priorities are permanently fixed.  Round robin mode: Sets the lowest priority for the channel that last received an execution request.
An interrupt request can be sent to the CPU on completion of the specified number of transfers. Rev. 3.0, 04/02, page 463 of 1064 
The following kinds of DMAC transfer activation requests are provided  External request (1) Normal DMA mode Two
 pins. Low level detection or falling edge detection can be specified. External requests can only be accepted on channel 0 and channel 1. (2) On-demand data transfer mode (DDT mode) The SH7551 performs interfacing between an external device and the DMAC using the
, , ,
 , ID [1:0], and D[31:0] pins. The SH7551R performs interfacing between an external device and the DMAC using the
, , ,
 , ID [2:0], and D[31:0] pins. External requests can be accepted on all eight channels. Channel 0 does not have a request queue, but channels 1 to 3 in the SH7751 and channels 1 to 7 in the SH7751R each have four request queues.  On-chip peripheral modules Transfer requests from the SCI, SCF, and TMU. These can be accepted on all channels.  Auto-request A transfer request is generated automatically within the DMAC.
Channel functions: Transfer modes that can be set are different for each channel. (1) Normal DMA mode • Channel 0: Single or dual address mode. External requests are accepted. • Channel 1: Single or dual address mode. External requests are accepted. • Channel 2: Dual address mode only • Channel 3: Dual address mode only • Channel 4 (SH7751R only): Dual address mode only • Channel 5 (SH7751R only): Dual address mode only • Channel 6 (SH7751R only): Dual address mode only • Channel 7 (SH7751R only): Dual address mode only (2) DDT mode • Channel 0: Single or dual address mode. External requests are accepted. • Channel 1: Single or dual address mode. External requests are accepted. • Channel 2: Single or dual address mode. External requests are accepted. • Channel 3: Single or dual address mode. External requests are accepted. • Channel 4 (SH7751R only): Single or dual address mode. External requests are accepted. • Channel 5 (SH7751R only): Single or dual address mode. External requests are accepted. • Channel 6 (SH7751R only): Single or dual address mode. External requests are accepted. Rev. 3.0, 04/02, page 464 of 1064 • Channel 7 (SH7751R only): Single or dual address mode. External requests are accepted. In DDT mode, data transfer is carried out by the SH7751 using the
, , ,
 K, ID [1:0], and D[31:0] signals to perform handshaking between the external device and the DMAC, and data transfer is carried out by the SH7751R using the
, , ,
 , ID [2:0], and D[31:0] signals to perform handshaking between the external device and the DMAC.
Request-queue clear for each channel (SH7751R only) Request queues can be cleared on a channel-by-channel basis in either of the following two ways.  Clearing a request queue by DTR format The request queues of the relevant channel are cleared when it receives DTR.SZ = 110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1–8].  Using software to clear the request queue The request queues of the relevant channel are cleared by writing a 1 to the CHCRn.QCL bit (request-queue clear bit) of each channel. Note: * DTR.COUNT [7:4] (DTR [23:20]): Sets the port as not used. Rev. 3.0, 04/02, page 465 of 1064 14.1.2 Block Diagram (SH7751) Figure 14.1 shows a block diagram of the DMAC. On-chip peripheral module Internal bus Peripheral bus DMAC module Count control SARn Register control DARn DMATCRn Activation control CHCRn DMAOR Request priority control TMU SCI, SCIF DACK0, DACK1 DRAK0, DRAK1 , D[31:0] ID[1:0] External bus 32B data buffer Bus state controller DMAOR: SARn: DMAC operation register DMAC source address register DARn: DMAC destination address register DMATCRn: DMAC transfer count register CHCRn: DMAC channel control register (n: 0 to 3) External address/on-chip peripheral module address Bus interface 4 DDT module DTR command buffer CH0 CH1 CH2 CH3 DBREQ DDTMODE BAVL DDTD Request controller 48 bits id[1:0] tdack Figure 14.1 Block Diagram of DMAC Rev. 3.0, 04/02, page 466 of 1064 SAR0, DAR0, DMATCR0, CHCR0 only dreq0-3 14.1.3 Pin Configuration (SH7751) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name 0 DMA transfer request
 acceptance Abbreviation I/O Function
 Input DMA transfer request input from external device to channel 0 DRAK0 Output Acceptance of request for DMA transfer from channel 0 to external device confirmation Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request
 acceptance DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device
 Input DMA transfer request input from external device to channel 1 DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external device confirmation Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device Rev. 3.0, 04/02, page 467 of 1064 Table 14.2 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation
 (
)  I/O Function Input Data bus release request from external device for DTR format input Output Data bus release notification (DRAK0) Transfer request signal Data bus can be used 2 cycles after  is asserted  (
) Input If asserted 2 cycles after  assertion, DTR format is sent Only  asserted: DMA request
 and  asserted simultaneously: Direct request to channel 2 DMAC strobe 
 Output Reply strobe signal for external device from DMAC Output Notification of channel number to external device at same time as 
 output (DACK0) Channel number notification ID [1:0] (DRAK1, DACK1) (ID [1] = DRAK1, ID [0] = DACK1) 14.1.4 Register Configuration (SH7751) Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers are allocated to each channel, and an additional control register is shared by all four channels. Table 14.3 DMAC Registers Channel Name Abbreviation Read/ Write Area 7 Initial Value P4 Address Address 0 DMA source address register 0 SAR0 R/W Undefined H'FFA00000 H'1FA00000 32 DMA destination address register 0 DAR0 R/W Undefined H'FFA00004 H'1FA00004 32 DMA transfer count register 0 DMATCR0 R/W Undefined H'FFA00008 H'1FA00008 32 DMA channel control register 0 CHCR0 Rev. 3.0, 04/02, page 468 of 1064 R/W* Access Size H'00000000 H'FFA0000C H'1FA0000C 32 Table 14.3 DMAC Registers (cont) Channel Name Abbreviation Read/ Write Area 7 Initial Value P4 Address Address 1 DMA source address register 1 SAR1 R/W Undefined H'FFA00010 H'1FA00010 32 DMA destination address register 1 DAR1 R/W Undefined H'FFA00014 H'1FA00014 32 DMA transfer count register 1 DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32 DMA channel control register 1 CHCR1 R/W* H'00000000 H'FFA0001C H'1FA0001C 32 DMA source address register 2 SAR2 R/W Undefined H'FFA00020 H'1FA00020 32 DMA destination address register 2 DAR2 R/W Undefined H'FFA00024 H'1FA00024 32 DMA transfer count register 2 DMATCR2 R/W Undefined H'FFA00028 H'1FA00028 32 DMA channel control register 2 CHCR2 R/W* H'00000000 H'FFA0002C H'1FA0002C 32 DMA source address register 3 SAR3 R/W Undefined H'FFA00030 H'1FA00030 32 DMA destination address register 3 DAR3 R/W Undefined H'FFA00034 H'1FA00034 32 DMA transfer count register 3 DMATCR3 R/W Undefined H'FFA00038 H'1FA00038 32 DMA channel control register 3 CHCR3 R/W* H'00000000 H'FFA0003C H'1FA0003C 32 DMAOR R/W* H'00000000 H'FFA00040 H'1FA00040 32 2 3 Com- DMA operation mon register Access Size Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. * Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. Rev. 3.0, 04/02, page 469 of 1064 14.2 Register Descriptions 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 0 Initial value: — ············································· — R/W ············································· R/W ············································· R/W: DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next source address. In single address mode, the SAR value is ignored when a device with DACK has been specified as the transfer source. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode, sleep mode, and deep sleep mode. Rev. 3.0, 04/02, page 470 of 1064 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bit: 23 0 ············································· Initial value: R/W: — ············································· — R/W ············································· R/W DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a counter feedback function, and during a DMA transfer they indicate the next destination address. In single address mode, the DAR value is ignored when a device with DACK has been specified as the transfer destination. Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode, sleep mode, and deep sleep mode. Notes: 1. When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with the setting of bit 0, bits 1–0, bits 2–0, or bits 4–0, respectively. If an address specification that ignores boundary considerations is made, the DMAC will detect an address error and halt operation on all channels (DMAOR: address error flag AE = 1). The DMAC will also detect an address error and halt if an area 7 address is specified in an external data bus transfer, or if the address of a nonexistent on-chip peripheral module is specified. 2. External addresses are 29 bits in length. SAR[31:29] and DAR[31:29] are not used in DMA transfer, and it is recommended that they both be set to 000. Rev. 3.0, 04/02, page 471 of 1064 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: 31 30 29 28 27 26 25 24 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Initial value: R/W: Bit: Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers that specify the transfer count for the corresponding channel (byte count, word count, longword count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the remaining number of transfers is shown. Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written with 0. The initial value of these registers after a power-on or manual reset is undefined. They retain their values in standby mode, sleep mode, and deep sleep mode. Rev. 3.0, 04/02, page 472 of 1064 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: Initial value: R/W: Bit: 31 30 29 28 27 26 25 24 SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 — — — — DS RL AM AL Initial value: 0 0 0 0 — — — — R/W: R R R R R/W (R/W) R/W (R/W) Bit: 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TM TS2 TS1 TS0 — IE TE DE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/(W) R/W Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag. The RL, AM, AL, and DS bits may be absent, depending on the channel. DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA interface, see section 13.3.7, PCMCIA Interface. Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot be modified (for write, a write value of 0 should always be used) and are always read as 0. These registers are initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode, sleep mode, and deep sleep mode. Rev. 3.0, 04/02, page 473 of 1064 Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 31: SSA2 Bit 30: SSA1 Bit 29: SSA0 Description 0 0 0 Reserved in PCMCIA access 1 Dynamic bus sizing I/O space 0 8-bit I/O space 1 16-bit I/O space 0 8-bit common memory space 1 16-bit common memory space 0 8-bit attribute memory space 1 16-bit attribute memory space 1 1 0 1 (Initial value) Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control for PCMCIA interface area access. Bit 28: STC Description 0 CS5 space wait cycle selection (Initial value) Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR), are selected 1 CS6 space wait cycle selection Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Rev. 3.0, 04/02, page 474 of 1064 Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description 0 0 0 Reserved in PCMCIA access 1 Dynamic bus sizing I/O space 0 8-bit I/O space 1 16-bit I/O space 0 8-bit common memory space 1 16-bit common memory space 0 8-bit attribute memory space 1 16-bit attribute memory space 1 1 0 1 (Initial value) Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for PCMCIA interface area access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. Bit 24: DTC Description 0 CS5 space wait cycle selection (Initial value) Settings of bits A5W2–A5W0 in wait control register 2 (WCR2), and bits A5PCW1–A5PCW0, A5TED2–A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR), are selected 1 CS6 space wait cycle selection Settings of bits A6W2–A6W0 in wait control register 2 (WCR2), and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and A6TEH2–A6TEH0 in the PCMCIA control register (PCR), are selected Note: For details, see section 13.3.7, PCMCIA Interface. Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0. Rev. 3.0, 04/02, page 475 of 1064 Bit 19—
 Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the
 pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3. Bit 19: DS Description 0 Low level detection 1 Falling edge detection (Initial value) Notes: Level detection burst mode when TM = 1 and DS = 0 Edge detection burst mode when TM = 1 and DS = 1 Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of
) is an active-high or active-low output. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode. Bit 18: RL Description 0 DRAK is an active-high output 1 DRAK is an active-low output (Initial value) Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR1–CHCR3. (DDT mode: TDACK) Bit 17: AM Description 0 DACK is output in read cycle 1 DACK is output in write cycle (Initial value) Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode. Bit 16: AL Description 0 Active-high output 1 Active-low output Rev. 3.0, 04/02, page 476 of 1064 (Initial value) Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. Bit 15: DM1 Bit 14: DM0 Description 0 0 Destination address fixed 1 Destination address incremented (+1 in 8-bit transfer, +2 in 16bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) 0 Destination address decremented (–1 in 8-bit transfer, –2 in 16bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32byte burst transfer) 1 Setting prohibited 1 (Initial value) Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. Bit 13: SM1 Bit 12: SM0 Description 0 0 Source address fixed 1 Source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32byte burst transfer) 0 Source address decremented (–1 in 8-bit transfer, –2 in 16-bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32byte burst transfer) 1 Setting prohibited 1 (Initial value) Rev. 3.0, 04/02, page 477 of 1064 Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 Bit 8: RS0 0 0 External request, dual address mode* * (external address space external address space) (Initial value) 1 Setting prohibited 0 External request, single address mode 0 0 1 Description 1 3
External address space 1
external device* * 1, 3 External request, single address mode
external address space* * Auto-request (external address space
external address space)* Auto-request (external address space
on-chip peripheral module)* Auto-request (on-chip peripheral module
external address 1, 3 External device 1 0 0 2 1 2 1 0 2 space)* 1 0 0 1 1 0 1 1 Setting prohibited 0 SCI transmit-data-empty interrupt transfer request 2 (external address space SCTDR1)* 1 SCI receive-data-full interrupt transfer request 2 (SCRDR1 external address space)* 0 SCIF transmit-data-empty interrupt transfer request 2 (external address space SCFTDR2)* 1 SCIF receive-data-full interrupt transfer request 2 (SCFRDR2 external address space)* 0 TMU channel 2 (input capture interrupt, external address space 2 external address space)* 1 TMU channel 2 (input capture interrupt) 2 (external address space on-chip peripheral module)* 0 TMU channel 2 (input capture interrupt) 2 (on-chip peripheral module external address space)* 1 Setting prohibited






Notes: *1 External request specifications are valid only for channels 0 and 1. Requests are not accepted for channels 2 and 3 in normal DMA mode. *2 Dual address mode *3 In DDT mode, an external request specification is possible for channels 0, 1, 2, and 3. Rev. 3.0, 04/02, page 478 of 1064 Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM Description 0 Cycle steal mode 1 Burst mode (Initial value) Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. In access to external memory, the specification is treated as an access size as described in section 13.3, Operation. In access to a register, the specification is treated as a register access size. Bit 6: TS2 Bit 5: TS1 Bit 4: TS0 Description 0 0 0 Quadword size (64-bit) specification(Initial value) 1 Byte size (8-bit) specification 0 Word size (16-bit) specification 1 Longword size (32-bit) specification 0 32-byte block transfer specification 1 1 0 Bit 3—Reserved: This bit is always read as 0, and should only be written with 0. Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE Description 0 Interrupt request not generated after number of transfers specified in DMATCR (Initial value) 1 Interrupt request generated after number of transfers specified in DMATCR Rev. 3.0, 04/02, page 479 of 1064 Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. Bit 1: TE Description 0 Number of transfers specified in DMATCR not completed (Initial value) [Clearing conditions]   1 When 0 is written to TE after reading TE = 1 In a power-on or manual reset, and in standby mode Number of transfers specified in DMATCR completed Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. Bit 0: DE Description 0 Operation of corresponding channel is disabled 1 Operation of corresponding channel is enabled (Initial value) When auto-request is specified (with RS3–RS0), transfer is begun when this bit is set to 1. In the case of an external request or on-chip peripheral module request, transfer is begun when a transfer request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to 0. Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0, or when the NMIF or AE bit in DMAOR is 1. Rev. 3.0, 04/02, page 480 of 1064 14.2.5 DMA Operation Register (DMAOR) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 DDT — — — — — PR1 PR0 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W 7 6 5 4 3 2 1 0 — — — — — AE NMIF DME Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/(W) R/(W) R/W Initial value: R/W: Bit: Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags. DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0. Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. Bit 15: DDT Description 0 Normal DMA mode 1 On-demand data transfer mode Note: (Initial value)  (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1, the  pin function is enabled and this pin becomes an active-low output. Rev. 3.0, 04/02, page 481 of 1064 Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description 0 0 CH0 > CH1 > CH2 > CH3 1 CH0 > CH2 > CH3 > CH1 0 CH2 > CH0 > CH1 > CH3 1 Round robin mode 1 (Initial value) Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description 0 No address error, DMA transfer enabled (Initial value) [Clearing condition] When 0 is written to AE after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] When an address error is caused by the DMAC Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. Bit 1: NMIF Description 0 No NMI input, DMA transfer enabled [Clearing condition] When 0 is written to NMIF after reading NMIF = 1 1 NMI input, DMA transfer disabled [Setting condition] When an NMI interrupt is generated Rev. 3.0, 04/02, page 482 of 1064 (Initial value) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. Bit 0: DME Description 0 Operation disabled on all channels 1 Operation enabled on all channels 14.3 (Initial value) Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. There are two modes for DMA transfer: single address mode and dual address mode. Either burst mode or cycle steal mode can be selected as the bus mode. 14.3.1 DMA Transfer Procedure After the desired transfer conditions have been set in the DMA source address register (SAR), DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one transfer unit of data (determined by the setting of TS2–TS0). In auto-request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is decremented by 1 for each transfer. The actual transfer flow depends on the address mode and bus mode. 3. When the specified number of transfers have been completed (when the DMATCR value reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE interrupt request is sent to the CPU. 4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event of an address error, a DMAE interrupt request is forcibly sent to the CPU. Figure 14.2 shows a flowchart of this procedure. Rev. 3.0, 04/02, page 483 of 1064 Note: If a transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). Rev. 3.0, 04/02, page 484 of 1064 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) No DE, DME = 1? Yes *4 Illegal address check (reflected in AE bit) No NMIF, AE, TE = 0? Yes *2 Transfer request issued? *1 No *3 Yes Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR DMATCR = 0? NMIF or AE = 1 or DE = 0 or DME = 0? No Yes No Yes DMTE interrupt request (when IE = 1) NMIF or AE = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, detection method Transfer suspended No Yes End of transfer Normal end Notes: *1 In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE and DME bits are set to 1. *2 level detection (external request) in burst mode, or cycle steal mode *3 edge detection (external request) in burst mode, or auto-request mode in burst mode *4 An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn Figure 14.2 DMAC Transfer Flowchart Rev. 3.0, 04/02, page 485 of 1064 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The transfer request mode is selected by means of bits RS3–RS0 in DMA channel control registers 0–3 (CHCR0–CHCR3). Auto Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bit in CHCR0–CHCR3 and the DME bit in the DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in CHCR0–CHCR3 and the NMIF and AE bits in DMAOR are all 0). External Request Mode: In this mode a transfer is performed in response to a transfer request signal (
) from an external device. One of the modes shown in table 14.4 should be chosen according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when
 is input. The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the
 signal (level detection when DS = 0, edge detection when DS = 1).
 is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0). In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1). The source of the transfer request does not have to be the data transfer source or destination. Rev. 3.0, 04/02, page 486 of 1064 Table 14.4 Selecting External Request Mode with RS Bits RS3 RS2 RS1 RS0 Address Mode Transfer Source Transfer Destination 0 0 0 0 Dual address mode External memory, memory-mapped external device, or external device with DACK External memory, memory-mapped external device, or external device with DACK 1 0 Single address mode External memory or memory-mapped external device External device with DACK 1 Single address mode External device with DACK External memory or memory-mapped external device
External Request Acceptance Conditions 1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, if an external request (
: edge-detected) is input it will be held inside the DMAC until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0). 2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0, CHCR.TE = 0), if an external request (
) is input, DMA transfer is started. 3. An external request (
) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF = 1, DMAOR.AE = 1, during a power-on reset or manual reset, in deep sleep mode, standby mode, or while the DMAC is in the module standby state. 4. A previously input external request will be canceled by the occurrence of an NMI interrupt (DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or manual reset.
Usage Notes 1. An external request (
) is detected by a low level or falling edge. Ensure that the external request (
) signal is held high when there is no DMA transfer request from an external device after a power-on reset or manual reset. When DMA transfer is restarted, check whether a DMA transfer request is being held. 2. With
 edge detection, an accepted external request can be canceled by first negating
, enabling a change of setting from CHCR.DS = 1 to CHCR.DS = 0, and then asserting
 after setting CHCR.DS to 1 again. Rev. 3.0, 04/02, page 487 of 1064 On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit (TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input. The source of the transfer request does not have to be the data transfer source or destination. However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full interrupt), the transfer source must be the SCI/SCIF’s receive data register (SCRDR1/SCFRDR2). When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty interrupt), the transfer destination must be the SCI/SCIF’s transmit data register (SCTDR1/SCFTDR2). Rev. 3.0, 04/02, page 488 of 1064 Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer RS3 RS2 RS1 RS0 Request Source Request Signal Transfer Source Transfer Destination Bus Mode 1 0 0 1 1 0 1 TMU: SCI: SCIF: Notes: 0 SCI transmitter SCTDR1 (SCI transmit-dataempty transfer request) External* SCTDR1 Cycle steal mode 1 SCI receiver SCRDR1 (SCI receive-data-full transfer request) SCRDR1 External* Cycle steal mode 0 SCIF transmitter SCFTDR2 (SCIF transmit-dataempty transfer request) External* SCFTDR2 Cycle steal mode 1 SCIF receiver SCFRDR2 (SCIF receive-data-full transfer request) SCFRDR2 External* Cycle steal mode 0 TMU channel 2 Input capture occurrence External* External* Burst/cycle steal mode 1 TMU channel 2 Input capture occurrence External* On-chip peripheral Burst/cycle steal mode 0 TMU channel 2 Input capture occurrence On-chip External* peripheral Burst/cycle steal mode Timer unit Serial communication interface Serial communication interface with FIFO * External memory or memory-mapped external device 1. SCI/SCIF burst transfer setting is prohibited. 2. If input capture interrupt acceptance is set for multiple channels and DE =1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt. 3. A DMA transfer request by means of an input capture interrupt can be canceled by setting TCR2.ICPE1 = 0 and TCR2.ICPE0 = 0 in the TMU. To output a transfer request from an on-chip peripheral module, set the DMA transfer request enable bit for that module and output a transfer request signal. For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and 16, Serial Communication Interface with FIFO (SCIF). When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs every transfer in cycle steal mode, and in the last transfer in burst mode. Rev. 3.0, 04/02, page 489 of 1064 14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority orders are available in fixed mode:
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3 The priority order is selected with bits PR1 and PR0 in DMAOR. Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. This is illustrated in figure 14.3. The order of priority in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3. Note: In round robin mode, if no transfer request is accepted for any channel during DMA transfer, the priority order becomes CH0 > CH1 > CH2 > CH3. Rev. 3.0, 04/02, page 490 of 1064 Transfer on channel 0 Initial priority order CH0 > CH1 > CH2 > CH3 Channel 0 is given the lowest priority. Priority order after transfer CH1 > CH2 > CH3 > CH0 Transfer on channel 1 Initial priority order CH0 > CH1 > CH2 > CH3 Priority order after transfer CH2 > CH3 > CH0 > CH1 When channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously. Transfer on channel 2 Initial priority order When channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. If there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. CH0 > CH1 > CH2 > CH3 Priority order after transfer Priority after transfer due to issuance of a transfer request for channel 1 only. CH3 > CH0 > CH1 > CH2 CH2 > CH3 > CH0 > CH1 Transfer on channel 3 Initial priority order CH0 > CH1 > CH2 > CH3 No change in priority order Priority order after transfer CH0 > CH1 > CH2 > CH3 Figure 14.3 Round Robin Mode Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The operation of the DMAC in this case is as follows. Rev. 3.0, 04/02, page 491 of 1064 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. The channel 3 transfer is started. 8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. Transfer request 1. Issued for channels 0 and 3 Channel waiting 3. Issued for channel 1 3 DMAC operation Channel priority order 2. Start of channel 0 transfer 0>1>2>3 Change of priority order 1, 3 4. End of channel 0 transfer 1>2>3>0 5. Start of channel 1 transfer 3 6. End of channel 1 transfer Change of priority order 2>3>0>1 7. Start of channel 3 transfer None Change of priority order 8. End of channel 3 transfer 0>1>2>3 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode Rev. 3.0, 04/02, page 492 of 1064 14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. The actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. Table 14.6 Supported DMA Transfers Transfer Destination External Device with DACK External Memory Memory-Mapped External Device On-Chip Peripheral Module External device with DACK Not available Single address mode Single address mode Not available External memory Single address mode Dual address mode Dual address mode Dual address mode Memory-mapped external device Single address mode Dual address mode Dual address mode Dual address mode On-chip peripheral module Not available Dual address mode Dual address mode Not available Transfer Source Rev. 3.0, 04/02, page 493 of 1064 Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows an example of a transfer between external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle. External address bus External data bus SH7751 Series External memory DMAC External device with DACK DACK : Data flow Figure 14.5 Data Flow in Single Address Mode Two types of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. Only the external request signal (
) is used in both these cases. Figure 14.6 shows the transfer timing for single address mode. The access timing depends on the type of external memory. For details, see the descriptions of the memory interfaces in section 13, Bus State Controller (BSC). Rev. 3.0, 04/02, page 494 of 1064 CKIO A28–A0 Address output to external memory space CSn D63–D0 DACK WE Data output from external device with DACK DACK signal to external device with DACK WE signal to external memory space (a) From external device with DACK to external memory space CKIO A28–A0 Address output to external memory space CSn D63–D0 RD DACK Data output from external memory space RD signal to external memory space DACK signal to external device with DACK (b) From external memory space to external device with DACK Figure 14.6 DMA Transfer Timing in Single Address Mode Rev. 3.0, 04/02, page 495 of 1064 Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either onchip peripheral module or external address. In dual address mode, data is read from the transfer source in the data read cycle, and written to the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles. The transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 14.7, data is read from external memory into the BSC’s data buffer in the read cycle, then written to the other external memory in the write cycle. Figure 14.8 shows the timing for this operation. SAR BSC Data bus DAR Memory Address bus DMAC Transfer source module Transfer destination module Data buffer Taking the SAR value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (BSC). 1st bus cycle SAR BSC Data bus DAR Memory Address bus DMAC Transfer source module Transfer destination module Data buffer Taking the DAR value as the address, the data stored in the BSC’s data buffer is written to the transfer destination module. 2nd bus cycle Figure 14.7 Operation in Dual Address Mode Rev. 3.0, 04/02, page 496 of 1064 CKIO A28–A0 Transfer source address Transfer destination address D63–D0 DACK Data read cycle (1st cycle) Data write cycle (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0– CHCR3. Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end condition is satisfied. Cycle steal mode can be used with all categories of transfer request source, transfer source, and transfer destination. Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and
 level detection. Rev. 3.0, 04/02, page 497 of 1064 Bus returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC Read Write CPU CPU Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied. Bus release by means of  and refresh requests conform to the DMAC burst mode transfer priority specification in bus control register 1 (BCRL.DMABST). With
 low level detection in external request mode, however, when
 is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted, even if the transfer end condition has not been satisfied. Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in this example are single address mode and
 level detection (CHCRn.DS = 0, CHCRn.TM = 1). Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.10 Example of DMA Transfer in Burst Mode Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode setting can also be made. Rev. 3.0, 04/02, page 498 of 1064 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Mode Single Dual Request Mode Bus Mode Transfer Size Usable (Bits) Channels External B/C 8/16/32/64/32B 0, 1 (2, 3)* External device with DACK External and memory-mapped external device B/C 8/16/32/64/32B 0, 1 (2, 3)* 1 B/C 8/16/32/64/32B 0, 1, 2, 3* * 1 B/C 8/16/32/64/32B 0, 1, 2, 3* * 1 B/C 8/16/32/64/32B 0, 1, 2, 3* * 2 B/C* 3 8/16/32/64* 2 B/C* 3 8/16/32/64* Type of Transfer External device with DACK and external memory External memory and external Internal* , 7 memory external* External memory and memory- Internal* , 7 mapped external device external* Memory-mapped external device and memory-mapped external device Internal* , 7 external* External memory and on-chip peripheral module Internal* Memory-mapped external device and on-chip peripheral module Internal* 32B: B: C: 32-byte burst transfer Burst Cycle steal External: External request 6 6 5, 6 5, 6 5, 6 4 0, 1, 2, 3* * 5, 6 4 0, 1, 2, 3* * 5, 6 Internal: Auto request, on-chip peripheral module request Notes: *1 External request, auto-request, or on-chip peripheral module request (TMU input capture interrupt request) possible. In the case of an on-chip peripheral module request, it is not possible to specify external memory data transfer with the SCI (SCIF) as the transfer request source. *2 Auto-request, or on-chip peripheral module request possible. If the transfer request source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or the transfer destination must be SCTDR1 (SCFTDR2). *3 When the transfer request source is the SCI (SCIF), only cycle steal mode can be used. *4 Access size permitted for the on-chip peripheral module register that is the transfer source or transfer destination. *5 When the transfer request is an external request, only channels 0 and 1 can be used. *6 In DDT mode, transfer requests can be accepted for all channels from external devices capable of DTR format output. Rev. 3.0, 04/02, page 499 of 1064 *7 See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA transfer by means of an external request. (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7751 Series in normal DMA mode. Table 14.8 External Request Transfer Sources and Destinations in Normal Mode Transfer Source Transfer Destination Usable Address DMAC Mode Channels 1 Synchronous DRAM External device with DACK Single 0, 1 2 External device with DACK Synchronous DRAM Single 0, 1 3 SRAM-type, DRAM External device with DACK Single 0, 1 4 External device with DACK SRAM-type, DRAM Single 0, 1 5 Synchronous DRAM Dual 0, 1 6 SRAM-type, MPX, PCMCIA Dual 0, 1 7 SRAM-type, DRAM, PCMCIA, MPX Dual 0, 1 8 SRAM-type, MPX, PCMCIA Dual 0, 1 Transfer Direction (Settable Memory Interface) SRAM-type, MPX, PCMCIA * SRAM-type, MPX, PCMCIA * * Synchronous DRAM SRAM-type, DRAM, PCMCIA, MPX * *: DACK output setting in dual address mode transfer "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: 1. Memory interfaces on which transfer is possible in single address mode are SRAM, byte control SRAM, burst ROM, DRAM, and synchronous DRAM. 2. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. Rev. 3.0, 04/02, page 500 of 1064 (b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7751 Series in DDT mode. Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Transfer Source Transfer Destination Usable Address DMAC Mode Channels 1 Synchronous DRAM External device with DACK Single 0, 1, 2, 3 2 External device with DACK Synchronous DRAM Single 0, 1, 2, 3 3 Synchronous DRAM SRAM-type, MPX, PCMCIA Dual 0, 1, 2, 3 4 SRAM-type, MPX, PCMCIA Dual 0, 1, 2, 3 5 SRAM-type, DRAM, PCMCIA, MPX Dual 0, 1, 2, 3 6 SRAM-type, MPX, PCMCIA Dual 0, 1, 2, 3 Transfer Direction (Settable Memory Interface) * Synchronous DRAM SRAM-type, MPX, PCMCIA * * SRAM-type, DRAM, PCMCIA, MPX * *: DACK output setting in dual address mode transfer "SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting. Notes: 1. The only memory interface on which single address mode transfer is possible in DDT mode is synchronous DRAM. 2. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface. Bus Mode and Channel Priority Order When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set for channel 0. If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. Channel execution alternates in the order: channel 1  channel 0  channel 1  channel 0. An example of round robin mode operation is shown in figure 14.11. Rev. 3.0, 04/02, page 501 of 1064 Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends. CPU CPU DMAC CH1 DMAC CH1 DMAC channel 1 burst mode DMAC CH0 DMAC CH1 DMAC CH0 CH0 CH1 CH0 DMAC channel 0 and channel 1 round robin mode DMAC CH1 DMAC CH1 DMAC channel 1 burst mode CPU CPU Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing) Figure 14.11 Bus Handling with Two DMAC Channels Operating Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the bus is passed to the CPU during a break in requests. 14.3.5 Number of Bus Cycle States and
 Pin Sampling Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. See section 13, Bus State Controller (BSC), for details. DREQ Pin Sampling Timing: In external request mode, the
 pin is sampled at the rising edge of CKIO clock pulses. When
 input is detected, a DMAC bus cycle is generated and DMA transfer executed after four CKIO cycles at the earliest. With
 falling edge detection, as the signal passes via an asynchronous circuit the DMAC recognizes
 two cycles (CKIO) later (one cycle (CKIO) later in the case of low level detection). The second and subsequent
 sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of single address mode). DRAK is output for one cycle only, once each time
 is detected, regardless of the transfer mode or
 detection method. In the case of burst mode edge detection,
 is sampled in the first cycle only, and so DRAK is output in the first cycle only . Operation: Figures 14.12 to 14.22 show the timing in each mode. Rev. 3.0, 04/02, page 502 of 1064 1. Cycle Steal Mode In cycle steal mode, The
 sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of
. For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. If
 is not detected at this time, sampling is executed in every subsequent cycle. In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If
 is not detected at this time, sampling is executed in every subsequent cycle. For details of the timing for various memory accesses, see section 13, Bus State Controller (BSC). Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after the first
 sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle. Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the first
 sampling operation. The second sampling begins one cycle after the first assertion of DRAK. In single address mode, the DACK signal is output every DMAC transfer cycle. 2. Burst Mode, Dual Address Mode, Level Detection
 sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 3. Burst Mode, Single Address Mode, Level Detection
 sampling timing in burst mode using single address mode and level detection is shown in figure 14.20. In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle. Rev. 3.0, 04/02, page 503 of 1064 In figure 14.22, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. 4. Burst Mode, Dual Address Mode, Edge Detection In burst mode using dual address mode and edge detection,
 sampling is performed in the first cycle only. For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR.
 is not sampled during this time, and therefore DRAK is output in the first cycle only. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. 5. Burst Mode, Single Address Mode, Edge Detection In burst mode using single address mode and edge detection,
 sampling is performed only in the first cycle. For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR.
 is not sampled during this time, and therefore DRAK is output in the first cycle only. In single address mode, the DACK signal is output every DMAC transfer cycle. Suspension of DMA Transfer in Case of
 Level Detection With
 level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which DMA transfer is being executed can judge from the rising edge of CKIO that DRAK has been asserted, and can suspend DMA transfer by negating
. In this case, the next DRAK signal is not output. Rev. 3.0, 04/02, page 504 of 1064 Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Level Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 505 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[31:0] A[25:0] CKIO 2nd acceptance Write Destination address DMAC : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address Bus locked CPU Read Source address DMAC Write Destination address Bus locked CPU Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Edge Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 506 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[31:0] A[25:0] CKIO DMAC Write CPU Destination address 2nd acceptance : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address Bus locked DMAC Write CPU Destination address 3rd acceptance Read Source address Bus locked DMAC 4th acceptance Read Source address Figure 14.14 Dual Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 507 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[31:0] A[25:0] CKIO 2nd acceptance Write Destination address DMAC-1 : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address Bus locked Read Write Destination address DMAC-2 Source address Bus locked CPU Figure 14.15 Dual Address Mode/Burst Mode External Bus  External Bus/
 (Edge Detection), DACK (Read Cycle) Rev. 3.0, 04/02, page 508 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[31:0] A[25:0] CKIO : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC-1 Read DMAC-2 Write Destination address Bus locked Source address TE bit: transfer end Write Destination address Bus locked CPU Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)  External Bus Rev. 3.0, 04/02, page 509 of 1064 (When Bcyc : Pcyc = 1 : 1) Bus cycle D[31:0] A[25:0] On-chip peripheral data bus On-chip peripheral address bus CKIO CPU Read Source address DMAC Write Destination address CPU Read Source address DMAC Write Destination address CPU Read Source address DMAC Write CPU Destination address Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus  On-Chip SCI (Level Detection) Rev. 3.0, 04/02, page 510 of 1064 CPU (When Bcyc : Pcyc = 1 : 1) Bus cycle On-chip peripheral data bus On-chip peripheral address bus D[31:0] A[25:0] CKIO Read T1 T2 Write CPU Destination address DMAC Source address Read T1 T2 Write CPU Destination address DMAC Source address Read T1 T2 Write Destination address DMAC Source address Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Level Detection) Rev. 3.0, 04/02, page 511 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[31:0] A[25:0] CKIO DMAC 2nd acceptance CPU : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC 3rd acceptance Read Source address CPU DMAC 4th acceptance Read Source address CPU DMAC Read Source address CPU Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus  External Bus/
 (Edge Detection) Rev. 3.0, 04/02, page 512 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (edge detection) D[31:0] A[25:0] CKIO DMAC 2nd acceptance : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address CPU DMAC 3rd acceptance Read Source address CPU DMAC Read Source address CPU Figure 14.20 Single Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection) Rev. 3.0, 04/02, page 513 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[31:0] A[25:0] CKIO DMAC-1 2nd acceptance : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC-2 3rd acceptance Read Source address DMAC-3 Read Source address CPU 4th acceptance DMAC-4 Read Source address Figure 14.21 Single Address Mode/Burst Mode External Bus  External Bus/
 (Edge Detection) Rev. 3.0, 04/02, page 514 of 1064 DACK0 Bus cycle DRAK0 DREQ0 (edge detection) D[31:0] A[25:0] CKIO DMAC-1 : DREQ sampling and determination of channel priority CPU 1st acceptance Read Source address DMAC-2 DMAC-3 Read Source address TE bit: transfer end Read Source address DMAC-4 Read Source address CPU Figure 14.22 Single Address Mode/Burst Mode External Bus  External Bus/
 (Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM: Row Hit Write) Rev. 3.0, 04/02, page 515 of 1064 DACK0 Bus cycle DRAK0 DREQ1 DREQ0 (level detection) D[31:0] A[25:0] CKIO CPU Asserted 2 cycles before start of bus cycle 2nd acceptance D7 DMAC-1 D6 : DREQ sampling and determination of channel priority 1st acceptance D1 Destination address 3rd acceptance D1 Asserted 2 cycles before start of bus cycle D8 D7 DMAC-2 D6 Destination address D1 Asserted 2 cycles before start of bus cycle D8 D7 DMAC-3 D6 Destination address D8 CPU 14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer. 1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request) When a transfer end condition is satisfied, acceptance of DMAC transfer requests is suspended. The DMAC completes transfer for the transfer requests accepted up to the point at which the transfer end condition was satisfied, then stops. In cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, AutoRequest) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge detection, only the first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 4 and 5 under Operation in section 14.3.5. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 3. Burst Mode, Level Detection (External Request) The delay between the point at which a transfer end condition is satisfied and the point at which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation in section 14.3.5. Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 4. Transfer Suspension Bus Timing Transfer suspension is executed on completion of processing for one transfer unit. In dual address mode transfer, write cycle processing is executed even if a transfer end condition is satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed before operation is suspended. Rev. 3.0, 04/02, page 516 of 1064 Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied:
The value in the DMA transfer count register (DMATCR) reaches 0.
The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1. End of transfer when DMATCR = 0 When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an interrupt (DMTE) request is sent to the CPU. Transfer ending when DMATCR = 0 does not follow the procedures described in 1, 2, 3, and 4 in section 14.3.6. 2. End of transfer when DE = 0 in CHCR When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows the procedures described in 1, 2, 3, and 4 in section 14.3.6. Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all channels simultaneously when either of the following conditions is satisfied:
The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is set.
The DMA master enable bit (DME) in DMAOR is cleared to 0. 1. End of transfer when AE = 1 in DMAOR If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. Therefore, when AE is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer, it is necessary to make a new setting for the channel that caused the address error, then write 0 to the AE bit after first reading 1 from it. Acceptance of external requests is suspended while AE is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. Rev. 3.0, 04/02, page 517 of 1064 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1 from it. As in the case of AE being set to 1, acceptance of external requests is suspended while NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of internal requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new setting is made. 3. End of transfer when DME = 0 in DMAOR If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA source address register (SAR), DMA destination address register (DAR), and DMA transfer count register (DMATCR) indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. When resuming transfer, DME must be set to 1. Operation will then be resumed from the next transfer. Rev. 3.0, 04/02, page 518 of 1064 14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions Register Set Value Transfer source: external memory SAR1 H'0C000000 Transfer source: external device with DACK DAR1 (Accessed by DACK) Number of transfers: 32 DMATCR1 H'00000020 Transfer source address: decremented CHCR1 H'000022A5 DMAOR H'00000201 Transfer destination address: (setting invalid) Transfer request source: external pin (
) edge detection Bus mode: burst Transfer unit: word No interrupt request at end of transfer Channel priority order: 2 > 0 > 1 > 3 Rev. 3.0, 04/02, page 519 of 1064 14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module, and simultaneously issue a transfer request, using the
, , ,
 , ID [1:0], DTR.ID, and DTR.MD signals between an external device and the DMAC. Figure 14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with
, , ,
 , ID [1:0], DTR.ID, and DTR.MD pins). DMAC DDT Memory SAR0 DAR0 DREQ0–3 Request ddtmode controller ddtmode tdack id[1:0] bavl Address bus CHCR0 Data bus Data buffer DMATCR0 DTR BSC Data buffer ID[1:0] External device (with , , , , and ID [1:0]) FIFO or memory Figure 14.23 On-Demand Transfer Mode Block Diagram After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU, a transfer request is output from an external device using the
, , ,
 , DTR.ID [1:0], and DTR.MD [1:0] signals (handshake protocol using the data bus). A transfer request can also be issued simply by asserting , without using the external bus (handshake protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a transfer request can be issued directly from an external device (with
, , ,
 , DTR.ID [1:0], and DTR.MD [1:0] pins) by asserting
 and  simultaneously . In DDT mode, there is a choice of five modes for performing DMA transfer. Rev. 3.0, 04/02, page 520 of 1064 1. Normal data transfer mode (channel 0)  (the data bus available signal) is asserted in response to
 (the data bus request signal) from an external device. Two CKIO-synchronous cycles after  is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with  (the transfer request signal). The initial settings are then made in the DMAC channel 0 control register, and the DMA transfer is processed. 2. Normal data transfer mode (except channel 1 to channel 3) In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA transfer requests only are performed from the external device. As in 1 above,
 is asserted from the external device and the external bus is secured, then the DTR command is driven. The transfer request channel can be specified by means of the two ID bits in the DTR command. 3. Handshake protocol using the data bus (valid for channel 0 only) This mode is only valid for channel 0. After the initial settings have been made in the DMAC channel 0 control register, the DDT module asserts a data transfer request for the DMAC by setting the DTR command ID = 00, MD = 00, and SZ  101, 110 and driving the DTR command. 4. Handshake protocol without use of the data bus The DDT module includes a function for recording the previously asserted request channel. By using this function, it is possible to assert a transfer request for the channel for which a request was asserted immediately before, by asserting  only from an external device after a transfer request has once been made to the channel for which an initial setting has been made in the DMAC control register (DTR command and data transfer setting by the CPU in the DMAC). 5. Direct data transfer mode (valid for channel 2 only) A data transfer request can be asserted for channel 2 by asserting
 and  simultaneously from an external device after the initial settings have been made in the DMAC channel 2 control register. Rev. 3.0, 04/02, page 521 of 1064 14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. / /DRAK0 / /DACK0 SH7751 Series ID1, ID0/DRAK1, DACK1 External device CLK D31–D0 = DTR A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode

: Data bus release request signal for transmitting the data transfer request format (DTR format) or a DMA request from an external device to the DMAC If there is a wait for release of the data bus, an external device can have the data bus released by asserting
. When
 is accepted, the BSC asserts .

 : Data bus D31–D0 release signal Assertion of  means that the data bus will be released two cycles later. : Transfer request signal Assertion of  has the following different meanings.  In normal data transfer mode (except channel 0),  is asserted, and at the same time the DTR format is output, two cycles after  is asserted.  In the case of the handshake protocol without use of the data bus, asserting  enables a transfer request to be issued for the channel for which a transfer request was made immediately before. This function can be used only when  is not asserted two cycles earlier.  In the case of direct data transfer mode (valid only for channel 2), a direct transfer request can be made to channel 2 by asserting
 and  simultaneously. Rev. 3.0, 04/02, page 522 of 1064 


 : Reply strobe signal for external device from DMAC The assertion timing is the same as the DACKn assertion timing for each memory interface. However, note that
  is an active-low signal.
ID1, ID0: Channel number notification signals  00: Channel 0  01: Channel 1  10: Channel 2  11: Channel 3 Data Transfer Request Format (DTR) 31 28 27 SZ ID 25 23 MD 0 (Reserved) (Reserved) Figure 14.25 Data Transfer Request Format The data transfer request format (DTR format) consists of 32 bits. In the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus, channel number and transfer request mode are specified. Connection is made to D31 through D0. Bits 31 to 29: Transmit Size (SZ2–SZ0)
000: Handshake protocol (data bus used)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Request queue clear specification
111: Transfer end specification Bit 28: Reserved Bits 27 and 26: Channel Number (ID1, ID0)
00: Channel 0
01: Channel 1
10: Channel 2
11: Channel 3 Rev. 3.0, 04/02, page 523 of 1064 Bits 25 and 24: Transfer Request Mode (MD1, MD0)
00: Handshake protocol (data bus used)
01: Setting prohibited
10: Request queue clear specification
11: Setting prohibited Bits 23 to 0: Reserved Notes: 1. In channels 1 to 3, only the ID field is valid. 2. In channel 0, the MD field is valid. Set MD = 00. If 01, 10, or 11 is set, the DMAC will halt with an address error. 3. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst mode and cycle steal mode, a handshake protocol is used to transfer each unit of data. 4. When specifying data transfer requests using a handshake protocol for channel 0, set ID = 00, MD = 00, and SZ  101, 110 for the DTR format. Use the MOV instruction to make settings in the DMAC's SAR0, DAR0, CHCR0, and DMATCR0 registers. Either single address mode or dual address mode can be used as the transfer mode. Select one of the following settings: CHCR0.RS3—RS0 = 0000, 0010, 0011. Operation is not guaranteed if the DTR format data settings are DTR.ID = 00, DTR.MD = 00, and DTR.SZ  101, 110. Usable SZ, ID, and MD Combination in DDT Mode Table 14.11 shows the usable combination of SZ, ID, and MD in DDT mode of the SH7751. Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode SZ [2:0] ID [1:0] MD [1:0] Function 000 00 00 Request for transfer to channel 0 110 00 10 Request queue clear 111 00 00 Transfer end X 01 X Request for transfer to channel 1 X 10 X Request for transfer to channel 2 X 11 X Request for transfer to channel 3 Notes: Don’t set values other than those shown in the above table. X: Don’t care Rev. 3.0, 04/02, page 524 of 1064 14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer. On channels 1 to 3, output a transfer request from an external device by means of the DTR format (ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored, and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains in the request queue and a transfer is completed, the request queue retains it. When another transfer request is sent at that time, the transfer request is added to the request queue if the request queue is vacant. Rev. 3.0, 04/02, page 525 of 1064 Figure 14.26 Single Address Mode/Synchronous DRAM  External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS latency=3, TPC=3) Rev. 3.0, 04/02, page 526 of 1064 Tg tRASD Tj Tk Tl tAD Tm Tn ID1-ID0 D31-D0 (READ) DQMn RD/ tBAVD tTRS tBAVD tRASD tTRH To Tp tRDS tIDD tTDAD tBSD tCASD2 tDQMD [2CKIO cycles - tDTRS] (= 18ns: 100MHz) DTR= 1CKIO cycle (= 10ns: 100MHz) tCASD2 tRWD tCSD c1 tDTRH Ti Row Th Addr tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Tb BANK CKIO Ta tBSD tRDH c2 Ts c3 tDQMD Tr DMAC Channel c1 Tq c4 Tu tIDD tTDAD tCSD tAD Tt Tv Tw Figure 14.27 Single Address Mode/External Device  Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1, TRWL=2, TPC=1) Rev. 3.0, 04/02, page 527 of 1064 Tb Tg tRASD Tj Tk Tl tAD Tm Tn ID1-ID0 D31-D0 (READ) DQMn RD/ tBAVD tTRS tBAVD tBSD c1 tTRH tIDD tCASD2 tBSD tWDD c2 DMAC Channel tTDAD To tRWD tDQMD [2CKIO cycles - tDTRS] (= 18ns: 100MHz) DTR= 1CKIO cycle (= 10ns: 100MHz) tWDD tCASD2 tRASD tRWD tCSD c1 tDTRH Ti Row Th Addr tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Ta BANK CKIO c4 tIDD tTDAD c3 Tp Tr tDQMD tCSD tAD Tq Ts Tt Tu Tv Tw Figure 14.28 Dual Address Mode/Synchronous DRAM  SRAM Longword Transfer Rev. 3.0, 04/02, page 528 of 1064 Tg tRASD Tj Tk Tl tAD Tm Tn ID1-ID0 D31-D0 (READ) DQMn RD/ tBAVD tTRS tBAVD tRASD tTRH To Tp tRDS tBSD tCASD2 tDQMD [2CKIO cycles - tDTRS] (= 18ns: 100MHz) DTR= 1CKIO cycle (= 10ns: 100MHz) tCASD2 tRWD tCSD c1 tDTRH Ti Row Th Addr tDTRS Tf H/L Te Row tDBQH Td Precharge-sel Tc tAD Row tDBQS Tb BANK CKIO Ta tBSD tRDH c2 Ts c3 tDQMD Tr DMAC Channel c1 Tq c4 tCSD tAD Tt DMAC Channel tTDAD tTDAD CKIO DBREQ BAVL TR A25–A0 D31–D0 RA CA D0 DTR RAS, CAS, WE BA D1 D2 D3 RD TDACK 00 ID1, ID0 Figure 14.29 Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer CKIO DBREQ BAVL TR RA A25–A0 D31–D0 RAS, CAS, WE DTR CA D0 BA D1 D2 D3 D4 D5 WT TDACK ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device  External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 529 of 1064 CKIO DBREQ BAVL TR A25–A0 D31–D0 RA CA DTR RAS, CAS, WE CA D0 BA RD CA D1 RD RD DQMn TDACK ID1, ID0 00 00 Figure 14.31 Single Address Mode/Burst Mode/External Bus  External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 530 of 1064 CKIO DBREQ BAVL TR RA A25–A0 D31–D0 RAS, CAS, WE DTR BA CA CA D0 D1 WT WT DQMn TDACK ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device  External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 531 of 1064 CKIO DBREQ BAVL TR A25–A0 D31–D0 CA DTR MD = 00 CMD D0 CA D1 D2 D3 DTR MD = 00 WT WT TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev. 3.0, 04/02, page 532 of 1064 D0 D1 CKIO DBREQ BAVL TR A25–A0 D31–D0 CA DTR MD = 00 CMD D0 CA D1 D2 D3 D0 WT D1 D2 D3 WT TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev. 3.0, 04/02, page 533 of 1064 CKIO DBREQ BAVL TR RA A25–A0 CA D0 D31–D0 RAS, CAS, WE BA D1 D2 D3 RD Figure 14.35 Read from Synchronous DRAM Precharge Bank CKIO DBREQ Transfer requests can be accepted BAVL TR RA A25–A0 CA D31–D0 RAS, CAS, WE D0 PCH BA D1 D2 D3 RD Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev. 3.0, 04/02, page 534 of 1064 CKIO DBREQ BAVL TR A25–A0 CA D0 D31–D0 RAS, CAS, WE D1 D2 D3 RD Figure 14.37 Read from Synchronous DRAM (Row Hit) CKIO DBREQ BAVL TR A25–A0 RA D0 D31–D0 RAS, CAS, WE CA BA D1 D2 D3 WT Figure 14.38 Write to Synchronous DRAM Precharge Bank Rev. 3.0, 04/02, page 535 of 1064 CKIO DBREQ Transfer requests can be accepted BAVL TR RA A25–A0 CA D31–D0 RAS, CAS, WE D0 BA PCH D1 D2 D3 WT Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CKIO DBREQ BAVL TR A25–A0 CA D31–D0 D0 RAS, CAS, WE WT D1 D2 D3 Figure 14.40 Write to Synchronous DRAM (Row Hit) Rev. 3.0, 04/02, page 536 of 1064 CKIO DBREQ BAVL TR RA A25–A0 D31–D0 RAS, CAS, WE CA DTR D0 BA D1 D2 RD TDACK ID1, ID0 00 Figure 14.41 Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 3.0, 04/02, page 537 of 1064 DMA Operation Register (DMAOR) 31 15 9 8 2 PR[1:0] AE NMIF DDT DME DDT: 0: Normal DMA mode 1: On-demand data transfer mode Figure 14.42 DDT Mode Setting CKIO DBREQ BAVL No DMA request sampling TR A25–A0 D31–D0 CA DTR CMD D0 WT CA D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 WT TDACK ID1, ID0 Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device  External Bus Data Transfer Rev. 3.0, 04/02, page 538 of 1064 1 0 CKIO DBREQ BAVL Wait for next DMA request TR CA A25–A0 D31–D0 CA DTR D0 CMD D1 D2 D3 RD D0 D1 D2 D3 RD TDACK ID1, ID0 Start of data transfer Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus  External Device Data Transfer CKIO DBREQ BAVL TR A25–A0 D31–D0 CMD CA CA D0 DTR RD CA Idle cycle RD D2 Idle cycle D3 Idle cycle RD DQMn TDACK ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus  External Device Data Transfer Rev. 3.0, 04/02, page 539 of 1064 CKIO DBREQ BAVL TR A25–A0 D31–D0 CA DTR CMD DQMn CA CA D0 D1 D3 WT WT WT Idle cycle Idle cycle Idle cycle TDACK ID1, ID0 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device  External Bus Data Transfer Rev. 3.0, 04/02, page 540 of 1064 CKIO DBREQ BAVL TR A25–A0 D31–D0 RA CA DTR D0 D1 D2 D3 ID = 1, 2, or 3 RAS, CAS, WE BA RD TDACK ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus Rev. 3.0, 04/02, page 541 of 1064 CKIO DBREQ BAVL TR A25–A0 RA CA D31–D0 D0 RAS, CAS, WE BA D1 D2 D3 RD TDACK ID1, ID0 10 No DTR cycle, so requests can be made at any time Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus  External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus Rev. 3.0, 04/02, page 542 of 1064 Four requests can be queued Handshaking is necessary to send additional requests CKIO 1st 2nd 3rd 5th 4th No more requests A25 A0 RA CA D0 D31 D0 RAS, CAS, WE BA RD CA CA D1 D2 D3 D0 RD D1 CA D2 D3 RD D0 D1 D2 RD ID1, ID0 Must be ignored (no request transmitted)
Figure 14.49 Single Address Mode/Burst Mode/External Bus External Device Data Transfer/Direct Data Transfer Request to Channel 2 Rev. 3.0, 04/02, page 543 of 1064 Four requests can be queued Handshaking is necessary to send additional requests CKIO 1st 2nd 3rd A25–A0 5th 4th RA D0 D31–D0 RAS, CAS, WE CA BA WT CA D1 D2 D3 D0 WT CA D1 D2 D3 D0 WT CA D1 D2 D3 WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device  External Bus Data Transfer/Direct Data Transfer Request to Channel 2 Rev. 3.0, 04/02, page 544 of 1064 Handshaking is necessary to send additional requests Four requests can be queued CKIO 1st 2nd 3rd A25–A0 5th 4th D0 D31–D0 RAS, CAS, WE RD CA CA CA D1 RD D2 D3 D0 D1 CA D2 D3 RD D0 D1 D2 RD ID1, ID0 Must be ignored (no request transmitted)
Figure 14.51 Single Address Mode/Burst Mode/External Bus External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev. 3.0, 04/02, page 545 of 1064 Four requests can be queued 1st 2nd 3rd 4th Handshaking is necessary to send additional requests 5th A25–A0 CA D31–D0 D0 RAS, CAS, WE WT CA D1 D2 D3 D0 WT CA D1 D2 D3 D0 WT CA D1 D2 D3 WT ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device  External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev. 3.0, 04/02, page 546 of 1064 14.5.4 Notes on Use of DDT Module 1. Normal data transfer mode (channel 0) Set DTR.ID = 00 and DTR.MD = 00. If a setting of MD = 01, 10, or 11 is made, the DMAC will halt with an address error. In this case, the error can be cleared by reading DMAOR.AE = 1, then writing AE = 0. 2. Normal data transfer mode (except channel 1 to channel 3) If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored. 3. Handshake protocol using the data bus (valid on channel 0 only) a. The handshake protocol using the data bus can be executed only on channel 0. (The DTR format must be set to DTR.ID = 00, DTR.MD = 00, and DTR.SZ  101, 110. Operation is not guaranteed if the DTR format data settings are DTR.ID = 00, DTR. MD = 00, and DTR.SZ  101, 110.) b. If, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that DMA transfer is executed settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ  101, 110 are input in the handshake protocol using the data bus, a transfer request will be asserted for channel 0. c. If  only is asserted by means of the handshake protocol without use of the data bus and a DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE = 1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1. 4. Handshake protocol without use of the data bus a. With the handshake protocol without use of the data bus, a DMA transfer request can be input to the DMAC again for the channel for which transfer was requested immediately before by asserting  only. b. When using the handshake protocol without use of the data bus, first make the necessary settings in the DMAC control registers. c. When not using the handshake protocol without use of the data bus, if  only is asserted without outputting DTR, a request will be issued for the channel for which DMA transfer was requested immediately before. Also, if the first DMA transfer request after a power-on reset is input by asserting  only, it will be ignored and the DMAC will not operate. 5. Direct data transfer mode (valid on channel 2 only) a. If a DMA transfer request for channel 2 is input by simultaneous assertion of
 and  during DMA transfer execution with the handshake protocol without use of the data bus, it will be accepted if there is space in the DDT channel 2 request queue. b. In direct data transfer mode (with
 and  asserted simultaneously),
 is not interpreted as a bus arbitration signal, and therefore the  signal is never asserted. 6. Request queue transfer request acceptance a. The DDT has four request queues for each of channels 1 to 3. When these request queues are full, a DMA transfer request from an external device will be ignored. Rev. 3.0, 04/02, page 547 of 1064 b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished (burst mode) or that a DMA bus cycle is not in progress (cycle steal mode). 7. DTR format a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows. When DTR.ID= 00 • MD = 00, SZ  101, 110: Handshake protocol using the data bus • MD  00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request) • MD = 10, SZ = 110: DDT request queue clear When DTR.ID  00 • Transfer request to channels 1—3 (items other than ID ignored) 8. Data transfer end request a. A data transfer end request (DTR.ID = 00, MD  00, SZ = 111) cannot be accepted during channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway. b. When a transfer end request (DTR.ID = 00, MD  00, SZ = 111) is accepted, the values set in CHCR0.SAR0, DAR0, and DMATCR0 are retained. In this case, execution cannot be restarted from an external device. To restart execution, set CHCR0.DE = 1 with an MOV instruction. 9. Request queue clearance a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are all cleared. All external requests held on the DMAC side are also cleared. b. In case 3-c, the DMAC freeze state can be cleared. c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in case 11, the DMAC freeze state can be cleared. 10.
 assertion a. After
 is asserted, do not assert
 again until  is asserted, as this will result in a discrepancy between the number of
 and  assertions. b. The  assertion period due to
 assertion is one cycle. If a row address miss occurs in a read or write in the non-precharged bank during synchronous DRAM access,  is asserted for a number of cycles in accordance with the RAS precharge interval set in BSC.MCR.TCP. c. It takes one cycle for
 to be accepted by the DMAC after being asserted by an external device. If a row address miss occurs at this time in a read or write in the nonprecharged bank during synchronous DRAM access, and  is asserted, the
 signal asserted by the external device is ignored. Therefore,  is not asserted again due to this signal. Rev. 3.0, 04/02, page 548 of 1064 11. Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode, the DMAC will freeze. This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT mode. 12. Confirming DMA transfer requests and number of transfers executed The channel associated with a DMA bus cycle being executed in response to a DMA transfer request can be confirmed by determining the level of external pins ID1 and ID0 at the rising edge of the CKIO clock while
  is asserted. (ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3) Rev. 3.0, 04/02, page 549 of 1064 14.6 Configuration of the DMAC (SH7751R) 14.6.1 Block Diagram of the DMAC Figure 14.53 is a block diagram of the DMAC in the SH7751R. On-chip peripheral module Internal bus Peripheral bus DMAC module Count control SAR0–7 Registr control DAR0–7 DMATCR0–7 Activation control CHCR0–7 DMAOR TMU SCI, SCIF Request priority control queclr0–7 Bus interface DACK0, DACK1 DRAK0, DRAK1 External address/on-chip peripheral module address dmaqueclr0-7 , 32B data buffer / D[31:0] External bus Bus state controller 8 Request dreq0–7 SAR0, DAR0, DMATCR0, CHCR0 only DDT module DTR command buffer Request controller CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 DBREQ DDTMODE BAVL DDTD ID[1:0] 48 bits id[2:0] tdack DMAOR: SAR: DAR: DMATCR: CHCR: DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register Figure 14.53 Block Diagram of the DMAC Rev. 3.0, 04/02, page 550 of 1064 14.6.2 Pin Configuration (SH7751R) Tables 14.12 and 14.13 show the pin configuration of the DMAC. Table 14.12 DMAC Pins Channel Pin Name 0 DMA transfer request DREQ acceptance confirmation Abbreviation I/O Function
 Input DMA transfer request input from external device to channel 0 DRAK0 Output Acceptance of request for DMA transfer from channel 0 to external device Notification to external device of start of execution DMA transfer end notification 1 DMA transfer request DREQ acceptance confirmation DACK0 Output Strobe output to external device of DMA transfer request from channel 0 to external device
 Input DMA transfer request input from external device to channel 1 DRAK1 Output Acceptance of request for DMA transfer from channel 1 to external device Notification to external device of start of execution DMA transfer end notification DACK1 Output Strobe output to external device of DMA transfer request from channel 1 to external device Rev. 3.0, 04/02, page 551 of 1064 Table 14.13 DMAC Pins in DDT Mode Pin Name Data bus request Data bus available Abbreviation
 (
)  /
 I/O Function Input Data bus release request from external device for DTR format input Output Data bus release notification (DRAK0) Data bus can be used 2 cycles after  is asserted Notification of channel number to external device at same time as 
 output Transfer request signal  (
) Input If asserted 2 cycles after  assertion, DTR format is sent Only  asserted: DMA request
 and  asserted simultaneously: Direct request to channel 2 DMAC strobe 
 Output Reply strobe signal for external device from DMAC Output Notification of channel number to external device at same time as 
 output (DACK0) Channel number notification ID[1:0] (DRAK1, DACK1) (ID [1] = DRAK1, ID [0] = DACK1) Requests for DMA transfer from external devices are normally accepted only on channel 0 (
) and channel 1 (
 ). In DDT mode, the  pin functions as both the data-busavailable pin and channel-number-notification (
) pin. 14.6.3 Register Configuration (SH7751R) Table 14.14 shows the configuration of the DMAC’s registers. The DMAC of the SH7751R has a total of 33 registers: four registers are assigned to each channel, and there is a control register for the overall control of the DMAC. Rev. 3.0, 04/02, page 552 of 1064 Table 14.14 Register Configuration Channel Name 0 1 2 3 Abbreviation Read/ Write Area 7 Initial Value P4 Address Address DMA source address register 0 SAR0 R/W Undefined H'FFA00000 H'1FA00000 32 DMA destination address register 0 DAR0 R/W Undefined H'FFA00004 H'1FA00004 32 DMA transfer count register 0 DMATCR0 R/W Undefined H'FFA00008 H'1FA00008 32 DMA channel control register 0 CHCR0 R/W* H'00000000 H'FFA0000C H'1FA0000C 32 DMA source address register 1 SAR1 R/W Undefined H'FFA00010 H'1FA00010 32 DMA destination address register 1 DAR1 R/W Undefined H'FFA00014 H'1FA00014 32 DMA transfer count register 1 DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32 DMA channel control register 1 CHCR1 R/W* H'00000000 H'FFA0001C H'1FA0001C 32 DMA source address register 2 SAR2 R/W Undefined H'FFA00020 H'1FA00020 32 DMA destination address register 2 DAR2 R/W Undefined H'FFA00024 H'1FA00024 32 DMA transfer count register 2 DMATCR2 R/W Undefined H'FFA00028 H'1FA00028 32 DMA channel control register 2 CHCR2 R/W* H'00000000 H'FFA0002C H'1FA0002C 32 DMA source address register 3 SAR3 R/W Undefined H'FFA00030 H'1FA00030 32 DMA destination address register 3 DAR3 R/W Undefined H'FFA00034 H'1FA00034 32 DMA transfer count register 3 DMATCR3 R/W Undefined H'FFA00038 H'1FA00038 32 DMA channel control register 3 CHCR3 R/W* H'00000000 H'FFA0003C H'1FA0003C 32 DMAOR R/W* H'00000000 H'FFA00040 H'1FA00040 32 Com- DMA operation mon register Access Size Rev. 3.0, 04/02, page 553 of 1064 Table 14.14 Register Configuration (cont) Channel Name 4 5 6 7 Abbreviation Read/ Write Area 7 Initial Value P4 Address Address DMA source address register 4 SAR4 R/W Undefined H'FFA00050 H'1FA00050 32 DMA destination address register 4 DAR4 R/W Undefined H'FFA00054 H'1FA00054 32 DMA transfer count register 4 DMATCR4 R/W Undefined H'FFA00058 H'1FA00058 32 DMA channel control register 4 CHCR4 R/W* H'00000000 H'FFA0005C H'1FA0005C 32 DMA source address register 5 SAR5 R/W Undefined H'FFA00060 H'1FA00060 32 DMA destination address register 5 DAR5 R/W Undefined H'FFA00064 H'1FA00064 32 DMA transfer count register 5 DMATCR5 R/W Undefined H'FFA00068 H'1FA00068 32 DMA channel control register 5 CHCR5 R/W* H'00000000 H'FFA0006C H'1FA0006C 32 DMA source address register 6 SAR6 R/W Undefined H'FFA00070 H'1FA00070 32 DMA destination address register 6 DAR6 R/W Undefined H'FFA00074 H'1FA00074 32 DMA transfer count register 6 DMATCR6 R/W Undefined H'FFA00078 H'1FA00078 32 DMA channel control register 6 CHCR6 R/W* H'00000000 H'FFA0007C H'1FA0007C 32 DMA source address register 7 SAR7 R/W Undefined H'FFA00080 H'1FA00080 32 DMA destination address register 7 DAR7 R/W Undefined H'FFA00084 H'1FA00084 32 DMA transfer count register 7 DMATCR7 R/W Undefined H'FFA00088 H'1FA00088 32 DMA channel control register 7 CHCR7 H'00000000 H'FFA0008C H'1FA0008C 32 R/W* Access Size Notes: Longword access should be used for all control registers. If a different access width is used, reads will return all 0s and writes will not be possible. * Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after being read as 1, to clear the flags. Rev. 3.0, 04/02, page 554 of 1064 14.7 Register Descriptions (SH7751R) 14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA source address registers 0–7 (SAR0–SAR7) are 32-bit readable/writable registers that specify the source address for a DMA transfer. The functions of these registers are the same as on the SH7751. For more information, see section 14.2.1, DMA Source Address Registers 0–3 (SAR0–SAR3). 14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA destination address registers 0–7 (DAR0–DAR7) are 32-bit readable/writable registers that specify the destination address for a DMA transfer. The functions of these registers are the same as on the SH7751. For more information, see section 14.2.2, DMA Destination Address Registers 0–3 (DAR0–DAR3). Rev. 3.0, 04/02, page 555 of 1064 14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 — — — — — — — — R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA transfer count registers 0–7 (DMATCR0–DMATCR7) are 32-bit readable/writable registers that specify the number of transfers in transfer operations for the corresponding channel (bytecount, word count, longword count, quadword count, or 32-byte count). Functions of these registers are the same as the transfer-count registers of the SH7751. For more information, see section 14.2.3, DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3). 14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7) Bit: 31 30 29 28 27 26 25 24 SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 — — — — DS RL AM AL 0 0 0 0 0 0 0 0 R R R R 7 6 5 4 TM 0 R/W (R/W) R/W (R/W) 3 TS2 TS1 TS0 QCL 0 0 0 0 2 1 0 IE TE DE 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) R/W DMA channel control registers 0–7(CHCR0–CHCR7) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information about the PCMCIA interface, see section 13.3.7, PCMCIA Interface. No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should always be 0. These bits are always read as 0. Rev. 3.0, 04/02, page 556 of 1064 These registers are initialized to H'00000000 by a power-on or manual reset. Their values are retained in standby, sleep, and deep-sleep modes. Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2SSA0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the DSA2–DSA0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait cycle control for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0. Bit 19—
 Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the
 pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external device of the acceptance of
) is an active-high or active-low output. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. Rev. 3.0, 04/02, page 557 of 1064 In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR1–CHCR7. (DDT mode:
 ) For details of the settings, see the description of the AM bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. For details of the settings, see the description of the DM1 and DM0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. For details of the settings, see the description of the RS3–RS0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0– CHCR3). Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For details of the settings, see the description of the TS2–TS0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 3Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. This bit is only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1. Rev. 3.0, 04/02, page 558 of 1064 CHCR Bit 3 QCL Description 0 This bit is always read as 0. (Initial value) Writing a 0 to this bit is invalid. 1 When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the DDT side and any external requests stored in the DMAC. The written value is not retained. Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated after the number of data transfers specified in DMATCR (when TE = 1). For details of the settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0– CHCR3). Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3). 14.7.5 DMA Operation Register (DMAOR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — DDT DBL Initial value: 0 0 R/W: R/W R/W 0 0 0 0 R R R R PR1 PR0 0 0 R/W R/W 0 0 0 0 0 R R R R R AE NMIF DME 0 0 0 R/(W) R/(W) R/W DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode. Rev. 3.0, 04/02, page 559 of 1064 DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0. Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 14Number of DDT-Mode Channels (DBL): Selects the number of channels that are able to accept external requests in DDT mode. Bit 14: DBL Description 0 Four DDT-mode channels 1 Eight DDT-mode channels (Initial value) Note: When DMAOR.DBL = 0, channels 4 to 7 do not accept external requests. When DMAOR.DBL = 1, one channel can be selected from among channels 0–7 by the combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.15 shows the channel selection by DTR format in the DDT mode. Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)  101 DTR.ID[1:0] DTR.SZ[2:0] 00 CH0 CH4 01 CH1 CH5 10 CH2 CH6 11 CH3 CH7 31 DTR.SZ[2:0] = 101 29 28 27 26 25 24 23 SZ ID MD 16 COUNT* 0 (Reserved) Reserved Note: * These bits are valid when request queue clear is specified (with no transfer count function). Figure 14.54 DTR Format (Transfer Request Format) (SH7751R) Rev. 3.0, 04/02, page 560 of 1064 Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. DMAOR Bit 9 DMAOR Bit 8 PR1 PR0 Description 0 0 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 0 1 CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 1 0 CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 1 1 Round robin mode (Initial value) Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are suspended. Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the DME bit in section 14.2.5, DMA Operation Register (DMAOR) Rev. 3.0, 04/02, page 561 of 1064 14.8 Operation (SH7751R) Operation specific to the SH7751R is described here. For details of operation, see section 14.3, Operation. 14.8.1 Channel Specification for a Normal DMA Transfer In normal DMA transfer mode, the DMAC always operates with eight channels, and external requests are only accepted on channel 0 (
) and channel 1 (
 ). After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR, DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends when the transfer-end condition is satisfied. There are three modes for transfer requests: autorequest, external request, and on-chip peripheral module request. The addressing modes for DMA transfer are the single-address mode and the dual-address mode. Bus mode is selectable between burst mode and cycle steal mode. 14.8.2 Channel Specification for DDT-Mode DMA Transfer For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels. External requests are accepted on channels 0–3 when DMAOR.DBL = 0, and on channels 0–7 when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in section 14.7.5, DMA Operation Register (DMAOR). 14.8.3 Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used. For more details, see section 14.5, On-Demand Transfer Mode (DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of
  assertion) assertion of 
 from the  (bus-release notification) pin are used to notify the external device of the DMAC channel that is to be used (see table 14.16, Notification of Transfer Channel in Eight-Channel DDT Mode). When the DMAC is set up for eight-channel external request acceptance in DDT mode (DMAOR.DBL = 1), it is important to note that the  pin has the two functions as shown in table 14.17. Rev. 3.0, 04/02, page 562 of 1064 Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode  /
 ID[1:0] Transfer Channel 1 00 CH0 01 CH1 10 CH2 11 CH3 00 CH4 01 CH5 10 CH6 11 CH7 0 Table 14.17 Function of  
 = High 
 = Low 14.8.4 Function of  Bus available (data-bus enabled) Notification of channel number (
) Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1. Table 14.18 shows the DTR format settings for clearing request queues. Rev. 3.0, 04/02, page 563 of 1064 Table 14.18 DTR Format for Clearing Request Queues DMAOR.DBL DTR.ID DTR.MD DTR.SZ DTR.COUNT[7:4] Description 0 10 110 * Clear the request queues of all channels (1–7). 00 Clear the CH0 request-accepted flag Setting prohibited 11 1 00 10 110 * Clear the request queues of all channels (1–7). 0001 Clear the CH0 request-accepted flag 0010 Clear the CH1 request queues. 0011 Clear the CH2 request queues. 0100 Clear the CH3 request queues. 0101 Clear the CH4 request queues. 0110 Clear the CH5 request queues. 0111 Clear the CH6 request queues. 1000 Clear the CH7 request queues. Clear the CH0 request-accepted flag. 11 Note: (SH7751R) DTR.SZ = DTR[31:29], DTR.ID = DTR[27:26], DTR.MD = DTR[25:24], DTR.COUNT[7:4] = DTR[23:20] 14.8.5 Interrupt-Request Codes When the number of transfers specified in DMATCR has been finished and the interrupt request is enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each channel. Table 14.19 lists the interrupt-request codes that are associated with these transfer-end interrupts. Rev. 3.0, 04/02, page 564 of 1064 CKIO / RA A25–A0 CA DTR D63–D0 RAS, CAS, WE D0 BA D1 D2 RD ID1, ID0 00 Figure 14.55 Single Address Mode/Burst Mode/External Bus  External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Table 14.19 DMAC Interrupt-Request Codes Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer-end interrupt H'640 High DMTE1 CH1 transfer-end interrupt H'660 DMTE2 CH2 transfer-end interrupt H'680 DMTE3 CH3 transfer-end interrupt H'6A0 DMTE4 CH4 transfer-end interrupt H'780 DMTE5 CH5 transfer-end interrupt H'7A0 DMTE6 CH6 transfer-end interrupt H'7C0 DMTE7 CH7 transfer-end interrupt H'7E0 DMAE Address error interrupt H'6C0 Low DMTE4–DMTE7: These codes are not used in the SH7751. Rev. 3.0, 04/02, page 565 of 1064 CKIO / RA A25–A0 D63–D0 RAS, CAS, WE ID1, ID0 CA DTR D0 BA D1 RD 00 Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus  External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 Rev. 3.0, 04/02, page 566 of 1064 D2 14.9 Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7751 or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0– DMATCR7, and CHCR0–CHCR7 in the SH7751R, first clear the DE bit for the relevant channel to 0. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating. Confirmation method when DMA transfer is not executed correctly: With the SH7751, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR3, and DMATCR0–DMATCR3. With the SH7751R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR0–CHCR7, and DMATCR0–DMATCR7. If NMIF was set before the transfer, the DMATCR transfer count will remain at the set value. If NMIF was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR0–CHCR3 in the SH7751 or CHCR0– CHCR7 in the SH7751R, the DMATCR value will indicate the remaining number of transfers. Also, the next addresses to be accessed can be found by reading SAR0–SAR3 and DAR0– DAR3 in the SH7751 or SAR0–SAR7 and DAR0–DAR7 in the SH7751R. If the AE bit has been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to the module standby state, standby mode, or deep sleep mode. Either check that TE = 1 in the SH7751’s CHCR0–CHCR3 or in the SH7751R’s CHCR0– CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0 in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, CCN, BSC, UBC, or PCIC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the relevant channel before setting DE to 1 in CHCR, or make the register settings with DE cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1 in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set. Rev. 3.0, 04/02, page 567 of 1064 Rev. 3.0, 04/02, page 568 of 1064 Section 15 Serial Communication Interface (SCI) 15.1 Overview The SH7751 Series is equipped with a single-channel serial communication interface (SCI) and a single-channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. The SCI supports a smart card interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface function for IC card interface use. For details, see section 17, Smart Card Interface. The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO registers for both transmission and reception. For details, see section 16, Serial Communication Interface with FIFO (SCIF). 15.1.1 Features SCI features are listed below.
Choice of synchronous or asynchronous serial communication mode  Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided that enables serial data communication with a number of processors. There is a choice of 12 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: A break can be detected by reading the RxD pin level directly from the serial port register (SCSPTR1) when a framing error occurs.  Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. Rev. 3.0, 04/02, page 569 of 1064 There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors
Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data.
On-chip baud rate generator allows any bit rate to be selected.
Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin
Four interrupt sources There are four interrupt sources—transmit-data-empty, transmit-end, receive-data-full, and receive-error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer.
When not in use, the SCI can be stopped by halting its clock supply to reduce power consumption. Rev. 3.0, 04/02, page 570 of 1064 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 TxD Parity generation SCSSR1 SCSCR1 SCSMR1 SCSPTR1 Transmission/ reception control Internal data bus SCBRR1 Pφ Baud rate generator Pφ/4 Pφ/16 Pφ/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 15.1 Block Diagram of SCI Rev. 3.0, 04/02, page 571 of 1064 15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation I/O Function Serial clock pin SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/
bit in SCSMR1. Break state transmission and detection, can be set in the SCI’s SCSPTR1 register. 15.1.4 Register Configuration The SCI has the internal registers shown in table 15.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform transmitter/receiver control. With the exception of the serial port register, the SCI registers are initialized in standby mode and in the module standby state as well as after a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 15.2 SCI Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 Serial status register SCSSR1 R/(W)* H'84 H'FFE00010 H'1FE00010 8 Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 H'FFE0001C H'1FE0001C 8 Serial port register SCSPTR1 1 R/W Notes: *1 Only 0 can be written, to clear flags. *2 The value of bits 2 and 0 is undefined Rev. 3.0, 04/02, page 572 of 1064 2 H'00* 15.2 Register Descriptions 15.2.1 Receive Shift Register (SCRSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCRDR1 automatically. SCRSR1 cannot be directly read or written to by the CPU. 15.2.2 Receive Data Register (SCRDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for reception. Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data continuously. SCRDR1 is a read-only register, and cannot be written to by the CPU. SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 3.0, 04/02, page 573 of 1064 15.2.3 Transmit Shift Register (SCTSR1) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1. SCTSR1 cannot be directly read or written to by the CPU. 15.2.4 Transmit Data Register (SCTDR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1. SCTDR1 can be read or written to by the CPU at all times. SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 3.0, 04/02, page 574 of 1064 15.2.5 Serial Mode Register (SCSMR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/
CHR PE O/ STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCSMR1 is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Communication Mode (C/
): Selects asynchronous mode or synchronous mode as the SCI operating mode. Bit 7: C/
Description 0 Asynchronous mode 1 Synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR Description 0 8-bit data 1 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted. Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/ bit. Rev. 3.0, 04/02, page 575 of 1064 Bit 4—Parity Mode (O/): Selects either even or odd parity for use in parity addition and checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/ bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4: O/ Description 0 Even parity* 1 2 1 (Initial value) Odd parity* Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added. Bit 3: STOP Description 0 1 stop bit* 1 1 (Initial value) 2 2 stop bits* Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. *2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Rev. 3.0, 04/02, page 576 of 1064 Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/ bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication Function. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from P , P/4, P/16, and P/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 P
clock 1 P
/4 clock 1 0 P
/16 clock 1 P
/64 clock (Initial value) Note: P
: Peripheral clock 15.2.6 Serial Control Register (SCSCR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Rev. 3.0, 04/02, page 577 of 1064 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE Description 0 Transmit-data-empty interrupt (TXI) request disabled* 1 Transmit-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5: TE Description 0 Transmission disabled* 1 Transmission enabled* 1 (Initial value) 2 Notes: *1 The TDRE flag in SCSSR1 is fixed at 1. *2 In this state, serial transmission is started when transmit data is written to SCTDR1 and the TDRE flag in SCSSR1 is cleared to 0. SCSMR1 setting must be performed to decide the transmit format before setting the TE bit to 1. Rev. 3.0, 04/02, page 578 of 1064 Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE Description 0 Reception disabled* 1 2 Reception enabled* 1 (Initial value) Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. *2 Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SCSMR1 setting must be performed to decide the receive format before setting the RE bit to 1. Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description 0 Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] 1  When the MPIE bit is cleared to 0  When data with MPB = 1 is received Multiprocessor interrupts enabled* Note: * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt (TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data transmission. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) request disabled* 1 Transmit-end interrupt (TEI) request enabled* (Initial value) Note: * TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. Rev. 3.0, 04/02, page 579 of 1064 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining the SCI’s operating mode with SCSMR1. For details of clock source selection, see table 15.9 in section 15.3, Operation. Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Asynchronous mode Internal clock/SCK pin functions as 1 input pin (input signal ignored)* Synchronous mode Internal clock/SCK pin functions as 1 serial clock output* Asynchronous mode Internal clock/SCK pin functions as 2 clock output* Synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as 3 clock input* Synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as 3 clock input* Synchronous mode External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: *1 Initial value *2 Outputs a clock of the same frequency as the bit rate. *3 Inputs a clock with a frequency 16 times the bit rate. Rev. 3.0, 04/02, page 580 of 1064 15.2.7 Serial Status Register (SCSSR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 — 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE Description 0 Valid transmit data has been written to SCTDR1 [Clearing conditions] 1  When 0 is written to TDRE after reading TDRE = 1  When data is written to SCTDR1 by the DMAC There is no valid transmit data in SCTDR1 (Initial value) [Setting conditions]  Power-on reset, manual reset, standby mode, or module standby  When the TE bit in SCSCR1 is 0  When data is transferred from SCTDR1 to SCTSR1 and data can be written to SCTDR1 Rev. 3.0, 04/02, page 581 of 1064 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF Description 0 There is no valid receive data in SCRDR1 (Initial value) [Clearing conditions] 1  Power-on reset, manual reset, standby mode, or module standby  When 0 is written to RDRF after reading RDRF = 1  When data in SCRDR1 is read by the DMAC There is valid receive data in SCRDR1 [Setting condition] When serial reception ends normally and receive data is transferred from SCRSR1 to SCRDR1 Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCSCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1  Power-on reset, manual reset, standby mode, or module standby  When 0 is written to ORER after reading ORER = 1 2 An overrun error occurred during reception* [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 The receive data prior to the overrun error is retained in SCRDR1, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued either. Rev. 3.0, 04/02, page 582 of 1064 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1  Power-on reset, manual reset, standby mode, or module standby  When 0 is written to FER after reading FER = 1 A framing error occurred during reception [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 2 when reception ends, and the stop bit is 0* Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1  Power-on reset, manual reset, standby mode, or module standby  When 0 is written to PER after reading PER = 1 A parity error occurred during reception* 2 [Setting condition] When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/ bit in SCSMR1 Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCSCR1 is cleared to 0. *2 If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. Rev. 3.0, 04/02, page 583 of 1064 Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND Description 0 Transmission is in progress [Clearing conditions] 1  When 0 is written to TDRE after reading TDRE = 1  When data is written to SCTDR1 by the DMAC Transmission has been ended (Initial value) [Setting conditions]  Power-on reset, manual reset, standby mode, or module standby  When the TE bit in SCSCR1 is 0  When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit character Bit 1—Multiprocessor Bit (MPB): This bit is read-only and cannot be written to. The read value is undefined. Note: This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode, however, this does not function correctly in this LSI. Do not use the read value from this bit. Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission. Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether transmission has been completed before changing its value. Bit 0: MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Rev. 3.0, 04/02, page 584 of 1064 (Initial value) 15.2.8 Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 EIO — — — 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SPB1IO SPB1DT SPB0IO SPB0DT SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. Bit 7: EIO Description 0 When the RIE bit is 1, RXI and ERI interrupts are sent to INTC(Initial value) 1 When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin (Initial value) Rev. 3.0, 04/02, page 585 of 1064 Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined. Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level Rev. 3.0, 04/02, page 586 of 1064 SCI I/O port block diagrams are shown in figures 15.2 to 15.4. Reset R Q D SPB1IO C SPTRW Internal data bus Reset SCK Q R D SPB1DT C SPTRW SCI Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1. Figure 15.2 SCK Pin Rev. 3.0, 04/02, page 587 of 1064 Reset R Q D SPB0IO C Internal data bus SPTRW Reset TxD R Q D SPB0DT C SPTRW SCI Transmit enable signal Serial transmit data SPTRW: Write to SPTR Figure 15.3 TxD Pin SCI RxD Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 15.4 RxD Pin Rev. 3.0, 04/02, page 588 of 1064 15.2.9 Bit Rate Register (SCBRR1) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state. The SCBRR1 setting is found from the following equations. Asynchronous mode: N= Pφ × 106 – 1 64 × 22n–1 × B Synchronous mode: N= Where B: N: P: n: Pφ × 106 – 1 8 × 22n–1 × B Bit rate (bits/s) SCBRR1 setting for baud rate generator (0  N  255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR1 Setting n Clock CKS1 CKS0 0 P
0 0 1 P
/4 0 1 2 P
/16 1 0 3 P
/64 1 1 Rev. 3.0, 04/02, page 589 of 1064 The bit rate error in asynchronous mode is found from the following equation: Error (%) = Pφ × 106 – 1 × 100 (N + 1) × B × 64 × 22n–1 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode. Rev. 3.0, 04/02, page 590 of 1064 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode P
(MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34 9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 –18.62 0 1 –14.67 0 1 0.00 P
(MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73 31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 Legend Blank: No setting is available. —: A setting is available but error occurs. Rev. 3.0, 04/02, page 591 of 1064 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) P
(MHz) 6 6.144 7.37288 8 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99 P
(MHz) 9.8304 10 12 12.288 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00 Rev. 3.0, 04/02, page 592 of 1064 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) P
(MHz) 14.7456 16 19.6608 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 86 0.31 3 88 –0.25 150 2 191 0.00 2 207 0.16 2 255 0.00 3 64 0.16 300 2 95 0.00 2 103 0.16 2 127 0.00 2 129 0.16 600 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 1200 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 2400 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 4800 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 9600 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 19200 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36 31250 0 14 –1.70 0 15 0.00 0 19 –1.70 0 19 0.00 38400 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 P
(MHz) 24 24.576 28.7 30 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 106 –0.44 3 108 0.08 3 126 0.31 3 132 0.13 150 3 77 0.16 3 79 0.00 3 92 0.46 3 97 –0.35 300 2 155 0.16 2 159 0.00 2 186 –0.08 2 194 0.16 600 2 77 0.16 2 79 0.00 2 92 0.46 2 97 –0.35 1200 1 155 0.16 1 159 0.00 1 186 –0.08 1 194 0.16 2400 1 77 0.16 1 79 0.00 1 92 0.46 1 97 –0.35 4800 0 155 0.16 0 159 0.00 0 186 –0.08 0 194 –1.36 9600 0 77 0.16 0 79 0.00 0 92 0.46 0 97 –0.35 19200 0 38 0.16 0 39 0.00 0 46 –0.61 0 48 –0.35 31250 0 23 0.00 0 24 –1.70 0 28 –1.03 0 29 0.00 38400 0 19 –2.34 0 19 0.00 0 22 1.55 0 23 1.73 Rev. 3.0, 04/02, page 593 of 1064 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode P
(MHz) 4 8 16 28.7 30 Bit Rate (bits/s) n N n N n N n N n N 10 — — — — — — — — — — 250 2 249 3 124 3 249 — — — — 500 2 124 2 249 3 124 3 223 3 233 1k 1 249 2 124 2 249 3 111 3 116 2.5k 1 99 1 199 2 99 2 178 2 187 5k 0 199 1 99 1 199 2 89 2 93 10k 0 99 0 199 1 99 1 178 1 187 25k 0 39 0 79 0 159 1 71 1 74 50k 0 19 0 39 0 79 0 143 0 149 100k 0 9 0 19 0 39 0 71 0 74 250k 0 3 0 7 0 15 — — 0 29 500k 0 1 0 3 0 7 — — 0 14 1M 0 0* 0 1 0 3 — — — — 0 0* 0 1 — — — — 2M Note: As far as possible, the setting should be made so that the error is within 1%. Blank: No setting is available. —: A setting is available but error occurs. *: Continuous transmission/reception is not possible. Rev. 3.0, 04/02, page 594 of 1064 Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P
(MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0 Rev. 3.0, 04/02, page 595 of 1064 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P
(MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) P
(MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0 Rev. 3.0, 04/02, page 596 of 1064 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9.
Asynchronous mode  Data length: Choice of 7 or 8 bits  Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length)  Detection of framing, parity, and overrun errors, and breaks, during reception  Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used).
Synchronous mode  Transfer format: Fixed 8-bit data  Detection of overrun errors during reception  Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip. When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock. Rev. 3.0, 04/02, page 597 of 1064 Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: CHR MP PE STOP Mode C/
Data Length Multiprocessor Parity Stop Bit Bit Bit Length 0 8-bit data No 0 0 0 0 1 Asynchronous mode Yes 1 1 0 7-bit data No 1 1 0 * 1 0 1 Yes * * * * 1 bit 2 bits Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes Synchronous mode No No 1 bit 2 bits 1 bit 1 1 1 bit 2 bits 0 1 0 1 bit 2 bits 0 1 1 bit 2 bits 0 1 No 2 bits 8-bit data None Note: An asterisk in the table means “Don’t care.” Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting Bit 7: C/
Bit 1: CKE1 Bit 0: CKE0 0 0 0 1 1 SCI Transmit/Receive Clock Mode Asynchronous mode 0 Clock Source SCK Pin Function Internal SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 1 1 0 1 Rev. 3.0, 04/02, page 598 of 1064 Synchronous mode 15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-bycharacter basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.5 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data (LSB) 0 D0 Start bit 1 bit 1 (MSB) D1 D2 D3 D4 D5 D6 D7 Transmit/receive data 7 or 8 bits 0/1 1 1 Parity bit Stop bit(s) 1 bit, or none 1 or 2 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR1 setting. Rev. 3.0, 04/02, page 599 of 1064 Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 2 3 4 5 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 * 1 0 S 8-bit data MPB STOP 0 * 1 1 S 8-bit data MPB STOP STOP 1 * 1 0 S 7-bit data MPB STOP 1 * 1 1 S 7-bit data MPB STOP STOP Note: An asterisk in the table means “Don’t care.” S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 3.0, 04/02, page 600 of 1064 6 7 8 9 10 11 12 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 15.7 shows a sample SCI initialization flowchart. Rev. 3.0, 04/02, page 601 of 1064 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR1 to 0 When clock output is selected in asynchronous mode, it is output immediately after SCSCR1 settings are made. Set CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 2. Set the data transfer format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set data transfer format in SCSMR1 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Set value in SCBRR1 Wait 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits No Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCI will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 15.7 Sample SCI Initialization Flowchart Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Rev. 3.0, 04/02, page 602 of 1064 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes Read TEND flag in SCSSR1 TEND = 1? No 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) 3. Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR1 to 0. Yes Break output? No Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR1 to 0 End of transmission Figure 15.8 Sample Serial Transmission Flowchart Rev. 3.0, 04/02, page 603 of 1064 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is set to 1 at this time, a TEI interrupt request is generated. Figure 15.9 shows an example of the operation for transmission in asynchronous mode. Rev. 3.0, 04/02, page 604 of 1064 Start bit 1 Serial data 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler TEI interrupt request One frame Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. Rev. 3.0, 04/02, page 605 of 1064 Start of reception Read ORER, PER, and FER flags in SCSSR1 PER or FER or ORER = 1? No Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 Yes Error handling 1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. 2. SCI status check and receive data read : Read SCSSR1 and check that RDRF = 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. 3. Serial reception continuation procedure: To continue serial reception, complete zeroclearing of the RDRF flag before the stop bit for the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by an RXI interrupt and the SCRDR1 value is read.) End of reception Figure 15.10 Sample Serial Reception Flowchart (1) Rev. 3.0, 04/02, page 606 of 1064 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling No Clear RE bit in SCSCR1 to 0 PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 End Figure 15.10 Sample Serial Reception Flowchart (2) Rev. 3.0, 04/02, page 607 of 1064 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SCSMR1. b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Note: No further receive operations can be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. A receive-data-full request is always output to the DMAC when the RDRF flag changes to 1. Table 15.11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER Reception of next data is completed while RDRF flag in SCSSR1 is set to 1 Receive data is not transferred from SCRSR1 to SCRDR1 Framing error FER Stop bit is 0 Receive data is transferred from SCRSR1 to SCRDR1 Parity error PER Received data parity differs from that (even or odd) set in SCSMR1 Receive data is transferred from SCRSR1 to SCRDR1 Figure 15.11 shows an example of the operation for reception in asynchronous mode. Rev. 3.0, 04/02, page 608 of 1064 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 0/1 RDRF FER RXI interrupt request One frame SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Rev. 3.0, 04/02, page 609 of 1064 Note: Even when this LSI has received data with a 0 multiprocessor bit that was meant to be sent to another station, the RDRF flag in SCSSR1 is set to 1. When the RDRF flag in SCSSR1 is set to 1, the exception handling routine reads the MPIE bit in SCSCR1, and skips the receive data if the MPIE bit is 1. Skipping of unnecessary data is achieved by collaborative operation with the exception handling routine. Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle: Receiving station specification (MPB = 0) Data transmission cycle: Data transmission to receiving station specified by ID MPB: Multiprocessor bit Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 3.0, 04/02, page 610 of 1064 Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2. Data Transfer Operations Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for multiprocessor serial data transmission. Use the following procedure for multiprocessor serial data transmission after enabling the SCI for transmission. Rev. 3.0, 04/02, page 611 of 1064 Start of transmission Read TEND flag in SCSSR1 TEND = 1? No 2. Preparation for data transfer: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1. Yes Set MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1 3. Serial data transmission: Write the first transmit data to SCTDR1, then clear the TDRE flag to 0. Clear TDRE flag to 0 Read TEND flag in SCSSR1 TEND = 1? 1. SCI status check and ID data write: Read SCSSR1 and check that the TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0. No Yes Clear MPBT bit in SCSSR1 to 0 To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Write data to SCTDR1 Clear TDRE flag to 0 Read TDRE flag in SCSSR1 TDRE = 1? No Yes No All data transmitted? Yes End of transmission Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart Rev. 3.0, 04/02, page 612 of 1064 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. The serial transmit data is sent from the TxD pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The order of transmission is the same as in step 2. Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format. Rev. 3.0, 04/02, page 613 of 1064 1 Serial data Start bit 0 Multiproces- Stop sor bit bit Data D0 D1 D7 1 1 Start bit 0 Data D0 D1 Multiproces- Stop Start bit sor bit bit D7 0 1 0 Data D0 D1 Multiproces- Stop sor bit bit D7 0 1 Idle state (mark state) TDRE TEND Data written to SCTDR1 and TDRE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request TEI interrupt request MPBT bit cleared to 0, data written to SCTDR1, and TDRE flag cleared to 0 by TEI interrupt handler Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for multiprocessor serial reception. Use the following procedure for multiprocessor serial data reception after enabling the SCI for reception. Rev. 3.0, 04/02, page 614 of 1064 Start of reception 1. ID reception cycle: Set the MPIE bit in SCSCR1 to 1. Set MPIE bit in SCSCR1 to 1 2. SCI status check, ID reception and comparison: Read SCSSR1 and SCSCR1, and check that the RDRF flag is set to 1 and the MPIE bit is set to 0, then read the receive data in SCRDR1 and compare it with this station’s ID. Read ORER and FER flags in SCSSR1 FER = 1? or ORER = 1? Yes If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. No Read RDRF flag in SCSSR1 Read MPIE bit in SCSCR1 No 3. SCI status check and data reception: Read SCSSR1 and check that the RDRF flag is set to 1, then read the data in SCRDR1. RDRF = 1 and MPIE = 0? Yes Read receive data in SCRDR1 No This station’s ID? Yes Read ORER and FER flags in SCSSR1 FER = 1? or ORER = 1? Yes No Read RDRF flag in SCSSR1 RDRF = 1? 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR1 to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. No Yes Read receive data in SCRDR1 All data received? Yes No Error handling End of reception Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.0, 04/02, page 615 of 1064 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 End Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.0, 04/02, page 616 of 1064 Figure 15.16 shows an example of SCI operation for multiprocessor format reception. 1 Start Data (ID1) bit Serial data 0 D0 D1 Stop Start MPB bit bit D7 1 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 Idle state (mark state) 1 MPIE RDRF SCRDR1 value ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data is not this station’s ID, MPIE bit is set to 1 again RXI interrupt request The RDRF flag is cleared to 0 by is the RXI interrupt handler (a) Data does not match station’s ID 1 Start Data (ID2) bit Serial data 0 D0 D1 Stop Start MPB bit bit D7 1 1 0 Data (Data2) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF SCRDR1 value ID2 ID1 RXI interrupt request (multiprocessor interrupt) MPIE = 0 SCRDR1 data read and RDRF flag cleared to 0 by RXI interrupt handler As data matches this station’s ID, reception continues and data is received by RXI interrupt handler Data2 MPIE bit set to 1 again (b) Data matches station’s ID Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.0, 04/02, page 617 of 1064 In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit position. If the multiprocessor bit is 0, the MPIE bit is not changed. 4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1. 15.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.17 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don’t care Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Note: * High except in continuous transfer Figure 15.17 Data Format in Synchronous Communication Rev. 3.0, 04/02, page 618 of 1064 Bit 7 Don’t care In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock. Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before the end of bit 7. Data Transfer Operations SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1. Figure 15.18 shows a sample SCI initialization flowchart. Rev. 3.0, 04/02, page 619 of 1064 1. Set the clock selection in SCSCR1. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Initialization Clear TE and RE bits in SCSCR1 to 0 2. Set the data transfer format in SCSMR1. 3. Write a value corresponding to the bit rate into SCBRR1. (Not necessary if an external clock is used.) Set RIE, TIE, TEIE, MPIE, CKE1 and CKE0 bits in SCSCR1 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR1 to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SCSMR1 Set value in SCBRR1 Wait 1-bit interval elapsed? No Yes Set TE and RE bits in SCSCR1 to 1, and set RIE, TIE, TEIE, and MPIE bits End Figure 15.18 Sample SCI Initialization Flowchart Rev. 3.0, 04/02, page 620 of 1064 Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Start of transmission Read TDRE flag in SCSSR1 TDRE = 1? No Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 All data transmitted? No Yes 2. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1, and then clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the direct memory access controller (DMAC) is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1.) Read TEND flag in SCSSR1 TEND = 1? No Yes Clear TE bit in SCSCR1 to 0 End Figure 15.19 Sample Serial Transmission Flowchart Rev. 3.0, 04/02, page 621 of 1064 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. 4. After completion of serial transmission, the SCK pin is fixed high. Figure 15.20 shows an example of SCI operation in transmission. Transfer direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Data written to SCTDR1 and TDRE flag cleared to 0 in TXI interrupt handler TXI interrupt request One frame Figure 15.20 Example of SCI Transmit Operation Rev. 3.0, 04/02, page 622 of 1064 TEI interrupt request Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Start of reception Read ORER flag in SCSSR1 Yes ORER = 1? No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data received? Yes Clear RE bit in SCSCR1 to 0 End of reception 1. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. 2. SCI status check and receive data read: Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. (The RDRF flag is cleared automatically when the direct memory access controller (DMAC) is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Figure 15.21 Sample Serial Reception Flowchart (1) Rev. 3.0, 04/02, page 623 of 1064 Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR1 to 0 End Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from SCRSR1 to SCRDR1. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If a receive error is detected in the error check, the operation is as shown in table 15.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0. 3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 15.22 shows an example of SCI operation in reception. Rev. 3.0, 04/02, page 624 of 1064 Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Data read from SCRDR1 and RDRF flag cleared to 0 in RXI interrupt handler RXI interrupt request ERI interrupt request due to overrun error One frame Figure 15.22 Example of SCI Receive Operation Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.23 shows a sample flowchart for simultaneous serial transmit and receive operations. Use the following procedure for simultaneous serial data transmit and receive operations after enabling the SCI for transmission and reception. Rev. 3.0, 04/02, page 625 of 1064 Start of transmission/reception Read TDRE flag in SCSSR1 No TDRE = 1? Yes Write transmit data to SCTDR1 and clear TDRE flag in SCSSR1 to 0 1. SCI status check and transmit data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. 2. Receive error handling: If a receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. 3. SCI status check and receive data read: Read ORER flag in SCSSR1 Read SCSSR1 and check that the RDRF flag is set to 1, then read the receive data in SCRDR1 and clear the Yes ORER = 1? RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. No Error handling Read RDRF flag in SCSSR1 No RDRF = 1? Yes Read receive data in SCRDR1, and clear RDRF flag in SCSSR1 to 0 No All data transferred? Yes Clear TE and RE bits in SCRSR1 to 0 End of transmission/reception 4. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, finish reading the RDRF flag, reading SCRDR1, and clearing the RDRF flag to 0, before the MSB (bit 7) of the current frame is received. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR1 and clear the TDRE flag to 0. (Checking and clearing of the TDRE flag is automatic when the DMAC is activated by a transmit-data-empty interrupt (TXI) request, and data is written to SCTDR1. Similarly, the RDRF flag is cleared automatically when the DMAC is activated by a receive-data-full interrupt (RXI) request and the SCRDR1 value is read.) Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1. Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception Rev. 3.0, 04/02, page 626 of 1064 15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is generated separately from the interrupt request. A TDR-empty request can activate the direct memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0 automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC. When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the interrupt request. An RDR-full request can activate the DMAC to perform data transfer. The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is performed by the DMAC. When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated. The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be carried out by the DMAC and receive error handling is to be performed by means of an interrupt to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be generated even during normal data reception. When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC cannot be activated by a TEI interrupt request. A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the transmit operation has ended. Table 15.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Receive error (ORER, FER, or PER) Not possible High RXI Receive data register full (RDRF) Possible  TXI Transmit data register empty (TDRE) Possible  TEI Transmit end (TEND) Not possible Low See section 5, Exceptions, for the priority order and relation to non-SCI interrupts. Rev. 3.0, 04/02, page 627 of 1064 15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1. Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to SCTDR1. Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is not transferred from SCRSR1 to SCRDR1, and the receive data is lost. Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Errors RDRF ORER FER PER Receive Data Transfer SCRSR1  SCRDR1 Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X O: Receive data is transferred from SCRSR1 to SCRDR1. X: Receive data is not transferred from SCRSR1 to SCRDR1. Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1 again. Rev. 3.0, 04/02, page 628 of 1064 Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of its current state, and the TxD pin becomes an output port outputting the value 0. Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.24. Rev. 3.0, 04/02, page 629 of 1064 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ................. (1) 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1/(2  16))  100% = 46.875% ............................................ (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 3.0, 04/02, page 630 of 1064 When Using the DMAC: When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated. (See figure 15.25) SCK t TDRE TxD D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t > 4. Figure 15.25 Example of Synchronous Transmission by DMAC When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as the activation source with bits RS3 to RS0 in CHCR. When Using Synchronous External Clock Mode:
Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock SCK has changed from 0 to 1.
Only set both TE and RE to 1 when external clock SCK is 1.
In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero 1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF will be set to 1 but copying to SCRDR1 will not be possible. When Using DMAC: When using the DMAC for transmission/reception, make a setting to suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program. Rev. 3.0, 04/02, page 631 of 1064 Rev. 3.0, 04/02, page 632 of 1064 Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview The SH7751 Series is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1.1 Features SCIF features are listed below.
Asynchronous serial communication Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even/odd/none  Receive error detection: Parity, framing, and overrun errors  Break detection: If the receive data following that in which a framing error occurred is also at the space “0” level, and there is a frame error, a break is detected. When a framing error occurs, a break can also be detected by reading the RxD2 pin level directly from the serial port register (SCSPTR2).
Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and continuous serial data transmission and reception.
On-chip baud rate generator allows any bit rate to be selected.
Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin Rev. 3.0, 04/02, page 633 of 1064 
Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently.
The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption.
Modem control functions (
 and ) are provided.
The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained.
A timeout error (DR) can be detected during reception. Rev. 3.0, 04/02, page 634 of 1064 16.1.2 Block Diagram Bus interface Figure 16.1 shows a block diagram of the SCIF. Module data bus RxD2 SCFRDR2 (16-stage) SCFTDR2 (16-stage) SCRSR2 SCTSR2 SCSMR2 SCLSR2 SCFDR2 SCFCR2 SCFSR2 SCSCR2 SCSPTR2 SCBRR2 Pφ Baud rate generator Parity generation Pφ/4 Pφ/16 Transmission/ reception control TxD2 Internal data bus Pφ/64 Clock Parity check External clock SCK2 TXI RXI ERI BRI SCIF SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register SCFSR2: SCBRR2: SCSPTR2: SCFCR2: SCFDR2: SCLSR2: Serial status register Bit rate register Serial port register FIFO control register FIFO data count register Line status register Figure 16.1 Block Diagram of SCIF Rev. 3.0, 04/02, page 635 of 1064 16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation I/O Function Serial clock pin MD0/SCK2 I/O Clock input/output Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin MD7/
 I/O Transmission enabled I/O Transmission request Modem control pin MD8/ Note: These pins function as the MD0, MD1, MD2, MD7, and MD8 mode input pins after a poweron reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, CKE1, and CKE0 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF’s SCSPTR2 register. 16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Name Abbreviation R/W Initial Value P4 Address Serial mode register SCSMR2 R/W H'0000 H'FFE80000 H'IFE80000 16 Bit rate register SCBRR2 R/W H'FF H'FFE80004 H'IFE80004 8 Serial control register SCSCR2 R/W H'0000 H'FFE80008 H'IFE80008 16 Transmit FIFO data register SCFTDR2 W Serial status register SCFSR2 Area 7 Address Access Size Undefined H'FFE8000C H'IFE8000C 8 1 R/(W)* H'0060 H'FFE80010 H'IFE80010 16 Receive FIFO data register SCFRDR2 R Undefined H'FFE80014 H'IFE80014 8 FIFO control register SCFCR2 R/W H'0000 FIFO data count register SCFDR2 R H'0000 Serial port register Line status register R/(W)* H'FFE8001C H'IFE8001C 16 2 SCSPTR2 R/W SCLSR2 H'FFE80018 H'IFE80018 16 3 H'0000* H'FFE80020 H'IFE80020 16 H'0000 H'FFE80024 H'IFE80024 16 Notes: *1 Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be modified. *2 The value of bits 6, 4, 2, and 0 is undefined. *3 Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified. Rev. 3.0, 04/02, page 636 of 1064 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO register, SCFRDR2, automatically. SCRSR2 cannot be directly read or written to by the CPU. 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: 7 6 5 4 3 2 1 0 R/W: R R R R R R R R SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes). SCFRDR2 is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in the receive FIFO register, an undefined value will be returned. When the receive FIFO register is full of receive data, subsequent serial data is lost. The contents of SCFRDR2 are undefined after a power-on reset or manual reset. Rev. 3.0, 04/02, page 637 of 1064 16.2.3 Transmit Shift Register (SCTSR2) Bit: 7 6 5 4 3 2 1 0 R/W: — — — — — — — — SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2 to SCTSR2, and transmission started, automatically. SCTSR2 cannot be directly read or written to by the CPU. 16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: 7 6 5 4 3 2 1 0 R/W: W W W W W W W W SCFTDR2 is a 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data written in this case is ignored. The contents of SCFTDR2 are undefined after a power-on reset or manual reset. Rev. 3.0, 04/02, page 638 of 1064 16.2.5 Serial Mode Register (SCSMR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — CHR PE O/ STOP — CKS1 CKS0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R R/W R/W SCSMR2 is a 16-bit register used to set the SCIF’s serial transfer format and select the baud rate generator clock source. SCSMR2 can be read or written to by the CPU at all times. SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR Description 0 8-bit data 1 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. Bit 5: PE Description 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/ bit. Bit 4—Parity Mode (O/): Selects either even or odd parity for use in parity addition and checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. The O/ bit setting is invalid when parity addition and checking is disabled. Rev. 3.0, 04/02, page 639 of 1064 Bit 4: O/ Description 0 Even parity* 1 2 1 (Initial value) Odd parity* Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. *2 When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP Description 0 1 stop bit* 1 (Initial value) 2 1 2 stop bits* Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. *2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Reserved: This bit is always read as 0, and should only be written with 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the onchip baud rate generator. The clock source can be selected from P , P/4, P/16, and P/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, Bit Rate Register (SCBRR2). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 P
clock 1 P
/4 clock 1 0 P
/16 clock 1 P
/64 clock Note: P
: Peripheral clock Rev. 3.0, 04/02, page 640 of 1064 (Initial value) 16.2.6 Serial Control Register (SCSCR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE REIE — CKE1 CKE0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R/W The SCSCR2 register performs enabling or disabling of SCIF transfer operations, serial clock output, and interrupt requests, and selection of the serial clock source. SCSCR2 can be read or written to by the CPU at all times. SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 8, and 2—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1. Bit 7: TIE Description 0 Transmit-FIFO-data-empty interrupt (TXI) request disabled* 1 Transmit-FIFO-data-empty interrupt (TXI) request enabled (Initial value) Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1. Rev. 3.0, 04/02, page 641 of 1064 Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF. Bit 5: TE Description 0 Transmission disabled 1 Transmission enabled* (Initial value) Note: * Serial transmission is started when transmit data is written to SCFTDR2 in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description 0 Reception disabled* 1 2 Reception enabled* 1 (Initial value) Notes: *1 Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. *2 Serial transmission is started when a start bit is detected in this state. Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1. Rev. 3.0, 04/02, page 642 of 1064 Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE Description 0 Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled* (Initial value) 1 Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. Bits 1 and 0: Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCIF clock source and enable/disable clock output from the SCK2 pin. The combination of CKE1 and CKE0 determine whether the SCK2 pin functions as serial clock output pin or the serial clock input pin. Note, however, that the setting of the CKE0 bit is valid only when CKE1 = 0 (internal clock operation). When CKE1 = 1 (external clock), CKE0 is ignored. Also, be sure to set CKE1 and CKE0 prior to determining the SCIF operating mode with SCSMR2. Bit 1: CKE1 Bit 0: CKE0 Description 0 0 Internal clock/SCK pin functions as port (Initial value) 1 Internal clock/SCK2 pin functions as clock output* 0 External clock/SCK2 pin functions as clock input* 1 External clock/SCK2 pin functions as clock input* 1 1 2 2 Notes: *1 Outputs a clock with a frequency 16 times the bit rate. *2 Inputs a clock with a frequency 16 times the bit rate. Rev. 3.0, 04/02, page 643 of 1064 16.2.7 Serial Status Register (SCFSR2) Bit: 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR Initial value: R/W: 0 1 1 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R R R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the receive FIFO register. SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified. SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 12—Number of Parity Errors (PER3–PER0): These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes in which a parity error occurred. If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to PER0 will be 0. Bits 11 to 8—Number of Framing Errors (FER3–FER0): These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR2. After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in which a framing error occurred. If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Rev. 3.0, 04/02, page 644 of 1064 Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2, and reception continues. The FER and PER bits in SCFSR2 can be used to determine whether there is a receive error in the data read from SCFRDR2. Bit 7: ER Description 0 No framing error or parity error occurred during reception (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When 0 is written to ER after reading ER = 1 A framing error or parity error occurred during reception [Setting conditions]  When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0*  When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/ bit in SCSMR2 Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. Rev. 3.0, 04/02, page 645 of 1064 Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description 0 Transmission is in progress [Clearing conditions] 1  When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1  When data is written to SCFTDR2 by the DMAC Transmission has been ended (Initial value) [Setting conditions]  Power-on reset or manual reset  When the TE bit in SCSCR2 is 0  When there is no transmit data in SCFTDR2 on transmission of the last bit of a 1-byte serial transmit character Rev. 3.0, 04/02, page 646 of 1064 Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2. Bit 5: TDFE Description 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR2 [Clearing conditions] 1  When transmit data exceeding the transmit trigger set number is written to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE  When transmit data exceeding the transmit trigger set number is written to SCFTDR2 by the DMAC The number of transmit data bytes in SCFTDR2 does not exceed the transmit trigger set number (Initial value) [Setting conditions]  Power-on reset or manual reset  When the number of SCFTDR2 transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation* Note: * As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be ignored. The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2. Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK Description 0 A break signal has not been received (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When 0 is written to BRK after reading BRK = 1 A break signal has been received* [Setting condition] When data with a framing error is received, followed by the space “0” level (low level ) for at least one frame length Note: * When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive data transfer is resumed. Rev. 3.0, 04/02, page 647 of 1064 Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read from the receive FIFO data register (SCFRDR2). Bit 3: FER Description 0 There is no framing error in the receive data that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When there is no framing error in the data that is to be read next from SCFRDR2 There is a framing error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a framing error in the data that is to be read next from SCFRDR2 Bit 2—Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read from the receive FIFO data register (SCFRDR2). Bit 2: PER Description 0 There is no parity error in the receive data that is to be read from SCFRDR2 (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When there is no parity error in the data that is to be read next from SCFRDR2 There is a parity error in the receive data that is to be read from SCFRDR2 [Setting condition] When there is a parity error in the data that is to be read next from SCFRDR2 Rev. 3.0, 04/02, page 648 of 1064 Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). Bit 1: RDF Description 0 The number of receive data bytes in SCFRDR2 is less than the receive trigger set number (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When SCFRDR2 is read until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF  When SCFRDR2 is read by the DMAC until the number of receive data bytes in SCFRDR2 falls below the receive trigger set number The number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger set number [Setting condition] When SCFRDR2 contains at least the receive trigger set number of receive data bytes* Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR2 is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR2 is indicated by the lower bits of SCFDR2. Rev. 3.0, 04/02, page 649 of 1064 Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR Description 0 Reception is in progress or has ended normally and there is no receive data left in SCFRDR2 (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When all the receive data in SCFRDR2 has been read after reading DR = 1, and 0 is written to DR  When all the receive data in SCFRDR2 has been read by the DMAC No further receive data has arrived [Setting condition] When SCFRDR2 contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received* Note: * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: Elementary time unit (time for transfer of 1 bit) 16.2.8 Bit Rate Register (SCBRR2) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR2. SCBRR2 can be read or written to by the CPU at all times. SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Rev. 3.0, 04/02, page 650 of 1064 The SCBRR2 setting is found from the following equation. Asynchronous mode: Pφ × 106 – 1 64 × 22n–1 × B N= Where B: N: P: n: Bit rate (bits/s) SCBRR2 setting for baud rate generator (0  N  255) Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SCSMR2 Setting n Clock CKS1 CKS0 0 P
0 0 1 P
/4 0 1 2 P
/16 1 0 3 P
/64 1 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = 16.2.9 Pφ × 106 – 1 × 100 (N + 1) × B × 64 × 22n–1 FIFO Control Register (SCFCR2) Bit: 15 14 13 12 11 — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP Initial value: R/W: 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. Rev. 3.0, 04/02, page 651 of 1064 SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state. Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bits 10, 9 and 8—
 Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits output the high level to the
 signal when the number of received data stored in the receive FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below. Bit 10: RSTRG2 Bit 9: RSTRG1 Bit 8: RSTRG0  Output Active Trigger 0 0 0 15 1 1 0 4 1 6 0 8 1 10 0 12 1 14 1 1 0 1 (Initial value) Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2). The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than the trigger set number shown in the following table. Bit 7: RTRG1 Bit 6: RTRG0 Receive Trigger Number 0 0 1 1 4 0 8 1 14 1 Rev. 3.0, 04/02, page 652 of 1064 (Initial value) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table. Bit 5: TTRG1 Bit 4: TTRG0 Transmit Trigger Number 0 0 8 (8) 1 4 (12) 0 2 (14) 1 1 (15) 1 (Initial value) Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set. Bit 3—Modem Control Enable (MCE): Enables the  and
 modem control signals. Bit 3: MCE Description 0 Modem signals disabled* 1 Modem signals enabled (Initial value) Note: *
 is fixed at active-0 regardless of the input value, and  output is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. Bit 2: TFRST Description 0 Reset operation disabled* 1 Reset operation enabled (Initial value) Note: * A reset operation is performed in the event of a power-on reset or manual reset. Bit 1—Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive FIFO data register and resets it to the empty state. Bit 1: RFRST Description 0 Reset operation disabled* 1 Reset operation enabled (Initial value) Note: * A reset operation is performed in the event of a power-on reset or manual reset. Rev. 3.0, 04/02, page 653 of 1064 Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the
 pin and  pin, enabling loopback testing. Bit 0: LOOP Description 0 Loopback test disabled 1 Loopback test enabled (Initial value) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2. SCFDR2 can be read by the CPU at all times. Bit: 15 14 13 12 11 10 9 8 — — — T4 T3 T2 T1 T0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data. Bit: 7 6 5 4 3 2 1 0 — — — R4 R3 R2 R1 R0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data. Rev. 3.0, 04/02, page 654 of 1064 16.2.11 Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT Initial value: R/W: SPB2IO SPB2DT 0 — 0 — 0 — 0 — R/W R/W R/W R/W R/W R/W R/W R/W SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface with FIFO (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the SCK2 pin by means of bits 3 and 2. Data can be read from, and output data written to, the  pin by means of bits 5 and 4. Data can be read from, and output data written to, the
 pin by means of bits 6 and 7. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies the serial port
 pin input/output condition. When the
 pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to 1  pin RTSDT bit value is output to  pin (Initial value) Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port
 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the
 pin. The
 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Rev. 3.0, 04/02, page 655 of 1064 Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies the serial port  pin input/output condition. When the  pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to 1 CTSDT bit value is output to
 pin
 pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port  pin input/output data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for details). In output mode, the CTSDT bit value is output to the  pin. The  pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 3—Serial Port Clock Port I/O (SCKIO): Sets the I/O for the SCK2 pin serial port. To actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit, set the CKE1 and CKE0 bits of the SCSCR2 register to 0. Bit 3: SCKIO Description 0 Shows that the value of the SCKDT bit is not output to the SCK2 pin (Initial value) 1 Shows that the value of the SCKDT bit is output to the SCK2 pin. Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin. Regardless of the value of the SCKIO bit, the value of the SCK2 pin is fetched from the SCKDT bit. The initial value after a power-on reset or manual reset is undefined. Rev. 3.0, 04/02, page 656 of 1064 Bit 2: SCKDT Description 0 Shows I/O data level is LOW 1 Shows I/O data level is HIGH Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level Rev. 3.0, 04/02, page 657 of 1064 SCIF I/O port block diagrams are shown in figures 16.2 to 16.6. Reset R D7 Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R D6 Q D RTSDT C SPTRW SCIF Modem control enable signal* RTS2 signal Mode setting register SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.2 MD8/RTS2 Pin Rev. 3.0, 04/02, page 658 of 1064 Reset R Q D CTSIO C D5 Internal data bus SPTRW Reset MD7/CTS2 R Q D CTSDT C D4 SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 MD7/CTS2 Pin Rev. 3.0, 04/02, page 659 of 1064 Reset R Q D SPB2IO C D1 Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C D0 SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register D0 Internal data bus SPTRR SPTRR: Read SPTR Figure 16.5 MD2/RxD2 Pin Rev. 3.0, 04/02, page 660 of 1064 Reset R Q D SCKIO C Internal data bus SPTRW Reset MD0/SCK2 Q R D SCKDT C SPTRW SCIF Clock output enable signal Serial clock output signal Mode setting register * Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2. Figure 16.6 MD0/SCK2 Pin Rev. 3.0, 04/02, page 661 of 1064 16.2.12 Line Status Register (SCLSR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — ORER Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R (R/W)* Note: * Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 0: ORER Description 0 Reception in progress, or reception has ended normally* 1 (Initial value) [Clearing conditions] 1  Power-on reset or manual reset  When 0 is written to ORER after reading ORER = 1 2 An overrun error occurred during reception* [Setting condition] When the next serial reception is completed while the receive FIFO is full Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0. *2 The receive data prior to the overrun error is retained in SCFRDR2, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. Rev. 3.0, 04/02, page 662 of 1064 16.3 Operation 16.3.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed.
 and  signals are also provided as modem control signals. The transmission format is selected using the serial mode register (SCSMR2), as shown in table 16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register (SCSCR2), as shown in table 16.4.
Data length: Choice of 7 or 8 bits
Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length)
Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception
Indication of the number of data bytes stored in the transmit and receive FIFO registers
Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock, and a clock with a frequency of 16 times the bit rate must be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings Bit 6: CHR Bit 5: PE 0 0 SCIF Transfer Format Bit 3: STOP Mode Data Length Multiprocessor Bit 0 Asynchronous mode 8-bit data No Parity Bit No 1 1 0 0 0 Yes 0 1 1 bit 2 bits 7-bit data No 1 1 1 bit 2 bits 1 1 Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits Rev. 3.0, 04/02, page 663 of 1064 Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting SCIF Transmit/Receive Clock Bit 1: CKE1 Bit 0: CKE0 Mode Clock Source SCK2 Pin Function 0 0 Asynchronous mode Internal SCIF does not use SCK2 pin 1 1 0 1 16.3.2 Output clock with frequency of 16 times the bit rate External Inputs clock with frequency of 16 times the bit rate Serial Operation Data Transfer Format Table 16.5 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings. Rev. 3.0, 04/02, page 664 of 1064 Table 16.5 Serial Transfer Formats SCSMR2 Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8-bit data STOP 0 0 1 S 8-bit data STOP STOP 0 1 0 S 8-bit data P STOP 0 1 1 S 8-bit data P STOP STOP 1 0 0 S 7-bit data STOP 1 0 1 S 7-bit data STOP STOP 1 1 0 S 7-bit data P STOP 1 1 1 S 7-bit data P STOP STOP S: Start bit STOP: Stop bit P: Parity bit Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF’s serial clock, according to the setting of the CKE1 bit in SCSCR2. For details of SCIF clock source selection, see table 16.4. When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit rate used. When operating using the internal clock, the clock can be output via the SCK2 pin. The frequency of this clock is 16 times the bit rate. Rev. 3.0, 04/02, page 665 of 1064 Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR2 is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR2, SCFTDR2, or SCFRDR2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR2 has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR2 should first be set to 1 to reset SCFTDR2. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. Figure 16.7 shows a sample SCIF initialization flowchart. Rev. 3.0, 04/02, page 666 of 1064 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits in SCSCR2 to 0 2. Set the data transfer format in SCSMR2. 3. Write a value corresponding to the bit rate into SCBRR2. (Not necessary if an external clock is used.) Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 and CKE0 bits in SCSCR2 (leaving TE and RE bits cleared to 0) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSCR2 to 1. Also set the RIE, REIE, and TIE bits. Set data transfer format in SCSMR2 Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Set value in SCBRR2 Wait 1-bit interval elapsed? No Yes Set RTRG1–0, TTRG1–0, and MCE bits in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1, and set RIE, TIE, and REIE bits End Figure 16.7 Sample SCIF Initialization Flowchart Rev. 3.0, 04/02, page 667 of 1064 Serial Data Transmission: Figure 16.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Start of transmission Read TDFE flag in SCFSR2 TDFE = 1? No The number of transmit data bytes that can be written is 16 (transmit trigger set number). Yes Write transmit data (16 − transmit trigger set number) to SCFTDR2, read 1 from TDFE flag and TEND flag in SCFSR2, then clear to 0 All data transmitted? 2. Serial transmission continuation procedure: No Yes No Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: Read TEND flag in SCFSR2 TEND = 1? Read SCFSR2 and check that the TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR2, then clear the TE bit in SCSCR2 to 0. In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of SCFDR2. Clear TE bit in SCSCR2 to 0 End of transmission Figure 16.8 Sample Serial Transmission Flowchart Rev. 3.0, 04/02, page 668 of 1064 In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is at least 16 (transmit trigger set number). 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls to or below the transmit trigger number set in the FIFO control register (SCFCR2), the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. a. Start bit: One 0-bit is output. b. Transmit data: 8-bit or 7-bit data is output in LSB-first order. c. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) d. Stop bit(s): One or two 1-bits (stop bits) are output. e. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. Figure 16.9 shows an example of the operation for transmission in asynchronous mode. Rev. 3.0, 04/02, page 669 of 1064 Start bit 1 Serial data Data 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 Idle state (mark state) 1 TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the  input value. When  is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When  is set to 0, the next transmit data is output starting from the start bit. Figure 16.10 shows an example of the operation when modem control is used. Start bit Serial data TxD2 0 Parity Stop bit bit D0 D1 D7 0/1 1 Start bit 0 D0 D1 D7 0/1 CTS2 Drive high before stop bit Figure 16.10 Example of Operation Using Modem Control (CTS2) Rev. 3.0, 04/02, page 670 of 1064 Serial Data Reception: Figure 16.11 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR2 and ORER flag in SCLSR2 ER or DR or BRK or ORER = 1? No Read RDF flag in SCFSR2 No RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCFSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End of reception Yes Error handling 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag in SCLSR2, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read SCFSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. Figure 16.11 Sample Serial Reception Flowchart (1) Rev. 3.0, 04/02, page 671 of 1064 Error handling No ORER = 1? Yes Overrun error handling No ER = 1? 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 (the break data in which a framing error occurred is stored). Yes Receive error handling No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCFSR2, and ORER flag in SCLSR2, to 0 End Figure 16.11 Sample Serial Reception Flowchart (2) Rev. 3.0, 04/02, page 672 of 1064 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. a. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. b. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. c. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred. d. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the b, c, and d checks are passed, the receive data is stored in SCFRDR2. Note: Reception continues when parity error, framing error occurs. 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR2 is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Rev. 3.0, 04/02, page 673 of 1064 Figure 16.12 shows an example of the operation for reception. 1 Serial data Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 Parity Stop bit bit D1 D7 0/1 0 0/1 RDF FER RXI interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the
 signal is output when SCFRDR2 is empty. When
 is 0, reception is possible. When
 is 1, this indicates that SCFRDR2 contains a number of data bytes equal to or greater than the
 output active trigger set number. The
 output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR2), described in section 16.2.9. RTS2 also goes to 1 when bit 4 (RE) in SCSCR2 is 0. Figure 16.13 shows an example of the operation when modem control is used. Parity Stop bit bit Start bit Serial data RxD2 0 D0 D1 D2 D7 0/1 1 Start bit 0 RTS2 Figure 16.13 Example of Operation Using Modem Control (RTS2) Rev. 3.0, 04/02, page 674 of 1064 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When transmission/reception is carried out using the DMAC, output of interrupt requests to the interrupt controller can be inhibited by clearing the RIE bit in SCSCR2 to 0. By setting the REIE bit to 1 while the RIE bit is cleared to 0, it is possible to output ERI and BRI interrupt requests, but not RXI interrupt requests. When the TDFE flag in the serial status register (SCFSR2) is set to 1, a transmit-FIFO-data-empty request is generated separately from the interrupt request. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. When the RDF flag or DR flag in SCFSR2 is set to 1, a receive-FIFO-data-full request is generated separately from the interrupt request. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. When using the DMAC for transmission/reception, set and enable the DMAC before making the SCIF settings. See section 14, Direct Memory Access Controller (DMAC), for details of the DMAC setting procedure. When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 16.6 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Priority on Reset Release ERI Interrupt initiated by receive error flag (ER) Not possible High RXI Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR) Possible BRI Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) TXI Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible   Low Rev. 3.0, 04/02, page 675 of 1064 See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO data count register (SCFDR2). SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR2 after receiving a break, the receive operation continues. Sending a Break Signal: The input/output condition and level of the TxD2 pin are determined by bits SPB2IO and SPB2DT in the serial port register (SCSPTR2). This feature can be used to send a break signal. Rev. 3.0, 04/02, page 676 of 1064 After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.14. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD2) Start bit +7.5 clocks D0 D1 Synchronization sampling timing Data sampling timing Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% ....................... (1) 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency Rev. 3.0, 04/02, page 677 of 1064 From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1 / (2  16) )  100% = 46.875% ............................................... (2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler. Serial Ports: Note that, when the SCIF pin value is read using a serial port, the value read will be the value two peripheral clock cycles earlier. Rev. 3.0, 04/02, page 678 of 1064 Section 17 Smart Card Interface 17.1 Overview An IC card (smart card) interface subset conforming to ISO/IEC 7816-3 (Identification Card) is supported as a serial communication interface (SCI) extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 Features Features of the smart card interface are listed below.
Asynchronous mode  Data length: 8 bits  Parity bit generation and checking  Transmission of error signal (parity error) in receive mode  Error signal detection and automatic data retransmission in transmit mode  Direct convention and inverse convention both supported
On-chip baud rate generator allows any bit rate to be selected
Three interrupt sources There are three interrupt sources—transmit-data-empty, receive-data-full, and transmit/receive error—that can issue requests independently. The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) to execute data transfer. Rev. 3.0, 04/02, page 679 of 1064 17.1.2 Block Diagram Bus interface Figure 17.1 shows a block diagram of the smart card interface. Module data bus RxD SCRDR1 SCTDR1 SCRSR1 SCTSR1 SCSCMR1 SCSSR1 SCSCR1 SCSMR1 SCSPTR1 SCBRR1 Pφ Baud rate generator Parity generation Pφ/4 Pφ/16 Transmission/ reception control TxD Internal data bus Pφ/64 Clock Parity check External clock SCK TXI RXI ERI SCI SCSCMR1: SCRSR1: SCRDR1: SCTSR1: SCTDR1: SCSMR1: SCSCR1: SCSSR1: SCBRR1: SCSPTR1: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Figure 17.1 Block Diagram of Smart Card Interface Rev. 3.0, 04/02, page 680 of 1064 17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data output 17.1.4 Register Configuration The smart card interface has the internal registers shown in table 17.2. Details of the SCBRR1, SCTDR1, SCRDR1, and SCSPTR1 registers are the same as for the normal SCI function: see the register descriptions in section 15, Serial Communication Interface (SCI). With the exception of the serial port register, the smart card interface registers are initialized in standby mode and in the module standby state as well as by a power-on reset or manual reset. When recovering from standby mode or the module standby state, the registers must be set again. Table 17.2 Smart Card Interface Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Serial mode register SCSMR1 R/W H'00 H'FFE00000 H'1FE00000 8 Bit rate register SCBRR1 R/W H'FF H'FFE00004 H'1FE00004 8 Serial control register SCSCR1 R/W H'00 H'FFE00008 H'1FE00008 8 Transmit data register SCTDR1 R/W H'FF H'FFE0000C H'1FE0000C 8 1 Serial status register SCSSR1 R/(W)* H'84 H'FFE00010 H'1FE00010 8 Receive data register SCRDR1 R H'00 H'FFE00014 H'1FE00014 8 Smart card mode register SCSCMR1 R/W H'00 H'FFE00018 H'1FE00018 8 Serial port register SCSPTR1 R/W H'00* H'FFE0001C H'1FE0001C 8 2 Notes: *1 Only 0 can be written, to clear flags. *2 The value of bits 2 and 0 is undefined. Rev. 3.0, 04/02, page 681 of 1064 17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state. Bit: 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value: — — — — 0 0 — 0 R/W: — — — — R/W R/W — R/W Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3: SDIR Description 0 SCTDR1 contents are transmitted LSB-first (Initial value) Receive data is stored in SCRDR1 LSB-first 1 SCTDR1 contents are transmitted MSB-first Receive data is stored in SCRDR1 MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the bit 3 function for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2: SINV Description 0 SCTDR1 contents are transmitted as they are Receive data is stored in SCRDR1 as it is 1 SCTDR1 contents are inverted before being transmitted Receive data is stored in SCRDR1 in inverted form Rev. 3.0, 04/02, page 682 of 1064 (Initial value) Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description 0 Smart card interface function is disabled 1 Smart card interface function is enabled 17.2.2 (Initial value) Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 GM(C/
) CHR PE O/ STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. With the normal smart card interface, this bit is cleared to 0. Setting this bit to 1 selects GSM mode, an additional mode for controlling the timing for setting the TEND flag that indicates completion of transmission, and the type of clock output used. The details of the additional clock output control mode are specified by the CKE1 and CKE0 bits in the serial control register (SCSCR1). In GSM mode, the pulse width is guaranteed when SCK start/stop specifications are made by CKE1 and CKE0. Bit 7: GM Description 0 Normal smart card interface mode operation 1 (Initial value)
The TEND flag is set 12.5 etu after the beginning of the start bit
Clock output on/off control only GSM mode smart card interface mode operation
The TEND flag is set 11.0 etu after the beginning of the start bit
Clock output on/off and fixed-high/fixed-low control (set in SCSCR1) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface, for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. Rev. 3.0, 04/02, page 683 of 1064 17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: 7 6 5 4 3 2 1 0 TIE RIE TE RE — — CKE1 CKE0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. Bits 3 and 2: Not used with the smart card interface. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits specify the function of the SCK pin. In smart card interface mode, an internal clock is always used as the clock source. In smart card interface mode, it is possible to specify a fixed high level or fixed low level for the clock output, in addition to the usual switching between enabling and disabling of the clock output. GM CKE1 CKE0 SCK Pin Function 0 0 0 Port I/O pin 1 Clock output as SCK output pin 1 1 0 1 0 Invalid setting: must not be used 1 Invalid setting: must not be used 0 Output pin with output fixed low 1 Clock output as output pin 0 Output pin with output fixed high 1 Clock output as output pin Rev. 3.0, 04/02, page 684 of 1064 17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER/ ERS PER TEND — — 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. Bits 7 to 5: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface, for details. Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4: ERS Description 0 Normal reception, no error signal (Initial value) [Clearing conditions] 1
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to ERS after reading ERS = 1 An error signal has been sent from the receiving side indicating detection of a parity error [Setting condition]
When the low level of the error signal is detected Note: Clearing the TE bit in SCSCR1 to 0 does not affect the ERS flag, which retains its previous state. Bit 3—Parity Error (PER): Operates in the same way as for the normal SCI. See section 15, Serial Communication Interface, for details. Rev. 3.0, 04/02, page 685 of 1064 Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description 0 Transmission in progress [Clearing condition]
1 When 0 is written to TDRE after reading TDRE = 1 Transmission has been ended (Initial value) [Setting conditions]
Power-on reset, manual reset, standby mode, or module standby
When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0
When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character
When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character etu: Elementary time unit (time for transfer of 1 bit) Bits 1 and 0: Not used with the smart card interface. 17.3 Operation 17.3.1 Overview The main functions of the smart card interface are as follows.
One frame consists of 8-bit data plus a parity bit.
In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
If a parity error is detected during reception, a low error signal level is output for a 1-etu period 10.5 etu after the start bit.
If an error signal is detected during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer.
Only asynchronous communication is supported; there is no synchronous communication function. Rev. 3.0, 04/02, page 686 of 1064 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the VCC power supply side with a resistor. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. Chip port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Note: If an IC card is not connected, and both TE and RE are set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. VCC TxD IO Data line RxD SH7751 Series SCK Clock line Px (port) Reset line CLK RST IC card Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections Rev. 3.0, 04/02, page 687 of 1064 17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data. If an error signal is detected during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output Ds: D0–D7: Dp: DE: Start bit Data bits Parity bit Error signal Receiving station output Figure 17.3 Smart Card Interface Data Format The operation sequence is as follows. 1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. 2. The transmitting station starts transmission of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). 3. With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. Rev. 3.0, 04/02, page 688 of 1064 If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data. 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR1 GM 0 1 O/ 1 0 CKS1 CKS0 SCBRR1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCSCR1 TIE RIE TE RE 0 0 CKE1 CKE0 SCTDR1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SCSSR1 TDRE RDRF ORER FER/ERS PER TEND 0 0 SCRDR1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCSCMR1 — — — — SDIR SINV — SMIF SCSPTR1 — — — SPB1IO SPB1DT SPB0IO EIO SPB0DT Note: A dash indicates an unused bit. Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to select the clock output state. The O/
bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. Rev. 3.0, 04/02, page 689 of 1064 I/O data Ds Da Db Dc Dd De Df Dg Dh Dp DE Guard time 12.5 etu TXI (TEND interrupt) GM = 0 11.0 etu GM = 1 etu: Elementary Time Unit (time for transfer of 1 bit) Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. Serial Control Register (SCSCR1) Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. The CKE1 and CKE0 bits specify the clock output state. See section 17.3.5, Clock, for details. Smart Card Mode Register (SCSCMR1) Settings: The SDIR bit and SINV bit are both cleared to 0 if the IC card is of the direct convention type, and both set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used. Figure 17.5 shows examples of register settings and the waveform of the start character for the two types of IC card (direct convention and inverse convention). With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data in this case is H'3B. The parity bit is 1 since even parity is stipulated for the smart card. With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/
bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception). Rev. 3.0, 04/02, page 690 of 1064 (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State (Z) State (a) Direct convention (SDIR = SINV = O/ = 0) (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (b) Inverse convention (SDIR = SINV = O/ = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for calculating the bit rate is shown below. Table 17.5 shows some sample bit rates. If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= Pφ × 106 1488 × 22n–1 × (N + 1) Where: N = Value set in SCBRR1 (0  N  255) B = Bit rate (bits/s) P = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Rev. 3.0, 04/02, page 691 of 1064 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) P (MHz) N 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 0 9600.0 13440.9 14400.0 19200.0 33602.2 44354.8 67204.3 1 4800.0 6720.4 7200.0 9600.0 16801.1 22177.4 33602.2 2 3200.0 4480.3 4800.0 6400.0 11200.7 14784.9 22401.4 Note: Bit rates are rounded to one decimal place. The method of calculating the value to be set in the bit rate register (SCBRR1) from the peripheral module operating frequency and bit rate is shown below. Here, N is an integer in the range 0  N  255, and the smaller error is specified. N= Pφ × 106 – 1 1488 × 22n–1 × B Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) P (MHz) 7.1424 10.00 10.7136 14.2848 25.00 33.00 50.00 Bits/s N Error N Error N Error N Error N Error N Error N Error 9600 0 0.00 1 30.00 1 25.00 1 8.99 3 14.27 4 8.22 6 0.01 Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) P (MHz) Maximum Bit Rate (bits/s) N n 7.1424 19200 0 0 10.00 26882 0 0 10.7136 28800 0 0 16.00 43010 0 0 20.00 53763 0 0 25.0 67204 0 0 30.0 80645 0 0 33.0 88710 0 0 50.0 67204 0 0 Rev. 3.0, 04/02, page 692 of 1064 The bit rate error is given by the following equation: Pφ Error (%) = 1488 × 22n–1 × B × (N + 1) × 106 – 1 × 100 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state. Table 17.8 Register Settings and SCK Pin State Register Values Setting 1 1* 2 2* 2 3* SCK Pin SMIF GM CKE1 CKE0 Output State 1 0 0 0 Port Determined by setting of SPB1IO and SPB1DT bits in SCSPTR1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SCK (serial clock) output state Low output Low-level output state SCK (serial clock) output state High output High-level output state SCK (serial clock) output state Notes: *1 The SCK output state changes as soon as the CKE0 bit setting is changed. Clear the CKE1 bit to 0. *2 Stopping and starting the clock by changing the CKE0 bit setting does not affect the clock duty cycle. Port value Width is undefined Width is undefined Port value SCK (a) When GM = 0 CKE1 value Specified width Specified width CKE1 value SCK (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting Rev. 3.0, 04/02, page 693 of 1064 17.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1. Clear the TE and RE bits in the serial control register (SCSCR1) to 0. 2. Clear error flags FER/ERS, PER, and ORER in the serial status register (SCSSR1) to 0. 3. Set the GM bit, parity bit (O/
), and baud rate generator select bits (CKS1 and CKS0) in the serial mode register (SCSMR1). Clear the CHR and MP bits to 0, and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR1). When the SMIF bit is set to 1, the TxD pin and RxD pin both go to the high-impedance state. 5. Set the value corresponding to the bit rate in the bit rate register (SCBRR1). 6. Set the clock source select bits (CKE1 and CKE0) in SCSCR1. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCSCR1. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 3.0, 04/02, page 694 of 1064 Initialization Clear TE and RE bits in SCSCR1 to 0 1 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 2 In SCSMR1, set parity in O/ bit, clock in CKS1 and CKS0 bits, and set GM 3 Set SMIF, SDIR, and SINV bits in SCSCMR1 4 Set value in SCBRR1 5 In SCSCR1, set clock in CKE1 and CKE0 bits, and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. 6 Wait 1-bit interval elapsed? No Yes Set TIE, RIE, TE, and RE bits in SCSCR1 7 End Figure 17.7 Sample Initialization Flowchart Rev. 3.0, 04/02, page 695 of 1064 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the FER/ERS error flag in SCSSR1 is cleared to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1. 4. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. 5. To continue transmitting data, go back to step 2. 6. To end transmission, clear the TE bit to 0. With the above processing, interrupt handling is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation below for details. Rev. 3.0, 04/02, page 696 of 1064 Start 1 Initialization Start of transmission 2 FER/ERS = 0? No Yes Error handling No TEND = 1? 3 Yes No Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 4 All data transmitted? 5 Yes FER/ERS = 0? No Yes Error handling No TEND = 1? Yes Clear TE bit in SCSCR1 to 0 6 End of transmission Figure 17.8 Sample Transmission Processing Flowchart Rev. 3.0, 04/02, page 697 of 1064 Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0. 3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1. 4. Read the receive data from SCRDR1. 5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2. 6. To end reception, clear the RE bit to 0. With the above processing, interrupt handling is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated. See Interrupt Operation below for details. If a parity error occurs during reception and the PER flag is set to 1, the received data is still transferred to SCRDR1, and therefore this data can be read. Rev. 3.0, 04/02, page 698 of 1064 Start 1 Initialization Start of reception 2 ORER = 0 and PER = 0? No Yes Error handling No RDRF = 1? 3 Yes No Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 4 All data received? 5 Yes Clear RE bit in SCSCR1 to 0 6 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Rev. 3.0, 04/02, page 699 of 1064 Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and FER/ERS in SCSSR1 is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.9. Table 17.9 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit mode Receive mode Flag Mask Bit Interrupt Source Normal operation TEND TIE TXI Error FER/ERS RIE ERI Normal operation RDRF RIE RXI Error PER, ORER RIE ERI Data Transfer Operation by DMAC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC. In a transmit operation, when the TEND flag in SCSSR1 is set to 1, a TXI interrupt is requested. If the TXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TEND flag is automatically cleared to 0 when data transfer is performed by the DMAC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically, including retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and therefore the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SCSSR1 is set to 1. If the RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC. If an error occurs, an error flag is set but the RDRF flag is not. The DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. The error flag must therefore be cleared. When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). Rev. 3.0, 04/02, page 700 of 1064 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing is shown in figure 17.10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode The receive margin in smart card mode can therefore be expressed as shown in the following equation. M = (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) × 100% 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 372) Clock duty cycle (D = 0 to 1.0) Frame length (L =10) Absolute deviation of clock frequency Rev. 3.0, 04/02, page 701 of 1064 From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 – 1/2  372)  100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. Retransfer Operation when SCI is in Receive Mode: Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The PER bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The RDRF bit in SCSSR1 is not set for a frame in which an error has occurred. 3. If an error is found when the received parity bit is checked, the PER bit in SCSSR1 is not set to 1. 4. If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF bit in SCSSR1 is automatically set to 1. If the RIE bit in SCSCR1 is enabled at this time, an RXI interrupt request is generated. 5. When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. nth transfer frame Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer frame n+1 (DE) 5 Ds D0 D1 D2 D3 D4 RDRF 2 4 1 3 PER Figure 17.11 Retransfer Operation in SCI Receive Mode Rev. 3.0, 04/02, page 702 of 1064 Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated. The FER/ERS bit in SCSSR1 should be cleared to 0 before the next parity bit is sampled. 2. The TEND bit in SCSSR1 is not set for a frame for which an error signal indicating an error is received. 3. If an error signal is not sent back from the receiving side, the FER/ERS bit in SCSSR1 is not set. 4. If an error signal is not sent back from the receiving side, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SCSSR1 is set to 1. If the TIE bit in SCSCR1 is enabled at this time, a TXI interrupt request is generated. nth transfer frame Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp TDRE Transfer from SCTDR1 to SCTSR1 Transfer from SCTDR1 to SCTSR1 Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 Transfer from SCTDR1 to SCTSR1 TEND 2 4 FER/ERS 1 3 Figure 17.12 Retransfer Operation in SCI Transmit Mode Rev. 3.0, 04/02, page 703 of 1064 (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode. 2. Write 0 to the TE and RE bits in the serial control register (SCSCR1) to stop transmit/receive operations. At the same time, set the CKE1 bit to the value for the fixed output state in standby mode. 3. Write 0 to the CKE0 bit in SCSCR1 to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5. Write H'00 to the serial mode register (SCSMR1) and smart card mode register (SCSMR1). 6. Make the transition to the standby state. Returning from Standby Mode to Smart Card Interface Mode: 7. Clear the standby state. 8. Set the CKE1 bit in SCSCR1 to the value for the fixed output state at the start of standby (the current SCK pin state). 9. Set smart card interface mode and output the clock. Clock signal generation is started with the normal duty cycle. Standby mode Normal operation 123 4 56 Normal operation 7 89 Figure 17.13 Procedure for Stopping and Restarting the Clock Rev. 3.0, 04/02, page 704 of 1064 (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3. Set the serial mode register (SCSMR1) and smart card mode register (SCSCMR1), and switch to smart card mode operation. 4. Set the CKE0 bit in SCSCR1 to 1 to start clock output. Rev. 3.0, 04/02, page 705 of 1064 Rev. 3.0, 04/02, page 706 of 1064 Section 18 I/O Ports 18.1 Overview The SH7751 Series has a 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows:
Available only in PCI-disabled mode.
32-bit I/O port with input/output direction independently specifiable for each bit.
Pull-up can be specified independently for each bit.
The 32 bits of the general-purpose I/O port are divided into 16-bit port A and 16-bit port B. Interrupts can be input to 16-bit port A.
Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2 (BCR2). (Do not set PORTEN = 1 when in PCI-enabled mode.) The features of the SCI I/O port are as follows:
Data can be output when the I/O port is designated for output and SCI enabling has not been set. This allows break function transmission.
The RxD pin value can be read at all times, allowing break state detection.
SCK pin control is possible when the I/O port is designated for output and SCI enabling has not been set.
The SCK pin value can be read at all times. The features of the SCIF I/O port are as follows:
Data can be output when the I/O port is designated for output and SCIF enabling has not been set. This allows break function transmission.
The RxD2 pin value can be read at all times, allowing break state detection.
SCK2,
, and  pin control is possible when the I/O port is designated for output and SCIF enabling has not been set.
The SCK2,
, and  pin values can be read at all times. Rev. 3.0, 04/02, page 707 of 1064 18.1.2 Block Diagrams Figure 18.1 is a block diagram of the 16-bit general-purpose I/O port A with interrupt function. PBnPUP PORTEN Pull-up resistor Internal bus PDTRW Port 15 (input/ output)/AD15 to Port 0 (input/ output)/AD0 1 D Q C MPX 0 ADn output data BCK 0 1 MPX ADnDIR PBnIO MPX 0 Interrupt controller PTIRENn PORTEN PBnPuP DnDIR PBnIO PTIRENn 0: Port not available 0: Pull-up 0: Input 0: Input 0: Interrupt input disabled Data input strobe 1 Q C D BCK 1: Port available 1: Pull-up off 1: Output 1: Output 1: Interrupt input enabled Figure 18.1 16-Bit Port A Rev. 3.0, 04/02, page 708 of 1064 Figure 18.2 is a block diagram of the 16-bit general-purpose I/O port B, which has no interrupt function. PBnPUP Pull-up resistor PORTEN Internal bus PDTRW Port 31 (input/ output)/AD31 to Port 16 (input/ output)/AD16 1 D Q C MPX 0 ADn output data BCK 0 1 PBnIO Data input strobe 0 MPX MPX ADnDIR 1 C Q D BCK PORTEN PBnPuP DnDIR PBnIO 0: Port not available 0: Pull-up 0: Input 0: Input 1: Port available 1: Pull-up off 1: Output 1: Output Figure 18.2 16-Bit Port B Rev. 3.0, 04/02, page 709 of 1064 SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset R Q D SPB1IO C Internal data bus SPTRW Reset SCK Q R D SPB1DT C SPTRW SCI Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1. Figure 18.3 SCK Pin Rev. 3.0, 04/02, page 710 of 1064 * Reset R Q D SPB0IO C Internal data bus SPTRW Reset TxD R Q D SPB0DT C SCI Transmit enable signal SPTRW Serial transmit data SPTRW: Write to SPTR Figure 18.4 TxD Pin SCI RxD Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 18.5 RxD Pin Rev. 3.0, 04/02, page 711 of 1064 SCIF I/O port block diagrams are shown in figures 18.6 to 18.10. Reset R Q D SPB2IO C Internal data bus SPTRW Reset MD1/TxD2 R Q D SPB2DT C SPTRW Mode setting register SCIF Transmit enable signal Serial transmit data SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register Internal data bus SPTRR SPTRR: Read SPTR Figure 18.7 MD2/RxD2 Pin Rev. 3.0, 04/02, page 712 of 1064 Reset R Q D SCKIO C Internal data bus SPTRW Reset MD0/SCK2 Q R D SCKDT C SPTRW Mode setting register SCIF Clock output enable signal Serial clock output signal * Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2. Figure 18.8 MD0/SCK2 Pin Rev. 3.0, 04/02, page 713 of 1064 Reset R Q D CTSIO C Internal data bus SPTRW Reset MD7/CTS2 R Q D CTSDT C SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.9 MD7/CTS2 Pin Rev. 3.0, 04/02, page 714 of 1064 Reset R Q D RTSIO C Internal data bus SPTRW Reset MD8/RTS2 R Q D RTSDT C SCIF Modem control enable signal* SPTRW Mode setting register RTS2 signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. Figure 18.10 MD8/RTS2 Pin 18.1.3 Pin Configuration Table 18.1 shows the 32-bit general-purpose I/O port pin configuration. Table 18.1 32-Bit General-Purpose I/O Port Pins Pin Name Signal I/O Function Port 31 pin AD31/PORT31 I/O I/O port Port 30 pin AD30/PORT30 I/O I/O port Port 29 pin AD29/PORT29 I/O I/O port Port 28 pin AD28/PORT28 I/O I/O port Port 27 pin AD27/PORT27 I/O I/O port Port 26 pin AD26/PORT26 I/O I/O port Port 25 pin AD25/PORT25 I/O I/O port Port 24 pin AD24/PORT24 I/O I/O port Rev. 3.0, 04/02, page 715 of 1064 Table 18.1 32-Bit General-Purpose I/O Port Pins (cont) Pin Name Signal I/O Function Port 23 pin AD23/PORT23 I/O I/O port Port 22 pin AD22/PORT22 I/O I/O port Port 21 pin AD21/PORT21 I/O I/O port Port 20 pin AD20/PORT20 I/O I/O port Port 19 pin AD19/PORT19 I/O I/O port Port 18 pin AD18/PORT18 I/O I/O port Port 17 pin AD17/PORT17 I/O I/O port Port 16 pin AD16/PORT16 I/O I/O port Port 15 pin AD15/PORT15 I/O* I/O port / GPIO interrupt Port 14 pin AD14/PORT14 I/O* I/O port / GPIO interrupt Port 13 pin AD13/PORT13 I/O* I/O port / GPIO interrupt Port 12 pin AD12/PORT12 I/O* I/O port / GPIO interrupt Port 11 pin AD11/PORT11 I/O* I/O port / GPIO interrupt Port 10 pin AD10/PORT10 I/O* I/O port / GPIO interrupt Port 9 pin AD9/PORT9 I/O* I/O port / GPIO interrupt Port 8 pin AD8/PORT8 I/O* I/O port / GPIO interrupt Port 7 pin AD7/PORT7 I/O* I/O port / GPIO interrupt Port 6 pin AD6/PORT6 I/O* I/O port / GPIO interrupt Port 5 pin AD5/PORT5 I/O* I/O port / GPIO interrupt Port 4 pin AD4/PORT4 I/O* I/O port / GPIO interrupt Port 3 pin AD3/PORT3 I/O* I/O port / GPIO interrupt Port 2 pin AD2/PORT2 I/O* I/O port / GPIO interrupt Port 1 pin AD1/PORT1 I/O* I/O port / GPIO interrupt Port 0 pin AD0/PORT0 I/O* I/O port / GPIO interrupt Note: * When port pins are used as GPIO interrupts, they must be set to input mode. The input setting can be made in the PCTRA register. Rev. 3.0, 04/02, page 716 of 1064 Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin SCK I/O Clock input/output Receive data pin RxD Input Receive data input Transmit data pin TxD Output Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/
bit in SCSMR1. Break state transmission and detection can be performed by means of a setting in the SCI’s SCSPTR1 register. Table 18.3 shows the SCIF I/O port pin configuration. Table 18.3 SCIF I/O Port Pins Pin Name Abbreviation I/O Function Serial clock pin MD0/SCK2 I/O Clock input/output Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output Modem control pin MD7/ I/O Transmission enabled I/O Transmission request Modem control pin MD8/ Note: These pins function as the MD0, MD1, MD2, MD7, and MD8 mode input pins after a poweron reset. These pins are made to function as serial pins by performing SCIF operation settings with the TE, RE, CKE1, and CKE0 bits in SCSCR2 and the MCE bit in SCFCR2. Break state transmission and detection can be set in the SCIF’s SCSPTR2 register. Rev. 3.0, 04/02, page 717 of 1064 18.1.4 Register Configuration The 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Area 7 Address Access Size Name Abbreviation R/W Initial Value* P4 Address Port control register A PCTRA R/W H'00000000 H'FF80002C H'1F80002C 32 Port data register A PDTRA R/W Undefined H'FF800030 H'1F800030 16 Port control register B PCTRB R/W H'00000000 H'FF800040 H'1F800040 32 Port data register B PDTRB R/W Undefined H'FF800044 H'1F800044 16 GPIO interrupt control register GPIOIC R/W H'00000000 H'FF800048 H'1F800048 16 Serial port register SCSPTR1 R/W Undefined H'FFE0001C H'1FE0001C 8 Serial port register SCSPTR2 R/W Undefined H'FFE80020 H'1FE80020 16 Note: * Initialized by a power-on reset. Rev. 3.0, 04/02, page 718 of 1064 18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port A (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port A should be set to output with PCTRA after writing a value to the PDTRA register. PCTRA is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 PB15PUP PB15IO PB14PUP PB14IO PB13PUP PB13IO PB12PUP PB12IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PB11PUP PB11IO PB10PUP PB10IO PB9PUP PB9IO PB8PUP PB8IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PB7PUP PB7IO PB6PUP PB6IO PB5PUP PB5IO PB4PUP PB4IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB3PUP PB3IO PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port A is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 0–15) of 16-bit port A is pulled up 1 Bit m (m = 0–15) of 16-bit port A is not pulled up (Initial value) Rev. 3.0, 04/02, page 719 of 1064 Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port A is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 0–15) of 16-bit port A is an input 1 Bit m (m = 0–15) of 16-bit port A is an output 18.2.2 (Initial value) Port Data Register A (PDTRA) Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port A. When a bit is set as an output, the value written to the PDTRA register is output from the external pin. When a value is read from the PDTRA register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRA register is read. PDTR is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT Initial value: R/W: Bit: Initial value: R/W: 18.2.3 9 8 PB9DT PB8DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port B (port 31 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 16-bit port B should be set to output with PCTRB after writing a value to the PDTRB register. PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. Rev. 3.0, 04/02, page 720 of 1064 Bit: 31 30 29 28 27 26 25 24 PB31PUP PB31IO PB30PUP PB30IO PB29PUP PB29IO PB28PUP PB28IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 PB27PUP PB27IO PB26PUP PB26IO PB25PUP PB25IO PB24PUP PB24IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 PB23PUP PB23IO PB22PUP PB22IO PB21PUP PB21IO PB20PUP PB20IO Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 PB19PUP PB19IO PB18PUP PB18IO PB17PUP PB17IO PB16PUP PB16IO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16bit port B is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description 0 Bit m (m = 16–31) of 16-bit port B is pulled up 1 Bit m (m = 16–31) of 16-bit port B is not pulled up (Initial value) Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port B is an input or an output. Bit 2n: PBnIO Description 0 Bit m (m = 16–31) of 16-bit port B is an input 1 Bit m (m = 16–31) of 16-bit port B is an output (Initial value) Rev. 3.0, 04/02, page 721 of 1064 18.2.4 Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit in the 16-bit port B. When a bit is set as an output, the value written to the PDTRB register is output from the external pin. When a value is read from the PDTRB register while a bit is set as an input, the external pin value sampled on the external bus clock is read. When a bit is set as an output, the value written to the PDTRB register is read. PDTRB is not initialized by a power-on or manual reset, or in standby mode, and retains its contents. Bit: 15 14 13 12 11 10 9 8 PB31DT PB30DT PB29DT PB28DT PB27DT PB26DT PB25DT PB24DT Initial value: R/W: Bit: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB23DT PB22DT PB21DT PB20DT PB19DT PB18DT PB17DT PB16DT Initial value: R/W: 18.2.5 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents. GPIO interrupts are active-low level interrupts. Bit-by-bit masking is possible, and the OR of all the bits set as GPIO interrupts is used for interrupt detection. Which bits interrupts are input to can be identified by reading the PDTRA register. Rev. 3.0, 04/02, page 722 of 1064 Bit: 15 14 13 12 11 10 9 PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 Initial value: 8 PTIREN8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bit: Initial value: R/W: Bit n (n = 0–15)—Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn Description 0 Port m (m = 0–15) of 16-bit port A is used as a normal I/O port (Initial value) 1 Port m (m = 0–15) of 16-bit port A is used as a GPIO interrupt* Note: * When using an interrupt, set the corresponding port to input in the PCTRA register before making the PTIRENn setting. 18.2.6 Serial Port Register (SCSPTR1) Bit: Initial value: R/W: 7 6 5 4 EIO — — — 3 2 1 0 0 0 0 0 0 — 0 — R/W — — — R/W R/W R/W R/W SPB1IO SPB1DT SPB0IO SPB0DT The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt. SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined. SCSPTR1 is not initialized in the module standby state or standby mode. Bit 7—Error Interrupt Only (EIO): See section 15.2.8, Serial Port Register (SCSPTR1). Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Rev. 3.0, 04/02, page 723 of 1064 Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description 0 SPB1DT bit value is not output to the SCK pin 1 SPB1DT bit value is output to the SCK pin (Initial value) Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 2: SPB1DT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 1—Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition. When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit, the TE bit in SCSCR1 should be cleared to 0. Bit 1: SPB0IO Description 0 SPB0DT bit value is not output to the TxD pin 1 SPB0DT bit value is output to the TxD pin (Initial value) Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB0DT Description 0 Input/output data is low-level 1 Input/output data is high-level Rev. 3.0, 04/02, page 724 of 1064 18.2.7 Serial Port Register (SCSPTR2) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT Initial value: R/W: SPB2IO SPB2DT 0 — 0 — 0 — 0 — R/W R/W R/W R/W R/W R/W R/W R/W The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface with FIFO (SCIF) pins. Input data can be read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. SCK2 pin data reading and output data writing can be performed by means of bits 3 and 2.
 pin data reading and output data writing can be performed by means of bits 5 and 4, and  pin data reading and output data writing by means of bits 7 and 6. SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR2 is not initialized in standby mode or in the module standby state. Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies serial port  pin input/output. When the  pin is actually set as a port output pin and outputs the value set by the RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 7: RTSIO Description 0 RTSDT bit value is not output to the 1  pin RTSDT bit value is output to the  pin (Initial value) Rev. 3.0, 04/02, page 725 of 1064 Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port  pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the  pin is designated as an output, the value of the RTSDT bit is output to the  pin. The  pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 6: RTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 5—Serial Port CTS Port I/O (CTSIO): Specifies serial port
 pin input/output. When the
 pin is actually set as a port output pin and outputs the value set by the CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0. Bit 5: CTSIO Description 0 CTSDT bit value is not output to the 1  pin CTSDT bit value is output to the  pin (Initial value) Bit 4—Serial Port CTS Port Data (CTSDT): Specifies the serial port
 pin input/output data. Input or output is specified by the CTSIO pin (see the description of bit 5, CTSIO, for details). When the
 pin is designated as an output, the value of the CTSDT bit is output to the
 pin. The
 pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 4: CTSDT Description 0 Input/output data is low-level 1 Input/output data is high-level Bit 3—Serial Port Clock Port I/O (SCKIO): Sets the I/O for the SCK2 pin serial port. To actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit, set the CKE1 and CKE0 bits of the SCSCR2 register to 0. Bit 3: SCKIO Description 0 Shows that the value of the SCKDT bit is not output to the SCK2 pin (Initial value) 1 Shows that the value of the SCKDT bit is output to the SCK2 pin Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin. Regardless of the value of the Rev. 3.0, 04/02, page 726 of 1064 SCKIO bit, the value of the SCK2 pin is fetched from the SCKDT bit. The initial value after a power-on reset or manual reset is undefined. Bit 2: SCKDT Description 0 Shows I/O data level is LOW 1 Shows I/O data level is HIGH Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0. Bit 1: SPB2IO Description 0 SPB2DT bit value is not output to the TxD2 pin 1 SPB2DT bit value is output to the TxD2 pin (Initial value) Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. Bit 0: SPB2DT Description 0 Input/output data is low-level 1 Input/output data is high-level Rev. 3.0, 04/02, page 727 of 1064 Rev. 3.0, 04/02, page 728 of 1064 Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features.
Fifteen interrupt priority levels can be set By setting the five interrupt priority registers, the priorities of on-chip peripheral module interrupts can be selected from 15 levels for different request sources.
NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception handler, enabling it to be used as a noise canceler.
NMI request masking when SR.BL bit is set It is possible to select whether or not NMI requests are to be masked when the SR.BL bit is set. 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the INTC. Rev. 3.0, 04/02, page 729 of 1064 NMI Input control IRL3– IRL0 4 4 TMU (Interrupt request) RTC (Interrupt request) SCI (Interrupt request) SCIF (Interrupt request) SR WDT (Interrupt request) I3 I2 I1 I0 REF (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request) GPIO PCIC Priority identifier Comparator Interrupt request CPU (Interrupt request) (Interrupt request) IPR ICR Bus interface INTC TMU: RTC: SCI: SCIF: WDT: REF: DMAC: H-UDI: GPIO: PCIC: ICR: IPRA–IPRD: INTPRI00: SR: Timer unit Realtime clock unit Serial communication interface Serial communication interface with FIFO Watchdog timer Memory refresh controller section of the bus state controller Direct memory access controller Hitachi user debug interface unit I/O port PCI bus controller Interrupt control register Interrupt priority registers A–D Interrupt priority register 00 Status register Figure 19.1 Block Diagram of INTC Rev. 3.0, 04/02, page 730 of 1064 Internal bus IPRA–IPRD, INTPRI00 19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Abbreviation I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt input pins

 Input Input of interrupt request signals (maskable by I3–I0 in SR) 19.1.4 – Register Configuration The INTC has the registers shown in table 19.2. Table 19.2 INTC Registers Name Abbreviation R/W Initial 1 Value* P4 Address Area 7 Address Access Size Interrupt control register ICR R/W * H'FFD00000 H'1FD00000 16 Interrupt priority register A IPRA R/W H'0000 H'FFD00004 H'1FD00004 16 Interrupt priority register B IPRB R/W H'0000 H'FFD00008 H'1FD00008 16 Interrupt priority register C IPRC R/W H'0000 H'FFD0000C H'1FD0000C 16 Interrupt priority register D IPRD R/W H'DA74 H'FFD00010 H'1FD00010 16 Interrupt priority register 00 INTPRI00 R/W H'00000000 H'FE080000 H'1E080000 32 Interrupt request register 00 INTREQ00 R H'00000000 H'FE080020 H'1E080020 32 Interrupt mask register 00 INTMSK00 R/W H'000003FF H'FE080040 H'1E080040 32 Interrupt mask clear register 00 INTMSKCLR00 W — H'FE080060 H'1E080060 32 2 Notes: *1 Initialized by a power-on reset or manual reset. *2 H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. Rev. 3.0, 04/02, page 731 of 1064 19.2 Interrupt Sources There are three types of interrupt sources: NMI, IRL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in the status register in the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in the interrupt control register (ICR) is used to select either rising or falling edge. When the NMIE bit in the ICR register is modified, the NMI interrupt is not detected for a maximum of 6 bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (I3–I0) in the status register (SR). Rev. 3.0, 04/02, page 732 of 1064 19.2.2 IRL Interrupts IRL interrupts are input by level at pins
–
. The priority level is the level indicated by pins
–
. An
–
 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7751 Series Interrupt requests Priority encoder 4 to to Figure 19.2 Example of IRL Interrupt Connection Rev. 3.0, 04/02, page 733 of 1064 Table 19.3
–
 Pins and Interrupt Levels



 Interrupt Priority Level Interrupt Request 0 0 0 0 15 Level 15 interrupt request 1 14 Level 14 interrupt request 1 0 13 Level 13 interrupt request 1 12 Level 12 interrupt request 0 0 11 Level 11 interrupt request 1 10 Level 10 interrupt request 0 9 Level 9 interrupt request 1 8 Level 8 interrupt request 0 7 Level 7 interrupt request 1 6 Level 6 interrupt request 0 5 Level 5 interrupt request 1 4 Level 4 interrupt request 0 3 Level 3 interrupt request 1 2 Level 2 interrupt request 0 1 Level 1 interrupt request 1 0 No interrupt request 1 1 1 0 0 1 1 0 1 A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the
 pin change is detected. In standby mode, as the bus clock is stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt handling starts. However, the priority level can be changed to a higher one. The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL interrupt handling. Pins
–
 can be used for four independent interrupt requests by setting the IRLM bit to 1 in the ICR register. Rev. 3.0, 04/02, page 734 of 1064 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following ten modules:
Hitachi user debug interface unit (H-UDI)
Direct memory access controller (DMAC)
Timer unit (TMU)
Realtime clock (RTC)
Serial communication interface (SCI)
Serial communication interface with FIFO (SCIF)
Bus state controller (BSC)
Watchdog timer (WDT)
I/O port (GPIO)
PCI bus controller (PCIC) Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). The interrupt mask bits (I3–I0) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an erroneous interrupt from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. Furthermore, in case of an interrupt of TMU channels 3 and 4 and PCIC, read the interrupt factor register 00 (INTREQ00). This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip. Processing can be continued without any problem by executing an RTE instruction. Rev. 3.0, 04/02, page 735 of 1064 19.2.4 Interrupt Exception Handling and Priority Table 19.4 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source. This is why, for instance, the value of INTEVT is used as an offset at the start of the interrupt handler and branched to in order to identify the interrupt source. The order of priority of the on-chip peripheral modules is specified as desired by setting priority levels from 0 to 15 in interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). The order of priority of the on-chip peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 19.4. Updating of interrupt priority registers A to D, and INTPRI00 should only be carried out when the BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority registers, then clear the BL bit to 0. This will secure the necessary timing internally. Rev. 3.0, 04/02, page 736 of 1064 Table 19.4 Interrupt Exception Handling Sources and Priority Order Interrupt Source INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within IPR Setting Unit Default Priority NMI H'1C0 16 — — High
 –

0 H'200 15 — —
 –

1 H'220 14 — —
 –

2 H'240 13 — —
 –

3 H'260 12 — —
 –

4 H'280 11 — —
 –

5 H'2A0 10 — —
 –

6 H'2C0 9 — —
 –

7 H'2E0 8 — —
 –

8 H'300 7 — —
 –

9 H'320 6 — —
 –

A H'340 5 — —
 –

B H'360 4 — —
 –

C H'380 3 — —
 –

D H'3A0 2 — —
 –

E H'3C0 1 — — IRL0 H'240 15–0 (13) IPRD (15–12) — IRL1 H'2A0 15–0 (10) IPRD (11–8) — IRL2 H'300 15–0 (7) IPRD (7–4) — IRL3 H'360 15–0 (4) IPRD (3–0) — H-UDI H-UDI H'600 15–0 (0) IPRC (3–0) — GPIO GPIOI H'620 15–0 (0) IPRC (15–12) — DMAC DMTE0 H'640 15–0 (0) IPRC (11–8) DMTE1 H'660 DMTE2 H'680 DMTE3 H'6A0 DMTE4* H'780 DMTE5* H'7A0 DMTE6* H'7C0 DMTE7* DMAE IRL H'7E0                                                                             H'6C0 Low Low High Rev. 3.0, 04/02, page 737 of 1064 Table 19.4 Interrupt Exception Handling Sources and Priority Order (cont) Interrupt Source INTEVT Interrupt Priority IPR (Bit Code (Initial Value) Numbers) Priority within IPR Setting Unit Default Priority PCIC (0) PCISERR H'A00 INTPRI00 (3–0) — High INTPRI00 (7–4) High PCIC (1) PCIERR H'AE0 15–0 (0) 15–0 (0) PCIPWDWN H'AC0 PCIPWON H'AA0 PCIDMA0 H'A80 PCIDMA1 H'A60 PCIDMA2 H'A40           PCIDMA3 H'A20 Low TMU3 TUNI3 H'B00 15–0 (0) INTPRI00 (11–8) — TMU4 TUNI4 H'B80 15–0 (0) INTPRI00 (15–12) — TMU0 TUNI0 H'400 15–0 (0) IPRA (15–12) — TMU1 TUNI1 H'420 15–0 (0) IPRA (11–8) — TMU2 TUNI2 H'440 15–0 (0) IPRA (7–4) High TICPI2 H'460 ATI H'480 PRI H'4A0 CUI H'4C0 ERI H'4E0 RXI H'500 TXI H'520 TEI H'540 ERI H'700 RXI H'720 BRI H'740 TXI H'760 WDT ITI H'560 15–0 (0) IPRB (15–12) — REF RCMI H'580 15–0 (0) IPRB (11–8) ROVI H'5A0 RTC SCI SCIF Low 15–0 (0) High    Low 15–0 (0) IPRB (7–4) High     Low 15–0 (0) IPRC (7–4) High     Low Notes: * SH7751R only TUNI0–TUNI4: Underflow interrupts TICPI2: Input capture interrupt Rev. 3.0, 04/02, page 738 of 1064 IPRA (3–0) High Low                                                               Low ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: H-UDI interrupt GPIOI: I/O port interrupt DMTE0–DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt PCISERR: PCIC SERR error interrupt PCIERR: PCIC error interrupt PCIPWDWN: PCIC power-down request interrupt PCIPWON: PCIC power-ON request interrupt PCIDMA0 to 3: PCIC DMA transfer end interrupts 19.3 Register Descriptions 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 739 of 1064 IPRD Bit: 15 14 13 12 11 10 9 8 Initial value: 1 1 0 1 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 1 1 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: Table 19.5 shows the relationship between the interrupt request sources and the IPRA–IPRD register bits. Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12 11–8 7–4 3–0 Interrupt priority register A TMU0 TMU1 Interrupt priority register B WDT REF* TMU2 RTC SCI1 Reserved* Interrupt priority register C GPIO DMAC SCIF H-UDI Interrupt priority register D IRL0 IRL1 IRL2 IRL3 1 2 Notes: *1 REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus State Controller (BSC), for details. *2 Reserved bits: These bits are always read as 0 and should always be written with 0. As shown in table 19.5, four on-chip peripheral modules are assigned to each register. Interrupt priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the fourbit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). 19.3.2 Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset. It is not initialized in standby mode. Rev. 3.0, 04/02, page 740 of 1064 Bit: 15 14 13 12 11 10 9 8 Bit name: NMIL MAI — — — — NMIB NMIE Initial value: 0/1* 0 0 0 0 0 0 0 R/W: R R/W — — — — R/W R/W Bit: 7 6 5 4 3 2 1 0 IRLM — — — — — — — 0 0 0 0 0 0 0 0 R/W — — — — — — — Bit name: Initial value: R/W: Note: * 1 when NMI pin input is high, 0 when low. Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. Bit 15: NMIL Description 0 NMI pin input level is low 1 NMI pin input level is high Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU’s SR.BL bit. Bit 14: MAI Description 0 Interrupts enabled even while NMI pin is low 1 Interrupts disabled while NMI pin is low* (Initial value) Note: * NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB Description 0 NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) 1 NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1. If interrupt requests are enabled while SR.BL = 1, the previous exception information will be lost, and so must be saved beforehand. 2. This bit is cleared automatically by NMI acceptance. Rev. 3.0, 04/02, page 741 of 1064 Bit 8—NMI Edge Select (NMIE): Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. Bit 8: NMIE Description 0 Interrupt request detected on falling edge of NMI input 1 Interrupt request detected on rising edge of NMI input (Initial value) Bit 7—IRL Pin Mode (IRLM): Specifies whether pins
–
 are to be used as levelencoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM Description 0
 1
 pins used as level-encoded interrupt requests (Initial value) pins used as four independent interrupt requests (level-sense IRQ mode) Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written with 0. 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) The interrupt priority level setting register (INTPRI00) sets the order of priority (levels 15 to 0) of the internal peripheral module interrupts. The INTPRI00 register is a 32-bit read/write register. It is initialized to H'00000000 at a reset. It is not initialized in standby mode. Bit: 31 30 29 ... 19 18 17 16 ... Initial value: 0 0 0 ... 0 0 0 0 R/W: R R R ... R R R R Bit: 15 14 13 ... 3 2 1 0 ... Initial value: R/W: 0 0 0 ... 0 0 0 0 R/W R/W R/W ... R/W R/W R/W R/W Table 19.6 shows the relationship between interrupt request sources and the respective bits of the INTPRI00 register. Rev. 3.0, 04/02, page 742 of 1064 Table 19.6 Interrupt Request Sources and INTPRI00 Register Bits Register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4 3 to 0 Interrupt priority level setting register Reserved Reserved Reserved Reserved TMU ch4 TMU ch3 PCI (1) PCI (0) Note: Reserved bits: These bits always read as 0, and should only be written with 0. As shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register. Values of H'F (1111) to H'0 (0000) can be set in each 4 bits, allowing the order levels of the corresponding interrupts to be set. H'F is priority level 15 (highest level) while H'0 is priority level 0 (request mask). Reserved: These bits are always read as 0, and should only be written with 0. 19.3.4 Interrupt Factor Register 00 (INTREQ00) The interrupt factor register 00 (INTREQ00) shows which interrupt have been requested of the INTC. Even when the interrupts are masked with INTPRI00 and INTMSK00, the bits in this register are not affected. INTREQ00 is a 32-bit read-only register. Bit: 31 30 29 Initial value: 0 0 0 R/W: R R Bit: 7 Initial value: R/W: ... 11 10 9 8 ... 0 0 0 0 R ... R R R R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R ... Bits 31 to 0—Interrupt Request: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Shows no corresponding interrupt request 1 Shows existence of corresponding interrupt request (Initial value) Rev. 3.0, 04/02, page 743 of 1064 19.3.5 Interrupt Mask Register 00 (INTMSK00) The interrupt mask register 00 (INTMSK00) specifies whether or not to mask individual interrupts each time they are requested. The INTMSK00 register is a 32-bit register. It is initialized to H'000003FF at a reset. The values are retained in standby mode. To clear each interrupt mask, write 1 to the corresponding bit of the INTMSKCLR00 register. The values in INTMSK00 do not change if you write 0 to it. Bit: 31 30 29 ... 11 10 9 8 ... Initial value: 0 0 0 ... 0 0 1 1 R/W: R R R ... R R R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Bits 31 to 0—Interrupt Masks: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Accept corresponding interrupt request 1 Mask corresponding interrupt request Rev. 3.0, 04/02, page 744 of 1064 (Initial value) 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) The interrupt mask clear register 00 (INTMSKCLR00) clears the masks for each request of the corresponding interrupt. INTMSKCLR00 is a 32-bit write-only register. Bit: 31 30 29 ... 11 10 9 8 ... Initial value: — — — ... — — — — R/W: W W W ... W W W W Bit: 7 6 5 4 3 2 1 0 Initial value: — — — — — — — — R/W: W W W W W W W W Bits 31 to 0—Interrupt Mask Clear: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation. Bits 31 to 0 Description 0 Do not change corresponding interrupt mask 1 Clear corresponding interrupt mask Rev. 3.0, 04/02, page 745 of 1064 19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 bit allocation The following shows the relationship between individual bits in the register and interrupt factors. Table 19.7 Bit Allocation Bit No. Module Interrupt 31 to 10 Reserved Reserved 9 TMU TUNI4 8 TMU TUNI3 7 PCI PCIERR 6 PCI PCIPWDWN 5 PCI PCIPWON 4 PCI PCIDMA0 3 PCI PCIDMA1 2 PCI PCIDMA2 1 PCI PCIDMA3 0 PCI PCISERR Rev. 3.0, 04/02, page 746 of 1064 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers A to D (IPRA–IPRD) and interrupt priority register 00 (INTPRI00). Lower-priority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 19.4, Interrupt Exception Handling Sources and Priority Order, is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3–I0) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt at a break between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the handling routine for the particular interrupt source. Notes: 1. The interrupt mask bits (I3–I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7751 Series. 2. The interrupt source flag should be cleared in the exception handling routine. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, then wait for the interval shown in table 19.8 (Time for priority decision and SR mask bit comparison) before clearing the BL bit or executing an RTE instruction. 3. Depending on the interrupt factor, the interrupt mask (INTMSK00) must be cleared for each factor using the INTMSKCLR00 register. See section 19.3.5, Interrupt Mask Register 00 (INTMSK00), and section 19.3.6, Interrupt Mask Clear Register 00 (INTMSKCLR00), for details. Rev. 3.0, 04/02, page 747 of 1064 Program execution state Interrupt generated? No Yes (BL bit in SR = 0) or (sleep or standby mode)? No NMIB in ICR = 1 and NMI? Yes No No NMI? Yes Yes No Level 15 interrupt? Yes Yes I3–I0* = level 14 or lower? No Set interrupt source in INTEVT Yes Level 14 interrupt? Yes I3–I0 = level 13 or lower? No Yes Save SR to SSR; save PC to SPC No Level 1 interrupt? Yes I3–I0 = level 0? No Set BL, MD, RB bits in SR to 1 Branch to exception handler Note: * I3–I0: Interrupt mask bits in status register (SR) Figure 19.3 Interrupt Operation Flowchart Rev. 3.0, 04/02, page 748 of 1064 No 19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2. Clear the interrupt source in the corresponding interrupt handler. 3. Save SPC and SSR to the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be shortened for urgent processing. 19.4.3 Interrupt Masking with MAI Bit By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin is low, irrespective of the BL and IMASK bits in the SR register.
In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin.
In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the MAI bit is set to 1. Rev. 3.0, 04/02, page 749 of 1064 19.5 Interrupt Response Time The time from generation of an interrupt request* until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 19.8. Note: * Including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is generated. Table 19.8 Interrupt Response Time Number of States Item NMI RL Peripheral Modules Time for priority decision and SR mask bit comparison* 1Icyc + 4Bcyc 1Icyc + 7Bcyc 1Icyc + 2Bcyc Wait time until end of sequence being executed by CPU S – 1 ( 0)  Icyc S – 1 ( 0)  Icyc S – 1 ( 0)  Icyc Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handler is started 4  Icyc 4  Icyc 4  Icyc Response time Total 5Icyc + 4Bcyc + (S – 1)Icyc 5Icyc + 7Bcyc + (S – 1)Icyc 5Icyc + 2Bcyc + (S – 1)Icyc Minimum case 13Icyc 19Icyc 9Icyc When Icyc: Bcyc = 2:1 Maximum case 36 + S Icyc 60 + S Icyc 20 + S Icyc When Icyc: Bcyc = 8:1 Notes Icyc: One cycle of internal clock supplied to CPU, etc. Bcyc: One CKIO cycle S: Latency of instruction Note: * In the SH7751, this includes the case where the mask bit (IMASK) in SR is changed and a new interrupt is generated. Rev. 3.0, 04/02, page 750 of 1064 Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective selfmonitoring debugger, enabling programs to be debugged with the chip alone, without using an incircuit emulator. 20.1.1 Features The UBC has the following features.
Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B, or on sequential conditions (sequential break setting: channel A  channel B).
The following can be set as break compare conditions:  Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked  Data (channel B only, 32-bit mask capability)  Bus cycle: Instruction access/operand access  Read/write  Operand size: Byte/word/longword/quadword
An instruction access cycle break can be effected before or after the instruction is executed. Rev. 3.0, 04/02, page 751 of 1064 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access control Address bus Data bus Channel A Access comparator BBRA BARA Address comparator BASRA BAMRA Channel B Access comparator BBRB BARB Address comparator BASRB BAMRB Data comparator BDRB BDMRB BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register Control BRCR User break trap request Figure 20.1 Block Diagram of User Break Controller Rev. 3.0, 04/02, page 752 of 1064 Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Name Abbreviation R/W Initial Value P4 Address Area 7 Address Access Size Break address register A BARA R/W Undefined H'FF200000 H'1F200000 32 Break address mask register A BAMRA R/W Undefined H'FF200004 H'1F200004 8 Break bus cycle register A BBRA R/W H'0000 H'FF200008 H'1F200008 16 Break ASID register A BASRA R/W Undefined H'FF000014 H'1F000014 8 Break address register B BARB R/W Undefined H'FF20000C H'1F20000C 32 Break address mask register B BAMRB R/W Undefined H'FF200010 H'1F200010 8 Break bus cycle register B BBRB R/W H'0000 H'FF200014 H'1F200014 16 Break ASID register B BASRB R/W Undefined H'FF000018 H'1F000018 8 Break data register B BDRB R/W Undefined H'FF200018 H'1F200018 32 Break data mask register B BDMRB R/W Undefined H'FF20001C H'1F20001C 32 Break control register BRCR R/W H'0000* H'FF200020 H'1F200020 16 Note: * Some bits are not initialized. See section 20.2.12, Break Control Register (BRCR), for details. Rev. 3.0, 04/02, page 753 of 1064 20.2 Register Descriptions 20.2.1 Access to UBC Registers The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value. UBC register contents cannot be transferred to a floating-point register using a floatingpoint memory load instruction. When a UBC register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction jump destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the SH7751 Series executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. Rev. 3.0, 04/02, page 754 of 1064 20.2.2 Break Address Register A (BARA) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Note: *: Undefined Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual address used in the channel A break conditions. BARA is not initialized by a power-on reset or manual reset. Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address (bits 31–0) used in the channel A break conditions. Rev. 3.0, 04/02, page 755 of 1064 20.2.3 Break ASID Register A (BASRA) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Note: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset. Bits 7 to 0—Break ASID A7 to A0 (BASA7–BASA0): These bits hold the ASID (bits 7–0) used in the channel A break conditions. 20.2.4 Break Address Mask Register A (BAMRA) Bit: 7 6 5 4 3 2 1 0 — — — — BAMA2 BASMA BAMA1 BAMA0 Initial value: 0 0 0 0 * * * * R/W: R R R R R/W R/W R/W R/W Note: *: Undefined Break address mask register A (BAMRA) is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA. BAMRA is not initialized by a power-on reset or manual reset. Bits 7 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 2—Break ASID Mask A (BASMA): Specifies whether all bits of the channel A break ASID (BASA7–BASA0) are to be masked. Bit 2: BASMA Description 0 All BASRA bits are included in break conditions 1 No BASRA bits are included in break conditions Rev. 3.0, 04/02, page 756 of 1064 Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0 Description 0 0 0 All BARA bits are included in break conditions 1 Lower 10 bits of BARA are masked, and not included in break conditions 0 Lower 12 bits of BARA are masked, and not included in break conditions 1 All BARA bits are masked, and not included in break conditions 0 Lower 16 bits of BARA are masked, and not included in break conditions 1 Lower 20 bits of BARA are masked, and not included in break conditions * Reserved (cannot be set) 1 1 0 1 Note: *: Don’t care 20.2.5 Break Bus Cycle Register A (BBRA) Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — SZA2 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets three conditions—(1) instruction access/operand access, (2) read/write, and (3) operand size—from among the channel A break conditions. BBRA is initialized to H'0000 by a power-on reset. It retains its value in standby mode. Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0. Rev. 3.0, 04/02, page 757 of 1064 Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 Bit 4: IDA0 Description 0 0 Condition comparison is not performed 1 Instruction access cycle is used as break condition 0 Operand access cycle is used as break condition 1 Instruction access cycle or operand access cycle is used as break condition 1 (Initial value) Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. Bit 3: RWA1 Bit 2: RWA0 Description 0 0 Condition comparison is not performed 1 Read cycle is used as break condition 0 Write cycle is used as break condition 1 Read cycle or write cycle is used as break condition 1 (Initial value) Bits 6, 1, and 0—Operand Size Select A (SZA2–SZA0): These bits select the operand size of the bus cycle used as a channel A break condition. Bit 6: SZA2 Bit 1: SZA1 Bit 0: SZA0 Description 0 0 0 Operand size is not included in break conditions (Initial value) 1 Byte access is used as break condition 0 Word access is used as break condition 1 Longword access is used as break condition 0 Quadword access is used as break condition 1 Reserved (cannot be set) * Reserved (cannot be set) 1 1 0 1 Note: *: Don’t care Rev. 3.0, 04/02, page 758 of 1064 20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register. The bit configuration is the same as for BAMRA. 20.2.9 Break Data Register B (BDRB) Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Note: *: Undefined Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset. Rev. 3.0, 04/02, page 759 of 1064 Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: 31 30 29 28 27 26 25 24 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Bit: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 Initial value: R/W: Bit: Initial value: R/W: BDMB8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Note: *: Undefined Break data mask register B (BDMRB) is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. BDMRB is not initialized by a power-on reset or manual reset. Rev. 3.0, 04/02, page 760 of 1064 Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn Description 0 Channel B break data bit BDBn is included in break conditions 1 Channel B break data bit BDBn is masked, and not included in break conditions n = 31 to 0 Note: When the data bus value is included in the break conditions, the operand size should be specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and BDMRB. 20.2.11 Break Bus Cycle Register B (BBRB) BBRB is the channel B bus break register. The bit configuration is the same as for BBRA. 20.2.12 Break Control Register (BRCR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 CMFA CMFB — — — PCBA — — 0 0 0 0 0 * 0 0 R/W R/W R R R R/W R R 7 6 5 4 3 2 1 0 DBEB PCBB — — SEQ — — UBDE * * 0 0 * 0 0 0 R/W R/W R R R/W R R R/W Note: *: Undefined The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. Rev. 3.0, 04/02, page 761 of 1064 Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). Bit 15: CMFA Description 0 Channel A break condition is not matched 1 Channel A break condition match has occurred (Initial value) Bit 14—Condition Match Flag B (CMFB): Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write). Bit 14: CMFB Description 0 Channel B break condition is not matched 1 Channel B break condition match has occurred (Initial value) Bits 13 to 11—Reserved: These bits are always read as 0, and should only be written with 0. Bit 10—Instruction Access Break Select A (PCBA): Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 10: PCBA Description 0 Channel A PC break is effected before instruction execution 1 Channel A PC break is effected after instruction execution Bits 9 and 8—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB Description 0 Data bus condition is not included in channel B conditions 1 Data bus condition is included in channel B conditions Note: When the data bus is included in the break conditions, bits IDB1–0 in break bus cycle register B (BBRB) should be set to 10 or 11. Rev. 3.0, 04/02, page 762 of 1064 Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB Description 0 Channel B PC break is effected before instruction execution 1 Channel B PC break is effected after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset. Bit 3: SEQ Description 0 Channel A and B comparisons are performed as independent conditions 1 Channel A and B comparisons are performed as sequential conditions (channel A channel B)
Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0. Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see section 20.4, User Break Debug Support Function) is to be used. Bit 0: UBDE Description 0 User break debug function is not used 1 User break debug function is used 20.3 Operation 20.3.1 Explanation of Terms Relating to Accesses (Initial value) An instruction access is an access that obtains an instruction. For example, the fetching of an instruction from the branch destination when a branch instruction is executed is an instruction access. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+disp2+4 in the instruction MOV.W@(disp,PC), Rn is an operand access. As the term “data” is used to distinguish data from an address, the term “operand access” is used in this section. Rev. 3.0, 04/02, page 763 of 1064 In the SH7751 Series, all operand accesses are treated as either read accesses or write accesses. The following instructions require special attention:
PREF, OCBP, and OCBWB instructions: Treated as read accesses.
MOVCA.L and OCBI instructions: Treated as write accesses.
TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. The SH7751 Series handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword. 20.3.2 Explanation of Terms Relating to Instruction Intervals In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions.

Example of sequence of instructions with no branch: 100 Instruction A (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A) 104 Instruction C (2 instructions after instruction A) 106 Instruction D (3 instructions after instruction A) Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) Rev. 3.0, 04/02, page 764 of 1064 20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR). Set the break addresses in the break address registers for each channel (BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers (BASRA, BASRB), and the address and ASID masking methods in the break address mask registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions, also set the break data in the break data register (BDRB) and the data mask in the break data mask register (BDMRB). 2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups (RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit (in the CPU’s SR register). When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is 1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not reset. Therefore, a memory store instruction should be used on the BRCR register to clear the flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for Sequential Conditions, for the operation when the channel A condition match and channel B condition match occur close together. With sequential conditions, only the channel B condition match flag is set. When sequential condition mode has been selected, if it is wished to clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register. Rev. 3.0, 04/02, page 765 of 1064 20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, overrun-fetched instructions (instructions that are fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of instructions subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a post-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. Rev. 3.0, 04/02, page 766 of 1064 20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Address Bits Compared Quadword (100) Address bits A31–A3 Longword (011) Address bits A31–A2 Word (010) Address bits A31–A1 Byte (001) Address bits A31–A0 Not included in condition (000) In quadword access, address bits A31–A3 In longword access, address bits A31–A2 In word access, address bits A31–A1 In byte access, address bits A31–A0 2. When data bus is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in the break control register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register B (BDMRB) settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions—address, ASID, and data—are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-bit data units satisfies the data match condition. Set the IDB1–0 bits in break bus cycle register B (BBRB) to 10 or 11. When byte data is specified, the same data should be set in the two bytes comprising bits 15–8 and bits 7–0 in break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are ignored. 3. When the DBEB bit in the break control register (BRCR) is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction). Rev. 3.0, 04/02, page 767 of 1064 20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A)  flag not set Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A)  flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. Example 1: 110 Instruction (pre-execution break on channel A)  flag set 112 Instruction (pre-execution break on channel B)  flag not set Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss)  flag set 20.3.7 Program Counter (PC) Value Saved 1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). In this case, the PC value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). Rev. 3.0, 04/02, page 768 of 1064 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, memory updating and register updating that essentially cannot be performed by exception 2 cannot be performed is guaranteed irrespective of the existence of exception 1. The program counter value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 20.3.8 Contiguous A and B Settings for Sequential Conditions When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B Instruction B is 0 instructions after instruction A Equivalent to setting the same address. Do not use this setting Instruction B is 1 instruction after instruction A Sequential operation is not guaranteed Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after instruction A Sequential operation is not guaranteed Instruction B is 2 or more instructions after instruction A Sequential operation is guaranteed Rev. 3.0, 04/02, page 769 of 1064 3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after instruction A Sequential operation is not guaranteed Instruction B is 4 or more instructions after instruction A Sequential operation is guaranteed 4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn. 20.3.9 Usage Notes 1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. a. Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. b. Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. c. Operand access break (address/data): The BL bit value after the executed instruction is referenced. d. In the case of an instruction that modifies the BL bit SL.BL PreExecution Instruction Access PostExecution Instruction Access PreExecution Instruction Access PostExecution Instruction Access Operand Access (Address/Data) 0 A A A A A M M M M A A M A M M M M M M M
0 1
0 0
1 1
1 A: Accepted M: Masked Rev. 3.0, 04/02, page 770 of 1064 e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). f. If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A)  SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B)  SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is valid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A  A  B (user break generated)  B (no break generated) 7. In the event of contention between a re-execution type exception and a post-execution break in a multistep instruction, the re-execution type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completion type exception. Consequently, in the event of contention between a completion type exception and a post-execution break, the postexecution break is suppressed in accordance with the priorities of the two events. For example, in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition. 20.4 User Break Debug Support Function The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the BRCR register, the DBR register value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break debug support function is shown in figure 20.2. Rev. 3.0, 04/02, page 771 of 1064 Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Exception/ interrupt/trap? Trap Interrupt EXPEVT ← exception code INTEVT ← interrupt code EXPEVT ← H'160 TRA ← TRAPA (imm) SGR ← R15 No Yes Reset exception? (BRCR.UBDE == 1) && (user break exception)? Yes No PC ← DBR PC ← VBR + vector offset Debug program Exception handling routine PC ← H'A0000000 R15 ← SGR (STC instruction) Execute RTE instruction PC ← SPC SR ← SSR End of exception operations Figure 20.2 User Break Debug Support Function Flowchart Rev. 3.0, 04/02, page 772 of 1064 20.5 Examples of Use Instruction Access Cycle Break Condition Settings
Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode  Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions)  Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'00000404 with ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE with ASID = H'70.
Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 Conditions set: Channel A  channel B sequential mode  Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word  Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003722E with ASID = H'70.
Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000 Conditions set: Independent channel A/channel B mode  Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word Rev. 3.0, 04/02, page 773 of 1064  Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. Operand Access Cycle Break Condition Settings
Register settings: BASRA = H'80 / BARA = H'00123456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000ABCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000A512 / BDMRB = H'00000000 / BRCR = H'0080 Conditions set: Independent channel A/channel B mode  Channel A: ASID: H'80 / address: H'00123456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions)  Channel B: ASID: H'70 / address: H'000ABCDE / address mask: H'02 Data: H'0000A512 / data mask: H'00000000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'00123454, a word read at address H'00123456, or a byte read at address H'00123456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000AB000 to H'000ABFFE with ASID = H'70. Rev. 3.0, 04/02, page 774 of 1064 20.6 User Break Controller Stop Function This function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller. 20.6.1 Transition to User Break Controller Stopped State Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit to 1 and enter the stopped state. (1) Initialize BBRA and BBRB to 0; (2) Initialize BRCR to 0; (3) Make a dummy read of BRCR; (4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back. (5) Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not change the values of these registers in the exception handling routine. Do not read or write the following registers while the user break controller clock is stopped: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these registers are read or written, the value cannot be guaranteed. 20.6.2 Cancelling the User Break Controller Stopped State The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps (6) and (7) below to clear the MSTP5 bit to 0 to cancel the stopped state. (6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data back; (7) Make two dummy reads of STBGR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps (6) and (7), make sure that the values in these registers are not changed in the exception handling routine. Rev. 3.0, 04/02, page 775 of 1064 20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov #0, R0 mov.l #BBRA, R1 mov.w R0, @R1 mov.l #BBRB, R1 mov.w R0, @R1 ; (2) Initialize BRCR to 0. mov.l #BRCR, R1 mov.w R0, @R1 ; (3) Dummy read BRCR. mov.w @R1, R0 ; (4) Read STBCR2, then set MSTP5 bit in the read data to 1 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 or #H’1, R0 mov.b R0, @R1 ; (5) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 ; Canceling user break controller stopped state ; (6) Read STBCR2, then clear MSTP5 bit in the read data to 0 and write it back mov.l #STBCR2, R1 mov.b @R1, R0 and #H’FE, R0 mov.b R0, @R1 ; (7) Twice dummy read STBCR2. mov.b @R1, R0 mov.b @R1, R0 Rev. 3.0, 04/02, page 776 of 1064 Section 21 Hitachi User Debug Interface (H-UDI) 21.1 Overview 21.1.1 Features The Hitachi user debug interface (H-UDI) is a serial input/output interface conforming to JTAG, IEEE 1149.1, and IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7751 Series H-UDI support boundary-scan, and is used for emulator connection. The functions of this interface should not be used when using an emulator. Refer to the emulator manual for the method of connecting the emulator. The H-UDI uses six pins (TCK, TMS, TDI, TDO,

, and /BRKACK). In the SH7751 Series, six dedicated emulator pins have been added (AUDSYNC, AUDCK, and AUDATA3 to AUDATA0). The pin functions and serial transfer protocol conform to the JTAG specifications. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the H-UDI. The TAP (test access port) controller and control registers are reset independently of the chip reset pin by driving the

pin low or setting TMS to 1 and applying TCK for at least five clock cycles. The other circuits are reset and initialized in an ordinary reset. The H-UDI circuit has six internal registers: SDBPR, SDBSR, SDIR, SDINT, SDDRH, and SDDRL (these last two together designated SDDR). The SDBPR register supports the JTAG bypass mode, SDBSR is a shift register forming a JTAG boundary scan, SDIR is the command register, SDDR is the data register, and SDINT is the H-UDI interrupt register. SDIR can be accessed directly from the TDI and TDO pins. Rev. 3.0, 04/02, page 777 of 1064 Interrupt/reset etc. Break control /BRKACK TCK Decoder TDI Shift register SDBPR SDBSR SDIR SDINT SDDRH SDDRL TDO MUX AUDSYNC AUDCK Trace control AUDATA3–0 Figure 21.1 Block Diagram of H-UDI Circuit Rev. 3.0, 04/02, page 778 of 1064 Peripheral module bus TAP controller TMS 21.1.3 Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins Pin Name Abbreviation I/O Function When Not Used Clock pin TCK Input Same as the JTAG serial clock input Open* pin. Data is transferred from data input pin TDI to the H-UDI circuit, and data is read from data output pin TDO, in synchronization with this signal. Mode pin TMS Input The mode select input pin. Changing Open* this signal in synchronization with TCK determines the meaning of the data input from TDI. The protocol conforms to the JTAG (IEEE Std 1149.1) specification. Reset pin

Input The input pin that resets the H-UDI. * * This signal is received asynchronously with respect to TCK, and effects a reset of the JTAG interface circuit when low.

must be driven low for a certain period when powering on, regardless of whether or not JTAG is used. This differs from the IEEE specification. Data input pin TDI Input The data input pin. Data is sent to the H-UDI circuit by changing this signal in synchronization with TCK. Open* Data output pin TDO Output The data output pin. Data is sent to the H-UDI circuit by reading this signal in synchronization with TCK. Open Emulator pin / Input/ output Dedicated emulator pin Open* BRKACK AUDSYNC Output Dedicated emulator pin Open 1 1 2, 3 1 1 AUDCK AUDATA3– AUDATA0 Notes: *1 Pulled up inside the chip. When designing a board that allows use of an emulator, or when using interrupts and resets via the H-UDI, there is no problem in connecting a pullup resistance externally. *2 When designing a board that enables the use of an emulator, or when using interrupts and resets via the H-UDI, drive

low for a period overlapping 
at power-on, and also provide for control by

alone. Rev. 3.0, 04/02, page 779 of 1064 *3 Ground fixed or connected to the same signal (or the same behavior) as 
. However, the following problem occurs in the ground fixed. Minute current flows when

is fixed to the ground because it is pulled up in the chip. The current value follows the regulations of the pull-up resistance of the port pin. This current does not affect the operation of the chip; however, it consumes unnecessary power. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or SH7751 Series CPG setting so that the TCK frequency is lower than that of the SH7751 Series peripheral module clock. 21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR and SDBSR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side Abbreviation P4 R/W Address Access Initial 1 Size Value* R/W Access Initial 1 Size Value* Instruction register SDIR R 16 H'FFFF R/W 32 H'FFFFFFFD (Fixed 2 value* ) Data register H SDDR/ R/W H'FFF00008 H'1FF00008 SDDRH 32/16 Undefined — — — Data register L SDDRL R/W H'FFF0000A H'1FF0000A 16 Undefined — — — Bypass register SDBPR — — Undefined R/W 1 — Interrupt factor register SDINT 16 H'0000 W* 32 H'00000000 Boundary scan register SDBSR — — Undefined R/W — Undefined Name Area 7 Address H-UDI Side H'FFF00000 H'1FF00000 — — R/W H'FFF00014 H'1FF00014 — — 3 Notes: *1 Initialized when the

pin goes low or when the TAP is in the Test-Logic-Reset state. *2 The value read from H-UDI is fixed (H'FFFFFFFD). *3 1 can be written to the LSB using the H-UDI interrupt command. Rev. 3.0, 04/02, page 780 of 1064 21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the

pin or in the TAP Test-Logic-Reset state. When this register is written to from the H-UDI, writing is possible regardless of the CPU mode. Operation is undefined if a reserved command is set in this register. Bit: 15 14 13 12 11 10 9 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R R R R R Bits 15 to 8—Test Instruction Bits (TI7–TI0) Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TI7 TI6 TI5 TI4 TI3 TI2 TI1 Bit 8: TI0 Description 0 0 0 0 0 0 0 0 EXTEST 0 0 0 0 0 1 0 0 SAMPLE/PRELOAD 0 1 1 0 — — — — H-UDI reset negate 0 1 1 1 — — — — H-UDI reset assert 1 0 1 — — — — — H-UDI interrupt 1 1 1 1 1 1 1 1 Bypass mode (Initial value) Other than above Reserved Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1. Rev. 3.0, 04/02, page 781 of 1064 21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is initialized by

, but not by a CPU reset. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Note: *: Undefined Bits 31 to 0—DR Data: These bits store the SDDR value. 21.2.3 Bypass Register (SDBPR) The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the H-UDI. Rev. 3.0, 04/02, page 782 of 1064 21.2.4 Interrupt Factor Register (SDINT) The interrupt factor register (SDINT) is a 16-bit register that can be read/written from the CPU. When a (H-UDI interrupt) command is set in the SDIR (Update-IR) via the H-UDI pin, the INTREQ bit is set to 1. While SDIR has the “H-UDI interrupt” command, the SDINT register is connected between H-UDI pins TDI and TDO, and can be read as a 32-bit register. The high 16 bits are 0 and the low 16 bits are SDINT. Only 0 can be written to the INTREQ bit from the CPU. While this bit is 1, the interrupt request continues to be generated, and must therefore be cleared to 0 by the interrupt handler. This register is initialized by

or when in the Test Logic Reset state. Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — INTREQ Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bits 15 to 1— Reserved: These bits always read as 0, and should only be written with 0. Bit 0—Interrupt Request Bit (INTREQ): Shows the existence of an interrupt request from the “H-UDI interrupt” command. The interrupt request can be cleared by writing 0 to this bit from the CPU. When 1 is written to this bit, the existing value is retained. 21.2.5 Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register on the PAD for controlling the chip’s I/O pins. Using the EXTEST and SAMPLE/PRELOAD commands, it can perform a JTAG (IEEE Std 1149.1)-compatible boundary scan test. Table 21.3 shows the relationship between SH7751 Series pins and the boundary scan register. Rev. 3.0, 04/02, page 783 of 1064 Table 21.3 Structure of Boundary Scan Register No. Pin name Type    IN from TDI 418 417 IN 416 STATUS1 CTL 415 STATUS1 OUT 414 STATUS0 CTL 413 STATUS0 OUT 412 DRAK1 CTL 411 DRAK1 OUT 410 DRAK0 CTL 409 DRAK0 OUT 408 DACK1 CTL 407 DACK1 OUT 406 DACK0 CTL 405 DACK0 OUT 404 MD5 IN 403 MD5 CTL 402 MD5 OUT 401 MD4/  IN 400 MD4/  CTL 399 MD4/  OUT 398 MD3/  IN 397 MD3/  CTL 396 MD3/  OUT 395 AUDATA3 CTL 394 AUDATA3 OUT 393 AUDATA2 CTL 392 AUDATA2 OUT 391 AUDATA1 CTL 390 AUDATA1 OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 784 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 389 AUDATA0 CTL 388 AUDATA0 OUT 387 AUDCK CTL 386 AUDCK OUT 385 AUDSYNC CTL 384 AUDSYNC OUT 383 MD7/
 IN 382 MD7/
 CTL 381 MD7/
 OUT 380 MD0/SCK2 IN 379 MD0/SCK2 CTL 378 MD0/SCK2 OUT 377 MD1/TXD2 IN 376 MD1/TXD2 CTL 375 MD1/TXD2 OUT 374 SCK IN 373 SCK CTL 372 SCK OUT 371 IN 369 
 /MD8 
 /MD8 
 /MD8 OUT 368 TCLK IN 367 TCLK CTL 366 TCLK OUT 370 CTL 365 RXD IN 364 MD2/RXD2 IN 363 TXD IN 362 TXD CTL 361 TXD OUT 360  IN Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 785 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 359 MD6/  IN 358 IN 356  / / / 355 NMI IN 354 IN 351     350 AD0 IN 349 AD0 CTL 348 AD0 OUT 347 AD1 IN 346 AD1 CTL 345 AD1 OUT 344 AD2 IN 343 AD2 CTL 342 AD2 OUT 341 AD3 IN 340 AD3 CTL 339 AD3 OUT 338 AD4 IN 337 AD4 CTL 336 AD4 OUT 335 AD5 IN 334 AD5 CTL 333 AD5 OUT 332 AD6 IN 331 AD6 CTL 330 AD6 OUT 357 353 352 CTL OUT IN IN IN Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 786 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 329 AD7 IN 328 AD7 CTL 327 AD7 OUT 326 C/ IN 325 C/ CTL 324 C/ OUT 323 AD8 IN 322 AD8 CTL 321 AD8 OUT 320 AD9 IN 319 AD9 CTL 318 AD9 OUT 317 AD10 IN 316 AD10 CTL 315 AD10 OUT 314 AD11 IN 313 AD11 CTL 312 AD11 OUT 311 AD12 IN 310 AD12 CTL 309 AD12 OUT 308 AD13 IN 307 AD13 CTL 306 AD13 OUT 305 AD14 IN 304 AD14 CTL 303 AD14 OUT 302 AD15 IN 301 AD15 CTL 300 AD15 OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 787 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 299 C/ IN 298 C/ CTL 297 C/ OUT 296 PAR IN 295 PAR CTL 294 PAR OUT 293       
 
 
   


       C/ C/ C/ IN 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT IN CTL OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 788 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 269 AD16 IN 268 AD16 CTL 267 AD16 OUT 266 AD17 IN 265 AD17 CTL 264 AD17 OUT 263 AD18 IN 262 AD18 CTL 261 AD18 OUT 260 AD19 IN 259 AD19 CTL 258 AD19 OUT 257 AD20 IN 256 AD20 CTL 255 AD20 OUT 254 AD21 IN 253 AD21 CTL 252 AD21 OUT 251 AD22 IN 250 AD22 CTL 249 AD22 OUT 248 AD23 IN 247 AD23 CTL 246 AD23 OUT 245 C/ IN 244 C/ CTL 243 C/ OUT 242 AD24 IN 241 AD24 CTL 240 AD24 OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 789 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 239 AD25 IN 238 AD25 CTL 237 AD25 OUT 236 AD26 IN 235 AD26 CTL 234 AD26 OUT 233 AD27 IN 232 AD27 CTL 231 AD27 OUT 230 AD28 IN 229 AD28 CTL 228 AD28 OUT 227 AD29 IN 226 AD29 CTL 225 AD29 OUT 224 AD30 IN 223 AD30 CTL 222 AD30 OUT 221 AD31 IN 220 AD31 CTL 219 AD31 OUT 218 IN 211     /
  /
  /
 
/ 

/ 
210 PCICLK 217 216 215 214 213 212 CTL OUT IN CTL OUT CTL OUT IN Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 790 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 209 CTL 206 


 
 205 IDSEL IN 204 IN 185  /MD9  /MD9  /MD9  /MD10  /MD10  /MD10       


 
 
 
  / /  /  / 184 A25 CTL 183 A25 OUT 182 A24 CTL 181 A24 OUT 180 A23 CTL 208 207 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 OUT CTL OUT CTL OUT IN CTL OUT IN CTL OUT CTL OUT CTL OUT CTL OUT IN CTL OUT CTL OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 791 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 179 A23 OUT 178 A22 CTL 177 A22 OUT 176 A21 CTL 175 A21 OUT 174 A20 CTL 173 A20 OUT 172 A19 CTL 171 A19 OUT 170 A18 CTL 169 A18 OUT 168 D31 IN 167 D31 CTL 166 D31 OUT 165 D30 IN 164 D30 CTL 163 D30 OUT 162 D29 IN 161 D29 CTL 160 D29 OUT 159 D28 IN 158 D28 CTL 157 D28 OUT 156 D27 IN 155 D27 CTL 154 D27 OUT 153 D26 IN 152 D26 CTL 151 D26 OUT 150 D25 IN Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 792 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 149 D25 CTL 148 D25 OUT 147 D24 IN 146 D24 CTL 145 D24 OUT 144 D23 IN 143 D23 CTL 142 D23 OUT 141 D22 IN 140 D22 CTL 139 D22 OUT 138 D21 IN 137 D21 CTL 136 D21 OUT 135 D20 IN 134 D20 CTL 133 D20 OUT 132 D19 IN 131 D19 CTL 130 D19 OUT 129 D18 IN 128 D18 CTL 127 D18 OUT 126 D17 IN 125 D17 CTL 124 D17 OUT 123 D16 IN 122 D16 CTL 121 D16 OUT 120 /DQM3 CTL Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 793 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 119 OUT 117 /DQM3  /DQM2  /DQM2 116 A17 CTL 115 A17 OUT 114 A16 CTL 113 A16 OUT 112 A15 CTL 111 A15 OUT 110 A14 CTL 109 A14 OUT 108 A13 CTL 107 A13 OUT 106 A12 CTL 105 A12 OUT 104 A11 CTL 103 A11 OUT 102 A10 CTL 101 A10 OUT 118 CTL OUT 100 A9 CTL 99 A9 OUT 98 A8 CTL 97 A8 OUT 96 A7 CTL 95 A7 OUT 94 A6 CTL 93 A6 OUT 92 A5 CTL 91 A5 OUT 90 A4 CTL Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 794 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 89 A4 OUT 88 A3 CTL 87 A3 OUT 86 A2 CTL 85 A2 OUT 84 A1 CTL 83 A1 OUT 82 A0 CTL 81 A0 OUT 80 CTL 75       74 CKE CTL 73 CKE OUT 72 CTL 65 // // RD/ RD/  /DQM1  /DQM1 /DQM0 /DQM0 64 D15 IN 63 D15 CTL 62 D15 OUT 61 D14 IN 60 D14 CTL 79 78 77 76 71 70 69 68 67 66 OUT CTL OUT CTL OUT OUT CTL OUT CTL OUT CTL OUT Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 795 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 59 D14 OUT 58 D13 IN 57 D13 CTL 56 D13 OUT 55 D12 IN 54 D12 CTL 53 D12 OUT 52 D11 IN 51 D11 CTL 50 D11 OUT 49 D10 IN 48 D10 CTL 47 D10 OUT 46 D9 IN 45 D9 CTL 44 D9 OUT 43 D8 IN 42 D8 CTL 41 D8 OUT 40 D7 IN 39 D7 CTL 38 D7 OUT 37 D6 IN 36 D6 CTL 35 D6 OUT 34 D5 IN 33 D5 CTL 32 D5 OUT 31 D4 IN 30 D4 CTL Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 796 of 1064 Table 21.3 Structure of Boundary Scan Register (cont) No. Pin name Type 29 D4 OUT 28 D3 IN 27 D3 CTL 26 D3 OUT 25 D2 IN 24 D2 CTL 23 D2 OUT 22 D1 IN 21 D1 CTL 20 D1 OUT 19 D0 IN 18 D0 CTL 17 D0 OUT 16   / /             CTL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT CTL OUT to TDO Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW. Rev. 3.0, 04/02, page 797 of 1064 21.3 Operation 21.3.1 TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG.
The transition condition is the TMS value at the rising edge of TCK.
The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge.
The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO is in the high-impedance state.
In a transition to

= 0, a transition is made to the Test-Logic-Reset state asynchronously with respect to TCK. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR Update-IR 0 1 Figure 21.2 TAP Control State Transition Diagram Rev. 3.0, 04/02, page 798 of 1064 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 0 21.3.2 H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending a H-UDI reset assert command, and then sending a H-UDI reset negate command, from the H-UDI pin (see figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the length of time the reset pin is held low in order to effect a power-on reset. H-UDI reset assert H-UDI pin H-UDI reset negate Chip internal reset CPU state Normal Reset Reset processing Figure 21.3 H-UDI Reset 21.3.3 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an address based on VBR and return effected by means of an RTE instruction. The exception code stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be controlled with bits 3 to 0 of control register IPRC. The H-UDI interrupt request signal is asserted when, after the command is set (Update-IR), the INTREQ bit of the SDINT register is set to 1. The interrupt request signal is not negated until 0 is written to the INTREQ bit by software, and there is therefore no risk of the interrupt request being unexpectedly missed. While the H-UDI interrupt command is set in SDIR, the SDINT register is connected between TDI and TDO. Rev. 3.0, 04/02, page 799 of 1064 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) The H-UDI pin can be set in the JTAG boundary scan mode by setting a command in SDIR from the H-UDI. However, in the case of the SH7751 Series, the bypass register (SDBPR) is not initialized in the Capture-DR state, and the following limitations apply: 1. Clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, and CKIO) are excluded from the boundary scan. 2. Reset-related signals (
, 
, and CA) are excluded from the boundary scan. 3. H-UDI signals (TCK, TDI, TDO, TMS, and

) are excluded from the boundary scan. 4. With EXTEST, assert the 
pin (Low), negate the 
pin (High), and assert the CA pin (High). With SAMPLE/PRELOAD, assert the CA pin (High). 5. When executing a boundary scan (EXTEST, SAMPLE/PRELOAD, and BYPASS), supply a clock signal to the EXTAL pin. The allowed range of input clock frequencies is from 1 to 33.3 MHz. Execute the boundary scan after tOSC1 (the power-on oscillation-stabilization time) has elapsed. The clock signal need not be supplied to the EXTAL pin after tOSC1 has elapsed. For details on tOSC1 (the power-on oscillation-stabilization time), see section 23, Electrical Characteristics. 6. When the SH7751 is in bypass mode, the bypass register (SDBPR) is not fixed in the CaptureDR state. (It is cleared to 0 in the SH7751R.) 21.4 Usage Notes 1. SDIR Command Once an SDIR command is set, it does not change until another command is written from the H-UDI, unless initialized by asserting

or the TAP is set in the Test-Logic-Reset state. 2. SDIR Commands in Sleep Mode Sleep mode is cleared by an H-UDI interrupt or H-UDI reset, and these exception requests are accepted in this mode. In standby mode, neither an H-UDI interrupt nor an H-UDI reset is accepted. 3. In standby mode, the H-UDI function cannot be used. Furthermore, TCK must be retained at a high level when entering the standby mode in order to retain the TAP state before and after standby mode. 4. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. Rev. 3.0, 04/02, page 800 of 1064 Section 22 PCI Controller (PCIC) 22.1 Overview The PCI Controller (PCIC) controls the PCI bus and transfers data between memory connected to the external bus and a PCI device connected to the PCI bus. The ability for PCI devices to be connected directly not only facilitates the design of systems using PCI buses but also enables systems to be more compact and capable of high-speed data transfer. 22.1.1 Features The PCIC has the following features:
Conforms to PCI version 2.1.*
Compatible with PCI bus operating speeds of 33 MHz/66 MHz.
Compatible with 32-bit PCI bus.
Up to four PCI master devices running at 33 MHz or one PCI master device at 66 MHz can be connected.
Arbitration control is available as a PCI host function.
Can operate as master or target.
When operating as master, PIO and DMA transfer are available.
Four DMA transfer channels.
Six 32-bit x 16 longword internal FIFO (one for target reading, one for target writing, and four for DMA transfer).
Asynchronous operation of BSC bus clock and PCI bus clock available, and CKIO can be used as PCI bus clock.
SRAM, DRAM, SDRAM, and MPX* can be used as external memory for PCI bus data transfers.
32-bit or 16-bit memory data bus for data transfers with PCI bus (32-bit bus when connected to SDRAM).
Support for big endian and little endian local bus (PCI bus operates with little endian, while internal bus for peripheral modules operates with big endian). 1 2 Notes: *1 The PCIC of the SH7751 series does not completely conform to version 2.1 of the PCI specifications. When configuring a PCI system in which an SH7751-series device is used, take the necessary steps and confirm the system’s operation before using it. (1) In version 2.1 of the PCI specifications, the I/O space for PCI devices is defined as being no more than 256 bytes, but the SH7751’s specifications require 1 Mbytes of I/O space for the PCI. Rev. 3.0, 04/02, page 801 of 1064 (2) Version 2.1 of the PCI specifications states that any combination of the byteenable signals (
 [3:0]) is possible when accepting a configuration access. The SH7751 specifications, however, define the values of
 [3:0] as being ignored on the acceptance of a configuration access and that access is in longword (DWORD) units only. *2 MPX is only supported by the SH7751R and is not supported by the SH7751. Rev. 3.0, 04/02, page 802 of 1064 22.1.2 Block Diagram Figure 22.1 is a block diagram of the PCIC. PCI bus PCIC module Interrupts Interrupt control PCI bus interface Local register Internal peripheral module bus (Peripheral bus) Internal peripheral module bus interface Data transfer control PCI configuration register FIFO 32B × 2 sides × 6 Local register Local register Bus request Acknowledge PCIC bus controller Local register Local bus Local bus clock (Bφ) cycle: Bcyc Feedback input clock from CKIO PCI clock 33/66 MHz (PCICLK) Figure 22.1 PCIC Block Diagram Rev. 3.0, 04/02, page 803 of 1064 22.1.3 Pin Configuration Table 22.1 shows the configuration of I/O pins of the PCIC. Table 22.1 Pin Configuration PCI Standard No. Pin Name Signal Name Function I/O Status in Operating Modes I/O Pull-up Type Resistor*1 Host Non-host Remarks Master Target Master Target 1 PCICLK CLK PCI input clock (33 MHz/66 MHz) in I I I I 2
 — Reset output out O O — — AD31 to AD0 AD[31:0] Address/data t/s I/O I/O I/O I/O Low level output at reset 4 C/ to C/ C/[3:0] Command/byte enable t/s O I O I Low level output at reset 5 PAR PAR t/s I/O I/O I/O I/O Low level output at reset
   


     
 3 6 7 8 9 10 11 12 13 14 15 16 17  
/   
/   

    
/  MD9 Parity Bus cycle s/t/s Yes O I O I Initiator ready s/t/s Yes O I O I Target ready s/t/s Yes I O I O Transaction stop s/t/s Yes I O I O Exclusive access control s/t/s Yes O I O I Device select s/t/s Yes I O I O Bus request (host function) t/s Yes I I — — Bus grant t/s Yes — — I Bus grant (host function) t/s No O O — Bus request t/s No — — O Parity error s/t/s Yes I/O O I/O O System error o/d Yes O O O O Interrupt (async) o/d Yes — — O O Bus request (host function) t/s Yes I I — — PCI clock switch (BCLK/PCICLK) in I I I I Rev. 3.0, 04/02, page 804 of 1064 — 2 * Table 22.1 Pin Configuration (cont) PCI Standard No. Pin Name Signal Name 18
 /  MD10 19
  20
 to
 21 IDSEL  to  IDSEL Function I/O Status in Operating Modes I/O Pull-up Type Resistor*1 Host Non-host Master Target Master Target Bus request (host function) t/s Host bridge function ON/OFF in Bus request (host function) t/s Bus grant (host function) Config device select Yes I I — — I I I I I I — — t/s O O — — in — — I I Yes in: Input out: Output s/t/s: Sustained try state o/d: Open drain t/s: Try state Notes: *1 Terminal provided with a pull-up resistor. *2 The values of external pins are sampled in a power-on reset by means of the *3 This must be fixed at Low when not in used. 22.1.4 Remarks 2 * 3 *
 pin. Register Configuration The PCIC has the PCI configuration registers and PCI control registers shown in table 22.2, 22.3 and 22.4. Also, the PCI bus address space is allocated to the internal bus for the peripheral modules, making it possible to access the PCI bus by program IO (PIO). Not only do these registers control the PCI bus but also enable high-speed data transfers between the PCI device and memory on the SH-4 external data bus (hereinafter, the SH-4 external data bus is referred to as the local bus to distinguish it from the PCI bus). Rev. 3.0, 04/02, page 805 of 1064 Table 22.2 List of PCI Configuration Registers PCI Configuration P4 Address Address Area 7 Address Access Size H'00 H'FE200000 H'1E200000 32 H'04 H'FE200004 H'1E200004 32 H'08 H'FE200008 H'1E200008 32 Name Abbreviation PCI R/W PP-Bus R/W Initial Value PCI configuration register 0 PCICONF0 R R * PCI configuration register 1 PCICONF1 R/W R/W H'02900080 PCI configuration register 2 PCICONF2 R R R/W[31:8] R (other) H'xxxxxx* PCI configuration register 3 PCICONF3 R/W[15:8] R (other) R/W[15:8] R (other) H'00000000 H'0C H'FE20000C H'1E20000C 32 PCI configuration register 4 PCICONF4 R/W R/W H'00000001 H'10 H'FE200010 H'1E200010 32 PCI configuration register 5 PCICONF5 R/W R/W H'00000000 H'14 H'FE200014 H'1E200014 32 PCI configuration register 6 PCICONF6 R/W R/W H'00000000 H'18 H'FE200018 H'1E200018 32 PCI configuration register 7 PCICONF7 R R H'00000000 H'1C H'FE20001C H'1E20001C 32 PCI configuration register 8 PCICONF8 R R H'00000000 H'20 H'FE200020 H'1E200020 32 PCI configuration register 9 PCICONF9 R R H'00000000 H'24 H'FE200024 H'1E200024 32 PCI configuration register 10 PCICONF10 R R H'00000000 H'28 H'FE200028 H'1E200028 32 PCI configuration register 11 PCICONF11 R R/W H'xxxxxxxx H'2C H'FE20002C H'1E20002C 32 PCI configuration register 12 PCICONF12 R R H'00000000 H'30 H'FE200030 H'1E200030 32 PCI configuration register 13 PCICONF13 R R H'00000040 H'34 H'FE200034 H'1E200034 32 PCI configuration register 14 PCICONF14 R R H'00000000 H'38 H'FE200038 H'1E200038 32 PCI configuration register 15 PCICONF15 R/W[7:0] R (other) R/W[7:0] R (other) H'00000100 H'3C H'FE20003C H'1E20003C 32 PCI configuration register 16 PCICONF16 R R R/W[18:16] R (other) H'00010001 H'40 H'FE200040 H'1E200040 32 PCI configuration register 17 PCICONF17 R/W[1:0] R (other) R/W[1:0] R (other) H'00000000 H'44 H'FE200044 H'1E200044 32 Reserved — R R H'00000000 H'48 to H'FC H'FE200048 H'1E200048 32 to to H'FE2000FC H'1E2000FC Notes: 1 2 x: Undefined value *1 Varies with the logic versions of the chip. *2 H'35051054 for the SH7751; H'350E1054 for the SH7751R. Rev. 3.0, 04/02, page 806 of 1064 Table 22.3 PCI Configuration Register Configuration PCI Configuration P4 Address Address PCI Configuration Register Area 7 Address 31 to 24 23 to 16 15 to 8 7 to 0 PCI R/W PP-Bus R/W H'00 H'FE200000 H'1E200000 Device ID Device ID Vendor ID Vendor ID R R H'04 H'FE200004 H'1E200004 Status Status Command Command R/W R/W H'08 H'FE200008 H'1E200008 Class code Class code Class code Revision ID R R/W[31:8] R (other) H'0C H'FE20000C H'1E20000C BIST Header type PCI latency timer Cache line size R/W[15:8] R (other) R/W[15:8] R (other) H'10 H'FE200010 H'1E200010 Base address (I/O area) Base address (I/O area) Base address (I/O area) Base address (I/O area) R/W R/W H'14 H'FE200014 H'1E200014 Base address Base address Base address Base address R/W (local address (local address (local address (local address area 0) area 0) area 0) area 0) R/W H'18 H'FE200018 H'1E200018 Base address Base address Base address Base address R/W (local address (local address (local address (local address area 1) area 1) area 1) area 1) R/W H'1C H'FE20001C H'1E20001C Reserved Reserved Reserved Reserved R R H'20 H'FE200020 H'1E200020 Reserved Reserved Reserved Reserved R R H'24 H'FE200024 H'1E200024 Reserved Reserved Reserved Reserved R R H'28 H'FE200028 H'1E200028 Reserved Reserved Reserved Reserved R R H'2C H'FE20002C H'1E20002C Subsystem ID Subsystem ID Subsystem vendor ID Subsystem vendor ID R R/W H'30 H'FE200030 H'1E200030 Reserved Reserved Reserved Reserved R R H'34 H'FE200034 H'1E200034 Reserved Reserved Reserved Extended function pointer R R H'38 H'FE200038 H'1E200038 Reserved Reserved Reserved Reserved R R H'3C H'FE20003C H'1E20003C Max_Lat Min_Gnt Interrupt pin Interrupt line R/W[7:0] R (other) R/W[7:0] R (other) H'40 H'FE200040 H'1E200040 Power management related Power management related Power management related Power management related R R/W[18:16] R (other) H'44 H'FE200044 H'1E200044 Power management related Power management related Power management related Power management related R/W[1:0] R (other) R/W[1:0] R (other) H'48 to H'0FC H'FE200048 to H'FE2000FC H'1E200048 Reserved to H'1E2000FC Reserved Reserved Reserved R R Rev. 3.0, 04/02, page 807 of 1064 Table 22.4 List of PCIC Local Registers PCI I/O Address (SH7751/ P4 SH7751R) Address Name Abbreviation PCI R/W PP-Bus R/W Initial Value Area 7 Address Access Size PCI control register PCICR R R/W H'000000*0 H'100/ H'00 H'FE200100 H'1E200100 32 Local space register 0 for PCI PCILSRO R R/W H'00000000 H'104/ H'04 H'FE200104 H'1E200104 32 Local space register 1 for PCI PCILSR1 R R/W H'00000000 H'108/ H'08 H'FE200108 H'1E200108 32 Local address register 0 for PCI PCILAR0 R/W R/W H'00000000 H'10C/ H'0C H'FE20010C H'1E20010C 32 Local address register 1 for PCI PCILAR1 R/W R/W H'00000000 H'110/ H'10 H'FE200110 H'1E210110 32 PCI interrupt register PCIINT R/W R/W H'00000000 H'114/ H'14 H'FE200114 H'1E200114 32 PCI interrupt mask register PCIINTM R/W R/W H'00000000 H'118/ H'18 H'FE200118 H'1E200118 32 Error address data register for PCI PCIALR R R H'xxxxxxxx H'11C/ H'1C H'FE20011C H'1E20011C 32 Error command data register for PCI PCICLR R R H'0000000x H'120/ H'20 H'FE200120 H'1E200120 32 Reserved — — — H'00000000 H'124 to H'12C/ H'24 to H'2C H'FE200124 to H'FE20012C H'1E200124 to H'1E20012C 32 PCI arbiter interrupt register PCIAINT R/W R/W H'00000000 H'130/ H'30 H'FE200130 H'1E200130 32 PCI arbiter interrupt mask register PCIAINTM R/W R/W H'00000000 H'134/ H'34 H'FE200134 H'1E200134 32 Error bus master data register for PCI PCIBMLR R R H'00000000 H'138/ H'38 H'FE200138 H'1E200138 32 Reserved — — — H'00000000 H'13C/ H'3C H'FE20013C H'1E20013C 32 DMA transfer arbitration register for PCI PCIDMABT R/W R/W H'00000000 H'140/ H'40 H'FE200140 H'1E200140 32 Reserved — — — H'00000000 H'144 to H'17C/ H'44 to H'7C H'FE200144 to H'FE20017C H'1E200144 to H'1E20017C 32 DMA transfer PCI address register 0 for PCI PCIDPA0 R/W R/W H'00000000 H'180/ H'80 H'FE200180 H'1E200180 32 DMA transfer local bus starting address regsiter 0 for PCI PCIDLA0 R/W R/W H'00000000 H'184/ H'84 H'FE200184 H'1E200184 32 DMA transfer count register 0 for PCI PCIDTC0 R/W R/W H'00000000 H'188/ H'88 H'FE200188 H'1E200188 32 Rev. 3.0, 04/02, page 808 of 1064 Table 22.4 List of PCIC Local Registers (cont) PCI I/O Address (SH7751/ P4 SH7751R) Address Abbreviation PCI R/W PP-Bus R/W Initial Value Area 7 Address Access Size DMA control register 0 for PCI PCIDCR0 R/W R/W H'00000000 H'18C/ H'8C H'FE20018C H'1E20018C 32 DMAPCI address register 1 for PCI PCIDPA1 R/W R/W H'00000000 H'190/ H'90 H'FE200190 H'1E200190 32 DMA transfer local bus starting address register 1 for PCI PCIDLA1 R/W R/W H'00000000 H'194/ H'94 H'FE200194 H'1E200194 32 DMA transfer count register 1 for PCI PCIDTC1 R/W R/W H'00000000 H'198/ H'98 H'FE200198 H'1E200198 32 DMA control register 1 for PCI PCIDCR1 R/W R/W H'00000000 H'19C/ H'9C H'FE20019C H'1E20019C 32 DMA transfer PCI address register 2 for PCI PCIDPA2 R/W R/W H'00000000 H'1A0/ H'A0 H'FE2001A0 H'1E2001A0 32 DMA transfer local bus starting address register 2 for PCI PCIDLA2 R/W R/W H'00000000 H'1A4/ H'A4 H'FE2001A4 H'1E2001A4 32 DMA transfer count register 2 for PCI PCIDTC2 R/W R/W H'00000000 H'1A8/ H'A8 H'FE2001A8 H'1E2001A8 32 DMA control register 2 for PCI PCIDCR2 R/W R/W H'00000000 H'1AC/ H'AC H'FE2001AC H'1E2001AC 32 DMA transfer PCI address register 3 for PCI PCIDPA3 R/W R/W H'00000000 H'1B0/ H'B0 H'FE2001B0 H'1E2001B0 32 DMA transfer local bus starting address register 3 for PCI PCIDLA3 R/W R/W H'00000000 H'1B4/ H'B4 H'FE2001B4 H'1E2001B4 32 DMA transfer count register 3 for PCI PCIDTC3 R/W R/W H'00000000 H'1B8/ H'B8 H'FE2001B8 H'1E2001B8 32 DMA control register 3 for PCI PCIDCR3 R/W R/W H'00000000 H'1BC/ H'BC H'FE2001BC H'1E2001BC 32 PIO address register PCIPAR — R/W H'80xxxxxx — H'FE2001C0 H'1E2001C0 32 Memory space base register PCIMBR — R/W H'xx000000 — H'FE2001C4 H'1E2001C4 32 IO space base register PCIIOBR — R/W H'xxxx0000 — H'FE2001C8 H'1E2001C8 32 PCI power management interrupt register PCIPINT — R/W H'00000000 — H'FE2001CC H'1E2001CC 32 PCI power management interrupt mask register PCIPINTM — R/W H'00000000 — H'FE2001D0 H'1E2001D0 32 PCI clock control register PCICLKR — R/W H'00000000 — H'FE2001D4 H'1E2001D4 32 Reserved — H'00000000 — H'FE2001D8 to H'FE2001DC H'1E2001D8 to H'1E2001DC 32 Name Rev. 3.0, 04/02, page 809 of 1064 Table 22.4 List of PCIC Local Registers (cont) Abbreviation Name PCI R/W PP-Bus R/W Initial Value PCI I/O Address (SH7751/ P4 SH7751R) Address Area 7 Address Access Size PCI bus control register 1 PCIBCR1 — R/W H'*0000000 — H'FE2001E0 H'1E2001E0 32 PCI bus control register 2 PCIBCR2 — R/W H'0000*FFC — H'FE2001E4 H'1E2001E4 32 PCI wait control register 1 PCIWCR1 — R/W H'77777777 — H'FE2001E8 H'1E2001E8 32 PCI wait control register 2 PCIWCR2 — R/W H'FFFEEFFF — H'FE2001EC H'1E2001EC 32 PCI wait control register 3 PCIWCR3 — R/W H'07777777 — H'FE2001F0 H'1E2001F0 32 PCIC discrete memory control register PCIMCR — R/W H'00000000 — H'FE2001F4 H'1E2001F4 32 PCIC bus control 1 register 3* PCIBCR3 — R/W H'00000001 — H'FE2001F8 H'1E2001F8 32 Reserved — H'FE2001FC H'1E2001FC 32 Port control register PCIPCTR — R/W H'00000000 — H'FE200200 H'1E200200 32 Port data register PCIPDTR — R/W H'00000000 — H'FE200204 H'1E200204 32 Reserved — H'00000000 — H'FE200208 to H'FE20021C H'1E200208 to H'1E20021C 32 PIO data register PCIPDR H'xxxxxxxx — H'FE200220 H'1E200220 32 H'00000000 — R/W Notes: * The values of some external pins are sampled in a power-on reset by means of the
 pin. x indicates “undefined.” *1: PCIC bus control register 3 is provided only in the SH7751R. The relevant areas of the SH7751 are reserved areas. Rev. 3.0, 04/02, page 810 of 1064 22.2 PCIC Register Descriptions 22.2.1 PCI Configuration Register 0 (PCICONF0) Bit: 31 30 29 28 27 26 25 DEVID15 DEVID14 DEVID13 DEVID12 DEVID11 DEVID10 DEVID9 24 DEVID8 Initial value: 0 0 1 1 0 1 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 DEVID7 DEVID6 DEVID5 DEVID4 DEVID3 DEVID2 DEVID1 DEVID0 Initial value: 0 0 0 0 0/1* 1 0/1* 1/0* PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 VNDID15 VNDID14 VNDID13 VNDID12 VNDID11 VNDID10 VNDID9 VNDID8 Initial value: 0 0 0 1 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 VNDID7 VNDID6 VNDID5 VNDID4 VNDID3 VNDID2 VNDID1 VNDID0 Initial value: 0 1 0 1 0 1 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Note: * These values differ between SH7751 and SH7751R. Indicated with * are for the SH7751R. PCI configuration register 0 (PCICONF0) is a 32-bit read-only register that includes the device ID and vender ID PCI configuration registers stipulated in the PCI local bus specifications. The SH7751 ID (H'3505) or the SH7751R ID (H'350E) is read from bits 31 to 16; the Hitachi ID (H'1054) is read from bits 15 to 0. All bits of the PCICONF0 are fixed in hardware. Rev. 3.0, 04/02, page 811 of 1064 Bits 31 to 16—DEVID15 to 0: These bits specify the device ID of the SH7751 or SH7751R allocated by the PCI device vendor. H'3505 (fixed in hardware) for the SH7751, and H'350E (fixed in hardware) for the SH7751R. Bits 15 to 0—DNVID15 to 0: These bits specify Hitachi as the PCI device maker (vendor ID). (H'1054: fixed in hardware) 22.2.2 PCI Configuration Register 1 (PCICONF1) Bit: Initial value: 31 30 29 28 27 26 25 24 DPE SSE RMA RTA STA DEV1 DEV0 DPD 0 0 0 0 0 0 1 0 PCI-R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC PP Bus-R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC Bit: 23 22 21 20 19 18 17 16 FBBC UDF 66M PM — — — — Initial value: 1 0 0 1 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R/W R/W R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — PBBE SER Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R/W PP Bus-R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 WCC PER VPS MWIE SPC BUM MES IOS 1 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R R R R/W R/W R/W PP Bus-R/W: R/W R/W R R R R/W R/W R/W Initial value: Note: Cleared by writing WC:1. (Writing of 0 is ignored.) PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the status and command PCI configuration registers stipulated in the PCI local bus specifications. The status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to 0 (command register) contain the settings required for initiating transfers on the PCI bus. Rev. 3.0, 04/02, page 812 of 1064 Bits 31 to 27, 24, 8 to 6, and 2 to 0 can be written to from both the PP and PCI buses. However, bits 31 to 27 and 24 are write-clear bits that are cleared when 1 is written to them. Bits 22 and 21 can be written to from the PP bus. Other bits are fixed in hardware. The PCICONF1 register is initialized to H'02900080 at a power-on reset or software reset. Always write to this register before initiating transfers on the PCI bus. Bit 31—Parity Error Detection Status (DPE): Indicates the detection of a parity error in read data when the PCIC is operating as the master, or a party error in write data when the PCIC is operating as a target. Bit 31: DPE Description 0 No parity error detected by device 1 Parity error detected by device (Initial value) Set this bit regardless of the parity error response bit (bit 6) on the device Bit 30—System Error Output Status (SSE): Indicates the  assert operation of the PCIC. Bit 30: SSE Description 0 Device not asserting 

1 (Initial value) Device asserting 

(Value retained until cleared) Bit 29—Master abort receive status (RMA): Indicates the termination of transaction by master abort when the PCIC is operating as the master. Bit 29: RMA Description 0 No transaction termination using bus master abort 1 Detection by bus master of transaction termination by bus master abort (Initial value) However, in the case of a master abort in a special cycle, notify the master devices that are not set Bit 28—Target Abort Receive Status (RTA): Indicates the termination of transaction by master abort when the PCIC is operating as the master. Bit 28: RTA Description 0 No transaction termination using target abort 1 Detection by bus master of transaction termination by target abort (Initial value) Bit 27—Target Abort Execution Status (STA): Indicates the termination of transaction by target abort when the PCIC is operating as the target. Rev. 3.0, 04/02, page 813 of 1064 Bit 27: STA Description 0 No transaction termination using target abort by target device (Initial value) 1 Transaction termination by target abort by target device. Notification by target device Bits 26 and 25— Timing Status (DEV1 and 0): These bits indicate the  response timing when the PCIC is operating as a target. Bit 26: DEV1 Bit 25: DEV0 Description 0 0 High-speed (not supported) 1 Medium speed 0 Low speed (not supported) 1 Reserved 1 (Initial value) Bit 24—Data Parity Status (DPD): Indicates the  assert operation or the detection of  when the PCIC is operating as the master. This bit is set only when the parity error response bit (bit 6) is 1. Bit 24: DPD Description 0 Data parity not detected 1 Data parity occurred (Initial value) Bit 23—High-Speed Back-To-Back Status (FBBC): Shows whether a high-speed back-to-back transfer to a different target can be accepted when the PCIC is operating as a target. Bit 23: FBBC Description 0 The target does not have a high-speed back-to-back transaction function for use with other targets 1 The target has a high-speed back-to-back transaction function for use with other targets (Initial value) Bit 22—User Defined Function System (UDF): Shows whether user defined functions are supported. Bit 22: UDF Description 0 This device does not support user functions 1 This device supports user functions (Initial value) Bit 21—66 MHz Operating Status (66M): Shows whether 66 MHz operation is supported. Rev. 3.0, 04/02, page 814 of 1064 Bit 21: 66M Description 0 This device supports 33 MHz operation 1 This device supports 66 MHz operation (Initial value) Bit 20—PCI Power Management (PM): Shows whether the PCI power management is supported. Bit 20: PM Description 0 Power management not supported 1 Power management supported (Initial value) Bits 19 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—High-Speed Back-To-Back Control (PBBE): Selects whether or not to allow high-speed back-to-back control with different targets when privileged as the master. Bit 9: PBBE Description 0 Allows high-speed back-to-back control only with same target (Initial value) 1 Allows high-speed back-to-back control with different target (Not supported) Bit 8— Output Control (SER): Controls the  output. Bit 8: SER 0 1 Description 

output disabled (Hi-Z) 

output enabled (Initial value) Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address and data are output in master write operations, only address is output in master read operations, and only data is output in target read operations, at least in two clocks. Bit 7: WCC Description 0 Disable address/data stepping control 1 Enable address/data stepping control (Initial value) Bit 6—Parity Error Response (PER): Controls the device response when a parity error is detected or a parity error report is received.  is asserted only when PER = 1. Rev. 3.0, 04/02, page 815 of 1064 Bit 6: PER Description 0 Ignore detected parity errors 1 Respond to detected parity error (Initial value) Bit 5—VGA Pallet Snoop Control (VPS) Bit 5: VPS Description 0 VGA-compatible device 1 The device does not respond to pallet register writes (not supported) (Initial value) Bit 4—Memory Write and Invalidate Control (MWIE): Controls the issuance of memory and invalidate command when the PCIC is operating as the master. Bit 4: MWIE Description 0 The device uses memory write 1 The device can execute memory write and invalidate commands (not supported) (Initial value) Bit 3—Special Cycle Control (SPC): Shows whether special cycles are supported when the PCIC is operating as a target. Bit 3: SPC Description 0 Ignore special cycle 1 Monitor special cycle (not supported) (Initial value) Bit 2—PCI Bus Master Control (BUM): Controls the bus master operation. Bit 2: BUM Description 0 Disable bus master operation 1 Enable bus master operation (Initial value) Bit 1—Memory Space Control (MES): Controls the access to the memory space when the PCIC is operating as a target. When this bit is 0, all memory transfers to the PCIC are terminated by master abort. Bit 1: MES Description 0 Disable access to memory space 1 Enable access to memory space Rev. 3.0, 04/02, page 816 of 1064 (Initial value) Bit 0—I/O Space Control (IOS): Controls the access to the I/O space when the PCIC is operating as a target. When this bit is 0, all I/O transfers to the PCIC are terminated by master abort. Bit 0: IOS Description 0 Disable access to I/O space 1 Enable access to I/O space 22.2.3 (Initial value) PCI Configuration Register 2 (PCICONF2) Bit: 31 30 29 28 27 26 25 24 CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16 Initial value: — — — — — — — 0 PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PP Bus-R/W: Bit: CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PP Bus-R/W: Bit: CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 REVID7 REVID6 REVID5 REVID4 REVID3 REVID2 REVID1 REVID0 Initial value: * * * * * * * * PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R PP Bus-R/W: Bit: *: Initial values vary with the logic versions of the chip. The PCI configuration register 2 (PCICONF2) is a 32-bit read/partial-write register that includes the class code and revision ID PCI configuration registers stipulated in the PCI local bus Rev. 3.0, 04/02, page 817 of 1064 specifications. Bits 31 to 8 (class code) set the device functions. The chip logic version can be read from bits 7 to 0 (revision ID). Bits 31 to 8 can be written to from the PP bus. Bits 7 to 0 are fixed in hardware. The PCICONF2 register class codes are not initialized at a reset. They must be initialized while CFINIT (bit 0) of the PCI control registers (PCICR) is cleared. Bits 31 to 24—Base Class Code (CLASS23 to 16): These bits indicate the base class code. For details of setting values, refer to table 22.5. Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16) CLASS23 to 16 Base Class Meaning H'00 Device designed prior to class code being defined H'01 High-capacity storage controller H'02 Network controller H'03 Display controller H'04 Multimedia device H'05 Memory controller H'06 Bridge device H'07 Simple communication device H'08 Basic peripheral device H'09 Input device H'0A Docking station H'0B Processor H'0C Serial bus controller H'0D to H'FE Reserved H'FF Device not categorized in defined class Bits 23 to 16—Sub Class Codes (CLASS15 to 8): For details, please see Appendix D, Pin Functions of the PCI Local Bus Specifications, Revision 2.1. Bits 15 to 8—Register Level Programming Interface (CLASS7 to 0): For details, please see Appendix D, Pin Functions of the PCI Local Bus Specifications, Revision 2.1. Bits 7 to 0—Revision ID (REVID7 to 0): Shows the PCIC revision. The initial value differs according to the logic version of the chip. Rev. 3.0, 04/02, page 818 of 1064 22.2.4 PCI Configuration Register 3 (PCICONF3) Bit: 31 30 29 28 27 26 25 24 BIST7 BIST6 BIST5 BIST4 BIST3 BIST2 BIST1 BIST0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 HEAD7 HEAD6 HEAD5 HEAD4 HEAD3 HEAD2 HEAD1 HEAD0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 LAT7 LAT6 LAT5 LAT4 LAT3 LAT2 LAT1 LAT0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial value: Bit: CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 3 (PCICONF3) is a 32-bit read/partial-write register that includes the BIST function, header type, latency timer, and cache line size PCI configuration registers stipulated in the PCI local bus specification. The BIST function is read from bits 31 to 24, the header type from bits 23 to 16, the cache line size from bits 7 to 0. The guaranteed time for the PCIC to occupy the PCI bus when the PCIC is master is set in bits 15-8 (latency timer). Bits 15 to 8 can be written to. Other bits are fixed in hardware. The PCICONF3 register is initialized to H'00000000 at a power-on reset and software reset. Rev. 3.0, 04/02, page 819 of 1064 Bit 31—BIST7: BIST function support Bit 31: BIST7 Description 0 Function not supported 1 Function supported (not supported) (Initial value) Bit 30—BIST6: Used to control the BIST starting. Bit 30: BIST6 Description 0 Execution completed 1 Executing (not supported) (Initial value) Bits 29 and 28—BIST5 and 4: These bits always return 0 when read. Bits 27 to 24—BIST3 to 0: BIST status on completion of operation. Bits 27 to 24: BIST3 to 0 Description H'0 Passed test H'1 to H'F Test failed (not supported) (Initial value) Bit 23—Multifunction Status (HEAD7): Shows whether the device is a multi-function unit or a single-function unit. Bit 23: HEAD7 Description 0 Single-function device 1 Device has between 2 and 8 functions (not supported) (Initial value) Bits 22 to 16—Configuration Layout Type (HEAD6 to 0): These bits indicate the layout type of the configuration register. Bits 22 to 16: HEAD6 to 0 Description H'00 Type 00h layout supported H'01 Type 01h layout supported (not supported) H'02 to H'3F Reserved (Initial value) Bits 15 to 8—Latency Timer Register (LAT7 to 0): These bits specify the latency time of the PCI bus when the PCIC is operating as the master. Rev. 3.0, 04/02, page 820 of 1064 Bits 7 to 0—Cache Line Size (CACHE7 to 0): Not supported. Memory target is set cachedisabled, and SDONE and 
are ignored. 22.2.5 PCI Configuration Register 4 (PCICONF4) Bit: 31 30 29 28 27 26 25 24 BASE31 BASE30 BASE29 BASE28 BASE27 BASE26 BASE25 BASE24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W* R/W* R/W* R/W* PP Bus-R/W: R/W R/W R/W R/W R/W* R/W* R/W* R/W* 15 14 13 12 11 10 9 8 BASE9 BASE8 Bit: BASE15 BASE14 BASE13 BASE12 BASE11 BASE10 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* PP Bus-R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit: 7 6 5 4 3 2 1 0 BASE7 BASE6 BASE5 BASE4 BASE3 BASE2 — ASI Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Note: * These bits are read-only in the SH7751 and can be read from and written to in the SH7751R. PCI configuration register 4 (PCICONF4) is a 32-bit read/partial-write register that accommodates the I/O-space base address register, which is one of the PCI configuration registers that are stipulated in the PCI’s local-bus specifications. PCICONF4 holds the higher-order bits of the address used when a device on the PCI bus uses I/O transfer commands to access a local register in the PCIC. Rev. 3.0, 04/02, page 821 of 1064 In the SH7751, the 12 higher-order bits (bits 31 to 8) are set; in the SH7751R, the 24 higher-order bits are set. As the I/O space for the PCI bus, allocate 1 Mbyte of space for the SH7751 and 256 bytes of space for the SH7751R. In the SH7751, bits 30 to 20 are writable, and bits 19 to 2 and 0 are fixed by the hardware. In the SH7751R, bits 31 to 8 are writable, and bits 7 to 2 and 0 are fixed by the hardware. The PCICONF4 register is initialized to H'00000001 at a power-on reset and software reset. Always write to this register prior to executing I/O transfers (accessing the local registers in the PCIC) to or from the PCIC from the PCI bus. Bits 31 to 8—Base Address of the I/O Space (BASE 31 to 8): Sets the base address of the local registers (I/O space) in the PCIC. In the SH7751, bits 19 to 8 are fixed to H'000 in hardware. Bits 7 to 2—Base Address of the I/O Space (BASE 7 to 2): Fixed at H'00 in hardware. Bit 1—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 0—Address Space Indicator (ASI): Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: ASI Description 0 Memory space 1 I/O space Rev. 3.0, 04/02, page 822 of 1064 (Initial value) 22.2.6 PCI Configuration Register 5 (PCICONF5) Bit: 31 30 29 28 27 26 25 24 BASE031 BASE030 BASE029 BASE028 BASE027 BASE026 BASE025 BASE024 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE023 BASE022 BASE021 BASE020 BASE019 BASE018 BASE017 BASE016 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R R R R PP Bus-R/W: R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 Bit: BASE015 BASE014 BASE013 BASE012 BASE011 BASE010 BASE09 BASE08 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 BASE07 BASE06 BASE05 BASE04 LA0PREF LA0TYPE1 LA0TYPE0 LA0ASI Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 5 (PCICONF5) is a 32-bit read/partial-write register that accommodates the memory space base address PCI configuration register stipulated in the PCI local bus specifications. This register holds the high bits (12 max. in bits 31 to 20) of the address used when a device on the PCI bus accesses local memory on the SH local bus using memory transfer commands. Allocate at least the capacity set in the local space register 0 (PCILSR0) as PCI bus memory space. Bits 19 to 0 are fixed in hardware. Of writable bits 31 to 20, those that hold valid values differ according to the value set in PCILSR0. Rev. 3.0, 04/02, page 823 of 1064 Table 22.6 Memory Space Base Address Register (BASE0) PCILSR0 [28:20] Register Value Required Address Space BASE0[31:20] Valid Writable Bits b'0_0000_0000 1 MB Bits 31 to 20 b'0_0000_0001 2 MB Bits 31 to 21 b'0_0000_0011 4 MB Bits 31 to 22 : : : b'0_1111_1111 256 MB Bits 31 to 28 b'1_1111_1111 512 MB Bits 31 to 29 The PCICONF5 register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register before transferring data to and from the PCIC memory from the PCI bus. Bits 31 to 20—Base Address of the Memory Space 0 (BASE0 31 to 20): These bits specify the base address of the local address space 0 (SH7751 Series external bus space). Bits 19 to 4—Base Address of the Memory Space 0 (BASE0 19 to 4): Fixed at H'0000 in hardware. Bit 3—Pre-fetch Control (LA0PREF): Shows availability of prefetching of the local address space 0. Bit 3: LA0PREF Description 0 Prefetch disabled 1 Prefetch enabled (not supported) (Initial value) Bits 2 and 1—LA0TYPE1 and 0: In the case of I/O space, can be set as the base address. Shows the memory type of the local address space 0. Bit 2: LA0TYPE1 Bit 1: LA0TYPE0 Description 0 0 Base address can be set to 32-bit width, 32-bit space (Initial value) 1 Base address can be set to 32-bit width, less than 1MB space (not supported) 0 Base address is 64-bit width (not supported) 1 Reserved 1 Rev. 3.0, 04/02, page 824 of 1064 Bit 0—LA0ASI: Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: LA0ASI Description 0 Memory space 1 I/O space 22.2.7 (Initial value) PCI Configuration Register 6 (PCICONF6) Bit: 31 30 29 28 27 26 25 24 BASE131 BASE130 BASE129 BASE128 BASE127 BASE126 BASE125 BASE124 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: BASE123 BASE122 BASE121 BASE120 BASE119 BASE118 BASE117 BASE116 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R R R R PP Bus-R/W: R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 Bit: BASE115 BASE114 BASE113 BASE112 BASE111 BASE110 BASE19 BASE18 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 BASE17 BASE16 BASE15 BASE14 LA1PREF LA1TYPE1 LA1TYPE0 LA1ASI Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 6 (PCICONF6) is a 32-bit read/partial-write register that accommodates the memory space base address PCI configuration register stipulated in the PCI local bus specifications. This register contains the most significant bits (maximum 12 in bits 31 to 20) of the address used when a device on the PCI bus accesses local memory on the SH local bus Rev. 3.0, 04/02, page 825 of 1064 using memory transfer commands. Minimally, allocate the capacity set in the local space register 1 (PCILSR1) to PCI bus memory space. Bits 19 to 0 are fixed in hardware. The number of valid bits of those that can be written to (bit 31 to 20) differs according to the value set in PCILSR1. Table 22.7 Memory Space Base Address Register (BASE1) PCILSR1 [28:20] Register Value Required Address Space Valid BASE1 [31:20] Write Bits b'0_0000_0000 1 MB Bits 31 to 20 b'0_0000_0001 2 MB Bits 31 to 21 b'0_0000_0011 4 MB Bits 31 to 22 : : : b'0_1111_1111 256 MB Bits 31 to 28 b'1_1111_1111 512 MB Bits 31 to 29 The PCICONF6 register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register prior to transferring data to or from the PCIC memory from the PCI bus. Bits 31 to 20—Base Address of the Memory Space 1 (BASE1 31 to 20): Specifies the base address of the local address space 1 (SH7751 Series external bus space). Bits 19 to 4—Base Address of the Memory Space 1 (BASE1 19 to 4): Fixed at H'0000 in hardware. Bit 3—Pre-fetch Control (LA1PREF): Shows whether the local address space 1 can be prefetched. Bit 3: LA1PREF Description 0 Prefetch disabled 1 Prefetch enabled (not supported) Rev. 3.0, 04/02, page 826 of 1064 (Initial value) Bits 2 and 1—Memory Type (LA1TYPE1 to 0): These bits indicate the memory type of the local address space 1. Bit 2: LA1TYPE1 Bit 1: LA1TYPE0 Description 0 0 The base address can be set to 32-bit width, 32-bit space (Initial value) 1 The base address can be set to 32-bit width, but less than 1MB (not supported) 0 The base address has 64-bit width (not supported) 1 Reserved 1 Bit 0—Address Space Indicator (LA1ASI): Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: LA1ASI Description 0 Memory space 1 I/O space 22.2.8 (Initial value) PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. Rev. 3.0, 04/02, page 827 of 1064 22.2.9 PCI Configuration Register 11 (PCICONF11) Bit: Initial value: PCI-R/W: PP Bus-R/W: Bit: 31 30 29 28 27 26 25 24 SSID15 SSID14 SSID13 SSID12 SSID11 SSID10 SSID9 SSID8 — — — — — — — — R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 SSID7 SSID6 SSID5 SSID4 SSID3 SSID2 SSID1 SSID0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 SVID15 SVID14 SVID13 SVID12 SVID11 SVID10 SVID9 SVID8 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: Bit: PP Bus-R/W: Bit: PP Bus-R/W: The PCI configuration register 11 (PCICONF11) is a 32-bit read/write register that accommodates the subsystem ID and subsystem vendor ID PCI configuration registers stipulated in the PCI local bus specifications. The register contains the ID of the add-in board that SH7751 Series is installed on its subsystem (bits 31 to 16) as well as the subsystem vendor ID (bits 15 to 0). All bits can be written to from the PP bus. The PCICONF11 register is not initialized at a reset. Always initialize this register while the CFINIT bit (bit 0) of the PCICR register is cleared. Bits 31 to 16—SSID15 to 0: Specifies the subsystem ID. Bits 15 to 0—SVID15 to 0: Specifies the PCI subsystem vendor ID. Rev. 3.0, 04/02, page 828 of 1064 22.2.10 PCI Configuration Register 12 (PCICONF12) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. Rev. 3.0, 04/02, page 829 of 1064 22.2.11 PCI Configuration Register 13 (PCICONF13) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 CAPPTR7 CAPPTR6 CAPPTR5 CAPPTR4 CAPPTR3 CAPPTR2 CAPPTR1 CAPPTR0 Initial value: 0 1 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 13 (PCICONF13) is a 32-bit read-only register that accommodates the extended function pointer PCI configuration register stipulated in the PCI power management specifications. The address offset of the extended function is read from bits 7 to 0. All bits are fixed in hardware. Bits 31 to 8—Reserved: These bits are always read as 0. Bits 7 to 0—CAPPTR: These bits specify the address offset of the extended functions (power management). The initial value is H'40 (fixed). Rev. 3.0, 04/02, page 830 of 1064 22.2.12 PCI Configuration Register 14 (PCICONF14) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bits 31 to 0—Reserved: These bits are always read as 0. Rev. 3.0, 04/02, page 831 of 1064 22.2.13 PCI Configuration Register 15 (PCICONF15) Bit: 31 30 29 28 27 26 25 24 MLAT7 MLAT6 MLAT5 MLAT4 MLAT3 MLAT2 MLAT1 MLAT0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 MGNT7 MGNT6 MGNT5 MGNT4 MGNT3 MGNT2 MGNT1 MGNT0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 IPIN7 IPIN6 IPIN5 IPIN4 IPIN3 IPIN2 IPIN1 IPIN0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ILIN7 ILIN6 ILIN5 ILIN4 ILIN3 ILIN2 ILIN1 ILIN0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W The PCI configuration register 15 (PCICONF15) is a 32-bit read/partial-write register that accommodates the maximum latency, minimum grant, interrupt pin, and interrupt line PCI configuration registers stipulated in the PCI local bus specifications. The interrupt pins used by the SH7751/SH7751R are read from bits 15 to 8. Bits 7 to 0 indicate to which of the interrupt request signal lines of an interrupt controller the interrupt line is connected. Bits 31 to 8 are fixed in hardware. Bits 7 to 0 can be written to from both the PP bus and PCI bus. The PCICONF15 register is initialized to H'00000100 at a power-on reset and software reset. Bits 31 to 24—Designation of Maximum Latency (MLAT7 to 0): These bits specify the maximum time from the time the PCI master device demands bus privileges and to the time it obtains the privileges (not supported). Rev. 3.0, 04/02, page 832 of 1064 Bits 23 to 16—Minimum Latency Specification (MGNT 7 to 0): Specify the burst interval required by the PCI device (not supported). Bits 15 to 8—Interrupt Pin Specification (IPIN7 to 0) Bits 15 to 8: IPIN7 to 0 Description H'04  used  used  used  used H'05 to H'FF Reserved bits H'01 H'02 H'03 (Initial value) Bits 7 to 0—Interrupt Line Specification (ILIN7 to 0): Specifies an interrupt line of a system to which interrupt output used by the PCIC is connected. Rev. 3.0, 04/02, page 833 of 1064 22.2.14 PCI Configuration Register 16 (PCICONF16) Bit: 31 30 29 28 27 PMESPT4 PMESPT3 PMESPT2 PMESPT1 PMESPT0 26 25 24 D2SPT D1SPT — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — DS1 — PMECLK VER2 VER1 VER0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 NIP0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CAPID7 CAPID6 CAPID5 CAPID4 CAPID3 CAPID2 CAPID1 CAPID0 Initial value: 0 0 0 0 0 0 0 1 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI configuration register 16 (PCICONF16) is a 32-bit read/partial-write register than accommodates the power management function (PMC), next-item pointer, and extended function ID power management registers stipulated in the PCI power management specifications. PCICONF16 is valid only when the PCIC is functioning not as the host. The power management related functions are read from bits 31 to 16 (PMC), the address offset of the next function in the extended function list is read from bits 15 to 8 (next item pointer), and the power management ID (H'01) is read from bits 7 to 0 (extended function ID). Bits 18 to 16 can be written to from the PP bus only. Other bits are fixed in hardware. The PCICONF16 regsiter is initialized to H'00010001 at a power-on reset and a software reset. Rev. 3.0, 04/02, page 834 of 1064 Bits 31 to 27—PME Support (PMESPT4 to 0): Not supported. Defines the function state supporting   output. Bit 26—D2 Support (D2SPT): Not supported. Specifies whether D2 state is supported. Bit 25—D1 Support (D1SPT): Not supported. Specifies whether D1 state is supported. Bits 24 to 22—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 21—DSI: Specifies whether bit-device-specific initialization is required. Bit 20—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 19—PME Clock (PMECLK): Not supported. Specifies whether a clock is required for   support. Bits 18 to 16—Version (VER2 to 0): Specify the version of power management specifications. Bits 15 to 8—Next Item Pointer (NIP7 to 0): Specify the offset to the next extended function register Bits 7 to 0—Extended Function ID (CAPID7 to 0): Extended function (Capability Identifier) ID. These bits always return H'01 when read. Rev. 3.0, 04/02, page 835 of 1064 22.2.15 PCI Configuration Register 17 (PCICONF17) Bit: 31 30 29 28 27 26 25 24 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 PMEST DTATSCL1 DTATSCL0 DATASEL3 DATASEL2 DATASEL1 DATASEL0 PMEEN Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — PWRST1 PWRST0 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W The PCI configuration register 17 (PCICONF17) is a 32-bit read/partial-write register that accommodates the power management control/status (PMCSR), bridge-compatible PMCSR extended (PMCSR_BSE), and data power management registers stipulated in the PCI power management specifications. PCICONF17 is valid only when the PCIC is operating not as the host. Bits 31 to 24 (data) and bits 23 to 16 (PMCSR_BSE) are not supported. The power management status is read from bits 15 to 0 (PMCSR). Bits 1 and 0 can be written to from both the PP bus and the PCI bus. Other bits are fixed in hardware. PCICONF17 is initialized to H'00000000 at a power-on reset and software reset. Rev. 3.0, 04/02, page 836 of 1064 When B'11 is written to bits 1 and 0 and a transition is made to power state D3 (power down mode), PCIC operation as a master target is disabled, regardless of the setting of bits 2 to 0 of the PCICONF1 (bus master control, memory and I/O space access control) (these bits are masked). When B'00 is written to bits 1 and 0 and a transition is made to power state D0 (normal operating mode), the mask is canceled. Bits 31 to 24—DATA (DATA7 to 0): Not supported. Data field for power management. Bits 23 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—PME Status (PMEST): Not supported. Shows the status of the   bit. This bit is set when the signal is output. Bits 14 and 13—Data Scale (DTATSCL1 to 0): Not supported. These bits specify the scaling value for the data field value. Bits 12 to 9—Data Select (DATASEL3 to 0): Not supported. Select the value to be output to the data field. Bit 8—  Enable (PMEEN): Not supported. Controls the   signal output. Bits 7 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 1 and 0—Power State (PWRST1 and 0): Specifies the power state. No state transition is effected when a non-supported state is specified. (Normal termination, no error output.) Bit 1: PWRST1 Bit 0: PWRST0 Description 0 0 D0 state (Initial value, normal state) 1 D1 state (not supported) 0 D2 state (not supported) 1 D3 state (power down mode) 1 Rev. 3.0, 04/02, page 837 of 1064 22.2.16 Reserved Area Reserved area. Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Note: PCI configuration addresses H'48 to H'FC are reserved. Bits 31 to 0—Reserved: These bits always return 0 when read. Rev. 3.0, 04/02, page 838 of 1064 22.2.17 PCI Control Register (PCICR) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — TRDSGL BYTESWAP Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 PCIPUP BMABT MD10 MD9 SERR INTA RSTCTL CFINIT Initial value: 0 0 0/1* 0/1* 0 0 0 0 PCI-R/W: R R R R R R R R R/W R/W R R R/W R/W R/W R/W PP Bus-R/W: Note: * The value of the external pin is sampled in a power-on reset by means of the
 pin. The PCI control register (PCICR) is a 32-bit register that monitors the status of the mode pin at initialization and controls the basic operation of the PCIC. Bits 5 (MD10) and 4 (MD9) are readonly bits from the PP bus. Other bits are read/write bits. Bits 9 (TRDSGL) and 8 (BYTESWAP) are read/write bits from the PCI bus. Other bits are read-only. In PCIC host operation, a software reset can be applied to the PCI bus by means of bit 1 (RSTCTL) of PCICR. When a software reset is executed, the  pin is asserted and the internal state of the PCIC is initialized. The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1 (RSTCTL) is not initialized. All other bits are initialized in the same way as at a software reset. Rev. 3.0, 04/02, page 839 of 1064 This register can be written to only when bits 31 to 24 are H'A5. Always set bit 0 (CFINIT) to 1 on completion of PCIC register initialization. Bits 31 to 10—Reserved: These bits are always read as 0. When writing, write H'A5 to bits 31 to 24, and 0 to others. Bit 9—Target Read Single Buffer (TRDSGL): This bit specifies whether one target read buffer (32 bytes) or two target read buffers (64 bytes) are used for target memory read access to the PCIC. When two target read buffers faces are used, the data from two buffers are read via the local bus in advanced. Bit 9: TRDSGL Description 0 Use 2 target read buffers 1 Use 1 target read buffer only (Initial value) Bit 8—Data Byte Swap (BYTESWAP): Specifies whether the data byte is swapped when the PCIC performs PIO transfer. Bit 8: BYTESWAP Description 0 Send data as-is 1 Swap data byte before sending (Initial value) Note: For details, refer to section 22.4, Endians. Bit 7—PCI Signal Pull-up (PCIUP): Controls the pull-up resistance of the PCI signal. Regarding the pins that are subject to pull-up, refer to Table 22.1. Regarding the pull-up control provided when the /MD9, /MD10 or  is used as a port, refer to the section on port control register (PCIPCTR). Bit 7: PCIUP Description 0 Pull-up 1 No pull-up (Initial value) Bit 6—Bus Master Arbitration (BMABT): Controls the PCI bus arbitration mode of the PCIC when the PCIC is operating as the host. When the PCIC is non-host, the value of this bit is ignored. Bit 6: BMABT Description 0 Fixed priority order (device 0 (PCIC) > device 1 > device 2 > device 3 > device 4) (Initial value) 1 Pseudo round-ribbon (The priority level of the device with bus privileges is set lowest at the next access.) Rev. 3.0, 04/02, page 840 of 1064 Bit 5—Mode 10 Pin Monitor (MD10): Monitors the /MD10 pin value in a power-on reset by means of the  pin. Bit 5: MD10 Description 0 Host bridge function (arbitration) enabled 1 Host bridge function disabled Bit 4—Mode 9 Pin Monitor (MD9): Monitors the /MD9 pin value in a power-on reset by means of the  pin. Bit 4: MD9 Description 0 PCICLK used as PCI clock 1 Feedback input clock from CKIO used as PCI clock Bit 3— Output (SERR): Software control of  output. This bit is valid only when bit 8 (SER) of the PCICONFI register is “1”. When “1” is written to this bit,  is asserted for 1 clock. This bit always returns “0” when read. Used when the PCIC is not the host. If used when the PCIC is the host, an  assert interrupt is generated for the SH7751 Series. Bit 3: SERR 0 1 Description 

pin at Hi-Z Assert 

(Low output) (Initial value) Bit 2—     Output (INTA): Software control of   (valid only when PCIC is not host) Bit 2: INTA 0 1 Description  pin at Hi-Z (driven to High by pull-up resistor) Assert  (Low output) (Initial value) Bit 1—PCIRST Output Control (RSTCTL): Controls the  output. ORed with a poweron reset before output. This field is reset only at a power-on reset. Do not use the field when the PCIC is non-host. Bit 1: PCIRST Description 0 Negate  
 (High output) 1 (Initial value) Assert  
 (Low output) Rev. 3.0, 04/02, page 841 of 1064 Bit 0—PCIC Internal Register Initialization Control Bit (CFINIT): After the SH initializes the PCI registers, setting this bit enables access from the PCI bus. During initialization, no bus privileges are granted to other devices on the PCI bus while operating as the host. When operating not as the host, a retry is returned without the access from the PCI bus being accepted. Bit 0: CFINIT Description 0 Initialization busy 1 Initialization complete (Initial value) 22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0]) Bit: 31 30 29 — — — 28 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 — — — — 0 0 0 0 0 PLSR23 PLSR22 PLSR21 PLSR20 Initial value: PCI-R/W: PP Bus-R/W: Bit: 0 0 0 27 26 25 24 PLSR28 PLSR27 PLSR26 PLSR25 PLSR24 R R R R R R R R R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI local space register [1:0] (PCILSR [1:0]) specifies the capacities of the two local address spaces (address space 0 and address space 1) supported when a device on the PCI bus performs a Rev. 3.0, 04/02, page 842 of 1064 memory read/memory write of the PCIC using target transfers. This is a 32-bit register that can be read and written from the PP bus, or read only from the PCI bus. The PCILSR [1:0] register is initialized to H'00000000 at a power-on reset and software reset. Always write to this register before performing target transfers to specify the capacity of the address space being used. Specify the value “(capacity –1) bytes” in bits 28 to 20. For example, to secure a 32MB space, set the value H'01F00000. If you specify all zeros, a 1MB space is reserved. You can specify an address space up to 512MB. Refer to Table 22.6 in section 22.2.6, PCI Configuration Register 5 (PCICONF5). Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bits 28 to 20—Capacities of the Local Address Spaces 0, 1 (PLSR28 to 20): These bits specify the capacities of the address space 0 and address space 1 in bytes. Specifying (capacity –1) bytes. A 1MB space is secured if all zeros are specified. Bits 19 to 0—Reserved: These bits always return 0 when read. Always write 0 to these bits. Rev. 3.0, 04/02, page 843 of 1064 22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0]) Bit: 31 30 29 28 27 26 25 24 — — — LAR28 LAR27 LAR26 LAR25 LAR24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 LAR23 LAR22 LAR21 LAR20 — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R R/W R/W R/W R/W R R R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — — PP Bus-R/W: Bit: Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI local address register [1:0] (PCILAR [1:0]) specifies the starting address (external address of local bus) of the two local address spaces (address space 0 and address space 1) supported when performing memory read/memory write operations due to target transfers to the PCIC. It is a 32-bit register that can be read and written from the PP bus and is read-only from the PCI bus. The PCILAR [1:0] register is initialized to H'00000000 at a power-on reset and software reset. The valid bits of the local address specified by this register vary according to the capacity of the address space specified in the PCILSR [1:0] register. In other words, set 0 in the least significant address bit which corresponds to the capacity set by PCILSR0, 1, and set the starting address only in the most significant address bit. For example, when the capacity of the local address space is set to 32MB (PCILSR: H'01F00000), bits 28 to 25 of the local address are valid. Only the value set in these bits is used as the physical address of the local address space. Rev. 3.0, 04/02, page 844 of 1064 Always write to this register prior to target transfers. Specify the starting address (physical address) of the memory installed on the local bus according to the address space being used. Bits 28 to 26 of the PCI local address register 0 select the local address area. Bits 25 to 20 show the address within that area. Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 28 to 20—Local Address (LAR28 to 20): Specify bits 28 to 20 of the starting address of the local address space. Bits 19 to 0—Reserved: These bits always return 0 when read. Always write 0 to these bits. Rev. 3.0, 04/02, page 845 of 1064 22.2.20 PCI Interrupt Register (PCIINT) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — M_LOCK T_TGT_A ON BORT Initial value: TGT_RET MST_DIS RY 0 0 0 0 0 0 0 0 PCI-R/W: R/WC R/WC R R R R R/WC R/WC PP Bus-R/W: R/WC R/WC R R R R R/WC R/WC 7 6 5 4 3 2 1 0 Bit: ADRPER SERR_D T_DPER T_PERR_ M_TGT_A M_MST_ M_DPER M_DPER R ET R_WT DET BORT ABORT R_WT R_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC PP Bus-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC Note: WC: Cleared by writing “1”. (Writing of 0 is ignored.) The PCI interrupt register (PCIINT) is a 32-bit register that saves the error source when an error occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus, or when the PCIC is the PCI master or PCI target. This register can be read from both the PP bus and PCI bus. Also, 1 can be written from either the PP bus or PCI bus to perform a write-clear in which the detection bit is cleared to its initial value (0). The PCIINT register is initialized to H'00000000 at a power-on reset or software reset. When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) Rev. 3.0, 04/02, page 846 of 1064 Note that the error detection bits can be set even when the interrupt is masked. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—Unlocked Transfer Detection Interrupt (M_LOCKON): When the PCIC is master, an unlocked PIO transfer was performed when the I-specified target was locked. Bit 14—Target Target Abort Interrupt (T_TGT_ABORT): Indicates the termination of transaction by target abort when the PCIC is a target. Target abort is generated when the 2 least significant address bits (bits 1, 0) and byte enable constitute an illegal combination (illegal byte enable) during I/O transfer. Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—Target Memory Read Retry Timeout Interrupt (TGT_RETRY): When the PCIC is 15 target, the master did not attempt a retry within the prescribed number of PCI bus clocks (2 ) (detected only in the case of memory read operations). Bit 8—Master Function Disable Error Interrupt (MST_DIS): Indicates that an attempt was made to conduct a master operation (PIO transfer, DMA transfer) when bit 2 (BUM) of the PCICONF1 was set to 0 to prohibit bus master operations. Bit 7—Address Parity Error Detection Interrupt (ADRPERR): Address parity error detected. Detects only when bit 6 (PER) and bit 8 (SER) of the PCICONF1 are both 1. Bit 6— Detection Interrupt (SERR_DET): When the PCIC is host, assertion of the  signal was detected. Bit 5—Target Write Data Parity Error Interrupt (T_DPERR_WT): When the PCIC is target, a data parity error was detected while receiving a target write transfer (only detected when PCICONFI bit 6 (PER) is 1). Bit 4—Target Read   Detection Interrupt (T_PERR_DET): When the PCIC is target,  was detected when receiving a target read transfer. Detects only when bit 6 (SER) of the PCICONF1 is 1. Bit 3—Master Target Abort Interrupt (M_TGT_ABORT): When the PCIC is master. Indicates the termination of transaction by target abort. Bit 2—Master Master Abort Interrupt (M_MST_ABORT): When the PCIC is master. Indicates the termination of transaction by master abort. Rev. 3.0, 04/02, page 847 of 1064 Bit 1—Master Write   Detection Interrupt (M_DPERR_WT): When the PCIC is master.  received from the target while writing data to the target. Detects only when bit 6 (PER) of the PCICONF1 is 1. Bit 0—Master Read Data Parity Error Interrupt (M_DPERR_RD): When the PCIC is master, a parity error was detected during a data read from the target. Detects only when bit 6 (PER) of the PCICONF1 is 1. 22.2.21 PCI Interrupt Mask Register (PCIINTM) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — M_LOCK T_TGT_A ON BORT Initial value: TGT_RET MST_DIS RY 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R R R R R/W R/W PP Bus-R/W: R/W R/W R R R R R/W R/W 7 6 5 4 3 2 1 0 Bit: ADRPER SERR_D T_DPER T_PERR_ M_TGT_A M_MST_ M_DPER M_DPER R ET R_WT DET BORT ABORT R_WT R_RD Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W The PCI interrupt mask register (PCIINTM) sets the respective interrupt masks for the interrupts generated when errors occur in PCI transfers. It is a 32-bit read/write register that can be accessed Rev. 3.0, 04/02, page 848 of 1064 from both the PP bus and PCI bus. When set to 0, the respective interrupt is disabled, and enabled when set to 1. The PCIINTM register is initialized to H'00000000 at a power-on reset and software reset. Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—Unlocked Transfer Detection Interrupt Mask (M_LOCKON) Bit 14—Target Target Abort Interrupt Mask (T_TGT_ABORT) Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 9—Target Retry Timeout Interrupt Mask (TGT_RETRY) Bit 8—Master Function Disable Error Interrupt Mask (MST_DIS) Bit 7—Address Parity Error Detection Interrupt Mask (ADRPERR) Bit 6— Detection Interrupt Mask (SERR_DET) Bit 5—Target Write Data Parity Error Interrupt Mask (T_DPERR_WT) Bit 4—Target Read   Detection Interrupt Mask (T_PERR_DET) Bit 3—Master Target Abort Interrupt Mask (M_TGT_ABORT) Bit 2—Master Master Abort Interrupt Mask (M_MST_ABORT) Bit 1—Master Write Data Parity Error Interrupt Mask (M_DPERR_WT) Bit 0—Master Read Data Parity Error Interrupt Mask (M_DPERR_RD) Rev. 3.0, 04/02, page 849 of 1064 22.2.22 PCI Address Data Register at Error (PCIALR) Bit: 31 30 29 28 27 26 25 24 ALOG31 ALOG30 ALOG29 ALOG28 ALOG27 ALOG26 ALOG25 ALOG24 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 ALOG23 ALOG22 ALOG21 ALOG20 ALOG19 ALOG18 ALOG17 ALOG16 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 ALOG9 ALOG8 ALOG15 ALOG14 ALOG13 ALOG12 ALOG11 ALOG10 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ALOG7 ALOG6 ALOG5 ALOG4 ALOG3 ALOG2 ALOG1 ALOG0 Initial value: — — — — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI address data register at error (PCIALR) stores the PCI address data (ALOG [31:0]) of errors that occur on the PCI bus. It is a 32-bit register that can be read from both the PP bus and PCI bus. The PCIALR register is not initialized at a power-on reset or software reset. The initial value is undefined. A valid value is retained only when one of the PCIINT register bits is set to 1. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error. (Initial value is undefined.) Rev. 3.0, 04/02, page 850 of 1064 22.2.23 PCI Command Data Register at Error (PCICLR) Bit: 31 30 29 28 27 MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3 26 25 24 TGT — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0 Initial value: 0 0 0 0 — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI command data register at error (PCICLR) stores the type of transfer (MSTPIO, MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, or TGT) when an error occurs on the PCI bus, and the PCI command (CMDLOG [3:0]). It is a 32-bit register that can be read from both the PP bus and PCI bus. Although bits 31 to 26 of the PCICLR register are initialized at a power-on reset and a software reset, bits 3 through 0 are not initialized. When an error is detected, 1 is set in one of bits 31 to 26, and the relevant command value is retained in bits 3 to 0. A valid value is retained only when one of the PCIINT register bits is set to 1. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively. Rev. 3.0, 04/02, page 851 of 1064 Bit 31—PIO Error (MSTPIO): Error occurred in PIO transfer. Bit 30—DMA0 Error (MSTDMA0): Error occurred in DMA channel 0 transfer. Bit 29—DMA1 Error (MSTDMA1): Error occurred in DMA channel 1 transfer. Bit 28—DMA2 Error (MSTDMA2): Error occurred in DMA channel 2 transfer. Bit 27—DMA3 Error (MSTDMA3): Error occurred in DMA channel 3 transfer. Bit 26—Target Error (TGT): Error occurred in target read or target write transfer. Bits 25 to 4—Reserved: These bits are always read as 0. Bits 3 to 0—Command Log (CMDLOG3 to 0): These bits retain the PCI transfer command information (value of C/
 line) upon detection of an error. (Initial value is undefined.) Rev. 3.0, 04/02, page 852 of 1064 22.2.24 PCI Arbiter Interrupt Register (PCIAINT) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — MST_BRKN — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R/WC R/WC R/WC R R R PP Bus-R/W: R R R/WC R/WC R/WC R R R Bit: 7 6 5 4 3 2 1 0 — — — — DPERR_WT DPERR_RD TGT_BUSTO MST_BUSTO TGT_ABORT MST_ABORT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R/WC R/WC R/WC R/WC PP Bus-R/W: R R R R R/WC R/WC R/WC R/WC Note: Cleared by writing WC:1. (Writing of 0 is ignored.) The PCI arbiter interrupt register (PCIAINT) is a 32-bit register that stores the sources of PCI bus errors occurring during transfers by another PCI master device when the PCIC is operating as the host with the arbitration function. The register can be read from both the PP bus and the PCI bus. Also, each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it from either the PP bus or the PCI bus. (Write clear) The PCIINT register is initialized to H'00000000 at a power-on reset or software reset. When an error is detected, the bit corresponding to the error type is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) The error detection bits are set even when the interrupts are masked. Rev. 3.0, 04/02, page 853 of 1064 Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 13—Master Broken Interrupt (MST_BRKN): Detects when the master granted with bus privileges does not start a transaction (  not asserted) within 16 clocks. Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither  nor   are not returned within 16 clocks in the case of the first data transfer, or within 8 clocks in the case of second and subsequent data transfers. Bit 11—Master Bus Timeout Interrupt (MST_BUSTO):  is not returned within 8 clocks. Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 3—Target Abort Interrupt (TGT_ABORT): Indicates the termination of transaction by target abort when a device other than the PCIC is operating as the bus master. Bit 2—Master Abort Interrupt (MST_ABORT): Indicates the termination of transaction by master abort when a device other than the PCIC is operating as the bus master. Bit 1—Read Data Parity Error Interrupt (DPERR_WT): Indicates the detection of the assertion of  in a data read operation when a device other than the PCIC is operating as the bus master. Bit 0—Write Data Parity Error Interrupt (DPERR_RD): Indicates the detection of the assertion of  in a data write operation when a device other than the PCIC is operating as the bus master. Rev. 3.0, 04/02, page 854 of 1064 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — MST_BRKN — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R/W R/W R/W R R R PP Bus-R/W: R R R/W R/W R/W R R R Bit: 7 6 5 4 3 2 1 0 — — — — DPERR_WT DPERR_RD TGT_BUSTO MST_BUSTO TGT_ABORT MST_ABORT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R/W R/W R/W R/W PP Bus-R/W: R R R R R/W R/W R/W R/W The PCI arbiter interrupt mask register (PCIAINTM) sets interrupt masks for the individual interrupts that occur due to errors generated during PCI transfers performed by other PCI devices when the PCIC is operating as the host with the arbitration function. Each bit is set to 0 to disable the respective interrupt, or 1 to enable that interrupt. The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset. Bits 31 to 14—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 13—Master Broken Interrupt Mask (MST_BRKN) Bit 12—Target Bus Timeout Interrupt Mask (TGT_BUSTO) Rev. 3.0, 04/02, page 855 of 1064 Bit 11—Master Bus Timeout Interrupt Mask (MST_BUSTO) Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 3—Target Abort Interrupt Mask (TGT_ABORT) Bit 2—Master Abort interrupt Mask (MST_ABORT) Bit 1—Read Data Parity Error Interrupt Mask (DPERR_WT) Bit 0—Write Data Parity Error Interrupt Mask (DPERR_RD) 22.2.26 PCI Error Bus Master Data Register (PCIBMLR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — REQ4ID REQ3ID REQ2ID REQ1ID REQ0ID Initial value: 0 0 0 — — — — — PCI-R/W: R R R R R R R R PP Bus-R/W: R R R R R R R R The PCI error bus master data register (PCIBMLR) stores the device number of the bus master at the time an error occurred in PCI transfer by another PCI device when the PCIC was operating as the host with the arbitration function. It is a 32-bit register than can be read from both the PP bus and PCI bus. The PCIINTM register is initialized to H'00000000 at a power-on reset or software reset. A valid value is retained only when one of the PCIAINT register bits is set to 1. The bus master data holding circuit can only store data for one master. For this reason, no bus master data is stored for any second or subsequent errors if errors occur consecutively. Bits 31 to 5—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 4—REQ4 Error (REQ4ID): Error occurred when device 4 (REQ4) was bus master. Rev. 3.0, 04/02, page 856 of 1064 Bit 3—REQ3 Error (REQ3ID): Error occurred when device 3 (REQ3) was bus master. Bit 2—REQ2 Error (REQ2ID): Error occurred when device 2 (REQ2) was bus master. Bit 1—REQ1 Error (REQ1ID): Error occurred when device 1 (REQ1) was bus master. Bit 0—REQ0 Error (REQ0ID): Error occurred when device 0 (REQ0) was bus master. 22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — DMABT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R R/W PP Bus-R/W: R R R R R R R R/W The PCI DMA transfer arbitration register (PCIDMABT) is a register that controls the arbitration mode in the case of DMA transfers. Two types of DMA arbitration mode can be selected: priorityfixed and pseudo round-robin. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIDMABT register is initialized to H'00000000 at a power-on reset or software reset. Always write to this register to specify the DMA transfer arbitration mode prior to starting DMA transfers. Bits 31 to 1—Reserved: These bits always returns 0 when read. Always write 0 to these bits when writing. Bit 0—DMA3 Arbitration Mode (DMABT): Controls the DMA arbitration mode. Bit 0: DMABT Description 0 Priority-fixed (Channel 0 > Channel 1 > Channel 2 > Channel 3) (Initial value) 1 Pseudo round-robin Rev. 3.0, 04/02, page 857 of 1064 22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0]) Bit: 31 30 29 28 27 26 25 24 PDPA31 PDPA30 PDPA29 PDPA28 PDPA27 PDPA26 PDPA25 PDPA24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit: PDPA23 PDPA22 PDPA21 PDPA20 PDPA19 PDPA18 PDPA17 PDPA16 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PDPA9 PDPA8 Bit: PDPA15 PDPA14 PDPA13 PDPA12 PDPA11 PDPA10 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PDPA7 PDPA6 PDPA5 PDPA4 PDPA3 PDPA2 PDPA1 PDPA0 Bit: Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W The DMA transfer PCI address register [3:0] (PCIDPA [3:0]) specifies the starting address at the PCI when performing DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIINTM register is initialized to H'00000000 at a power-on reset and a software reset. The transfer address of a byte boundary or character boundary can be set, but the 2 least significant bits of this register are ignored, and the data of the longword boundary is transferred. Before starting a DMA transfer, be sure to write to this register. After a DMA transfer starts, the value in the register is not retained. Always re-set the register value before starting a new DMA transfer after a DMA transfer has been completed. Rev. 3.0, 04/02, page 858 of 1064 Bits 31 to 0—DMA Transfer PCI Starting Address (PDPA31 to 0): Set the PCI starting address for DMA transfer. 22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) Bit: 31 30 29 28 27 26 25 24 — — — Initial value: 0 0 0 PDLA28 PDLA27 PDLA26 PDLA25 PDLA24 0 0 0 0 0 PCI-R/W: R R R R/W R/W R/W R/W R/W PP Bus-R/W: R R R R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 PDLA23 PDLA22 PDLA21 PDLA20 PDLA19 PDLA18 PDLA17 PDLA16 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PDLA9 PDLA8 Bit: PDLA15 PDLA14 PDLA13 PDLA12 PDLA11 PDLA10 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PDLA7 PDLA6 PDLA5 PDLA4 PDLA3 PDLA2 PDLA1 PDLA0 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial value: The DMA transfer local bus start address register [3:0] (PCIDLA [3:0]) specifies the starting address at the local bus when performing DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. The PCIDLA register is initialized to H'00000000 at a power-on reset and a software reset. Rev. 3.0, 04/02, page 859 of 1064 The transfer address of a byte boundary or character boundary can be set, but the 2 least significant bits of the register are ignored, and the data of the longword boundary is transferred. Note that the local bus starting address set in this register is the external address of the SH. Always write to this register prior to starting DMA transfers. After a DMA transfer starts, the register value is not retained. Always re-set this register before starting a new DMA transfer after a DMA transfer has completed. Bits 31 to 29—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 28 to 0—DMA Transfer Local Bus Starting Address (PDLA28 to 0): These bits set the starting address of the local bus (external address of SH) for DMA transfer. Bits 28 to 26 indicate the local bus area. 22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]) Bit: 31 30 29 28 27 26 25 24 — — — — — — PTC25 PTC24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R R R R R R R/W R/W PP Bus-R/W: R R R R R R R/W R/W Bit: 23 22 21 20 19 18 17 16 PTC23 PTC22 PTC21 PTC20 PTC19 PTC18 PTC17 PTC16 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PTC15 PTC14 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Initial value: Bit: Initial value: Bit: Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 860 of 1064 The DMA transfer counter register [3:0] (PCIDTC [3:0]) specifies the number of bytes for DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. When read during a DMA transfer, it returns the remaining number of bytes in the DMA transfer. The PCIDTC register is initialized to H'00000000 at a power-on reset and a software reset. Bits 25 to 0 are used to specify the number of transfer bytes. When set to H'00000000, the maximum 64MB transfer is performed. Since the transfer data size corresponds only to longword data, the 2 least significant bits are ignored. Always write to this register prior to starting a DMA transfer. Please re-set this register when starting a new DMA transfer after a DMA transfer completes. Bits 31 to 26—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 25 to 0—PIC25 to 0: Specify the number of bytes in DMA transfer. The maximum number of transfer bits are 64 MB (when set to H'00000000). Rev. 3.0, 04/02, page 861 of 1064 22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0]) Bit: 31 30 29 ... 19 18 17 16 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: R R R ... R R R R PP Bus-R/W: R R R ... R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — Initial value: 0 0 0 0 0 0 0 0 ALNMD10 ALMMD9 DMAST PCI-R/W: R R R R R R/W R/W R PP Bus-R/W: R R R R R R/W R/W R Bit: 7 6 5 4 3 2 1 0 DMAIM DMAIS LAHOLD — IOSEL0 DIR Initial value: DMASTOP DMASTRT 0 0 0 0 0 0 0 0 PCI-R/W: R/W R/WC R/W R R/W R/W R/W R/W PP Bus-R/W: R/W R/WC R/W R R/W R/W R/W R/W Note: Cleared by writing WC:1. (Writing of 0 is ignored.) The DMA transfer control register [3:0] (PCIDCR [3:0]) specifies the operating mode of the respective channels and the method of transfer, etc. This 32-bit read/write register can be accessed from the PP bus and PCI bus. The PCIDCR register is initialized to H'00000000 at a power-on reset and software reset. Writing 1 to bit 0 (DMASTRT) starts DMA transfer. Always re-set the value in this register before starting a new DMA transfer after completion of a DMA transfer. When setting the DMASTOP bit, do not write 1'b1 to the DMASTART bit. Also, write the same setting at the start of transfer to the DMAIM, DMAIS, LAHOLD, IOSEL and DIR bits. Example: Starting transfer with PCIDCR = H'00000085 Forced DMA termination PCIDCR = H'00000086 If DMA is forcibly terminated with a value other than the setting used in the transfer being performed, data accuracy is not guaranteed. Bits 31 to 11—Reserved: These bits always return 0 when read. Always write 0 to these bits. Rev. 3.0, 04/02, page 862 of 1064 Bits 10 and 9—Alignment Mode (ALNMD): Sets data alignment when local bus is big endian Bit 10: ALNMD10 Bit 9: ALNMD9 Description 0 0 Byte boundary mode 1 W/LW boundary mode 1 (LW data is sent as byte
4) 0 W/LW boundary mode 2 (LW data is sent as word
2) 1 W/LW boundary mode 3 (LW data is sent as longword) 1 (Initial value) Notes: W: Word LW: Longword For details, refer to section 22.4, Endians. Bit 8—DMA Transfer End Status (DMAST): Indicates the DMA transfer end status. Bit 8: DMAST Description 0 Normal termination 1 Abnormal termination (Error detection or forced DMA transfer termination) (Initial value) Bit 7—DMA Transfer Termination Interrupt Mask (DMAIM): Specifies the DMA transfer termination interrupt mask. Bit 7: DMAIM Description 0 Interrupt disabled 1 Interrupt enabled (Initial value) Bit 6—DMA Transfer Termination Interrupt Status (DMAIS): Indicates the DMA transfer termination interrupt status. The interrupt status is set even when the interrupt mask is set. Bit 6: DMAIS When writing When reading Description 0 Ignored 1 Status clear 0 Interrupt not detected 1 Interrupt detected (Initial value) Bit 5—Local Address Control (LAHOLD): Local address control during DMA transfer Bit 5: LAHOLD Description 0 Incremented 1 High address fixed (Address A[4:0] is incremented) (Initial value) Rev. 3.0, 04/02, page 863 of 1064 Bit 4—Reserved: This bit always returns 0 when read. Always write 0 to this bit. Bit 3—PCI Address Space Type (IOSEL): Type of PCI address space during transfer Bit 3: IOSEL Description 0 Memory space 1 I/O space (Initial value) Bit 2—Transfer Direction (DIR): Transfer direction during DMA transfer Bit 2: DIR Description 0 Transfer from PCI bus to local bus (SH bus) 1 Transfer from local bus (SH bus) to PCI bus (Initial value) Bit 1—Forced DMA Transfer Termination (DMASTOP): Forced termination of DMA transfer Bit 1: DMASTOP When writing Description 0 1 When reading Writing of 0 is ignored. Forced termination of DMA transfer When DMA transfer stops due to forced DMA transfer termination, 1 is set Bit 0—DMA Transfer Start Control (DMASTRT): Controls the starting of DMA transfer. Bit 0: DMASTRT When writing When reading Description 0 Ignored 1 Start 0 End of transfer 1 Busy (in transfer) Rev. 3.0, 04/02, page 864 of 1064 (Initial value) 22.2.32 PIO Address Register (PCIPAR) Bit: 31 30 29 28 27 26 25 24 CFGEN — — — — — — — Initial value: 1 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 BUSNO23 BUSNO22 BUSNO21 BUSNO20 BUSNO19 BUSNO18 BUSNO17 BUSNO16 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PP Bus-R/W: Bit: DEVNO15 DEVNO14 DEVNO13 DEVNO12 DEVNO11 FNCNO10 FNCNO9 FNCNO8 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — PP Bus-R/W: Bit: REGADR7 REGADR6 REGADR5 REGADR4 REGADR3 REGADR2 Initial value: — — — — — — 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R R PP Bus-R/W: The PIO address register (PCIPAR) is used when issuing configuration cycles on the PCI bus when the PCIC is host. The PCIC supports the configuration mechanism 1 stipulated in the PCI local bus specifications. This register is equivalent to the configuration register of configuration mechanism 1. This register is equivalent to the CONFIG_ADDRESS of configuration mechanism 1. The check that the issuance of the PCI configuration cycle is enabled, and access the PCI configuration space, this register contains the PCI bus No., device No., Function No., and LW (longword) boundary of the configuration register. This 32-bit read/write register can be accessed from the PP bus. Bit 31 (CFGEN) is set in hardware and none of the other bits of the PCIPAR register are initialized at a power-on reset or software reset. Rev. 3.0, 04/02, page 865 of 1064 Always write to this register prior to accessing the PCI configuration space. After setting a value in this register, generate the configuration cycle by reading or writing to the PIO data register (PCIPDR). Also, a special cycle is issued by setting H'8000FF00 in this register and writing to the PCIPDR. Bit 31—Configuration Cycle Generate Enable (CFGEN): Indicates the configuration cycle generation enable. Bits 30 to 24—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bits 23 to 16—PCI Bus No. (BUSNO): These bits specify the No. of the PCI bus subject to configuration access. Bus No. D indicates the bus connected with the PCIC. The bus No. is expressed with 8 bits, and its maximum value is 255. Bits 15 to 11—Device No. (DEVNO): These bits specify the No. of the device subject to configuration access. The device No. is expressed with 5 bits, and takes a value from bits 0 to 31. In place of IDSEL, one of bits 31 to 16 of the A/D line, corresponding to the device No. set in this field, is driven to “1”. The following table shows the relationship between the device No. and IDSEL (A/D [31 to 16]). When the device No. is 10h or greater, A/D [31 to 16]) are all zeros. DEVNO IDSEL DEVNO IDSEL DEVNO IDSEL DEVNO IDSEL H'0 AD[16] = 1 H'4 AD[20] = 1 H'8 AD[24] = 1 H'C AD[28] = 1 H'1 AD[17] = 1 H'5 AD[21] = 1 H'9 AD[25] = 1 H'D AD[29] = 1 H'2 AD[18] = 1 H'6 AD[22] = 1 H'A AD[26] = 1 H'E AD[30] = 1 H'3 AD[19] = 1 H'7 AD[23] = 1 H'B AD[27] = 1 H'F AD[31] = 1 Bits 10 to 8: Function No. (FNCNO): These bits specify the No. of the function subject to configuration access. The function No. is expressed with 3 bits, and takes a value of 0 to 7. Bits 7 to 2—Configuration Register Address (REGADR): These bits set the register subject to configuration access with a longword boundary. Bits 1 and 0—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Rev. 3.0, 04/02, page 866 of 1064 22.2.33 Memory Space Base Register (PCIMBR) Bit: Initial value: PCI-R/W: PP Bus-R/W: Bit: 31 30 29 28 27 26 25 24 MBR31 MBR30 MBR29 MBR28 MBR27 MBR26 MBR25 MBR24 0 0 0 0 0 0 0 0 — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — LOCK Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R/W The memory space base register (PCIMBR) specifies the most significant 8 bits of the address of the PCI memory space when performing a memory read/write operation using PIO transfers. It also specifies locked transfers. This 32-bit read/write register can be accessed from the PP bus. All bits of the PCIMBR register are initialized to 0 at a power-on reset. They are not initialized at a software reset. Setting bit 0 (LOCK) to 1 locks the memory space for PIO transfers while the bit remains set. A locked transfer consists of the combined read and write operations. Do not attempt to perform other PIO transfers during the locked combination of read and write operations. Always write to this register prior to performing memory read/write operations by PIO transfer. Rev. 3.0, 04/02, page 867 of 1064 Bits 31 to 24—Memory Space Base Address (MBR31 to 24): Sets the base address for the PCI memory space in PIO transfers. (Initial value is undefined.) Bits 23 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 0—Lock Transfer (LOCK): Specifies the locking of the memory space during PIO transfer. Bit 0: LOCK Description 0 Not locked 1 Locked (Initial value) 22.2.34 I/O Space Base Register (PCIIOBR) Bit: 31 30 29 28 27 26 25 24 IOBR31 IOBR30 IOBR29 IOBR28 IOBR27 IOBR26 IOBR25 IOBR24 Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: Bit: 23 22 21 20 19 18 17 16 IOBR23 IOBR22 IOBR21 IOBR20 IOBR19 IOBR18 — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R R 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PP Bus-R/W: Bit: PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — — LOCK Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R/W Rev. 3.0, 04/02, page 868 of 1064 The I/O space base register (PCIIOBR) species the most significant 14 bits of the address of the PCI I/O space when performing I/O read and I/O write operations by PIO transfer. It also specifies locked transfers. This 32-bit read/write register can be accessed from the PP bus. All bits of the PCII0BR register are initialized to 0 at a power-on reset. They are not initialized at a software reset. Setting bit 0 (LOCK) to 1 locks the I/O space for PIO transfers while the bit remains set. A locked transfer consists of the combined read and write operations. Do not attempt to perform other PIO transfers during the locked combination of read and write operations. Always write to this register prior to I/O space read and I/O space write operations by PIO transfer. Bits 31 to 18—I/O Space Base Address (IOBR31 to 18): Sets the base register for the PCI I/O space in PIO transfers. Bits 17 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 0—Lock Transfer (LOCK): Specifies the locking of the I/O space during PIO transfer. Bit 0: LOCK Description 0 Not locked 1 Locked (Initial value) Rev. 3.0, 04/02, page 869 of 1064 22.2.35 PCI Power Management Interrupt Register (PCIPINT) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/WC R/WC PWRST_ PWRST_ D3 D0 Note: Cleared by setting WC:1. (Writing of 0 is ignored.) The PCI power management interrupt register (PCIPINT) controls the power management interrupts. It provides the interrupt bits for a transition to the power state D3 (power down mode) and recovery to the power state D0 (normal state). This 32-bit read/write register can be accessed from the PP bus. The PCIPINT register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When an interrupt is detected, the bit corresponding to the content of that interrupt is set to 1. Each interrupt detection bit can be cleared to 0 by writing 1 to it (write clear). The power state D0 interrupt is not generated at a power-on reset. Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 1—Power state D3 (PWRST_D3): Transition request to power-down mode interrupt for SH7751 and SH7751R. Bit 0—Power state D0 (PWRST_D0): Restore from power-down mode interrupt for SH7751 and SH7751R. Note: The power states D3, D0 are not masked even when the interrupt mask bit is set ON. Rev. 3.0, 04/02, page 870 of 1064 22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/W R/W DPERR_ DPERR_ WT RD The PCI power management interrupt mask register (PCIPINTM) sets the interrupt mask for the power management interrupts. This 32-bit read/write register can be accessed from the PP bus. The PCIPINTM register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. Interrupt masks can be set for both the interrupt for a transition to the power state D3 (power down mode) and recovery to the power state D0 (normal status). Setting the respective bit to 0 disables the interrupt and setting it to 1 enables the interrupt. Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 1—Power State D3 (PWRST_D3): Transition request to power-down mode interrupt mask for SH7751 and SH7751R. Bit 0—Power State D0 (PWRST_D0): Restore from power-down mode interrupt mask for SH7751 and SH7751R. Rev. 3.0, 04/02, page 871 of 1064 22.2.37 PCI Clock Control Register (PCICLKR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R/W R/W PCICLKS BCLKST TOP OP The PCI clock control register (PCICLKR) controls the stopping of the local bus clock (BCLK) in the PCIC and the PCI bus clock. This 32-bit read/write register can be accessed from the PP bus. The PCICLKR register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When the PCI bus clock is input from the external input pin , the PCI bus clock can be stopped by setting the PCICLKSTOP bit to 1. Likewise, the local bus clock can be stopped by setting the BCLKSTOP bit to 1. When the PCI bus clock is input via the CKIO pin, setting BCLKSTOP to 1 stops both the B in the PCIC and the feedback input clock from CKIO. Writing to this register is valid only when bits 31 to 24 are H'A5. Bits 31 to 2—Reserved: These bits are always read as 0. When writing, always write H'A5 to bits 31 to 24, and 0 to the other bits. Always write 0 to these bits when writing. Bit 1—PCICLK Stop Control (PCICLKSTOP): Controls the stopping of the clock input via the PCICLK pin. Bit 1: PCICLKSTOP Description 0 PCICLK input enabled 1 Stop PCICLK input Rev. 3.0, 04/02, page 872 of 1064 (Initial value) Bit 0—BCLK Stop Control (BCLKSTOP): Controls the stopping of the B input clock and CKIO input clock in the PCIC. Bit 0: BCLKSTOP Description 0 B
input enabled 1 Stop B
input (Initial value) 22.2.38 PCIC-BSC Registers PCIC Bus Control Register 1 (PCIBCR1) PCIC Bus Control Register 2 (PCIBCR2) 1 PCIC Bus Control Register 3 (PCIBCR3)* PCIC Wait Control Register 1 (PCIWCR1) PCIC Wait Control Register 2 (PCIWCR2) PCIC Wait Control register 3 (PCIWCR3) PCIC Discrete Memory Control Register (PCIMCR) Because PCI bus data is stored, in the PCIC, in memory on the local bus, the PCIC is equipped with an internal bus controller (PCIC-BSC). The PCIC-BSC performs the same type of control as the slave function of the bus controller (BSC). There are six registers in the PCIC-BSC: PCIBCR1 (equivalent to the BCR1 of the BSC), PCIBCR2 (equivalent to the BCR2 of the BSC), PCIBCR3 (equivalent to the BCR3 of the BSC), PCIWCR1 (equivalent to the WCR1 of the BSC), PCIWCR2 (equivalent to the WCR2 of the BSC), PCIWCR3 (equivalent to the WCR3 of the BSC), and PCIMCR (equivalent to the MCR of the BSC). Each is a 32-bit register. BCR2 and BCR3 are 16-bit registers, but PCIBCR2 and PCIBCR3 should be accessed by longword access. The low 16 bits of PCIBCR2 and PCIBCR3 corresponds to the 16 bits of these registers, respectively. See section 13, Bus State Controller (BSC), for details of the initial values, etc.
The PCIC-BSC performs the same operations as the slave mode of the BSC. Therefore, the MATER bit of the PCI bus control register 1 (PCIBCR1) shows the slave status.
Because the PCIC-BSC operates in slave mode, the bus privilege is handed to the BSC once per bus cycle. Note, however, that the external memory capable of data transfers to the PCI bus is SRAM, 2 DRAM, synchronous DRAM, and MPX* . Also, the memory data width is 32-bit or 16-bit only (only 32-bit in the case of synchronous DRAM). Do not specify other external memory types (burst ROM, MPX, byte control SRAM or PCMCIA) as the external memory for data transfers with the PCI bus.
Because the PCIC-BSC operates in slave mode, the RAS-down mode of DRAM and SDRAM is not available.
The local bus supports both big and little endian. However, the PCI bus supports only little endian. Rev. 3.0, 04/02, page 873 of 1064 The PCI-BSC does not support mode register setting of synchronous DRAM nor refreshing of synchronous DRAM or DRAM. These must be executed by the BSC. Also, do not implement any settings that are not allowed in slave mode in the PCIC-BSC registers. This is because bit 30: master/slave flag (MASTER) of the PCIBCR1 is fixed Low, regardless of the value of the external master/slave setting pin (MP7) at a power-on reset, and the PCIC-BSC therefore is set in slave mode. In the case of external memory not used for data transfers with the PCI bus, make the same settings as the corresponding bus state controller register. These registers are initialized at a power-on reset, but not by a software reset. Notes: *1 This register is provided only in the SH7751R, not provided in the SH7751. *2 MPX is supported only in the SH7751R, not supported in the SH7751. 22.2.39 Port Control Register (PCIPCTR) Bit: 31 30 29 28 27 26 25 24 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 — — — — — Initial value: 0 0 0 0 0 PORT2EN PORT1EN PORT0EN 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 — — PB2PUP PB2IO PB1PUP PB1IO PB0PUP PB0IO Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R/W R/W R/W R/W R/W R/W Rev. 3.0, 04/02, page 874 of 1064 The port control register (PCIPCTR) selects whether to enable or disable port function allocation for pins for unwanted PCI bus arbitration when the PCIC is used in non-host mode. It also specifies the swithing ON/OFF of pin pull-up resistances and between input and output. This 32bit read/write register can be accessed from the PP bus. The PCIPCTR register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When the PCIC is operating as host, the port function cannot be used if the arbitration function is enabled. Bits 31 to 19—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 18—Port 2 Enable (PORT2EN): Provides the enable control for the port 2. Bit 18: PORT2EN Description 0 Do not use pins    or  
 as ports 1 (Initial value) Use pins    or  
 as ports Bit 17—Port 1 Enable (PORT1EN): Provides the enable control for the port 1. Bit 17: PORT1EN Description 0 Do not use pins    or  
 as ports 1 (Initial value) Use pins    or  
 as ports Bit 16—Port 0 Enable (PORT0EN): Provides the enable control for the port 0. Bit 16: PORT0EN Description 0 Do not use pins    or  
 as ports 1 (Initial value) Use pins    or  
 as ports Bits 15 to 6—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 5—Port 2 Pull-up Resistance Control (PB2PUP): Controls pull-up resistance when  pin is used as port. Bit 5: PB2PUP Description 0 Pull-up  
 pin 1 (Initial value) Do not pull-up  
 pin Rev. 3.0, 04/02, page 875 of 1064 Bit 4—Port 2 Input/Output Control (PB2IO): Controls input or output when  is used as a port. Bit 4: PB2IO Description 0 Set  
 pin for input 1 (Initial value) Set  
 pin for output Bit 3—Port 1 Pull-up Resistance Control (PB1PUP): Controls pull-up resistance when  pin is used as port. Bit 3: PB1PUP Description 0 Pull-up  
 pin 1 (Initial value) Do not pull-up  
 pin Bit 2—Port 1 Input/Output Control (PB1IO): Controls input or output when  is used as a port. Bit 2: PB1IO Description 0 Set  
 pin for input 1 (Initial value) Set  
 pin for output Bit 1—Port 0 Pull-up Resistance Control (PB0PUP): Controls pull-up resistance when  pin is used as port. Bit 1: PB0PUP Description 0 Pull-up  
 pin 1 (Initial value) Do not pull-up  
 pin Bit 0—Port 0 Input/Output Control (PB0IO): Controls input or output when  is used as a port. Bit 0: PB0IO Description 0 Set  
 pin for input 1 Set  
 pin for output Rev. 3.0, 04/02, page 876 of 1064 (Initial value) 22.2.40 Port Data Register (PCIPDTR) Bit: 31 30 29 ... 11 10 9 8 — — — ... — — — — Initial value: 0 0 0 ... 0 0 0 0 PCI-R/W: — — — ... — — — — PP Bus-R/W: R R R ... R R R R Bit: 7 6 5 4 3 2 1 0 — — PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value: 0 0 0 0 0 0 0 0 PCI-R/W: — — — — — — — — PP Bus-R/W: R R R/W R/W R/W R/W R/W R/W The port data register (PCIPDTR) inputs and outputs the port data when allocation of the port function to the unwanted PCI bus arbitration pins is enabled when the PCIC is operating in nonhost mode. This 32-bit read/write register can be accessed from the PP bus. The PCIPDTR register is intialized to H'00000000 at a power-on reset. It is not initialized at a software reset. Data is output in sync with the local bus clock. Input data is fetched at the rising edge of the local bus clock. Bits 31 to 6—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 5—Port 2 Output Data (PB5DT): Output data when   pin is used as port. (  pin is output-only.) Bit 4—Port 2 Input/Output Data (PB4DT): Receives input data and sets output data when the  pin is used as a port. Bit 3—Port 1 Output Data (PB3DT): Output data when   pin is used as port. (  pin is output-only.) Bit 2—Port 1 Input/Output Data (PB2DT): Receives input data and sets output data when the  pin is used as a port. Bit 1—Port 0 Output Data (PB1DT): Output data when   pin is used as port. (  pin is output-only.) Rev. 3.0, 04/02, page 877 of 1064 Bit 0—Port 0 Input/Output Data (PB0DT): Receives input data and sets output data when the  pin is used as a port. 22.2.41 PIO Data Register (PCIPDR) Bit: 31 30 29 28 27 26 25 24 PPDA31 PPDA30 PPDA29 PPDA28 PPDA27 PPDA26 PPDA25 PPDA24 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 PP Bus-R/W: Bit: PPDA23 PPDA22 PPDA21 PPDA20 PPDA19 PPDA18 PPDA17 PPDA16 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 PPDA9 PPDA8 PPDA15 PPDA14 PPDA13 PPDA12 PPDA11 PPDA10 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: Bit: 7 6 5 4 3 2 1 0 PPDA7 PPDA6 PPDA5 PPDA4 PPDA3 PPDA2 PPDA1 PPDA0 Initial value: — — — — — — — — PCI-R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W PP Bus-R/W: The PIO data register (PCIPDR) sets the data for read/write in the PCI configuration cycle. This 32-bit read/write register can be accessed from the PP bus. The PCIPDR register is not initialized at a power-on reset or software reset. The initial value is undefined. Always write to this register before accessing the PCI configuration space. Always read/write to this register after setting the value in the PIO address register (PIOPAR). The configuration cycle on the PCI bus can be generated by reading/writing to this register. Rev. 3.0, 04/02, page 878 of 1064 Bits 31 to 0—PIO Configuration Data (PPDA31 to 0): Read/write register for configuration data in PIO transfers. The configuration cycle on the PCI bus can be generated by reading/writing to this register. 22.3 Description of Operation 22.3.1 Operating Modes The external mode pins (MD9 and MD10) select whether the PCIC operates as the host on the PCI bus and also select the bus clock for the PCI bus. The mode selection signals input via the external mode pins are fetched on negation of a power-on reset. Table 22.8 Operating Modes MD9 MD10 Operating Modes 0 0 The PCIC host functions are enabled and the external input via the PCICLK pin is the operating clock for the PCI bus 1 The PCIC host functions are enabled and the SH7751 Series bus clock (feedback input clock from CKIO pin) is the operating clock for the PCI bus 0 The PCIC host functions are disabled (non-host) and the input clock from the PCICLK pin is selected as the clock for the PCI bus 1 PCIC-disabled mode. In this mode, PCIC operation is disabled 1 Note: In PCIC-disabled mode, do not attempt to access the PCIC local registers. In this section, the clock resulting from the above mode switching is known as the PCI bus clock. Rev. 3.0, 04/02, page 879 of 1064 22.3.2 PCI Commands Table 22.9 lists the PCI commands and shows the PCIC support. Table 22.9 PCI Command Support Host Operation Non-Host Operation Command Master Target Master Target Memory read O O O O Memory read line X  X  When the target, operates as memory read Memory read multiple X  X  When the target, operates as memory read Memory write O O O O Memory write and invalidate X  X  I/O read O O O O I/O write O O O O Configuration read O — — O Configuration write O — — O Interrupt acknowledge cycle X X X X Special cycle O — — X Dual address cycle X X X X Remarks When the target, operates as memory write Notes: O: Supported : Limited support X, —: Not issued by PCIC or no response from PCIC When PCIC Operates as Master: The PCIC supports the memory read command, memory write command, I/O read command, and I/O write command. When the host functions are enabled, the configuration command and special cycle can also be used. When PCIC Operates as Target: The PCIC receives the memory read command, memory write command, I/O read command, and I/O write command. The memory read line command and memory read multiple command function as memory reads, while the memory write invalidate command functions as a memory write. When operating in non-host mode, the PCIC accepts the configuration command. Rev. 3.0, 04/02, page 880 of 1064 22.3.3 PCIC Initialization After a power-on reset, the configuration register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host, the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus. When the PCIC is not operating as host, retries are returned without accepting access from PCI devices connected to the PCI bus. The PCIC’s internal configuration registers and local registers must be initialized while the CFINIT bit is cleared to 0. On completion of initialization, set the CFINIT bit to 1. When operating as host, arbitration is enabled; when operating as non-host, the PCIC can be accessed from the PCI bus. Regardless of whether or not the PCIC is operating as host, external PCI devices cannot be accessed from the PCIC while the CFINIT bit is cleared. If the PCIC's internal configuration registers and local registers are initialized correctly, the PCIC will operate correctly. However, we recommend first setting the CFINIT bit to 1. When the PCIC is operating as the host, arbitration is enabled. When operating as non-host, the PCIC can be accessed from the PCI bus. Regardless of whether the PCIC is operating as the host or non-host, external PCI devices cannot be accessed from the PCIC while the CFINT bit is being cleared. Set the CFINIT bit to 1 before accessing an external PCIC device. Be sure to initialize the following 13 registers while the CFINIT bit is being cleared: configuration registers 1, 2, 11 (PCICONF1, 2, 11) for PCI, local space registers 0, 1 (PCILSR0, 1) for PCI, local address registers 0, 1 (PCILAR0, 1) for PCI, PCI bus control registers 1, 2 (PCIBCR1, 2) for PCIC-BSC, PCI weight control registers 1, 2, 3 (PCIWCR1, 2, 3), and PCI-specific memory control register (PCIMCR). Since the PCIC-BSC is fixed in sleep mode at a power-on reset regardless of the value of the external pin (MD7) for master/slave designation, do not make a PCIC-BSC register setting that is prohibited in the sleep mode. Also, as the BSC has BCR1 and BREQEN bits that enable an external request and a bus request from the PCIC to be accepted, BCR1 and BREQEN should be set to 1 when the PCIC is used. While 1 is being set in the CFINIT bit, the registers for the PCIC-BSC (PCIBCR1, 2, PCIWCR1, 2, 3, PCIMCR) cannot be written to. The data transfer accuracy between the PCI bus and local bus cannot be guaranteed if an attempt is made to write to any of these registers during this period. Rev. 3.0, 04/02, page 881 of 1064 22.3.4 Local Register Access Only longword (32-bit) access of the PCIC's internal local registers and configuration registers from the CPU is supported. (It is possible to use PIO transfers to perform byte, word, and longword access of the memory space and I/O space on the PCI bus.) If an attempt is made to access these registers using other than the prescribed access size, zero is returned when reading and writing is ignored. The same is true if you attempt to access the reserved areas in the register area in the PCIC. Some of the configuration registers and local registers can be accessed both from the CPU and from the PCI device(s). Therefore, arbitration is performed for both types of access and either the CPU or PCI device access made to wait according to the access timing. In the read bus cycle from the CPU, the internal bus cycle for the peripheral module is made to wait until the data is actually ready. In the write bus cycle, the bus cycle of the internal bus for peripheral modules ends with the data having been written to the interface (register located immediately after the PCIC input) register on the internal bus for peripheral modules, but the data is not actually written to the local register(s) or PCI bus until the following clock cycle. If it is necessary to check that the data has actually been written, read the register to which the data was to have been written. This is because the read cycle must be after the write cycle has completed. When accessing from a PCI device, the PCI bus cycle is caused to wait until the read or write operation has actually completed. The internal bus for peripheral modules used for read/write operations from the CPU operates only with big endians. 22.3.5 Host Functions The PCIC has the following PCI bus host functions (host devices):
Inter-PCI device arbitration function
Configuration register access function
Special cycle generation function
Reset output function
Clock output function Inter-PCI Device Arbitration: The PCI bus arbitration circuit in the PCIC can be used when the PCIC is operating as the host device. The arbitration circuit can be connected to up to four external PCI devices (devices that can operate as master devices) that request bus privileges. Rev. 3.0, 04/02, page 882 of 1064 If multiple bus privilege requests are made simultaneously by the PCI devices, the bus privilege is grated in the predetermined order of priority. There are two orders of priority: fixed, and pseudo round robin. The mode is selected by setting the bus master arbitration mode control bit (BMABT) of the PCI control register (PCICR).
Priority-fixed mode (BMABT = 0) In priority-fixed mode, the priority order of bus privilege requests is fixed and cannot be changed. The order is as follows: PCIC (device 0) > device 1 > device 2 > device 3 > device 4 That is, the PCIC has the highest order of priority and device 4 has the lowest. When bus privilege requests occur simultaneously, the device with the highest order of priority takes precedence. Here, device 1 is the PCI device using bus privilege request pins  and  , device 2 uses  and  , device 3 uses  and  , and device 4 uses  and  . When the PCIC is operating as the host device, no bus privilege request signals are output from the PCIC to the PCI bus arbitration circuit.
Pseudo round-robin mode (BMABT = 1) In pseudo round-robin mode, when a device takes the bus privilege, the priority order of that device becomes lowest. In the initial state, the priority order is set to the same as in the fixed mode. Here, device 1 outputs a bus privilege request, after which the priority order changes to … PCIC > device 2 > device 3 > device 4 > device 1. If the PCIC then outputs a bus privilege request and takes the bus privilege, the priority order changes to … Device 2 > device 3 > device 4 > device 1 > PCIC. Likewise, if device 3 outputs a bus privilege request and takes the bus privilege, the priority order becomes … Device 2 > device 4 > device 1 > PCIC > device 3. In this way, the priority order of the master device that takes the bus privilege always changes to lowest after the data transfer is completed. Rev. 3.0, 04/02, page 883 of 1064 1. Initial order of priority (transfer by device 1) PCIC > device 1 > device 2 > device 3 > device 4 2. Order of priority after transfer (transfer by PCIC) PCIC > device 2 > device 3 > device 4 > device 1 3. Order of priority after transfer (transfer by device 3) device 2 > device 3 > device 4 > device 1 > PCIC 4. Order of priority after transfer device 2 > device 4 > device 1 > PCIC > device 3 When the PCIC is operating as the host device, the PCIC performs the PCI bus parking (bus drive when not in use). When 3 or fewer master devices are connected, set the level of the unused pins of  [4:1] high. In non-host mode, the PCI bus arbitration function of the PCIC is disabled. PCI bus arbitration is performed according to the specifications of the connected PCI bus arbiter. For details, see section 22.3.6, PCI Bus Arbitration in Non-host Mode. Configuration Register Access: The configuration register of external PCI devices can be accessed when the PCIC is operating as the host device. The PIO address register (PCIPAR) and PIO data register (PCIPDR) are used to generate a configuration read/write transfer for accessing the configuration register. The PCIC supports the configuration mechanism stipulated in the PCI local bus spec. First, specify in the PCIPAR the address of the configuration register of the external PCI device to be accessed. See section 22.2, PCIC Register Descriptions, for how to set the PCIPAR. Next, read data from the PCIPDR or write data to the PCIPDR. Only longword (32-bit) access of the PCIPDR is supported. Special Cycle Generation: When the PCIC operates as the host device, a special cycle is generated by setting H'8000FF00 in the PCIPAR and writing to the PCIPDR. Reset Output: When the PCIC is operating as the host device,  can be used to reset the PCI bus. See section 22.5, Resetting, for details of  . Clock Output: When the PCIC is operating as the host device and the bus clock (CKIO pin) is selected as the PCI bus clock, not only does the PCIC’s PCI bus clock operate using the CKIO clock but the CKIO clock can also be used as the PCI bus clock. Thus, there is no requirement for an external PCI clock oscillation circuit. When using the CKIO clock, please note the limitations on CKIO clock frequency, stability, and load capacitance that can be connected to the CKIO pin. Check the clock oscillation circuit and Rev. 3.0, 04/02, page 884 of 1064 electrical characteristics in section 10, Clock Oscillation Circuits, and section 23, Electrical Characteristics. 22.3.6 PCI Bus Arbitration in Non-host Mode When operating in non-host mode, the PCI bus arbitration function in the PCIC is disabled and PCI bus arbitration is performed according to the specifications of the externally connected PCI bus arbiter. In this case, the PCIC must request PCI bus privileges from the PCI bus arbiter (system host device). The  /  pins are used for the bus request signals, and the /  pins are used for the bus grant signals. When the bus grant signals are asserted when the bus request signals are not asserted, the PCIC performs bus parking. Also, when the PCIC is used as a target device that does not request bus privileges, the /  pins must be fixed at the high level. 22.3.7 PIO Transfers PIO transfer is a data transfer mode in which a peripheral bus is used to access the memory space and I/O space of the PCI bus. The following commands are supported in PIO transfer mode:
Memory read, memory write, I/O read, and I/O write
Locked transfer (High-speed back-to-back transfers are not supported.) In PIO transfer mode, only single transfers are supported. 32-byte burst transfers are not supported. In memory transfers and I/O transfers, the supported, so generate byte enable signals (
) to match the respective access sizes and output these signals to the PCI bus. Access sizes are byte, word, and longword. Locked transfers are supported only in the case of memory transfers and I/O transfers. High-speed back-to-back transfers are not supported. Rev. 3.0, 04/02, page 885 of 1064 Memory Transfers: This section describes how PIO transfers are used to access memory space. 16MB between H'FD000000 and H'FDFFFFFF of area P4 (H'1D000000 to H'1DFFFFFF in area 7) is allocated as PCI memory address space. This space is used as the least significant 24 bits of the PCI address. However, in memory transfers, the two low bits of the PCI address are ignored, and B'00 is output to the PCI bus. The most significant 8 bits (MBR [31:24]) of the memory space base register (PCIMBR) are used as the most significant bits of the PCI address. These two addresses are combined to specify a 32-bit PCI address. To transfer to the memory space, first specify the most significant 8 bits of the PCI address in the PCIMBR, then access the PCI memory address space. If within the 16MB space, the PCI memory address space can be consecutively accessed simply by setting the PCIMBR once. If it is necessary to access an address space over the 16MB, set PCIMBR again. When performing locked transfers in memory transfer mode, set the PCIMBR memory space lock specification bit (LOCK). While the LOCK bit is set, the memory space is locked. Note the following when performing LOCK transfers:
A LOCK transfer consists of one read transfer and one write transfer. Always start with the read transfer. The system will operate correctly if you start with a write transfer, but the resource LOCK will not be established. Also, the system will operate correctly if you perform two LOCK read transfers, but the LOCK will be released at the next LOCK write transfer.
The minimum resource for which the LOCK is guaranteed is a 16-byte block. However, the system will operate correctly even if LOCK transfers are made to addresses other than where the LOCK is established.
You cannot access other targets while a target is LOCKed (from the LOCK read until the LOCK write).  PIO LOCK access of another target ends normally and transfers on the PCI bus are also generated.  Unlocked PIO transfer requests invoked between a LOCK read and LOCK write end normally, but no transfers are generated on the PCI bus.  DMA transfers are postponed until the LOCK transfer ends. Rev. 3.0, 04/02, page 886 of 1064 H'FD000000 PCI memory space 16 Mbytes H'FDFFFFFF PCI memory space address 31 24 23 0 H'FD 31 2 0 24 23 00 PCI address 31 24 23 0 PIOMBR LOCK identifier Figure 22.2 PIO Memory Space Access I/O Transfers: This section describes how to access I/O space using PIO transfers. The 256kB from H'FE240000 to H'FE27FFFF of area P4 (H'1E240000 to H'1E27FFFF in area 7) is allocated as PCI I/O address space. This space is used for the least significant 18 bits of the PCI address. The most significant 14 bits (IOBR [31:18]) of the I/O space base register (PCIIOBR) are used as the most significant 14 bits of the PCI address. These two addresses are combined to specify the 32-bit PCI address. For transfers to the I/O space, first specify the most significant 14 bits of the PCI address in PCIIOBR, then access the PCI I/O address space. If within the 256kB space, you can access the PCI I/O address space consecutively simply by setting the PCIIOBR once. If it is necessary to access another address space beyond 256kB, set PCIIOBR again. When performing locked transfers in I/O transfers, set the I/O space lock specification bit (LOCK) in the PCIIOBR. The I/O space is locked while the LOCK bit is set. The same precautions apply to LOCK I/O transfers as to LOCK memory transfers. Rev. 3.0, 04/02, page 887 of 1064 H'FE200000 PCI register space 256 kbytes PIC I/O space 256 kbytes H'FE23FFFF H'FE240000 H'FE27FFFF 31 18 17 PCI I/O space H'FE24–H'FE27 address 0 31 18 17 0 PCI address 31 18 17 0 PIOIOBR LOCK identifier Figure 22.3 PIO I/O Space Access PIO Transfer Error: An error on the PCI bus that occurs in a transfer during a PIO write operation is not detected. When an error is generated during a PIO read operation, the PIO transfer is forcibly terminated to prevent effects on the DMA transfer and target transfer. However, accuracy of the read data is not guaranteed. 22.3.8 Target Transfers The following commands are available for transferring data in target transfers.
Memory read and memory write
I/O read and I/O write (access to PCIC local registers)
Configuration read, configuration write
Locked transfer is supported.
High-speed back-to-back, is not supported. When the PCIC is operating in non-host mode, no response is made on reception of special cycle commands. Memory Read/Memory Write Commands: In the case of memory read and memory write commands, both single transfers and burst transfers are supported on the PCI bus. Data on the PCI bus is always longword data, but
 can be used to control the valid byte lane. In the case of memory read, longword data is always read from the local bus and output to the PCI bus. In the case of memory write, the internal control allows only the writing of valid byte lane data to the Rev. 3.0, 04/02, page 888 of 1064 local bus. Only the linear mode is supported for addressing for burst transfers, and the 2 least significant bits of the PCI address are regarded as B'00. If a memory read line command or memory read multiple command is received, they operate as memory reads. Similarly, when a memory write invalidate command is received, it functions as a memory write. Data must be set in the following registers prior to performing target transfers using memory read or memory write commands: PCI configuration register 5 (PCICNF5), PCI configuration register 6 (PCICNF6), PCI local space register 0 (PCILSR [0]), PCI local space register 1 (PCILSR [1]), PCI local address register 0 (PCILAR [0]), and PCI local address register 1 (PCILAR [1]). PCICONF5 (PCICONF6) 31 20 19 0 PCI address 31 0 PCIC access adjudication PCILSR0 (PCILSR1) PCILAR0 (PCILAR1) 31 28 20 19 0 000001111 31 28 20 19 0 31 28 0 Local address Figure 22.4 Local Address Space Accessing Method The PCIC supports two local address spaces (address space 0 and address space 1). A certain range of the address space on the PCI bus corresponds to the local address space. The local address space 0 is controlled by the PCICONF5, PCILAR0 and PCISR0. Figure 22.4 shows the method of accessing the local address space. The PCICONF5 indicates the starting address of the memory space used by the PCI device. The PCILAR0 specifies the starting address of the local address space 0. The PCILSR0 expresses the size of the memory used by the PCI device. Regarding the method of setting each register, refer to section 22.2, PCIC Register Descriptions. Rev. 3.0, 04/02, page 889 of 1064 For the PCICONF5 and PCILAR0, the most significant address bit that is higher than the memory size set in the PCILSR0 becomes valid. The most significant address bit of the PCICONF5 and the PCI address output from an external PCI device are compared for the purpose of determining whether the access is made to the PCIC. When the addresses correspond, the access to the PCIC is recognized, and a local address is generated from the most significant address bit of the PCILAR0 and the least significant bit of the PCI address output from the external PCI device. The PCI command is executed for this local address. If the most significant address bit of the PCI address output from the external PCI device does not correspond with the most significant address bit of the PCICONF5, the PCIC does not respond to the PCI command. Address space 1 is, like address space 0, controlled by the PCICONF6, PCILSR1, and PCILAR1. In this way, it is possible to set two address spaces. In systems with two or less local bus areas that can be accessed from the PCI bus, separate address spaces can be allocated to each of them. To make it possible to access three or more areas from the PCI bus, set the address spaces so that multiple areas are covered. In this case, we can assume that the address space includes areas for which no memory is installed. Note that, in this case, it is not possible to disable target transfers to areas for which no memory is installed. I/O-Read and I/O-Write Commands: The local registers of the PCIC are accessed by means of a target transfer triggered by an I/O-read or I/O-write command. In the SH7751, accessing the local registers by means of I/O transfer is made possible by setting a base address that specifies 1 Mbyte 1 of I/O space* in PCI configuration register 4 (PCICONF4). In the SH7751R, a base address that specifies 256 bytes of I/O space should be set. I/O-read and I/O-write commands only supports single transfers. The values of the byte-enable signals (
 [3:0]) are ignored, and longword accesses are carried out inside the PCIC. When executing an I/O-read and I/O-write commands transfer, specify B'0000 as the
 [3:0] value. Note that some of the local registers are not accessible from the PCI bus. For details, see section 22.2, PCIC Register Descriptions. Configuration-Read and Configuration-Write Commands: When the PCIC operates as a nonhost device, the configuration registers of the PCIC are accessed by using configuration-read and configuration-write commands. Configuration access only supports single transfers. In the SH7751, the values of the byte-enable 2 signals (
 [3:0]) are ignored, and longword accesses are carried out inside the PCIC* . In the SH7751R, the values of
 are enabled. When executing a configuration-write operation, specify B'0000 as the
 [3:0] value. Rev. 3.0, 04/02, page 890 of 1064 Notes: *1 In the SH7751, this is not compliant with version 2.1 of the PCI specifications, in which the I/O space for PCI devices is defined as being no more than 256 bytes. When the SH7751 is used in a PCI non-host device, such as on a PCI card, it may be recognized as a device that cannot be used during device configuration, because it requires an I/O space that is larger than 256 bytes. *2 In the SH7751, this is not compliant with version 2.1 of the PCI specifications, which states that any combination of the byte-enable signals (
 [3:0]) is possible when accepting a configuration access. For this reason, when access in units of bytes or words is specified by the combination of
 [3:0], the whole longword unit is overwritten by the write operation. Locked Transfer: Locked transfers are supported, but the locked space becomes the whole memory of the PCIC in the case of memory transfers, and becomes the whole register space in the case of I/O transfers or configuration transfers. While the memory is locked, retry is returned for all memory accesses of the PCIC from other PCI devices. Register access is, however, accepted. Similarly, while the registers are locked, retry is returned for all I/O accesses or configuration accesses of the PCIC from another PCI device, but memory access is accepted. 22.3.9 DMA Transfers DMA transfers allow the high-speed transfer of data between devices connected to the local bus and PCI bus when the PCIC has bus privileges as master. The following commands are supported in the case of DMA transfers:
Memory read, memory write, I/O read, and I/O write (Locked transfers are not supported.) (High-speed back-to-back transfers are not supported.) There are four DMA channels. In each channel, a maximum of 64MB can be set for each transfer, the number of transfer bytes and the starting address for the transfer being set at a longword boundary. In DMA transfers, all transferred data is handled in long word units, so the number of transfer bytes and the low 2 bits of the transfer initial address are ignored and B'0000 is always output for
. Also, in DMA transfers, because burst transfers are effected using linear addressing, the low 2 bits of the output PCI address are always B'00. Note that locked transfers are not supported in the case of DMA transfers. Rev. 3.0, 04/02, page 891 of 1064 Starting DMA Transfer: The following registers exist to control DMA transfers: DMA transfer arbitration register (PCIDMABT) and, for four channels, the DMA transfer PCI address register [3:0] (PCIDPA [3:0]), DMA transfer local bus starting address register [3:0] (PCIDLA [3:0]), DMA transfer count register [3:0] (PCIDTC [3:0]), and DMA control register [3:0] (PCIDCR [3:0]). Set the arbitration mode in PCIDMABT prior to starting the DMA transfer. Also select the DMA channel to be used, set the PCI bus starting address and local bus starting address in the appropriate PCIDPA and PCIDLA for the selected channel, respectively, set the number of bytes in the transfer in PCIDTC, set the DMA transfer mode in the PCIDCR, and specify a transfer start request. The transfer starting address and the number of bytes in the transfer can be set on byte or word boundaries, but because the least significant two bits of these registers are ignored, the transfer is performed in longword units. Also, note that the local bus starting address set in PCIDLA is the physical address. PCIDPA, PCIDLA, and PCIDTC are updated during data transfer. If another DMA transfer is to be performed on completion of one DMA transfer, new values must be set in these registers. The registers controlling DMA transfers can be set from both CPU and PCI device. Note that the DMA channel allocated to the CPU and PCI device must be predetermined when configuring the system. When performing DMA transfers, the address of the local bus and the size of data to be transferred can be set to a 32-byte boundary to ensure that data transfers on the local bus are as efficient as possible. PCIDCR can be used to control the abortion of DMA transfers, the direction of DMA transfers, to select PCI commands (memory/I/O) whether to update the PCI address, whether to update the local address, whether to use transfer termination interrupts, and, when the local bus is big endian, the method of alignment. Figure 22.5 shows an example of DMA transfer control register settings. Rev. 3.0, 04/02, page 892 of 1064 31 1 0 0: Fixed priority 1: Pseudo round-robin Arbitration mode PCIDMABT H'0000 0000 H'0000 0004 31 28 0 PCIDLA Local address . . . . External memory space Area 0: H'00000000 to H'03FFFFFF Area 1: H'04000000 to H'07FFFFFF Area 2: H'0800 0000 to H'0BFFFFFF Area 3: H'0C000000 to H'0FFFFFFF Area 4: H'10000000 to H'13FFFFFF Area 5: H'14000000 to H'17FFFFFF . . . H'1BFF FFFC Area 6: H'18000000 to H'1BFFFFFF 32 bits 31 26 25 0 DMA transfer PCIDTC Transfer count PCI memory/ I/O space H'0000 0000 H'0000 0004 H'0000 000C . . . 31 0 PCIDPA PCI address . . . H'FFFF FFFC 32 bits 31 PCIDCR 11 10 0 Transfer control Figure 22.5 Example of DMA Transfer Control Register Settings Rev. 3.0, 04/02, page 893 of 1064 DMA Transfer End: The following describes the status on termination of a DMA transfer.
Normal termination DMA transfer ends after the set number of bytes has been transferred. In the case of normal termination, the DMA end status bit (DMAST) of the PCIDCR and the DMA transfer start control bit (DMASTART) are cleared, and the DMA transfer termination interrupt status bit (DMAIS) is set. If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination interrupt is issued. Note that the DMAIS bit is set even if the DMAIM bit is set to 0. The DMAIS bit is maintained until it is cleared. Therefore, the DMAIS bit must be cleared before starting the next DMA transfer.
Abnormal termination The DMA transfer may terminate abnormally if an error on the PCI bus is detected during data transfer or the DMA transfer is forcibly terminated.  Error in data transfer When an error occurs during DMA transfer, the DMA transfer is forcibly terminated on the channel in which the error occurred. There is no effect on data transfers on other channels.  Forced termination of DMA transfer When the PCIDCR and DMASTOP bits for a channel are set, data transfer on that channel is forcibly terminated. However, when the DMASTOP bit is set, do not write 1 to the DMASTRT bit. Also, in control bits other than the DMASTOP bit, write the value at the time of transfer started. In the case of an abnormal termination, the DMA termination status bit (DMAST) in the PCIDCR is set when the cause of that abnormal termination (error detection or forced termination of DMA transfer) occurs. After the data transfer terminates, the DMA transfer start control bit (DMASTART) is cleared and the DMA transfer termination interrupt status bit (DMAIS) is set. If the DMA transfer interrupt mask bit (DMAIM) is set to 1, the DMA transfer termination interrupt is issued. In the event of an abnormal termination, the transferred data is not guaranteed. Figure 22.6 shows an example of DMA transfer flowchart. Rev. 3.0, 04/02, page 894 of 1064 DMA transfer start DMA transfer starts when 1 is set in the DMASTRT bit of the PCIDCR register. DMA transfer (⇔ FIFO) Transfer address update The PCIDPA and PCIDLA registers are updated (increment/fixed) by the LAHOLD bit of the PCIDCR register. Transfer count decrement The PCIDTC decrements at a rate equaling the number of transfer bytes (4 bytes). Is transfer error detected? Yes No DMASTOP = 1? No Yes Yes DMA transfer is forcibly stopped when 1 is set in the DMASTOP bit of the PCIDCR register. (Do not set 1 in the DMASTRT bit at the same time.) PCIDTC > 0? No DMAST = 0 DMAST = 1 Normal ending Abnormal ending After DMA transfer completion, the DMASTRT bit of the PCIDCR register is cleared to 0, and the DMAIS bit of the PCIDCR register is set to 1. Figure 22.6 Example of DMA Transfer Flowchart
Termination by software reset When the RSTCTL bit of the PCICR is asserted, the PCIC is reset and DMA transfers are forcibly terminated. Note, however, that when transfers are terminated by a software reset, the PCIDCR is also reset and the DMA transfer control registers are all cleared. Rev. 3.0, 04/02, page 895 of 1064 DMA Arbitration: If transfer requests are made simultaneously on multiple DMA channels in the PCI, transfer arbitration is required. There are two modes that can be selected to determine order of priority of the DMA transfers on the four channels: fixed order of priority and pseudo roundrobin. The mode is selected using the DMABT bit of the PCI's DMA transfer arbitration register (PCIDMABT). For arbitration to be performed in such a way as to maintain high-speed data transfer, there are 4 FIFOs (32-byte  2 buffer structure) for the four DMA transfer channels. The FIFOs have a 2buffer structure, enabling one buffer to be accessed from the PCI bus while the other is being accessed from the local bus. Depending on the direction of the transfer, the input port of the FIFO for DMA transfers. Transfers are possible in both directions between the local bus and PCI bus by selecting the transfer direction. The arbitration circuit monitors the data transfer requests (data write requests to the FIFO when the FIFO is empty and read requests from the FIFO when it is full) 4 DMA transfer channels to control the data transfers. If a DMA transfer request occurs at the same time as a PIO transfer request, the PIO transfer takes precedence over transfers on the four DMA channels, regardless of the specified mode of DMA transfer priority order. Fixed Priority Mode (DMABT = 0): In fixed priority mode, the order of priority of data transfer requests is fixed and cannot be changed. The order is as follows: Channel 0 DMA transfer > channel 1 DMA transfer > channel 2 DMA transfer > channel 3 DMA transfer DMA transfer on channel 0. Take the highest priority and channel 3 DMA transfers take the lowest priority. When data transfer requests occur simultaneously, the data transfer with the highest priority takes precedence. Let's look at data transfers from the local bus to the PCI bus in fixed priority mode. The arbitration circuit monitors the transfer requests from the respective data transfer control circuits and writes data read from the local bus to the data transfer FIFO that not only is empty but also has the highest priority. On the other hand, it checks if transfer data exists in the respective FIFOs and reads that data from the data transfer FIFO in which there is data and which has the highest priority, and outputs that data to the PCI bus. For example, if channel 1 FIFO is empty, the arbitration circuit writes the data from the local bus into the channel 1 FIFO. Next, if data of 32bytes or more is in the channel 1 FIFO, it outputs that data to the PCI bus. Rev. 3.0, 04/02, page 896 of 1064 If data has been written to both buffers of the channel 1 FIFO, the channel 1 FIFO is busy while data is output from one of those buffers to the PCI bus. While it is busy, data is written from the local bus to the channel 2 FIFO, which has the next highest order of priority. When all data has been output from the channel 1 FIFO to the PCI bus, data is output from the channel 2 FIFO, which still contains data, to the PCI bus. Thus, in fixed priority mode, execution alternates between the two data transfers with the highest priority. That is, if DMA transfers are performed simultaneously on 4 channels, the data transfers start with alternation between channels 1 and 2 and then move to alternating between 2 and 3 when all the data in channel 1 has been transferred. Likewise, execution moves to alternation between channels 3 and 4 on completion of channel 2. This pattern is the same when data is transferred from the PCI bus to the local bus. Pseudo round-robin mode (DMABT = 1): In pseudo round-robin mode, as each time data is transferred, the order of priority is changed so that the priority level of the completed data transfer becomes the lowest. Regarding pseudo round-robin mode operations, refer to section 22.3.5, Host Functions. 22.3.10 Transfer Contention within PCIC No contention occurs in the PCIC in the case of PIO transfer requests from the CPU and memory reads/memory writes due to target transfers. This is because PIO transfers use an internal bus for peripheral modules, and this operates independently of the local bus that has memory accessed by external PCI devices. Contention can occur in the PCIC in the case of PIO transfer requests from the CPU and IO reads/IO writes due to target transfers (PCIC local register access). In this case, however, arbitration is performed in the PCIC such that priority is given to register access by the external PCI device that has the PCI bus rights. Rev. 3.0, 04/02, page 897 of 1064 22.3.11 PCI Bus Basic Interface The PCI interface of this LSI conforms to the PCI version 2.1 stipulations and can be connected to a device with a PCI bus interface. While the PCIC is set in host mode, or while set in non-host mode, operation differs according to whether or not bus parking is performed, and whether or not the PCI bus arbiter function is enabled or not. In host mode, the AD, PAR, C/
 signal lines are driven by the PCIC when transfers are not being performed on the PCI bus (bus parking). When the PCIC subsequently starts transfers as master, these signal lines continue to be driven until the end of the address phase. However, in non-host mode, the master performing parking is determined according to the GNT output by the external arbiter. When the master performing parking is not the same master as that starting the subsequent transfer, a high impedance state of at least one clock is generated prior to the address phase. In host mode, the arbiters in the PCICs and the REQ and GNT between PCICs are connected internally. Here, pins / , /MD9, /MD10, and  function as the REQ inputs from the external masters 1 to 4. Similarly,  /  ,  ,  , and   function as the GNT outputs to external masters 1 to 4. Including the PCIC, arbitration of up to five masters is possible. In non-host mode, pins /  functions as the GNT input of the PCIC, while  /  functions as the REQ output of the PCIC. Master Read/Write Cycle Timing: Figures 22.7 is an example of a single-write cycle in host mode. Figure 22.8 is an example of a single read cycle in host mode. Figure 22.9 is an example of a burst write cycle in non-host mode. And Figure 22.10 is an example of a burst read cycle in nonhost mode. Note that the response speed of  and  differs according to the connected target device. In PIO transfers, always use single read/write cycles. The issuing of configuration transfers is only possible in host mode. LOCK transfers are possible only using PIO transfers. Rev. 3.0, 04/02, page 898 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ DP0 BE0 LOCKed IDSEL / – / – , , Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.7 Master Write Cycle in Host Mode (Single) Rev. 3.0, 04/02, page 899 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ DPn BE0 LOCKed IDSEL / – / – , , Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.8 Master Read Cycle in Host Mode (Single) Rev. 3.0, 04/02, page 900 of 1064 PCICLK Addr AD31–AD0 PAR C/ Com –C/ D0 D1 Dn AP DP0 DPn-1 BE0 BE1 BEn APn IDSEL / / Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) Rev. 3.0, 04/02, page 901 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ BE0 D1 Dn DP0 DPn-1 BE1 DPn BEn IDSEL / / Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) Rev. 3.0, 04/02, page 902 of 1064 Target Read/Write Cycle Timing: The PCIC responds to target memory read accesses from an external master by retries until 8 longword data are prepared in the PCIC's internal FIFO. That is, it always responds to the first target read with a retry. Also, if a target memory write access is made, the PCIC responds to all subsequent target memory accesses with a retry until the write data is completely written to local memory. Thus, the content of the data is guaranteed when data written to the target is immediately subject to a target read operation. The following restrictions apply to the SH7751. In a system in which access is made to the same address in local memory by two or more PCI devices, the data cannot be guaranteed when a target read is performed immediately after a target write. The possibility of an error occurs when the target read immediately after the target write gets bus privileges at the point the data is ready for a target read by a different PCI device prior to the target write. In this case, the data prior to the target write is read. If such transfers are likely to occur, implement either (a) or (b) below. (a) If using the data that has been read, perform two read operations and use only the data from the second read operation. (b) If not using the data that has been read (if you are performing the read operation in order to determine the timing for actually writing data to the destination), be sure that the read address* immediately after writing is different from the write address. Note: * The address that does not correspond to the address AD[31:2] on a longword boundary. With the SH7751R, in the following case the values of data are discarded for a target read that is executed immediately after a target write because the data read in an earlier read operation that was carried out by a different PCI device are discarded. Only single transfers are supported in the case of target accesses of the configuration space and I/O space. If there is a burst access request, the external master is disconnected on completion of the first transfer. Note that the  response speed is fixed at 2 clocks (Medium) in the case of target access of the PCIC. Figure 22.11 shows an example target single read cycle in non-host mode. Figure 22.12 shows an example target single write cycle in non-host mode. Figure 22.13 is an example of a target burst read cycle in host mode. And Figure 22.14 is an example target burst write cycle in host mode. Rev. 3.0, 04/02, page 903 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ DP0 BE0 Disconnect LOCKed IDSEL At Config Access / / Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.11 Target Read Cycle in Non-Host Mode (Single) Rev. 3.0, 04/02, page 904 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ DP0 BE0 Disconnect LOCKed IDSEL At Config Access / / Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.12 Target Write Cycle in Non-Host Mode (Single) Rev. 3.0, 04/02, page 905 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ BE0 D1 Dn DP0 DPn-1 BE1 BEn DPn Disconnect LOCKed IDSEL Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.13 Target Memory Read Cycle in Host Mode (Burst) Rev. 3.0, 04/02, page 906 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ Com –C/ D1 D0 DP0 BE0 Dn DPn-1 BE1 DPn BEn Disconnect LOCKed IDSEL Addr: Dn: AP: DPn: Com: BEn: PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.14 Target Memory Write Cycle in Host Mode (Burst) Rev. 3.0, 04/02, page 907 of 1064 Address/Data Stepping Timing: By writing 1 to the WCC bit (bit 7 of the PCICONF1), a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the stipulated logic level in one clock. When the PCIC operates as the host, it is recommended to use this function for the issuance of configuration transfers. Figure 22.15 is an example of burst memory write cycle with stepping. Figure 22.16 is an example of target burst read cycle with stepping. PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ Addr: Dn: AP: DPn: Com: BEn: Dn DP0 BE0 DPn-1 DPn BEn PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, With Stepping) Rev. 3.0, 04/02, page 908 of 1064 PCICLK Addr AD31–AD0 AP PAR C/ D0 Com –C/ Addr: Dn: AP: DPn: Com: BEn: Dn DP0 BE0 DPn-1 DPn BEn PCI space address nth data Address parity nth data parity Command nth data byte enable Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping) Rev. 3.0, 04/02, page 909 of 1064 22.4 Endians 22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules The internal bus (peripheral bus) for the peripheral modules that write data from CPU to the PCIC registers operates in big endians. On the other hand, PCI bus operates in little endian. Therefore, big/little endian conversion is required in PIO transfer, as shown in figure 22.17. The PCIC supports two endian conversion modes, the BYTESWAP bit of the PCI control register (PCICR) switching between these modes. PCI bus Peripheral bus 32 bits Big → little 32 bits 32 bits 32 bits Little → big Big endian Little endian Figure 22.17 Endian Conversion Modes for Peripheral Bus 1. Byte data boundary mode: Big/little endian conversion is performed on the assumption that all data is on byte boundaries. (BYTESWAP = 1) 2. Word/longword (W/LW) boundary mode: Big/little endian conversion is performed according to the size of data accessed. (BYTESWAP = 0) Table 22.10 shows the access sizes supported by the conversion modes at the destination of peripheral bus access. The local registers in the PCIC are always accessed in the word/longword boundary mode regardless of the transfer mode. Figure 22.18 shows the data alignment between peripheral bus and PCI bus in each boundary mode. Rev. 3.0, 04/02, page 910 of 1064 Table 22.10 Access Size Transfer Mode Access Destination Access Size W/LW Boundary Mode Byte Data Boundary Mode PCI external device B, W, LW Yes Yes Memory space I/O space B, W, LW Yes Yes Configuration register LW Yes Yes LW Yes W/LW boundary mode PCIC register Notes: B: Byte W: Word LW: Longword Memory/I/O space access (Peripheral bus ↔ PCI bus) Peripheral bus Size Address Data 31 4n+0 4n+1 PCI bus 0 Data (W/LW boundary mode) Data (Byte data boundary mode) 31 31 0 0 B0 B0 B1 Address (memory I/O) B0 B1 B1 4n+0/4n+0 1110 4n+0/4n+1 1101 4n+0/4n+2 1011 4n+0/4n+3 0111 4n+0/4n+0 1100 Byte 4n+2 B2 4n+3 4n+0 B2 B3 B2 B3 B0 B1 B3 B0 B1 B1 B0 Word Long Word 4n+2 B2 B3 4n+0 B0 B1 B2 B3 B2 B3 B3 B2 4n+0/4n+2 0011 B0 B1 B2 B3 B3 B2 B1 B0 4n+0/4n+0 0000 Figure 22.18 Peripheral Bus  PCI Bus Data Alignment Rev. 3.0, 04/02, page 911 of 1064 22.4.2 Endian Control for Local Bus Big and little endians are supported on the local bus, determined at power-on reset by the external endian specification pin (MD5). Therefore, when transferring data between the local bus and the PCI bus, when the local bus is set for big endian, big/little endian conversion is therefore required. Figure 22.19 shows the block diagram of the local bus endian control. An endian conversion circuit is provided between the local bus and the FIFO. For details of the endian control, refer to section 22.4.3, Endian Control in DMA Transfers, and section 22.4.4, Endian Control in Target Transfers (Memory Read/Memory Write). Local bus FIFO 32 bits LW DMA Big/little → little LW PCI bus 32 bits Target RD FIFO 32 bits Little → big/little LW B, W, LW DMA 32 bits Targer WT Big/little endian Little endian Figure 22.19 Endian Control for Local Bus 22.4.3 Endian Control in DMA Transfers Although only the longword access size is supported in DMA transfers (see table 22.11), the endian conversion mode can be selected from the following four types depending on whether the longword data consists of four byte data units or two word data units. The conversion mode can be switched by the setting of bits 10 and 9 (ALNMD) of the DMA control registers (PCIDCR0 to 3) for PCI. 1. Byte data boundary mode: Big/little endian conversion is performed on the assumption that all data is on a byte boundary. (ALNMD = b'00) 2. Word/longword (W/LW) boundary mode 1: Longword data is transferred as byte data x 4. (ALNMD = b'01) 3. Word/longword (W/LW) boundary mode 2: Longword data is transferred as word data x 2. (ALNMD = b'10) 4. Word/longword (W/LW) boundary mode 3: Longword data is transferred as longword data x 1. (ALNMD = b'11) Rev. 3.0, 04/02, page 912 of 1064 Only longword access size is supported in the case of DMA transfers. Figure 22.20 shows the data alignment in the respective boundary modes in DMA transfers. Table 22.11 DMA Transfer Access Size and Endian Conversion Mode Endian Conversion Mode Local Bus Endian Data Transfer Direction Access Size W/LW Boundary Mode (1 to 3) Byte Data Boundary Mode Big endian Local bus  PCI bus LW Yes Yes Little endian Local bus  PCI bus LW Conversion not required Conversion not required When local bus is big endian Local bus PCI bus Byte data boundary mode Size = LW 31 0 B0 B1 B2 B3 31 0 B3 B2 B1 B0 W/LW W/LW W/LW boundary mode 1 boundary mode 2 boundary mode 3 31 0 B3 B2 B1 B0 31 0 B2 B3 B0 B1 31 0 B0 B1 B2 B3 = 0000 When local bus is little endian Local bus Size = LW 31 PCI bus 0 B3 B2 B1 B0 31 0 B3 B2 B1 B0 = 0000 Figure 22.20 Data Alignment at DMA Transfer Rev. 3.0, 04/02, page 913 of 1064 22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) In target transfers, for memory read and memory write that perform data transfer between the local bus and the PCI bus, big/little endian conversion is required in the same way as for DMA transfers when the local bus is set for big endians. Word/longword boundary modes are not supported in the case of target transfers. As shown in table 22.12, the byte data boundary mode is used, instead of ALNMD, for all transfers. The access sizes supported in the case of target transfers are as follows: For target reads (local bus to PCI bus), longword only. For target writes (PCI bus to local bus), longword/word/byte. In target write operations, the byte, word and longword data in the PCIC are transferred to the local bus in one or two transfer operations depending on the type of the byte enable signal of the PCI bus. For example, when C/
 = b'1010, byte access to the local bus is generated twice. When C/
 = b'1000, byte access and word access are each generated once. Table 22.12 Target Transfer Access Size and Endian Conversion Mode Endian Conversion Mode Local Bus Endian Data Transfer Direction Access Size W/LW Boundary Mode (1 to 3) Byte Data Boundary Mode Big endian Target read LW No Yes Target write B, W, LW No Yes Target read LW Target write B, W, LW Conversion not required Conversion not required Little endian Rev. 3.0, 04/02, page 914 of 1064 Target memory read transfers (local bus → PCI bus) when local bus is big endian Local bus Size 31 LW PCI bus 0 31 B0 B1 B2 B3 BE 0 B3 B2 B1 B0 H'0 to H'F Target memory write transfers (local bus ← PCI bus) when local bus is big endian Size Local bus 31 B B1 B B+B 0111 B3 B0 B1 W 1011 B2 B3 B1 B0 B2 B3 B0 B1 B0 B2 B2 + B3 B3 + B3 B3 1100 0011 B3 B2 + 1110 1101 B1 B2 B+B BE 0 B0 B B+B 31 B0 B W PCI bus 0 B0 1010 0101 B1 B0 0110 B+B B1 + B2 B2 B1 1001 W+B B0 B1 + B2 B2 B1 B0 1000 W+B B0 B1 + B3 B1 B0 0100 B+W B0 + B2 B3 B3 B2 B0 0010 + B2 B3 B3 B2 B1 B+W B1 — — LW B0 B1 B2 B3 B3 0001 1111 B3 B2 B1 B0 0000 Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) Rev. 3.0, 04/02, page 915 of 1064 Target memory read transfers (local bus → PCI bus) when local bus is little endian Local bus Size 31 LW PCI bus 0 31 B3 B2 B1 B0 BE 0 B3 B2 B1 B0 H'0 to H'F Target memory write transfers (local bus ← PCI bus) when local bus is little endian Size Local bus 31 B B0 1011 B2 B3 0111 B3 B1 B0 B1 B0 B3 B2 B0 + B1 B+B B2 B2 + B3 B3 B0 + B3 B3 1100 0011 B3 B2 B+B 1110 1101 B1 B2 W B+B BE 0 B1 B W 31 B0 B B PCI bus 0 B0 1010 0101 B1 B0 0110 B+B B1 + B2 B2 B1 1001 W+B B1 B0 + B2 B2 B1 B0 1000 W+B B1 B0 + B3 B1 B0 0100 B0 0010 B+W B+W B0 + B3 B2 B1 — — LW B3 B2 B1 B0 + B3 B2 B3 B3 B2 B3 B2 B1 0001 1111 B3 B2 B1 B0 0000 Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus) Rev. 3.0, 04/02, page 916 of 1064 22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write) The access size is fixed at longword when accessing the PCIC local register using I/O read or I/O write commands. Addresses are specified using 4-byte boundaries, and BE[3:0] is specified as B'0000. The data alignment in target transfers (I/O read and I/O write) is shown in figure 22.22. Target I/O read transfer data alignment (local register Size Address Local register 31 LW 4n PCI bus 0 B3 B2 B1 B0 Target I/O write transfer data alignment (PCI bus Size Address 4n 31 BE 0 B3 B2 B1 B0 PCI bus 0 B3 B2 B1 B0 H’0000 local register) Local register 31 LW PCI bus) 31 BE 0 B3 B2 B1 B0 H’0000 Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) 22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write) The data alignment when accessing the PCIC configuration register using the target configuration read and configuration write commands is shown in figure 22.23. In the SH7751 the access size is fixed at longword. The BE[3:0] value is ignored. In the SH7751R all BE combinations are valid. Rev. 3.0, 04/02, page 917 of 1064 Target configuration read transfer data alignment (configuration register Configuration register 31 0 B3 B2 B1 B0 PCI bus 31 BE 0 H’0 to H’F B3 B2 B1 B0 SH7751 target configuration write transfer data alignment (PCI bus Configuration register 31 0 B3 B2 B1 B0 PCI bus 31 B3 B2 B1 B0 31 0 B3 B2 B1 31 B0 31 0 B3 B2 0 B1 B0 31 0 B3 B1 B0 31 0 B3 B1 31 31 B0 31 0 B3 B3 B2 B1 B0 31 31 0001 0 B3 B2 B0 31 0 31 0011 0 B3 B1 B0 31 0 31 B1 B0 31 B2 0101 B1 31 0 B3 B0 31 31 0111 0 B2 B1 B0 31 0 1001 0 B2 B0 31 0 1011 31 B1 B0 31 0 0 B1 B0 31 B1 0 31 0 1101 0 B0 31 1100 0 B1 B0 1010 0 B2 31 1000 0 31 B2 0110 0 31 B0 0100 0 B2 B1 0 0100 0 B3 B2 B1 0010 0 31 B2 B1 B0 0000 0 B3 31 31 BE 0 B3 0 B3 31 configuration register) PCI bus B3 B2 31 B3 H’0 to H’F B3 B2 B1 0 B3 B2 BE B3 B2 B1 B0 Configuration register 0 configuration register) 0 SH7751R target configuration transfer data alignment (PCI bus 31 PCI bus) 1110 0 1111 Figure 22.23 Data Alignment at Target Configuration Transfer (Both Big Endian and Little Endian) Rev. 3.0, 04/02, page 918 of 1064 22.5 Resetting This section describes the resetting supported by the PCIC. Power-On Reset when Host: A reset ( ) can be output to the PCI bus when the PCIC is host. The  pin is asserted when a power-on reset is generated at the  pin or when a software reset is generated by setting 1 in the  output control bit (RSTCTL) of the PCI control register (PCICR). Reset Input in Non-Host Mode: The PCIC has no dedicated reset input pin. A reset signal from the PCI bus can be connected to the  pin and a power-on reset applied to the SH7751/SH7751R, but the following point must be noted: In the PCI standard, the reset (  signal must be asserted for a minimum of 1msec, check the time required for the power-on reset of the SH7751/SH7751R (see section 23, Electrical Characteristics), and design the timing of power-on resets so that it satisfies the conditions of the reset period for both. Manual Reset: The PCIC does not support the input of manual reset signals via the  pin. No initialization therefore occurs by manual resets. Software Reset: Software resets are generated by setting 1 in the  output control bit (RSTCTL) of the PCI control register (PCICR). The  pin is asserted at the same time as the PCIC is reset. While a software reset is asserted, the PCIC registers cannot be accessed. Assertion requires a minimum of 1ms. Software resets are canceled by setting a 0 to the RSTCTL bit. It is not possible to set 0 in the RSTCTL bit and set other bits of the PCICR at the same time. After setting 0 in the RSTCTL bit, set other bits of the PCICR. Note that not all PCIC registers are reset at a software reset. See section 22.2, PCIC Register Descriptions, for details of which registers are reset. Use software clears as required for any registers that are not cleared by the software reset. Note that, since software resets cannot be asserted while the PCI bus clock is stopped, software resets must be asserted when the PCI bus clock (PCICLK or CKIO) is being input. Note that data cannot be guaranteed if a software reset is used while a data transfer is in progress. Rev. 3.0, 04/02, page 919 of 1064 22.6 Interrupts 22.6.1 Interrupts from PCIC to CPU There are 8 interrupts, as shown in the following, that can be generated by the PCIC for the CPU. The interrupt controller also controls the individual interrupt priority levels and interrupt masks, etc. See the section 19, Interrupt Controller (INTC), for details. Table 22.13 Interrupts Interrupt Source Function INTPRI00 PCISERR SERR error interrupt [3:0] PCIERR ERR error interrupt [7:4] PCIPWDWN Power-down request interrupt PCIPWON Power-on request interrupt PCIDMA0 DMA0 transfer end interrupt PCIDMA1 DMA1 transfer end interrupt PCIDMA2 DMA2 transfer end interrupt PCIDMA3 DMA3 transfer end interrupt Priority High High Low Low System Error () Interrupt (PCISERR): This interrupt shows detection of the  pin being asserted. This interrupt is generated only when the PCIC is operating as host. When the PCIC is operating as non-host, the SERR bit in the PCI control register (PCICR) is used to notify the host device of the system error (assertion of  pin). The  pin can be asserted when the SERR bit is asserted and when an address parity error is detected in a target transfer. When the SER bit of the PCI configuration register 1 (PCICONF1) is set to 0, the  pin is not asserted. Error Interrupt (PCIERR): Shows error detection by the PCIC. The error interrupt is asserted when either of the following errors is detected:
Interrupts detected by PCI interrupt register (PCIINT)
Interrupts detected by PCI arbiter interrupt register (PCIAINT) The interrupts that can be detected by these two registers can also be masked. The PCI interrupt mask register (PCIINTM) masks the PCIINT interrupts, and the PCI arbiter interrupt mask register (PCIAINTM) masks the PCIAINT interrupts. See section 22.2, PCIC Register Descriptions, for details. Rev. 3.0, 04/02, page 920 of 1064 The following are also set in relation to error interrupts: of the PCI configuration register 1 (PCICONF1), the parity error output status (DPE) the system error output status (SSE), the master abort reception status (RMA), the target abort reception status (RTA), the target abort execution status (STA) and the data parity status (DPD). DMA Channel 0 Transfer Termination Interrupt (PCIDMA0): The DMA termination interrupt status (DMAIS) bit of the DMA control register 0 (PCIDCR0) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 1 Transfer Termination Interrupt (PCIDMA1): The DMA termination interrupt status (DMAIS) bit of the DMA control register 1 (PCIDCR1) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 2 Transfer Termination Interrupt (PCIDMA2): The DMA termination interrupt status (DMAIS) bit of the DMA control register 2 (PCIDCR2) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. DMA Channel 3 Transfer Termination Interrupt (PCIDMA3): The DMA termination interrupt status (DMAIS) bit of the DMA control register 3 (PCIDCR3) is set. The interrupt mask is set by the DMA termination interrupt mask (DMAIM) bit of the same register. Power Management Interrupt (Transition Request to Normal Status) (PCIPWON): The power state D0 (PWRS_D0) bit of the PCI power management interrupt register (PCIPINT) is set. The power state D0 interrupt mask can be set using the power state D0 (PWRS_D0) bit of the PCI power management interrupt mask register (PCIPINTM). Power Management Interrupt (Transition Request to Power-Down Mode) (PCIPWDWN): The power state D3 (PWRS_D3) bit of the PCI power management interrupt register (PCIPINT) is set. The power state D3 interrupt mask can be set using the power state D3 (PWRS_D3) bit of the PCI power management interrupt mask register (PCIPINTM). 22.6.2 Interrupts from External PCI Devices To receive interrupt signals from external PCI devices, etc., while the PCIC is operating as the host device, use the  [3:0] pin. The PCIC has no dedicated external interrupt input pin. 22.6.3   When the PCIC is operating as a non-host device, the   output can be used for interrupts to the host device.   can be asserted (Low output)/negated (High output) using the   output soft control bit (INTA) of the PCI control register (PCICR).   is open collector output. Rev. 3.0, 04/02, page 921 of 1064 22.7 Error Detection The PCIC can store error information generated on the PCI bus. The address information (ALOG [31:0]) at the time of the error is stored in the PCI error address data register (PCIALR). The PCI error command information register (PCICLR) stores the type of transfer (MSTPIO, MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, TGT) at the time of the error, and the PCI command (CMDLOG [3:0]). When the PCIC is operating as host, the PCI error bus master information register (PCIBMLR) stores the bus master information (REQ4ID, REQ3ID, REQ2ID, REQ1ID, REQ0ID) at the time of the error. The error information storage circuit can only store information for one error. Therefore, when errors occur consecutively, no information is stored for the second or subsequent errors. Error information is cleared by resets. 22.8 PCIC Clock Three clocks are used with the PCIC. The peripheral module clock (P) is used for PCIC register access and PIO transfers. The bus clock (B) is used for local bus control. The PCI bus clock is used for PCI bus operation. The peripheral module clock and PCI bus clock do not need to be in sync, and there is no particular limit on the frequency ratio. However, in PIO transfers and when registers are being accessed, etc., circuits operating with the peripheral module clock and circuits operating with the PCI bus clock and circuits that synchronize both clocks are used, so the transfer speed depends on the frequency of the peripheral module clock as well. The bus clock (B) and PCI bus clock do not need to be in sync. However, the PCI bus clock should be set to the same frequency as the bus clock (B) or lower. The maximum PCI bus clock is 66 MHz. Either of the following can be selected using MD9 as the PCI bus clock: the CKIO feedback input clock and the clock input from the external input pin (PCICLK). External Input Pin (PCICLK) Operating Mode: In this mode the PCI bus clock is input from outside. This mode requires the provision of an external oscillation module for the PCI. CKIO Operating Mode: In this mode, the clock output from the CKIO pin is used as the PCI bus clock. The feedback input from the CKIO pin is used as the PCI bus clock. This mode can only be used when the PCIC is operating as the host bridge. It cannot be used in non-host mode. Rev. 3.0, 04/02, page 922 of 1064 When using this mode, note the CKIO load capacitance and only use it within the prescribed load stated in the manual. Note, too, that the clock frequency of CKIO cannot be guaranteed until the PLL oscillation stabilizes after a power-on reset or the clock frequency is changed. Also, in standby mode, the clock stops. This mode should only be employed after checking that these points do not cause any problems from the viewpoint of the system configuration. In CKIO operating mode, the maximum B frequency is 66 MHz. When not using the PCICLK pin, fix the pin level high. 66 MHz Compatibility: The PCIC is not necessarily fully compatible with the 66 MHz bus standard of the PCI. For details, see section 23, Electrical Characteristics. In the electrical characteristics of the PCI bus-related pins, the permissible delay on the board is extremely short. For this reason, the on-board load capacitance and impedance matching should be considered before connecting to a 66MHz-compatible PCI device. Note, too, that only one PCI device can be connected. In the PCI standard, there are two methods for checking if a PCI device can operate at 66 MHz: checking the 66 MHz operating status in the configuration register 1, and monitoring the 
pin in the PCI bus standard. The PCIC supports the 66 MHz operating status (66M) bit of the configuration register 1 (PCICONF1). The PCIC does not have a special pin for directly monitoring the 
pin. Also, there is no control output pin for switching between 33 MHz and 66 MHz when an external oscillator is used. A special external circuit is required to effect these controls. 22.9 Power Management 22.9.1 Power Management Overview The PCIC supports the PCI power management (version 1.0 compatible) configuration registers. These are as follows:
Support for the PCI power management control configuration register;
Support for the power-down/restore request interrupts from hosts on the PCI bus. There are three configuration registers for PCI power management control. PCI configuration register 13 shows the address offset (CAPPTR) of the configuration registers for power management. In the PCIC, this offset is fixed at CAPPTR = H'40. PCI configuration register 16 and PCI configuration register 17 are power management registers. They support two states: power state D0 (normal) and power state D3 (power down mode). The PCIC detects when the power state (PWRST) bit of the PCI configuration register 17 changes (when it is written to from an external PCI device), and issues a power management interrupt. To control the power management interrupts, there are a PCI power management interrupt register Rev. 3.0, 04/02, page 923 of 1064 (PCIPINT) and PCI power management interrupt mask register (PCIPINTM). Of the power management interrupts, the power state D3 (PWRS_D3) interrupt detects a transition from the power state D0 to D3, while power state D0 (PWRS_D0) interrupt detects a transition from the power state D3 to D0. Interrupt masks can be set for each interrupt. No power state D0 interrupt is generated at a power-on reset. The following cautions should be noted when the PCIC is operating in non-host mode and a power down interrupt is received from the host: In PCI power management (version 1.0 compatible), the PCI bus clock stops within a minimum of 16 clocks after the host device has instructed a transition to power state D3. After detecting a power state D3 (power down) interrupt, do not, therefore, attempt to read or write to local registers that can be accessed from the CPU and PCI bus. Because these registers operate using the PCI bus clock, the read/write cycle for these registers will not be completed if the clock stops. 22.9.2 Stopping the Clock Power savings can be achieved by stopping the bus clock used by the PCIC and the PCI bus clock. The PCI clock control register (PCICLKR) is provided for controlling the PCIC clock. Regarding the control register for stopping the peripheral module clock (PCLK) in the PCIC, refer to section 9, Power-Down Modes. The method of stopping the clock differs according to the operating mode of the PCI bus clock. See table 22.14. Rev. 3.0, 04/02, page 924 of 1064 Table 22.14 Method of Stopping Clock per Operating Mode PCIC Master Clock operating status Normal operation/ sleep SH (Other than PCIC) PCICLK Operation BCLK Operation PCICLK Operation BCLK Normal operation Normal operation Normal operation Normal operation PCLK Normal operation Normal operation Normal operation Normal operation PCICLK Not used Normal operation Not used Normal operation Stopped Stopped Stopped Stopped PCLK Normal operation Normal operation Normal operation Normal operation PCICLK Not used Normal operation Not used Normal operation BCLK Stopped Stopped Stopped Stopped PCLK Stopped Stopped Stopped Stopped PCICLK Not used Stopped Not used Stopped BCLK stopped from SH BCLK and PCICLK stopped from SH PCI command + interrupt (PCIC  SH) + BCLK restarted from SH Recovery Not used 1 PME interrupt (connected to IRL) + BCLK restarted from SH PME interrupt (connected to IRL) + BCLK and PCICLK restarted from SH PCI command + interrupt (PCIC  SH) + BCLK restarted from SH Recovery NMI, IRL, 2 and RESET on-chip peripheral interrupt NMI, IRL, RESET + BCLK restarted from SH NMI, IRL, RESET + BCLK and PCICLK restarted from SH NMI, IRL, RESET + BCLK restarted from SH + wait for PCI command (recovery) Deep sleep BCLK Standby Slave Transition/ Deep sleep Transition Sleep Recovery command Rev. 3.0, 04/02, page 925 of 1064 Table 22.14 Method of Stopping Clock per Operating Mode (cont) PCIC Master PCICLK Operation BCLK Operation PCICLK Operation Transition Standby command Standby command PCICLK stopped from SH + standby command PCI command + interrupt (PCIC  SH) + standby command Recovery Not used 1 PME interrupt (connected to IRL) PME interrupt (connected to IRL) + PCICLK restarted from SH Power-on reset Recovery NMI, IRL, 2 and RESET on-chip peripheral interrupt NMI, IRL, and RESET NMI, IRL, RESET + PCICLK restarted from SH NMI, IRL, RESET + wait for PCI command (recovery) SH (Other than PCIC) Transition/ Standby Recovery Slave Notes: Recovery 1: Recovery from PCI bus Recovery 2: Recovery from other than PCI bus External Input Pin (PCICLK) Operating Mode: The PCI bus clock can be stopped by writing 1 to the PCICLKSTOP bit. The bus clock can be stopped by writing 1 to the BCLKSTOP bit. It requires a minimum of 2 clocks of the PCI bus clock for the clock to actually stop after writing to PCICLKR (setting the PCICLKSTOP bit to 1). It takes a similar time for the clock to restart. Bus Clock (CKIO) Operating Mode: Both the PCI bus clock and bus clock can be stopped by writing 1 to the BCLKSTOP bit. It requires a minimum of 2 clocks of the bus clock for the clock to actually stop after writing to PCICLKR (setting the BCLKSTOP bit to 1). It takes a similar time for the clock to restart. While the PCI bus clock is stopped, it is not possible to access the local registers that can be accessed both from the peripheral module internal bus and from the PCI bus. Neither writing nor reading can be performed correctly. Also, the following cautions must be observed when stopping the bus clock and PCI bus clock while the PCI is in use: Rev. 3.0, 04/02, page 926 of 1064 
When operating as host device The clock must be stopped only after stopping the operation of external PCI devices connected to the PCI bus. If you stop the clock prior to stopping the external devices, access from those external devices will cause a hang-up. Stop the clock only after checking that there is no problem in respect to the system configuration. One method of stopping the operation of external PCI devices is to use the PCI power management, as discussed above. Stop the clock after switching the external PCI devices to power state D3 (power-down mode). In this case, all external PCI devices must support PCI power management.
When operating in non-host mode When operating in non-host mode, the PCI bus clock must be in external input operating mode (PCICLK). In this case, the host device is responsible for stopping and restarting the PCI bus clock, so it is not necessary to stop the clock using PCICLKR of the PCIC. Make sure that the CPU receives the interrupt in accordance with the power management sequence. 22.9.3 Compatibility with Standby and Sleep To stop all the PCIC's internal clocks, the SLEEP command must be used to transit to standby mode. When operating in external input pin (PCICLK) operating mode, set the PCICLKSTOP bit to 1 to stop the PCI bus clock, transit to standby, then, after recovering from standby, clear the PCICLKSTOP bit to 0 to prevent hazards occuring in the PCI bus clock. Note that the PCIC clock does not stop after transiting to sleep mode. When using the standby command in systems using the PCI bus, first check that the system does not hang up if the clock is stopped. 22.10 Port Functions When the PCIC is operating in non-host mode, the arbitration pin of the PCI bus can be used as a port. When using the host functions (arbitration), the port functions cannot be used. The following six pins can be used: , , 4,  ,  , and  . The three pins ! , and  can be used as I/O ports. The three pins  ,  , and   can be used as output ports. Data is output in synchronous with the bus clock (CKIO). Input data is fetched at the rising edge of the bus clock. Port control is performed by the port control register (PCIPCTR) and port data register (PCIPDTR). PCIPCTR controls the existence of the port function, the switching ON/OFF of the pull-up resistance, and the switching between input and output. PCIPDTR performs the input/output of port data. Rev. 3.0, 04/02, page 927 of 1064 22.11 Version Management The PCIC version management is written in the revision ID (8 bits) of the PCI configuration register 2 (PCICONF2). Rev. 3.0, 04/02, page 928 of 1064 Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings Item Symbol Value I/O, RTC, CPG power supply voltage V DDQ, VDD-RTC, VDD-CPG –0.3 to 4.2 VDD, VDD-PLL1/2 –0.3 to 2.5 Internal power supply voltage Unit V 2 –0.3 to 4.6* V 2 –0.3 to 2.1* Input voltage Vin –0.3 to VDDQ + 0.3 V Operating temperature Topr –20 to 75
C –40 to 85* Storage temperature Tstg 1 –55 to 125
C Notes: The LSI may be permanently damaged if the maximum ratings are exceeded. The LSI may be permanently damaged if any of the VSS pins are not connected to GND. For the powering-on and powering-off sequences, see Appendix G, Power-On and PowerOff Procedures. *1: HD6417751F167I and HD6417751BP167I only. *2: HD6417751R only. Rev. 3.0, 04/02, page 929 of 1064 23.2 DC Characteristics Table 23.2 DC Characteristics (HD6417751RBP240) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.4 1.5 1.6 — 255 660 Sleep mode — 140 180 Standby mode — — 400 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation IDD — — 800 — 100 145 Sleep mode — 60 115 Standby mode — — 400 Normal operation IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ — — 800 — 15 25 — 3 5 mA I
= 240 MHz A Ta = 25
C * Ta  50
C * mA I
= 240 MHz, B
= 120 MHz A Ta = 25
C * Ta  50
C * A VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 930 of 1064 — 1 1 RTC on * RTC off 2 1 1 Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). *2 To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 931 of 1064 Table 23.3 DC Characteristics (HD6417751RF240) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.4 1.5 1.6 — 255 660 Sleep mode — 140 180 Standby mode — — 400 — — 800 — 85 120 Sleep mode — 50 95 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 240 MHz A Ta = 25
C * Ta  50
C * I
= 240 MHz, B
= 80 MHz A Ta = 25
C * Ta  50
C * A VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 BRKACK, 
,   , CA Rev. 3.0, 04/02, page 932 of 1064 — 1 mA VDDQ  0.9 — VIH 1 RTC on* RTC off 2 1 1 Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 12 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). *2 To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 933 of 1064 Table 23.4 DC Characteristics (HD6417751RBP200) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.35 1.5 1.6 — 210 550 Sleep mode — 115 150 Standby mode — — 400 — — 800 — 85 120 Sleep mode — 50 95 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 200 MHz A Ta = 25
C * Ta  50
C * I
= 200 MHz, B
= 100 MHz A Ta = 25
C * Ta  50
C * A VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 BRKACK, 
,   , CA Rev. 3.0, 04/02, page 934 of 1064 — 1 mA VDDQ  0.9 — VIH 1 RTC on * RTC off 2 1 1 Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). *2 To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 935 of 1064 Table 23.5 DC Characteristics (HD6417751RF200) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, deep-sleep mode, standby mode 1.35 1.5 1.6 — 210 550 Sleep mode — 115 150 Standby mode — — 400 — — 800 — 85 120 Sleep mode — 50 95 Standby mode — — 400 — — 800 — 15 25 — 3 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, deep-sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 200 MHz A Ta = 25
C * Ta  50
C * I
= 200 MHz, B
= 67 MHz A Ta = 25
C * Ta  50
C * A VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 BRKACK, 
,   , CA Rev. 3.0, 04/02, page 936 of 1064 — 1 mA VDDQ  0.9 — VIH 1 RTC on * RTC off 2 1 1 Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 12 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. *1 RCR2.RTCEN must be set to 1 to reduce the leak current in the standby mode (There is no need to input a clock from EXTAL2). *2 To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 937 of 1064 Table 23.6 DC Characteristics (HD6417751BP167) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 167 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * mA I
= 167 MHz, B
= 84 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * A VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 938 of 1064 — RTC on RTC off Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 939 of 1064 Table 23.7 DC Characteristics (HD6417751BP167I) Ta = –40 to +85
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 167 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * mA I
= 167 MHz, B
= 84 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * A VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 940 of 1064 — RTC on RTC off Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 941 of 1064 Table 23.8 DC Characteristics (HD6417751F167) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 167 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * mA I
= 167 MHz, B
= 84 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * A VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 942 of 1064 — RTC on RTC off Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 943 of 1064 Table 23.9 DC Characteristics (HD6417751F167I) Ta = –40 to +85
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode 1.6 1.8 2.0 — 420 750 Sleep mode — 100 130 Standby mode — — 400 — — 800 — 70 100 Sleep mode — 40 80 Standby mode — — 400 — — 800 — — 25 — — 5 VDD-CPG VDD-RTC VDD Normal mode, sleep mode, standby mode VDD-PLL1/2 Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDD IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ mA I
= 167 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * mA I
= 167 MHz, B
= 84 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * A VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 944 of 1064 — RTC on RTC off Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 945 of 1064 Table 23.10 DC Characteristics (HD6417751VF133) Ta = –20 to +75
C Item Symbol Min Typ Max Unit Test Conditions Power supply voltage VDDQ VDD-CPG VDD-RTC 3.0 3.3 3.6 V Normal mode, sleep mode, standby mode VDD VDD-PLL1/2 1.4 1.5 1.6 IDD — 210 470 Sleep mode — 60 80 Standby mode — — 200 — — 300 — 35 80 Sleep mode — 20 65 Standby mode — — 200 — — 200 — — 25 — — Current dissipation Current dissipation Current dissipation Input voltage Normal operation Normal operation IDDQ Standby mode IDD-RTC
, NMI, 
, 
/ Normal mode, sleep mode, standby mode mA I = 133 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * mA I = 133 MHz, B = 67 MHz A Ta = 25
C (RTC on) * Ta > 50
C (RTC on) * A 5 VDDQ  0.9 — VDDQ + 0.3 V PCICLK VDDQ  0.6 — VDDQ + 0.3 Other PCI input pins VDDQ  0.5 — VDDQ + 0.3 Other input pins 2.0 VDDQ + 0.3 VIH BRKACK, 
,   , CA Rev. 3.0, 04/02, page 946 of 1064 — RTC on RTC off Item Input voltage Symbol Min Typ Max VIL –0.3 — VDDQ  0.1 V PCICLK –0.3 — VDDQ  0.2 Other PCI input pins –0.3 — VDDQ  0.3 Other input pins –0.3 — VDDQ  0.2
, NMI, 
, 
/ Unit Test Conditions BRKACK, 
,   , CA Input leak current All input pins |Iin| — — 1 A Vin = 0.5 to VDDQ –0.5 V Three-state leak current I/O, all output pins (off state) |Isti| — — 1 A Vin = 0.5 to VDDQ –0.5 V Output voltage PCI pins VOH 2.4 — — V VDDQ = 3.0 V, IOH = –4 mA 2.4 — — VDDQ = 3.0 V, IOH = –2 mA — — 0.55 VDDQ = 3.0 V, IOL = 4 mA — — 0.55 VDDQ = 3.0 V, IOL = 2 mA Other output pins PCI pins VOL Other output pins Pull-up resistance All pins Rpull 20 60 180 k Pin capacitance All pins CL — — 10 pF Notes: 1. Connect VDD-RTC, and VDD-CPG to VDDQ, VDD-PLL1/2 to VDD, and VSS-CPG, VSS-PLL1/2, and VSS-RTC to GND, regardless of whether or not the PLL circuits and RTC are used. 2. The current dissipation values are for VIH min = VDDQ – 0.5 V and VIL max = 0.5 V with all output pins unloaded. 3. IDD is the sum of the VDD and VDD-PLL1/2 currents. 4. IDDQ is the sum of the VDDQ, VDD-RTC, and VDD-CPG currents. * To reduce the leakage current in standby mode, the RTC must be turned on (RCR2.TRCEN = 1 and clock is input to EXTAL2). Rev. 3.0, 04/02, page 947 of 1064 Table 23.11 Permissible Output Currents Item Symbol Min Typ Max Unit Permissible output low current (per pin; other than PCI pins) IOL — — 2 mA Permissible output low current (per pin; PCI pins) IOL — — 4 Permissible output low current (total) IOL — — 120 Permissible output high current (per pin; other than PCI pins) –IOH — — 2 Permissible output high current (per pin; PCI pins) –IOH — — 4 Permissible output high current (total) (–IOH) — — 40 mA Note: To protect chip reliability, do not exceed the output current values in table 23.11. 23.3 AC Characteristics In principle, this LSI’s input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 23.12 Clock Timing (HD6417751RBP240) Item Operating frequency Symbol CPU, FPU, cache, TLB f Min Typ Max Unit MHz 1 — 240 External bus 1 — 84 Peripheral modules 1 — 60 Symbol Min Typ Max Unit f 1 — 240 MHz External bus 1 — 84 Peripheral modules 1 — 60 Notes Table 23.13 Clock Timing (HD6417751RF240) Item Operating frequency CPU, FPU, cache, TLB Rev. 3.0, 04/02, page 948 of 1064 Notes Table 23.14 Clock Timing (HD6417751RBP200) Item Operating frequency Symbol Min Typ Max Unit f 1 — 200 MHz External bus 1 — 100 Peripheral modules 1 — 50 Min Typ Max Unit MHz CPU, FPU, cache, TLB Notes Table 23.15 Clock Timing (HD6417751RF200) Item Operating frequency Symbol 1 — 200 External bus CPU, FPU, cache, TLB f 1 — 84 Peripheral modules 1 — 50 Notes Table 23.16 Clock Timing (HD6417751BP167(I), HD6417751F167(I)) Item Operating frequency Symbol Min Typ Max Unit f 1 — 167 MHz External bus 1 — 84 Peripheral modules 1 — 42 Min Typ Max Unit MHz CPU, FPU, cache, TLB Notes Table 23.17 Clock Timing (HD6417751VF133) Item Operating frequency Symbol 1 — 134 External bus CPU, FPU, cache, TLB f 1 — 67 Peripheral modules 1 — 34 Notes Rev. 3.0, 04/02, page 949 of 1064 23.3.1 Clock and Control Signal Timing Table 23.18 Clock and Control Signal Timing (HD6417751RBP240) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit fEX 16 34 MHz PLL1 12-times/PLL2 operation 14 20 PLL1/PLL2 not operating 1 34 PLL1 6-times/PLL2 operation Figure EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 120 MHz PLL1/PLL2 operating 1 34 MHz CKIO clock output cycle time tcyc 8.3 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 3 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 3 — ms 23.7 Standby return oscillation settling time 3 tOSC4 3 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5 PLL1/PLL2 not operating
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. Rev. 3.0, 04/02, page 950 of 1064 Table 23.19 Clock and Control Signal Timing (HD6417751RF240) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit fEX 16 34 MHz PLL1 12-times/PLL2 operation 16 20.0 PLL1/PLL2 not operating 1 34 PLL1 6-times/PLL2 operation Figure EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 fOP 25 84 MHz CKIO clock output PLL1/PLL2 operating 1 84 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 3 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 3 — ms 23.7 Standby return oscillation settling time 3 tOSC4 3 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5 PLL1/PLL2 not operating
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. Rev. 3.0, 04/02, page 951 of 1064 Table 23.20 Clock and Control Signal Timing (HD6417751RBP200) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit fEX 16 34 MHz PLL1 12-times/PLL2 operation 14 17 PLL1/PLL2 not operating 1 34 PLL1 6-times/PLL2 operation Figure EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 fOP 25 100 MHz CKIO clock output PLL1/PLL2 operating 1 34 MHz CKIO clock output cycle time tcyc 10 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 5 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5 PLL1/PLL2 not operating
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. Rev. 3.0, 04/02, page 952 of 1064 Table 23.21 Clock and Control Signal Timing (HD6417751RF200) VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF Item EXTAL clock input frequency Symbol Min Max Unit fEX 16 34 MHz PLL1 12-times/PLL2 operation 14 17 PLL1/PLL2 not operating 1 34 PLL1 6-times/PLL2 operation Figure EXTAL clock input cycle time tEXcyc 30 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output fOP 25 84 MHz PLL1/PLL2 operating 1 34 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 5 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 Standby return oscillation settling time 1* tOSC2 2 — ms Standby return oscillation settling time 2* tOSC3 2 — ms Standby return oscillation settling time 3* tOSC4 2 — ms IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5 PLL1/PLL2 not operating
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. * When the oscillation settling time of the crystal resonator is 1 ms or less. Rev. 3.0, 04/02, page 953 of 1064 Table 23.22 Clock and Control Signal Timing (HD6417751BP167, HD6417751F167, HD6417751BP167I, HD6417751F167I) HD6417751BP167, HD6417751F167: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75
C, CL = 30 pF HD6417751BP167I, HD6417751F167I: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –40 to 85
C, CL = 30 pF Item Symbol Min Max Unit 1/2 divider operating fEX 30 56 MHz 1/2 divider not operating fEX 15 28 fEX 2 56 fEX 1 28 EXTAL clock input cycle time tEXcyc 17.8 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock input rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output PLL2 operating fOP 30 84 MHz PLL2 not operating EXTAL clock input frequency PLL1/PLL2 operating PLL1/PLL2 1/2 divider not operating operating 1/2 divider not operating Figure fOP 1 84 MHz CKIO clock output cycle time tcyc 11.9 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 10 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 28 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. Rev. 3.0, 04/02, page 954 of 1064 Table 23.23 Clock and Control Signal Timing (HD6417751VF133) VDDQ = 3.0 to 3.6 V, VDD = typ. 1.5 V, Ta = –20 to +75
C, CL = 30 pF Item Symbol Min Max Unit 1/2 divider operating fEX 30 45 MHz 1/2 divider not operating fEX 15 23 fEX 2 45 fEX 1 23 EXTAL clock input cycle time tEXcyc 22.2 1000 ns 23.1 EXTAL clock input low-level pulse width tEXL 3.5 — ns 23.1 EXTAL clock input high-level pulse width tEXH 3.5 — ns 23.1 EXTAL clock output rise time tEXr — 4 ns 23.1 EXTAL clock input fall time tEXf — 4 ns 23.1 CKIO clock output PLL2 operating fOP 30 67 MHz PLL2 not operating EXTAL clock input frequency PLL1/PLL2 operating PLL1/PLL2 1/2 divider not operating operating 1/2 divider not operating Figure fOP 1 67 MHz CKIO clock output cycle time tcyc 14.9 1000 ns 23.2(1) CKIO clock output low-level pulse width tCKOL1 1 — ns 23.2(1) CKIO clock output high-level pulse width tCKOH1 1 — ns 23.2(1) CKIO clock output rise time tCKOr — 3 ns 23.2(1) CKIO clock output fall time tCKOf — 3 ns 23.2(1) CKIO clock output low-level pulse width tCKOL2 3 — ns 23.2(2) CKIO clock output high-level pulse width tCKOH2 3 — ns 23.2(2) Power-on oscillation settling time tOSC1 10 — ms 23.3, 23.5 Power-on oscillation settling time/mode settling tOSCMD 10 — ms 23.3, 23.5 MD reset setup time tMDRS 3 — tcyc MD reset hold time tMDRH 20 — ns 23.3, 23.5 tRESW 20 — tcyc 23.3, 23.4, 23.5, 23.6 PLL synchronization settling time tPLL 200 —
s 23.9, 23.10 Standby return oscillation settling time 1 tOSC2 10 — ms 23.4, 23.6 Standby return oscillation settling time 2 tOSC3 5 — ms 23.7 Standby return oscillation settling time 3 tOSC4 5 — ms 23.8 IRL interrupt determination time (RTC used, standby mode) tIRLSTB — 200
s 23.10 tTRSTRH 0 — ns 23.3, 23.5
 assert time 
 reset hold time Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 23 MHz. When a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the CKIO pin should be a maximum of 50 pF. Rev. 3.0, 04/02, page 955 of 1064 tEXcyc tEXL tEXH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tEXf tEXr Note: When the clock is input from the EXTAL pin Figure 23.1 EXTAL Clock Input Timing tcyc tCKOL1 tCKOH1 VOH VOH VOH 1/2VDDQ 1/2VDDQ VOL VOL tCKOf tCKOr Figure 23.2(1) CKIO Clock Output Timing tCKOH2 1.5 V tCKOL2 1.5 V 1.5 V Figure 23.2(2) CKIO Clock Output Timing Rev. 3.0, 04/02, page 956 of 1064 Stable oscillation CKIO, internal clock VDD min VDD tRESW tOSC1 tOSCMD tMDRH MD10 to MD0 tTRSTRH TRST (High) CA Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 23.3 Power-On Oscillation Settling Time Standby Stable oscillation CKIO, internal clock tRESW tOSC2 or Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 23.4 Standby Return Oscillation Settling Time (Return by
 
    or 
) Rev. 3.0, 04/02, page 957 of 1064 Stable oscillation Internal clock VDD min VDD tRESW tOSC1 tOSCMD tMDRH MD10 to MD0 tTRSTRH CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 23.5 Power-On Oscillation Settling Time Stable oscillation Standby Internal clock tRESW tOSC2 or CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 23.6 Standby Return Oscillation Settling Time (Return by
 
    or 
) Rev. 3.0, 04/02, page 958 of 1064 Standby Stable oscillation CKIO, internal clock tOSC3 NMI Note: Oscillation settling time when on-chip resonator is used Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) Stable oscillation Standby CKIO, internal clock tOSC4 – Note: Oscillation settling time when on-chip resonator is used Figure 23.8 Standby Return Oscillation Settling Time (Return by 
–
 ) Rev. 3.0, 04/02, page 959 of 1064 Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input tPLL × 2 PLL synchronization PLL synchronization PLL output, CKIO output Internal clock STATUS1– STATUS0 Normal Normal Standby Note: When an external clock is input from EXTAL. Figure 23.9 PLL Synchronization Settling Time in Case of
   
 or NMI Interrupt – interrupt request Stable input clock Stable input clock EXTAL input PLL synchronization tIRLSTB tPLL × 2 PLL synchronization PLL output, CKIO output Internal clock STATUS1– STATUS0 Normal Standby Normal Note: When an external clock is input from EXTAL. Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt Rev. 3.0, 04/02, page 960 of 1064 23.3.2 Control Signal Timing Table 23.24 Control Signal Timing (1) Item HD6417751R BP240 HD6417751R BP200 HD6417751R F240 HD6417751R F200 * * * * Symbol Min Max Min Max Min Max Min Max Unit Figure tBREQS 2.0 — 2.5 — 3.5 — 3.5 — ns 23.11 tBREQH 1.5 — 1.5 — 1.5 — 1.5 — ns 23.11 tBACKD — 5.3 — 5.3 — 6 — 6 ns 23.11 Bus tri-state delay time tBOFF1 — 12 — 12 — 12 — 12 ns 23.11 Bus tri-state delay time to standby mode tBOFF2 — 2 — 2 — 2 — 2 tcyc 23.12 Bus buffer on time tBON1 — 12 — 12 — 12 — 12 ns 23.11 Bus buffer on time from standby tBON2 — 1 — 1 — 1 — 1 tcyc 23.12 STATUS0/1 delay time tSTD1 — 5.3 — 5.3 — 6 — 6 ns 23.12 STATUS0/1 delay time to standby tSTD2 — 2 — 2 — 2 — 2 tcyc 23.12 
 setup time 
 hold time  delay time Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ, Ta = –20 to 75C, CL = 30 pF, PLL2 on Rev. 3.0, 04/02, page 961 of 1064 Table 23.25 Control Signal Timing (2) Item HD6417751VF133 HD6417751BP167 HD6417751BP167I HD6417751F167 HD6417751F167I *1 *2 Symbol Min Max Min Max Unit Figure tBREQS 3.5 — 3.5 — ns 23.11 
 setup time 
 hold time  delay time tBREQH 1.5 — 1.5 — ns 23.11 tBACKD — 8 — 8 ns 23.11 Bus tri-state delay time tBOFF1 — 12 — 12 ns 23.11 Bus tri-state delay time to standby mode tBOFF2 — 2 — 2 tcyc 23.12 Bus buffer on time tBON1 — 12 — 12 ns 23.11 Bus buffer on time from standby tBON2 — 2 — 2 tcyc 23.12 STATUS0/1 delay time tSTD1 — 9 — 9 ns 23.12 STATUS0/1 delay time to standby tSTD2 — 2 — 2 tcyc 23.12 Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ, Ta = –20 to 75
C, CL = 30 pF, PLL2 on *2 VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ, Ta = –20 to 75
C, CL = 30 pF, PLL2 on (HD6417751BP167, HD6417751F167) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ, Ta = –40 to 85
C, CL = 30 pF, PLL2 on (HD6417751BP167I, HD6417751F167I) Rev. 3.0, 04/02, page 962 of 1064 CKIO tBREQH tBREQH tBREQS tBREQS tBACKD A25–A0, , RD/ , , , , , , tBACKD tBOFF1 , tBON1 Figure 23.11 Control Signal Timing Normal operation Standby mode Normal operation CKIO STATUS0, STATUS1 Standby Normal tSTD2 , , , , , / Normal tSTD1 , , , tBON2 tBOFF2 A25–A0, D31–D0 DACKn, DRAKn, SCK, * TXD, TXD2, CTS2, RTS2 Note: * When the PHZ bit in STBCR is set to 1, these pins go to the high-impedance state (except for pins being used as port pins, which retain their port state). Figure 23.12 Pin Drive Timing for Standby Mode Rev. 3.0, 04/02, page 963 of 1064 23.3.3 Bus Timing Table 23.26 Bus Timing (1) HD6417751R BP240 HD6417751R BP200 HD6417751R F240 HD6417751R F200 * * * * Item Symbol Min Max Min Max Min Max Min Max Unit Address delay time tAD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tBSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tCSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns  delay time  delay time
delay time
 delay time tRWD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tRSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tRDS 2.0 — 2.5 — 3.5 — 3.5 — ns Read data hold time tRDH 1.5 — 1.5 — 1.5 — 1.5 — ns  delay time tWEDF — 5.3 — 5.3 — 6 — 6 ns tWED1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns Write data delay time tWDD Read data setup time (falling edge)  delay time
 setup time
 hold time
 delay time  delay time 1  delay time 2 Notes Relative to CKIO falling edge 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tRDYS 2.0 — 2.5 — 3.5 — 3.5 — ns tRDYH 1.5 — 1.5 — 1.5 — 1.5 — ns tRASD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tCASD1 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns DRAM tCASD2 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM CKE delay time tCKED 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM DQM delay time tDQMD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns SDRAM tFMD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns MPX tIO16S 2.0 — 2.5 — 3.5 — 3.5 — ns PCMCIA
 delay time  setup time  hold time 
delay time tIO16H 1.5 — 1.5 — 1.5 — 1.5 — ns PCMCIA tICWSDF 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns PCMCIA tICRSD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns PCMCIA DACK delay time tDACD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns DACK delay time (falling edge) tDACDF 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns (falling edge) 
 delay time Rev. 3.0, 04/02, page 964 of 1064 Relative to CKIO falling edge HD6417751R BP240 HD6417751R BP200 HD6417751R F240 HD6417751R F200 * * * * Item Symbol Min Max Min Max Min Max Min Max Unit DTR setup time tDTRS 2.0 — 2.5 — 3.5 — 3.5 — ns DTR hold time tDTRH 1.5 — 1.5 — 1.5 — 1.5 — ns tDBQS 2.0 — 2.5 — 3.5 — 3.5 — ns tDBQH 1.5 — 1.5 — 1.5 — 1.5 — ns tTRS 2.0 — 2.5 — 3.5 — 3.5 — ns tTRH 1.5 — 1.5 — 1.5 — 1.5 — ns tBAVD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tTDAD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns tIDD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 
 setup time 
 hold time 
setup time 
hold time  delay time  delay time ID1, ID0 delay time Notes Note: * VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ., Ta = –20 to +75C, CL = 30 pF, PLL2 on Rev. 3.0, 04/02, page 965 of 1064 Table 23.27 Bus Timing (2) HD6417751VF133 HD6417751BP167 HD6417751BP167I HD6417751F167 HD6417751F167I *1 *2 Item Symbol Min Max Min Max Unit Address delay time tAD 1.0 8 1.0 8 ns tBSD 1.0 8 1.0 8 ns tCSD 1.0 8 1.0 8 ns ns  delay time  delay time
delay time
 delay time tRWD 1.0 8 1.0 8 tRSD 1.0 8 1.0 8 ns Read data setup time tRDS 3.5 — 3.5 — ns Read data hold time tRDH 1.5 — 1.5 — ns tWEDF 1.0 8 1.0 8 ns  delay time tWED1 1.0 8 1.0 8 ns Write data delay time tWDD 1.0 8 1.0 8 ns tRDYS 3.5 — 3.5 — ns  delay time (falling edge) Notes Relative to CKIO falling edge
 setup time
 hold time
 delay time  delay time 1  delay time 2 tRDYH 1.5 — 1.5 — ns tRASD 1.0 8 1.0 8 ns tCASD1 1.0 8 1.0 8 ns DRAM tCASD2 1.0 8 1.0 8 ns SDRAM CKE delay time tCKED 1.0 8 1.0 8 ns SDRAM DQM delay time tDQMD 1.0 8 1.0 8 ns SDRAM 
 delay time  setup time  hold time 
delay time tFMD 1.0 8 1.0 8 ns MPX tIO16S 3.5 — 3.5 — ns PCMCIA tIO16H 1.5 — 1.5 — ns PCMCIA tICWSDF 1.0 8 1.0 8 ns PCMCIA 
 delay time tICRSD 1.0 8 1.0 8 ns PCMCIA DACK delay time tDACD 1.0 8 1.0 8 ns DACK delay time (falling edge) tDACDF 1.0 8 1.0 8 ns (falling edge) Rev. 3.0, 04/02, page 966 of 1064 Relative to CKIO falling edge HD6417751VF133 HD6417751BP167 HD6417751BP167I HD6417751F167 HD6417751F167I *1 *2 Item Symbol Min Max Min Max Unit DTR setup time tDTRS 3.5  3.5  ns DTR hold time tDTRH 1.5  1.5  ns tDBQS 3.5  3.5  ns tDBQH 1.5  1.5  ns tTRS 3.5  3.5  ns tTRH 1.5  1.5  ns 
 setup time 
 hold time 
setup time 
hold time  delay time  delay time tBAVD 1.0 8 1.0 8 ns tTDAD 1.0 8 1.0 8 ns ID1, ID0 delay time tIDD 1.0 8 1.0 8 ns Notes Notes: *1 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ., Ta = –20 to +75
C, CL = 30 pF, PLL2 on *2 VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ., Ta = –20 to +75
C, CL = 30 pF, PLL2 on (HD6417751BP167, HD6417751F167) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ, Ta = –40 to 85
C, CL = 30 pF, PLL2 on (HD6417751BP167I, HD6417751F167I) Rev. 3.0, 04/02, page 967 of 1064 T1 T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 RD/ tRSD tRSD tRSD tRDS D31–D0 (read) tWED1 tWEDF tWDD tRDH tWEDF tWDD tWDD D31–D0 (write) tBSD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tBSD tDACD tDACD tDACDF tDACD DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Rev. 3.0, 04/02, page 968 of 1064 T1 Tw T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 RD/ tRSD tRSD tRSD tRDS D31–D0 tRDH (read) tWED1 tWEDF tWDD tWEDF tWDD tWDD D31–D0 (write) tBSD tBSD tRDYS tDACD tRDYH tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) tDACD tDACDF tDACD DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) Rev. 3.0, 04/02, page 969 of 1064 T1 Tw Twe T2 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 RD/ tRSD tRSD tRSD tRDS D31–D0 (read) tWED1 tWEDF tWDD tRDH tWEDF tWDD tWDD D31–D0 (write) tBSD tBSD tRDYS tDACD DACKn (SA: IO ← memory) tDACDF tRDYH tRDYS tDACD tRDYH tDACD tDACDF DACKn (SA: IO → memory) tDACD tDACD DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 970 of 1064 TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 RD/ tRSD tRSD tRSD tRDS D31–D0 (read) tWED1 tWEDF tWDD tRDH tWEDF tWDD tWDD D31–D0 (write) tBSD tBSD tDACD tDACD DACKn (SA: IO ← memory) tDACDF DACKn (SA: IO → memory) DACKn (DA) tDACD tDACD tDACDF tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev. 3.0, 04/02, page 971 of 1064 T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD tAD A25–A5 tAD A4–A0 RD/ tCSD tCSD tRWD tRWD tRSD tRSD tRDS D31–D0 (read) tBSD tDACD tRDH tRDS tBSD tDACD tDACD DACKn (SA: IO ← memory) tRSD tDACD tDACD DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.17 Burst ROM Bus Cycle (No Wait) Rev. 3.0, 04/02, page 972 of 1064 tRDH Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) Rev. 3.0, 04/02, page 973 of 1064 tDACD tDACD tDACD Twb tRDH tAD TB1 tRDYH TB2 tRDS tRDYH Twe tRDYS tRSD tRDYS tBSD tRWD tCSD tAD Tw Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) RDY BS D31–D0 (read) RD RD/WR CSn A4–A0 A25–A5 CKIO T1 TB2 TB1 Twb TB2 Twb tRDYS TB1 tRDH tRWD tAD tRDYH tDACD tRDS tRSD tCSD T2 Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev. 3.0, 04/02, page 974 of 1064 tBSD TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 tRDS T2 tRDH TH1 tAD tDACD tDACD tBSD tDACD tRDS tDACD tDACD tRSD tRWD TB1 tRWD tAD TS1 tRDH TH1 tCSD tRSD TB2 tCSD tAD T1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) D31–D0 (read) RD/ A4–A0 A25–A5 CKIO TS1 Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 975 of 1064 tRDH Twb Twbe TB2 TB1 Twb Twbe TB2 tBSD TB1 tBSD Twb Twbe tRDS T2 tAD tBSD tDACD tDACD tRDYH tRDYS tDACD tRDYS tBSD tRSD tRDYH tDACD tRDYS tRDYS tRDYH tDACD tRDYH tRDH tRSD tRWD tRDS tAD TB1 tRWD tRSD TB2 tCSD Twe tCSD tAD Tw Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) D31–D0 (read) RD/ A4–A0 A25–A5 CKIO T1 Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) Rev. 3.0, 04/02, page 976 of 1064 tRASD tCASD2 tBSD Tc3 tRDS Tc4/Td1 c1 tRDH Td2 tDQMD Td3 Td4 tAD Tpc tRASD tCASD2 tDQMD tDACD tDACD tBSD tRWD column Tc2 tRWD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Row Address H/L tAD Tc1 tCSD Row Precharge-sel Trw tCSD Row tAD Tr Bank CKIO Tpc Tpc Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) Rev. 3.0, 04/02, page 977 of 1064 tBSD Tc3 tRDS Tc4/Td1 c1 c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 tDQMD Td7 Td8 c8 tAD Tpc tRASD tDQMD tCASD2 tCASD2 tDACD tBSD c2 tRDH c7 tDACD tRWD Tc2 tRWD c1 H/L tAD Tc1 tCSD tRASD Trw tCSD Row Row Row tAD Tr Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Address Precharge-sel Bank CKIO Tpc Tpc Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD [1:0] = 01, CAS Latency = 3) Rev. 3.0, 04/02, page 978 of 1064 tRASD tCASD2 Tc3 tRDS Tc4/Td1 c1 c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 tDQMD Td7 Td8 tAD tRASD tCASD2 tDQMD tDACD tBSD tBSD c2 tRDH c7 c8 tDACD tRWD c1 Tc2 tRWD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Row Address H/L tAD Tc1 tCSD Row Precharge-sel Trw tCSD Row tAD Bank CKIO Tr Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) Rev. 3.0, 04/02, page 979 of 1064 tRWD tRASD tRASD tRWD tCSD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Address Row Row H/L Precharge-sel tAD Tr Row tAD Tpc Bank CKIO Tpr tCASD2 Trw tDQMD c1 H/L tAD Tc1 tCASD2 Tc2 Tc3 c1 tDACD tBSD tRDS Tc4/Td1 tBSD c2 tRDH c5 H/L tAD Td2 Td3 c3 Td4 c4 Td5 c5 Td6 c6 Td8 c7 tDQMD Td7 c8 tDACD tCSD tAD Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3) Rev. 3.0, 04/02, page 980 of 1064 tRDS c1 tDQMD tCASD2 tRASD tDACD tBSD tBSD c2 tRDH c5 H/L Td3 c3 Td4 c4 Td5 c5 Td6 c6 tDQMD Td7 c7 Td8 c8 tAD tDACD tRASD tRWD tAD Td2 tRWD tCASD2 Tc4/Td1 tCSD c1 H/L Tc3 tCSD tAD Tc2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) CKE D31–D0 (read) DQMn RD/ Address Precharge-sel Bank CKIO Tc1 Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc CKIO tAD tAD Bank Row Precharge-sel Row H/L Address Row c1 tAD tCSD tCSD tRWD tRWD RD/ tRASD tRASD tCASD2 tCASD2 tDQMD tDQMD DQMn tWDD D31–D0 (write) tWDD c1 tBSD tBSD CKE DACKn (SA: IO → memory) tDACD tDACD Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) Rev. 3.0, 04/02, page 981 of 1064 Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) Rev. 3.0, 04/02, page 982 of 1064 tDACD tCASD2 tRASD tCSD Row Row Row tAD tWDD tRASD Trw Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Tr tBSD c1 tDQMD tCASD2 tRWD c1 H/L tAD Tc1 tBSD c2 tWDD tCASD2 tRWD Tc2 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trw1 Trw1 Tpc Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD [1:0] = 01, TRWL [2:0] = 010) Rev. 3.0, 04/02, page 983 of 1064 tDACD tRASD tCSD Row Row Row tAD tWDD tRASD Trw Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Tr tBSD c1 tDQMD tCASD2 tRWD c1 H/L tAD Tc1 tBSD c2 tWDD tCASD2 tRWD Tc2 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trw1 Trw1 Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) Rev. 3.0, 04/02, page 984 of 1064 tRASD tRWD tCSD H/L tAD tRASD tRWD Tpc Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Tpr tDACD Row Row Row tAD Tr tWDD Trw Tc2 tBSD c1 tDQMD tBSD c2 tWDD tCASD2 tCASD2 c1 H/L tAD Tc1 Tc3 c3 Tc4 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trw1 Trw1 Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL [2:0] = 010) Rev. 3.0, 04/02, page 985 of 1064 tDACD tRASD tWDD tCASD2 (Tnop) tBSD c1 tDQMD tRWD tCSD c1 H/L tAD Tc1 Tc3 c3 Tc4 Normal write Single address DMA tBSD c2 tWDD tCASD2 tRWD Tc2 c4 c5 c5 H/L tAD Tc5 Tc6 c6 c7 tDACD Tc7 Tc8 c8 tDQMD tCSD tAD Trwl Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line. DACKn (SA: IO → memory) CKE D31–D0 (write) DQMn RD/ Address Precharge-sel Bank CKIO Tnop Trwl tDACD Tpr Tpc CKIO tAD tAD Bank Row Precharge-sel H/L Address tCSD tCSD tRWD tRWD tRASD tRASD RD/ tCASD2 tCASD2 tDQMD tDQMD tWDD tWDD DQMn D31–D0 (write) tBSD CKE tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) Rev. 3.0, 04/02, page 986 of 1064 TRr1 TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc CKIO tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tRWD tCSD tRWD RD/ tRASD tRASD tRASD tCASD2 tCASD2 tCASD2 tRASD tCASD2 tDQMD tDQMD DQMn D31–D0 (write) tWDD tWDD tBSD CKE tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001) Rev. 3.0, 04/02, page 987 of 1064 TRs1 TRs2 TRs3 TRs4 TRs5 Trc Trc Trc CKIO tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tCSD tRWD tRWD RD/ tRASD tCASD2 tRASD tCASD2 tRASD tRASD tCASD2 tCASD2 tDQMD tDQMD DQMn tWDD tWDD D31–D0 (write) tBSD tCKED tCKED CKE tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001) Rev. 3.0, 04/02, page 988 of 1064 TRp1 TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 RD/ tCASD2 tCASD2 tDQMD tDQMD tWDD tWDD DQMn D31–D0 (write) tBSD CKE tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) Rev. 3.0, 04/02, page 989 of 1064 TRp1 TRp2 TRp3 TRp4 TMw TMw2 TMw3 TMw4 TMw5 CKIO tAD tAD tAD Bank Precharge-sel Address tCSD tCSD tCSD tRWD tRWD tRWD tRASD tRASD tRASD tCASD2 tCASD2 RD/ tCASD2 tCASD2 tDQMD tDQMD tWDD tWDD DQMn D31–D0 (write) tBSD CKE tDACD tDACD DACKn Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.34(b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) Rev. 3.0, 04/02, page 990 of 1064 Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 Rev. 3.0, 04/02, page 991 of 1064 tDACD tDACD tDACD tWDD tRASD Tr2 tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) D31–D0 (write) D31–D0 (read) RD/ A25–A0 CKIO tBSD (1) tCASD1 Tc2 tBSD tRDS column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc tDACD tDACD tWDD tCASD1 tRASD tRWD tCSD Row tAD Tr1 tDACD tDACD tWDD tRASD Tr2 Trw tBSD tBSD Tc2 tRDS tCASD1 Tcw (2) column tAD Tc1 tDACD tDACD tWDD tRDH tCASD1 tRASD tRWD tCSD tAD Tpc Tpc Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) Rev. 3.0, 04/02, page 992 of 1064 tRDS tAD Tpc tDACD tCASD1 tRASD tDACD tRASD tBSD tBSD tRDH tCASD1 tRASD tRWD column Tce tRWD tCASD1 tAD Tc2 tCSD Row Tc1 tCSD tAD Tr2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Tr1 Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) Rev. 3.0, 04/02, page 993 of 1064 tCASD1 c2 Tc2 tRDH Tc1 d2 Tc2 Tc1 c8 Tc2 tRDS Tce d8 tAD Tpc tDACD tCASD1 tRASD tDACD tRASD tBSD tBSD tRDS d1 tDACD tCASD1 tRDH tCASD1 tRASD tRWD c1 Tc1 tRWD tCASD1 tAD Tc2 tCSD Row Tc1 tCSD tAD Tr2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Tr1 Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) Rev. 3.0, 04/02, page 994 of 1064 tDACD tDACD tCASD1 tRASD tBSD tBSD tCASD1 c1 Tcw Tc2 tCASD1 Tc1 tRDS tRDH tDACD d1 tCASD1 c2 Tcw Tc2 Tc1 Tcw Tc2 Tc1 Tc2 c8 d7 tCASD1 Tcw tRDS Tce tAD Tpc d8 tRDH tCASD1 tRASD tRWD tAD Tc1 tRWD tRASD Trw tCSD Row Tr2 tCSD tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) Rev. 3.0, 04/02, page 995 of 1064 c1 Tcw Tc2 Tc1 tCASD1 Tcnw c2 Tc2 tRDH Tcw Tcw Tc1 d2 Tcw Tc2 Tc1 tCASD1 Tcnw Tcw c8 Tc2 Tcnw tRDS Tce tAD Tpc tRASD tDACD t DACD tCASD1 tRASD tBSD tCASD1 tRDS tDACD d1 d8 tRDH tCASD1 tRASD tRWD tAD Tc1 tRWD tBSD Trw tCSD Row Tr2 tCSD tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) Rev. 3.0, 04/02, page 996 of 1064 tDACD tCASD1 tRASD tRWD tCSD tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Tpc tDACD tBSD tRASD Row Tr2 tCASD1 tAD Tc1 tBSD c1 Tc2 tRDS Tc2 tRDH tDACD c2 d1 tCASD1 Tc1 Tc1 d2 Tc2 tCASD1 Tc1 c8 Tc2 tRDS Tce d8 tRDH tCASD1 tRWD tCSD tAD Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) Rev. 3.0, 04/02, page 997 of 1064 tRWD tDACD tBSD tCSD tAD Tc1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO ← memory) D31–D0 (read) RD/ Address CKIO Tnop tBSD tCASD1 c1 Tc2 tRDS tCASD1 tAD Tc1 d1 tRDH tDACD c2 Tc2 Tc1 d2 Tc2 tCASD1 Tc1 T2 c8 tRDS tRASD Tce d8 RAS-down mode ended tRDH tCASD1 tRWD tCSD tAD Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) Rev. 3.0, 04/02, page 998 of 1064 tCASD1 d1 tCASD1 c2 Tc2 d2 Tc1 Tc2 Tc1 c8 Tc2 d8 tAD Tpc tDACD tDACD tWDD tCASD1 tRASD tDACD tDACD tWDD tRASD tBSD tDACD tBSD tRDS tDACD tWDD tRDH d2 d8 tRDS tCASD1 tWDD tRDH tCASD1 tRASD tRWD c1 Tc1 tRWD d1 tAD Tc2 tCSD Row Tc1 tCSD tAD Tr2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) D31–D0 (write) D31–D0 (read) RD/ Address CKIO Tr1 Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) Rev. 3.0, 04/02, page 999 of 1064 c1 Tcw Tc2 d1 tCASD1 Tc1 c2 Tcw Tc2 d2 Tc1 Tcw Tc2 Tc1 c8 Tcw Tc2 tAD Tpc tDACD tDACD tWDD tCASD1 tRASD tDACD tDACD tWDD tRASD tBSD d1 tDACD tRDS tCASD1 tDACD tWDD tRDH d2 d8 tRDS tCASD1 tRDH tWDD d3 tCASD1 tRASD tRWD tBSD tAD Tc1 tRWD Trw tCSD Row Tr2 tCSD tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) D31–D0 (write) D31–D0 (read) RD/ Address CKIO Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) Rev. 3.0, 04/02, page 1000 of 1064 c1 Tcw Tc2 Tc1 tCASD1 Tcnw c2 Tcw Tc2 d2 Tcw Tc1 Tcw Tc2 Tcnw d8 Tc1 c8 Tcw Tc2 tAD Tcnw tDACD tDACD tWDD tWDD tRASD tDACD tDACD tCASD1 tRASD tBSD tBSD d1 tWDD tRDH tDACD d1 tDACD tRDS tCASD1 d2 tRDS tCASD1 Tpc tRDH tWDD d8 tCASD1 tRASD tRWD tAD Tc1 tRWD Trw tCSD Row Tr2 tCSD tAD Tr1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (SA: IO → memory) DACKn (SA: IO ← memory) D31–D0 (write) D31–D0 (read) RD/ Address CKIO Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 CKIO tAD Address tAD Row tAD c1 c2 c8 tCSD tCSD tRWD tRWD RD/ tRASD tRASD tCASD1 tCASD1 tCASD1 tRDS D31–D0 (read) tRDH tWDD tWDD tBSD tDACD tDACD tDACD tRDS tRDH d8 tWDD d1 tDACD tCASD1 d2 d1 D31–D0 (write) tCASD1 tWDD d2 d8 tBSD tDACD DACKn (SA: IO ← memory) tDACD DACKn (SA: IO → memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) Rev. 3.0, 04/02, page 1001 of 1064 Tnop Tc1 Tc2 Tc1 Tc1 Tc2 Tc2 Tc1 Tc2 CKIO tAD Address tAD c1 c2 c8 tCSD tRWD RD/ RAS down mode ended tCASD1 tCASD1 tRDS D31–D0 (read) tWDD tCASD1 tRDS tRDH d2 d1 d1 tBSD tWDD d8 tBSD tDACD tDACD d2 tRDH d8 tWDD D31–D0 (write) DACKn (SA: IO ← memory) tCASD1 tRASD tDACD tDACD DACKn (SA: IO → memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) Rev. 3.0, 04/02, page 1002 of 1064 TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tCASD1 tRASD tCASD1 tWDD D31–D0 (write) DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 000, TRC [2:0] = 001) Rev. 3.0, 04/02, page 1003 of 1064 TRr1 TRr2 TRr3 TRr4 TRr4w TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tCASD1 tRASD tCASD1 tWDD D31–D0 (write) DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS [2:0] = 001, TRC [2:0] = 001) Rev. 3.0, 04/02, page 1004 of 1064 TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc CKIO tAD A25–A0 tCSD tRWD RD/ tRASD tCASD1 tRASD tCASD1 tRASD tCASD1 tWDD D31–D0 (write) DACKn (SA: IO ← memory) tDACD tDACD DACKn (SA: IO → memory) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001) Rev. 3.0, 04/02, page 1005 of 1064 Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait Rev. 3.0, 04/02, page 1006 of 1064 tDACD tBSD tRDS (1) tBSD tWDD tDACD tWDD tRDH tRSD tRWD tCSD tAD tWEDF tRSD tWEDF tWDD tWED1 tRSD tRWD tCSD tAD Tpcm2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RDY BS D15–D0 (write) WE1 D15–D0 (read) RD RD/WR CExx REG (WE0) A25–A0 CKIO Tpcm1 TED tDACD tBSD tWDD tWED1 tRSD tRWD tCSD tAD Tpcm0 tBSD tWDD Tpcm1 tRDYS tWEDF tRSD Tpcm1w (2) tRDYS TEH tWEDF tWDD tRSD tRWD tCSD tAD tDACD tRDH Tpcm2w tRDYH tRDS Tpcm2 tRDYH Tpcm1w Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait Rev. 3.0, 04/02, page 1007 of 1064 ( ( ) ) ) tDACD tIO16S tBSD (1) tWDD tDACD tIO16H tBSD tWDD tICWSDF tICWSDF tRDS tRDH tRWD tCSD tAD tICRSD tICRSD tRWD tCSD tAD Tpci2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) D15–D0 (write) D15–D0 (read) RD/ ( A25–A0 CKIO Tpci1 tDACD tBSD tWDD tICWSDF tICRSD tRWD tCSD tAD Tpci0 tBSD tWDD Tpci1 tRDYS tICWSDF (2) tIO16H tICWSDF tWDD tRWD tCSD tAD tDACD tRDH tICRSD Tpci2w tIO16S tRDS Tpci2 tRDYH tRDYH Tpci1w tRDYS tICRSD Tpci1w Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing) Rev. 3.0, 04/02, page 1008 of 1064 ( ( ( ) ) ) tBSD tWDD tBSD tWDD tICWSDF tICWSDF tICRSD tRWD tCSD tAD Tpci1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high D15–D0 (write) D15–D0 (read) RD/ A0 A25–A1 CKIO Tpci0 tICWSDF tRDS Tpci2 tIO16S tIO16H tRDYS tRDYH tICRSD Tpci1w tRDH tICRSD Tpci2w tWDD tCSD tAD Tpci0 tWDD tICWSDF Tpci1 tICWSDF Tpci2 tRDYS tRDYH Tpci1w Tpci2w tWDD tRWD tCSD tAD Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 1009 of 1064 A tCSD tBSD tRDYS tRDYH Tmd1w tDACD tWED1 tRWD tRDYH tRDH tCSD D0 tRDS Tmd1 (2) tDACD tBSD tRDYS tWED1 tWDD tFMD Tmd1w 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tWED1 A tCSD tRWD tWDD tFMD Tm0 (1) tBSD tRDYH tRDH tCSD tRWD D0 tRDS Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD tRDYS tWED1 tRWD tWDD tFMD Tmd1w Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RD/ D63–D0 / CKIO Tm1 Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 1010 of 1064 tWED1 tRWD tCSD tWDD tWED1 tRWD tCSD tWDD tDACD tRDYH 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD D0 Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1w (2) tBSD tRDYH D0 tWDD tFMD Tm1 (1) tDACD tBSD tRDYS tWED1 tRWD tCSD A tWDD tFMD Tmd1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RD/ D63–D0 / CKIO Tm1 (3) tRDYS tBSD D0 tRDYH Tmd1w tCSD tWDD tDACD tWED1 tRWD tRDYH Tmd1 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tDACD tBSD tWDD tFMD Tmd1w tRDYS tWED1 tRWD tCSD A tWDD tFMD Tm1 Figure 23.55 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait) (2) 1st Data (No Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control) Rev. 3.0, 04/02, page 1011 of 1064 Tmd1 tDACD tBSD tBSD tRDYS tRDYH D3 D4 Tmd5 D5 Tmd6 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (1) Tmd4 D6 Tmd7 D7 tFMD Tmd8 D8 tDACD tRWD D2 tRDH Tmd3 tRWD D1 Tmd2 tCSD tWDD tRDS Tmd1w tCSD A tWDD tFMD Tm1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RD/ D31–D0 / CKIO tDACD tBSD Tmd1 tBSD D1 Tmd2 D2 (2) Tmd3 D3 tRDYS Tmd7 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address tRDH Tmd2w tRDYH tWDD tRDS Tmd1w tRDYS tRWD tCSD A tWDD tFMD Tm1 D7 tRDYH tFMD Tmd8w Tmd8 tRWD tCSD tDACD D8 Figure 23.56 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External Wait Control) Rev. 3.0, 04/02, page 1012 of 1064 tDACD tBSD tRDYS tBSD tRDYH D5 Tmd5 D6 Tmd6 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address (1) D4 Tmd4 D7 Tmd7 D8 tFMD Tmd8 tWDD tDACD tRWD D3 Tmd3 tRWD D2 Tmd2 tCSD D1 tWDD Tmd1 tCSD A tWDD tFMD Tm1 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) RD/ D31–D0 / CKIO tWDD Tmd1w tBSD tRDYS tDACD tBSD tRWD tCSD A tWDD tFMD Tm1 D1 D2 Tmd2 (2) D3 Tmd3 D7 Tmd7 tRDYS 1st data bus cycle information D31–D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25–D0: Address Tmd2w tRDYH Tmd1 D8 Tmd8 tRDYH tFMD Tmd8w tDACD tRWD tCSD tWDD Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) Rev. 3.0, 04/02, page 1013 of 1064 tRSD tDACD tDACD tBSD tWED1 (1) tDACD tBSD tWEDF tRDS tDACD tDACD tWED1 tRDH tRSD tRWD tRWD tRSD tCSD tAD tCSD tAD T2 Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high DACKn (DA) DACKn (SA: IO ← memory) D31–D0 (read) RD RD/ A25–A0 CKIO T1 tDACD tDACD tBSD tWED1 tRSD Tw (2) tDACD tRDYS tBSD tWEDF tRSD tRWD tCSD tAD T1 tWED1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tRDYH tRDS T2 tDACD tRSD Tw (3) tRDYH Twe tRDYS tDACD tRDYS tBSD tWEDF tDACD tBSD tWED1 tRSD tRWD tCSD tAD T1 tRDH tRSD tRWD tCSD tAD tDACD tDACD tWED1 tRDYH tRDS T2 TS1 T1 T2 TH1 CKIO tAD tAD tCSD tCSD tRWD tRWD A25–A0 RD/ tRSD D31–D0 (read) tRDS tWED1 tBSD tDACD tRSD tRSD tRDH tWED1 tWEDF tBSD tDACD DACKn (SA: IO ← memory) tDACD tDACD DACKn (DA) Notes: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01) Rev. 3.0, 04/02, page 1014 of 1064 23.3.4 Peripheral Module Signal Timing Table 23.28 Peripheral Module Signal Timing (1) HD6417751 HD6417751 HD6417751 HD6417751 RBP240 RBP200 RF240 RF200 2 2 2 * * 2 * * Module Item Symbol Min Max Min Max Min Max Min Max Unit TMU, RTC Timer clock pulse width (high) tTCLKWH 4 — 4 — 4 — 4 — Pcyc* 23.64 Timer clock pulse width (low) tTCLKWL 4 — 4 — 4 — 4 — Pcyc* 23.64 Timer clock rise time tTCLKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc* 23.64 Timer clock fall time tTCLKf — 0.8 — 0.8 — 0.8 — 0.8 Pcyc* 23.64 tROSC Oscillation settling time — 3 — 3 — 3 — 3 s Input clock tScyc cycle (asynchronous) 4 — 4 — 4 — 4 — Pcyc* 23.64 Input clock cycle (synchronous) tScyc 6 — 6 — 6 — 6 — Pcyc* 23.64 Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 0.8 — 0.8 — 0.8 — 0.8 Pcyc* 23.64 Input clock fall time tSCKf — 0.8 — 0.8 — 0.8 — 0.8 Pcyc* 23.64 Transfer data delay time tTXD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.64 Receive data setup time (synchronous) tRXS 16 — 16 — 16 — 16 — ns 23.64 Receive data hold time (synchronous) tRXH 16 — 16 — 16 — 16 — ns 23.64 Output data tPORTD delay time 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.64 Input data setup time tPORTS 2 — 2.5 — 3.5 — 3.5 — ns 23.64 Input data hold time tPORTH 1.5 — 1.5 — 1.5 — 1.5 — ns 23.64 SCI I/O ports Figure Notes 1 1 1 1 23.64 1 1 23.64 1 1 Rev. 3.0, 04/02, page 1015 of 1064 HD6417751 HD6417751 HD6417751 HD6417751 RBP240 RBP200 RF240 RF200 2 2 Module Item DMAC 
 2 * * 2 * * Symbol Min Max Min Max Min Max Min Max Unit Figure Notes tDRQS 2 — 2.5 — 3.5 — 3.5 — ns 23.64 tDRQH 1.5 — 1.5 — 1.5 — 1.5 — ns 23.64 tDRAKD 1.5 5.3 1.5 5.3 1.5 6 1.5 6 ns 23.64 5 — 5 — 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — 30 — 30 — ns 23.69 Standby mode 5 — 5 — 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — 30 — 30 — ns 23.69 Standby mode setup time 
 hold time DRAKn delay time INTC NMI pulse tNMIH width (high) NMI pulse width (low) H-UDI tNMIL Input clock cycle tTCKcyc 50 — 50 — 50 — 50 — ns 23.65, 23.67 Input clock pulse width (high) tTCKH 15 — 15 — 15 — 15 — ns 23.65 Input clock pulse width (low) tTCKL 15 — 15 — 15 — 15 — ns 23.65 Input clock rise time tTCKr — 10 — 10 — 10 — 10 ns 23.65 Input clock fall time tTCKf — 10 — 10 — 10 — 10 ns 23.65 tASEBRKS 10 — 10 — 10 — 10 — tcyc 23.66 tASEBRKH 10 — 10 — 10 — 10 — tcyc 23.66 TDI/TMS setup time tTDIS 15 — 15 — 15 — 15 — ns 23.67 TDI/TMS hold time tTDIH 15 — 15 — 15 — 15 — ns 23.67 TDO delay time tTDO 0 10 0 10 0 10 0 10 ns 23.67 ASEPINBRK pulse width tPINBRK 2 — 2 — 2 — 2 — Pcyc* 23.68 
setup time 
hold time Notes: *1 Pcyc: P clock cycles *2 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on Rev. 3.0, 04/02, page 1016 of 1064 1 Table 23.29 Peripheral Module Signal Timing (2) HD6417751VF133 HD6417751BP167 HD6417751BP167I HD6417751F167 HD6417751F167I *2 Module TMU, RTC SCI I/O ports Item Symbol Min Max *3 Min Max Unit Figure 1 23.59 1 23.59 1 23.59 1 Timer clock pulse width (high) tTCLKWH 4 — 4 — Pcyc* Timer clock pulse width (low) tTCLKWL 4 — 4 — Pcyc* Timer clock rise time tTCLKr — 0.8 — 0.8 Pcyc* Timer clock fall time tTCLKf — 0.8 — 0.8 Pcyc* 23.59 Oscillation settling time tROSC — 3 — 3 s 23.60 Input clock cycle (asynchronous) tScyc 4 — 4 — Pcyc* Input clock cycle (synchronous) tScyc 6 — 6 — Input clock pulse width tSCKW 0.4 0.6 0.4 Input clock rise time tSCKr — 0.8 Input clock fall time tSCKf — Transfer data delay time tTXD Receive data setup time (synchronous) 1 23.61 Pcyc* 1 23.61 0.6 tScyc 23.61 — 0.8 Pcyc* 0.8 — 0.8 — 30 — tRXS 0.8 — Receive data hold time (synchronous) tRXH 0.8 Output data delay time tPORTD Input data setup time Input data hold time 1 23.61 Pcyc* 1 23.61 30 ns 23.62 0.8 — Pcyc* — 0.8 — — 8 — tPORTS 3.5 — tPORTH 1.5 — 1 23.62 Pcyc* 1 23.62 8 ns 23.63 3.5 — ns 23.63 1.5 — ns 23.63 Notes Rev. 3.0, 04/02, page 1017 of 1064 Module Item DMAC 
 setup HD6417751VF133 HD6417751BP167 HD6417751BP167I HD6417751F167 HD6417751F167I *2 *3 Symbol Min Max Min Max Unit Figure tDRQS 3.5 — 3.5 — ns 23.64 tDRQH Notes time 
 hold time INTC 1.5 — 1.5 — ns 23.64 DRAKn delay time tDRAKD — 8 — 8 ns 23.64 NMI pulse width (high) 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — ns 23.69 Standby mode 5 — 5 — tcyc 23.69 Normal or sleep mode 30 — 30 — ns 23.69 Standby mode NMI pulse width (low) H-UDI tNMIH tNMIL Input clock cycle tTCKcyc 50 — 50 — ns 23.65, 23.67 Input clock pulse width (high) tTCKH 15 — 15 — ns 23.65 Input clock pulse width (low) tTCKL 15 — 15 — ns 23.65 Input clock rise time tTCKr — 10 — 10 ns 23.65 Input clock fall time tTCKf — 10 — 10 ns 23.65 
setup tASEBRKS 10 — 10 — tcyc 23.66 time 
hold time tASEBRKH 10 — 10 — tcyc 23.66 tTDIS 15 — 15 — ns 23.67 TDI/TMS hold time tTDIH 15 — 15 — ns 23.67 TDO delay time 0 12 0 10 ns 23.67 2 — 2 — Pcyc* TDI/TMS setup time tTDO ASE-PINBRK pulse tPINBRK width 1 23.68 Notes: *1 Pcyc: P clock cycles *2 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ, Ta = –20 to 75
C, CL = 30 pF, PLL2 on *3 VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ, Ta = –20 to 75
C, CL = 30 pF, PLL2 on (HD6417751BP167, HD6417751F167) VDDQ = 3.0 to 3.6 V, VDD = 1.8 V typ, Ta = –40 to 85
C, CL = 30 pF, PLL2 on (HD6417751BP167I, HD6417751F167I) Rev. 3.0, 04/02, page 1018 of 1064 TCLK tTCLKWH tTCLKWL tTCLKf tTCLKr Figure 23.59 TCLK Input Timing Oscillation settling time RTC internal clock VDD-RTC VDD-RTC min tROSC Figure 23.60 RTC Oscillation Settling Time at Power-On tSCKW SCK, SCK2 tScyc tSCKf tSCKr Figure 23.61 SCK Input Clock Timing tScyc SCK tTXD tTXD TXD RXD tRXS tRXH Figure 23.62 SCI I/O Synchronous Mode Clock Timing Rev. 3.0, 04/02, page 1019 of 1064 CKIO Ports 31–0 (read) tPORTS tPORTH Ports 31–0 (write) tPORTD tPORTD Figure 23.63 I/O Port Input/Output Timing CKIO tDRQH tDRQH DREQn tDRQS tDRQS tDRAKD DRAKn Figure 23.64(a) 
 /DRAK Timing CKIO tDBQS tDBQH DBREQ tBAVD tBAVD BAVL tTRH tTRS TR tDTRS D31 to D0 (READ) (1) tDTRH (2) (1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz) (2): DTR = 1CKIO cycle (= 10 ns: 100 MHz) (tDTRS + tDTRH) < DTR < 10 ns Figure 23.64(b) 
 /
Input Timing and  Output Timing Rev. 3.0, 04/02, page 1020 of 1064 tTCKcyc tTCKL tTCKH VIH VIH VIH 1/2VDDQ 1/2VDDQ VIL VIL tTCKf tTCKr Note: When clock is input from TCK pin Figure 23.65 TCK Input Timing tASEBRKS tASEBRKH / BRKACK Figure 23.66 tTCKcyc TCK TDI TMS
 Hold Timing tTDIS tTDIH tTDO TDO Figure 23.67 H-UDI Data Transfer Timing tPINBRK Figure 23.68 Pin Break Timing Rev. 3.0, 04/02, page 1021 of 1064 tNMIH tNMIL NMI Figure 23.69 NMI Input Timing Rev. 3.0, 04/02, page 1022 of 1064 Table 23.30 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1) HD6417751RBP240, HD6417751RBP200, HD6417751RF240, HD6417751RF200: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF 33 MHz Pin Item PCICLK 66 MHz Symbol Min Max Min Max Unit Figure Clock cycle tPCICYC 30 — 15 30 ns 23.70 Clock pulse width (high) tPCIHIGH 11 — 6 — ns 23.70 Clock pulse width (low) tPCILOW 11 — 6 — ns 23.70 Clock rise time tPCIr — 4 — 1.5 ns 23.70 Clock fall time tPCIf — 4 — 1.5 ns 23.70 
 Output data delay time tPCIVAL — 10 — 8 ns 23.71 IDSEL Input hold time tPCIH 1.5 — 1.5 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 AD31–AD0 Output data delay time tPCIVAL — 10 — 8 ns 23.71 C/–C/ Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 Input hold time tPCIH 1.5 — 1.5 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 Output data delay time tPCIVAL — 10 — 8 ns 23.71 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 12 ns 23.71 Input hold time tPCIH 1.5 — 1.5 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 PAR 
 
 
    


/  
/ MD9 
/ MD10 
/ /
 –  

 Rev. 3.0, 04/02, page 1023 of 1064 Table 23.31 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2) HD6417751BP167, HD6417751F167: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75
C, CL = 30 pF HD6417751BP167I, HD6417751F167I: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –40 to 85
C, CL = 30 pF HD6417751F133: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF 33 MHz 66 MHz Pin Item Symbol Min Max Min Max Unit Figure PCICLK Clock cycle tPCICYC 30 — 15 30 ns 23.70 Clock pulse width (high) tPCIHIGH 11 — 6 — ns 23.70 Clock pulse width (low) tPCILOW 11 — 6 — ns 23.70 Clock rise time tPCIr — 4 — 1.5 ns 23.70 Clock fall time tPCIf — 4 — 1.5 ns 23.70 
 Output data delay time tPCIVAL — 10 — 10 ns 23.71 IDSEL Input hold time tPCIH 1 — 1 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 AD31–AD0 Output data delay time tPCIVAL — 10 — 10 ns 23.71 C/–C/ Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 Input hold time tPCIH 1 — 1 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 Output data delay time tPCIVAL — 10 — 10 ns 23.71 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 12 ns 23.71 Input hold time tPCIH 1 — 1 — ns 23.72 Input setup time tPCISU 3 — 3 — ns 23.72 Tri-state drive delay time tPCION — 10 — 10 ns 23.71 Tri-state high-impedance delay time tPCIOFF — 12 — 12 ns 23.71 PAR 
 
 
    


/  
/ MD9 
/ MD10 
/ /
 –  

 Rev. 3.0, 04/02, page 1024 of 1064 tPCICYC tPCIHIGH VH tPCILOW VH VH 0.5VDDQ 0.5VDDQ VL VL tPCIr tPCIf Figure 23.70 PCI Clock Input Timing 0.4VDDQ PCICLK tPCIVAL 0.4VDDQ Output delay 3-state output tPCION tPCIOFF Figure 23.71 Output Signal Timing Rev. 3.0, 04/02, page 1025 of 1064 PCICLK 0.4VDDQ tPCISU tPCIH 0.4VDDQ Input 0.4VDDQ Figure 23.72 Output Signal Timing Table 23.32 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1) HD6417751RBP240, HD6417751RBP200, HD6417751RF240, HD6417751RF200: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to 75
C, CL = 30 pF Pin 
/MD9 
/MD10 
 –  Item Symbol Min Max Unit Figure Output data delay time tPCIPORTD — 10 ns 23.73 Input hold time tPCIPORTH 1.5 — ns 23.73 Input setup time tPCIPORTS 3.5 — ns 23.73 Output data delay time tPCIPORTD — 10 ns 23.73 Table 23.33 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2) HD6417751BP167, HD6417751F167: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –20 to 75
C, CL = 30 pF HD6417751BP167I, HD6417751F167I: VDDQ = 3.0 to 3.6 V, VDD = 1.8 V, Ta = –40 to 85
C, CL = 30 pF Pin 
/MD9 
/MD10 
 –  Item Symbol Min Max Unit Figure Output data delay time tPCIPORTD — 10 ns 23.73 Input hold time tPCIPORTH 1.5 — ns 23.73 Input setup time tPCIPORTS 3.5 — ns 23.73 Output data delay time tPCIPORTD — 10 ns 23.73 Rev. 3.0, 04/02, page 1026 of 1064 Table 23.34 PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings in Non-Host Mode) HD6417751VF133: VDDQ = 3.0 to 3.6 V, VDD = 1.5 V typ, Ta = –20 to +75
C, CL = 30 pF, PLL2 on Pin 
/MD9 
/MD10 
 –  Item Symbol Min Max Unit Figure Output data delay time tPCIPORTD — 10 ns 23.73 Input hold time tPCIPORTH 1.5 — ns 23.73 Input setup time tPCIPORTS 3.5 — ns 23.73 Output data delay time tPCIPORTD — 10 ns 23.73 CKIO tPCIPORTS tPCIPORTH (read) tPCIPORTD tPCIPORTD (write) Figure 23.73 I/O Port Input/Output Timing Rev. 3.0, 04/02, page 1027 of 1064 23.3.5 AC Characteristic Test Conditions The AC characteristic test conditions are as follows:  Input/output signal reference level: 1.5 V (VDDQ = 3.3 ±0.3 V)  Input pulse level: VSSQ–3.0 V (VSSQ–VDDQ for
, 
, NMI, and 
/BRKACK)  Input rise/fall time: 1 ns The output load circuit is shown in figure 23.74 IOL DUT output LSI output pin VREF CL IOH Notes: 1. CL is the total value, including the capacitance of the test jig, etc. The capacitance of each pin is set to 30 pF. 2. IOL and IOH values are as shown in table 23.11, Permissible Output Currents. Figure 23.74 Output Load Circuit Rev. 3.0, 04/02, page 1028 of 1064 23.3.6 Change in Delay Time Based on Load Capacitance Figure 23.74 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larger than the stipulated value (30 pF) is connected to the LSI pins. When connecting an external device with a load capacitance exceeding the regulation, use the chart in figure 23.74 as reference for system design. Note that if the load capacitance to be connected exceeds the range shown in figure 23.75 the graph will not be a straight line. +4.0 ns Delay time +3.0 ns +2.0 ns +1.0 ns +0.0 ns +0 pF +25 pF +50 pF Load capacitance Figure 23.75 Load CapacitanceDelay Time Rev. 3.0, 04/02, page 1029 of 1064 Rev. 3.0, 04/02, page 1030 of 1064 Appendix A Address List Table A.1 Address List Module Register Area 7 1 P4 Address Address* Power-On Size Reset Manual Reset SynchroStand- nization Sleep by Clock PCIC PCIMEM H'FD00 0000 H'FD00 0000 8, to to 16, H'FDFF FFFF H'FDFF FFFF 32 According to PCI memory space INTC INTPRI00 H'FE08 0000 H'1E08 0000 32 H'0000 0000 Held Held Held Pclk INTC INTREQ00 H'FE08 0020 H'1E08 0020 32 H'0000 0000 Held Held Held Pclk INTC INTMSK00 H'FE08 0040 H'1E08 0040 32 H'0000 03FF Held Held Held Pclk INTC INTMSKCLR H'FE08 0060 H'1E08 0060 32 00 Write-only CPG CLKSTP00 H'0000 0000 Held CPG CLKSTPCLR H'FE0A 0008 H'1E0A 0008 32 00 Write-only TMU TSTR2 H'FE10 0004 H'1E10 0004 8 H'00 Held Held Held Pclk TMU TCOR3 H'FE10 0008 H'1E10 0008 32 H'FFFF FFFF Held Held Held Pclk TMU TCNT3 H'FE10 000C H'1E10 000C 32 H'FFFF FFFF Held Held Held Pclk TMU TCR3 H'FE10 0010 H'1E10 0010 16 H'0000 Held Held Held Pclk TMU TCOR4 H'FE10 0014 H'1E10 0014 32 H'FFFF FFFF Held Held Held Pclk TMU TCNT4 H'FE10 0018 H'1E10 0018 32 H'FFFF FFFF Held Held Held Pclk TMU TCR4 H'FE10 001C H'1E10 001C 16 H'0000 Held Held Held Pclk PCIC PCICONF0 H'FE20 0000 H'1E20 0000 32 H'35051054 Held (SH7751)/ H'350E1054 (SH7751R) Held Held Pclk PCIC PCICONF1 H'FE20 0004 H'1E20 0004 32 H'02900080 Held Held Held Pclk PCIC PCICONF2 H'FE20 0008 H'1E20 0008 32 Undefined Held Held Held Pclk PCIC PCICONF3 H'FE20 000C H'1E20 000C 32 H'00000000 Held Held Held Pclk PCIC PCICONF4 H'FE20 0010 H'1E20 0010 32 H'00000001 Held Held Held Pclk PCIC PCICONF5 H'FE20 0014 H'1E20 0014 32 H'00000000 Held Held Held Pclk PCIC PCICONF6 H'FE20 0018 H'1E20 0018 32 H'00000000 Held Held Held Pclk H'FE0A 0000 H'1E0A 0000 32 Pclk Pclk Held Held Pclk Pclk Rev. 3.0, 04/02, page 1031 of 1064 SynchroStand- nization Clock Sleep by Module Register PCIC PCICONF7 H'FE20 001C H'1E20 001C 32 H'00000000 Held Held Held Pclk PCIC PCICONF8 H'FE20 0020 H'1E20 0020 32 H'00000000 Held Held Held Pclk PCIC PCICONF9 H'FE20 0024 H'1E20 0024 32 H'00000000 Held Held Held Pclk PCIC PCICONF10 H'FE20 0028 H'1E20 0028 32 H'00000000 Held Held Held Pclk PCIC PCICON111 H'FE20 002C H'1E20 002C 32 Undefined Held Held Held Pclk PCIC PCICONF12 H'FE20 0030 H'1E20 0030 32 H'00000000 Held Held Held Pclk PCIC PCICONF13 H'FE20 0034 H'1E20 0034 32 H'00000040 Held Held Held Pclk PCIC PCICONF14 H'FE20 0038 H'1E20 0038 32 H'00000000 Held Held Held Pclk PCIC PCICONF15 H'FE20 003C H'1E20 003C 32 H'00000100 Held Held Held Pclk PCIC PCICONF16 H'FE20 0040 H'1E20 0040 32 H'00010001 Held Held Held Pclk PCIC PCICONF17 H'FE20 0044 H'1E20 0044 32 H'00000000 Held Held Held Pclk PCIC PCICR H'FE20 0100 H'1E20 0100 32 H'00000000 Held Held Held Pclk PCIC PCILSR0 H'FE20 0104 H'1E20 0104 32 H'00000000 Held Held Held Pclk PCIC PCILSR1 H'FE20 0108 H'1E20 0108 32 H'00000000 Held Held Held Pclk PCIC PCILAR0 H'FE20 010C H'1E20 010C 32 H'00000000 Held Held Held Pclk PCIC PCILAR1 H'FE20 0110 H'1E20 0110 32 H'00000000 Held Held Held Pclk PCIC PCIINT H'FE20 0114 H'1E20 0114 32 H'00000000 Held Held Held Pclk PCIC PCIINTM H'FE20 0118 H'1E20 0118 32 H'00000000 Held Held Held Pclk PCIC PCIALR H'FE20 011C H'1E20 011C 32 Undefined Held Held Held Pclk PCIC PCICLR H'FE20 0120 H'1E20 0120 32 Undefined Held Held Held Pclk PCIC PCIAINT H'FE20 0130 H'1E20 0130 32 H'00000000 Held Held Held Pclk PCIC PCIAINTM H'FE20 0134 H'1E20 0134 32 H'00000000 Held Held Held Pclk PCIC PCIBLLR H'FE20 0138 H'1E20 0138 32 Undefined Held Held Held Pclk PCIC PCIDMABT H'FE20 0140 H'1E20 0140 32 H'00000000 Held Held Held Pclk PCIC PCIDPA0 H'FE20 0180 H'1E20 0180 32 H'00000000 Held Held Held Pclk PCIC PCIDLA0 H'FE20 0184 H'1E20 0184 32 H'00000000 Held Held Held Pclk PCIC PCIDTC0 H'FE20 0188 H'1E20 0188 32 H'00000000 Held Held Held Pclk PCIC PCIDCR0 H'FE20 018C H'1E20 018C 32 H'00000000 Held Held Held Pclk PCIC PCIDPA1 H'FE20 0190 H'1E20 0190 32 H'00000000 Held Held Held Pclk PCIC PCIDLA1 H'FE20 0194 H'1E20 0194 32 H'00000000 Held Held Held Pclk PCIC PCIDTC1 H'FE20 0198 H'1E20 0198 32 H'00000000 Held Held Held Pclk Rev. 3.0, 04/02, page 1032 of 1064 Power-On Size Reset Manual Reset Area 7 1 P4 Address Address* Power-On Size Reset Manual Reset SynchroStand- nization Clock Sleep by Module Register Area 7 1 P4 Address Address* PCIC PCIDCR1 H'FE20 019C H'1E20 019C 32 H'00000000 Held Held Held Pclk PCIC PCIDPA2 H'FE20 01A0 H'1E20 01A0 32 H'00000000 Held Held Held Pclk PCIC PCIDLA2 H'FE20 01A4 H'1E20 01A4 32 H'00000000 Held Held Held Pclk PCIC PCIDTC2 H'FE20 01A8 H'1E20 01A8 32 H'00000000 Held Held Held Pclk PCIC PCIDCR2 H'FE20 01AC H'1E20 01AC 32 H'00000000 Held Held Held Pclk PCIC PCIDPA3 H'FE20 01B0 H'1E20 01B0 32 H'00000000 Held Held Held Pclk PCIC PCIDLA3 H'FE20 01B4 H'1E20 01B4 32 H'00000000 Held Held Held Pclk PCIC PCIDTC3 H'FE20 01B8 H'1E20 01B8 32 H'00000000 Held Held Held Pclk PCIC PCIDCR3 H'FE20 01BC H'1E20 01BC 32 H'00000000 Held Held Held Pclk PCIC PCIPAR H'FE20 01C0 H'1E20 01C0 32 Undefined Held Held Held Pclk PCIC PCIMBR H'FE20 01C4 H'1E20 01C4 32 Undefined Held Held Held Pclk PCIC PCIIOBR H'FE20 01C8 H'1E20 01C8 32 Undefined Held Held Held Pclk PCIC PCIPINT H'FE20 01CC H'1E20 01CC 32 H'00000000 Held Held Held Pclk PCIC PCIPINTM H'FE20 01D0 H'1E20 01D0 32 H'00000000 Held Held Held Pclk PCIC PCICLKR H'FE20 01D4 H'1E20 01D4 32 H'00000000 Held Held Held Pclk PCIC PCIBCR1 H'FE20 01E0 H'1E20 01E0 32 H'00000000 Held Held Held Pclk PCIC PCIBCR2 H'FE20 01E4 H'1E20 01E4 32 H'00003FFC Held Held Held Pclk PCIC PCIBCR3 H'FE20 01F8 H'1E20 01F8 32 H'0000 0001 Held Held Held Pclk PCIC PCIWCR1 H'FE20 01E8 H'1E20 01E8 32 H'7777 7777 Held Held Held Pclk PCIC PCIWCR2 H'FE20 01EC H'1E20 01EC 32 H'FFFE EFFF Held Held Held Pclk PCIC PCIWCR3 H'FE20 01F0 H'1E20 01F0 32 H'0777 7777 Held Held Held Pclk PCIC PCIMCR H'FE20 01F4 H'1E20 01F4 32 H'0000 0000 Held Held Held Pclk PCIC PCIPCTR H'FE20 0200 H'1E20 0200 32 H'00000000 Held Held Held Pclk PCIC PCIPDTR H'FE20 0204 H'1E20 0204 32 H'00000000 Held Held Held Pclk PCIC PCIPDR H'FE20 0220 H'1E20 0220 32 Undefined Held Held Held Pclk PCIC PCIIO H'FE24 0000 H'1E24 0000 8, to to 16, H'FE27 FFFF H'1E27 FFFF 32 According to PCI I/O space Pclk Rev. 3.0, 04/02, page 1033 of 1064 SynchroStand- nization Clock Sleep by Module Register CCN PTEH H'FF00 0000 H'1F00 0000 32 Undefined Undefined Held Held Iclk CCN PTEL H'FF00 0004 H'1F00 0004 32 Undefined Undefined Held Held Iclk CCN TTB H'FF00 0008 H'1F00 0008 32 Undefined Undefined Held Held Iclk CCN TEA H'FF00 000C H'1F00 000C 32 Undefined Held Held Held Iclk CCN MMUCR H'FF00 0010 H'1F00 0010 32 H'0000 0000 H'0000 0000 Held Held Iclk CCN BASRA H'FF00 0014 H'1F00 0014 8 Undefined Held Held Held Iclk CCN BASRB H'FF00 0018 H'1F00 0018 8 Undefined Held Held Held Iclk CCN CCR H'FF00 001C H'1F00 001C 32 H'0000 0000 H'0000 0000 Held Held Iclk CCN TRA H'FF00 0020 H'1F00 0020 32 Undefined Held Held Iclk CCN EXPEVT H'FF00 0024 H'1F00 0024 32 H'0000 0000 H'0000 0020 Held Held Iclk CCN INTEVT H'FF00 0028 H'1F00 0028 32 Undefined Undefined Held Held Iclk CCN PTEA H'FF00 0034 H'1F00 0034 32 Undefined Undefined Held Held Iclk CCN QACR0 H'FF00 0038 H'1F00 0038 32 Undefined Undefined Held Held Iclk CCN QACR1 H'FF00 003C H'1F00 003C 32 Undefined Undefined Held Held Iclk UBC BARA H'FF20 0000 H'1F20 0000 32 Undefined Held Held Held Iclk UBC BAMRA H'FF20 0004 H'1F20 0004 8 Undefined Held Held Held Iclk UBC BBRA H'FF20 0008 H'1F20 0008 16 H'0000 Held Held Held Iclk UBC BARB H'FF20 000C H'1F20 000C 32 Undefined Held Held Held Iclk UBC BAMRB H'FF20 0010 H'1F20 0010 8 Undefined Held Held Held Iclk UBC BBRB H'FF20 0014 H'1F20 0014 16 H'0000 Held Held Held Iclk UBC BDRB H'FF20 0018 H'1F20 0018 32 Undefined Held Held Held Iclk UBC BDMRB H'FF20 001C H'1F20 001C 32 Undefined Held Held Held Iclk UBC BRCR H'FF20 0020 H'1F20 0020 16 H'0000* Held Held Held Iclk BSC BCR1 H'FF80 0000 H'1F80 0000 32 H'0000 0000 Held Held Held Bclk BSC BCR2 H'FF80 0004 H'1F80 0004 16 H'3FFC Held Held Held Bclk BSC BCR3 H'FF80 0050 H'1F80 0050 16 H'0000 Held Held Held Bclk BSC BCR4 H'FE0A 00F0 H'1E0A 00F0 32 H'0000 0000 Held Held Held Bclk BSC WCR1 H'FF80 0008 H'1F80 0008 32 H'7777 7777 Held Held Held Bclk BSC WCR2 H'FF80 000C H'1F80 000C 32 H'FFFE EFFF Held Held Held Bclk BSC WCR3 H'FF80 0010 H'1F80 0010 32 H'0777 7777 Held Held Held Bclk Rev. 3.0, 04/02, page 1034 of 1064 Power-On Size Reset Manual Reset Area 7 1 P4 Address Address* 2 Undefined Power-On Size Reset Manual Reset SynchroStand- nization Clock Sleep by Module Register Area 7 1 P4 Address Address* BSC MCR H'FF80 0014 H'1F80 0014 32 H'0000 0000 Held Held Held Bclk BSC PCR H'FF80 0018 H'1F80 0018 16 H'0000 Held Held Held Bclk BSC RTCSR H'FF80 001C H'1F80 001C 16 H'0000 Held Held Held Bclk BSC RTCNT H'FF80 0020 H'1F80 0020 16 H'0000 Held Held Held Bclk BSC RTCOR H'FF80 0024 H'1F80 0024 16 H'0000 Held Held Held Bclk BSC RFCR H'FF80 0028 H'1F80 0028 16 H'0000 Held Held Held Bclk BSC PCTRA H'FF80 002C H'1F80 002C 32 H'0000 0000 Held Held Held Bclk BSC PDTRA H'FF80 0030 H'1F80 0030 16 Undefined Held Held Held Bclk BSC PCTRB H'FF80 0040 H'1F80 0040 32 H'0000 0000 Held Held Held Bclk BSC PDTRB H'FF80 0044 H'1F80 0044 16 Undefined Held Held Held Bclk BSC GPIOIC H'FF80 0048 H'1F80 0048 16 H'0000 0000 Held Held Held Bclk BSC SDMR2 H'FF90 xxxx H'1F90 xxxx 8 Write-only BSC SDMR3 H'FF94 xxxx H'1F94 xxxx 8 DMAC SAR0 H'FFA0 0000 H'1FA0 0000 32 Undefined Undefined Held Held Bclk DMAC DAR0 H'FFA0 0004 H'1FA0 0004 32 Undefined Undefined Held Held Bclk Undefined Bclk Bclk DMAC DMATCR0 H'FFA0 0008 H'1FA0 0008 32 Undefined Held Held Bclk DMAC CHCR0 H'FFA0 000C H'1FA0 000C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR1 H'FFA0 0010 H'1FA0 0010 32 Undefined Undefined Held Held Bclk DMAC DAR1 H'FFA0 0014 H'1FA0 0014 32 Undefined Undefined Held Held Bclk DMAC DMATCR1 H'FFA0 0018 H'1FA0 0018 32 Undefined Undefined Held Held Bclk DMAC CHCR1 H'FFA0 001C H'1FA0 001C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR2 H'FFA0 0020 H'1FA0 0020 32 Undefined Undefined Held Held Bclk DMAC DAR2 H'FFA0 0024 H'1FA0 0024 32 Undefined Undefined Held Held Bclk DMAC DMATCR2 H'FFA0 0028 H'1FA0 0028 32 Undefined Undefined Held Held Bclk DMAC CHCR2 H'FFA0 002C H'1FA0 002C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR3 H'FFA0 0030 H'1FA0 0030 32 Undefined Undefined Held Held Bclk DMAC DAR3 H'FFA0 0034 H'1FA0 0034 32 Undefined Undefined Held Held Bclk DMAC DMATCR3 H'FFA0 0038 H'1FA0 0038 32 Undefined Undefined Held Held Bclk DMAC CHCR3 H'FFA0 003C H'1FA0 003C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC DMAOR H'FFA0 0040 H'1FA0 0040 32 H'0000 0000 H'0000 0000 Held Held Bclk Rev. 3.0, 04/02, page 1035 of 1064 Power-On Size Reset Manual Reset SynchroStand- nization Clock Sleep by Module Register Area 7 1 P4 Address Address* DMAC SAR4 H'FFA0 0050 H'1FA0 0050 32 Undefined Undefined Held Held Bclk DMAC DAR4 H'FFA0 0054 H'1FA0 0054 32 Undefined Undefined Held Held Bclk DMAC DMATCR4 H'FFA0 0058 H'1FA0 0058 32 Undefined Undefined Held Held Bclk DMAC CHCR4 H'FFA0 005C H'1FA0 005C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR5 H'FFA0 0060 H'1FA0 0060 32 Undefined Undefined Held Held Bclk DMAC DAR5 H'FFA0 0064 H'1FA0 0064 32 Undefined Undefined Held Held Bclk Undefined DMAC DMATCR5 H'FFA0 0068 H'1FA0 0068 32 Undefined Held Held Bclk DMAC CHCR5 H'FFA0 006C H'1FA0 006C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR6 H'FFA0 0070 H'1FA0 0070 32 Undefined Undefined Held Held Bclk DMAC DAR6 H'FFA0 0074 H'1FA0 0074 32 Undefined Undefined Held Held Bclk DMAC DMATCR6 H'FFA0 0078 H'1FA0 0078 32 Undefined Undefined Held Held Bclk DMAC CHCR6 H'FFA0 007C H'1FA0 007C 32 H'0000 0000 H'0000 0000 Held Held Bclk DMAC SAR7 H'FFA0 0080 H'1FA0 0080 32 Undefined Undefined Held Held Bclk DMAC DAR7 H'FFA0 0084 H'1FA0 0084 32 Undefined Undefined Held Held Bclk DMAC DMATCR7 H'FFA0 0088 H'1FA0 0088 32 Undefined Undefined Held Held Bclk DMAC CHCR7 H'FFA0 008C H'1FA0 008C 32 H'0000 0000 H'0000 0000 Held Held Bclk CPG FRQCR H'FFC0 0000 H'1FC0 0000 16 * CPG STBCR H'FFC0 0004 H'1FC0 0004 8 CPG WTCNT 2 Held Held Held Pclk H'00 Held Held Held Pclk 3 H'FFC0 0008 H'1FC0 0008 8/16* H'00 Held Held Held Pclk 3 CPG WTCSR H'FFC0 000C H'1FC0 000C 8/16* H'00 Held Held Held Pclk CPG STBCR2 H'FFC0 0010 H'1FC0 0010 8 H'00 Held Held Held Pclk RTC R64CNT H'FFC8 0000 H'1FC8 0000 8 Held Held Held Held Pclk RTC RSECCNT H'FFC8 0004 H'1FC8 0004 8 Held Held Held Held Pclk RTC RMINCNT H'FFC8 0008 H'1FC8 0008 8 Held Held Held Held Pclk RTC RHRCNT H'FFC8 000C H'1FC8 000C 8 Held Held Held Held Pclk RTC RWKCNT H'FFC8 0010 H'1FC8 0010 8 Held Held Held Held Pclk RTC RDAYCNT H'FFC8 0014 H'1FC8 0014 8 Held Held Held Held Pclk RTC RMONCNT H'FFC8 0018 H'1FC8 0018 8 Held Held Held Held Pclk RTC RYRCNT H'FFC8 001C H'1FC8 001C 16 Held Held Held Held Pclk Held Held Held Pclk RTC RSECAR H'FFC8 0020 H'1FC8 0020 8 Rev. 3.0, 04/02, page 1036 of 1064 Held* 2 SynchroStand- nization Clock Sleep by Module Register RTC RMINAR H'FFC8 0024 H'1FC8 0024 8 Held* 2 Held Held Held Pclk RTC RHRAR H'FFC8 0028 H'1FC8 0028 8 Held* 2 Held Held Held Pclk Held* 2 Held Held Held Pclk Held* 2 Held Held Held Pclk Held* 2 Held Held Held Pclk Held Held Pclk RTC RTC RTC RTC RWKAR RDAYAR RMONAR RCR1 Power-On Size Reset Manual Reset Area 7 1 P4 Address Address* H'FFC8 002C H'1FC8 002C 8 H'FFC8 0030 H'1FC8 0030 8 H'FFC8 0034 H'1FC8 0034 8 H'FFC8 0038 H'1FC8 0038 8 H'00* 2 2 H'00* 2 H'00* 2 RTC RCR2 H'FFC8 003C H'1FC8 003C 8 H'09* Held Held Pclk RTC RCR3 H'FFC8 0050 H'1FC8 0050 8 H'00 Held Held Held Pclk RTC RYRAR H'FFC8 0054 H'1FC8 0054 16 Undefined Held Held Held Pclk INTC ICR H'FFD0 0000 H'1FD0 0000 16 H'0000* Held Held Pclk INTC IPRA H'FFD0 0004 H'1FD0 0004 16 H'0000 H'0000 Held Held Pclk INTC IPRB H'FFD0 0008 H'1FD0 0008 16 H'0000 H'0000 Held Held Pclk INTC IPRC H'FFD0 000C H'1FD0 000C 16 H'0000 H'0000 Held Held Pclk INTC IPRD H'FFD0 0010 H'1FD0 0010 16 H'DA74 H'DA74 Held Held Pclk TMU TOCR H'FFD8 0000 H'1FD8 0000 8 H'00 H'00 Held Held TMU TSTR H'FFD8 0004 H'1FD8 0004 8 H'00 H'00 Held H'00* TMU TCOR0 H'FFD8 0008 H'1FD8 0008 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCNT0 H'FFD8 000C H'1FD8 000C 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCR0 H'FFD8 0010 H'1FD8 0010 16 H'0000 Held Held Pclk TMU TCOR1 H'FFD8 0014 H'1FD8 0014 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCNT1 H'FFD8 0018 H'1FD8 0018 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCR1 H'FFD8 001C H'1FD8 001C 16 H'0000 Held Held Pclk TMU TCOR2 H'FFD8 0020 H'1FD8 0020 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCNT2 H'FFD8 0024 H'1FD8 0024 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TMU TCR2 H'FFD8 0028 H'1FD8 0028 16 H'0000 H'0000 Held Held Pclk TMU TCPR2 H'FFD8 002C H'1FD8 002C 32 Held Held Held Held Pclk SCI SCSMR1 H'FFE0 0000 H'1FE0 0000 8 H'00 H'00 Held H'00 Pclk SCI SCBRR1 H'FFE0 0004 H'1FE0 0004 8 H'FF H'FF Held H'FF Pclk SCI SCSCR1 H'FFE0 0008 H'1FE0 0008 8 H'00 H'00 Held H'00 Pclk SCI SCTDR1 H'FFE0 000C H'1FE0 000C 8 H'FF H'FF Held H'FF Pclk 2 H'0000* H'0000 H'0000 2 Pclk 2 Pclk Rev. 3.0, 04/02, page 1037 of 1064 Power-On Size Reset SynchroStand- nization Clock Sleep by Module Register Area 7 1 P4 Address Address* Manual Reset SCI SCSSR1 H'FFE0 0010 H'1FE0 0010 8 H'84 H'84 Held H'84 Pclk SCI SCRDR1 H'FFE0 0014 H'1FE0 0014 8 H'00 H'00 Held H'00 Pclk SCI SCSCMR1 H'FFE0 0018 H'1FE0 0018 8 H'00 Held H'00 H'00 2 SCI SCSPTR1 H'FFE0 001C H'1FE0 001C 8 H'00* SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16 H'0000 SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8 SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16 SCIF SCFTDR2 SCIF H'00* 2 Pclk 2 Held H'00* H'0000 Held Held Pclk H'FF H'FF Held Held Pclk H'0000 H'0000 Held Held Pclk H'FFE8 000C H'1FE8 000C 8 Undefined Undefined Held Held Pclk SCFSR2 H'FFE8 0010 H'1FE8 0010 16 H'0060 H'0060 Held Held Pclk SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8 Undefined Undefined Held Held Pclk SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16 H'0000 H'0000 Held Held Pclk SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16 H'0000 H'0000 Held Held Pclk Held Held Pclk Held Held Pclk 2 2 Pclk SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16 H'0000* H'0000* SCIF SCLSR2 H'FFE8 0024 H'1FE8 0024 16 H'0000 H'0000 H-UDI SDIR H'FFF0 0000 H'1FF0 0000 16 H'FFFF* Held Held Held Pclk H-UDI SDDR H'FFF0 0008 H'1FF0 0008 32 Held Held Held Held Pclk Hi-UDI SDINT H'FFF0 0014 H'1FF0 0014 16 H'0000 Held Held Held Pclk 2 Notes: *1 With control registers, the above addresses in the physical page number field can be accessed by means of a TLB setting. When these addresses are set directly without using the TLB, operations are limited. *2 Includes undefined bits. See the descriptions of the individual modules. *3 Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. Rev. 3.0, 04/02, page 1038 of 1064 Appendix B Package Dimensions Unit: mm 30.6 ± 0.2 28 192 129 128 256 65 *Dimension including the plating thickness Base material dimension 1.4 1.3 0˚ – 8˚ + 0.10 0.08 0.40 – 0.15 0.11 M 3.20 64 * 0.18 ± 0.05 0.16 ± 0.04 * 0.17 ± 0.05 0.15 ± 0.04 1 3.95 Max 30.6 ± 0.2 0.4 193 0.5 ± 0.2 Hitachi Code JEDEC JEITA Mass (reference value) FP-256G — Conforms 5.4 g Figure B.1 Package Dimensions (256-pin QFP) Rev. 3.0, 04/02, page 1039 of 1064 Unit: mm 27.0 A B 0.20 (× 4) 27.0 C 0.635 W 2.1 0.6 ± 0.1 0.35 C 0.20 C 1.27 Y A 1.27 0.635 V U T R P N M L K J H G F E D C B A 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 256 × φ0.75 ± 0.15 0.30 M C A B 0.10 M C Details of the part A Hitachi Code JEDEC JEITA Mass (reference value) Figure B.2 Package Dimensions (256-pin BGA) Rev. 3.0, 04/02, page 1040 of 1064 BP-256 — — 3.0 g Appendix C Mode Pin Settings The MD10–MD0 pin values are input in the event of a power-on reset via the
 pin. Clock Modes Table C.1 Clock Operating Modes (SH7751) External Pin Combination Clock Operating Mode MD2 MD1 0 0 0 1 1 2 3 4 1 0 5 Table C.2 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 Off On On 6 3/2 3/2 H'0E1A 1 Off On On 6 1 1 H'0E23 0 On On On 3 1 1/2 H'0E13 1 Off On On 6 2 1 H'0E13 0 On On On 3 3/2 3/4 H'0E0A 1 Off On On 6 3 3/2 H'0E0A External Pin Combination MD2 MD1 0 0 0 1 PLL1 PLL2 CPU Clock Bus Clock Peripheral Module Clock FRQCR Initial Value 0 On (
12) On 12 3 3 H'0E1A 1 On (
12) On 12 3/2 3/2 H'0E2C 0 On (
6) On 6 2 1 H'0E13 On (
12) On 12 4 2 H'0E13 0 0 On (
6) On 6 3 3/2 H'0E0A 1 On (
12) On 1 0 OFF (
6) OFF 3 1 MD0 Frequency (vs. Input Clock) 1 1 2 5 6 1/2 Frequency Divider Clock Operating Modes (SH7751R) Clock Operating Mode 4 MD0 Frequency (vs. Input Clock) 12 6 3 H'0E0A 1 1/2 1/2 H'0808 Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode. 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (fEX) and the CKIO clock output (fOP) in section 23.3.1, Clock and Control Signal Timing. Rev. 3.0, 04/02, page 1041 of 1064 Table C.3 Area 0 Memory Map and Bus Width Pin Value MD6 MD4 MD3 Memory Type Bus Width 0 0 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 Reserved (Cannot be used) Reserved (Cannot be used) 1 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 MPX interface 32 bits 0 0 Reserved (Cannot be used) Reserved (Cannot be used) 1 SRAM interface 8 bits 0 SRAM interface 16 bits 1 SRAM interface 32 bits 1 1 Table C.4 Endian Pin Value MD5 Endian 0 Big endian 1 Little endian Table C.5 Master/Slave Pin Value MD7 Master/Slave 0 Slave 1 Master Table C.6 Clock Input Pin Value MD8 Clock Input 0 External input clock 1 Crystal resonator Rev. 3.0, 04/02, page 1042 of 1064 Table C.7 PCI Mode Pin Value Mode MD10 MD9 Mode 0 0 0 PCI host with external clock input 1 0 1 PCI host with bus clock 2 1 0 PCI non-host with external clock input 3 1 1 PCI disabled Note: When exiting standby mode or hardware standby mode using a power-on reset, do not change the PCI mode. Rev. 3.0, 04/02, page 1043 of 1064 Appendix D Pin Functions D.1 Pin States Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common) Reset (Power-On) Reset (Manual) Pin Name I/O Master Slave Master Slave D0–D31 I/O Z Z* A2–A17, A0–A25
 /
 
 /  CKE  –

/ 
 RD/

 /DQM3 /DQM2 /DQM1 /DQM0 /
 /
 /
 16 Z 15 16 Z* 9 15 Bus Standby Released 16 Z* 16 Z 15 Z* 15 7 Hardware Standby Notes O Z Z Z* O* Z* Z* O* Z* Z I I I I I I I I O H H H O Z H 14 I PI PI I* I* O H PZ H Z* O H O H O H H PZ PZ 6 O* H O* 6 15 H Z* 6 H 14 15 5 Z* O* 15 5 Z* O* Z 15 5 15 5 Z* O* Z 15 7 Z* 15 Z Z* O* Z H Z* O H O H O H PZ PZ PZ 6 O* 6 O* O* O* O H O H DACK1–DACK0 O L MD7/CTS2 I/O I* MD6/ I I* MD5 I I* MD4/ I/O* MD3/ I/O* PZ PZ L I* 19 I* 19 I* I* 3 I* 6 O* 6 O* I* 19 I* 19 Z* I* 19 I* Z* H I Z* O* Z* O* Z 15 5 Z* O* 15 5 Z* O* Z 15 15 5 Z* O* 15 5 Z* O* Z 15 15 5 Z* O* 15 5 Z* O* Z 15 Z* O* 15 5 Z* O* 15 5 Z 15 15 5 Z* O* 15 5 Z* O* Z 15 15 5 Z* O* 15 5 Z* O* Z 15 15 5 15 5 Z* O* Z 13 8 O Z* Z* Z* Z* O* Z* O* I* 19 I* 15 Z* 14 19 I* 5 Z* I* 15 14 15 Z* 13 Z 5 L 19 19 Rev. 3.0, 04/02, page 1044 of 1064 O* L 19 2 6 14 Z* 15 Z* PZ PZ Z* H* 15 15 Z* H H PZ I* 6 O H 14 6 O O Z* O* 15 O* Z O* Z* H* PZ 6 Z 6 15 PZ I* I 15 Z* 7 H PI 7 15 H PI I 15 Z* H* L O I I* 15 O 14 14 13 I* O* 14 I* 15 Z* 15 Z* H Z* 15 Z* 13 8 14 Z DMAC 13 Z SCIF 14 I PCMCIA (I/O) I* O I* 15 Z* 15 Z 15 Z PCMCIA 15 Z PCMCIA Z* 15 15 7 15 Z* H* Z* H* Z* 15 7 Z* Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common) (cont) Reset (Power-On) Reset (Manual) Pin Name I/O Master Slave Master Slave CKIO O O O ZO* ZO* STATUS1–STATUS0 O O O O O 
–
 PI PI I* I 10 14 I* I* PI PI I* I PI PI I* DRAK1–DRAK0 O L L 19 L 19 RXD I PI PI I* MD1/TXD2 I/O I* MD2/RXD2 TxD I 19 19 I* PI 19 I* 19 I* 13 I* 13 Z* 13 I* 13 I/O PZ PZ MD8/RTS2 I/O 19 I* 19 I* I* TCLK I/O PI PI TDO O PO TMS I TCK TDI 
 
  CA Z* O I* 13 Z* O I INTC 13 I DMAC I* 8 I* 13 INTC I* 13 13 I 14 13 OI* 13 8 Z* O* Z* 11 ZO* 14 14 13 Z* O* I* Z I* 13 13 10 O 13 I* I* PI I* 13 I* I/O I* I* I* ZO* 14 13 L I/O 10 I* 14 13 MD0/SCK2 SCK 14 13 I DREQ1–DREQ0 ZO* O I* 14 NMI 10 Hardware Standby Notes Bus Standby Released 13 I* O 13 13 8 13 I SCI Z SCI Z SCIF I* I SCIF O 13 Z* O 13 I* 13 8 Z SCI 13 I* O Z SCIF I* O 13 Z TMU PO PO Z H-UDI PI PI PI I H-UDI PI PI PI PI I H-UDI PI PI PI PI I H-UDI PI PI PI PI PI I H-UDI PI PI PI PI PI I 13 I* I* 13 PO PI I I Z* O* SCIF 13 8 I* Z* O* I* O Z* O* Z DMAC 13 I* 13 8 OI* Z* O* Z 13 13 13 13 I* Z 8 O* I* 13 I* O PO PO PI PI PI PI PI PI I PI I PI 14 14 13 13 14 13 14 I PI PI I* I* I* I* I I I I I I I I I Rev. 3.0, 04/02, page 1045 of 1064 Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable) Reset (Power On) Reset (Manual) Standby Reset (Software) NonHost Host NonHost Host NonHost Host Hardware Standby Notes Pin Name I/O NonHost Host AD31–AD31 I/O L Z IOZ IOZ K Z L Z Z – I/O L Z IOZ IOZ K Z L Z Z PAR I/O L Z IOZ IOZ K Z L Z Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PZ PZ Z 12 PI PZ Z 12, 18 (IO* * ) 



   
 
 
 
 – 
  
 /  –  /
  PCICLK 12 IOZ* 12 IOZ* I/O PZ PZ IOZ* I/O PZ PZ IOZ* 12 PZ PZ IZ* I/O PZ PZ IOZ* PZ PZ Z* 12 Z* 12 I/O I/O 12 IZ* 12 12 IOZ* IOZ* IOZ* PZ IOZ* 12 I/O PZ PZ IOZ* I/O PI PZ I* I PI PI O Z O I 12 Z* 12 Z* 12 IOZ* IOZ* PZ PZ Z* Z* 12 12 PZ I/O Z* 12 Z* 12 IOZ* 12 I/O 12 Z* 12 Z* 12 Z* 12 Z* 12 Z* 12 IOZ* Z* 12 Z* 13, 18 (IO* * ) 12 I* 12 I* 12 Z O Z Z I Z* 12 Z* 12 Z* 12, 18 (IO* * ) I* 12 I* PI PI Z Z (K) K Z (K) Z Z (K) Z O O K K Z H Z I I I I I I I Z I* 12 
 O L L K K K K L L Z IDSEL I PI I PI I PI I PI I Z PZ PZ Z  O PZ PZ Rev. 3.0, 04/02, page 1046 of 1064 12 ODK ODK * 12 * 12 ODK ODK * 12 * Values in parenthesis are when using PORT Values in parenthesis are when using PORT Table D.3 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) Reset (Power-On) Reset (Manual) HardBus ware Released Standby Notes Pin Name I/O Master Slave Master Slave Standby AD31–AD0 I/O Z Z Z (K) Z (K) Z* (K) Z* (K) Z – — Z Z Z Z Z Z Z PAR O Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z — Z Z Z Z Z Z Z O Z Z Z Z Z Z Z O Z Z Z Z Z Z Z 



   
 
 
 
 –
  
  –  17 17 PCICLK — Z Z Z Z Z Z Z 
 O Z Z Z Z Z Z Z IDSEL — Z Z Z Z Z Z Z  — Z Z Z Z Z Z Z Notes: I: O: H: L: Z: K: IZ/IOZ: PZ: PI: ODK: Values in parenthesis are when using PORT Input Output High-level output Low-level output High-impedance Output state held Response to access from PCI Pulled up with a built-in pull-up resistance Input pulled up with a built-in pull-up resistance Open-drain output state held Rev. 3.0, 04/02, page 1047 of 1064 *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 *15 *16 *17 *18 *19 D.2
Output when area 2 DRAM is used. Output when area 5 PCMCIA is used. Output when area 6 PCMCIA is used. Depends on refresh and DMAC operations. Z (I) or O (refresh), depending on register setting (BCR1.HIZCNT). Depends on refresh operation. Z (I) or H (state held), depending on register setting (BCR1.HIZMEM). Z or O, depending on register setting (STBCR.PHZ). Output when refreshing is set. Z or O, depending on register setting (FRQCR.CKOEN). Z or O, depending on register setting (STBCR.STHZ). Pullup, depending on register setting (PCICR.PCIPUP). Pullup, depending on register setting (STBCR.PPU). Pullup, depending on register setting (BCR1.IPUP). Pullup, depending on register setting (BCR1.OPUP). Pullup, depending on register setting (BCR1.DPUP). Pullup, depending on register setting (BCR2.PORTEN). Pullup, depending on register setting (PCIPCTR.PB2PUP to PCIPCTR.PB4PUP). Pullup by on-chip pullup resistor. Note that this cannot be used for pullup of the mode pin during a power-on reset. Pullup or pulldown should be performed externally to the SH-4. Handling of Unused Pins When RTC is not used  EXTAL2: Pull up to 3.3 V  XTAL2: Leave unconnected  VDD-RTC: Power supply  VSS-RTC:
Power supply When PLL1 is not used  VDD-PLL1: Power supply  VSS-PLL1: Power supply
When PLL2 is not used  VDD-PLL2: Power supply  VSS-PLL2: Power supply
When on-chip crystal oscillator is not used  XTAL: Leave unconnected  VDD-CPG: Power supply  VSS-CPG: Power supply Rev. 3.0, 04/02, page 1048 of 1064 Table D.4 Handling of Pins When PCI is Not Used Pin Name I/O Handling AD31–AD31 I/O Pull up to 3.3 V*
–
 I/O Pull up to 3.3 V PAR I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I/O Pull up to 3.3 V I Pull up to 3.3 V O Pull up to 3.3 V   

 
     
 
–
 
 
 –
  
  O Pull up to 3.3 V PCICLK I Pull up to 3.3 V 
 O Leave unconnected IDSEL I Pull up to 3.3 V   O Leave unconnected Note: * When not used as a general-purpose I/O port. Rev. 3.0, 04/02, page 1049 of 1064 Appendix E Synchronous DRAM Address Multiplexing Tables (1) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 0 16M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1050 of 1064 (2) BUS 32 AMX 0 (16M: 512k × 16b × 2) × 2 * AMXEXT 1 16M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 4MB Synchronous DRAM Address Pins Function A14 A13 A20 A20 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1051 of 1064 (3) BUS 32 AMX 1 (16M: 1M × 8b × 2) × 4 * AMXEXT 0 16M, column-addr-9bit SH7751 Series Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A13 A22 A22 A11 BANK selects bank address A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1052 of 1064 (4) BUS 32 AMX 1 (16M: 1M × 8b × 2) × 4 * AMXEXT 1 16M, column-addr-9bit SH7751 Series Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A14 A13 A21 A21 A11 BANK selects bank address A12 A22 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1053 of 1064 (5) BUS 32 AMX 2 (64M: 1M × 16b × 4) × 2 * 64M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 16MB Synchronous DRAM Address Pins Function A16 A15 A23 A23 A13 A14 A22 A22 A12 A13 A21 0 A11 A12 A20 H/L A10 A11 A19 0 A9 A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1054 of 1064 BANK selects bank address Address precharge setting Address (6) BUS 32 AMX 3 (64M: 2M × 8b × 4) × 4 * 64M, column-addr-9bit SH7751 Series Address Pins RAS Cycle CAS Cycle 32MB Synchronous DRAM Address Pins Function A16 A15 A24 A24 A13 A14 A23 A23 A12 A13 A22 0 A11 A12 A21 H/L A10 A11 A20 0 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used BANK selects bank address Address precharge setting Address Rev. 3.0, 04/02, page 1055 of 1064 (7) BUS 32 AMX 4 (64M: 512k × 32b × 4) × 1 * 64M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 A13 A21 A21 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1056 of 1064 BANK selects bank address (8) BUS 32 AMX 5 (64M: 1M × 32b × 2) × 1 * 64M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 8MB Synchronous DRAM Address Pins Function A15 A14 A22 A22 A12 BANK selects bank address A13 A21 0 A11 A12 A20 H/L A10 Address precharge setting A11 A19 0 A9 Address A10 A18 0 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1057 of 1064 (9) BUS 32 AMX 6 (64M: 4M × 4b × 4) × 8 * (R8M: 4M × 8b × 4) × 4 64M, column-addr-10bit SH7751 Series Address Pins RAS Cycle CAS Cycle 64MB Synchronous DRAM Address Pins Function BANK selects bank address A15 A25 A25 A13 A14 A24 A24 A12 A13 A23 0 A11 A12 A22 H/L A10 Address precharge setting A11 A21 A11 A9 Address A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 A1 Not used A0 Not used Rev. 3.0, 04/02, page 1058 of 1064 (10) BUS 32 AMX 6 (256M: 4M × 16b × 4) × 2 * AMXEXT1 256M, column-addr-9bit SH7751 Series Address Pins RAS Cycle CAS Cycle 64MB Synchronous DRAM Address Pins Function A16 A25 A25 A14 A15 A24 A24 A13 A14 A23 0 A12 A13 A22 0 A11 A12 A21 H/L A10 Address precharge setting A11 A20 0 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 Not used A0 Not used BANK selects bank address Rev. 3.0, 04/02, page 1059 of 1064 (11) BUS 32 AMX 7 (16M: 256k × 32b × 2) × 1 * 16M, column-addr-8bit SH7751 Series Address Pins RAS Cycle CAS Cycle 2MB Synchronous DRAM Address Pins Function A13 A12 A20 A20 A10 BANK selects bank address A11 A19 H/L A9 Address precharge setting A10 A18 0 A8 Address A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 Not used A0 Not used Note: * Example configurations of synchronous DRAM Rev. 3.0, 04/02, page 1060 of 1064 Appendix F Instruction Prefetching and Its Side Effects The SH7751 Series is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 20-byte area of any memory space. If program code is located in these areas, the memory area will be exceeded and a bus access for instruction pre-reading may be initiated. A case in which this is a problem is shown below. Address H'03FFFFF8 H'03FFFFFA Area 0 H'03FFFFFC H'03FFFFFE Area 1 H'04000000 H'04000002 . . . . . ADD R1,R4 JMP @R2 NOP NOP PC (program counter) Instruction prefetch address Figure F.1 Instruction Prefetch Figure F.1 presupposes a case in which the instruction (ADD) indicated by the program counter (PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction. In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1 may be initiated. Instruction Prefetch Side Effects 1. It is possible that an external bus access caused by an instruction prefetch may result in misoperation of an external device, such as a FIFO, connected to the area concerned. 2. If there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. Remedies 1. These illegal instruction fetches can be avoided by using the MMU. 2. The problem can be avoided by not locating program code in the last 20 bytes of any area. Rev. 3.0, 04/02, page 1061 of 1064 Appendix G Power-On and Power-Off Procedures
Power-on  Supply the internal power after supplying power to the I/O, RTC, and CPG.*  Supply power to VDDQ, VDD-RTC, and VDD-CPG simultaneously.  At power-on, the
 signal is low. Normally, supply power to the I/O, RTC, and CPG before (or at the same time as) entering the signal lines (
, 
, MD0 to MD10, and external clock). If the signal lines are entered first, the LSI may be damaged.  Input high level to 
 in compliance with the voltage level of the I/O, RTC, CPG power supply voltage.
Power-off  When turning off the power, there are no restrictions for the timing of
, 
.  Turn off the I/O, RTC, CPG power supply voltage after (or at the same time as)* turning off the internal power supply voltage. Note however that the internal power supply voltage may exceed the I/O, RTC, CPG power supply voltage by a maximum of 0.3 V only when the system is being turned off.  The power supply level must be lowered in compliance with the I/O, RTC, CPG power supply voltage. Note: * 10 ms or less for the HD6417751R.
The ratings and procedures for power-on and power-off are given below. VDDQ = VDD-RTC = VDD-CPG = 0 V The LSI may be damaged if 0.3 V < Vin < VDDQ + 0.3 V 0.3 V < VDD, VDD-PLL1/2 < VDDQ + 0.3 V are not satisfied when VDDQ = VDD-RTC = VDD-CPG. Power-on VDDQ Power-off 2.0 V VDD, VDD-PLL1/2 1.2 V GND ton 0 ≤ ton < 10 ms* toff 0 ≤ toff < 10 ms* Note: * HD6417751R only Figure G.1 Power-On and Power-Off Procedures Rev. 3.0, 04/02, page 1062 of 1064 Appendix H List of Models Table H.1 SH7751 Series Models Product Name Voltage Operating Frequency Model Marking Package SH7751 1.8 V 167 MHz HD6417751BP167 256-pin BGA HD6417751F167 256-pin QFP SH7751R 1.5 V 133 MHz HD6417751VF133 1.5 V 240 MHz HD6417751RBP240 256-pin BGA HD6417751RF240 256-pin QFP HD6417751RBP200 256-pin BGA HD6417751RF200 256-pin QFP 200 MHz Rev. 3.0, 04/02, page 1063 of 1064 Rev. 3.0, 04/02, page 1064 of 1064 SH7751 Series Hardware Manual Publication Date: 1st Edition, April 2000 3rd Edition, April 2002 Published by: Business Planning Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.