H8/300H SERIES Microcontrollers
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applications based on the examples described herein.
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use the products in MEDICAL APPLICATIONS.
Contents
Welcome .... .....................................................................................................1
CPU ........... .....................................................................................................5
Addressing . .....................................................................................................7
Addressing Modes ................................................................................................................. 7
Instruction Set ..................................................................................................9
Arithmetic Instructions .......................................................................................................... 10
Bit Processing........................................................................................................................ 11
Block Move Instruction ......................................................................................................... 12
Software Interrupt.................................................................................................................. 12
CPU States / Low power modes .......................................................................13
Low Power Modes ................................................................................................................. 13
Sleep Mode............................................................................................................................ 13
Software Standby Mode......................................................................................................... 13
Hardware Standby Mode........................................................................................................ 14
Extra Power Down Support - H8 / 3048 ................................................................................. 14
Clock Gearing........................................................................................................................ 15
Exceptions and Interrupts .................................................................................17
Trap Exceptions..................................................................................................................... 18
Interrupt Controller................................................................................................................ 18
H8 / 300 Compatible Mode.................................................................................................... 18
H8 / 300H Advanced Mode.................................................................................................... 18
External Interrupts ................................................................................................................. 18
Interrupt Vectors.................................................................................................................... 18
Interrupt Response Time........................................................................................................ 19
On-chip Memory..............................................................................................21
Flash Memory (F-ZTAT) .................................................................................23
Technology............................................................................................................................ 24
Bus State Controller (BSC) ..............................................................................25
DRAM and PSRAM Interface................................................................................................ 26
Chip Select Generation .......................................................................................................... 27
i
Direct Memory Access Controller (DMAC)..................................................... 29
Short Address Mode .............................................................................................................. 30
Full Address Mode................................................................................................................. 30
DMAC Interrupts................................................................................................................... 30
DMAC Modes ....................................................................................................................... 30
Integrated Timer Unit (ITU) ............................................................................ 33
Output Compare Functions .................................................................................................... 35
Input Capture Functions......................................................................................................... 35
Timer Synchronisation........................................................................................................... 35
PWM Operating Modes ......................................................................................................... 36
Standard PWM Mode ............................................................................................................ 36
AC Motor Control Outputs .................................................................................................... 37
Complementary 6-Phase PWM .............................................................................................. 37
Reset Synchronised PWM...................................................................................................... 38
Phase Counting Mode ............................................................................................................ 38
ITU Interrupts........................................................................................................................ 39
Timing Pattern Controller (TPC) ..................................................................... 41
Stepper Motor Control with the TPC...................................................................................... 41
Watchdog Timer (WDT).................................................................................. 45
Serial Communications Interface (SCI)............................................................ 47
Analogue to Digital Converter (ADC).............................................................. 49
Digital to Analogue Converter (DAC) ......................................................................... 50
H8/300H Summary .......................................................................................... 51
H8/3001 series ....................................................................................................................... 55
H8/3002 series ....................................................................................................................... 56
H8/3003 series ....................................................................................................................... 57
H8/3004 and H8/3005 series .................................................................................................. 58
H8/3032 series ....................................................................................................................... 59
H8/3042 series ....................................................................................................................... 60
H8/3048 series ....................................................................................................................... 61
Packages................................................................................................................................ 62
Ordering Information ....................................................................................... 63
ii
Welcome
to Hitachi's 16-Bit microcontroller family H8/300H.
H8/300H has enjoyed tremendous success since its introduction in 1993 as a successor to
Hitachi's equally successful H8/500 family. Dataquest has found Hitachi's 16-Bit
microcontrollers to be the most successful world-wide as well as in Europe.
SGS
13%
Intel
12%
Siemens
11%
Motorola
21%
NEC
7%
Hitachi
23%
European 16-Bit µC market shares 1995
Others
13%
Source:Dataquest
At Hitachi Europe we think that this success was driven by our strong commitment to be a
leading force in the microcontroller marketplace and our belief that we must listen to our
customer's requirements and then meet these. As H8/300H is the result of combining many
years of experience of Hitachi with the experience of our customers, H8/300H is an excellent
example where this policy has worked for our customers and Hitachi.
The European Electronics Industry demands full service and support.
At Hitachi, we responded by setting up a European engineering and tool design subsidiary 12
years ago: Hitachi Microsystems Europe (HMSE) based in Maidenhead (UK).
HMSE provides our customers with locally designed and supported tools ranging from low cost
evaluation boards to fully featured real time emulators based on IBM-compatible PC's at a
very competitive price. Software ranges from Assembler, an ANSI C-Compiler via a C-level
debugger to HIOS, Hitachi's real time operating system. To speed development HMSE supplies
MakeApp, a tool that sets up peripherals and creates driver routines on the click of a mouse.
HMSE also offers support and engineering resources for customers wishing to use Hitachi's
ASIC capabilities. This also applies to our µCBIC program, enabling our customers to select
one of Hitachi's CPU cores and combine it with peripherals from our library and adding
customer specified logic via VHDL or Verilog.
1
Hitachi also provides two technical help lines with 24 hour response, based in Maidenhead and
Munich, as well as local language application support in Italy, France and Scandinavia.
All of this backed by strong support from third party tool manufacturers, like Hewlett Packard,
Pentica and Lauterbach to name just a few.
H8/300H is part of Hitachi's software compatible H8 product range, which covers a
performance range from 400ns to 50ns cycle time, whilst increasing word length from 8 to 16 bit
and memory space from 64KB to 16MB. This product range offers an industry leading mix of
memory options (including flash), peripherals and performance/power consumption, all of this
being software compatible for protection of our customer’s software investment. Hitachi
produces and ships over 12 million H8 microcontrollers every month, in a vast range of
advanced packaging and temperature options.
H8S
higher performance or
less power consumption
H8/300H
16Bit, 16 MB address
faster
more memory
more integration
H8/300
low power
single chip
H8/300L
90
91
92
93
94
95
96
97
H8/300H has the performance (up to 10 native MIPS), the peripherals (very powerful timers, 10Bit ADC, serial communications, etc.) and the memory options (including H8/3048F with
128KB flash) to make it an industry standard in telecommunications and very successful in
industrial (e.g. motor control) and emerging consumer applications like new electronic video
cameras, set top boxes and advanced car radios. Since its introduction H8/300H has been
selected for hundreds of designs in Europe alone.
2
H8/3003
H8/3042
H8/3048
ROM-less
512 Byte RAM
112 pin QFP
rich peripherals
32K..64K ROM
2K RAM
100 pin QFP
rich peripherals
32K..128K ROM
2K..4K RAM
100 pin QFP
enhanced peripherals
Future
256K ROM
faster clock
further enhanced
peripherals
ROM-less
reduced peripherals
H8/3032 pin compatible
H8/3001
H8/3004+ 3005
ROM-less
512 Byte RAM
80 pin QFP
reduced peripherals
ROM-less
2K..4K RAM
80 pin QFP
reduced peripherals
30 NO
35 W
w A
an ith VA
d 25 IL
4K 6 A
RA K R BLE
M OM !
/O
TP
reduced pin count
reduced peripherals
H8/3035
16K..256K ROM
512Byte..4K RAM
80 pin QFP
reduced peripherals
8/
H8/3002
ROM-less
512 Byte RAM
100 pin QFP
rich peripherals
reduced pin count
slightly reduced peripherals
H
reduced pin count
3
4
CPU
The H8/300H CPU core has been designed as a 16/32 Bit general purpose register machine.
This architecture makes execution of software written in C very efficient and results in dense
code in order to reduce the amount of memory needed. Hence, H8/300H lowers total system
cost.
The H8/300H CPU is a general purpose register machine as shown below. The CPU comprises
eight 32-bit registers, each being further dividable into 16 and 8-bit registers. Being general
purpose there is no restriction placed on how each register is used, thus they can be used for
pointer or data operations. The architecture also allows any of the data addressing modes to be
used in conjunction with any register.
General Registers (ERn)
15
0
7
0
7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
CCR
7
6
5
4
3
2
1
0
I
UI
H
U
N
Z
V
C
This rich set of general purpose registers provides the compiler writer with ample opportunities
to optimise the code generated by the compiler. Local variables can be optimised into registers
wherever possible, thus reducing the number of bytes of code needed to manipulate them. Also,
because each register can be used as an accumulator, index register or address pointer, the
address arithmetic which must be performed by the compiler can be done very effectively.
Register ER7 is used as a stack pointer, so all accesses to stack based data can be performed
very fast.
5
These features significantly reduce the amount of code and time that is required to execute lines
of C source code when compared to traditional architectures, which have limited numbers of
fixed function accumulators and index registers.
The 32-bit register set also proves to be very useful in addressing large areas of memory, as a
24-bit pointer (this size pointer allows access to anywhere in the 16MBytes address space) can
be stored and manipulated in one register.
In addition to the general purpose registers there are two control registers, a Condition Code
Register (CCR) and a Program Counter (PC). The CCR is an 8-bit wide register which contains
all the CPU flags such as overflow, zero and carry as well as the interrupt flags. The carry flag
also doubles as a bit accumulator when the bit manipulation operations are used.
The H8/300H CPU offers a H8/300 compatible mode which allows straightforward reuse of
existing H8/300 software. This mode is available in H8/3032, H8/3042 and µCBIC products.
6
Addressing
To support large memory systems the linear address space of the H8/300H CPU core allows
direct access to every address in the whole 16MByte address space via 24-bit address pointers.
The linear address space means there is no need to set up page registers and there are also no
limitations on the size of code modules or data arrays and structures.
Addressing Modes
Another way a CPU architecture can support the efficiency of the compiler is by providing a full
set of powerful and flexible addressing modes. A CPU which only provides rudimentary
addressing modes makes a compiler inefficient in the access of variables, thereby increasing
both code size and execution time. To ensure that the compiler is as efficient as possible the
H8/300H CPU provides eight addressing modes as shown in the figure below.
Register direct
Rn
Register indirect
@ E Rn
Register indirect with displacement
@ (d: 16, E Rn)
@ (d: 24, E Rn)
Register indirect with post-increment/
@ E Rn +
Register indirect with pre-decrement
@ - E Rn
Absolute address
@ aa : 8
@ aa : 16
@ aa : 24
Immediate
# xx : 8
# xx : 16
# xx : 32
PC-relative
@ (d: 8, PC)
@ (d: 16, PC)
Memory indirect
@@ a a : 8
Each instruction can use a subset of the available addressing modes. The data transfer
instructions can make use of all addressing modes except PC relative and memory indirect. All
arithmetic and logical operations can use the register direct and immediate modes and the bit
manipulation instructions use the register direct, register indirect and absolute addressing modes.
Supporting both array and stack data types, the H8/300H has indirect addressing with either
postincrement or predecrement. These modes support byte, word and long word data (+1,2 and
4) as shown.
7
Register indirect with post-increment or pre-decrement
• Register indirect with post-increment
31
@ ERn +
op
0
23
0
23
0
Register contents
reg
+
1 , 2 or 4
• Register indirect with pre-decrement
@ ERn +
31
0
Register contents
op
reg
+
1 , 2 or 4
Operand Size
Added Value
Byte
1
Word
2
Longword
4
Three absolute addressing modes are provided using 8, 16 or 24-bit absolute addresses. Using
the 24-bit address the entire 16MBytes address space is accessible. The 8 and 16-bit absolute
address modes assume that the upper byte or word of the address is H'FFFF or H'FF respectively.
This allows for the efficient address specification for the on-chip I/O area and RAM areas which
are both placed at the top of the address map. These shortened addresses save significant
amounts of code when these areas are accessed.
8
Instruction Set
The H8/300H has an instruction set which suits the combined needs of HLL programming and
embedded applications. It comprises of 62 instructions, with an emphasis on arithmetic
instructions, address manipulation and bit processing. More than half of all instructions have an
instruction length of only 2Bytes making very compact code.
Function
Instruction
Data transfer
MOV, PUSH, POP, MOVTPE, MOVFPE
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU,
DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU
Loqic operations
AND,OR,XOR,NOT
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
Branch
Bcc, JMP, BSR, JSR, RTS
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
Block data transfer
EEPMOV
In comparison with the H8/300 CPU most of the data transfer, logical, shift and arithmetic
instructions are improved to handle 16 and 32-bit data. New instructions added to the H8/300H
include signed multiplication, sign extension, 16-bit branch instructions and a software trap
instruction. The following table illustrates the new and improved instructions provided by the
H8/300H.
9
DataSize
Byte
Word
Instruction
Long
Word
Data Transfer
MOV
EEPMOV (Block Transfer)
H8/300 & H8/300H
H8/300H
Arithmetic Operations
ADD, SUB, CMP,
MUL U/S
*
* improved
addressing
mode on H8/300H
DIV U/S
EXT. S/U
Logical Operations
AND, OR, XOR, etc.
Shift and Rotate
SHAL, SHAR, ROT, etc.
System Control
PUSH, POP
TRAPA
Branch
Bcc
d : 16
Arithmetic Instructions
In order to perform complex algorithms such as digital filtering the H8/300H is equipped with
powerful arithmetic instructions, including addition and subtraction on 32-bit data and
multiplication of 16 x 16-bit data and division of 32 / 16-bit data. Multiplication and division
are both available as signed and unsigned operations, which eliminate the need for time
consuming library calls. The table below gives a guide to the execution speed of various
arithmetic instructions with a clock of 16MHz.
Add 32bit operands
125ns
AND 32 bit operands
125ns
multiply/divide 16bit operands (32bit result, signed)
1.5 µs
multiply/divide 16bit operands (32bit result, unsigned)
1.375 µs
10
Bit Processing
In microcontroller applications it is often necessary to manipulate data on a bit by bit basis. A
good example would be where an I/O pin needs to be set to switch on a lamp or a solenoid. To
meet this demand the H8/300H has 14 separate bit processing instructions which allow the
programmer to manipulate bit data very easily.
Instruction: BRST RIL, RIH
RIL points to a bit position within RIH
RIL
7
0
0
0
0
0
1
0
1
0
= 5
7
0
0
1
0
0
0
0
0
0
bit # 5
Z
in CCR
It is also possible to perform boolean algebra on bit data using the carry flag of the CCR register
as a bit accumulator. In a microcontroller application it is often necessary to perform a branch
depending on the values of two bit flags located in RAM or I/O ports. Using the boolean
operations provided by the H8/300H the first bit can be loaded into the carry flag. Then a
bitwise logical operation can be executed using the second bit. This sequence would then be
followed by a branch depending on the value of the carry flag.
Another feature of the H8/300H bit processing capability is its ability to access bits indirectly,
using the value from a general purpose register as a bit pointer. This mechanism is shown below
and is useful for scanning a byte for set or cleared bits.
11
Block Move Instruction
Another efficient instruction provided by the H8/300H CPU is the EEPMOV or block data
transfer. This is useful when a table stored in ROM has to be transferred to RAM for
manipulation. Block sizes up to 64KBytes can be transferred with a single instruction.
Software Interrupt
The TRAPA instruction has been added to the H8/300H CPU. This instructions implements a
software interrupt, jumping to a service routine via one of four exception vectors (TRAPA 0 - 3).
This operation can be used to implement fast, space efficient calls to often used sub-routines
such as schedulers and other O/S routines. The TRAPA instruction can also be used as a call to
an error handling routine.
12
CPU States / Low power modes
The H8/300H CPU has four different processing states: program execution, exception handling,
bus-released and power-down.
In the program execution state the CPU executes normal program instructions in sequence, while
the exception handling state is a transient state in which the CPU executes an exception handling
sequence in response to a reset, interrupt or other exception. In the bus-released state the
external bus has been released to an external bus-master other than the CPU. In the power down
mode the CPU is halted to conserve power. The power down modes include three modes: sleep,
software standby and hardware standby. These modes are enhanced in the H8/3048 series by
adding module standby and clock gearing.
Low Power Modes
The H8/300H Series has been designed to be a microcontroller with high performance and low
power dissipation. It therefore can be used in 3V or 5V systems and only consumes 20mA
(max.) when operating at 3V and 8MHz.
To widen its use in battery operated equipment such as cellular telephones, an impressive set of
low power modes are also provided on all devices.
Sleep Mode
In this mode the device switches off the clock to the CPU, but all of the on-board peripherals
remain active, and register and memory contents are retained. Sleep mode is entered via the
“SLEEP” instruction; the CPU exits this mode whenever an enabled interrupt occurs.
A useful application for this mode is to reduce the average power consumed by a system, using a
timer to “wake” the CPU after a period of sleep.
Once woken, the CPU can process for a period of time and then after loading the timer again the
SLEEP instruction can be executed, again lowering the power consumption.
When sleep mode is entered the device's current consumption is reduced by approximately one
third over its operating value.
Software Standby Mode
Again, this mode can be entered using the SLEEP instruction, but in this case the on-chip
oscillator is stopped completely, putting the device into software standby. Standby current is
very low with a maximum value of 5µA. This is coupled with a data retention voltage of 2V,
allowing the microcontrollers internal RAM contents to be maintained using just two 1.5V
13
battery cells or possibly a large “reservoir” capacitor. During software standby mode, the
microcontroller maintains the value of the I/O ports, so output ports can be set to the values the
system requires during power down, with the knowledge that they will remain stable during
software standby mode.
To exit from this mode, an external interrupt can be used, and a specialised timer circuit is
provided to ensure that the on-chip oscillator has started and is stable before execution of the
interrupt service routine begins.
Hardware Standby Mode
This mode allows the device to be put into the low power mode via an external pin. While in
this mode the maximum current consumption is 5µA and to exit hardware standby the chip must
be reset.
Extra Power Down Support - H8 / 3048
The H8/3048 range incorporates some extra power down options making it an ideal device in
many high performance battery driven systems. The first feature is the ability to put individual
peripherals into standby mode via software. The control register used for this operation is shown
below.
-
PSTOP
Initial Value:
R/W
0
R/W
1
-
MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0
0
R/W
0
0
R/W
R/W
0
0
0
R/W
R/W
R/W
A/D
Standby
Refresh
Controller
DMAC Standby
Standby
SCIO
Standby
SCI1
Standby
ITU
Standby
Enable / Disable
φ Clock Output
This feature makes the H8/3048 an ideal fit into cellular handsets as it mirrors the hardware
designer’s efforts to enable parts of the circuit to be powered down when they are not required.
14
Clock Gearing
Another power down feature provided by the H8/3048 is its ability to change the on-chip
operating frequency via a software command. This is achieved using a programmable clock
divider which allows the clock to be divided by 1, 2, 4 or 8.
Divide Ratio
φ = 16 MHz
0
1/1
φ = 16MHz
0
1
1/2
φ = 8 MHz
1
0
1/4
φ = 4 MHz
1
1
1/8
φ = 1 MHz
Bit 1
Bit 0
DIV 1
DIV 0
0
Clock gearing allows the performance and power dissipation to be changed to suit the system's
current mode. For example, when scanning a keyboard or other input device the divide by 8
option could be selected, but once a pressed key is detected the divide by 1 option can be
selected to instantly give the device full speed operation.
15
16
Exceptions and Interrupts
Exceptions on the H8/300H CPU fall into four categories, reset (highest priority), external
interrupts, internal interrupts and trap exceptions. The following table shows the exception
vector table for the H8/300H CPU core.
Exception Source
Vector
Vector Address
Reset
0
H'0000 to H’0003
Reserved for system use
1
H'0000 to H'0007
2
H'0008 to H'000B
3
H'000C to H'000F
4
H'0010 to H'0013
5
H'0014 to H'0017
6
H'0018 to H'001B
External interrupt (NMI)
7
H'001C to H'001F
Trap instruction (4 sources)
8
H'0020 to H'0023
9
H'0024 to H'0027
10
H'0028 to H'002B
11
H'002C to H'002F
External interrupt IRQO
12
H'0030 toH'0033
External interrupt IRQ1
13
H'0034 to H'0037
External intemipt IRQ2
14
H'0038 to H'003B
External interrupt IRQ3
15
H'003C to H'003F
External interrupt IRQ4
16
H'0040 to H'0043
External interrupt IRQ5
17
H'0044 to H'0047
External interrupt IRQ6
18
H'0048 to H'004B
External interrupt IRQ7
19
H'004C to H'004F
lnternal interrupts
20
to
60
H'0050 to H'0053
to
H'00F0 to H'00F3
17
Trap Exceptions
When the TRAP instruction is executed, the program will start executing from the location
specified in the relevant vector. The TRAP instruction has four vectors as specified by its
argument. This exception can be used as an efficient mechanism for calling operating system
functions, as it takes only 2 Bytes to execute a TRAP operation, compared to 4 Bytes for a BSR
and 8 Bytes for a JSR.
Interrupt Controller
The H8/300H interrupt controller (INTC) can be operated in two modes, either maintaining
compatibility with the standard H8/300 INTC, or in a more advanced mode.
H8 / 300 Compatible Mode
In this mode, the acceptance of maskable interrupts is controlled by the I bit in the CCR. If I is
set then all interrupts are disabled and if I is cleared then all interrupts are enabled. When an
interrupt is accepted the INTC automatically sets the I bit, thus disabling any other maskable
interrupt for the duration of the interrupt service routine (ISR), unless it is cleared by the user's
code.
H8 / 300H Advanced Mode
To increase the power of the interrupt controller, an extra interrupt status bit is included in the
condition code register, known as the Ul or User Interrupt bit. This extended operation allows
the user to specify raised priority interrupt sources, which are capable of interrupting a low
priority ISR which is already running. The priority of individual interrupt sources is programmed
in a number of interrupt priority registers (IPR).
External Interrupts
All the H8/300H devices include several external interrupts, including one non maskable
interrupt (NMI). NMI can be programmed to be activated on either the rising or falling edge and
the standard external interrupts can be programmed to recognise either a low level or a low
going edge.
Interrupt Vectors
To speed up the processing of interrupts, every interrupt source has its own vector. For example,
for each serial port there are separate vectors for transmit, receive and error interrupts.
Therefore, the ISR does not need to poll a peripheral block to find the source of any interrupt.
18
Interrupt Response Time
Interrupts are responded to rapidly on the H8/300H. When code and data are both located in the
on-chip memory, then the ISR will be reached within 2.6 microseconds (worst case) at 16MHz.
If this is coupled with the individual vector structure provided by the H8/300H, the ISR can be
performing useful work very quickly indeed. The table below shows how fast H8/300H
responds to interrupts in several configurations.
External Memory
8-Bit Bus
16-Bit Bus
No
Item
On-Chip Memory
2States
3 States
2 States
3 States
1
Interrupt priority decision
2
2 *1
2 *1
2 *1
2 *1
2
Maximum number of
1 to 23
states until end of current
instruction
1 to 27
1 to 31 *4 1 to 23
1 to 25*4
3
Saving PC and CCR to
stack
4
4
12 *4
4
6 *4
4
Vector fetch
4
8
12 *4
4
6 *4
5
Instruction prefetch *2
4
8
12 *4
4
6 *4
6
lnternal processing *3
4
4
4
4
4
19 to 41
27 to 53
43 to 73
19 to 41
25 to 49
Total (Clocks)
Notes:
1.
2.
3.
4.
One state for internal interrupts
Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine
lnternal processing after the interrupt is accepted and internal processing after
prefetch
The number of states increases if wait states are inserted in external memory
access
19
20
On-chip Memory
Often, due to its power and ability, a H8/300H device will be used in applications where the
program size is very large. At first glance, these large programs appear to preclude using any
microcontroller in single chip mode.
But large programs place no restriction on the H8 / 300H family, as unparalleled sizes of on-chip
program and data memory are available, even in its’ smallest package.
For example the H8 / 3048 with 128K of PROM / ROM / Flash and 4K of RAM in a single chip,
100-pin device measuring just 17.2 mm across its pins. New variants of the H8 / 300H family
are also under development.
ROM RAM
0
16k
512 Byte
3001
3002
3003
3030
32k
48k
64k
3040
3044
3041
3032
3042
3045
96k
128K
192K
256k
3047
3033
3048
3048
Flash
3034
3035
3031
1k
2k
3004
4k
3005
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BOLD products are also available as ZTAT (OTP).
21
22
Flash Memory (F-ZTAT)
Ev
al NO
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30
48
F
Together with the Flash-derivatives in other microcontroller families, Hitachi offers the worlds
best line up of microcontrollers with on-chip flash currently in full production. Hundreds of
customers world wide have taken advantage of our flash based microcontrollers in their designs,
about one third in industrial and automotive applications, approximately one fourth each in
consumer and office automation and the remainder in telecommunications.
The Advantages of flash based microcontrollers include:
•
•
•
•
•
•
end of line programming allows flexibility in the software until shipment
software flexibility during production ramp up and development
allows easy and fast update in the field without the need to open the equipment
allows software updates even remotely, e.g. via modem/phone line
fast response to changing customer requirements
non volatile storage of data and parameters
23
Technology
Flash memory is programmed by applying a high gate-drain voltage that draws hot electrons
generated in the vicinity of the drain into a floating gate. The threshold voltage of a programmed
cell is therefore higher than that of an erased cell. Cells are erased by grounding the gate and
applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel
out. A flash memory cell is read like an EPROM cell, by driving the gate to the high level and
detecting the drain current, which depends on the threshold voltage. Programming takes
50µs/Byte and erasing 1s per block or for the full flash memory.
Hitachi's H8/3048F offers full speed operation (16MHz/5V and 8MHz/3V), block division into
8 small (512Byte) and 8 large blocks (12K and 16K) and various ways to program the
H8/3048F's flash memory. These modes are selected by pins on reset and allow on-board
programming:
• User program mode: In user program mode the flash memory can be erased and programmed
under control of an user program. In this mode all the resources of the H8/3048F can be used
except the flash memory, as reading from the flash memory is not possible during erasing or
programming.
• Boot mode: Boot mode allows the user to erase and program the flash memory via the serial
interface SCI1. This is possible even if the microcontroller contains no user software, i.e. it
allows in-circuit-programming of new (empty) devices.
• PROM mode: The H8/3048F can also be programmed using general purpose PROM
programming equipment. The H8/3048F is inserted in the programmer using a socket
adapter available from Hitachi.
Other technical characteristics of Hitachi's on-chip Flash memory include:
• Security mechanism against malicious access makes theft of code virtually impossible.
• Accidental erase or write impossible without Vpp being present.
• 100 erase/write cycles guaranteed with higher specification under preparation.
24
Bus State Controller (BSC)
As one of the key reasons for using the H8/300H is the 16MBytes linear address space, it is
likely that it will be used in a system with a large quantity of memory. Consequently, the
H8/300H CPU core is supported by a powerful bus state controller (BSC) that allows the
memory to be configured in the system in the most appropriate way.
The H8/300H BSC is able to configure eight memory areas with their own independent
attributes. In the advanced modes, these areas are either 256KBytes (1 MBytes mode) or
2MBytes (16MBytes mode) in size. The attributes which can be set for each area are the bus
width, the number of cycles for each external access and the wait state mode used.
Bus width (bits)
access cycles
Size (max.)
SRAM
8/16
2..6
16MB
EPROM
8/16
2..6
16MB
PSRAM
8/16
2..6
16MB
DRAM
16
3..6
2MB
When a memory area is initialised into the 3-state access cycle mode, the wait state controller
can be activated for this area to allow slow devices to be connected to the bus of the H8/300H.
There are four wait modes available: the programmable wait mode, pin auto wait mode and the
pin wait modes 0 and 1.
Wait state controller mode
Operation
Pin wait mode 0
Two wait states are inserted whenever the wait pin is
sampled low. The wait state controller is otherwise
disabled for memory areas so specified.
Pin wait mode 1
The number of wait states programmed in the WSC
are inserted and then the wait pin is sampled. If it is
low further wait states are inserted.
Pin auto-wait mode
If the wait pin is low when sampled the number of wait
states programmed in the WSC are inserted and then
the bus cycle is terminated.
Programmable wait mode
For every access to the specified 3-state access area,
the number of wait states programmed in the WSC are
inserted automatically.
Combining the BSC with the on-chip refresh controller, allows the H8 / 300H to be interfaced to
a wide range of memory types, including DRAM, SRAM, PSRAM and EPROM with the
minimum of external logic. This function extends to the generation of chip selects
corresponding to the memory area being accessed.
25
DRAM and PSRAM Interface
To provide a large area of RAM, the most cost effective memory type to use is DRAM.
However, normally in an embedded system the external devices required to interface with
DRAM often causes designers to use SRAM as the lowest cost system option.
To allow designers to utilise the full benefit of using DRAM in their system, the H8/300H has
been equipped with a bus interface which can couple directly to DRAM with the minimum of
external components.
This has been achieved by incorporating the logic required to produce the DRAM interface
signals and a refresh controller into the BSC. For example, the figure below shows the
connection of a H8/3003 to a 4-Mbit DRAM.
2 WE 4-Mbit DRAM with 10-bit
row address, 8-bit column address,
and x 16-bit organization
H8/3003
A18
A17
A9
A8
A8
A7
A6
A5
A4
A3
A2
A1
A7
A6
A5
A4
A3
A2
A1
A0
CS3
RD
HWR
LWR
D15 to D0
RAS
CAS
UW
LW
OE
I/O15 to I/O0
The H8/300H supports 1Mbit and 4Mbit DRAM (2WE or 2CAS) in 16-bit wide configurations.
The refresh controller can be programmed to produce a wide variety of refresh intervals, and the
DRAM controller can put the DRAM into self refresh mode whenever the software standby
mode is selected.
26
Chip Select Generation
The BSC on the H8/3003, H8/3002 and H8/304X devices can be used to generate chip select
signals for different memory areas. These chip selects have the added benefit of becoming
active at the same time as the address becomes valid, thus removing any decode delay.
27
28
Direct Memory Access Controller (DMAC)
To complement a CPU which provides high performance operation for complex algorithms and
an address space which can handle large data structures and program modules, the addition of a
direct memory access controller (DMAC) on-chip will significantly increase the performance of
the system. The DMAC will allow the utilisation of the whole CPU performance for the system's
algorithms, while repetitive but important data transfer can be done via DMA.
Any external or internal interrupt that initiates a data transfer can be completely serviced by the
DMA without any interrupts being handled by the CPU. This drastically reduces the CPU
overhead needed for interrupt handling. When used with other on-chip peripherals such as the
ITU, the DMAC allows the control of real time inputs and outputs, or it can be used to service
the serial interfaces.
The basic H8/300H DMAC module incorporates four channels. However, the H8/3003 actually
provides eight channels. Each channel in the DMAC module can be utilised to perform transfers
between memory and I/O, while 2 channels need to be combined for memory to memory
transfers. Byte and word transfer are possible in all available operating modes.
Internal address bus
Internal
interrupts
IMIA0
IMIA1
IMIA2
IMIA3
Address buffer
TXI0
RXI0
Arithmetic-logic unit
DREQ1
IOAR0A
ETCR0A
Channel
0
TEND0
TEND1
MAR0B
Channel
0B
DTCR0A
IOAR0B
ETCR0B
Interrupt
signals
Module data bus
MAR0A
Channel
0A
Control logic
DREQ0
DTCR0B
DEND0A
DEND0B
DEND1A
DEND1B
MAR1A
Channel
1A
DTCR1A
DTCR1B
Data buffer
IOAR1A
ETCR1A
Channel
1
MAR1B
Channel
1B
IOAR1B
ETCR1B
Legend
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Internal data bus
29
Short Address Mode
In this mode an 8-bit source address and 24-bit destination address (or vice versa) are used.
During the transfer the 8-bit address (which points to an I/O register) is fixed while the 24-bit
address may change according to the way the channel has been initialised. In this mode DMA
transfers are initiated by interrupts from the timer block, the serial port or via an external signal.
One byte or word of data is transferred per request and the 24-bit address incremented by one or
two after each transfer. If a fixed memory address is required, then the channel can be put into
an idle mode, where the 24-bit address will not increment. Up to 64K transfers can be
performed before an interrupt is signaled to the CPU.
The DMA channel can also be set to automatically repeat up to 256 transfers continuously, with
the DMA channel being reinitialised and restarted after the specified number of transfers has
been performed. This is useful when cyclic data such as a control pattern for a stepper motor
has to be transferred.
Full Address Mode
To perform memory to memory transfers the full address mode can be used. Here, the source
and destination addresses are 24-bits wide each, and therefore memory to memory transfer can
be performed between any areas of the full 16MBytes address space.
DMA transfers can be initiated by software command, external signals or interrupts from the
timer block. This mode allows either a single transfer to occur per request, or for a block of data
to be moved. In the block mode, the DMAC can be set up in a burst mode, taking over the bus
from the processor until all the transfers are complete, or in a cycle steal mode where the
processor and the DMAC share the bus.
DMAC Interrupts
The DMAC can be set up to provide an interrupt per request, or to only interrupt the processor
when it has performed a programmed number of transfers.
DMAC Modes
The DMAC provides a choice of short and full addressing modes, which allow the DMA to be
adapted according to system requirements.
30
Address Register Length
Short
address
mode
Transfer mode
Activation
IO mode
• transfers 1 byte or 1 word per
request
• increments or decrements the
memory address by 1 or 2
• executes 1..65536 transfers
•
Idle mode
• transfers 1 byte or 1 word per
request
• holds the memory address
fixed
• executes 1..65536 transfers
•
•
•
Compare match/input capture A 24
interrupts from ITU channels
0..3
transmit data empty interrupt
from SCI
Receive data full interrupt from
SCI
External request
Repeat mode
• transfers 1 byte or 1 word per
request
• increments or decrements the
memory address by 1 or 2
• executes a specified number
(1..256) of transfers then
returns to the initial state and
continues
Full
address
Source
Destination
8
8
24
24
8
•
Normal mode
•
• auto request
retains the transfer request
externally
executes a specified
number (1..65536)
of transfers continuously
selection of burst mode or
cycle steal mode
• external request
transfers 1 byte or 1 word
per request
executes 1..65536
transfers
auto request
external request
24
24
•
Block transfer
• transfers 1 block of a specified
•
size per request
•
• executes 1..65536 transfers
• allows either the source or the
destination to be a fixed block
area
• block size can be 1..256 byte
or word
compare match/input capture A 24
interrupt from
ITU channels 0..3
external request
24
31
32
Integrated Timer Unit (ITU)
In many microcontroller based systems, very specialised timer functions are required. Often
these timer functions are produced in a user developed ASIC device, because the timers
provided by the microcontroller do not meet the performance required by the designer. The
timer unit on the H8 / 300H has been designed to allow maximum flexibility in its use, therefore
allowing the designer to get the timer configuration required without resorting to an external
timer device.
TCLKA to TCLKD
Clock selector
Ø, Ø/2, Ø/4, Ø/8
TOCXA 4 , TOCXB4
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
Control logic
Counter control and
pulse I/O control unit
TIOCA 0 to TIOCA4
TIOCB 0 to TIOCB4
TODR
TSNC
TMDR
On-chip data bus
TSTR
Bus interface
16-bit timer channel 0
16-bit timer channel 1
16-bit timer channel 2
Timer output master enable register (8 bits)
Timer output control register (8 bits)
Timer start register (8 bits)
Timer synchro register (8bits)
Timer mode register (8 bits)
Timer function control register (8 bits)
16-bit timer channel 3
Legend
TOER:
TOCR:
TSTR:
TSNC:
TMDR:
TFCR:
16-bit timer channel 4
TOCR
TFCR
Module data bus
The ITU consists of five separate 16-bit timer channels, each of which can be clocked from an
internal derivative of the system clock (φ, φ/2, φ/4 and φ/8) or from an external pin. If the φ clock
option is selected, then the minimum resolution of the timer is 62.5ns (φ = 16MHz). The
standard timer functions provided by the ITU include ten general registers (GR), which can be
used as output compares or input captures. Thus the complete timer block provides up to ten
pulse inputs or outputs. A further four 16-bit buffer registers (BR) reduce the overhead placed
on the CPU when servicing the timer block.
33
Item
Channel 0
Clock Sources
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable
independently
General registers
(output compare/
input capture registers)
GRA0,
GRB0
GRA1,
GRB1
GRA2,
GRB2
GRA3,
GRB3
Buffer registers
-
-
-
BRA3, BRB3 BRA4, BRB4
Input/output pins
TIOCA0
TIOCB0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCA4,
TIOCB4
Output pins
-
-
-
-
TOCXA4,
TOCXB4
GRA1/GRB1
compare
match or
input capture
GRA2/GRB2
compare
match or
input capture
GRA3/GRB3
compare
match or
input capture
GRA4/GRB4
compare
match or
input capture
Counter clearing function GRA0/GRB0
compare
match or
input capture
Channel 1
Channel 2
Channel 3
Channel 4
GRA4,
GRB4
Compare 0
match
output
√
√
√
√
√
1
√
√
√
√
√
Toggle
√
√
-
√
√
Input capture
√
√
√
√
√
Synchronization
√
√
√
√
√
PWM mode
√
√
√
√
√
Reset-synchronized PWM mode
-
-
-
-
Complementary PWM
mode
-
-
-
√
√
Phase counting
-
-
√
-
-
Buffering
-
-
-
√
√
Legend
√:Available
-: Not available
34
Output Compare Functions
To create output waveforms or timed interrupts, the ITU provides up to 10 output compare
registers. The output compares work by producing an output of a pre-programmed level and/or
an interrupt when the value in the counter matches the value stored in one of the output compare
registers. The events that can be initiated by these compare matches are transitions on an output
pin (to high, to low or toggle), a CPU interrupt (used for software timing functions), clearing the
counter and the triggering of a DMA channel.
Channels 3 and 4 allow to produce a pulse with duration down to one clock cycle (62.5ns at
16MHz).
A combination of the output compare function with the DMAC and the TPC (a peripheral
explained later) can be used to control stepper motors very easily.
Input Capture Functions
The ITU provides up to 10 channels of input capture. In this mode the timer can be set up so
that a transition on an input pin causes the value currently in the count register to be transferred
into a capture register, thus time stamping that particular event. The ITU can be set to capture
rising edges, falling edges and either of these. If required the timer unit can also clear the timer
when the programmed external event occurs.
The two buffer registers (BRA and BRB) provided in timer channels 3 and 4 can be used to
buffer input time stamps. This allows events which occur very close together to be time stamped
using one capture pin. This feature can also be used to measure the width of an incoming pulse,
by programming the capture input to be triggered on both the rising and falling edges.
By using input captures to measure the timing of external signals, very accurate measurements
of variables such as frequency can be taken. The user can be sure that the accuracy of the
measurement is not compromised by interrupt response time, as it is entirely a hardware driven
facility.
It is also possible to initiate DMA transfers when an input capture event occurs. This allows
time stamps to be automatically placed in memory via the DMA controller, without needing to
interrupt the CPU.
Timer Synchronisation
To allow timer channels in the ITU to be used in synchronisation, it is possible to set up two or
more timers so that they are simultaneously written to via software and cleared by compare
matches or input captures. When timer channels are put into this mode then their input and
output events are also synchronised.
35
PWM Operating Modes
The PWM (Pulse Width Modulation) modes of the ITU are described in the following diagrams.
Counter cleared by compare match
TCNT Value
GRB
GRA
Time
H'00
TIOCA
Write to GRA
Write to GRA
Standard PWM Mode
Each timer channel can be programmed to produce a single phase PWM output.Thus the ITU
can output up to five separate channels of PWM. In this mode GRA controls the time when the
pin goes high, and GRB when the pin goes low. Either GRA or GRB can be set to clear the
counter, thus setting the frequency of the PWM output. The table below shows the PWM
frequencies which can be obtained against device clock speed and output resolution.
PWM Resolution
16 MHz
12 MHz
10 MHz
8 MHz
6 MHz
14-bit
976.5 Hz
732.7 Hz
610 Hz
488 Hz
365 Hz
12-bit
3.9 KHz
2.9 KHz
2.4 KHz
2 KHz
1.5 KHz
10-bit
15.6 KHz
11.7 KHz
9.7 KHz
7.8 KHz
5.8KHz
9-bit
31.2 KHz
23.4 KHz
19.5 KHz
15.6 KHz
11.7 KHz
8-bit
62.4 KHz
46.9 Khz
39 KHz
31.3 KHz
23.4 KHz
7-bit
124.8 KHz
93.8 KHz
78 Khz
62.5 KHz
46.8 KHz
36
AC Motor Control Outputs
To provide the PWM signals required to drive AC machines, the ITU provides two further PWM
modes: Complementary 6-phase PWM and Reset Synchronised 6-phase PWM. The main
differences between these two modes are the transition points for the outputs and the provision
of dead time between the phase outputs.
Complementary 6-Phase PWM
In this mode channels 3 and 4 are combined to produce three pairs of non-overlapping PWM
waveforms, as described in the figure “H8/300H PWM modes”. As can be seen from this figure,
in this mode TCNT3 and TCNT4 act as up/down counters, counting down from the point set by
the compare match TCNT3 and GR3 and counting up from the point at which TCNT4
underflows.
TCNT3 and
TCNT4 values
Downcounting starts at
TCNT3
GRB3
GRA4
GRB4
TCNT4
Time
H'0000
Up counting starts when
TCNT4 underflows
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TIOCXB4
The PWM waveforms are produced from compare matches with the general registers GRB3,
GRA4 and GRB4. Using this mechanism, only three registers need to be reloaded to change the
modulation ratio, keeping the CPU overhead to a minimum.
In an AC motor control system, it is necessary to insert some deadtime between the switching of
the complementary phases to ensure that no short circuit condition occurs through the two
drivers. The ITU supports this function using the difference in value between the two timer
channels used. Thus a totally programmable deadtime is supported in this mode.
37
TCNT3 values
Counter cleared by compare
match with GRA3
GRA3
GRB3
GRA4
GRB4
H'0000
Time
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Reset Synchronised PWM
This output mode is shown in the figure “H8/300H PWM modes” and it provides three pairs of
complementary PWM waveforms, all having one common waveform transition point. In this
mode TCNT3 counts up until it is cleared by a match with GRA3. The output pins toggle at
compare matches between GRB3, GRA4, GRB4 and TCNT3 and they all toggle when TCNT3 is
cleared.
Phase Counting Mode
This mode finds use in servo control systems, where the position and speed feedback comes
from a 2- phase quadrature encoder. In this type of encoder the waveforms output change their
phase relationship depending on the direction of motion.
38
Counter value
Count up
Count down
Timer counter 2
time
TCLK1
TCLK0
TCLK1 and TCLK0 are signals provided by a 2-phase quadrature encoder. The value of timer
counter 2 reflects the position. Note: This mode is available only for timer counter 2
Countdown
High
TCLK0
TCLK1
Low
Countup
Low
High
High
Low
High
Low
Count condition: Count all edges
By utilising the phase counting mode on the ITU, TCNT2 will count up or down depending on
the phase of the incoming signals. Therefore, the value of TCNT2 will reflect the positional
changes experienced by the encoder.
This facility removes the requirement for extra hardware or interrupt handlers for position
monitoring. In this mode the comparators of channel 2 can also be used to generate interrupts,
for example when a certain position is reached.
ITU Interrupts
The ITU can produce a total of 15 interrupts. This comprises 3 per channel, one for each general
register and an overflow. Each interrupt has its own vector, making it unnecessary to poll flags,
thus enabling fast reaction by the CPU.
39
40
Timing Pattern Controller (TPC)
This peripheral can simultaneously output up to 16 waveforms, using a strobe signal produced
by the ITU. It is useful for generating the necessary waveforms for driving stepper motors.
ITU compare match signals
Legend
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Control logic
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
Internal
data bus
Pulse output
pins, group 3
PBDR
NDRB
PADR
NDRA
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
The main registers of the TPC are the next data registers (NDRA~D). These registers are each 4bits wide and contain the next data which will be transferred into the port data registers PADR
and PBDR. This data is transferred using a strobe signal generated by the selected timer channel
output compare. A separate timer channel can be specified to synchronise each group of 4-bits.
One of the main applications for this peripheral is the control of multiple stepper motors; if used
in conjunction with the on-chip DMA controllers then this control can be performed with very
little CPU supervision.
Stepper Motor Control with the TPC
A diagram showing how stepper motor control can be performed using the ITU, TPC and
DMAC is shown below. In this example a two phase stepper motor is being driven, using
complementary transistors. It is therefore necessary to provide a dead time between the
switching of the phases to eliminate any short circuit conditions between the high side and low
side drivers.
41
memory
DMA
channel 0
output pattern
data table
ITU
clock
OCRA
OCRB
NDRA
step pulse
period data
table
TPC
pins
DMA
channel 1
data flow
trigger
PBDR
motor
control
pulses
OCRA holds Non-Overlap time
OCRB holds step pulse time
Using compare matches from the ITU to stimulate the DMAC, new pattern data is provided to
the TPC. This pattern data represents the next phase drive pattern required, and is stored in a
memory table. The DMAC uses its memory to I/O function to transfer this data on each compare
match. The TPC also uses the stimulus from the ITU to transfer the contents of the NDR to the
port. Using a TPC mode where transitions on the port from 0 to 1 (i.e. switching on a phase) are
only made on compare match A, a dead time, equal to the value in GRA, is inserted.
42
Ac
ce
ler
ati
on
on
ati
ler
ce
De
revolutions
Constant
= CPU intervention required
When controlling a stepper motor, providing the phase patterns onto the port pins is only part of
the story. It is also necessary to modify the time between new patterns being output to allow
acceleration and deceleration of the motor as shown by the velocity profile.
When the TPC, ITU and DMAC are working together, the acceleration and deceleration phases,
as well as the steady speed phase can be controlled with minimal CPU overhead. The CPU need
only get involved when a transition from one phase to another is made.
This is achieved by using a second memory to I/O DMA channel to reload the timer compare
register after each new pattern has been output. Again the DMAC can take the next step period
data from a table of values stored in the memory of the system. Therefore, by providing a table
of increasing or decreasing values the motor can be decelerated or accelerated with no CPU
intervention.
The flexibility of the H8/300H’s stepper motor control functions will even allow multiple motors
to be controlled simultaneously by one device. The figure shows examples of the stepper motors
which can be controlled, and contrasts the resources required with the amount of resource
available on the H8/3003.
43
2-Phase 1-Excitation
2-Phase 2-Excitation
2-Phase 1-2-Excitation
5-Phase 5-Excitation
2-Phase
1-Excitation
2-Phase
2-Excitation
2-Phase
1-2-Excitation
5-Phase
H8 / 3003
Total
DMAC
2ch
2ch
2ch
2ch
8ch
TPC
4-bits
4-bits
4-bits
5-bits
16-bits
ITU
1ch
1ch
1ch
1ch
5ch
2 -Phase
I-Excitation
2-Phase
2-Excitation
2-Phase
1-2-Excitation
5-Phase
H8 / 3003
Total
DMAC
2 ch
2 ch
2 ch
2 ch
8 ch
TPC
4-bits
4-bits
4-bits
5-bits
16-bits
ITU
1 ch
1 ch
1 ch
1 ch
5 ch
44
Watchdog Timer (WDT)
Often, a watchdog timer is a very important feature in any embedded application. It is used to
ensure that any “mishap” in the system (such as a noise induced software crash) is rectified as
quickly as possible.
The principle behind a watchdog timer is very simple - a counter is constantly counting upwards,
and correctly operating software ensures that this counter never overflows by continuously
resetting the count. If the software crashes and the counter overflows, the watchdog “barks” and
sends some stimulus to the microcontroller (normally a reset) to restart system operations in a
controlled manner.
All H8/300H devices are equipped with a timer, which can be used either as a watchdog or as an
interval timer. Its “bark” is a reset if it is used as a watchdog.
Overflow
TCNT
Interrupt signal
(interval timer)
Interrupt
control
Read/
write
control
Internal
data bus
TCSR
Internal clock sources
Ø/2
RSTCSR
Ø/32
Ø/64
Reset
(internal, external)
Reset control
Clock
Clock
selector
Ø/128
Ø/256
Legend
TCNT:
Timer counter
TCSR:
Timer control/status register
RSTCSR: Reset control/status register
Ø/512
Ø/2048
Ø/4096
45
46
Serial Communications Interface (SCI)
This form of communication has many uses in microcontroller applications, such as interdevice
communications, diagnostics, host communication, and even as an interface to peripherals. All
H8/300H devices are equipped with at least one and very often two channels of serial
communication interface (SCI). These channels can be used for either synchronous or
asynchronous communications. This type of SCI is standard across the H8/300H range.
Bus interface
As shown in the block diagram each SCI channel has its own integral Baud rate generator, so
many Baud rates can be produced from the microcontroller's internal clock, without using any
other timers.
Module data bus
RDR
TDR
SSR
Internal
data bus
BRR
SCR
RxD
RSR
TSR
Baud rate
generator
SMR
Ø
Ø/4
Ø/16
Ø/64
Transmit/
receive control
TxD
Parity generate
Parity check
Clock
External clock
SCK
Legend
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
TEI
TXI
RXI
ERI
As well as using the integral Baud rate generator, each SCI can be configured to use an external
serial clock.
To allow “back to back” transmission or reception of serial data, the SCI has double buffered
transmit and receive shift registers.
The H8/300H serial ports also support multiprocessor communications using a master slave
configuration in addition to the standard modes.
In this mode, communication between devices is performed using an additional multiprocessor
bit (MPB) which is added to the data transmitted. This bit is used to differentiate between data
47
frames and address frames. Thus, any frame sent from the master with the MPB set to one can
be used to activate the required slave.
Legend
MPB: Multiprocessor bit
Transmitting
processor
Serial communication line
Serial data
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
(MPB = 1)
ID-sending cycle: receiving
processor address
H'AA
(MPB = 0)
Data -sending cycle:
data sent to receiving
processor specified by ID
Slave devices on this network will only produce a receive interrupt when a frame is received
with the MPB set, so the interrupt handler can check the address which has been transmitted.
Receive data errors are trapped using three error conditions -overflow,framing and parity. These
three errors are indicated via one interrupt vector and three status flags in the serial status
register.
48
Analogue to Digital Converter (ADC)
In many microcontroller based systems, some way of measuring analogue electrical values is
necessary.With this in mind, all members of the H8/300H family are equipped with a 10-bit A/D
converter.
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
On-chip
data bus
AVss
ADCR
ADCSR
ADDRD
ADDRC
10-bit D/A
ADDRB
VREF
ADDRA
AVcc
Bus interface
Module data bus
Successiveapproximations register
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
AN0
AN1
AN2
AN3
AN4
Ø/8
+
_
Analog
multiplexer
AN5
Ø/16
AN5
AN7
Control circuit
Comparator
Sample and
hold circuit
ADI
ADTRG
The converter works using a successive approximation algorithm and conversions take 138 states
(or 8.6µs if φ - 16MHz).
Up to 8 inputs can be converted; this is achieved using an 8 channel multiplexer between the
input port and the A/D. A sample and hold capacitor is used to ensure that once a conversion
begins, a change of the input value will not be reflected in a different conversion result.
As well as being able to perform single conversion (where only one channel is converted), the
H8/300H A/D converter can also be used to scan up to four channels. To support this mode of
operation, four A/D result registers are provided. Once the scan mode is selected, each channel
specified is converted sequentially with the conversion value being stored in the appropriate
result register. This mode of operation allows the user software to sample the current analogue
value of an input by simply reading the appropriate data register.
49
Digital to Analogue Converter (DAC)
The H8/304X device incorporates an 8-bit digital to analogue converter which has a maximum
conversion time of 6.2ms (φ = 16MHz). Two outputs are provided and multiplied with the
analogue to digital inputs. The output voltage range is from 0V through to the A/D reference
voltage.
50
H8/300H Summary
In the previous chapters we have given an overview as to why H8/300H gives the designers the
technical benefits that are demanded by today’s applications. Their purpose was to give you
enough insight into the features of the H8/300H family to see how you can benefit from the
performance, the rich set of peripherals and the memory options available. To summarize this:
• high performance CPU with architecture tailored for high level language software
development
• many low power, low voltage options
• memory line up from 16K to 256K ROM and 512Byte to 4K RAM, also version with 128K
Flash
• very powerful and sophisticated peripherals designed to offload the CPU and hence to
increase system performance
• full European technical and tool support
The following chapters are provided for you to select the right derivative for your application
from the H8/300H family.
51
Selection Guide (ROM-less)
Type No.
H8/3001
H8/3002
H8/3003
H8/3004
H8/3005
RAM (byte)
Vcc (V) / clock (MHz)
512
4.5-5.5/16
3.15-5.5/13
3.0-5.5/10
2.7-5.5/8
16M
8/16
5
-
512
4.5-5.5/16
3.0-5.5/10
2.7-5.5/8
512
4.5-5.5/16
3.0-5.5/10
2.7-5.5/8
16M
8/16
5
1
16M
8/16
5
1
2k
4.5-5.5/16
4.5-5.5/18
3.0-5.5/10
2.7-5.5/8
16M
8
5
1
4k
4.5-5.5/16
4.5-5.5/18
3.0-5.5/10
2.7-5.5/8
16M
8
5
1
1
12
4
2
2
16
8
4
2
16
1
-
1
-
4
20
4
8
Yes
Yes
4
30
7
8
Yes
Yes
8
34
9
8
Yes
21
6
8
Yes
21
6
32
FP-80A
TFP-80C
46
FP-100A*
FP-100B
TFP-100B
58
FP-112
TFP-80C
32
FP-80A
TFP-80C
32
FP-80A
Address space (byte)
External data bus (bit)
ITU (16-bit timer)
Watchdog timer
DMAC
Memory to/from I/O
Memory to Memory
SCI (async/sync)
TPC (bit)
ADC
10 bits
External trigger Input
Refresh controller
Chip select pins
Interrupts
Internal
External level
I/O
Package
* For availability of FP-100A please contact Hitachi or an authorized distributor
52
Selection Guide (ROM/ZTAT/Flash)
Type No.
H8/3030
H8/3031
H8/3032
H8/3040
H8/3041
H8/3042
ROM (byte)
16 k
32 k
64 k
32 k
48 k
64 k
RAM (byte)
512
1k
2k
2k
2k
2k
ZTAT(OTP)
-
-
Yes
-
-
Yes
Vcc (V) / clock (MHz)
Note 1
5/16
2.7-5.5/8
5/16
2.7-5.5/8
5/16
2.7-5.5/8
5/16
2.7-5.5/8
5/16
2.7-5.5/8
5/16
2.7-5.5/8
Address space (byte)
1M
1M
1M
16M
16M
16M
External data bus
(bit)
8
8
8
8/16
8/16
8/16
ITU (16-bit timer)
5
5
5
5
5
5
Watchdog timer
1
1
1
1
1
1
DMAC
Memory to/from I/O
Memory to Memory
-
-
-
4
2
4
2
4
2
SCI (async/sync)
1
1
1
2
2
2
TPC (bit)
16
16
16
16
16
16
ADC
10 bits
External trigger Input
8
Yes
8
Yes
8
Yes
8
Yes
8
Yes
8
Yes
8-bit DAC (channels)
-
-
-
2
2
2
Refresh controller
-
-
-
Yes
Yes
Yes
Chip select pins
-
-
-
4
4
4
Interrupts
Internal
External level
21
6
21
6
21
6
30
7
30
7
30
7
I/O
63
63
63
78
78
78
Package
FP-80A
TFP-80C
FP-80A
TFP-80C
FP-80A
TFP-80C
FP-100A*
FP-100B
TFP-100B
FP-100A*
FP-100B
TFP-100B
FP-100A*
FP-100B
TFP-100B
Note 1: 5V with±10% tolerance
* For availabilty of FP-100A please contact Hitachi or an authorized distributor
Now available up to 18MHz at 5V:
H8/3035
256K ROM/OTP
H8/3034
192K ROM
H8/3033
128K ROM
all with 4K RAM
53
Selection Guide (ROM/ZTAT/Flash)
Type No.
H8/3044
H8/3045
H8/3047
H8/3048
H8/3048F
ROM (byte)
32 k
64 k
96 k
128 k
128 k
RAM (byte)
2k
2k
4k
4k
4k
ZTAT(OTP)
-
-
-
Yes
Flash
Vcc (V) / clock (MHz)
Note 1
5/16
5/18
3.3/13
2.7/8
5/16
5/18
3.3/13
2.7/8
5/16
5/18
3.3/13
2.7/8
5/16
5/18
3.3/13
2.7/8
5/16
2.7-5.5/8
Address space (byte)
16M
16M
16M
16M
16M
External databus (bit)
8/16
8/16
8/16
8/16
8/16
ITU (16-bit timer)
5
5
5
5
5
Watchdog timer
1
1
1
1
1
DMAC
Memory to/from I/O
Memory to Memory
4
2
4
2
4
2
4
2
4
2
SCI (async/sync)
2
2
2
2
2
TPC (bit)
16
16
16
16
16
ADC
10 bits
External trigger Input
8
Yes
8
Yes
8
Yes
8
Yes
8
Yes
8-bit DAC (channels)
2
2
2
2
2
Smart card I/F
Yes
Yes
Yes
Yes
Yes
Refresh controller
Yes
Yes
Yes
Yes
Yes
Chip select pins
8
8
8
8
8
Interrupts
Internal
External level
30
7
30
7
30
7
30
7
30
7
I/O
78
78
78
78
78
Package
FP-100B
TFP-100B
FP-100B
TFP-100B
FP-100B
TFP-100B
FP-100B
TFP-100B
FP-100B
TFP-100B
Note 1: 5V with±10% tolerance
54
0.30 +- 0.10
0.12
0.10
0-5
20
0.80±0.30
0.50±0.10
0.50
41
P70 /AN0
P71 /AN1
Port 9
HWR
LWR
RAM
512 bytes
Address bus
AS
P72 /AN2
NMI
14.0
60
21
0.20 ± 0.05
1
1.60
o
1.00
0.10
0.17±0.05
40
14.0 ± 0.2
Interrupt controller
Bus controller
Address bus
Data bus (upper)
Data bus (lower)
H8/300H CPU
P73 /AN3
Port A
AV CC
AVSS
Programmable
timing pattern
controller (TPC)
PA 0 /TP0 /TCLKA
PA 1 /TP1 /TCLKB
PA 2 /TP2 /TIOCA 0 /TCLKC
Port B
PA 2 /TP2 /TIOCB 0 /TCLKD
Clock
osc.
PA 4 /TP4 /TIOCA 1 /A 23
PA 5 /TP5 /TIOCB 1 /A 22
PA 6 /TP6 /TIOCA 2 /A 21
PA 7 /TP7 /TIOCB 2 /A 20
MD0
1.20 Max
0.65
Data bus
0.00 Min
0.20 Max
1
+0.08
-0.05
80
+0.20
-0.16
61
3.05 Max
60
0.17
XTAL
2.70
EXTAL
0.10
PB 0 /TP8 /TIOCA 3
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
P8 0/IRQ 0
PB3 /TP11 /TIOCB 4
P8 1/IRQ 1
17.2+- 0.3
P61/BREQ
Port 6
P62/BACK
Port 8
v cc
v ss
v ss
v ss
v cc
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
D8
D9
D10
D11
D12
D13
D14
D15
H8/3001 series
Port 4
MD2
MD1
A19
O
/
A18
STBY
A17
RES
A16
A15
A14
A13
RD
A12
A11
61
80
A10
A9
P60/WAIT
A8
A7
A6
A5
A4
A3
16-bit
integrated
timer-pulse unit
(ITU)
A2
A1
A0
Serial communication
interface
(SCI) x 2 channels
P94 /SCK/IRQ4
A/D converter
P92/RXD
P90/TXD
Port 7
17.2 ± 0.3
14.0±0.2
12.0
41
40
0.10
20
21
0-5
o
55
56
1
0.08
0.10
51
50
25
0.50±0.20
0.50±0.10
0.50
14.0
26
1.0
0-10
1.00
0.10
P70 /AN0
P71 /AN1
Port A
P72 /AN2
Port 9
Programmable
timing pattern
controller (TPC)
P73 /AN3
P60/WAIT
P74 /AN4
AS
RD
RAM
512 bytes
Address bus
DMA controller
(DMAC)
P75 /AN5
LWR
Bus controller
Address bus
Data bus (upper)
Data bus (lower)
H8/300H CPU
P76 /AN6
NMI
P77 /AN7
VREF
AV CC
AVSS
HWR
PA 0 /TP0 /TEND0/TCLKA
PA 1 /TP1 /TEND1/TCLKB
PA 2 /TP2 /TIOCA 0 /TCLKC
PA 3 /TP3 /TIOCB 0 /TCLKD
Port B
PA 4 /TP4 /TIOCA 1 /A 23
PA 5 /TP5 /TIOCB 1 /A 22
Clock
osc.
75
0.20 ± 0.05
1
o
0.17±0.05
100
PA 6 /TP6 /TIOCA 2 /A 21
MD0
1.20 Max
76
16.0 ± 0.2
75
PA 7 /TP7 /TIOCB 2 /A 20
P8 0/RFSH/IRQ0
+0.08
-0.05
PB 0 /TP8 /TIOCA 3
P8 1/CS3/IRQ1
0.17
0.50
RESO
+0.20
-0.16
Data bus
0.00 Min
0.20 Max
0.20 +- 0.10
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
PB 3 /TP11 /TIOCB 4
XTAL
3.05 Max
2.70
PB5 /TP13 /TOCXB4
P8 2/CS2/IRQ2
PB 4 /TP12 /TOCXA4
EXTAL
0.12
16.0+- 0.3
P8 3/CS1/IRQ3
PB 6 /TP14 /DREQ0
PB7 /TP15 /DREQ1/ADTRG
P61/BREQ
Port 6
P62/BACK
Port 8
v cc
v cc
v cc
v ss
v ss
v ss
v ss
v ss
v ss
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
D8
D9
D10
D11
D12
D13
D14
D15
H8/3002 series
Port 4
MD2
MD1
A19
O
/
A18
STBY
RES
A17
A16
Interrupt controller
A15
A14
A13
A12
A11
76
100
A10
A9
Refresh
cotroller
A8
A7
A6
P84 /CS 0
A5
Watchdog timer
(WDT)
A4
A3
16-bit
integrated
timer-pulse unit
(ITU)
A2
A1
Serial communication
interface
(SCI) x2 channels
A0
P93/RXD1
P95/SCK1 /IRQ5
A/D converter
P92/RXD0
P94 /SCK0 /IRQ4
P91/TXD1
P90/TXD0
Port 7
16.0 ± 0.3
16.0±0.2
14.0
51
50
0.08
25
26
0-5
o
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
D8
D9
D10
D11
D12
D13
D14
v cc
v cc
v cc
v ss
v ss
v ss
v ss
v ss
v ss
D15
H8/3003 series
Data bus
Port 4
Port 5
P57/A23
P56/A22
P55/A21
P54/A20
MD2
H8/300H CPU
A19
Address bus
Clock
osc.
XTAL
Data bus (lower)
MD0
EXTAL
Data bus (upper)
MD1
A18
A17
O
/
A16
STBY
A15
RES
Interrupt controller
A14
NMI
AS
DMA controller
(DMAC)
A13
A12
A11
Address bus
RD
Bus controller
RESO
HWR
LWR
P61/BREQ
RAM
512 bytes
A10
A9
A8
Port 6
P62/BACK
A7
Refresh
cotroller
P60/WAIT
A6
A5
A4
P8 4/CS0
P8 2 /CS2/IRQ2
A3
Watchdog timer
(WDT)
Port 8
P8 3 /CS1/IRQ3
A2
A1
16-bit
integrated
timer-pulse unit
(ITU)
P81 /CS3/IRQ1
P8 0/RFSH/IRQ0
A0
Serial communication
interface
(SCI) x2 channels
P95/SCK1 /IRQ5
P94 /SCK0 /IRQ4
PC6 /IRQ6
P93/RXD1
Programmable
timing pattern
controller (TPC)
PC3/DREQ2/CS5
Port c
PC5/DREQ3/CS7
PC4/TEND3/CS6
Port 9
PC7 /IRQ7
A/D converter
P92/RXD0
P91/TXD1
P90/TXD0
PC2/TEND2/CS4
PC 1
PC 0
Port B
Port 7
P70 /AN0
P71 /AN1
P72 /AN2
P73 /AN3
P74 /AN4
P75 /AN5
P76 /AN6
P77 /AN7
PA 0 /TP0 /TCLKA /TEND0
PA 1 /TP1 /TCLKB /TEND1
PA 2 /TP2 /TIOCA 0 /TCLKC
PA 3 /TP3 /TIOCB 0 /TCLKD
PA 4 /TP4 /TIOCA 1
PA 5 /TP5 /TIOCB 1
PA 6 /TP6 /TIOCA 2
PA 7 /TP7 /TIOCB 2
PB 0 /TP8 /TIOCA 3
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
PB 3 /TP11 /TIOCB 4
PB5 /TP13 /TOCXB4
PB 4 /TP12 /TOCXA4
23.2 ± 0.3
20.0
57
84
85
56
0.65
23.2+- 0.3
112
29
1
+0.08
-0.05
1.6
0.17
+0.20
-0.16
0.13
3.05 Max
28
2.70
0.30 +- 0.10
0-5
0.10
0.1
PB 6 /TP14 /DREQ0
PB7 /TP15 /DREQ1/ADTRG
VREF
AV CC
AVSS
Port A
o
0.8±0.3
57
A19
D0
D1
D2
D3
D4
D5
D6
D7
v ss
v ss
v ss
v cc
v cc
H8/3004 and H8/3005 series
A18
A17
Data bus
A16
A15
Address bus
A14
A13
Data bus (upper)
A12
A11
Address bus
Data bus (lower)
MD2
MD1
MD0
EXTAL
XTAL
Clock
osc.
∅
A10
A9
A8
A7
H8/300H CPU
STBY
A6
RES
A5
RESO
NMI
A4
A3
Interrupt controller
A2
AS
RD
WR
A1
RAM*
Bus controller
A0
Wait-state controller
P83 /IRQ3
P82 /IRQ2
Port 8
Serial communication
interface (SCI) x 1 channel
Port 6
P60 /WAIT
P81 /IRQ1
Watching timer
P80 /IRQ0
A/D converter
16-bit
intrgrated timer unit
(ITU)
P94 /SCK /IRQ 4
Port 9
P9 2 /RXD1
P70 /AN 0
P71 /AN 1
P72 /AN 2
P73 /AN 3
P75 /AN 5
P76 /AN 6
P77 /AN 7
AV CC
AV SS
V REF
PA 0 / TCLKA
PA 1 / TCLKB
PA 2 / TIOCA0 /TCLKC
PA 3 / TIOCB 0 /TCLKD
PA 4 /TP4 /TIOCA 1 /A 23
PA 5 /TP5 /TIOCB 1 /A 22
PA 6 /TP6 /TIOCA 2 /A 21
PA 7 /TP7 /TIOCB 2 /A 20
PB 0 / TIOCA 3
PB 1 / TIOCB 3
PB 2 / TIOCA 4
P7 4 /AN 4
Port 7
Port A
PB 3 / TIOCB 4
PB 6
PB5 / TOCXB 4
PB 4 / TOCXA 4
PB7 / ADTRG
Port B
P9 0 /TXD0
14.0±0.2
Note: * 2 kbytes in the H8/3004, 4 kbytes in the H8/3005.
12.0
41
60
17.2 ± 0.3
14.0
61
40
80
0.65
17.2 ± 0.3
40
0.50
61
14.0 ± 0.2
41
60
21
1
80
25
21
+0.08
-0.05
1.60
58
0.10
M
0-5
0-5
0.10
0.10
0.17
+0.20
-0.16
3.05 Max
2.70
M
1.20 Max
1.00
20
0.12
o
0.80±0.30
0.10
0.50±0.10
0.00 Min
0.20 Max
1
0.30 ± 0.10
0.17±0.05
0.20 ± 0.05
o
P30 /D0
P31 /D1
P32 /D2
P33 /D3
P34 /D4
P35 /D5
P36 /D6
v ss
v ss
v ss
v cc
v cc
P37 /D7
H8/3032 series
Port 3
P53 /A15
P52 /A16
Port 5
MD2
Data bus (upper)
P51 /A17
MD1
P50 /A18
MD0
Data bus (lower)
EXTAL
Clock osc.
∅
STBY
Bus
controller
XTAL
H8/300H CPU
RES
RESO
P27 /A15
NMI
P26 /A14
P25 /A13
P24 /A12
Port 2
Interrupt
controller
PROM*
(or masked
ROM)
P23 /A11
P22 /A10
P6 5 /WR
P21 /A9
P6 4 /RD
P20 /A8
Port 6
P6 3 /AS
P6 0 /WAIT
P17 /A7
P16 /A6
P15 /A5
P14 /A4
Port 1
Watchdog
timer
(WDT)
RAM
P13 /A3
P12 /A2
P11 /A1
P8 3 / IRQ3
P81 / IRQ 1
P8 0/ IRQ 0
P10 /A0
Serial
connunication
interface
(SCI) x 1 channel
16-bit
integrated
timer-pulse unit
(ITU)
Port 8
P82 / IRQ 2
Programmable
timing pattern
controller (TPC)
P9 /SCK /IRQ 4
4
A/D converter
Port 9
P9 2 /RXD
Port B
P90/TXD
Port 7
P70 /AN 0
P71 /AN 1
P72 /AN 2
P73 /AN 3
P7 4 /AN 4
P75 /AN 5
P76 /AN 6
P77 /AN 7
PA 0 / TCLKA
PA 1 / TCLKB
PA 4 /TP4 /TIOCA 1
PA 2 / TIOCA 0 /TCLKC
PA 5 /TP5 /TIOCB 1
PA 3 / TIOCB 0 /TCLKD
PA 6 /TP6 /TIOCA 2
PA 7 /TP7 /TIOCB 2
PB 0 /TP8 /TIOCA 3
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
PB 3 /TP11 /TIOCB 4
PB 4 /TP12 /TOCXA4
PB 6 /TP14
PB5 /TP13 /TOCXB4
PB7 /TP15 /ADTRG
Vref
AV CC
AVSS
Port A
14.0±0.2
Note: PROM version is available only in the H8/3032 Series.
12.0
17.2 ± 0.3
41
60
14.0
61
21
0.65
0.50
80
40
80
21
1
20
0.20 ± 0.05
20
0.12
0-5
0.10
0.10
1.20 Max
1.60
0.17
+0.08
-0.05
3.05 Max
1.00
2.70
M
+0.20
-0.16
0.12
0-5
o
0.80±0.30
0.10
0.50±0.10
o
0.00 Min
0.20 Max
1
0.30 ± 0.10
M
0.17±0.05
40
17.2 ± 0.3
61
14.0±0.2
41
60
59
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
P30 /D8
P31 /D9
P32 /D10
P33 /D11
P34 /D12
P35 /D13
P36 /D14
v cc
v cc
v cc
v ss
v ss
v ss
v ss
v ss
v ss
P37 /D15
H8/3042 series
Port 3
Port 4
Address bus
P53 /A19
MD2
MD1
P52 /A18
Port 5
Data bus (upper)
P51 /A17
P50 /A16
Data bus (lower)
MD0
EXTAL
P27 /A15
XTAL
P26 /A14
∅
Clock
osc.
STBY
H8/300H CPU
P25 /A13
P24 /A12
Port 2
RES
RESO
P23 /A11
NMI
P22 /A10
Interrupt controller
P6 5 /HWR
DMA controller
(DMAC)
Port 6
P6 4 /RD
P6 3 /AS
Bus controller
P21 /A9
P6 6 /LWR
P20 /A8
P17 /A7
P16 /A6
PROM*
(or masked ROM)
P6 2 /BACK
P15 /A5
P14 /A4
Port 1
P6 1 /BREQ
P6 0 /WAIT
P13 /A3
P12 /A2
Refresh
cotroller
P11 /A1
P10 /A0
RAM
P84 /CS 0
Watchdog timer
(WDT)
Port 8
P8 3 /CS1 /IRQ 3
P82 /CS2 /IRQ2
P81 /CS3 /IRQ1
P8 0/RFSH/IRQ0
16-bit
integrated
timer-pulse unit
(ITU)
Serial communication
interface
(SCI) x2 channels
P95 /SCK /IRQ 5
1
P94 /SCK0 /IRQ4
Port 9
A/D converter
Programmable
timing pattern
controller (TPC)
P9 3 /RXD1
P9 2 /RXD0
P91/TXD1
D/A converter
P90/TXD0
Port B
Port 7
P70 /AN 0
P71 /AN 1
P72 /AN 2
P73 /AN 3
P7 4 /AN 4
P75 /AN 5
P76 /AN 6 /DA 0
P77 /AN 7 /DA 1
PA 0 /TP 0 /TEND0 /TCLKA
PA 1 /TP1 /TEND1 /TCLKB
PA 2 /TP2 /TIOCA 0 /TCLKC
PA 3 /TP3 /TIOCB 0 /TCLKD
PA 4 /TP4 /TIOCA 1 /A 23
PA 5 /TP5 /TIOCB 1 /A 22
PA 6 /TP6 /TIOCA 2 /A 21
PA 7 /TP7 /TIOCB 2 /A 20
PB 0 /TP8 /TIOCA 3
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
PB 3 /TP11 /TIOCB 4
PB5 /TP13 /TOCXB4
PB 4 /TP12 /TOCXA4
PB 6 /TP14 /DREQ0
PB7 /TP15 /DREQ1/ADTRG
VREF
AV CC
AVSS
Port A
16.0±0.2
Note: * H8/3042 only.
14.0
16.0 ± 0.3
51
75
14
76
26
0.50
0.50
100
50
100
26
1
25
0.20 ± 0.05
25
+0.08
-0.05
+0.20
-0.16
3.05 Max
1.00
1.0
0.08
0.17
M
2.70
0.08
1.20 Max
1
0.20 ± 0.10
0-5
60
0.12
0.50±0.20
0.10
0.50±0.10
0.00 Min
0.20 Max
o
0-10
0.10
M
0.17±0.05
50
16.0 ± 0.3
76
16.0 ± 0.2
51
75
o
P40 /D0
P41 /D1
P42 /D2
P43 /D3
P44 /D4
P45 /D5
P46 /D6
P47 /D7
P30 /D8
P31 /D9
P32 /D10
P33 /D11
P34 /D12
P35 /D13
P36 /D14
v cc
v cc
v cc
v ss
v ss
v ss
v ss
v ss
v ss
P37 /D15
H8/3048 series
Port 3
Port 4
Address bus
P53 /A19
P52 /A18
Port 5
Data bus (upper)
MD2
P51 /A17
MD1
P50 /A16
Data bus (lower)
MD0
EXTAL
P27 /A15
Clock pulse
generator
XTAL
∅
STBY
P26 /A14
H8/300H CPU
P25 /A13
P24 /A12
Port 2
RES
Vpp*/ RESO
P23 /A11
NMI
P22 /A10
Interrupt controller
P6 6 /LWR
ROM
(masked ROM,
PROM, or flash
memory)
P6 5 /HWR
Port 6
P6 4 /RD
P6 3 /AS
Bus controller
P21 /A9
DMA controller
(DMAC)
P20 /A8
P17 /A7
P16 /A6
P15 /A5
P14 /A4
Port 1
P6 2 /BACK
P6 1 /BREQ
P6 0 /WAIT
P13 /A3
P12 /A2
Refresh
cotroller
P11 /A1
P10 /A0
RAM
P84 /CS 0
Watchdog timer
(WDT)
Port 8
P8 3 /CS1 /IRQ 3
P82 /CS2 /IRQ2
P81 /CS3 /IRQ1
P8 0/RFSH/IRQ0
16-bit
integrated
timer-pulse unit
(ITU)
Serial communication
interface
(SCI) x2 channels
P95 /SCK /IRQ 5
1
P94 /SCK0 /IRQ4
Port 9
A/D converter
Programmable
timing pattern
controller (TPC)
P9 3 /RXD1
P9 2 /RXD0
P91/TXD1
D/A converter
P90/TXD0
Port B
Port 7
P70 /AN 0
P71 /AN 1
P72 /AN 2
P73 /AN 3
P7 4 /AN 4
P75 /AN 5
P76 /AN 6 /DA 0
P77 /AN 7 /DA 1
PA 0 /TP 0 /TEND0 /TCLKA
PA 1 /TP1 /TEND1 /TCLKB
PA 2 /TP2 /TIOCA 0 /TCLKC
PA 3 /TP3 /TIOCB 0 /TCLKD
PA 4 /TP4 /TIOCA 1 /A /23CS 6
PA 7 /TP7 /TIOCB 2 /A 20
PA 5 /TP5 /TIOCB 1 /A /22CS 5
PA 6 /TP6 /TIOCA 2 /A /21CS 4
PB 0 /TP8 /TIOCA 3
PB 1 /TP9 /TIOCB 3
PB 2 /TP10 /TIOCA 4
PB 3 /TP11 /TIOCB 4
PB5 /TP13 /TOCXB4
PB 4 /TP12 /TOCXA4
PB 6 /TP14 /DREQ0 /CS7
PB7 /TP15 /DREQ1/ADTRG
VREF
AV CC
AVSS
Port A
16.0±0.2
Note: * Vpp function is provided only for the flash memory version.
14.0
16.0 ± 0.3
51
75
14
76
26
0.50
0.50
100
50
100
26
1
25
0.20 ± 0.05
25
1.0
0.08
0.17
+0.08
-0.05
+0.20
-0.16
1.00
3.05 Max
M
2.70
0.08
1.20 Max
1
M
0-5
0.50±0.20
0.10
0.50±0.10
o
0.00 Min
0.20 Max
o
0-10
0.10
0.12
0.20 ± 0.10
0.17±0.05
50
16.0 ± 0.3
76
16.0 ± 0.2
51
75
61
Packages
16.0±0.3
14
24.8 ± 0.4
51
76
0.50
M
2.70
2.40
0.20
0-10
0.15
0.08
+0.20
-0.16
0.17 ± 0.05
+0.20
-0.16
3.05 Max
2.70
M
25
0.20 ± 0.10
30
0.13
26
1
+0.08
-0.06
0.65
1
100
1.0
0.17
31
3.05 Max
80
50
o
0-10
0.12
50
16.0 ± 0.3
81
14.0
18.8 ± 0.4
80
0.30 ± 0.10
51
75
20.0
1.20±0.20
0.10
FP-100A
o
0.50 ± 0.20
FP-100B
14.0±0.2
12.0
41
60
61
16.0 ± 0.2
76
80
21
1
0.65
16.0 ± 0.2
50
0.50
51
75
40
14.0±0.2
14.0
20
0.20 ± 0.05
100
0.10
M
26
0.00 Min
0.20 Max
0-5
0.10
0.50±0.10
0-5
o
0.10
0.50±0.10
FP-100B
0.17±0.05
1.00
1.20 Max
1.20 Max
M
1.00
0.17 ± 0.05
25
0.08
0.00 Min
0.20 Max
1
0.20 ± 0.05
TFP-100B
17.2 ± 0.3
14.0
23.2 ± 0.3
57
61
0.65
80
0.10
+0.20
-0.16
0-5
0.10
o
0.8 ± 0.30
62
M
1.60
0-5
0.10
TFP-100B
0.12
1.6
2.70
0.17 ± 0.5
3.05 Max
+0.20
-0.16
2.70
M
20
0.20 ± 0.05
28
0.13
21
1
TFP-80C
0.10
1
0.65
29
0.17 +0.20
-0.16
112
40
3.05 Max
56
23.2 ± 0.3
85
17.2 ± 0.3
84
0.30 ± 0.10
41
60
20
o
0.8 ± 0.30
o
Ordering Information
The following tables show the available derivatives for each series within the H8/300H family.
To build the actual part name append the desired clock rate to the part name's body. Example:
HD6413001F16 = H8/3001 in FP-80A package, 5V (±10%), 16mhz.
For details of the operating voltage range for ROM-less derivatives, please refer to the selection
guides on page 27.
63
H8/3001 Body
HD6413001
H8/3002 Body
HD6413002
H8/3003 Body
HD6413003
H8/3004 Body
HD6413004
H8/3005 Body
HD6413005
Package suffix
Package/Voltage/Temp.
available clock
F
16,18
FP-80A/5V
TF
16,18
TFP-80C/5V
VF
8,10,13
FP-80A/low
VTF
8,10,13
TFP-80C/low
o
0
Fl
16,18
FP-80A/5V/-40 C..85 C
o
o
TFP-80C/5V/-40 C..85 C
TFI
16,18
o
o
FP-80A/low/-40 C..85 C
VFI
8,10,13
o
o
TFP-80C/low/-40 C..85 C
VTFI
8,10,13
Package suffix
Package/Voltage/Temp.
available clock
F
10,12,16,17
FP-100B/5V
FP
16,17
FP-100A*/5V
TF
10,12,16,17
TFP-100B/5V
VF
8,10
FP-100B/low
VFP
8,10
FP-100A*/low
VTF
8,10
TFP-100B/low
o
o
Fl
10,12,16,17
FP-100B/5V/-40 C..85 C
o
o
TFP-100B/5V/-40 C..85 C
TFI
10,12,16,17
o
o
FP-100B/low/-40 C..85 C
VFI
8,10
o
o
TFP-100B/low/-40 C..85 C
VTFl
8,10
o
o
FP-100B/5V/-40 C..85 C
FJ
10,12,16,17
o
o
FP-100A*/5V/-40 C..85 C
FQ
16,17
Package suffix
Package/Voltage/Temp.
available clock
10,12,16
RF
FP-112/5V
10,12,16
TF
FP-112/5V
8,10
RVF
FP-112/low
8,10
TVF
FP-112/low
o
o
10,12,16
RFI
FP-112/5V/-40 C..85 C
o
o
FP-112/5V/-40 C..85 C
10,12,16
TFI
o
o
FP-112/low/-40 C..85 C
8,10
RVFI
o
o
FP-112/low/-40 C..85 C
8,10
TVFI
o
o
FP-112/5V/-40 C..85 C
10,12,16
RFJ
o
o
FP-112/5V/-40 C..85 C
10,12,16
TFJ
Note:
For H8/3003 derivatives with a package suffix starting “R”, a crystal with
double frequency is required, because of an internal divider by 2.
Package suffix
Package/Voltage/Temp.
available clock
16,18
F
FP-80A/5V
16,18
TE
TFP-80C/5V
8,10
VF
FP-80A/low
8,10
VTE
TFP-80C/low
o
o
16,18
Fl
FP-80A/5V/-40 C..85 C
o
o
TFP-80C/5V/-40 C..85 C
16,18
TEI
o
o
FP-80A/low/-40 C..85 C
8,10
VFI
o
o
TFP-80C/low/-40 C..85 C
8,10
VTEI
o
o
FP-80A/5V/-40 C..85 C
16,18
FJ
Package suffix
Package/Voltage/Temp.
available clock
16,18
F
FP-80A/5V
16,18
TE
TFP-80C/5V
8,10
VF
FP-80A/low
8,10
VTE
TFP-80C/low
o
o
16,18
Fl
FP-80A/5V/-40 C..85 C
o
o
TFP-80C/5V/-40 C..85 C
16,18
TEI
o
o
FP-80A/low/-40 C..85 C
8,10
VFI
o
o
TFP-80C/low/-40 C..85 C
8,10
VTEl
o
o
FP-80A/5V/-40 C..85 C
16,18
FJ
* For availability of FP-100A please contact Hitachi or an authorized distributor
64
For all of the parts with mask ROM, ZTAT or Flash the operating voltage range is
2.7..5.5V/8MHz, 3.0V..5.5V/10MHz, 3.15V..5.5V/13MHz and 4.5..5.5V otherwise.
H8/3032 (ZTAT)
Body
HD6473032
Package suffix
F
TF
VF
VTF
Fl
TFI
VFI
VTFI
FJ
Package/Voltage/Temp.
FP-80A/5V
TFP-80C/5V
FP-80A/low
TFP-80C/low
o
0
FP-80A/5V/-40 C..85 C
o
o
TFP-80C/5V/-40 C..85 C
o
o
FP-80A/low/-40 C..85 C
o
o
TFP-80C/low/-40 C..85 C
o
0
FP-80A/5V/-40 C..85 C
available clock
16,18
16,18
8,10
8,10
16,18
16,18
8,10
8,10
16,18
Package suffix
F
FP
TF
VF
VFP
VTF
Fl
TFI
VFI
VTFl
FJ
FQ
Package/Voltage/Temp.
FP-100B/5V
FP-100A*/5V
TFP-100B/5V
FP-100B/low
FP-100A*/low
TFP-100B/low
o
o
FP-100B/5V/-40 C..85 C
o
o
TFP-100B/5V/-40 C..85 C
o
o
FP-100B/low/-40 C..85 C
o
o
TFP-100B/low/-40 C..85 C
o
o
FP-100B/5V/-40 C..85 C
o
o
FP-100A*/5V/-40 C..85 C
available clock
10,12,16,17
16,17
10,12,16,17
8,10
8,10
8,10
10,12,16,17
10,12,16,17
8,10
8,10
10,12,16,17
16,17
Package suffix
F
TF
VF
VTF
FI
TFI
VFI
VTFI
FJ
H8/3048 (F-ZTAT= Flash memory)
Body
Package suffix
HD64F3048
F
TF
VF
VTF
FI
TFI
VFI
VTFI
FJ
Package/Voltage/Temp.
FP-100B/5V
TFP-100B/5V
FP-100B/low
TFP-100B/low
o
o
FP-100B/5V/-40 C..85 C
o
o
TFP-100B/5V/-40 C..85 C
o
o
FP-100B/low/-40 C..85 C
o
o
TFP-100B/low/-40 C..85 C
o
o
FP-100B/5V/-40 C..85 C
available clock
16,18
16,18
8,13
8,13
16,18
16,18
8,13
8,13
16,18
Package/Voltage/Temp.
FP-100B/5V
TFP-100B/5V
FP-100B/low
TFP-100B/low
o
o
FP-100B/5V/-40 C..85 C
o
o
TFP-100B/5V/-40 C..85 C
o
o
FP-100B/low/-40 C..85 C
o
o
TFP-100B/low/-40 C..85 C
o
o
FP-100B/5V/-40 C..85 C
available clock
16
16
8
8
16
16
8
8
16
H8/3042 (ZTAT)
Body
HD6473042S
H8/3048 (ZTAT)
Body
HD6473048S
65
H8/3040 (pseudo ROM-less version)
This device is a mask ROM H8/3040 with a blank ROM, for which standard ROM-less
commercial criteria apply (e.g. minimum order quantity). The part names comply with the
masked ROM naming rule (please refer to next page).
Body
HD6433040S
Vcc/clock suffix
Package suffix
Package/Temperature
FP-100B
00F
A, P, T, V
FP-100A
00FP
A, P, T, V
TFP-100B
00TF
A, P, T, V
o
o
FP-100B/-40 C..85 C
00FI
A, P, T, V
o
o
00TFI
A, P, T, V
TFP-100B/-40 C..85 C
o
o
00FJ
A, P
FP-100B/-40 C..85 C
o
o
00FQ
A, P
FP-100A/-40 C..85 C
Vcc/clock suffix:
A
16MHz/5V
P
17MHz/5V
T
10MHz/3.0..5.5V
V
8MHz/2.7..5.5V
Example: HD6433040SA00FP is a pseudo ROM-less H8/3040 in a FP-100A package, 16MHz, 5V and standard
o
o
temperature (-20 C..75 C).
* For availability of FP-100A please contact Hitachi or an authorized distributor
H8/3044 (pseudo ROM-less version)
This device is a mask ROM H8/3044 with a blank ROM, for which standard ROM-less
commercial criteria apply (e.g. minimum order quantity). The part names comply with the
masked ROM naming rule (please see below). It will be available in the first quarter 1997.
Body
HD6433044s
Vcc/clock suffix
A, M, S, V
A, M, S, V
A, M, S, V
A, M, S, V
A, M
A
M
S
V
66
Package suffix
00F
00TF
00FI
00TFI
00FJ
Vcc/clock suffix:
16MHz/5V
18MHz/5V
13MHz/3.15..5.5V
8MHz/2.7..5.5V
Package/Temperature
FP-I00B
TFP-I00B
o
o
FP-100B/-40 C..85 C
o
o
TFP-100B/-40 C..85 C
o
o
FP-I00B/-40 C..85 C
Naming rule for H8/300H mask ROM parts
HD643 + device body+ revision + code/speed + ROM code + package
4-digit code of desired H8/300H derivative, e.g. 3042 for H8/3042
device body
S for mask revision or omitted, for new inquiries always use “S”
revision
2-digit number assigned to mask after customer code submission
ROM code
16MHz/5V
code/speed
A..E
12MHz/5V
F..H
10MHZ/5V
K,L
18MHz/5V
M
17MHz/5V
P
13MHz/3.15..5.5V
S
I0MHz/3.0..5.5V
T,U
8MHz/2.7..5.5V
V,W
When the “ROM code” overflows (>99) the “code/speed” digit advances, e.g. from A99 to B00.
package
F
Fl
FJ
FP
FQ
TF
TFI
QFP
QFP
QFP
QFP
QFP
TQFP
TQFP
14mm x 14mm
14mm x 14mm
14mm x 14mm
14mm x 20mm
14mm x 20mm
14mm x 14mm
14mm x 14mm
I-spec
J-spec
J-spec
I-spec
Example: HD6433032SMxxF is a mask ROM H8/3032S (mask revision), with 18MHz/5V in
FP-80A package (14mm x 14mm) in standard spec. xx will be determined after ROM code
submission.
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Microcontrollers for wide temperature range (WTR)
All of Hitachi's microcontrollers are available in several temperature ranges. The standard
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temperature range is -20 C..75 C and is not indicated in the package suffix.
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-40 C..85 C (I and J-spec)
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Hitachi offers two specifications for -40 C..85 C. These are indicated in the package suffix by I
and J. I-spec has a wider temperature range compared with standard spec, but has the same
reliability. J-spec has improved reliability compared with standard spec. Hitachi recommends to
use J-spec for critical applications, particularly in industrial and automotive applications.
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-40 C..105 C (JE-spec)
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JE-spec has the same reliability as J-spec but extends the operating temperature range to 105 C.
This should - for example - be used in critical applications for automotive safety.
-40 C..125 C (K-spec)
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K-spec further extends the temperature range to 125 C and also improves reliability over JEspec. We recommend this for important safety features in the automotive market, where the
product is installed e.g. near the engine.
If you require JE- or K-spec, please contact your Hitachi sales office or authorized
distributor.
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