HD9P6409-9Z96

Datasheet HD-6409 CMOS Manchester Encoder-Decoder The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned silicon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Nonreturn-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deficiencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Features • Converter or Repeater Mode • Independent Manchester encoder and decoder operation • Static to 1Mbps data rate ensured • Low bit error rate • Digital PLL clock recovery • On-chip oscillator • Low operating power: 50mW Typical at +5V • Pb-Free (RoHS Compliant) Related Literature For a full list of related documents, visit our website: • HD-6409 device page Manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers. SDO NVM BOI BZI BOO Data Input Logic 5-Bit Shift Register and Decoder UDI Output Select Logic Command Sync Generator Edge Detector BZO CTS SRST RST Reset SD SD/CDS Input/ Output Select Manchester Encoder MS IX OX Oscillator ECLK DCLK Counter Circuits CO SS Figure 1. Block Diagram FN2951 Rev.5.00 Jul.8.19 Page 1 of 18 HD-6409 1. 1.1 1. Overview Overview Logic Symbol 17 11 SS CO 13 CLOCK GENERATOR 4 16 SD/CDS ECLK ENCODER 14 9 MS RST NVM 1.2 19 18 15 BOO BZO 2 1 3 6 SRST OX IX CTS CONTROL 5 8 7 SDO DCLK 12 BOI BZI UDI DECODER Ordering Information Part Number (1Mbps) (Notes 2, 3) Part Marking Temp. Range (°C) Tape and Reel (Units) (Note 1) Package (RoHS Compliant) Pkg. Dwg. # HD3-6409-9Z (No longer available or supported) HD3-6409-9Z -40 to +85 - 20 Ld PDIP E20.3 HD9P6409-9Z HD9P6409-9Z -40 to +85 - 20 Ld SOIC M20.3 HD9P6409-9Z96 HD9P6409-9Z -40 to +85 1k 20 Ld SOIC M20.3 Notes: 1. See TB347 for details on reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the HD-6409 device page. For more information about MSL, see TB363. 1.3 Pin Configuration 20 Ld PDIP, SOIC Top View BZI 1 BOI 2 19 BOO UDI 3 18 BZO SD/CDS 4 17 SS SDO 5 16 ECLK SRST 6 15 CTS NVM 7 14 MS DCLK 8 13 OX RST 9 12 IX GND 10 FN2951 Rev.5.00 Jul.8.19 20 VCC 11 CO Page 2 of 18 HD-6409 1.4 1. Overview Pin Descriptions Pin Number Type Symbol Name Description 1 I BZl Bipolar Zero Input Used in conjunction with Pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using Pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in conjunction with Pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using Pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) inputs Manchester II encoded data to the decoder. When using Pin 1 (BZl) and Pin 2 (BOl) for data input, UDI must be held low. 4 I/O 5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. 6 O SRST Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7 O NVM Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. 8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). 9 I RST Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK, and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received. 10 I GND Ground Ground 11 O CO Clock Output Buffered output of clock input IX. Can be used as a clock signal for other peripherals. 12 I IX Clock Input IX is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O OX Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crystal. 14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation in the repeater mode. 15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. 16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output that receives serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. 17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. SD/CDS Serial Data/Command Data Sync FN2951 Rev.5.00 Jul.8.19 In the converter mode, SD/CDS is an input that receives serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. Page 3 of 18 HD-6409 1. Overview Pin Number Type Symbol Name 18 O BZO Bipolar Zero Output 19 O BOO Bipolar One Out 20 I VCC VCC Description BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state. VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (Pin 20) to GND (Pin 10) is recommended. Note: (I) Input(O) Output FN2951 Rev.5.00 Jul.8.19 Page 4 of 18 HD-6409 2. 2.1 2. Specifications Specifications Absolute Maximum Ratings Parameter Minimum Supply Voltage Input, Output or I/O Voltage GND - 0.5 ESD Classification Maximum Unit +7.0 V VCC + 0.5 V Class 1 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W) PDIP Package 75 N/A SOIC Package 100 N/A Notes: 4. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. Parameter Minimum Maximum Unit -65 +150 °C Ceramic Package +175 °C Plastic Package +150 °C Storage Temperature Range Maximum Junction Temperature Pb-Free Reflow Profile (Note 5) see TB493 Note: 5. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 2.3 Operating Conditions Parameter Minimum Maximum Unit Operating Temperature Range -40 +85 °C Operating Voltage Range +4.5 +5.5 V Input Rise and Fall Times 50 ns Sync. Transition Span (t2) 1.5 Typical, (Notes 6, 7) DBP Short Data Transition Span (t4) 0.5 Typical, (Notes 6, 7) DBP Long Data Transition Span (t5) 1.0 Typical, (Notes 6, 7) DBP Zero Crossing Tolerance (tCD5) (Note 8) Notes: 6. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 7. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32X mode). 8. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode) from the nominal. 2.4 Die Characteristics Parameter Gate Counts FN2951 Rev.5.00 Jul.8.19 Value 250 Page 5 of 18 HD-6409 2.5 2. Specifications DC Electrical Specifications VCC = 5.0V ± 10%, TA = -40°C to +85°C Parameter Symbol Test Conditions (Note 9) Min (Note 11) Max (Note 11) Unit Logical “1” Input Voltage VIH VCC = 4.5V 70% VCC - V Logical “0” Input Voltage VIL VCC = 4.5V - 20% VCC V Logic “1” Input Voltage (Reset) VIHR VCC = 5.5V VCC -0.5 - V Logic “0” Input Voltage (Reset) VILR VCC = 4.5V - GND +0.5 V Logical “1” Input Voltage (Clock) VIHC VCC = 5.5V VCC -0.5 - V Logical “0” Input Voltage (Clock) VILC VCC = 4.5V - GND +0.5 V Input Leakage Current (Except IX) II VIN = VCC or GND, VCC = 5.5V -1.0 +1.0 µA Input Leakage Current (IX) II VIN = VCC or GND, VCC = 5.5V -20 +20 µA I/O Leakage Current IO VOUT = VCC or GND, VCC = 5.5V -10 +10 µA Output HIGH Voltage (All Except OX) VOH IOH = -2.0mA, VCC = 4.5V (Note 10) VCC -0.4 - V Output LOW Voltage (All Except OX) VOL IOL = +2.0mA, VCC = 4.5V (Note 10) - 0.4 V Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open - 100 µA Operating Power Supply Current ICCOP f = 16.0MHz, VIN = VCC or GND VCC = 5.5V, CL = 50pF - 18.0 mA (Note 9) - - - Functional Test FT Notes: 9. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH ≥ VCC/2, and VOL≤ VCC/2, VCC = 4.5V and 5.5V. 10. Interchanging of force and sense conditions is permitted. 11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 2.6 Capacitance TA = +25°C, Frequency = 1MHz. Parameter Input Capacitance Output Capacitance 2.7 Symbol CIN Test Conditions All measurements are referenced to device GND COUT Typ Unit 10 pF 12 pF AC Electrical Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C Parameter Symbol Test Conditions (Note 12) Min (Note 11) Max (Note 11) Unit Clock Frequency fC - 16 MHz Clock Period tC 1/fC - sec Bipolar Pulse Width t1 tC+10 - ns One-Zero Overlap t3 - tC-10 ns Clock High Time tCH f = 16.0MHz 20 - ns Clock Low Time tCL f = 16.0MHz 20 - ns Serial Data Setup Time tCE1 120 - ns Serial Data Hold Time tCE2 0 - ns DCLK to SDO, NVM tCD2 - 40 ns ECLK to BZO tR2 - 40 ns FN2951 Rev.5.00 Jul.8.19 Page 6 of 18 HD-6409 2. Specifications VCC = 5.0V ±10%, TA = -40°C to +85°C (Continued) Parameter Symbol Test Conditions (Note 12) Min (Note 11) Max (Note 11) Unit Output Rise Time (All except Clock) tr From 1.0V to 3.5V, CL = 50pF, Note 13 - 50 ns Output Fall Time (All except Clock) tf From 3.5V to 1.0V, CL = 50pF, Note 13 - 50 ns Clock Output Rise Time tr From 1.0V to 3.5V, CL = 20pF, Note 13 - 11 ns Clock Output Fall Time tf From 3.5V to 1.0V, CL = 20pF, Note 13 - 11 ns ECLK to BZO, BOO tCE3 Notes 13, 14 0.5 1.0 DBP CTS Low to BZO, BOO Enabled tCE4 Notes 13, 14 0.5 1.5 DBP CTS Low to ECLK Enabled tCE5 Notes 13, 14 10.5 11.5 DBP CTS High to ECLK Disabled tCE6 Notes 13, 14 - 1.0 DBP CTS High to BZO, BOO Disabled tCE7 Notes 13, 14 1.5 2.5 DBP UDI to SDO, NVM tCD1 Notes 13, 14 2.5 3.0 DBP RST Low to CDLK, SDO, NVM Low tCD3 Notes 13, 14 0.5 1.5 DBP RST High to DCLK, Enabled tCD4 Notes 13, 14 0.5 1.5 DBP UDI to BZO, BOO tR1 Notes 13, 14 0.5 1.0 DBP UDI to SDO, NVM tR3 Notes 13, 14 2.5 3.0 DBP Notes: 12. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF. 13. Limits established by characterization and are not production tested. 14. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. FN2951 Rev.5.00 Jul.8.19 Page 7 of 18 HD-6409 2.8 2. Specifications Timing Waveforms Note: UDI = 0, For Next Diagrams Bit Period BOI Bit Period Bit Period T1 t2 t3 t3 t1 BZI t2 Command Sync t1 BOI t2 t3 t3 t1 BZI Data Sync t2 t1 t1 BOI t3 BZI t3 t3 t3 t3 t1 t4 t5 One t5 t4 Zero One Note: BOI = 0, BZI = 1 For Next Diagrams t2 UDI t2 Command Sync t2 UDI t2 Data Sync t4 UDI t5 One t5 t4 Zero One t4 One Figure 2. tC tr 10% tCL tf tr 90% tCH 1.0V 3.5V tf Figure 3. Clock Timing FN2951 Rev.5.00 Jul.8.19 Figure 4. Output Waveform Page 8 of 18 HD-6409 2. Specifications ECLK tCE2 tCE1 SD/CDS tCE3 BZO BOO Figure 5. Encoder Timing CTS CTS BZO tCE6 ECLK tCE4 BOO tCE7 BZO tCE5 BOO ECLK Figure 6. Encoder Timing Figure 7. Encoder Timing DCLK tCD5 UDI Manchester Logic-1 Manchester Logic-0 tCD1 Manchester Logic-0 Manchester Logic-1 tCD2 SDO NRZ Logic-1 tCD2 NVM Note: Manchester Data-In is not synchronous with Decoder Clock. Decoder Clock is synchronous with decoded NRZ out of SDO. 15. Figure 8. Decoder Timing RST 50% RST tCD3 DCLK, SDO, NVM tCD4 50% Figure 9. Decoder Timing FN2951 Rev.5.00 Jul.8.19 50% DCLK Figure 10. Decoder Timing Page 9 of 18 HD-6409 2. Specifications UDI Manchester ‘1’ Manchester ‘0’ Manchester ‘0’ Manchester ‘1’ ECLK BZO tR2 tR1 tR2 Manchester ‘1’ Manchester ‘0’ Manchester ‘0’ tR3 SDO tR3 NVM Figure 11. Repeater Timing 2.9 Test Load Circuit DUT CL (Note) Note: Includes Stray and Jig Capacitance Figure 12. Test Load Circuit FN2951 Rev.5.00 Jul.8.19 Page 10 of 18 HD-6409 3. 3.1 3. Functional Descriptions Functional Descriptions Encoder Operation The encoder uses free running clocks at 1X and 2X the data rate derived from the system clock lX for internal timing. CTS controls the encoder outputs, ECLK, BOO, and BZO. A free running 1X ECLK is transmitted out of the encoder to drive the external circuits which supply the NRZ data to the MED at pin SD/CDS. A low on CTS enables encoder outputs ECLK, BOO, and BZO, while a high on CTS forces BZO, BOO high and holds ECLK low. When CTS goes from high to low 1 , a synchronization sequence is transmitted out on BOO and BZO. A synchronization sequence consists of eight Manchester “0” bits followed by a command sync pulse. 2 A command sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high followed by 1 1/2 bits low. 3 Serial NRZ data is clocked into the encoder at SD/CDS on the high to low transition of ECLK during the command sync pulse. The NRZ data received is encoded into Manchester II data and transmitted out on BOO and BZO following the command sync pulse. 4 Following the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. The length of the data block encoded is defined by CTS. Manchester data out is inverted. CTS 1 ECLK Don’t Care SD/CDS ‘1’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’ BZO 2 0 0 0 0 0 0 0 0 3 4 BOO Eight “0’s” Command Sync Synchronization Sequence tCE6 tCE5 Figure 13. Encoder Operation 3.2 Decoder Operation The decoder requires a single clock with a frequency 16X or 32X the desired data rate. The rate is selected on the speed select with SS low producing a 16X clock and high a 32X clock. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The internal operation of the decoder utilizes a free running clock synchronized with incoming data for its clocking. The Manchester II encoded data can be presented to the decoder in either of two ways. The Bipolar One and Bipolar Zero inputs accept data from differential inputs such as a comparator sensed transformer coupled bus. The Unipolar Data input can only accept noninverted Manchester II encoded data, such as Bipolar One Out through an inverter to Unipolar Data Input. The decoder continuously monitors this data input for valid sync pattern. Note that while the MED encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. A data sync is a logically inverted command sync. There is a 3-bit delay between UDI, BOl, or BZI input and the decoded NRZ data transmitted out of SDO. Control of the decoder outputs is provided by the RST pin. When RST is low, SDO, DCLK, and NVM are forced low. When RST is high, SDO is transmitted out synchronously with the recovered clock DCLK. The NVM output remains low after a low-to-high transition on RST until a valid sync pattern is received. The decoded data at SDO is in NRZ format. DCLK is provided so that the decoded bits can be shifted into an external register on every high-to-low transition of this clock. Three bit periods after an invalid Manchester bit is FN2951 Rev.5.00 Jul.8.19 Page 11 of 18 HD-6409 3. Functional Descriptions received on UDI, or BOl, NVM goes low synchronously with the questionable data output on SDO. Note: The decoder does not re-establish proper data decoding until another sync pattern is recognized. DCLK UDI Command Sync 1 0 0 1 0 1 0 1 0 1 0 1 0 SDO RST NVM Figure 14. Decoder Operation 3.3 Repeater Operation Manchester Il data can be presented to the repeater in either of two ways. The inputs Bipolar One In and Bipolar Zero In accept data from differential inputs such as a comparator or sensed transformer coupled bus. The input Unipolar Data In accepts only noninverted Manchester II coded data. The decoder requires a single clock with a frequency 16X or 32X the desired data rate. This clock is selected to 16X with Speed Select low and 32X with Speed Select high. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The inputs UDl, or BOl, BZl are delayed approximately 1/2 bit period and repeated as outputs BOO and BZO. The 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO. A low on CTS enables ECLK, BOO, and BZO. In contrast to the converter mode, a transition on CTS does not initiate a synchronization sequence of eight 0’s and a command sync. The repeater mode does recognize a command or data sync pulse. SD/CDS is an output which reflects the state of the most recent sync pulse received, with high indicating a command sync and low indicating a data sync. When RST is low, the outputs SDO, DCLK, and NVM are low, and SRST is set low. SRST remains low after RST goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. The reset bit is the first data bit after the sync pulse. With RST high, NRZ Data is transmitted out of Serial Data Out synchronously with the 1X DCLK. Input Count 1 2 3 4 5 6 7 ECLK Sync Pulse UDI BZO BOO RST SRST Figure 15. Repeater Operation FN2951 Rev.5.00 Jul.8.19 Page 12 of 18 HD-6409 3.4 3. Functional Descriptions Manchester Code Nonreturn-to-Zero (NRZ) code represents the binary values logic-0 and Iogic-1 with a static level maintained throughout the data cell. In contrast, Manchester code represents data with a level transition in the middle of the data cell. Manchester has bandwidth, error detection, and synchronization advantages over NRZ code. The Manchester II code Bipolar One and Bipolar Zero shown below are logical complements. The direction of the transition indicates the binary value of data. A logic-0 in Bipolar One is defined as a low-to-high transition in the middle of the data cell, and a logic-1 as a high-to-low mid bit transition, Manchester Il is also known as Biphase-L code. The bandwidth of NRZ is from DC to the clock frequency fc/2, while that of Manchester is from fc/2 to fc. Thus, Manchester can be AC or transformer coupled, which has considerable advantages over DC coupling. Also, the ratio of maximum to minimum frequency of Manchester extends one octave, while the ratio for NRZ is the range of 5 to 10 octaves. It is much easier to design a narrow band than a wideband amp. Secondly, the mid bit transition in each data cell provides the code with an effective error detection scheme. If noise produces a logic inversion in the data cell such that there is no transition, an error indiction is given, and synchronization must be re-established. This places relatively stringent requirements on the incoming data. The synchronization advantages of using the HD-6409 and Manchester code are several fold. One is that Manchester is a self clocking code. The clock in serial data communication defines the position of each data cell. Non self clocking codes, as NRZ, often require an extra clock wire or clock track (in magnetic recording). Further, there can be a phase variation between the clock and data track. Crosstalk between the two may be a problem. In Manchester, the serial data stream contains both the clock and the data, with the position of the mid bit transition representing the clock, and the direction of the transition representing data. There is no phase variation between the clock and the data. A second synchronization advantage is a result of the number of transitions in the data. The decoder resynchronizes on each transition, or at least once every data cell. In contrast, receivers using NRZ, which does not necessarily have transitions, must resynchronize on frame bit transitions, which occur far less often, usually on a character basis. This more frequent resynchronization eliminates the cumulative effect of errors over successive data cells. A final synchronization advantage concerns the HD-6409’s sync pulse that initiates synchronization. This 3-bit wide pattern is sufficiently distinct from Manchester data that a false start by the receiver is unlikely. Bit Period 1 2 3 4 5 Binary Code 0 1 1 0 0 Nonreturn-to-Zero Bipolar One Bipolar Zero Figure 16. Manchester Code FN2951 Rev.5.00 Jul.8.19 Page 13 of 18 HD-6409 3.5 3. Functional Descriptions Crystal Oscillator and LC Oscillator Modes C1 IX C0 R1 16MHz X1 C1 C1 = 32pF C0 = Crystal + Stray X1 = At Cut Parallel Resonance Fundamental Mode RS (Typical) = 30Ω OX R1 = 15MΩ IX L C1 OX CO C1 Figure 17. Crystal Oscillator Mode 3.6 C1 = 20pF C0 = 5pF c – 2C 1 0 C  -----------------------E 2 1 f  ----------------------O 2 LC e Figure 18. LC Oscillator Mode Using the 6409 as a Manchester Encoded UART BIPOLAR IN BZI VCC BIPOLAR IN BOI BOO BIPOLAR OUT UDI BZO BIPOLAR OUT SD/CDS SDO RESET SS ECLK SRST CTS NVM MS DCLK OX RST IX GND CO CTS LOAD A CP B CK ‘164 QH A DATA IN ‘273 B CK ‘164 DATA IN ‘273 CK LOAD ‘165 QH SI CK LOAD QH ‘165 Parallel Data In Parallel Data Out Figure 19. Manchester Encoder UART FN2951 Rev.5.00 Jul.8.19 Page 14 of 18 HD-6409 4. 4. Revision History Revision History Rev. Date Description 5.00 Jul.8.19 Applied new formatting throughout. Updated links throughout. Added Related Literature. Updated Ordering Information table by adding tape and reel information, removing HD3-6409-9, and updating Notes 1 and 3. Removed About Intersil section. Updated Disclaimer 4.00 Oct.1.15 Added Rev History beginning with Rev 4. Added About Intersil Verbiage. Updated Ordering Information on page 1 Updated POD M20.3 to most current version. Revision changes are as follows: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern FN2951 Rev.5.00 Jul.8.19 Page 15 of 18 HD-6409 5. 5. Package Outline Drawings Package Outline Drawings For the most recent package outline drawing, see M20.3. M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 7.60 7.40 1 2 10.65 10.00 0.25 (0.10) M B M 3 3 TOP VIEW 13.00 12.60 SEATING PLANE 2 2.65 2.35 5 0.75 1.27 BSC 0.49 0.35 7 0.25 (0.10) M 0.25 0.30 MAX C A M B S 1.27 0.40 x 45° 8° MAX 0.10 (0.004) SIDE VIEW DETAIL "X" 0.32 0.23 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 20 (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 TYPICAL RECOMMENDED LAND PATTERN FN2951 Rev.5.00 Jul.8.19 9. Dimensions in ( ) for reference only. 10. JEDEC reference drawing number: MS-013-AC. Page 16 of 18 HD-6409 5. Package Outline Drawings For the most recent package outline drawing, see E20.3. E20.3 (JEDEC MS-001-AD ISSUE D) 20 Lead Dual-In-Line Plastic Package (PDIP) N E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL MAX A - A1 0.015 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 -B-AE D BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS MIN C eB Notes: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. MIN MAX NOTES 0.210 - 5.33 4 - 0.39 - 4 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 0.430 - 10.92 7 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 20 20 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN2951 Rev.5.00 Jul.8.19 Page 17 of 18 1RWLFH  'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV DQGDSSOLFDWLRQH[DPSOHV