DATASHEET
HI-303
FN3125
Rev 1.00
Oct 1, 2015
Dual, SPDT CMOS Analog Switch
The HI-303 switch is a monolithic device fabricated using
CMOS technology and the Intersil dielectric isolation
process. This switch features break-before-make switching,
low and nearly constant ON resistance over the full analog
signal range, and low power dissipation.
Features
The HI-303 is TTL compatible and has a logic “0” condition
with an input less than 0.8V and a logic “1” condition with an
input greater than 4V. (See pinouts for switch conditions with
a logic “1” input.)
• Low On Resistance at 25oC . . . . . . . . . . . . . . . . . . . 35
Functional Diagram
• Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA
• Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA
• Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC
• TTL, CMOS Compatible
S
IN
• Analog Signal Range (15V Supplies) . . . . . . . . . . 15V
N
P
• Symmetrical Switch Elements
• Low Operating Power (Typ) . . . . . . . . . . . . . . . . . . . . 1.0mW
D
• Pb-Free Available (RoHS Compliant)
Applications
Pinout
Switch States Shown For A Logic “1” Input
HI-303 (PDIP, CERDIP, SOIC)
TOP VIEW
• Sample and Hold (i.e., Low Leakage Switching)
• Op Amp Gain Switching (i.e., Low On Resistance)
• Portable, Battery Operated Circuits
NC 1
14 V+
S3 2
13 S4
D3 3
12 D4
D1 4
11 D2
S1 5
10 S2
IN1 6
9 IN2
8 V-
GND 7
• Low Level Switching Circuits
• Dual or Single Supply Systems
Ordering Information
PART
NUMBER
HI1-0303-2
LOGIC
SW1, SW2
SW3, SW4
0
OFF
ON
1
ON
OFF
TEMP.
RANGE (oC)
-55 to 125
PACKAGE
PKG. DWG.
#
14 Ld CERDIP
F14.3
HI3-0303-5Z
(See Note)
0 to 75
14 Ld PDIP
(Pb-free)
E14.3
HI9P0303-9Z
(See Note)
-40 to 85
14 Ld SOIC
(Pb-free)
M14.15
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
FN3125 Rev 1.00
Oct 1, 2015
Page 1 of 12
HI-303
Schematic Diagrams
A
V+
MN1B
MN2B
MN3B
MP5B
MP4B
IN
OUT
MN4B
MN6B
MP3B
MP2B
MP1B
V-
A
SWITCH CELL
V+
D2A
MP1A
MP2A
MP3A
MP4A
MP5A
MP6A
MP7A
MP8A
200
A
A
LOGIC
IN
D1A
MN1A
MN2A
MN3A
MN4A
MN5A
GND
V-
MN6A
MN7A
MN8A
SWITCH CELL DRIVER
(ONE PER SWITCH CELL)
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
FN3125 Rev 1.00
Oct 1, 2015
Page 2 of 12
HI-303
Absolute Maximum Ratings
Thermal Information
Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . . 44V (22V)
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V
Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
JA (oC/W)
JC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
80
24
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
120
N/A
Maximum Junction Temperature
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HI-303-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-303-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HI-303-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic “1” = 4V, for Logic “0” = 0.8V.
Unless Otherwise Specified
-2
-5, -9
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Switch ON Time, tON
25
-
210
300
-
210
300
ns
Switch OFF Time, tOFF
25
-
160
250
-
160
250
ns
Break-Before-Make Delay, tOPEN
25
-
60
-
-
60
-
ns
Charge Injection Voltage, V (Note 7)
25
-
3
-
-
3
-
mV
OFF Isolation (Note 6)
25
-
60
-
-
60
-
dB
Input Switch Capacitance, CS(OFF)
25
-
16
-
-
16
-
pF
Output Switch Capacitance, CD(OFF)
25
-
14
-
-
14
-
pF
Output Switch Capacitance, CD(ON)
25
-
35
-
-
35
-
pF
Digital Input Capacitance, CIN
25
-
5
-
-
5
-
pF
Input Low Level, VINL
Full
-
-
0.8
-
-
0.8
V
Input High Level, VINH (Note 10)
Full
4
-
-
4
-
-
V
Input Leakage Current (Low), IINL (Note 5)
Full
-
-
1
-
-
1
A
Input Leakage Current (High), IINH (Note 5)
Full
-
-
1
-
-
1
A
Analog Signal Range
Full
-15
-
+15
-15
-
+15
V
ON Resistance, rON (Note 2)
25
-
35
50
-
35
50
Full
-
40
75
-
40
75
25
-
0.04
1
-
0.04
5
nA
Full
-
1
100
-
0.2
100
nA
25
-
0.04
1
-
0.04
5
nA
Full
-
1
100
-
0.2
100
nA
25
-
0.03
1
-
0.03
5
nA
Full
-
0.5
100
-
0.2
100
nA
PARAMETER
DYNAMIC CHARACTERISTICS
DIGITAL INPUT CHARACTERISTICS
ANALOG SWITCH CHARACTERISTICS
OFF Input Leakage Current, IS(OFF) (Note 3)
OFF Output Leakage Current, ID(OFF) (Note 3)
ON Leakage Current, ID(ON) (Note 4)
FN3125 Rev 1.00
Oct 1, 2015
Page 3 of 12
HI-303
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic “1” = 4V, for Logic “0” = 0.8V.
Unless Otherwise Specified (Continued)
PARAMETER
-2
-5, -9
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
25
-
0.09
0.5
-
0.09
0.5
mA
Full
-
-
1
-
-
1
mA
25
-
0.01
10
-
0.01
100
A
Full
-
-
100
-
-
-
A
25
-
0.01
10
-
0.01
100
A
Full
-
-
100
-
-
-
A
25
-
0.01
10
-
0.01
100
A
Full
-
-
100
-
-
-
A
POWER SUPPLY CHARACTERISTICS
Current, I+ (Note 8)
Current, I- (Note 8)
Current, I+ (Note 9)
Current, I- (Note 9)
NOTES:
2. VS = 10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions.
3. VS = 14V, VD = 14V.
4. VS = VD = 14V.
5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected.
6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K.
7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V.
8. VIN = 4V (one input, all other inputs = 0V).
9. VIN = 0.8V (all inputs).
10. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended.
Test Circuits and Waveforms
15V
VS = +3V
V+
S
LOGIC “1” = SWITCH ON
VO
D
RL
300
CL
33pF
LOGIC
INPUT
0V
SWITCH
OUTPUT
VINH
50%
50%
VS
LOGIC
INPUT
GND
90%
V-15V
SWITCH TYPE
VINH
HI-303
4V
0V
SWITCH
OUTPUT
10%
tOFF
tON
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1A. TEST CIRCUIT
FIGURE 1. SWITCH tON AND tOFF
FN3125 Rev 1.00
Oct 1, 2015
Page 4 of 12
HI-303
+15V
RGEN = 0
VGEN
(Continued)
V+
S
D
RL
10k
IN
CL
10pF
LOGIC INPUT (V)
Test Circuits and Waveforms
6
4
2
0
LOGIC INPUT
VGND
VLOGIC
-15V
0
10
(NOTE 11)
5
VGEN = 10V
0
0
0.4
0.8
1.2
VGEN = 5V
0
1.6
0.4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0
VGEN = 0V
0.8
TIME (s)
1.2
FIGURE 2E. VANALOG = 0V
FN3125 Rev 1.00
Oct 1, 2015
0.8
TIME (s)
1.2
1.6
FIGURE 2D. VANALOG = 5V
5
0.4
1.6
0
FIGURE 2C. VANALOG = 10V
0
1.2
5
TIME (s)
-5
0.8
TIME (s)
FIGURE 2B. TTL LOGIC INPUT
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 2A. TEST CIRCUIT
0.4
1.6
0
-5
VGEN = -5V
0
0.4
0.8
1.2
1.6
TIME (s)
FIGURE 2F. VANALOG = -5V
Page 5 of 12
HI-303
OUTPUT VOLTAGE (V)
Test Circuits and Waveforms
(Continued)
0
-5
-10
VGEN = -10V
0
0.4
0.8
1.2
1.6
TIME (s)
FIGURE 2G. VANALOG = -10V
NOTE:
11. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times.
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
15V
VS1 = +3V
VS2 = +3V
S1
V+
D1
D2
S2
RL2
GND
CL2
RL1
RL1 = RL2 = 300
CL1 = CL2 = 33pF
VINH
0V
OUT 2
LOGIC
INPUT
LOGIC “1” = SWITCH ON
LOGIC
INPUT
OUT 1
CL1
50%
50%
OUT 1
0V
SWITCH
OUTPUTS
V-15V
OUT 2
50%
50%
0V
SWITCH TYPE
VINH
HI-303
5V
tOPEN
tOPEN
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3A. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN)
Typical Performance Curves
80
DRAIN TO SOURCE ON RESISTANCE ()
DRAIN TO SOURCE ON RESISTANCE ()
80
V+ = +15V, V- = -15V
60
125oC
25oC
-55oC
40
20
0
-15
-10
-5
0
5
DRAIN VOLTAGE (V)
FIGURE 4. rDS(ON) vs VD
FN3125 Rev 1.00
Oct 1, 2015
10
15
TA = 25oC
D
60
C
B
40
A
20
A
B
C
D
0
-15
V+ = +15V, V- = -15V
V+ = +10V, V- = -10V
V+ = +7.5V, V- = -7.5V
V+ = +5V, V- = -5V
-10
-5
0
5
10
DRAIN VOLTAGE (V)
FIGURE 5. rDS(ON) vs VD
Page 6 of 12
15
HI-303
Typical Performance Curves
(Continued)
100
100
V+ = +15V, V- = -15V
CLOAD = 30pF, VS = 1VRMS
V+ = +15V, V- = -15V
80
OFF ISOLATION (dB)
POWER DISSIPATION (mW)
TA = 25oC, VS = 15V, RL = 2K
10
1.0
RL = 100
60
RL = 1k
40
20
0.1
1
10
100
1K
10K
100K
0
105
1M
106
108
FIGURE 7. OFF ISOLATION vs FREQUENCY
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING
FREQUENCY (SINGLE LOGIC INPUT)
10.0
10.0
V+ = +15V, V- = -15V
| VD | = | VS | = 14V
V+ = +15V, V- = -15V
1.0
1.0
ID(ON) (nA)
SOURCE OR DRAIN OFF
LEAKAGE CURRENT (nA)
107
FREQUENCY (Hz)
LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
0.1
0.1
0.01
25
0.01
25
75
125
75
125
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 9. ID(ON) vs TEMPERATURE*
FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE*
* The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero
depending on the analog voltage and temperature, and will vary greatly from unit to unit.
16
INPUT CAPACITANCE (pF)
OUTPUT ON CAPACITANCE (pF)
60
50
40
30
20
0
2
4
6
8
10
12
14
16
DRAIN VOLTAGE (V)
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FN3125 Rev 1.00
Oct 1, 2015
12
8
TRANSITION (INDETERMINATE
DUE TO ACTIVE INPUT)
4
0
2
4
6
8
10
12
14
INPUT VOLTAGE (V)
FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT
VOLTAGE
Page 7 of 12
16
HI-303
Typical Performance Curves
(Continued)
300
SWITCHING TIME (ns)
SWITCHING TIME (ns)
V+ = +15V, V- = -15V
VINH = 4.0V, VINL = 0V
tON
200
tOFF
100
-55
-35
-15
5
25
45
65
85
105
300
tON
200
tOFF
100
0
125
TEMPERATURE (oC)
INPUT SWITCHING THRESHOLD (V)
SWITCHING TIME/BREAK-BEFORE-MAKE TIME (s)
1.2
1.0
0.8
0.6
tON
tOFF
tOPEN
ONLY
0.2
0
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 14. SWITCHING TIME AND BREAK-BEFORE-MAKE
TIME vs POSITIVE SUPPLY VOLTAGE
FN3125 Rev 1.00
Oct 1, 2015
15
7
1.4
0.4
10
FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE
V- = -15V, TA = 25oC
VINH = 4.0V, VINL = 0V
1.6
5
NEGATIVE SUPPLY (V)
FIGURE 12. SWITCHING TIME vs TEMPERATURE
1.8
V+ = +15V, TA = 25oC
VINH = 4V, VINL = 0V
V- = -15V, TA = 25oC
6
5
4
3
2
1
0
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 15. INPUT SWITCHING THRESHOLD vs POSITIVE
SUPPLY VOLTAGE
Page 8 of 12
HI-303
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 1, 2015
FN3125.11
CHANGE
- Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD M14.15 to latest revision changes are as follow:
Added land pattern and moved dimensions from table onto drawing.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2002-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3125 Rev 1.00
Oct 1, 2015
Page 9 of 12
HI-303
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
INDEX
AREA
1 2 3
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
B
0.010 (0.25) M
C
L
eA
A1
eC
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
-
5
19.68
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
14
14
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
FN3125 Rev 1.00
Oct 1, 2015
Page 10 of 12
HI-303
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
b
ccc M
C A-B S
D S
eA/2
NOTES
-
0.200
-
5.08
-
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
eA
e
MAX
b
A A
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
c
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
N
14
14
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN3125 Rev 1.00
Oct 1, 2015
Page 11 of 12
HI-303
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN3125 Rev 1.00
Oct 1, 2015
Page 12 of 12
