HI-390
Dual SPDT CMOS Analog Switch
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TERSIL
1-888-IN
The Hl-390 switch is a monolithic device fabricated using
CMOS technology and the Intersil dielectric isolation process.
This device is TTL compatible and features low leakage and
supply currents, low and nearly constant ON resistance over
the analog signal range, break-before-make switching and
low power dissipation.
FN4754
Rev 1.00
August 2002
Features
• Analog Signal Range (15V Supplies) . . . . . . . . . . . 15V
• Low Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40pA
• Low On Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 35
• Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
Ordering Information
PART
NUMBER
HI1-0390-2
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30pC
TEMP. RANGE
(oC)
-55 to 125
PACKAGE
PKG. NO.
16 Ld CERDIP
F16.3
• TTL Compatible
• Symmetrical Switch Elements
• Low Operating Power. . . . . . . . . . . . . . . . . . . . . . . 1.0mW
Pinout
Switch States shown for a Logic “1” Input
Applications
HI-390 (CERDIP)
TOP VIEW
• Sample and Hold (i.e., Low Leakage Switching)
D1 1
16 S1
• Op Amp Gain Switching (i.e., Low On Resistance)
NC 2
15 IN1
• Portable, Battery Operated Circuits
D3 3
14 V-
S3 4
13 GND
S4 5
12 NC
D4 6
11 V+
NC 7
10 IN2
D2 8
9 S2
• Low Level Switching Circuits
• Dual or Single Supply Systems
Functional Diagram
S
IN
LOGIC
SW1, SW2
SW3, SW4
0
OFF
ON
1
ON
OFF
FN4754 Rev 1.00
August 2002
N
P
D
Page 1 of 8
HI-390
Schematic Diagrams
SWITCH CELL
A
V+
MN1B
MN2B
MP5B
MN3B
OUT
MP4B
IN
MN4B
MP3B
MN5B
MP2B
MP1B
V-
A
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
D2A
MP1A
MP2A
MP3A
MP4A
MP5A
MP6A
MP7A
MP8A
200
A
A
LOGIC
IN
D1A
MN1A
MN2A
MN3A
MN4A
MN5A
MN6A
MN7A
MN8A
GND
VSWITCH CELL DRIVER
(ONE PER SWITCH CELL)
FN4754 Rev 1.00
August 2002
Page 2 of 8
HI-390
Absolute Maximum Ratings
Thermal Information
Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . . . . . . . 44V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V
Thermal Resistance (Typical, Note 1)
JA (oC/W)
JC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
75
20
Maximum Junction Temperature
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges
HI-390-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN for Logic “1” = 4V, for Logic “0” = 0.8V,
Unless Otherwise Specified
TEMP (oC)
MIN
TYP
MAX
UNITS
Switch ON Time, tON
25
-
210
300
ns
Switch OFF Time, tOFF
25
-
160
250
ns
Break-Before-Make Delay, tOPEN
25
-
60
-
ns
PARAMETER
TEST CONDITIONS
DYNAMIC CHARACTERISTICS
Charge Injection Voltage, V
(Note 7)
25
-
3
-
mV
OFF Isolation
(Note 6)
25
-
60
-
dB
Input Switch Capacitance, CS(OFF)
25
-
16
-
pF
Output Switch Capacitance, CD(OFF)
25
-
14
-
pF
Output Switch Capacitance, CD(ON)
25
-
35
-
pF
Digital Input Capacitance, CIN
25
-
5
-
pF
Input Low Level, VINL
Full
-
-
0.8
V
Input High Level, VINH
Full
4
-
-
V
DIGITAL INPUT CHARACTERISTICS
Input Leakage Current (Low), IINL
(Note 5)
Full
-
-
1
A
Input Leakage Current (High), IINH
(Note 5)
Full
-
-
1
A
Full
-15
-
+15
V
25
-
35
50
Full
-
40
75
25
-
0.04
1
nA
Full
-
1
100
nA
25
-
0.04
1
nA
Full
-
1
100
nA
25
-
0.03
1
nA
Full
-
0.5
100
nA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
ON Resistance, rON
OFF Input Leakage Current, IS(OFF)
OFF Output Leakage Current, ID(OFF)
ON Input Leakage Current, IS(ON)
FN4754 Rev 1.00
August 2002
(Note 2)
(Note 3)
(Note 3)
(Note 4)
Page 3 of 8
HI-390
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN for Logic “1” = 4V, for Logic “0” = 0.8V,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP (oC)
MIN
TYP
MAX
UNITS
25
-
0.09
0.5
mA
Full
-
-
1
mA
25
-
0.01
10
A
Full
-
-
100
A
25
-
0.01
10
A
Full
-
-
100
A
25
-
0.01
10
A
Full
-
-
100
A
POWER SUPPLY CHARACTERISTICS
Current, I+
(Note 8)
Current, I-
(Note 8)
Current, I+
(Note 9)
Current, I-
(Note 9)
NOTES:
3. VS = 14V, VD =
4. VS = VD = 14V.
2. VS = 10V, IOUT =
10mA. On resistance derived from the voltage measured across the switch under these conditions.
14V.
5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected.
6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K, CL = CFIXTURE + CPROBE, OFF Isolation = 20 Log VS /VD .
7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V.
8. VIN = 4V (one input, all other inputs = 0V).
9. VIN = 0.8V (all inputs).
Test Circuits and Waveforms
15V
6
RGEN = 0
VGEN
S
D
RL
10k
IN
4
2
0
LOGIC INPUT
V-
GND
VLOGIC
CL
10pF
LOGIC INPUT (V)
V+
0
-15V
10
(NOTE 10)
5
VGEN = 10V
0
0
0.4
0.8
TIME (s)
1.2
FIGURE 1C. VANALOG = 10V
FN4754 Rev 1.00
August 2002
0.8
TIME (s)
1.2
1.6
FIGURE 1B. LOGIC INPUT
1.6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 1A. TEST CIRCUIT
0.4
5
0
VGEN = 5V
0
0.4
0.8
TIME (s)
1.2
1.6
FIGURE 1D. VANALOG = 5V
Page 4 of 8
HI-390
(Continued)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Test Circuits and Waveforms
5
0
VGEN = 0V
-5
0
0.4
0.8
TIME (s)
1.2
0
-5
0
1.6
FIGURE 1E. VANALOG = 0V
OUTPUT VOLTAGE (V)
VGEN = -5V
0.4
0.8
TIME (s)
1.2
1.6
FIGURE 1F. VANALOG = -5V
0
-5
-10
VGEN = -10V
0
0.4
0.8
TIME (s)
1.2
1.6
FIGURE 1G. VANALOG = -10V
NOTE:
10. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times.
FIGURE 1. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
Typical Performance Curves
80
80
60
rDS(ON) ()
rDS(ON) ()
60
125oC
25oC
-55oC
40
20
0
-15
D
TA = 25oC
V+ = +15V, V- = -15V
-10
-5
0
5
DRAIN VOLTAGE (V)
FIGURE 2. rDS(ON) vs VD
FN4754 Rev 1.00
August 2002
10
15
C
B
40
A
20 A
B
C
D
0
-15
V+ = +15V, V- = -15V
V+ = +10V, V- = -10V
V+ = +7.5V, V- = -7.5V
V+ = +5V, V- = -5V
-10
-5
0
5
10
DRAIN VOLTAGE (V)
FIGURE 3. rDS(ON) vs VD
Page 5 of 8
15
HI-390
Typical Performance Curves
100
V+ = +15V, V- = -15V
TA = 25oC, VS = 15V, RL = 2K
V+ = +15V, V- = -15V
CLOAD = 30pF, VS = 1VRMS
80
OFF ISOLATION (dB)
POWER DISSIPATION (mW)
100
(Continued)
10
1.0
RL = 100
60
RL = 1k
40
20
0.1
1
10
100
1K
10K
100K
0
105
1M
106
107
108
FREQUENCY (Hz)
LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
FIGURE 4. DEVICE POWER DISSIPATION vs SWITCHING
FREQUENCY (SINGLE LOGIC INPUT)
FIGURE 5. OFF ISOLATION vs FREQUENCY
10.0
10.0
V+ = +15V, V- = -15V
| VD | = | VS | = 14V
IS(OFF) OR ID(OFF) (nA)
V+ = +15V, V- = -15V
1.0
ID(ON) (nA)
1.0
0.1
0.1
0.01
25
0.01
25
75
125
TEMPERATURE (oC)
75
125
TEMPERATURE (oC)
FIGURE 6. IS(OFF) OR ID(OFF) vs TEMPERATURE (NOTE 11)
FIGURE 7. ID(ON) vs TEMPERATURE (NOTE 11)
NOTE:
60
16
50
12
CIN (pF)
CD(ON) (pF)
11. The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or
zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.
40
30
20
8
TRANSITION (INDETERMINATE
DUE TO ACTIVE INPUT)
4
0
2
4
6
8
10
DRAIN VOLTAGE (V)
12
14
16
FIGURE 8. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FN4754 Rev 1.00
August 2002
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
FIGURE 9. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE
Page 6 of 8
HI-390
Typical Performance Curves
(Continued)
300
V+ = +15V, V- = -15V
VINH = 4.0V, VINL = 0V
200
tON , tOFF (ns)
tON , tOFF (ns)
tON
tOFF
100
300
tON
200
tOFF
V+ = +15V, TA = 25oC
VINH = 4V, VINL = 0V
100
0
-55
-35
-15
5
25
45
65
TEMPERATURE (oC)
85
105
125
FIGURE 10. SWITCHING TIME vs TEMPERATURE
0
7
INPUT SWITCHING THRESHOLD (V)
V- = -15V, TA = 25oC
VINH = 4.0V, VINL = 0V
1.6
1.4
tON, tOFF (s)
15
FIGURE 11. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE
1.8
1.2
1.0
0.8
0.6
tON
0.4
tOFF
0.2
0
5
10
NEGATIVE SUPPLY (V)
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 12. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE
FN4754 Rev 1.00
August 2002
V- = -15V, TA = 25oC
6
5
4
3
2
1
0
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 13. INPUT SWITCHING THRESHOLD vs POSITIVE
SUPPLY VOLTAGE
Page 7 of 8
HI-390
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
(c)
E
M
-Bbbb S
C A-B S
Q
-C-
SEATING
PLANE
S1
b2
ccc M C A - B S
eA/2
-
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
c
aaa M C A - B S D S
D S
NOTES
0.014
eA
e
b
MAX
b
A A
MIN
A
A
L
MILLIMETERS
MAX
M
(b)
D
BASE
PLANE
MIN
b1
SECTION A-A
D S
INCHES
SYMBOL
NOTES:
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
© Copyright Intersil Americas LLC 2002. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4754 Rev 1.00
August 2002
Page 8 of 8
