HI1171JCB

HI1171 8-Bit, 40 MSPS, High Speed D/A Converter Pb R and -Free oH S Co DATASHEET a nt m pl i FN3662 Rev.3.00 October 26, 2005 Features Description • • • • • • • • The HI1171 is an 8-bit, 40MHz, high speed D/A converter. The converter incorporates an 8-bit input data register with blanking capability, and current outputs. The HI1171 features low glitch outputs. The architecture is a current cell arrangement to provide low linearity errors. The HI1171 is available in an Industrial temperature range and is offered in a 24 lead (200 mil) SOIC plastic package. For dual version, please refer to the HI1177 Data Sheet. For triple version, please refer to the HI1178 Data Sheet. Throughput Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-Bit Integral Linearity Error . . . . . . . . . . . . . . . . . . . 0.25 LSB Low Glitch Noise Single Supply Operation . . . . . . . . . . . . . . . . . . . . . +5V Low Power Consumption (Max) . . . . . . . . . . . . . 80mW Evaluation Board Available (HI1171-EV) Direct Replacement for the Sony CXD1171 Applications • • • • • • • Wireless Telecommunications Signal Reconstruction Direct Digital Synthesis Imaging Presentation and Broadcast Video Graphics Displays Signal Generators Pinout Ordering Information PART NUMBER TEMP. RANGE (oC) HI1171JCB -40 to 85 HI1171-EV 25 PACKAGE 24 Ld SOIC PKG. NO. M24.2-S Evaluation Board Typical Application Circuit HI1171 (SOIC) TOP VIEW +5V +5V HI1171 0.1F 1 24 DVDD D1 2 23 DVDD D7 D7 (MSB)(8) D2 3 22 AVDD D6 D6 (7) D3 4 21 IOUT2 D5 D5 (6) D4 5 20 IOUT1 D4 D4 (5) 19 AVDD D3 D3 (4) D2 D2 (3) D1 D1 (2) D0 D0 (LSB) (1) D5 6 D6 7 18 AVDD D7 8 17 VG BLNK 9 16 VREF DVSS 10 15 IREF VB 11 14 AVSS CLK 12 13 DVSS FN3662 Rev.3.00 October 26, 2005 0.1F DVDD (23, 24) (18, 19, 22) AVDD (LSB) D0 CLK (12) 0.1F VB (11) BLNK (9) DVSS (10, 13) (17) VG (16) VREF 0.1F 1k (20) IOUT1 D/A OUT 200 (15) IREF 3.3k (21) IOUT2 (14) AVSS Page 1 of 7 HI1171 Functional Block Diagram (LSB) D0 D1 D2 D3 DECODER 8-BIT LATCH D4 D5 D6 6 MSBs CURRENT CELLS IOUT2 2 LSBs CURRENT CELLS IOUT1 VG DECODER - (MSB) D7 CURRENT CELLS (FOR FULL SCALE) + VREF IREF BLNK BIAS VOLTAGE GENERATOR VB CLK FN3662 Rev.3.00 October 26, 2005 CLOCK GENERATOR Page 2 of 7 HI1171 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . +7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . +7.0V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 15mA Thermal Resistance (Typical, Note 1) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 8 - Bits -0.5 - 1.3 LSB SYSTEM PERFORMANCE Resolution, n Integral Linearity Error, INL fS = 40MHz (End Point) Differential Linearity Error, DNL fS = 40MHz - - 0.25 LSB Offset Error, VOS (Note 2) - - 1 mV Full Scale Error, FSE (Adjustable to Zero) (Note 2) - - 13 LSB Full Scale Output Current, IFS - 10 15 mA Full Scale Output Voltage, VFS 1.9 2.0 2.1 V Output Voltage Range, VFSR 0.5 2.0 2.1 V DYNAMIC CHARACTERISTICS Throughput Rate See Figure 7 40.0 - - MHz Glitch Energy, GE ROUT = 75 - 30 - pV-s Differential Gain, AV (Note 3) - 1.2 - % Differential Phase,  (Note 3) - 0.5 - Degree 0.5 - 2.0 V (Note 3) 1.0 - - M Input Logic High Voltage, VIH (Note 3) 3.0 - - V Input Logic Low Voltage, VIL (Note 3) - - 1.5 V Input Logic Current, IIL, IIH (Note 3) - - 5.0 A Digital Input Capacitance, CIN (Note 3) - 5.0 - pF Data Setup Time, tSU See Figure 1 5 - - ns Data Hold Time, tHLD See Figure 1 10 - - ns REFERENCE INPUT Voltage Reference Input Range Reference Input Resistance DIGITAL INPUTS TIMING CHARACTERISTICS FN3662 Rev.3.00 October 26, 2005 Page 3 of 7 HI1171 Electrical Specifications AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz, CLK Pulse Width = 12.5ns, TA = 25oC (Note 4) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Propagation Delay Time, tPD See Figure 9 - 10 - ns Settling Time, tSET (to 1/2 LSB) See Figure 1 - 10 15 ns CLK Pulse Width, tPW1, tPW2 See Figure 1 12.5 - - ns POWER SUPPLY CHARACTERISITICS IAVDD 14.3MHz, at Color Bar Data Input - 10.9 11.5 mA IDVDD 14.3MHz, at Color Bar Data Input - 4.2 4.8 mA Power Dissipation 200 load at 2VP-P Output - - 80 mW NOTES: 2. Excludes error due to external reference drift. 3. Parameter guaranteed by design or characterization and not production tested. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram tPW1 tPW2 CLK tSU tSU tSU tHLD tHLD tHLD DATA tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. FN3662 Rev.3.00 October 26, 2005 Page 4 of 7 HI1171 200 2 GLITCH ENERGY (pV/s) OUTPUT FULL SCALE VOLTAGE (V) Typical Performance Curves 1 100 VDD = 5.0V, R = 200 16R = 3.3k, TA = 25oC 1 REFERENCE VOLTAGE (V) 2 100 OUTPUT RESISTANCE () OUTPUT FULL SCALE VOLTAGE (V) FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE 200 FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY 2.0 1.9 VDD = 5.0V, VREF = 2.0V R = 20016R = 3.3k TA = 25oC 0 -25 0 25 50 75 AMBIENT TEMPERATURE (oC) FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE Pin Descriptions 24 PIN SOIC PIN NAME 1-8 D0(LSB) thru D7(MSB) 9 BLNK 10, 13 DVSS 11 VB PIN DESCRIPTION Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit. Blanking Line, used to clear the internal data register to the zero condition when High, normal operation when Low. Digital Ground. Voltage Bias, connect a 0.1F capacitor to DVSS . 12 CLK Data Clock Pin 100kHz to 40MHz. 14 AVSS Analog Ground. 15 IREF Current Reference, used to set the current range. Connect a resistor to AVSS that is 16 times greater than the resistor on IOUT1 . (See Typical Applications Circuit). 16 VREF 17 VG Input Reference Voltage used to set the output full scale range. Voltage Ground, connect a 0.1F capacitor to AVDD . 18, 19, 22 AVDD Analog Supply 4.75V to 7V. 20 IOUT1 Current Output Pin. FN3662 Rev.3.00 October 26, 2005 Page 5 of 7 HI1171 Pin Descriptions 24 PIN SOIC (Continued) PIN NAME PIN DESCRIPTION 21 IOUT2 Current Output pin used for a virtual ground connection. Usually connected to AVSS. 23, 24 DVDD Digital Supply 4.75V to 7V. Detailed Description The HI1171 is an 8-bit, current out D/A converter. The DAC can convert at 40MHz and run on a single +5V supply. The architecture is an encoded, switched current cell arrangement. As the values of both ROUT and RREF increase, power consumption is decreased, but glitch energy and output settling time is increased. Voltage Output Mode Clock Phase Relationship The output current of the HI1171 can be converted into a voltage by connecting an external resistor to IOUT1 . To calculate the output resistor use the following equation: The internal latch is closed when the clock line is high. The latch can be cleared by the BLNK line. When BLNK is set (HIGH) the contents of the internal data latch will be cleared. When BLNK is low data is updated by the CLK. ROUT = VFS /IFS , where VFS can range from +0.5V to +2.0V and IFS can range from 0mA to 15mA. In setting the output current the IREF pin should have a resistor connected to it that is 16 times greater than the output resistor: RREF = 16 x ROUT Noise Reduction To reduce power supply noise separate analog and digital power supplies should be used with 0.1F ceramic capacitors placed as close to the body of the HI1171 as possible. The analog (AVSS) and digital (DVSS) ground returns should be connected together back at the power supply to ensure proper operation from power up. Test Circuits (LSB) D0 1 8-BIT COUNTER WITH LATCH 2 20 VG D7 BLK 8 9 VB CLK AVDD 200 0.1F 16 11 15 12 OSCILLOSCOPE 17 0.1F CLK 40MHz SQUARE WAVE IO VREF 1k 2V IREF AVSS 3.3k FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT © Copyright Intersil Americas LLC 1997-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3662 Rev.3.00 October 26, 2005 Page 6 of 7 HI1171 Test Circuits (Continued) (LSB) D0 1 20 2 CONTROLLER DVM AVDD VG D7 0.1F 9 16 0.1F VREF 1k 2V 11 VB 200 17 8 BLK CLK 40MHz SQUARE WAVE IO IREF 15 AVSS 12 CLK 3.3k FIGURE 6. DC CHARACTERISTICS TEST CIRCUIT (LSB) D0 1 20 2 IO OSCILLOSCOPE AVDD VG D7 FREQUENCY DEMULTIPLIER 8 BLK 200 0.1F 9 16 0.1F 11 VB CLK 10MHz SQUARE WAVE 17 15 VREF 1k 2V IREF AVSS 12 CLK 3.3k FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT (LSB) D0 1 8-BIT COUNTER WITH LATCH 2 BLK CLK 1MHz SQUARE WAVE 8 9 CLK AVDD 17 OSCILLOSCOPE 75 0.1F 16 0.1F VB DELAY CONTROLLER IO VG D7 DELAY CONTROLLER 20 11 15 VREF 2V IREF 1k AVSS 12 1.2k FIGURE 8. SET UP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT FN3662 Rev.3.00 October 26, 2005 Page 7 of 7