HI3026
®
8-Bit, 120 MSPS, Flash A/D Converter
August 1997
Features
Description
• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB
• RGB Graphics Processing (LCD, PDP)
The HI3026 is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of
use. With a 120 MSPS encode rate capability and full-power
analog bandwidth of 150MHz, this component is ideal for applications requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3026’s clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with singleended inputs. The user may select 16-bit demultiplexed output
or 8-bit single channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at 1/2 the clock
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D converter to be clocked to the full 120 MSPS conversion rate.
Fabricated with an advanced Bipolar process, the HI3026 is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20°C to 75°C
temperature range. For a faster clock rate, please refer to
the HI3026A (140 MSPS).
• Digital Oscilloscopes
Ordering Information
• Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Integral Linearity Compensation Circuit
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . 21pF
• Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz
• Low Power Consumption . . . . . . . . . . . . . . . . . . 760mW
• Internal 1/2 Frequency Divider Circuit (w/Reset Function)
• CLK/2 Clock Output
• Compatible with ECL, PECL and TTL Digital Input Levels
• 1:2 Demultiplexed Output Pin
• Surface Mounting Package
• Direct Replacement for Sony CXA3026Q
Applications
• Digital Communications (QPSK, QAM)
PART
NUMBER
• Magnetic Recording (PRML)
TEMP. RANGE
(°C)
HI3026JCQ
-20 to 75
HI3026EVAL
25
PACKAGE
PKG. NO.
48 Ld MQFP
Q48.12x12-S
Evaluation Board
Pinout
P1D4
P1D7
P1D6
P1D5
DVCC2
DGND2
CLKOUT
RESETN/T
SELECT
INV
RESETN/E
RESET/E
HI3026 (MQFP)
TOP VIEW
DVEE3
1
48 47 46 45 44 43 42 41 40 39 38 37
36
VRB
2
3
35
34
P1D2
4
33
32
31
P1D0
DGND2
DVCC2
30
29
DVCC1
AVCC
VIN
VRM2
5
AVCC
8
9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
P1D1
DGND1
P2D7
P2D6
P2D5
P2D4
P2D3
P2D2
P2D0
P2D1
NC
DVCC2
DGND2
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
CLK/E
DGND3
10
NC
VRT
28
27
CLK/T
NC
VRM3
AGND
6
7
CLKN/E
AGND
VRM1
P1D3
File Number
4109.3
HI3026
Block Diagram
AVCC
5
8
INV
DVCC1
44
30
DVCC2
DGND3
19 31 42
12
VRT 11
R1
R/2
R
(MSB)
40 P1D7
1
R
39 P1D6
2
6 BITS
38 P1D5
9
8 BITS
R
64
R
37 P1D4
TTLOUT
63
VRM3
LATCHA
R
36 P1D3
35 P1D2
65
6 BITS
34 P1D1
6-BIT LATCH AND ENCODER
R
126
VRM2
7
VIN
6
127
R
128
ENCODER
R
R
129
33 P1D0
(LSB)
8 BITS
(MSB)
28 P2D7
6 BITS
R
27 P2D6
191
4
R
26 P2D5
192
193
R
TTLOUT
R
LATCHB
VRM1
25 P2D4
24 P2D3
6 BITS
23 P2D2
254
R
22 P2D1
255
R/2
VRB
2
CLK/T
15
CLK/E
13
CLKN/E
14
21 P1D0
(LSB)
R/2
DELAY
17
46
RESETN/E
48
RESET/E
47
NC
18
D
RESETN/T
16
Q
3
43 CLKOUT
SELECT
Q
10
45
AGND
29
SELECT DGND1
2
20 32
41
DGND2
1
DVEE3
HI3026
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage (AVCC , DVCC1, DVCC2) . . . . . . . . . . -0.5V to 7.0V
(DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
(DVEE3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V
(DGND3 - DVEE3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . .VRT - 2.7V to AVCC
Reference Input Voltage (VRT). . . . . . . . . . . . . . . . . . .2.7V to AVCC
(VRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AVCC
(|VRT - VRB|). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V
Digital Input Voltage
ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DVEE3 to 0.5V
PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3
TTL (***/T, INV). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1
Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DVCC1
VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
Recommended Operating Conditions
WITH DUAL POWER SUPPLIES
MIN
TYP
MAX
Supply Voltage
DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05
0
+0.05V
DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05
0
+0.05V
DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5
-5.0 -4.75V
Analog Input Voltage (VIN) . . . . . . . . . . . . . VRB
VRT
Reference Input Voltage
VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9
+4.1V
VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4
+2.6V
|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . 1.5
2.1V
Digital Input Voltage
ECL (***/E) VIH . . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V
ECL (***/E) VIL . . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V
TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V
TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . .
0.8V
Other (SELECT) VIH . . . . . . . . . . . . . . . .
DVCC1
Other (SELECT) VIL . . . . . . . . . . . . . . . .
DGND1
VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4
0.8
Max Conversion Rate (fC , Straight Mode) . . . 100
MSPS
Max Conversion Rate (fC , DMUX Mode). . . . 120
MSPS
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC
WITH A SINGLE POWER SUPPLY
MIN
TYP
MAX
Supply Voltage
DVCC1 , DVCC2 , AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05
0
+0.05V
DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DVEE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05
0
+0.05V
Analog Input Voltage (VIN) . . . . . . . . . . . . . . VRB
VRT
Reference Input Voltage
VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9
+4.1V
VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4
+2.6V
|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . 1.5
2.1V
Digital Input Voltage
PECL (***/E) VIH . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V
PECL (***/E) VIL . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V
TTL (***/T, INV) VIH . . . . . . . . . . . . . . . . . 2.0V
TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . . 0.8V
Other (SELECT) VIH . . . . . . . . . . . . . . . . . DVCC1
Other (SELECT) VIL . . . . . . . . . . . . . . . . . DGND1
VID (Note 3) (|***/E- ***N/E|). . . . . . . . . . . 0.4
0.8
Max Conversion Rate (fC , Straight Mode) . . . 100
MSPS
Max Conversion Rate (fC , DMUX Mode) . . . . 120
MSPS
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. ***/E and ***T indicate CLK/E and CLK/T, etc., for the pin name.
3. VID : Input Voltage Differential.
Electrical Specifications
PARAMETER
DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V,
TA = 25oC
TEST CONDITIONS
Resolution
MIN
TYP
MAX
UNITS
-
8
-
Bits
-
-
±0.5
LSB
-
-
±0.5
LSB
DC CHARACTERISTICS
Integral Linearity Error, EIL
VIN = 2VP-P , fC = 5 MSPS
Differential Linearity Error, EDL
ANALOG INPUT
-
21
-
pF
Analog Input Resistance, RIN
4
-
50
kΩ
Analog Input Current, IIN
0
-
500
μA
Analog Input Capacitance, CIN
VIN = +3.0V +0.07VRMS
3
HI3026
Electrical Specifications
DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V,
TA = 25oC (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Resistance (Note 4), RREF
75
115
155
Ω
Reference Current (Note 5), IREF
REFERENCE INPUT
9.7
17.4
28
mA
Offset Voltage VRT Side, EOT
2
-
15
mV
Offset Voltage VRB Side, EOB
2
-
10
mV
DIGITAL INPUT (ECL, PECL)
Digital Input Voltage: High, VIH
DGND3 - 1.05
-
DGND3 - 0.5
V
Digital Input Voltage: Low, VIL
DGND3 - 3.2
-
DGND3 -1.4
V
-
DGND3 - 1.2
-
V
Threshold Voltage, VTH
Digital Input Current: High, IIH
VIH = DGND3 - 0.8V
-50
-
+50
μA
Digital Input Current: Low, IIL
VIL = DGND3 - 1.6V
-75
-
0
μA
-
-
5
pF
Digital Input Voltage: High, VIH
2.0
-
-
V
Digital Input Voltage: Low, VIL
-
-
0.8
V
Threshold Voltage, VTH
-
1.5
-
V
Digital Input Capacitance
DIGITAL INPUT (TTL)
Digital Input Current: High, IIH
VIH = 3.5V
-50
-
0
μA
Digital Input Current: Low, IIL
VIL = 0.2V
-500
-
0
μA
-
-
5
pF
Digital Input Capacitance
DIGITAL OUTPUT (TTL)
Digital Output Voltage: High, VOH
IOH = -2mA
2.4
-
-
V
Digital Output Voltage: Low, VOL
IOL = 1mA
-
-
0.5
V
120
-
-
MSPS
Aperture Jitter, tAJ
-
10
-
ps
Sampling Delay, tDS
3
4.5
6
ns
SWITCHING CHARACTERISTICS
Maximum Conversion Rate, fC
DMUX Mode
Clock High Pulse Width, tPW1
CLK
3.2
-
-
ns
Clock Low Pulse Width, tPW0
CLK
3.2
-
-
ns
Reset Pulse Width, tPWR (Note 6)
RESETN
tx2
-
-
ns
RESET Signal Setup Time, tRS
RESETN-CLK
3.5
-
-
ns
RESET Signal Hold Time, tRH
RESETN-CLK
CLKOUT Output Delay, tDCLK
(CL = 5pF)
Data Output Delay (Note 6), tDO1
tDO2
DEMUX Mode (CL = 5pF)
Output Rise Time, tr
Output Fall Time, tf
0
-
-
ns
3.5
7
9
ns
t
t+1
t+2
ns
(CL = 5pF)
4.5
8
10
ns
0.8 to 2.0V
(CL = 5pF)
-
2
-
ns
0.8 to 2.0V
(CL = 5pF)
-
2
-
ns
150
-
-
MHz
DYNAMIC CHARACTERISTICS
Input Bandwidth
VIN = 2VP-P , -3dB
S/N Ratio
fC = 120 MSPS, fIN = 1kHz Full Scale,
DMUX Mode
-
46
-
dB
fC = 120 MSPS, fIN = 29.999MHz Full Scale,
DMUX Mode
-
40
-
dB
4
HI3026
Electrical Specifications
DVCC1 , 2 , AVCC , DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V,
TA = 25oC (Continued)
PARAMETER
TEST CONDITIONS
Error Rate (Note 7)
MIN
TYP
MAX
UNITS
fC = 120 MSPS, fIN = 1kHz Full Scale,
DMUX Mode, Error > 16 LSB
-
-
10-12
TPS
fC = 120 MSPS, fIN = 29.999MHz
Full Scale, DMUX Mode, Error > 16 LSB
-
-
10-9
TPS
fC = 100 MSPS, fIN = 24.999MHz
Full Scale, Straight Mode, Error > 16 LSB
-
-
10-9
TPS
POWER SUPPLY
Supply Current, ICC
125
145
185
mA
Supply Current, IEE
0.4
0.6
0.8
mA
Power Consumption (Note 8), PD
660
760
960
mW
NOTES:
4. RREF: Resistance value between VRT and VRB .
V RT – V RB
5. I REF = ---------------------------R REF .
1
6. T = ----- .
fC
7. The unit of measure TPS: Times Per Sample.
( V RT – V RB ) 2
-.
8. P D = ( I CC + I EE ) • V CC + -----------------------------------V
REF
Timing Diagrams
N-1
VIN
N+2
N+3
tDS
N
t
N+1
CLK
tPW1
tD02
tPW0
P1D0 TO D7
N-2
P2D0 TO D7
N-3
2V
N
N+2
N-1
N-1
0.8V
2V
0.8V
tD01
tDCLK
t + 1ns
CLK OUT
2V
2V
0.8V
0.8V
RESET PULSE
tPWR
FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC)
5
HI3026
Timing Diagrams
N+2
N-1
VIN
N+3
N+1
tDS
N
t
CLK
tPW1
tPW0
P1D0 TO D7
N-4
2.0V
0.8V
N-3
N-2
N-1
N
P2D0 TO D7
N-5
2.0V
0.8V
N-4
N-3
N-2
N-1
tD02
8ns
2.0V
CLK OUT
(CLK IS INVERTED AND OUTPUT)
0.8V
tDCLK
RESET PULSE
FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)
DGND3
VIH (MAX)
VIL
VTH (DGND3 - 1.2V)
VID
VIH
VIL (MIN)
FIGURE 3. ECL AND PECL SWITCHING LEVEL
Pin Descriptions
I/O
TYPICAL
VOLTAGE LEVEL
PIN NO
SYMBOL
3, 10
AGND
GND
EQUIVALENT CIRCUIT
Analog Ground. Separated from the
digital ground.
5, 8
AVCC
+5V (Typ)
Analog Power Supply. Separated from
the digital power supply.
20, 29
32, 41
DGND1
DGND2
GND
Digital Ground.
19, 30
31, 42
DVCC1
DVCC2
+5V (Typ)
Digital Power Supply.
12
DGND3
+5V (Typ) (With a
Single Power Supply)
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
GND (With Dual
Power Supplies)
6
DESCRIPTION
HI3026
Pin Descriptions (Continued)
PIN NO
SYMBOL
1
DVEE3
I/O
TYPICAL
VOLTAGE LEVEL
EQUIVALENT CIRCUIT
GND (With a Single
Power Supply)
DESCRIPTION
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
+5V (Typ) (With Dual
Power Supplies)
16, 17,
18
NC
No Connect pin. Not connected with
the internal circuits.
13
CLK/E
I
14
CLK/NE
I
ECL/PECL
Clock Input.
DGND3
R
R
13 48
14 47
I
47
RESET/E
I
Reset Input. When the input is set to low
level, the built-in CLK frequency divider
circuit can be reset.
1.2V
R
RESETN/E
R
48
DVEE3
15
CLK/T
I
46
RESETN/T
I
CLK/E Complementary Input. When left
open, this pin goes to the threshold
potential. Only CLK/E can be used for
operation, but complementary input is
recommended to attain fast and stable
operation.
TTL
RESETN/E Complementary Input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
Clock input.
DVCC1
R/2
15 46
R
Reset Input. When left open, this input
goes to high level. When the input is
set to low level, the built-in CLK
frequency divider circuit can be reset.
1.5V
DGND1
DVEE3
44
INV
I
TTL
Data Output Polarity Inversion Input.
When left open, this input goes to high
level. (See Table 1; I/O Correspondence
Table).
DVCC1
44
DGND1
DVEE3
45
SELECT
VCC or Ground
Data Output Mode Selection. (See
Table 2; Operating Mode Table).
DVCC1
45
DGND1
DVEE3
7
HI3026
Pin Descriptions (Continued)
PIN NO
SYMBOL
I/O
11
VRT
I
TYPICAL
VOLTAGE LEVEL
EQUIVALENT CIRCUIT
4.0V (Typ)
11
9
7
4
2
VRM3
VRB +
2
--- (VRT - VRB)
4
VRM1
VRB
VRB +
1
--- (VRT - VRB)
4
I
2.0V (Typ)
Top Reference Voltage. Bypass to
AGND with a 1μF tantal capacitor and
a 0.1μF chip capacitor.
R1
R/2
VRB +
3
--- (VRT - VRB)
4
VRM2
DESCRIPTION
Reference Voltage Mid Point. Bypass
to AGND with a 0.1μF chip capacitor.
R
COMPARATOR 1
R
COMPARATOR 63
9
R
7
R
Reference Voltage Mid Point. Bypass
to AGND with a 0.1μF chip capacitor.
COMPARATOR 64
COMPARATOR 127
Reference Voltage Mid Point. Bypass
to AGND with a 0.1μF chip capacitor.
COMPARATOR 128
COMPARATOR 191
4
R
COMPARATOR 192
Bottom Reference Voltage. Bypass to
AGND with a 1μF tantal capacitor and
a 0.1μF chip capacitor.
R
COMPARATOR 255
R/2
2
R2
6
VIN
I
VRT to VRB
Analog Input.
COMPARATOR
AVCC
AVCC
VREF
6
AGND
DVEE3
33 to 40
P1D0 to
P1D7
O
21 to 28
P2D0 to
P2D7
O
CLKOUT
O
Port 1 Side Data Output.
Port 2 Side Data Output.
DVCC1
DVCC2
21 TO 28
33 TO 40
100K
43
TTL
DGND1
43
DGND2
DVEE3
8
Clock Output. (See Table 2; Operating
Mode Table).
HI3026
- To prevent interference between AGND and DGND and
between AVCC and DVCC , make sure the respective patterns are separated. To prevent a DC offset in the power
supply pattern, connect the AVCC and DVCC lines at one
point each, via a ferrite-bead filter. Shorting the AGND
and DGND patterns in one place immediately under the
A/D converter improves A/D converter performance.
- Ground the power supply pins (AVCC , DVCC1 , DVCC2 ,
DVEE3) as close to each pin as possible with a 0.1μF or
larger ceramic chip capacitor. (Connect the AVCC pin to
the AGND pattern and the DVCC1 , DVCC2 , DVEE3 pins
to the DGND pattern).
- The digital output wiring should be as short as possible.
If the digital output wiring is long, the wiring capacitance
will increase, deteriorating the output slew rate and
resulting in reflection to the output waveform since the
original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of
approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or
parasitic inductance by using a large capacity drive circuit;
keeping wiring as short as possible, and using chip parts
for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate bypass to protect them from high-frequency noise. Bypass them to
AGND with approximately 1μF tantal capacitor and, 0.1μF
capacitor. At this time, approximately DGND3 - 1.2V
voltage is generated. However, this is not recommended for
use as threshold voltage VBB as it is too weak.
When the digital input level is ECL or PECL level, ***/E pins
should be used and ***/T pins left open. When the digital
input level is TTL, ***/T pins should be used and III/E pins
left open.
TABLE 1. A/D CODE TABLE
INV
1
0
VIN
STEP
VRT
255
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
254
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
D7
D0
128
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
127
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
•
•
•
•
•
•
•
•
•
VRB
D0
•
•
•
•
•
•
•
•
•
VRM2
D7
1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Notes on Operation
• The HI3026 is a high-speed A/D converter which is capable
of TTL, ECL and PECL level clock input. Characteristic
impedance should be properly matched to ensure optimum
performance during high-speed operation.
• The power supply and grounding have a profound influence
on converter performance. The power supply and grounding method are particularly important during high-speed
operation. General points for caution are as follows:
- The ground pattern should be as large as possible. It is
recommended to make the power supply and ground
patterns wider at an inner layer using a multi-layer
board.
Test Circuits
+V
4V
1.95V
VRT
5V
5V
A ICC
A
AVCC
DVCC1
DVCC2
VIN
S2
-
IEE
VRB
-V
CLK/E
DGND2
DGND1
AGND
S1: ON WHEN A < B
S2: ON WHEN A > B
DGND3
AB
COMPARATOR
5MHz PECL
VIN
2V
S1
+
DVEE3
HI3026
8
“0”
A8
TO
A1
B8
TO
B1
A0
B0
DVM
CONTROLLER
FIGURE 4. CURRENT CONSUMPTION MEASUREMENT
CIRCUIT
8
BUFFER
“1”
000...00
TO
111..10
FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL
LINEARITY ERROR MEASUREMENT CIRCUIT
9
HI3026
Test Circuits
(Continued)
VIN
SIGNAL
SOURCE
8
HI3026
A
LATCH
COMPARATOR
A>B
PULSE
COUNTER
B
fC
4
CLK
-1kHz
CLK
+
LATCH
2VP-P SINE WAVE
16 LSB
SIGNAL
SOURCE
1/
8
fC
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
VRT
VRM2
VIN
100MHz
VRB
AMP
CLK
OSC1
φ: VARIABLE
fR
VIN
8
HI3026
Δυ
129
Δt
128
127
VIN
LOGIC
ALALYZER
σ
(LSB)
126
125
CLK
1024
SAMPLES
CLK
OSC2
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
NOTE: Where σ (LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter tAJ is:
Δυ
256
t AJ = ⎛ σ / -------⎞ = σ/ ⎛ ---------- x 2πf⎞ .
⎝
⎝ 2
⎠
Δt ⎠
ECL
BUFFER
100MHz
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Operating Modes
The HI3026 has two types of operating modes which are selected with Pin 45 (SELECT).
TABLE 2. OPERATING MODE TABLE
OPERATING
MODE
SELECT
MAXIMUM
CONVERSION RATE
DMUX Mode
VCC
120 MSPS
Demultiplexed Output
60 MBPS
The input clock is 1/2 frequency
divided and output at 60MHz.
Straight Mode
GND
100 MSPS
Straight Output 100 MBPS
The input clock is inverted and
output at 100MHz.
DATA OUTPUT
CLOCK OUTPUT
termeasure, the HI3026 is equipped with a function which
resets the 1/2 frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at fC (Min) = 120 MSPS in this mode.
DMUX Mode (See Application Circuits, Figures 18, 19, 20)
Set the SELECT pin to VCC for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided
clock. The 1/2 frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.
Straight Mode (See Application Circuits, Figures 21, 22, 23)
When using multiple HI3026 units in parallel in this mode, differences in the start timing of the 1/2 frequency divided clock
may cause operation as shown in the figure below. As a coun-
10
HI3026
block must be set to match the logic input (CLK and RESET
signals) level.
Set the SELECT pin to GND for this mode. In this mode, data
output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.
TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS
The A/D converter can operate at fC (Min) = 100 MSPS in
this mode.
Digital Input Level and Supply Voltage Settings
The logic input level for the HI3026 supports ECL, PECL and
TTL levels.
DIGITAL
INPUT
LEVEL
DVEE3
DGND3
ECL
-5V
0V
±5V
Figures 18, 21
0V
+5V
+5V
Figures 19, 22
TTL
0V
+5V
+5V
Figures 20, 23
CLK
HI3026
CLK
CLKOUT
A
8 BITS
DATA
RESETN
HI3026
CLK
CLKOUT
B
8 BITS
DATA
RESETN
FIGURE 9. WHEN THE RESET PULSE IS NOT USED
CLK
RESET
PULSE
HI3026
CLK
CLK
CLKOUT
A
8 BITS
DATA
RESETN
HI3026
CLK
RESET PULSE
CLKOUT
B
RESETN
8 BITS
DATA
FIGURE 10. WHEN THE RESET PULSE IS USED
11
APPLICATION
CIRCUITS
PECL
The power supplies (DVEE3 , DGND3) for the logic input
CLK
SUPPLY
VOLTAGE
HI3026
Typical Performance Curves
170
CURRENT CONSUMPTION (mA)
CURRENT CONSUMPTION (mA)
170
160
150
140
130
-25
25
160
150
140
fCLK
-1kHz
4
DMUX MODE
CL = 5pF
fIN =
130
0
75
60
AMBIENT TEMPERATURE (oC)
FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE
CHARACTERISTICS RESPONSE
VRT = 4V
VRB = 2V
20
REFERENCE CURRENT (mA)
ANALOG INPUT CURRENT (μA)
FIGURE 11. CURRENT CONSUMPTION vs AMBIENT
TEMPERATURE CHARACTERISTICS
200
100
15
10
0
2
3
-25
4
25
75
AMBIENT TEMPERATURE (oC)
ANALOG INPUT VOLTAGE (V)
FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT
VOLTAGE CHARACTERISTICS
FIGURE 14. REFERENCE CURRENT vs AMBIENT
TEMPERATURE CHARACTERISTICS
50
fC = 120 MSPS
ERROR RATE (TPS)
10-6
40
SNR (dB)
120
CONVERSION RATE (MSPS)
30
fIN =
fCLK
-1kHz
4
ERROR > 16 LSB
10-7
10-8
10-9
10-10
20
1
3
5
10
30
120
50
140
CONVERSION RATE (MSPS)
INPUT FREQUENCY (MHz)
FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE
FIGURE 16. ERROR RATE vs CONVERSION RATE
CHARACTERISTICS
12
160
HI3026
MAXIMUM CONVERSION (MSPS)
Typical Performance Curves
170
160
(Continued)
fIN =
fCLK
-1kHz
4
ERROR > 16 LSB
ERROR RATE: 10-9 TPS
150
140
130
-25
25
75
AMBIENT TEMPERATURE (Co)
FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS
Application Circuits
+5V (D)
DG
ECL RESET PULSE
48 47 46 45 44 43 42 41 40 39 38 37
-5V (D)
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26 P2D0 TO P2D7
8-BIT DIGITAL DATA
25
1
AG
AG
2V
+5V (A)
DG
4V
12
13 14 15 16 17 18 19 20 21 22 23 24
ECL - CLK
DG
+5V (D)
FIGURE 18. DMUX ECL INPUT
13
8-BIT DIGITAL DATA
LATCH
DG
+5V (D)
DG
8-BIT DIGITAL DATA
LATCH
HI3026
Application Circuits
(Continued)
+5V (D)
DG
PECL RESET PULSE
48 47 46 45 44 43 42 41 40 39 38 37
DG
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26 P2D0 TO P2D7
8-BIT DIGITAL DATA
25
1
DG
AG
2V
+5V (A)
+5V (D)
4V
12
8-BIT DIGITAL DATA
LATCH
DG
+5V (D)
DG
8-BIT DIGITAL DATA
LATCH
13 14 15 16 17 18 19 20 21 22 23 24
PECL - CLK
DG
+5V (D)
FIGURE 19. DMUX PECL INPUT
+5V (D)
DG
TTL RESET PULSE
48 47 46 45 44 43 42 41 40 39 38 37
DG
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26 P2D0 TO P2D7
8-BIT DIGITAL DATA
25
1
AG
AG
2V
+5V (A)
+5V (D)
4V
12
13 14 15 16 17 18 19 20 21 22 23 24
TTL - CLK
DG
+5V (D)
FIGURE 20. DMUX TTL INPUT
14
8-BIT DIGITAL DATA
LATCH
DG
+5V (D)
DG
8-BIT DIGITAL DATA
LATCH
HI3026
Application Circuits
(Continued)
DG
+5V (D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
-5V (D)
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26
1
AG
AG
2V
+5V (A)
DG
4V
8-BIT DIGITAL DATA
LATCH
DG
+5V (D)
DG
25
12
13 14 15 16 17 18 19 20 21 22 23 24
ECL - CLK
ECL - TTL
DG
+5V (D)
FIGURE 21. STRAIGHT ECL INPUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
15
HI3026
Application Circuits
(Continued)
DG
+5V (D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
DG
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26
AG
AG
1
2V
+5V (A)
+5V(D)
4V
8-BIT DIGITAL DATA
LATCH
DG
+5V (D)
DG
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PECL - CLK
PECL - TTL
DG
+5V (D)
FIGURE 22. STRAIGHT PECL INPUT
DG
+5V (D)
DG
48 47 46 45 44 43 42 41 40 39 38 37
DG
2
36 P1D0 TO P1D7
35 8-BIT DIGITAL DATA
3
34
4
33
+5V (A)
5
32
AG
6
31
7
30
8
29
9
28
AG
10
27
AG
11
26
AG
AG
1
2V
+5V (A)
+5V(D)
4V
DG
+5V (D)
DG
25
12
13 14 15 16 17 18 19 20 21 22 23 24
TTL - CLK
DG
+5V (D)
FIGURE 23. STRAIGHT TTL INPUT
16
8-BIT DIGITAL DATA
LATCH
Application Circuits
(Continued)
AG
ANALOG
INPUT
AG
+
+5V
(A)
1μF
DG
+
+
1μF
AG
+
10μF
AG
12
11
10
9
8
7
6
5
4
3
2
DGND3
VRT
AGND
VRM3
AVCC
VRM2
VIN
AVCC
VRM1
AGND
VRB
1
RESETN/E 48
13
CLK/E
14
CLKN/E
15
CLK/T
16
NC
SELECT 45
17
NC
INV 44
18
NC
CLKOUT 43
19
DVCC2
DVCC2 42
20
DGND2
DGND2 41
21
P2D0
P1D7 40
22
P2D1
P1D6 39
23
P2D2
P1D5 38
24
P2D3
P1D4 37
RESET/E 47
P2D6
(MSB) P2D7
P1D3
P2D5
32
33
34
35
36
P1D3
31
P1D2
DVCC2
30
P1D2
DVCC1
29
P1D1
DGND1
28
P1D1
P2D7
27
P1D0
P2D6
26
(LSB) P1D0
P2D5
25
DGND2
P2D4
RESETN/T 46
P2D4
P2D2
P2D3
+
2V
10μF
SHORT
TTL CLK
(LSB) P2D0
P2D1
+
SHORT
-
SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY
UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION
IS THE CHIP CAPACITOR OF 0.1μF.
FIGURE 24. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED)
17
P1D6
(MSB) P1D7
(D)
AG
+
+5V
P1D4
P1D5
-
DVEE3
4V
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