HI5760BIB-T

DATASHEET HI5760 FN4320 Rev 8.00 Mar 30, 2005 10-Bit, 125/60MSPS, High Speed D/A Converter The HI5760 is a 10-bit, 125MSPS, high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. For an equivalent performance dual version, see the HI5728. Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS • Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V • Power Down Mode. . . . . . . . . . 23mW at 5V, 10mW at 3V • Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . 1 LSB • Adjustable Full Scale Output Current . . . . . 2mA to 20mA This device complements the HI5X60 family of high speed converters offered by Intersil, which includes 8, 10, 12, and 14-bit devices. • SFDR to Nyquist at 5MHz Output . . . . . . . . . . . . . . 68dBc Ordering Information • Single Power Supply from +5V to +3V PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CLOCK SPEED • Internal 1.2V Temperature Compensated Bandgap Voltage Reference • CMOS Compatible Inputs • Excellent Spurious Free Dynamic Range HI5760BIB -40 to 85 28 Ld SOIC M28.3 125MHz HI5760BIBZ (See Note) -40 to 85 28 Ld SOIC (Pb-free) M28.3 125MHz HI5760IA -40 to 85 28 Ld TSSOP M28.173 125MHz HI5760IAZ (See Note) -40 to 85 28 Ld TSSOP M28.173 125MHz (Pb-free) • Set Top Boxes HI5760/6IB -40 to 85 28 Ld SOIC M28.3 60MHz • Wireless Communications HI5760/6IBZ (See Note) -40 to 85 28 Ld SOIC (Pb-free) M28.3 60MHz • Direct Digital Frequency Synthesis HI5760EVAL1 25 • Pb-Free Available (RoHS Compliant) Applications Evaluation Platform • Cable Modems • Signal Reconstruction 125MHz * Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Test Instrumentation • High Resolution Imaging Systems • Arbitrary Waveform Generators Pinout HI5760 (SOIC, TSSOP) TOP VIEW D9 (MSB) 1 FN4320 Rev 8.00 Mar 30, 2005 28 CLK D8 2 27 DVDD D7 3 26 DCOM D6 4 25 NC D5 5 24 AVDD D4 6 23 NC D3 7 22 IOUTA D2 8 21 IOUTB D1 9 20 ACOM D0 (LSB) 10 19 COMP1 NC 11 18 FSADJ NC 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP Page 1 of 18 HI5760 Typical Applications Circuit HI5760 NC (11-14, 25) (15) SLEEP (16) REFLO D9 D9 (MSB) (1) D8 D8 (2) D7 D7 (3) D6 D6 (4) D5 D5 (5) D4 D4 (6) D3 D3 (7) D2 D2 (8) D1 D1 (9) D0 D0 (LSB) (10) CLK (28) 50 FERRITE BEAD 10F + 10H DCOM (17) REFIO ACOM 0.1F (18) FSADJ RSET (22) IOUTA 2k D/A OUT 50 50 (21) IOUTB D/A OUT (23) NC (19) COMP1 DCOM (26) (20) ACOM DVDD (27) (24) AVDD 0.1F FERRITE BEAD 10H 0.1F 0.1F +5V OR +3V (VDD ) + 10F Functional Block Diagram IOUTA IOUTB (LSB) D0 CASCODE CURRENT SOURCE D1 D2 D3 D4 LATCH LATCH 36 SWITCH MATRIX D5 36 5 LSBs + 31 MSB SEGMENTS D6 UPPER 5-BIT D7 31 DECODER D8 (MSB) D9 COMP1 CLK INT/EXT REFERENCE SELECT AVDD FN4320 Rev 8.00 Mar 30, 2005 ACOM DVDD DCOM REFLO INT/EXT VOLTAGE REFERENCE REFIO BIAS GENERATION FSADJ SLEEP Page 2 of 18 HI5760 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DVDD + 0.3V Internal Reference Output Current  50A Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Resistance (Typical, Note 1) Operating Conditions JA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Maximum Junction Temperature HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values HI5760 TA = -40oC TO 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 10 - - Bits -1 0.5 +1 LSB (Note 7) -0.5 0.25 +0.5 LSB Offset Error, IOS (Note 7) -0.025 +0.025 % FSR Offset Drift Coefficient (Note 7) - 0.1 - ppm FSR/oC Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -10 2 +10 % FSR With Internal Reference (Notes 2, 7) Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) Differential Linearity Error, DNL -10 1 +10 % FSR With External Reference (Note 7) - 50 - ppm FSR/oC With Internal Reference (Note 7) - 100 - ppm FSR/oC 2 - 20 mA (Note 3) -0.3 - 1.25 V Maximum Clock Rate, fCLK (Note 3) 125 - - MHz Output Settling Time, (tSETT) 0.2% (1 LSB, equivalent to 9 Bits) (Note 7) - 20 - ns 0.1% (1/2 LSB, equivalent to 10 Bits) (Note 7) - 35 - ns Singlet Glitch Area (Peak Glitch) RL = 25(Note 7) - 5 - pV•s Output Rise Time Full Scale Step - 1.0 - ns Output Fall Time Full Scale Step - 1.5 - ns - 10 - pF IOUTFS = 20mA - 50 - pA/Hz IOUTFS = 2mA - 30 - pA/Hz Full Scale Gain Drift Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Output Capacitance Output Noise FN4320 Rev 8.00 Mar 30, 2005 Page 3 of 18 HI5760 Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HI5760 TA = -40oC TO 85oC MIN TYP MAX UNITS fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) - 75 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) - 76 - dBc fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) - 75 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) - 76 - dBc fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) - 78 - dBc fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) - 71 - dBc fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) - 71 - dBc fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) - 76 - dBc PARAMETER TEST CONDITIONS AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz Spurious Free Dynamic Range, SFDR Within a Window Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) - 54 - dBc fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) - 64 - dBc fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) - 52 - dBc fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) - 60 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) - 74 - dBc fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) - 63 - dBc fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) - 55 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) - 68 - dBc fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) - 73 - dBc fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) - 73 - dBc AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) - 75 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) - 76 - dBc fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) - 78 - dBc Total Harmonic Distortion (THD) to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) - 71 - dBc fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) - 76 - dBc Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) - 56 - dBc fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) - 63 - dBc fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) - 55 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) - 68 - dBc fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) - 73 - dBc fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) - 73 - dBc fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) - 71 - dBc 1.04 1.16 1.28 V Internal Reference Voltage Drift - 60 - ppm/oC Internal Reference Output Current Sink/Source Capability - 0.1 - A Reference Input Impedance - 1 - M Reference Input Multiplying Bandwidth (Note 7) - 1.4 - MHz Spurious Free Dynamic Range, SFDR Within a Window VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ FN4320 Rev 8.00 Mar 30, 2005 Pin 18 Voltage with Internal Reference Page 4 of 18 HI5760 Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HI5760 TA = -40oC TO 85oC PARAMETER DIGITAL INPUTS TEST CONDITIONS MIN TYP MAX UNITS D9-D0, CLK Input Logic High Voltage with 5V Supply, VIH (Note 3) 3.5 5 - V Input Logic High Voltage with 3V Supply, VIH (Note 3) 2.1 3 - V Input Logic Low Voltage with 5V Supply, VIL (Note 3) - 0 1.3 V Input Logic Low Voltage with 3V Supply, VIL (Note 3) - 0 0.9 V Input Logic Current, IIH -10 - +10 A Input Logic Current, IIL -10 - +10 A - 5 - pF Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 41 (Note 3) 3 - - ns Data Hold Time, tHLD See Figure 41 (Note 3) 3 - - ns Propagation Delay Time, tPD See Figure 41 - 1 - ns CLK Pulse Width, tPW1 , tPW2 See Figure 41 (Note 3) 4 - - ns POWER SUPPLY CHARACTERISTICS AVDD Power Supply (Note 8) 2.7 5.0 5.5 V DVDD Power Supply (Note 8) 2.7 5.0 5.5 V Analog Supply Current (IAVDD) (5V or 3V, IOUTFS = 20mA) - 23 30 mA (5V or 3V, IOUTFS = 2mA) - 4 - mA Digital Supply Current (IDVDD) (5V, IOUTFS = Don’t Care) (Note 5) - 3 5 mA (3V, IOUTFS = Don’t Care) (Note 5) - 1.5 - mA Supply Current (IAVDD) Sleep Mode (5V or 3V, IOUTFS = Don’t Care) - 1.6 3 mA Power Dissipation (5V, IOUTFS = 20mA) (Note 6) - 165 - mW (5V, IOUTFS = 2mA) (Note 6) - 70 - mW (5V, IOUTFS = 20mA) (Note 9) - 150 - mW (3.3V, IOUTFS = 20mA) (Note 9) - 75 - mW (3V, IOUTFS = 20mA) (Note 6) - 85 - mW (3V, IOUTFS = 20mA) (Note 9) - 67 - mW (3V, IOUTFS = 2mA) (Note 6) - 27 - mW -0.2 - +0.2 % FSR/V Power Supply Rejection Single Supply (Note 7) NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the ratio should be 31.969. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential coupled transformer. 5. Measured with the clock at 50MSPS and the output frequency at 1MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. See ‘Definition of Specifications’. 8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal. 9. Measured with the clock at 60MSPS and the output frequency at 10MHz. FN4320 Rev 8.00 Mar 30, 2005 Page 5 of 18 HI5760 Typical Performance Curves, 5V Power Supply 80 76 74 75 -6dBFS 72 -6dBFS SFDR (dBc) SFDR (dBc) 70 0dBFS 65 60 70 -12dBFS 68 66 64 -12dBFS 55 0dBFS 62 60 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1 2 2 3 4 5 6 7 8 9 10 40 45 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) FIGURE 1. SFDR vs fOUT, CLOCK = 5MSPS FIGURE 2. SFDR vs fOUT, CLOCK = 25MSPS 80 75 0dBFS SFDR (dBc) SFDR (dBc) -6dBFS 70 65 -12dBFS 65 -12dBFS 60 55 60 55 -6dBFS 70 75 0dBFS 50 0 2 4 6 8 10 12 14 16 18 45 20 0 5 10 OUTPUT FREQUENCY (MHz) FIGURE 3. SFDR vs fOUT, CLOCK = 50MSPS 20 25 30 35 FIGURE 4. SFDR vs fOUT, CLOCK = 100MSPS 75 80 25MSPS 70 75 65 50MSPS 70 6dBFS -12dBFS 60 SFDR (dBc) SFDR (dBc) 15 OUTPUT FREQUENCY (MHz) 55 65 125MSPS 60 55 0dBFS 50 100MSPS 50 45 0 5 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz) FIGURE 5. SFDR vs fOUT, CLOCK = 125MSPS FN4320 Rev 8.00 Mar 30, 2005 45 50 45 -25 -20 -15 -10 -5 AMPLITUDE (dBFS) FIGURE 6. SFDR vs AMPLITUDE, fCLK / fOUT = 10 Page 6 of 18 0 HI5760 Typical Performance Curves, 5V Power Supply (Continued) 75 80 25MSPS 75 50MSPS 65 65 SFDR (dBc) SFDR (dBc) 70 100MSPS 60 125MSPS 55 60 125MSPS (16.9/18.1MHz) 45 40 -25 -20 -15 -10 -5 40 -25 0 AMPLITUDE (dBFS) -20 -15 -10 -5 0 AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS) FIGURE 7. SFDR vs AMPLITUDE, fCLK / fOUT = 5 FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, fCLK / fOUT = 7 75 75 2.5MHz 70 70 -6dBFS DIFF 10MHz 65 0dBFS DIFF 65 60 SFDR (dBc) SFDR (dBc) 100MSPS (13.5/14.5MHz) 50 45 20MHz 55 40MHz 50 60 55 -6dBFS SINGLE 50 45 0dBFS SINGLE 2 4 6 8 10 12 IOUT (mA) 14 16 18 45 20 5 10 15 20 25 30 35 40 FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS 80 -10 -10 2.5MHz 75 -20 -20 -30 -30 70 -40 -40 10.1MHz AMP (dB) (dB) Amp 65 60 55 -50 -50 fCLK = 100MSPS =f 100MSPS = 9.95MHz Fout =OUT 9.95MHz AMPLITUDE = 0dBFS Amplitude = 0dBFS SFDR = 64dBc SFDR = 64dBc 14dB 14dB EXTERNAL ATTENUATION ExternalANALYZER Analyzer Attenuation -60 -60 -70 -70 -80 -80 50 -90 -90 40.4MHz 45 40 -40 0 OUTPUT FREQUENCY (MHz) FIGURE 9. SFDR vs IOUT, CLOCK = 100MSPS SFDR (dBc) 50MSPS (6.75/7.25MHz) 55 50 40 25MSPS (3.38/3.63MHz) 70 -20 0 20 40 60 -100 -100 80 TEMPERATURE (oC) FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS FN4320 Rev 8.00 Mar 30, 2005 -110 -110 00 50 5MHz/DIV.. 5MHz/DIV. Frequency (MHz) FREQUENCY (MHz) FIGURE 12. SINGLE TONE SFDR Page 7 of 18 HI5760 Typical Performance Curves, 5V Power Supply (Continued) -10 -20 -20 Fclk = 100MSPS fCLK = 100MSPS Fout = 13.5/14.5MHz = 13.5/14.5MHz fOUT Combined PeakCOMBINED Amplitude =PEAK 0dBFS MTPR==0dBFS 62.9dBc AMPLITUDE 14dB External Analyzer Attenuation SFDR = 62.9dBc 14dB EXTERNAL ANALYZER ATTENUATION -40 -40 AMP(dB) (dB) Amp -50 -50 -60 -60 -30 -40 -70 -70 -80 -80 -50 -60 -70 -90 -90 -80 -100 -100 -110 -110 -90 00 5MHz/DIV. 5MHz/DIV. Frequency (MHz) FREQUENCY (MHz) -100 0.5 50 FIGURE 13. TWO TONE, CLOCK = 100MSPS -10 fCLK = 100MSPS fOUT = 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67dBc (IN A WINDOW) -30 -40 -30 -40 -60 -70 -50 -60 -80 -70 -90 -80 -100 -90 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) fCLK = 50MSPS fOUT = 1.9,2.2,2.8,3.1MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 73.6dBc (IN A WINDOW) -20 AMP (dB) -50 AMP (dB) 15 1.45MHz / DIV. FIGURE 14. FOUR-TONE, CLOCK = 100MSPS -20 -100 0.5 20 950kHz/DIV. 10 FREQUENCY (MHz) FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS FIGURE 16. FOUR-TONE, CLOCK = 50MSPS 0.4 0.4 0.2 0.2 LSB LSB fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 71.4dBc (IN A WINDOW) -20 AMP (dB) -30 -30 0 0 -0.2 -0.2 -0.4 -0.4 0 200 400 600 800 CODE FIGURE 17. DIFFERENTIAL NONLINEARITY FN4320 Rev 8.00 Mar 30, 2005 1000 0 200 400 600 800 1000 CODE FIGURE 18. INTEGRAL NONLINEARITY Page 8 of 18 HI5760 Typical Performance Curves, 5V Power Supply (Continued) 160 155 150 POWER (mW) 145 140 135 130 125 120 115 110 105 0 20 40 60 80 100 120 CLOCK RATE (MSPS) FIGURE 19. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA Typical Performance Curves, 3V Power Supply 80 80 0dBFS -6dBFS 75 -6dBFS 70 0dBFS SFDR (dBc) SFDR (dBc) 75 65 60 70 -12dBFS 65 -12dBFS 55 60 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1 2 2 3 OUTPUT FREQUENCY (MHz) 4 5 6 7 8 9 10 OUTPUT FREQUENCY (MHz) FIGURE 20. SFDR vs fOUT, CLOCK = 5MSPS FIGURE 21. SFDR vs fOUT, CLOCK = 25MSPS 80 80 75 75 0dBFS SFDR (dBc) SFDR (dBc) 70 -6dBFS 70 -12dBFS 65 60 0dBFS 65 -12dBFS 60 55 55 50 -6dBFS 50 0 2 4 6 8 10 12 14 16 18 OUTPUT FREQUENCY (MHz) FIGURE 22. SFDR vs fOUT, CLOCK = 50MSPS FN4320 Rev 8.00 Mar 30, 2005 20 45 0 5 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz) FIGURE 23. SFDR vs fOUT, CLOCK = 100MSPS Page 9 of 18 45 HI5760 Typical Performance Curves, 3V Power Supply (Continued) 80 80 75 75 70 70 65 SFDR (dBc) SFDR (dBc) 0dBFS -6dBFS 60 -12dBFS 100MSPS 125MSPS 60 55 50 50 0 5 10 15 20 25 30 35 40 45 50MSPS 65 55 45 25MSPS 45 -25 50 -20 -15 FIGURE 24. SFDR vs fOUT, CLOCK = 125MSPS -5 0 FIGURE 25. SFDR vs AMPLITUDE, fCLK / fOUT = 10 75 80 25MSPS 75 70 70 65 50MSPS 65 60 100MSPS 5MSPS 55 50 2 SFDR (dBc) SFDR (dBc) -10 AMPLITUDE (dBFS) OUTPUT FREQUENCY (MHz) ND 5A 50 PS MS 125MSPS 25MSPS (3.38/3.63MHz) 60 50MSPS (6.75/7.25MHz) 55 100MSPS (13.5/14.5MHz) 50 125MSPS (16.9/18.1MHz) 45 45 40 -25 -20 -15 -10 -5 40 -25 0 -20 -15 AMPLITUDE (dBFS) -10 -5 0 AMPLITUDE (dBFS) FIGURE 26. SFDR vs AMPLITUDE, fCLK / fOUT = 5 FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, fCLK/fOUT = 7 80 80 75 75 70 70 65 10MHz 60 20MHz SFDR (dBc) SFDR (dBc) 2.5MHz 0dBFS DIFF 65 -6dBFS SINGLE 60 -6dBFS DIFF 55 55 40MHz 50 50 0dBFS SINGLE 45 2 4 6 8 10 12 14 16 18 IOUT (MA) FIGURE 28. SFDR vs IOUT, CLOCK = 100MSPS FN4320 Rev 8.00 Mar 30, 2005 20 45 0 5 10 15 20 25 30 35 OUTPUT FREQUENCY (MHz) FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS Page 10 of 18 40 HI5760 Typical Performance Curves, 3V Power Supply (Continued) 80 -10 -30 70 10.1MHz -40 65 AMP (dB) SFDR (dBc) fCLK = 100MSPS fOUT = 9.95MHz AMPLITUDE = 0dBFS SFDR = 63dBc 14dB EXTERNAL ANALYZER ATTENUATION -20 2.5MHz 75 60 55 -50 -60 -70 -80 50 40.4MHz -90 45 -100 40 -40 -20 0 20 40 60 -110 80 0 5MHz/DIV. TEMPERATURE (oC) FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS FIGURE 31. SINGLE TONE SFDR -10 -20 fCLK = 100MSPS fOUT = 13.5/14.5MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 61.5dBc 14dB EXTERNAL ANALYZER ATTENUATION -40 AMP (dB) -50 -60 -30 -40 -70 -50 -60 -80 -70 -90 -80 -100 -90 0 5MHz/DIV. fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 70.6dBc (IN A WINDOW) -20 AMP (dB) -30 -110 -100 0.5 50 FREQUENCY (MHz) 1.45MHz/DIV. 15 FREQUENCY (MHz) FIGURE 32. TWO-TONE, CLOCK = 100MSPS FIGURE 33. FOUR-TONE, CLOCK = 100MSPS -20 -10 fCLK = 100MSPS fOUT = 2.6, 3.2, 3.8, 4.4, 5.6, 6.2, 6.8MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67.4dBc (IN A WINDOW) -40 -50 -60 -30 -40 -70 -50 -60 -80 -70 -90 -80 -100 -90 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS FN4320 Rev 8.00 Mar 30, 2005 fCLK = 50MSPS fOUT = 1.9, 2.2, 2.8, 3.1MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 74.2dBc (IN A WINDOW) -20 AMP (dB) -30 AMP (dB) 50 FREQUENCY (MHz) 20 -100 0 950kHz/DIV. FREQUENCY (MHz) FIGURE 35. FOUR-TONE, CLOCK = 50MSPS Page 11 of 18 10 HI5760 (Continued) 0.4 0.4 0.2 0.2 LSB LSB Typical Performance Curves, 3V Power Supply 0 0 -0.2 -0.2 -0.4 -0.4 0 200 400 600 800 1000 0 200 400 CODE 600 800 1000 CODE FIGURE 36. DIFFERENTIAL NONLINEARITY FIGURE 37. INTEGRAL NONLINEARITY 76 74 POWER (mW) 72 70 68 66 64 62 60 0 20 40 60 80 100 120 CLOCK RATE (MSPS) FIGURE 38. POWER vs CLOCK RATE, fCLK / fOUT = 10, IOUT = 20mA FN4320 Rev 8.00 Mar 30, 2005 Page 12 of 18 HI5760 Timing Diagrams 50% CLK D9-D0 GLITCH AREA = 1 / 2 (H x W) V 1/ LSB ERROR BAND 2 HEIGHT (H) IOUT t(ps) WIDTH (W) tSETT tPD FIGURE 39. OUTPUT SETTLING TIME DIAGRAM tPW1 FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW2 50% CLK tSU tSU tHLD tSU tHLD tHLD D9-D0 tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM FN4320 Rev 8.00 Mar 30, 2005 Page 13 of 18 HI5760 Definition of Specifications Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. In the case of the HI5760, the measurement was done by switching from code 0 to 256, or quarter scale. Termination impedance was 25 due to the parallel resistance of the output 50 and the oscilloscope’s 50 input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (full scale range) per degree C. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range. Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Power Supply Rejection, is measured using a single power supply. Its nominal +5V is varied 10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 of its original value. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either Tmin or Tmax. The units are ppm per degree C. Detailed Description The HI5760 is a 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 165mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources of equivalent current. The five LSBs are comprised of binary weighted current sources. Consider an input waveform to the converter which is ramped through all the codes from 0 to 1023. The five LSB current sources would begin to count up. When they reached the all high state (decimal value of 31) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 5 LSBs would count up another 31 codes, and then the next major current source would turn on and the five LSBs would all turn off. The process of the single, equivalent, major current source turning on and the five LSBs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as mid-scale and quarter scale transitions. By greatly reducing the amount of current switching at certain ‘major’ transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems. Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (full scale range) per degree C. FN4320 Rev 8.00 Mar 30, 2005 Page 14 of 18 HI5760 Digital Inputs and Termination The HI5760 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are 50 lines, then 50 termination resistors should be placed as close to the converter inputs as possible to the digital ground plane (if separate grounds are used). Ground Plane(s) If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. The converter will function properly with a single ground plane, as the Evaluation Board is configured in this matter. Refer to the Application Note on the HI5760 Evaluation Board for further discussion of the ground plane(s) upon availability. Noise Reduction To minimize power supply noise, 0.1F capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended. See the Application Note on the HI5760 Evaluation Board for more information upon availability. Voltage Reference The internal voltage reference of the device has a nominal value of +1.2V with a  60 ppm / oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1F capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, through operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.16V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86k RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D9-D0) IOUTA (mA) IOUTB (mA) 11111 11111 20 0 10000 00000 10 10 00000 00000 0 20 Outputs IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the ‘Reference’ section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mVP-P amplitude with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. 50 PIN 21 PIN 22 HI5760 VOUT = (2 x IOUT x REQ)V IOUTB 100 IOUTA 50 50 FIGURE 42. VOUT = 2 x IOUT x REQ, where REQ is ~12.5 IOUT (Full Scale) = (VFSADJ/RSET)x 32 FN4320 Rev 8.00 Mar 30, 2005 Page 15 of 18 HI5760 Pin Descriptions PIN NO. PIN NAME 1-10 D9 (MSB) Through D0 (LSB) 11-14 NC 15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20A active pulldown current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1F cap to ground when internal reference is enabled. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. 19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1F to AVDD . 20 ACOM Analog Ground. 21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 NC 24 AVDD 25 NC 26 DCOM Digital Ground. 27 DVDD Digital Supply (+3V to +5V). 28 CLK FN4320 Rev 8.00 Mar 30, 2005 PIN DESCRIPTION Digital Data Bit 9 (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). No Connect. Recommend ground. Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1F capacitor to ACOM.) Analog Supply (+3V to +5V). No Connect. (For upward compatibility to 12 and 14b devices, pin 25 needs to be grounded to ACOM.) Input for clock. Positive edge of clock latches data. Page 16 of 18 HI5760 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MAX MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e  MIN 0.05 BSC h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o  10.00 28 0o 10.65 - 0.394 N 0.419 1.27 BSC H 28 - 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4320 Rev 8.00 Mar 30, 2005 Page 17 of 18 HI5760 Thin Shrink Small Outline Plastic Packages (TSSOP) M28.173 N INDEX AREA E 0.25(0.010) M E1 2 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M SEATING PLANE L A D -C- e  A2 A1 b 0.10(0.004) M 0.25 0.010 c 0.10(0.004) C A M B S SYMBOL MIN MAX MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC E 0.246 L 0.0177 N NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. MILLIMETERS  0.65 BSC 0.256 6.25 0.0295 0.45 28 0o - 0.75 6 28 8o 0o - 6.50 7 8o Rev. 0 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2000-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4320 Rev 8.00 Mar 30, 2005 Page 18 of 18