HI5766
10-Bit, 60MSPS A/D Converter
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The HI5766 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 60MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
The HI5766 has excellent dynamic performance while
consuming only 260mW power at 60MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702, HI5703 and the
HI5746.
DATASHEET
FN4130
Rev 6.00
March 30, 2005
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60MSPS
• 8.3 Bits at fIN = 10MHz
• Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 260mW
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
• On Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• TTL/CMOS Compatible Digital Inputs
For internal voltage reference, please refer to the HI5767
data sheet.
• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V
Ordering Information
• Pb-Free Available (RoHS Compliant)
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
HI5766KCB
0 to 70
28 Ld SOIC (W)
M28.3
HI5766KCBZ
(See Note)
0 to 70
28 Ld SOIC (W)
(Pb-free)
M28.3
HI5766KCA
0 to 70
28 Ld SSOP
M28.15
HI5766KCAZ
(See Note)
0 to 70
28 Ld SSOP
(Pb-free)
M28.15
HI5766EVAL1
25
• Offset Binary or Two’s Complement Output Format
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
Pinout
HI5766
(SOIC, SSOP)
TOP VIEW
Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DVCC1 1
28 D0
DGND 2
27 D1
DVCC1 3
DGND 4
26 D2
AVCC 5
AGND 6
24 D4
VREF + 7
22 CLK
VREF - 8
21 DGND
23 DVCC2
VIN+ 9
20 D5
VIN- 10
VDC 11
19 D6
AGND 12
17 D8
AVCC 13
16 D9
OE 14
FN4130 Rev 6.00
March 30, 2005
25 D3
18 D7
15 DFS
Page 1 of 16
HI5766
Functional Block Diagram
VDC
CLOCK
BIAS
CLK
VINVIN+
S/H
STAGE 1
DFS
2-BIT
FLASH
2-BIT
DAC
OE
+
DVCC2
X2
D9 (MSB)
D8
D7
D6
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
STAGE 8
D5
D4
D3
2-BIT
FLASH
2-BIT
DAC
D2
D1
+
D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT
FLASH
AVCC
FN4130 Rev 6.00
March 30, 2005
AGND
DVCC1
DGND1
VREF +
VREF - (OPTIONAL)
Page 2 of 16
HI5766
Typical Application Schematic
HI5766
2.5V
2.0V
(OPTIONAL)
VREF+ (7)
VREF - (8)
(LSB) (28) D0
D0
(27) D1
D1
(26) D2
D2
(25) D3
D3
(24) D4
D4
DGND1 (2)
(20) D5
D5
DGND1 (4)
(19) D6
D6
DGND2 (21)
(18) D7
D7
(17) D8
D8
(MSB) (16) D9
D9
AGND (12)
AGND (6)
VIN +
CLOCK
VDC (11)
(3) DVCC1
VIN - (10)
(23) DVCC2
CLK (22)
(13) AVCC
DFS (15)
(5) AVCC
OE (14)
0.1F
+
10F
0.1F
+
10F
Pin Description
Pin Description
BNC
AGND
10F AND 0.1F CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
(1) DVCC1
VIN + (9)
VIN -
DGND
+5V
+5V
(Continued)
PIN NO.
NAME
Digital Supply (+5.0V).
15
DFS
Data Format Select Input.
DGND1
Digital Ground.
16
D9
Data Bit 9 Output (MSB).
3
DVCC1
Digital Supply (+5.0V).
17
D8
Data Bit 8 Output.
4
DGND1
Digital Ground.
18
D7
Data Bit 7 Output.
5
AVCC
Analog Supply (+5.0V).
19
D6
Data Bit 6 Output.
6
AGND
Analog Ground.
20
D5
Data Bit 5 Output.
7
VREF+
+2.5V Positive Reference Voltage
Input.
21
DGND2
22
CLK
Sample Clock Input.
8
VREF -
+2.0V Negative Reference Voltage
Input (Optional).
23
DVCC2
Digital Output Supply
(+3.0V or +5.0V).
9
VIN+
Positive Analog Input.
24
D4
Data Bit 4 Output.
10
VIN-
Negative Analog Input.
25
D3
Data Bit 3 Output.
11
VDC
DC Bias Voltage Output.
26
D2
Data Bit 2 Output.
12
AGND
Analog Ground.
13
AVCC
Analog Supply (+5.0V).
27
D1
Data Bit 1 Output.
14
OE
28
D0
Data Bit 0 Output (LSB).
PIN NO.
NAME
1
DVCC1
2
FN4130 Rev 6.00
March 30, 2005
DESCRIPTION
Digital Output Enable Control Input.
DESCRIPTION
Digital Ground.
Page 3 of 16
HI5766
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . 6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Resistance (Typical, Note 1)
Operating Conditions
Temperature Range
HI5766KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
-
-
Bits
ACCURACY
Resolution
Integral Linearity Error, INL
fIN = DC
-
1.0
2.0
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = DC
-
0.5
1.0
LSB
Offset Error, VOS
fIN = DC
-40
12
+40
LSB
Full Scale Error, FSE
fIN = DC
-
4
-
LSB
Minimum Conversion Rate
No Missing Codes
-
0.5
1
MSPS
Maximum Conversion Rate
No Missing Codes
60
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 10MHz
-
8.3
-
Bits
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
fIN = 10MHz
-
51.7
-
dB
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
fIN = 10MHz
-
53.7
-
dB
Total Harmonic Distortion, THD
fIN = 10MHz
-
-56.2
-
dBc
2nd Harmonic Distortion
fIN = 10MHz
-
-61.6
-
dBc
3rd Harmonic Distortion
fIN = 10MHz
-
-58.1
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 10MHz
-
58.1
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
62
-
dBc
Differential Gain Error
fS = 17.72 MSPS, 6 Step, Mod Ramp
-
0.8
-
%
Differential Phase Error
fS = 17.72 MSPS, 6 Step, Mod Ramp
-
0.1
-
Degree
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
DYNAMIC CHARACTERISTICS
FN4130 Rev 6.00
March 30, 2005
Page 4 of 16
HI5766
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
-
0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
-
1
-
M
-
10
-
pF
ANALOG INPUT
Analog Input Resistance, RIN
(Note 3)
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
(Note 3)
-10
-
+10
A
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
(Note 3)
-
0.5
-
A
-
250
-
MHz
0.25
-
4.75
V
Total Reference Resistance, RL
-
2.5K
-
Reference Current
-
1.0
-
mA
Full Power Input Bandwidth, FPBW
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
Differential Mode (Note 2)
REFERENCE INPUT
Positive Reference Voltage Input, VREF+
(Note 2)
-
2.5
-
V
Negative Reference Voltage Input, VREF -
(Note 2)
-
2.0
-
V
Reference Common Mode Voltage
(VREF+ + VREF -) / 2
(Note 2)
-
2.25
-
V
DC Bias Voltage Output, VDC
-
3.2
-
V
Maximum Output Current
-
-
0.4
mA
DC BIAS VOLTAGE
DIGITAL INPUTS
Input Logic High Voltage, VIH
CLK, DFS, OE
2.0
-
-
V
Input Logic Low Voltage, VIL
CLK, DFS, OE
-
-
0.8
V
Input Logic High Current, IIH
CLK, DFS, OE, VIH = 5V
-10.0
-
+10.0
A
Input Logic Low Current, IIL
CLK, DFS, OE, VIL = 0V
-10.0
-
+10.0
A
-
7
-
pF
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 5V
4.0
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 5V
-
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 5V
-
1
10
A
Output Logic High Voltage, VOH
IOH = 100A; DVCC2 = 3V
2.4
-
-
V
Output Logic Low Voltage, VOL
IOL = 100A; DVCC2 = 3V
-
-
0.5
V
Output Three-State Leakage Current, IOZ
VO = 0/5V; DVCC2 = 3V
-
1
10
A
-
10
-
pF
Output Capacitance, COUT
FN4130 Rev 6.00
March 30, 2005
Page 5 of 16
HI5766
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREF+ = 2.5V; VREF - = 2.0V; fS = 60 MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Hold, tH
-
7
-
ns
Data Output Delay, tOD
-
8
-
ns
Data Output Enable Time, tEN
-
5
-
ns
Data Output Enable Time, tDIS
-
5
-
ns
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
-
-
7
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
-
20
Cycles
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1
4.75
5.0
5.25
V
At 3.0V
2.7
3.0
3.3
V
At 5.0V
4.75
5.0
5.25
V
POWER SUPPLY CHARACTERISTICS
Digital Output Supply Voltage, DVCC2
Supply Current, ICC
VIN+ - VIN- = 1.25V and DFS = “0”
-
52
-
mA
Power Dissipation
VI+ - VIN- = 1.25V and DFS = “0”
-
260
-
mW
Offset Error Sensitivity, VOS
AVCC or DVCC = 5V 5%
-
0.4
-
LSB
Gain Error Sensitivity, FSE
AVCC or DVCC = 5V 5%
-
0.8
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
FN4130 Rev 6.00
March 30, 2005
Page 6 of 16
HI5766
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1
SN + 2
SN + 5
HN+5
SN + 6
HN + 6 S N + 7
HN + 7
SN + 8
HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1 , N - 1
B2 , N - 2
B2 , N - 1
9TH
STAGE
DATA
OUTPUT
B1 , N
B1 , N + 4
B2 , N
B9 , N - 5
DN - 7
B1 , N + 1
B9 , N - 4
DN - 6
B1 , N + 5
B1 , N + 6
B2 , N + 4
B2 , N + 5
B2 , N + 6
B9 , N
B9 , N + 1
B9 , N + 2
DN - 2
DN - 1
DN
B1 , N + 7
B9 , N + 3
DN + 1
tLAT
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. HI5766 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
DATA
OUTPUT
2.4V
DATA N - 1
0.5V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
FN4130 Rev 6.00
March 30, 2005
Page 7 of 16
HI5766
Typical Performance Curves
9
55
SNR
fS = 60 MSPS
fS = 60 MSPS
TA = 25oC
8
SND
dB
ENOB (BITS)
TA = 25oC
45
7
6
35
1
10
100
1
10
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
FIGURE 4. SINAD AND SNR vs INPUT FREQUENCY
85
75
9
fS = 60 MSPS
TA = 25oC
-2HD
ENOB (BITS)
dBc
fS = 60 MSPS
fIN = 10MHz
TA = 25oC
8
SFDR
65
-3HD
55
100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
-THD
7
6
5
4
3
45
1
10
INPUT FREQUENCY (MHz)
0
100
5
10
15
20
25
30
35
INPUT LEVEL (-dBFS)
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT LEVEL
FIGURE 5. -2HD, -3HD, -THD AND SFDR vs INPUT FREQUENCY
10
fS = 60 MSPS
fIN = 10MHz
8.6
ENOB (BITS)
9
ENOB (BITS)
8.8
fS = 60 MSPS
fIN = 10MHz
TA = 25oC
8
7
TA = 25oC
VREF + - VREF - = 0.5V
8.4
8.2
8.0
7.8
6
40
45
50
55
DUTY CYCLE (%, tH /tCLK)
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE
FN4130 Rev 6.00
March 30, 2005
60
7.6
2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75
VREF+ (V)
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +
Page 8 of 16
HI5766
Typical Performance Curves
(Continued)
53
85
52
SNR
fIN = 10MHz
75
51
dBc
SND
dB
fS = 60 MSPS
80
50
TA = 25oC
-2HD
70
VREF + - VREF - = 0.5V
-3HD
65
49
fS = 60 MSPS
fIN = 10MHz
TA = 25oC
48
-THD
60
SFDR
55
VREF + - VREF - = 0.5V
47
2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75
50
2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75
VREF+ (V)
VREF+ (V)
NOTE: SFDR depicted here does not include any harmonic distortion.
FIGURE 10. -2HD, -3HD, -THD AND SFDR vs VREF +
FIGURE 9. SINAD AND SNR vs VREF +
51
8.4
fS = 60 MSPS
fIN = 10MHz
50
SNR
8.2
49
dB
ENOB (BITS)
TA = 25oC
VREF - NOT DRIVEN
SINAD
48
8.0
47
7.8
2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75
VREF+ (V)
FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +
(VREF - NOT DRIVEN)
TA = 25oC
VREF - NOT DRIVEN
46
2.25
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
VREF+ (V)
2.75
FIGURE 12. SINAD AND SNR vs VREF + (VREF - NOT DRIVEN)
80
8.6
fS = 60 MSPS
fIN = 10MHz
75
fS = 60 MSPS
TA = 25oC
TA = 25oC
VREF - NOT DRIVEN
-3HD
ENOB (BITS)
70
dBc
fS = 60 MSPS
fIN = 10MHz
65
SFDR
60
8.5
10MHz
8.4
-2HD
1MHz
55
-THD
50
2.25
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
VREF+ (V)
FIGURE 13. -2HD, -3HD, -THD AND SFDR vs VREF +
(VREF - NOT DRIVEN)
FN4130 Rev 6.00
March 30, 2005
2.75
8.3
0.25
0.75
1.25
1.75
2.25
2.75
3.25
3.75
4.25
VCM (V)
FIGURE 14. EFFECTIVE NUMBER OF BITS (ENOB) vs
ANALOG INPUT COMMON MODE VOLTAGE
Page 9 of 16
4.75
HI5766
Typical Performance Curves
(Continued)
60
8.9
1MHz fIN 15MHz
SUPPLY CURRENT (mA)
8.7
ENOB (BITS)
60 MSPS/1MHz
8.5
8.3
60 MSPS/10MHz
8.1
7.9
50
ICC
40
AICC
30
DICC1
20
10
7.7
DICC2
7.5
-40
-20
0
20
40
TEMPERATURE (oC)
60
0
80
10
20
30
40
50
60
fS (MSPS)
FIGURE 15. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE
FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK
FREQUENCY
1200
9.5
1000
9.0
IREF +
8.5
800
tOD
tOD (ns)
IREF (A)
TA = 25oC
600
400
8.0
7.5
7.0
200
6.5
IREF -20
0
20
40
TEMPERATURE (oC)
60
6.0
-40
80
0.25
DG
DG (%)
0.75
0.15
0.70
0.65
0.65
0.2
DP
0.1
0.60
0.55
0.05
0.50
0.45
0.40
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
0
FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE
FN4130 Rev 6.00
March 30, 2005
0.60
DG (%)
0.80
20
40
TEMPERATURE (oC)
60
80
0.3
0.70
fS = 17.72 MSPS
DP (DEGREES)
0.85
0
FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE
FIGURE 17. REFERENCE CURRENT vs TEMPERATURE
0.90
-20
DP
0.25
DG
0.2
DP
0.15
0.55
DG
0.50
0.45
fS = 17.72 MSPS
AVCC /DVCC1 = 5V 5%, TA = 25oC
0.1
0.05
0
0.40
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25
DVCC2 (V)
FIGURE 20. DIFFERENTIAL GAIN/PHASE vs SUPPLY
VOLTAGE
Page 10 of 16
DP (DEGREES)
0
-40
HI5766
Typical Performance Curves
(Continued)
3.30
0
fS = 60 MSPS
fIN = 1MHz
-10
TA = 25oC
OUTPUT LEVEL (dB)
-20
VDC (V)
3.20
3.10
-30
-40
-50
-60
-70
-80
-90
3.00
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
-100
0
100
FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
300
400 500 600 700
FREQUENCY (BIN)
800
900
1023
FIGURE 22. 2048 POINT FFT PLOT
0
fS = 60 MSPS
fIN = 10MHz
-10
TA = 25oC
-20
OUTPUT LEVEL (dB)
200
-30
-40
-50
-60
-70
-80
-90
-100
0
100
200
300
400 500 600 700
FREQUENCY (BIN)
800
900
1023
FIGURE 23. 2048 POINT FFT PLOT
Detailed Description
Theory of Operation
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 24 depicts
the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal1
and 2 , derived from the master sampling clock. During the
sampling phase, 1 , the input signal is applied to the sampling
capacitors, CS . At the same time the holding capacitors, CH ,
are discharged to analog ground. At the falling edge of 1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,2 , the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
FN4130 Rev 6.00
March 30, 2005
differential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS . The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
1
VIN+
1
1
1
CS
2
VIN-
CH
-+
VOUT+
+-
VOUT-
CS
1
CH
1
FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
Page 11 of 16
HI5766
two-bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter. Each
converter stage in the pipeline will be sampling in one phase
and amplifying in the other clock phase. Each individual
subconverter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in the
pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit to
be used by the digital error correction logic. The output of each
subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The digital
error correction logic uses the supplementary bits to correct any
error that may exist before generating the final 10-bit digital data
output of the converter.
Because of the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital data
bus on the 7th cycle of the clock after the analog sample is
taken. This time delay is specified as the data latency. After the
data latency time, the digital data representing each succeeding
analog sample is output during the following clock cycle. The
digital output data is synchronized to the external sampling clock
by a double buffered latching technique. The output of the digital
error correction circuit is available in two’s complement or offset
binary format depending on the state of the Data Format Select
(DFS) control input (see Table 1, A/D Code Table).
Reference Voltage Inputs, VREF - and VREF+
The HI5766 is designed to accept two external reference voltage
sources at the VREF input pins. Typical operation of the
converter requires VREF+ to be set at +2.5V and VREF - to be
set at 2.0V. However, it should be noted that the input structure
of the VREF+ and VREF - input pins consists of a resistive
voltage divider with one resistor of the divider (nominally 500)
connected between VREF+ and VREF - and the other resistor of
the divider (nominally 2000) connected between VREF - and
analog ground. This allows the user the option of supplying only
the +2.5V VREF+ voltage reference with the +2.0V VREF - being
generated internally by the voltage division action of the input
structure.
The HI5766 is tested with VREF - equal to +2.0V and VREF+
equal to +2.5V yielding a fully differential analog input voltage
range of 0.5V. VREF+ and VREF - can differ from the above
voltages.
In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at both
of the reference voltage input pins, VREF+ and VREF -.
Analog Input, Differential Connection
The analog input to the HI5766 is a differential input that can
be configured in various ways depending on the signal source
and the required level of performance. A fully differential
connection (Figure 25 and Figure 26) will give the best
performance for the converter.
VIN+
VIN
R
HI5766
VDC
R
-VIN
VIN-
FIGURE 25. AC COUPLED DIFFERENTIAL INPUT
Since the HI5766 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V. For
the differential input connection this implies the analog input
common mode voltage can range from 0.25V to 4.75V. The
performance of the ADC does not change significantly with the
value of the analog input common mode voltage.
A DC voltage source, VDC , equal to 3.2V (Typ), is made
available to the user to help simplify circuit design when using an
AC coupled differential input. This low output impedance voltage
source is not designed to be a reference but makes an excellent
DC bias source and stays well within the analog input common
mode voltage range over temperature.
For the AC coupled differential input (Figure 25) assume the
difference between VREF+, typically 2.5V, and VREF -,
typically 2V, is 0.5V. Full scale is achieved when the VIN
and -VIN input signals are 0.5VP-P , with -VIN being
180 degrees out of phase with VIN . The converter will be at
positive full scale when the VIN+ input is at VDC + 0.25V and
the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V).
Conversely, the converter will be at negative full scale when
the VIN+ input is equal to VDC - 0.25V and VIN- is at
VDC + 0.25V (VIN+ - VIN- = -0.5V).
The analog input can be DC coupled (Figure 26) as long as the
inputs are within the analog input common mode voltage range
(0.25V VDC 4.75V).
VIN
VIN+
VDC
R
C
HI5766
VDC
-VIN
VDC
R
VIN-
FIGURE 26. DC COUPLED DIFFERENTIAL INPUT
FN4130 Rev 6.00
March 30, 2005
Page 12 of 16
HI5766
The resistors, R, in Figure 26 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
VIN
VIN+
VDC
R
C
VDC
HI5766
VIN-
Analog Input, Single-Ended Connection
The configuration shown in Figure 27 may be used with a
single ended AC coupled input.
VIN+
VIN
R
VDC
HI5766
VIN-
FIGURE 27. AC COUPLED SINGLE ENDED INPUT
Again, assume the difference between VREF+, typically
2.5V, and VREF-, typically 2V, is 0.5V. If VIN is a 1VP-P
sinewave, then VIN+ is a 1VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at
positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN= +0.5V) and will be at negative full scale when VIN+ is
equal to VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient
headroom must be provided such that the input voltage
never goes above +5V or below AGND. In this case, VDC
could range between 0.5V and 4.5V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the DC bias source, VDC , output of the
HI5766.
The single ended analog input can be DC coupled
(Figure 28) as long as the input is within the analog input
common mode voltage range.
FIGURE 28. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 28 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before driving
the HI5766.
Digital Output Control and Clock Requirements
The HI5766 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5766, the duty
cycle of the clock should be held at 50% 5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5766 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
FN4130 Rev 6.00
March 30, 2005
Page 13 of 16
HI5766
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
L
S
B
M
S
B
L
S
B
M
S
B
CODE CENTER
DESCRIPTION
DIFFERENTIAL
INPUT
VOLTAGE
(VIN+ - VIN-)
+Full Scale (+FS) -1/4 LSB
0.499756V
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
+FS -
11/4 LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0.498779V
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
+3/4 LSB
732.422V
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-1/4 LSB
-244.141V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-FS + 13/4 LSB
-0.498291V
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
-Full Scale (-FS) + 3/4 LSB
-0.499268V
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,
(VREF + - VREF -) = 0.5V.
9. VREF+ = 2.5V and VREF - = 2V.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE input
to logic low for normal operation.
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
Supply and Ground Considerations
The HI5766 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
digital data outputs also have a separate supply pin, DVCC2 ,
which can be powered from a 3V or 5V supply. This allows the
outputs to interface with 3V logic if so desired.
The part should be mounted on a board that provides separate
low impedance connections for the analog and digital supplies
and grounds. For best performance, the supplies to the HI5766
should be driven by clean, linear regulated supplies. The board
should also have good high frequency decoupling capacitors
mounted as close as possible to the converter. If the part is
powered off a single supply then the analog supply should be
isolated with a ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when using
high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that is
3/ LSBs below positive Full Scale (+FS) with the offset error
4
removed. Full Scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the ideal
value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best fit
straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5766. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the part
is -0.5dB down from Full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02
FN4130 Rev 6.00
March 30, 2005
Page 14 of 16
HI5766
where: VCORR = 0.5 dB.
Transient Response
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is below full scale.
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, fS/2, excluding DC.
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS/2
excluding the fundamental, the first five harmonics and DC.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB
below full scale.
FN4130 Rev 6.00
March 30, 2005
Over-Voltage Recovery
Over-Voltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) relative to the reference burst.
Page 15 of 16
HI5766
Timing Definitions
Data Latency (tLAT)
Refer to Figure 1 and Figure 2 for these definitions.
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus on
the 7th cycle of the clock after the analog sample is taken.
This is due to the pipeline nature of the converter where the
analog sample has to ripple through the internal subconverter
stages. This delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital data lags the analog input sample by 7
sample clock cycles.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Power-Up Initialization
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
Data output delay time is the time to where the new data (N)
is valid.
© Copyright Intersil Americas LLC 2000-2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4130 Rev 6.00
March 30, 2005
Page 16 of 16
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