HI5805
12-Bit, 5MSPS A/D Converter
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
performance while consuming 300mW power at 5MSPS.
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
FN3984
Rev 7.00
March 31, 2005
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
• Pb-Free Available (RoHS Compliant)
Applications
Ordering Information
PART
NUMBER
DATASHEET
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• Digital Communication Systems
SAMPLE
RATE
TEMP.
RANGE (oC)
HI5805BIB
5MSPS
-40 to 85
28 Ld SOIC (W) M28.3
• Document Scanners
HI5805BIBZ
(See Note)
5MSPS
-40 to 85
28 Ld SOIC (W) M28.3
(Pb-free)
• Additional Reference Documents
- AN9214 Using Intersil High Speed A/D Converters
- AN9707 Using the HI5805EVAL1 Evaluation Board
HI5805EVAL1
25
PACKAGE
PKG.
DWG. #
Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• Undersampling Digital IF
Pinout
HI5805
(SOIC)
TOP VIEW
CLK 1
28 D0
DVCC1 2
DGND1 3
27 D1
DVCC1 4
25 D3
DGND1 5
24 D4
AVCC 6
23 D5
AGND 7
22 DVCC2
21 DGND2
VIN+ 8
VIN- 9
FN3984 Rev 7.00
March 31, 2005
26 D2
20 D6
VDC 10
19 D7
VROUT 11
18 D8
VRIN 12
17 D9
AGND 13
AVCC 14
16 D10
15 D11
Page 1 of 12
HI5805
Functional Block Diagram
VDC
VINVIN+
BIAS
CLOCK
CLK
VROUT
VRIN
REF
S/H
STAGE 1
DVCC2
4-BIT
FLASH
4-BIT
DAC
+
D11 (MSB)
X8
D10
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
-
STAGE 3
4-BIT
FLASH
4-BIT
DAC
+
-
D9
D8
D7
D6
D5
D4
D3
D2
D1
X8
D0 (LSB)
STAGE 4
4-BIT
FLASH
AGND
AVCC
DGND2
DVCC1
DGND1
Typical Application Schematic
(LSB) (28) D0
(27) D1
VROUT (11) (26) D2
(25) D3
VRIN (12)
(24) D4
AGND (7)
(23) D5
AGND (13)
(20) D6
DGND1 (3)
(19) D7
DGND1 (5)
(18) D8
DGND2 (21)
(17) D9
(16) D10
(MSB) (15) D11
VIN+ (8)
VDC (10)
(2) DVCC1
VIN-
VIN- (9)
(22) DVCC2
CLK (1)
BNC
D11
+5V
0.1F
+
10F
0.1F
+5V
+
10F
(6) AVCC
(14) AVCC
HI5805
FN3984 Rev 7.00
March 31, 2005
AGND
DGND
(4) DVCC1
VIN+
CLOCK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
10F AND 0.1F CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
Page 2 of 12
HI5805
Absolute Maximum Ratings
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . +6.0V
DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = DVCC2 = DVCC3 = +5.0V, fS = 5MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC,
Unless Otherwise Specified
HI5805BIB (-40oC TO 85oC)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
12
-
-
Bits
Integral Linearity Error, INL
fIN = DC
-
1
2
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = DC
-
0.5
1
LSB
Offset Error, VOS
fIN = DC
-
19
-
LSB
Full Scale Error, FSE
fIN = DC
-
32
-
LSB
No Missing Codes
-
0.5
-
MSPS
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
No Missing Codes
5
-
-
MSPS
Effective Number of Bits, ENOB
fIN = 1MHz
10.0
11
-
Bits
Signal to Noise and Distortion Ratio, SINAD
fIN = 1MHz
-
68
-
dB
fIN = 1MHz
-
68
-
dB
-
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
Total Harmonic Distortion, THD
fIN = 1MHz
-
-80
2nd Harmonic Distortion
fIN = 1MHz
-
-86
3rd Harmonic Distortion
fIN = 1MHz
-
-83
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 1MHz
-
83
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
-68
-
dBc
-
1
-
Cycle
0.2V Overdrive
-
2
-
Cycle
Maximum Peak-to-Peak Differential Analog Input Range
(VIN+ - VIN-)
-
2.0
-
V
Maximum Peak-to-Peak Single-Ended Analog Input Range
-
4.0
-
V
M
Transient Response
Over-Voltage Recovery
dBc
dBc
ANALOG INPUT
1
-
-
-
10
-
pF
-10
-
+10
A
Differential Analog Input Bias Current IB DIFF = (IB+ - IB-)
-
0.5
-
A
Full Power Input Bandwidth, FPBW
-
100
-
MHz
Analog Input Resistance, RIN
(Notes 2, 3)
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
FN3984 Rev 7.00
March 31, 2005
(Note 3)
Page 3 of 12
HI5805
Electrical Specifications
AVCC = DVCC1 = DVCC2 = DVCC3 = +5.0V, fS = 5MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)
HI5805BIB (-40oC TO 85oC)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
1
2.3
4
V
Reference Output Voltage, VROUT (Loaded)
-
3.5
-
V
Reference Output Current
-
-
1
mA
Reference Temperature Coefficient
-
200
-
ppm/oC
Analog Input Common Mode Voltage Range (VIN+ + VIN-)/2
Differential Mode (Note 2)
INTERNAL VOLTAGE REFERENCE
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
-
3.5
-
V
Total Reference Resistance, RL
-
7.8
-
k
Reference Current
-
450
-
A
DC Bias Voltage Output, VDC
-
2.3
-
V
Max Output Current (Not To Exceed)
-
-
1
mA
2.0
-
-
V
DC BIAS VOLTAGE
DIGITAL INPUTS (CLK)
Input Logic High Voltage, VIH
-
-
0.8
V
Input Logic High Current, IIH
VCLK = 5V
-
-
10.0
A
Input Logic Low Current, IIL
VCLK = 0V
-
-
10.0
A
-
7
-
pF
1.6
-
-
mA
mA
Input Logic Low Voltage, VIL
Input Capacitance, CIN
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, IOL
VO = 0.4V (Note 2)
Output Logic Source Current, IOH
VO = 2.4V (Note 2)
DVCC3 = 3.0V, VO = 0.4V
-
1.6
-
-0.2
-
-
mA
-
-0.2
-
mA
-
5
-
pF
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
ps (RMS)
Data Output Delay, tOD
-
8
-
ns
Data Output Hold, t H
-
8
-
ns
-
-
3
Cycles
DVCC3 = 3.0V, VO = 2.4V
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Latency, tLAT
For a Valid Sample (Note 2)
Clock Pulse Width (Low)
5MSPS Clock
90
100
110
ns
Clock Pulse Width (High)
5MSPS Clock
90
100
110
ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, ICC
VIN+ - VIN- = 2V
-
60
70
mA
Analog Supply Current, AICC
VIN+ - VIN- = 2V
-
46
-
mA
Digital Supply Current, DICC1
VIN+ - VIN- = 2V
-
13
-
mA
Output Supply Current, DICC2
VIN+ - VIN- = 2V
-
1
-
mA
Power Dissipation
VIN+ - VIN- = 2V
-
300
350
mW
Offset Error PSRR, VOS
AVCC or DVCC = 5V 5%
-
2
-
LSB
Gain Error PSRR, FSE
AVCC or DVCC = 5V5%
-
30
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
FN3984 Rev 7.00
March 31, 2005
Page 4 of 12
HI5805
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN-1
HN - 1
SN
HN
S N + 1 HN + 1
SN + 2
HN + 2
S N + 3 HN + 3
SN+4
HN + 4
SN + 5
H N + 5 SN + 6
HN + 6
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B2, N - 2
3RD
STAGE
4TH
STAGE
B1, N
B2, N - 1
B3, N - 2
B4, N - 3
DATA
OUTPUT
B1, N + 1
B2, N
B3, N - 1
B4, N - 2
DN - 3
B1, N + 2
B2, N + 1
B3, N
B4, N - 1
DN - 2
B2, N + 2
B3, N + 1
B4, N
DN - 1
B1, N + 3
B2, N + 3
B3, N + 2
B4, N + 1
DN
B4, N + 2
DN + 1
B1, N + 4
B1, N + 5
B2, N + 4
B3, N + 3
B3, N + 4
B4, N + 3
DN + 2
DN + 3
tLAT
NOTES:
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM, N : M-th stage digital output corresponding to N-th sampled input.
7. DN : Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
DATA
OUTPUT
2.0V
DATA N - 1
DATA N
0.8V
FIGURE 2. INPUT-TO-OUTPUT TIMING
FN3984 Rev 7.00
March 31, 2005
Page 5 of 12
HI5805
Typical Performance Curves
11
70
fS = 5MSPS
fS = 5MSPS
10
TEMPERATURE = 25oC
TEMPERATURE = 25oC
60
SINAD (dB)
ENOB
9
8
50
7
40
6
30
5
10
INPUT FREQUENCY (MHz)
1
100
FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD) vs
INPUT FREQUENCY
70
-40
fS = 5MSPS
fS = 5MSPS
TEMPERATURE = 25oC
TEMPERATURE = 25oC
-50
THD (dBc)
SNR (dB)
60
50
40
-60
-70
1
10
-80
100
10
1
INPUT FREQUENCY (MHz)
100
INPUT FREQUENCY (MHz)
FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT
FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT
FREQUENCY
80
11
fS = 5MSPS
2MHz
1MHz
TEMPERATURE = 25oC
10
5MHz
70
9
ENOB
SFDR (dBc)
100
INPUT FREQUENCY (MHz)
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT
FREQUENCY
30
10
1
60
8
7
50
10MHz
fS = 5MSPS
TEMPERATURE = 25oC
20MHz
50MHz
6
100MHz
40
1
10
100
INPUT FREQUENCY (MHz)
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs
INPUT FREQUENCY
FN3984 Rev 7.00
March 31, 2005
5
0.4
0.5
DUTY CYCLE (tCLK-LOW /tCLK)
0.6
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK
DUTY CYCLE AND INPUT FREQUENCY
Page 6 of 12
HI5805
Typical Performance Curves
(Continued)
3.525
11
2MHz
1MHz
10
9
VREFNOM
10MHz
VROUT (V)
ENOB
3.515
5MHz
20MHz
8
fS = 5MSPS
7
3.505
3.495
VREFLD
50MHz
3.485
6
100MHz
5
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE AND INPUT FREQUENCY
3.475
-40
-20
0
20
40
TEMPERATURE (oC)
60
80
FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT
(VROUT) vs TEMPERATURE AND LOAD
306
70
304
CURRENT (mA)
POWER DISSIPATION (mW)
ITOT
60
fS = 5MSPS
VIN+ = VIN- = VDC
302
300
50
40
AICC
fS = 5MSPS
VIN+ = VIN- = VDC
30
20
DICC1
298
10
DICC2
296
-40
-20
0
20
40
TEMPERATURE (oC)
60
FIGURE 11. POWER DISSIPATION vs TEMPERATURE
0
0
-40
80
-20
0
20
40
TEMPERATURE (oC)
60
80
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
fIN = 1MHz, fS = 5MSPS
OUTPUT LEVEL (dB)
-20
-40
-60
-80
-100
-120
200
400
600
FREQUENCY BIN
800
1000
FIGURE 13. 2048 POINT FFT SPECTRAL PLOT
FN3984 Rev 7.00
March 31, 2005
Page 7 of 12
HI5805
Pin Descriptions
PIN NO.
NAME
1
CLK
DESCRIPTION
2
DVCC1
Digital Supply (5.0V).
3
DGND1
Digital Ground.
4
DVCC1
Digital Supply (5.0V).
5
DGND1
Digital Ground
6
AVCC
Analog Supply (5.0V).
7
AGND
Analog Ground.
8
VIN+
Positive Analog Input.
9
VIN-
Negative Analog Input.
10
VDC
DC Bias Voltage Output.
11
VROUT
12
VRIN
Reference Voltage Input.
13
AGND
Analog Ground.
14
AVCC
Analog Supply (5.0V).
15
D11
16
D10
Data Bit 10 Output.
17
D9
Data Bit 9 Output.
18
D8
Data Bit 8 Output.
19
D7
Data Bit 7 Output.
20
D6
21
DGND2
Digital Output Ground.
22
DVCC2
Digital Output Supply (3.0V to 5.0V).
23
D5
Data Bit 5 Output.
24
D4
Data Bit 4 Output.
25
D3
Data Bit 3 Output.
26
D2
Data Bit 2 Output.
27
D1
Data Bit 1 Output.
28
D0
Data Bit 0 Output (LSB).
Input Clock.
Reference Voltage Output.
Data Bit 11 Output (MSB).
Data Bit 6 Output.
Detailed Description
Theory of Operation
The HI5805 is a 12-bit, fully-differential, sampling pipeline A/D
converter with digital error correction. Figure 14 depicts the
circuit for the front end differential-in-differential-out sample-andhold (S/H). The switches are controlled by an internal clock
which is a non-overlapping two phase signal, f1 and f2 , derived
from the master clock. During the sampling phase, f1 , the input
signal is applied to the sampling capacitors, CS . At the same
time the holding capacitors, CH , are discharged to analog
ground. At the falling edge of f1 the input signal is sampled on
the bottom plates of the sampling capacitors. In the next clock
phase, f2 , the two bottom plates of the sampling capacitors are
connected together and the holding capacitors are switched to
the op-amp output nodes. The charge then redistributes
between CS and CH completing one sample-and-hold cycle.
The output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
FN3984 Rev 7.00
March 31, 2005
CS . The relatively small values of these components result in a
typical full power input bandwidth of 100MHz for the converter.
1
VIN +
1
1
1
CS
VOUT +
-+
+-
2
VIN -
CH
VOUT -
CS
1
CH
1
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock signal
is offset by 180 degrees from the previous stage clock signal,
with the result that alternate stages in the pipeline will
perform the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant bits
to form the final 12-bit output for the converter.
Because of the pipeline nature of this converter, the data on the
bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency. After
the data latency time, the data representing each succeeding
sample is output at the following clock pulse. The output data is
synchronized to the external clock by a latch. The digital outputs
are in offset binary format (See Table 1).
Internal Reference Generator, VROUT and VRIN
The HI5805 has an internal reference generator, therefore, no
external reference voltage is required. VROUT must be
connected to VRIN when using the internal reference voltage.
The HI5805 can be used with an external reference. The
converter requires only one external reference voltage
connected to the VRIN pin with VROUT left open.
The HI5805 is tested with VRIN equal to 3.5V. Internal to the
converter, two reference voltages of 1.3V and 3.3V are
generated for a fully differential input signal range of 2V.
In order to minimize overall converter noise, it is recommended
that adequate high frequency decoupling be provided at the
reference voltage input pin, VRIN .
Page 8 of 12
HI5805
TABLE 1.
CODE CENTER
DESCRIPTION
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL
INPUT VOLTAGE†
(USING INTERNAL
REFERENCE)
MSB
LSB
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale (+FS) - 1/4 LSB
+1.99976V
1
1
1
1
1
1
1
1
1
1
1
1
+FS - 11/4 LSB
1.99878V
1
1
1
1
1
1
1
1
1
1
1
0
+ 3/4 LSB
732.4V
1
0
0
0
0
0
0
0
0
0
0
0
- 1/4 LSB
-244.1V
0
1
1
1
1
1
1
1
1
1
1
1
-FS + 13/4 LSB
-1.99829V
0
0
0
0
0
0
0
0
0
0
0
1
-Full Scale (-FS) + 3/4 LSB
-1.99927V
0
0
0
0
0
0
0
0
0
0
0
0
† The voltages listed above represent the ideal center of each offset binary output code shown.
Analog Input, Differential Connection
The analog input to the HI5805 can be configured in various
ways depending on the signal source and the required level of
performance. A fully differential connection (Figure 15) will give
the best performance for the converter.
VIN
VIN+
HI5805
scale, all 1s digital data output code, when the VIN+ input is
at VDC +1V and the VIN- input is at VDC -1V (VIN+ - VIN- =
2V). Conversely, the ADC will be at negative full scale, all 0s
digital data output code, when the VIN+ input is equal to VDC 1V and VIN- is at VDC +1V (VIN+ - VIN- = -2V). From this, the
converter is seen to have a peak-to-peak differential analog
input voltage range of 2V.
The analog input can be DC coupled (Figure 16) as long as the
inputs are within the analog input common mode voltage range
(1.0V VDC 4.0V).
VDC
VIN
-VIN
VIN-
VIN+
VDC
R
FIGURE 15. AC COUPLED DIFFERENTIAL INPUT
Since the HI5805 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
common mode voltage range of 1.0V to 4.0V. The
performance of the ADC does not change significantly with the
value of the analog input common mode voltage.
A 2.3V DC bias voltage source, VDC , half way between the top
and bottom internal reference voltages, is made available to
the user to help simplify circuit design when using a differential
input. This low output impedance voltage source is not
designed to be a reference but makes an excellent bias source
and stays within the analog input common mode voltage range
over temperature.
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input,
(Figure 15), if VIN is a 2VP-P sinewave with -VIN being 180
degrees out of phase with VIN , then VIN+ is a 2VP-P
sinewave riding on a DC bias voltage equal to VDC and VINis a 2VP-P sinewave riding on a DC bias voltage equal to
VDC . Consequently, the converter will be at positive full
FN3984 Rev 7.00
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C
HI5805
VDC
-VIN
VDC
R
VIN-
FIGURE 16. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 16 are not absolutely necessary but
may be used as load setting resistors. A capacitor, C,
connected from VIN+ to VIN- will help filter any high frequency
noise on the inputs, also improving performance. Values
around 20pF are sufficient and can be used on AC coupled
inputs as well. Note, however, that the value of capacitor C
chosen must take into account the highest frequency
component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 17 may be used with a
single ended AC coupled input. Sufficient headroom must be
provided such that the input voltage never goes above +5V or
below AGND .
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HI5805
VIN+
VIN
HI5805
VDC
VIN-
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
Again, the difference between the two internal voltage
references is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a
4VP-P sinewave riding on a positive voltage equal to VDC. The
converter will be at positive full scale when VIN+ is at VDC +
2V (VIN+ - VIN- = 2V) and will be at negative full scale when
VIN+ is equal to VDC - 2V (VIN+ - VIN- = -2V). In this case,
VDC could range between 2V and 3V without a significant
change in ADC performance. The simplest way to produce
VDC is to use the VDC bias voltage output of the HI5805.
The single ended analog input can be DC coupled (Figure 18)
as long as the input is within the analog input common mode
voltage range.
VIN
VIN+
VDC
R
HI5805
C
supply. When driving CMOS logic, the digital outputs will swing
to the rails. When driving standard TTL loads, the digital
outputs will meet standard TTL level requirements even with a
3.0V supply.
In order to ensure rated performance of the HI5805, the duty
cycle of the clock should be held at 50% 5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5805 will only be guaranteed at
conversion rates above 0.5MSPS. This ensures proper
performance of the internal dynamic circuits.
Supply and Ground Considerations
The HI5805 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
part should be mounted on a board that provides separate low
impedance connections for the analog and digital supplies and
grounds. For best performance, the supplies to the HI5805
should be driven by clean, linear regulated supplies. The board
should also have good high frequency decoupling capacitors
mounted as close as possible to the converter. If the part is
powered off a single supply then the analog supply and ground
pins should be isolated by ferrite beads from the digital supply
and ground pins.
Refer to the Application Note AN9214, “Using Intersil High
Speed A/D Converters” for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
VDC
VIN -
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
The midscale code transition should occur at a level 1/4 LSB
above half scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from VIN+ to VIN- will help filter any high frequency
noise on the inputs, also improving performance. Values
around 20pF are sufficient and can be used on AC coupled
inputs as well. Note, however, that the value of capacitor C
chosen must take into account the highest frequency
component of the analog input signal.
The last code transition should occur for an analog input that is
3/ LSB below positive full scale with the offset error removed.
4
Full-scale error is defined as the deviation of the actual code
transition from this point.
A single ended source will give better overall system
performance if it is first converted to differential before driving
the HI5805.
Integral Linearity Error (INL)
Digital I/O and Clock Requirements
Power Supply Rejection Ratio (PSRR)
The HI5805 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5805 to be driven by CMOS logic.
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and gain error (in LSBs) is noted.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the ideal
value of 1 LSB.
INL is the worst case deviation of a code center from a best fit
straight line calculated from the measured data.
The digital CMOS outputs have a separate digital supply. This
allows the digital outputs to operate from a 3.0V to 5.0V
FN3984 Rev 7.00
March 31, 2005
Page 10 of 12
HI5805
Dynamic Performance Definitions
Total Harmonic Distortion (THD)
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5805. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full scale for all these tests. SNR and
SINAD are quoted in dB. The distortion numbers are quoted in
dBc (decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
Signal-to-Noise Ratio (SNR)
Intermodulation Distortion (IMD)
SNR is the measured RMS signal to RMS noise at a specified
input and sampling frequency. The noise is the RMS sum of all
of the spectral components except the fundamental and the
first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency, fS/2,
excluding DC.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below fS/2.
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2 , are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2),
(2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each
tone 6dB below full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = SINAD + V CORR -1.76 /6.02,
where: VCORR = 0.5dB.
VCORR adjusts the ENOB for the amount the input is below
fullscale.
FN3984 Rev 7.00
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HI5805
Transient Response
Aperture Delay (tAP)
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Over-Voltage Recovery
Aperture Jitter (tAJ)
Over-voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -fS
to +fS . The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3984 Rev 7.00
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