Datasheet
HIP2103, HIP2104
60V, 1A/2A Peak, Half-Bridge Driver with 4V UVLO
Features
The HIP2103 and HIP2104 are half-bridge drivers
designed for applications using DC motors, 3-phase
brushless DC motors, or other similar loads.
• 60V maximum bootstrap supply voltage
• 3.3V and 12V LDOs with dedicated enable pins
(HIP2104)
The two inputs (HI and LI) independently control the
high-side driver (HO) and the low-side driver (LO). HI
and LI can be configured to enable/disable the device,
which lowers the number of connections to a
microcontroller and the cost.
• 5µA sleep mode quiescent current
• VDD undervoltage lockout
• 3.3V or 5V CMOS compatible inputs with hysteresis
The low IDD bias current in the Sleep Mode prevents
battery drain when the device is not in use, which
eliminates the need for an external switch to
disconnect the driver from the battery.
• Integrated bootstrap FET (replaces traditional boot
strap diode)
• HIP2103 is available in 8 Ld SOIC and 3x3mm
TDFN packages
Integrated pull-down resistors on all of the inputs (LI,
HI, VDen, and VCen) reduce the need for external
resistors. An active low resistance pull-down on the
LO output ensures that the low-side bridge FET
remains off during the Sleep Mode or when VDD is
below the Undervoltage Lockout (UVLO) threshold.
• HIP2104 is available in a 4x4mm, 12 Ld DFN
package
• Pb-Free (RoHS Compliant)
Applications
The HIP2104 has a 12V linear regulator and a 3.3V
linear regulator with separate enable pins. The 12V
regulator provides internal bias for VDD and the 3.3V
regulator provides bias for an external microcontroller
(and/or other low voltage ICs), which eliminates the
need for discrete LDOs or DC/DC converters.
VBAT
• Half-bridge, full bridge, and BLDC motor drives
(see Figures 3, 4, 5)
• UPS and inverters
• Class-D amplifiers
• Any switch mode power circuit requiring a
half-bridge driver
VBAT
5.5
VBAT
VDen
VCen
5.0
VCC
HB
VDD
VDD
HO
HI
HO
HI
HIP2104
HS
LI
LO
µController
VSS
DC
Motor
HS
HIP2103
LO
LI
VDD
4.5
IBAT (µA)
HB
4.0
3.5
3.0
VSS
EPAD
EPAD
VCen = VDen = 0
2.5
2.0
10
20
30
40
50
VBAT (VDC)
Figure 1. Typical Full Bridge Application
FN8276 Rev.2.0
Feb 25, 2021
Figure 2. HIP2104 Shutdown Current vs VBAT
Page 1 of 30
© 2013 Renesas Electronics
HIP2103, HIP2104
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
2.
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
3.
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
3.4
3.5
3.6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.
Typical Perfomance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
5.4
6.
HIP2104 LDOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
19
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Transients on the HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.
General PCB Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.
General EPAD Heatsinking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FN8276 Rev.2.0
Feb 25, 2021
Page 2 of 30
HIP2103, HIP2104
1.
1.1
1. Overview
Overview
Typical Applications
VBATT
VBAT
VDen
VCen
VBATT
VCC
HB
VDD
HIP2104
HI
µController
DC
Motor
HO
HS
50Vmax
EPAD
LO
LI
VSS
Figure 3. Half-Bridge Motor Drive Topology
VBATT
VBATT
VBAT
VDen
VCen
VDD
VCC
HB
HB
VDD
VDD
VDD
HIP2104
HO
HO
HI
HS
LI
µController
DC
Motor
LO
VSS
HIP2103
HS
HI
LI
LO
VSS
EPAD
EPAD
Figure 4. Full Bridge Motor Driver Topology
FN8276 Rev.2.0
Feb 25, 2021
Page 3 of 30
HIP2103, HIP2104
1. Overview
VBATT
VBATT
HB
VDD
VDD
VBAT
VDen
HO
VCen
HIP2103
HS
VCC
LI
HB
VDD
BLDC
Motor
HIP2104
HO
HI
LO
VSS
EPAD
HS
LI
µController
HI
LO
HB
VSS
VDD
HO
HIP2103
EPAD
HS
HI
LI
LO
VSS
EPAD
Figure 5. BLDC (3-Phase) Motor Drive Topology
FN8276 Rev.2.0
Feb 25, 2021
Page 4 of 30
HIP2103, HIP2104
1.2
1. Overview
Block Diagram
VBAT
VDD
VCC
3.3V LDO
155C
OTP
12V LDO
1ms
Delay
VCen
1ms
Delay
VDen
100k
100K
See Figures 6 and 7 for
Sleep Mode Timing Details
VDD
HB
Boot FET
VDD UVLO
20µs
Delay
R
Q
Sleep
Mode
20µs
Delay
S
2M
Level Shift
HI
HO
Boot UVLO
100k
EPAD
Input Lockout
Logic Prevents
Shoot-Through
when LI and HI
are Both High
HS
VDD
LO
LI
Active pull-down 100
keeps bridge FET
off during VDD
UVLO, OTP, or
sleep
100k
VSS
HIP2103
FN8276 Rev.2.0
Feb 25, 2021
HIP2104
Page 5 of 30
HIP2103, HIP2104
1.3
1. Overview
Ordering Information
Part Number
(Notes 2, 3, 4)
Part
Marking
UVLO (V)
VCC
Regulator
(V)
VDD
Regulator
(V)
Tape and Reel
(Units) (Notes 1)
Package
(RoHS Compliant)
Pkg.
Dwg. #
HIP2103FRTAAZ
DZBF
4.0
N/A
N/A
-
8 Ld 3x3 TDFN
L8.3x3A
HIP2103FRTAAZ-T
DZBF
4.0
N/A
N/A
6k
8 Ld 3x3 TDFN
L8.3x3A
HIP2103FRTAAZ-T7A
DZBF
4.0
N/A
N/A
250
8 Ld 3x3 TDFN
L8.3x3A
HIP2103FBZ-T
2103 FBZ
4.0
N/A
N/A
6k
8 Ld SOIC
M8.15
HIP2103FBZ-T7A
2103 FBZ
4.0
N/A
N/A
250
8 Ld SOIC
M8.15
HIP2104FRAANZ
2104AN
4.0
3.3
12
-
12 Ld 4x4 DFN
L12.4x4A
HIP2104FRAANZ-T
2104AN
4.0
3.3
12
6k
12 Ld 4x4 DFN
L12.4x4A
HIP2104FRAANZ-T7A
2104AN
4.0
3.3
12
250
12 Ld 4x4 DFN
L12.4x4A
HIP2103-4DEMO1Z
HIP2103, HIP2104 3-phase, Full, or Half Bridge Motor Drive Demonstration Board
HIP2103-4DEMO2Z
Demonstration Board 3-Phase Module with HIP2103, HIP2104 Drivers
HIP2104DBEVAL1Z
HIP2104 Evaluation Board (Daughter Board)
HIP2103DBEVAL1Z
HIP2103 Evaluation Board (Daughter Board)
HIP2103_4MBEVAL1Z
HIP2103, HIP2104 Evaluation Board (Mother Board)
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the HIP2103 and HIP2104 device pages. For more information about MSL, see TB363.
4. All part numbers are rated -40°C to +125°C for the recommended operating junction temperature range.
FN8276 Rev.2.0
Feb 25, 2021
Page 6 of 30
HIP2103, HIP2104
2.
2. Pin Information
Pin Information
2.1
Pin Assignments
HIP2104
(12 Ld 4x4 DFN)
Top View
HIP2103
(8 Ld 3x3 TDFN)
Top View
VDD
1
HI
2
LI
3
VSS
4
EPAD
(VSS)
8
HB
VDen
1
12
VBAT
7
HO
VCen
2
11
HB
6
HS
VCC
3
10
HO
5
LO
VDD
4
9
HS
HI
5
8
LO
LI
6
7
VSS
(8 Ld SOIC)
Top View
2.2
VDD
1
8
HB
HI
2
7
HO
LI
3
6
HS
VSS
4
5
LO
EPAD
(VSS)
Pin Descriptions
HIP2103
HIP2104
8 Ld 8 Ld
TDFN SOIC
12 Ld
DFN
Symbol
Description
-
-
1
VDen
HIP2104 only. Enable input for the VDD linear regulator, 3.3V or 5V logic compatible, VBAT tolerant.
VDD output is turned on after 1ms debouncing period.
-
-
2
VCen
HIP2104 only. Enable input for the VCC linear regulator, 3.3V or 5V logic compatible, VBAT tolerant.
VCC output is turned on after 1ms debouncing period.
-
-
3
VCC
HIP2104 only. 3.3V/75mA output voltage of linear regulator. Enabled by VCen.
1
1
4
VDD
HIP2103: Driver supply voltage, 4.5V to 14V.
HIP2104: 12V/75mA output voltage of linear regulator and driver supply voltage. Enabled by VDen.
2
2
5
HI
High side input, 3.3V or 5V logic compatible. Internal 100kΩ pull-down resistor on the HI pin pulls HI to
logic 0 when floating.
3
3
6
LI
Low side input, 3.3V or 5V logic compatible. Internal 100kΩ pull-down resistor on the LI pin pulls LI to
logic 0 when floating.
4
4
7
VSS
5
5
8
LO
Low-side driver output. Connect to the lower NFET gate.
6
6
9
HS
High-side NFET source connection. Connect the bootstrap capacitor from HB to this pin.
7
7
10
HO
High-side driver output. Connect to the upper NFET gate.
8
8
11
HB
High-side Boot capacitor. Connect bootstrap capacitor from HS to this pin.
-
-
12
VBAT
(HIP2104 only) positive battery (bridge voltage) connection.
EP
-
EP
EPAD
Exposed pad. Connect EPAD to VSS. Renesas recommends connecting the EPAD to a low thermal
impedance on the PCB for optimum thermal performance.
FN8276 Rev.2.0
Feb 25, 2021
Signal ground.
Page 7 of 30
HIP2103, HIP2104
3.
3.1
3. Specifications
Specifications
Absolute Maximum Ratings
Parameter (Note 5)
Minimum
Maximum
Unit
Supply Voltage VDD (HIP2103 only)
-0.3
16
V
Bridge Supply Voltage VBAT (HIP2104 Only)
-0.3
60
V
High side Bias Voltage (VHB - VHS) (Note 12)
-0.3
16
V
Logic Inputs VCen, VDen (HIP2104 Only)
- 0.3
VBAT + 0.3
V
Logic Inputs LI, HI
- 0.3
VDD + 0.3
V
Output Voltage LO
- 0.3
VDD + 0.3
V
Output Voltage HO
VHS - 0.3
VHB + 0.3
V
-10
60
V
VHS - 0.3
66
V
Average Current in Boot Diode (Note 6)
100
mA
Maximum Boot Capacitor Value
10
µF
Average Output Current in HO and LO (Note 6)
200
mA
Voltage on HS (Note 12)
Voltage on HB
ESD Rating
Value
Unit
Human Body Model Class 2 (Tested per JESD22-A114E)
2
kV
Charged Device Model Class IV
1
kV
100
mA
Latch-Up (Tested per JESD-78B; Class 2, Level A) all pins
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
Notes:
5. All voltages are referenced toVSS unless otherwise specified.
6. When driving a power MOSFET or similar capacitive load, the average output current is the average of the rectified output current. The
peak output currents of this driver are self limiting by trans conductance or rDS(ON) and do not require any external components to minimize
the peaks. If the output is driving a non-capacitive load, such as an LED, the maximum output current must be limited by external means
to less than the specified recommended rectified average output current.
3.2
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
8 Ld DFN Package (Notes 7, 10)
46
7
12 Ld TDFN Package (Notes 7, 10)
44
7
8 Ld SOIC Package (Notes 8, 9)
105
55
Notes:
7. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See
TB379.
8. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
9. For θJC, the case temperature location is taken at the package top center.
10. For θJC, the case temperature location is the center of the exposed metal pad on the package underside.
11. The maximum value of VHS must be limited so that VHB does not exceed 60V.
12. If the duration of the negative voltage is significant with respect to the time constant to charge the boot capacitor (across HB and HS) the
voltage on the boot capacitor can charge as high as VDD - (-VHS) = (VDD +VHS) potentially violating the Voltage Rating for (VHB - VHS).
13. When VBAT < ~13V, the output of VDD sags. The 5V minimum specified for VBAT is the minimum level for which the UVLO does not
activate.
FN8276 Rev.2.0
Feb 25, 2021
Page 8 of 30
HIP2103, HIP2104
3. Specifications
Parameter
Minimum
Maximum
Unit
8 Ld DFN Package
2.2
W
12 Ld TDFN Package
2.3
W
8 Ld SOIC Package
0.95
W
8 Ld DFN Package
14.3
W
12 Ld TDFN Package
14.3
W
°C
Max Power Dissipation at +25°C in Free Air
Max Power Dissipation at +25°C on Copper Plane
Storage Temperature Range
-65
+150
Maximum Operating Junction Temperature Range
-40
+150
Nominal Over-Temperature Shutdown
Over Temperature Shut-down Range
+145
Pb-Free Reflow Profile
3.3
+155
°C
+165
°C
see TB493
Recommended Operating Conditions
Parameter (Note 5)
Minimum
Maximum
Unit
Junction Temperature
-40
+125
°C
Supply Voltage, VBAT (HIP2104 only) (Note 13)
5.0
50
V
Supply Voltage, VDD
4.5
14
V
High Side Bias Voltage (VHB - VHS) (Note 12)
-0.3
14
V
Voltage on HS, Transient, VHS (Notes 11, 12)
-10
50
V
VHS - 0.3V
60
V
40
V
0
VBAT
V
Output Voltage (LO)
GND
VDD
V
Output Voltage (HO)
VHS
VHB
V
0
150
mA
Voltage on HB
Voltage on HS, Continuous
Logic Inputs VCen, VDen (HIP2104 only)
Average Output Current in HO and LO (Note 6)
3.4
DC Electrical Specifications
VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified.
Boldface limits apply across the operating junction temperature range, -40°C to +125°C.
TJ = +25°C
Parameters
Symbol
Test Conditions
TJ = -40°C to +125°C
Min
Max
(Note 14) (Note 14) Unit
Min
Typ
Max
-2.5
+2.1
+4.8
-5
+5
%
83
151
237
80
245
mA
0.06
0.7
V
Linear Bias Supplies (HIP2104 Only)
VDD Output Voltage Over Rated Line,
Load, and Temperature
VDD12 Nominal VDD = 12V
VDD Output Current Limit (Brick Wall)
IDD12
VDD Drop Output Voltage (Figure 10)
VDdout Load = 75mA
VCC Output Voltage Over Rated Line,
Load, and Temperature
VCC3.3 Nominal VCC = 3.3V
VCC Output Current Limit (Brick Wall)
VCC Drop Output Voltage (Figure 11)
ICC
VCdout Load = 75mA
-3.9
+1.8
+4.3
-5
+5
%
83
149
237
80
245
mA
0.5
0.9
V
Bias Currents
FN8276 Rev.2.0
Feb 25, 2021
Page 9 of 30
HIP2103, HIP2104
3. Specifications
VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified.
Boldface limits apply across the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
Parameters
VDD Sleep Mode Current (HIP2103)
Symbol
IDDS
Test Conditions
HI = LI = 1, after 10 to 30µs delay
Min
Typ
Max
TJ = -40°C to +125°C
Min
Max
(Note 14) (Note 14) Unit
9.4
20
µA
VBAT Shutdown Current (HIP2104)
IDDSbatt VCen = VDen = 0, after 10 to 30µs
delay, VBAT = 50V
4.8
15
µA
VBAT (HIP2104) or VDD (HIP2103)
Operating Current
IDDO20 f = 20kHz, HI = LI = 50% square wave
VDD = 12V for HIP2103
832
1040
µA
IDDO10 f = 10kHz, HI = LI = 50% square wave
VDD = 12V for HIP2103
661
825
µA
135
160
µA
IHBS20K LI = 0, HI = 50% square wave 20kHz,
VHS = 0V, VHB = 12V
206
245
µA
IHBS10K LI = 0, HI = 50% square wave 10kHz,
VHS = 0V, VHB = 12V
167
193
µA
IHB20K LI = 0, HI = 50% square wave 20kHz,
VHB = 60V, VHS = 50V
201
240
µA
IHB10K LI = 0, HI = 50% square wave 10kHz,
VHB = 60V, VHS = 50V
164
190
µA
HB to HS Quiescent Current
HB to HS Operating Current
HB to VSS Operating Current
IHBQ
HI = 1, LO = 0, VHS = 0V, VHB = 12V
HB to VSS Quiescent Current
IHBQ
LI = HI = 0V; VHB = 60V, VHS = 50V
120
145
µA
HS to VSS Current, Sleep Mode
IHBS
LI = HI = 1; HB open, VHS = 50V
0.03
+1
µA
VDD = 12V
1.44
1.18
1.63
V
Input Pins
Low Level Input Voltage Threshold
VIL
High Level Input Voltage Threshold
VIH
2.06
1.73
2.4
V
Input Voltage Hysteresis
VHys
0.62
0.48
0.85
V
1.13
0.9
1.25
V
Low Level Input Voltage Threshold
VIL
High Level Input Voltage Threshold
VIH
1.63
1.38
1.84
V
Input Voltage Hysteresis
VHys
0.50
0.36
0.63
V
RI
100
80
130
kΩ
VDD Falling Threshold
VUVF
4.2
3.98
4.36
V
VDD Threshold Hysteresis
VUVH
0.34
0.267
0.37
V
8.2
2.42
15
Ω
Input Pull-Down
VDD = 5V
Undervoltage Lockout (Note 15)
Boot FET
On Resistance
RDon
IVDD-HB = 100mA, HI = 0, LI = 1
LO Gate Driver
Sinking rDS(ON)
RDSLOL ILO = 100mA, LI = 0
2.68
0.61
11
Ω
Sourcing rDS(ON)
RDSLOH ILO = -75mA, HI = 1
6.47
2.3
15
Ω
Peak Pull-Up Current
Peak Pull-Down Current
FN8276 Rev.2.0
Feb 25, 2021
ILOH12 HI = 1 VDD = 12V, CLOAD = 1000pF
ILOH5
HI = 1 VDD = 5V, CLOAD = 1000pF
(HIP2103 only)
ILOL12
HI = 0 VDD = 12V, CLOAD = 1000pF
ILOL5
HI = 0 VDD = 5V, CLOAD = 1000pF
(HIP2103 only)
1
A
A
2
A
A
Page 10 of 30
HIP2103, HIP2104
3. Specifications
VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO and LO unless otherwise specified.
Boldface limits apply across the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
Parameters
Symbol
Test Conditions
Min
Typ
Max
TJ = -40°C to +125°C
Min
Max
(Note 14) (Note 14) Unit
HO Gate Driver
Sinking rDS(ON)
RDSHOL IHO = 100mA, HI = 0
2.68
0.61
11
Ω
Sourcing rDS(ON)
RDSHOH IHO = -100mA, HI = 1
6.47
2.3
15
Ω
Peak Pull-Up Current
IHOH12 HI = 1 VDD = 12V, CLOAD = 1000pF
IHOH5
Peak Pull-Down Current
HI = 1 VDD = 5V, CLOAD = 1000pF
(HIP2103 only)
IHOL12 HI = 0 VDD = 12V, CLOAD = 1000pF
IHOL5
1
A
1
A
2
A
HI = 0 VDD = 5V, CLOAD = 1000pF
(HIP2103 only)
A
Notes:
14. Parameters with Min and/or Max limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
15. The UV lockout does not disable the VDD and VCC outputs.
3.5
AC Electrical Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. VDD load = 1µF and VCC load = 1µF (HIP2104 only)
Boldface limits apply across the operating junction temperature range, -40°C to +125°C.
TJ = +25°C
Parameters
Symbol
Test Conditions
Min
Typ
Max
TJ = -40°C to +125°C
Min
Max
Unit
VDen and VCen Turn-On Delay
(Figure 8) (HIP2104 only)
tVDen
tVCen
VDen = VCen = 1,
VCC = VDD = 10%,
VBAT = 50V
1.69
1.0
2.5
ms
VDen and VCen Turn-on Delay
(Figure 8) (HIP2104 only)
tVDen
tVCen
VDen = VCen = 1,
VCC = VDD = 10%,
VBAT = 18V
1.68
1.1
2.54
ms
VDen and VCen Turn-on Delay Matching
(Figure 8) (VDen - VCen) (HIP2104 only)
tVenM
VDen = VCen = 1,
VCC = 10%, VDD = 10%
VBAT = 50V
40
-290
340
ns
VDen and VCen Turn-on Delay Matching
(Figure 8) (VDen - VCen) (HIP2104 only)
tVenM
VDen = VCen = 1,
VCC = 10%, VDD = 10%
VBAT = 18V
40
-290
350
ns
LO Turn-Off Propagation Delay
(LI to LO falling) (Figure 9)
tFL12
HI = 0, LI = 1 to 0
VDD = 12V
27
13
39
ns
tFL5
HI = 0, LI = 1 to 0
VDD = 5V (HIP2103 only)
30
23
46
ns
tFH12
LI = 0, HI = 1 to 0
VDD = 12V
23
10
35
ns
tFH5
LI = 0, HI = 1 to 0
Vv = 5V (HIP2103 only)
27
19
38
ns
tRL12
HI = 0, LI = 0 to 1
VDD = 12V
21
7
32
ns
tRL5
HI = 0, LI = 0 to 1
VDD = 5V (HIP2103 only)
25
12
37
ns
tRH12
LI = 0, HI = 0 to 1
VDD = 12V
23
9
35
ns
tRH5
LI = 0, HI = 0 to 1
VDD = 5V (HIP2103 only)
28
15
40
ns
HO Turn-Off Propagation Delay
(HI to HO falling) (Figure 9)
LO Turn-On Propagation Delay
(LI to LO rising) (Figure 9)
HO Turn-On Propagation Delay
(HI to HO rising) (Figure 9)
FN8276 Rev.2.0
Feb 25, 2021
Page 11 of 30
HIP2103, HIP2104
3. Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. VDD load = 1µF and VCC load = 1µF (HIP2104 only)
Boldface limits apply across the operating junction temperature range, -40°C to +125°C. (Continued)
TJ = +25°C
Parameters
Symbol
Test Conditions
Min
Typ
Max
TJ = -40°C to +125°C
Min
Max
Unit
Turn-On/Off Propagation Mismatch
(HO rising to LO falling) (Figure 9)
tMONHL
LI = 1 -> 0
HI = 0 -> 1
-2.5
-8
+3
ns
Turn-On/Off Propagation Mismatch
(LO rising to HO falling) (Figure 9)
tMONLH
HI = 1 -> 0
LI = 0 -> 1
-4.2
-9.0
+5.4
ns
LO Output Rise Time (10% to 90%)
tR12
CL = 1nF
VDD = 12V
20.5
7
35
ns
tR5
CL = 1nF
VDD = 5V (HIP2103 only)
19.5
6
32
ns
tR12
CL = 1nF
VDD = 12V
21
8
35
ns
tR5
CL = 1nF
VDD = 5V (HIP2103 only)
21
8
34
ns
tF12
CL = 1nF
VDD = 12V
17
3
30
ns
tF5
CL = 1nF
VDD = 5V (HIP2103 only)
17
3
30
ns
tF12
CL = 1nF
VDD = 12V
16
2
30
ns
tF5
CL = 1nF
VDD = 5V (HIP2103 only)
16
1.5
29
ns
HO Output Rise Time (10% to 90%)
LO Output Fall Time (90% to 10%)
HO Output Fall Time (90% to 10%)
Time Delay to Set Sleep Mode
(Note 16, Figure 7)
tSlpS
HI = LI = 0 -> 1
17
9
27
µs
Time Delay to Reset Sleep Mode
(Note 16, Figure 7)
tSlpR
HI = 0, LI = 0 -> 1
17
9
27
µs
Note:
16. When HI and LI are on simultaneously, HO and LO are never on simultaneously. This feature is intended to initiate sleep. This feature
cannot be used to prevent shoot-through for normal alternating switching between LI and HI. Dead time must be provided when
HI = 0 -> LI = 1, or LI = 0 -> HI = 1. See Timing Diagrams (Figure 7 on page 13).
FN8276 Rev.2.0
Feb 25, 2021
Page 12 of 30
HIP2103, HIP2104
Timing Diagrams
HI = 0
HI = 0
LI = 1
LI = 1
*S LEE P
tSlpR
tSlpS
UVL O
~
~
~
~
UVL O
*S LEE P
~
~
3.6
3. Specifications
UV threshol d
V DD
~
~
V DD
tVD e n
V Den
~
~
V Den
V CC
~
~
V CC
V Cen
V Cen
tVC e n
Figure 6. VDD Power-On/Off Timing for Sleep Mode
2M:
: to HS
HO
100: to LS
Dead Tim e
P rovid ed By
Control ler
HO
LO
~
~
LO
S LEE P*
~ ~
~ ~
S LEE P*
HI
~
~
HI
LI
LI
20µs
20µs
* S leep mo de i s en abled when HI = LI = 1 for 20µs.
S leep mo de i s cl eared when HI = 0 and LI = 1 for 20µs.
Figure 7. Sleep Mode Enabled or Cleared by HI and LI Inputs
FN8276 Rev.2.0
Feb 25, 2021
Page 13 of 30
HIP2103, HIP2104
3. Specifications
10% VDD
VDD
VDD
10% VCC
VCC
VCC
tVDen
VDen
VDen
VCen
VCen
tVCen
tVenM
Figure 8. VCen and VDen Delay Matching
tFH
tRH
tMONHL
tMONLH
HO
HO
HI
HI
LO
LO
LI
LI
tRL
tFL
Figure 9. Propagation Delays
FN8276 Rev.2.0
Feb 25, 2021
Page 14 of 30
HIP2103, HIP2104
4.
4. Typical Perfomance Graphs
Typical Perfomance Graphs
14
4
12
No Load
160Ω (75mA at 12V)
3
10
44Ω (75mA at 3.3V)
VCC (V)
VDD (V)
No Load
8
6
2
4
1
2
0
20
18
16
14
12
10
8
6
4
2
0
0
6
4
5
Figure 10. VDD Dropout vs VBAT (HIP2104 Only)
2
1
Figure 11. VCC Dropout vs VBAT (HIP2104 Only)
5.5
1.80E-04
5.0
VCEN = VDEN = 1
1.60E-04
4.5
1.40E-04
4.0
IBAT (A)
IBAT (µA)
3
VBAT (V)
VBAT (V)
3.5
1.20E-04
VCEN = 0; VDEN = 1
1.00E-04
3.0
8.00E-05
2.5
2.0
10
20
30
6.00E-05
10
50
40
VCEN = 1; VDEN = 0
15
20
25
30
35
40
45
50
VBAT (V)
VBAT (V)
Figure 13. HIP2104 VBAT Current vs VBAT Voltage
Figure 12. HIP2104 Shutdown Current
(VCEN = VDEN = 0, HS = VBAT)
900
4
Switching, 20kHz
800
700
3
Switching, 10kHz
500
VCC (V)
IBAT (µA)
600
400
2
300
No Load on LO and HO
100
0
1
Switching, 0kHz
200
0
10
20
30
40
50
VBAT (V)
Figure 14. HIP2104 VBAT Operating Current
FN8276 Rev.2.0
Feb 25, 2021
60
0
0
25
50
75
100
125
150
ICC (mA)
Figure 15. HIP2104 VCC Current Limit
Page 15 of 30
HIP2103, HIP2104
4. Typical Perfomance Graphs
10
14
9
12
8
7
8
IDD (µA)
VDD (V)
10
6
6
5
4
4
3
2
2
0
0
50
100
1
150
5
6
7
8
9
Figure 16. HIP2104 VDD Current Limit
Switching, 20kHz
Falling UVLO (V)
600
IDD (µA)
13
14
4.3
700
Switching, 10kHz
500
400
300
Switching, 0kHz
200
4.1
3.9
3.7
100
No Load on LO and HO
5
7
9
3.5
-40
15
13
11
-20
0
VDD (V)
20
40
60
80
100
120
140
Temperature (°C)
Figure 18. HIP2103 Operating Current
Figure 19. HIP2103 and HIP2104 Falling VDD
Undervoltage Lockout Threshold
20
9
18
8
16
7
Sourcing
HO Output Resistance (Ω)
Boot FET Resistance (Ω)
12
4.5
800
14
12
10
8
6
4
6
5
4
Sinking
3
2
1
2
0
11
Figure 17. HIP2103 Sleep Current (HI = LI = 1)
900
0
10
VDD (V)
IDD (mA)
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 20. Boot FET Resistance
FN8276 Rev.2.0
Feb 25, 2021
120
140
0
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 21. HO Output Resistance
Page 16 of 30
HIP2103, HIP2104
4. Typical Perfomance Graphs
9
LO Output Resistance (Ω)
8
Sourcing
7
6
5
4
3
Sinking
2
1
0
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 22. LO Output Resistance
FN8276 Rev.2.0
Feb 25, 2021
Page 17 of 30
HIP2103, HIP2104
5.
5. Functional Description
Functional Description
The HIP2103 has independent control inputs, LI and HI, for each output, LO and HO. There is no logic inversion
for these input/output pairs. To minimize the possibility of shoot-through failures of the bridge FETs caused by
improper LI and HI signals from an external controller, internal logic in the driver prevents both outputs being high
simultaneously. When either input is high, the high input must go low before a high on the other input propagates
to its respective drive output. If both inputs are high simultaneously, both outputs are low. If one input is high,
followed by the other input going high, the internal logic prevents any shoot through. Note that the internal logic
does not prevent shoot-through if the dead time provided by the external controller is not sufficiently long as
required by the turn-on and turn-off times of the bridge FETS.
If both inputs are high simultaneously for longer than 30µs, the driver initiates a Sleep Mode to reduce the bias
current to minimize the battery drain. When in Sleep Mode, the HO output is in a high-impedance state (2MΩ
between HO and HS) and the LO output is held low with an active 100Ω pull-down resistor. The 100Ω pull-down
prevents inadvertent shoot-through resulting from transients on the bridge voltage while both drivers are in Sleep
Mode.
The Undervoltage Lockout (UVLO) on VDD drives HO and LO low when VDD is less than the UV threshold. Sleep
Mode is initiated if UVLO is asserted for longer than 30µs.
The high-side driver bias is established by the boot capacitor connected between HB and HS. The charge on the
boot capacitor is provided by the internal boot FET that is connected between VDD and HB. The current path to
charge the boot capacitor is enabled (boot FET is on) when the drain voltage on the low-side bridge FET (VHO) is
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