HIP2120FRTBZ-T

DATASHEET IGNS NOT RECOMMENDED FOR NEW DES NT EME LAC REP NO RECOMMENDED ter at contact our Technical Support Cen /tsc com rsil. .inte www or 1-888-INTERSIL HIP2120, HIP2121 FN7668 Rev 0.00 December 23, 2011 100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time Control and PWM Input The HIP2120 and HIP2121 are 100V, high frequency, half-bridge MOSFET driver ICs. They are based on the popular ISL2100A and ISL2101A half-bridge drivers. These drivers have a programmable dead-time to insure break-before-make operation between the high-side and low-side drivers. The dead-time is adjustable up to 250ns. A single PWM logic input controls both bridge outputs (HO, LO). An enable pin (EN), when low, drives both outputs to a low state. All logic inputs are VDD tolerant and the HIP2120 has CMOS inputs with hysteresis for superior operation in noisy environments. The HIP2120 has hysteretic inputs with thresholds that are proportional to VDD. The HIP2121 has 3.3V logic/TTL compatible inputs. Two package options are provided. The 10 Ld 4x4 DFN package has standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to comply with 100V conductor spacing per IPC-2221. Features • 9 Ld TDFN “B” Package Compliant with 100V Conductor Spacing Guidelines per IPC-2221 • Break-Before-Make Dead-Time Prevents Shoot-through and is adjustable up to 220ns • Bootstrap Supply Max Voltage to 114VDC • Wide Supply Voltage Range (8V to 14V) • Supply Undervoltage Protection • CMOS Compatible Input Thresholds with Hysteresis (HIP2120) • 1.6/1 Typical Output Pull-up/Pull-down Resistance • On-Chip 1 Bootstrap Diode Applications • Telecom Half-Bridge DC/DC Converters • UPS and Inverters • Motor Drives • Class-D Amplifiers • Forward Converter with Active Clamp Related Literature • FN7670 “HIP2122, HIP2123 100V, 2A Peak, High Frequency Half-Bridge Driver with Delay Timers” 100V max HIP2120/21 VDD HB PWM PWM CONTROLLER HO EN SECONDARY CIRCUITS HS RDT VSS LO EPAD FEEDBACK WITH ISOLATION DEAD-TIME (ns) HALF BRIDGE 200 160 140 120 100 80 60 40 20 8 16 24 32 40 48 56 64 80 RDT (k) FIGURE 1. TYPICAL APPLICATION FN7668 Rev 0.00 December 23, 2011 FIGURE 2. DEAD-TIME vs TIMING RESISTOR Page 1 of 16 HIP2120, HIP2121 Block Diagram VDD HB HIP2120, HIP2121 UNDER VOLTAGE HO LEVEL SHIFT HS HIP2121 HIP2120/21 PWM DELAY RDT UNDER VOLTAGE Optional inversion for future part numbers LO DELAY VSS EN HIP2121 HIP2120/21 EPAD IS ELECTRICALLY ISOLATED EPAD Pin Configurations HIP2120, HIP2121 (9 LD 4X4 TDFN) TOP VIEW HIP2120, HIP2121 (10 LD 4X4 TDFN) TOP VIEW VDD 1 10 LO HB 2 9 VSS HO 3 8 PWM HB 3 HS 4 7 EN HO NC 5 6 RDT HS FN7668 Rev 0.00 December 23, 2011 EPAD 10 LO 1 VDD 9 VSS 8 PWM 4 7 EN 5 6 RDT EPAD Page 2 of 16 HIP2120, HIP2121 Pin Descriptions 10 LD 9 LD SYMBOL DESCRIPTION 1 1 VDD Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS. 2 3 HB High-side bootstrap supply voltage referenced to HS. Connect the positive side of the bootstrap capacitor to this pin. Bootstrap diode is on-chip. 3 4 HO High-side output. Connect to gate of high-side power MOSFET. 4 5 HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 8 8 PWM 7 7 EN Output enable, when low, HO = LO = 0 9 9 VSS Negative voltage supply, which will generally be ground. 10 10 LO Low-side output. Connect to gate of low-side power MOSFET. 5 - NC No Connect. This pin is isolated from all other pins. 6 6 RDT A resistor connected between this pin and VSS adds additional delay time to the falling and rising edges of the PWM input. - - EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. PWM input. For PWM = 1, HO = 1 and LO = 0. For PWM = 0, HO = 0 and LO = 1. Ordering Information PART NUMBER (Notes 1, 2, 4) PART MARKING INPUT TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # HIP2120FRTAZ HIP 2120AZ CMOS -40 +125 10 Ld 4x4 TDFN L10.4x4 HIP2121FRTAZ HIP 2121AZ 3.3V/TTL -40 +125 10 Ld 4x4 TDFN L10.4x4 HIP2120FRTBZ (Note 3) HIP 2120BZ CMOS -40 +125 9 Ld 4x4 TDFN L9.4x4 HIP2121FRTBZ (Note 3) HIP 2121BZ 3.3V/TTL -40 +125 9 Ld 4x4 TDFN L9.4x4 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted for additional spacing. 4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2120, HIP2121. For more information on MSL please see tech brief TB363. FN7668 Rev 0.00 December 23, 2011 Page 3 of 16 HIP2120, HIP2121 Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 L9.4x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 L10.4x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FN7668 Rev 0.00 December 23, 2011 Page 4 of 16 HIP2120, HIP2121 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD, VHB - VHS (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V PWM and EN Input Voltage (Note 6) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . 42 4 9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . 42 4 Max Power Dissipation at +25°C in Free Air 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W 9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Maximum Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS + 8V to VHS + 14V and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - 1V to VDD + 100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .