HIP2211FBZ-T7A

Datasheet HIP2210, HIP2211 100V, 3A Source, 4A Sink, High Frequency Half-Bridge Drivers with HI/LI or Tri-Level PWM Input and Adjustable Dead Time The HIP2210 and HIP2211 are 100V, 3A source, 4A sink high-frequency half-bridge NMOS FET drivers. The HIP2211 features standard HI/LI inputs and is pin-compatible with popular Renesas bridge drivers such as the HIP2101 and ISL2111. The HIP2210 features a tri-level PWM input with programmable dead time. Its wide operating supply range of 6V to 18V and integrated high-side bootstrap diode supports driving the high-side and low-side NMOS in 100V half-bridge applications. These drivers feature strong 3A source, 4A sink drivers with very fast 15ns typical propagation delay and 2ns typical delay matching, making it optimal for high-frequency switching applications. VDD and boot UVLO protects against an undervoltage operation. The tri-level input of the HIP2210 PWM pin controls the high-side and low-side drivers with a single pin. When the PWM input is at logic high, the high-side bridge FET is turned on and the low-side FET is off. When the input is at logic low, the low-side bridge FET is turned on and the high-side FET is turned off. When the input voltage is in the mid-level state, both the high-side and low-side bridge FETs are turned off. The PWM threshold levels are proportional to an external input reference voltage on the VREF pin, allowing PWM operation across a 2.7V to 5.5V logic range. The HIP2210 is offered in a 10 Ld 4x4mm TDFN package. The HIP2211 is offered in 8 Ld SOIC, 8 Ld 4x4mm DFN, and 10 Ld 4x4mm TDFN packages. Features • HIP2211 drop-in replacement for the ISL2111 and HIP2101 8 Ld SOIC, 8 Ld DFN, and 10 Ld TDFN packages • 115VDC bootstrap supply maximum voltage supports 100V on the half-bridge • 3A source and 4A sink gate drivers for NMOS FETs • Fast propagation delay and matching: 15ns typical delay; 2ns typical matching (HIP2211) • Integrated 0.5Ω typical bootstrap diode • Wide 6V to 18V operating voltage range • VDD and boot Undervoltage Lockout (UVLO) • Robust noise tolerance: wide hysteresis at inputs; HS pin tolerates up to -10V continuous • HIP2211: HI/LI inputs 3.3V logic compatible with VDD voltage tolerance • HIP2210: Tri-Level PWM input with logic threshold levels set by external VREF pin from 2.7V to 5.5V • HIP2210: Programmable dead time prevents shoot-through; adjustable from 35ns to 350ns with a single resistor Applications • Telecom half-bridge and full-bridge DC/DC converters • 3-phase BLDC motor driver; H-Bridge motor driver • Two-switch forward and active clamp converters Related Literature For a full list of related documents, visit our website: • Multiphase PWM DC/DC controllers • Class-D amplifiers • HIP2210, HIP2211 device pages 12V 12V 1 VDD VCC 2 PWM DC/DC Controller HI LI 3 5 HIP 2211 6 4 8 7 HB VREF HO HS VOUT LO VSS HB PWM Controller PWM RDT VSS Figure 1. HIP2211 HI/LI Input Bridge Driver Typical Application 100 V HO EN HIP 2211 Pin-to-Pin Compatible with IS L21 11 FN9347 Rev.1.01 Jun.23.20 VDD VCC 100 V HIP 2210 10 Ld DFN HS VOUT LO VSS VSS HIP 2210 PWM Input with Programm ble De ad Tim e Figure 2. HIP2210 PWM Input Bridge Driver Typical Application Page 1 of 27 HIP2210, HIP2211 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 2. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 4 5 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 2.4 2.5 2.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 4.2 5. Gate Drive for NMOS Half-Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 6. HI/LI Input Control (HIP2211 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Input Control (HIP2210 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF Input (HIP2210 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EN Pin (HIP2210 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing HIP2210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Decoupling Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDT and Dead Time Delay (HIP2210 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HO and LO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 18 18 19 20 20 20 20 PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 PCB Layout and EPAD Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8. Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FN9347 Rev.1.01 Jun.23.20 Page 2 of 27 HIP2210, HIP2211 1. 1. Overview Overview 1.1 Block Diagrams VDD HB VDD UVLO HB UVLO HO Gat e Drive VREF 500 k HS 200 k Delay PWM Level Shift + + 200 k Delay Gat e Drive LO 100 k EN VSS 100 k Prog Dead Tim e RDT Figure 3. HIP2210 Block Diagram VDD HB VDD UVLO HB UVLO HO Gat e Drive 500 k HS HI Level Shift 100 k Gat e Drive LI 100 k LO 100 k VSS Figure 4. HIP2211 Block Diagram FN9347 Rev.1.01 Jun.23.20 Page 3 of 27 HIP2210, HIP2211 1.2 1. Overview Ordering Information Part Number (Note 4) HIP2210FRTZ (Note 2) Part Marking Temp. Range (°C) Tape and Reel (Units) (Note 1) HIP221 0FRTZ -40°C to +125°C - Package (RoHS Compliant) Pkg. Dwg. # 10 Ld 4x4 DFN L10.4x4 10 Ld 4x4 DFN L10.4x4 8 Ld SOIC M8.15 8 Ld 4x4 DFN L8.4x4 6k HIP2210FRTZ-T (Note 2) HIP2210FRTZ-T7A (Note 2) 250 HIP2211FRTZ (Note 2) HIP221 1FRTZ 6k HIP2211FRTZ-T (Note 2) HIP2211FRTZ-T7A (Note 2) 250 HIP2211FBZ (Note 3) 2211 FBZ - HIP2211FBZ-T (Note 3) 2.5k HIP2211FBZ-T7A (Note 3) 250 HIP2211FR8Z (Note 2) HIP221 1FR8Z - HIP2211FR8Z-T (Note 2) 6k HIP2211FR8Z-T7A (Note 2) 250 HIP2210EVAL1Z HIP2210 Evaluation Board HIP2211EVAL2Z HIP2211 (SOIC Package) Evaluation Board HIP2211EVAL3Z HIP2211 (10Ld TDFN Package) Evaluation Board Notes: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 4. For Moisture Sensitivity Level (MSL), see the HIP2210 and HIP2211 device pages. For more information about MSL, see TB363. 1.3 Pin Configurations HIP2211FRTZ (10 Ld 4x4 TDFN) Top View HIP2211FBZ (8 Ld SOIC) Top View VDD HB FN9347 Rev.1.01 Jun.23.20 1 2 8 7 LO VSS HO 3 6 LI HS 4 5 HI VDD 1 10 LO HB 2 9 VSS HO 3 8 LI HS 4 7 HI NC 5 6 NC EPAD Page 4 of 27 HIP2210, HIP2211 1. Overview HIP2210FRTZ (10 Ld 4x4 TDFN) Top View HIP2211FR8Z (8 Ld 4x4 DFN) Top View VDD HB 8 1 7 2 LO VSS EPAD HO HS 1.4 3 6 LI 4 5 HI VDD 1 10 LO HB 2 9 VSS HO 3 8 PWM EPAD HS 4 7 EN VREF 5 6 RDT Pin Descriptions Pin Number HIP2210 HIP2211 Pin Name 10 Ld DFN 10 Ld DFN 8 Ld SOIC 8 Ld DFN Description VDD 1 1 1 1 Analog input supply voltage and positive supply for the lower gate driver. Decouple this pin to ground with a 4.7µF or larger high-frequency ceramic capacitor to VSS. An additional 0.1µF ceramic decoupling capacitor placed close to VDD and VSS pin is recommended. HB 2 2 2 2 High-side bootstrap supply voltage for the upper gate driver referenced to HS. Connect the bootstrap capacitor to this pin and HS. HO 3 3 3 3 High-side output driver. Connect to the gate of the high-side NMOS FET. HS 4 4 4 4 High-side gate driver reference node. Connect to the source of the high-side NMOS FET. Connect the bootstrap capacitor to this pin and HB. HI - 7 5 5 High-side driver logic input. 3.3V logic compatible and VDD tolerant. LI - 8 6 6 Low-side driver logic input. 3.3V logic compatible and VDD tolerant. VREF 5 - - - Reference voltage that sets the PWM logic level thresholds. Analog supply range of 2.7V to 5.5V. Decouple VREF to VSS with a 0.1µF ceramic capacitor. If VREF is below 2.7V, the PWM inputs are ignored and HO = LO = 0. An internal 100kΩ pull-down resistor places VREF in the low state when the pin is left floating. RDT 6 - - - Programmable dead time control pin. Place a resistor from the RDT pin to VSS to set the dead time from 35ns to 350ns. The resistor range is 10kΩ to 100kΩ. Short the RDT pin to VSS to set the dead time to 15ns. See “PCB Layout Guidelines” on page 22 and “RDT and Dead Time Delay (HIP2210 Only)” on page 20 for more information. EN 7 - - - Output enable pin. When EN is low, HO = LO = 0. An internal 100kΩ pull-down resistor places EN in the low state when the pin is left floating. Output is enabled when EN is high (VDD tolerant). PWM 8 - - - Tri-level PWM input. Logic high drives HO high and LO low. Logic low drives HO low and LO high. In the mid-level state, both outputs are driven low. An internal resistor network biases the PWM pin to 50% of VREF when the pin is left floating to set the mid-level state. VSS 9 9 7 7 Ground reference for the VDD supply. When EPAD is available, connect VSS to EPAD. LO 10 10 8 8 Low-side output driver. Connect to the gate of the low-side NMOS FET. NC - 5, 6 - - No Connect. No electrical connection from this pin to the IC. - EPAD EPAD - EPAD FN9347 Rev.1.01 Jun.23.20 The EPAD is electrically isolated. Connect the EPAD to the PCB ground plane with thermal vias for heat removal. See “PCB Layout Guidelines” on page 22 for more information. Page 5 of 27 HIP2210, HIP2211 2. 2.1 2. Specifications Specifications Absolute Maximum Ratings Parameter (Note 5) Minimum Maximum Unit Supply Voltage, VDD -0.3 +20 V Boot Voltage, HB Referenced to HS -0.3 +20 V Bootstrap Voltage, HB Referenced to VSS -0.3 +120 V Bootstrap Voltage, HB Referenced to VDD -0.3 +110 V The greater of [-10 or -(20 - VDD)] +120 V EN, HI, and LI Voltage -0.3 VDD + 0.3 V PWM, VREF, RDT Voltage -0.3 +6 V Voltage on LO -0.3 VDD + 0.3 V -2 - V VHS - 0.3 VHB + 0.3 V VHS - 2 - V Continuous Voltage on HS Transient Voltage on LO (Repetitive Transient for 100ns) Voltage on HO Transient Voltage on HO (Repetitive Transient for 100ns) ESD Ratings Value Unit 2.5 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA Human Body Model (Tested per JS-001-2017) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Note: 5. All voltages referenced to VSS unless otherwise specified. 2.2 Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) Max Power Dissipation at +25°C in Free Air (W) (Note 10) 8 Ld SOIC (Notes 8, 9) 102 50 1.22 10 Ld TDFN, 8 Ld DFN (Notes 6, 7) 40 2.5 3.12 Package Type Notes: 6. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 7. For θJC, the case temperature location is the center of the exposed metal pad on the package underside. 8. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. 9. For θJC, the case temperature location is taken at the package top center. 10. Specified at published junction to ambient thermal resistance for a junction temperature of +150°C. See Note 6 for test condition to establish junction to ambient thermal resistance. Parameter Minimum Maximum Unit Maximum Junction Temperature -65 +150 °C Maximum Storage Temperature Range -55 +140 °C Pb-Free Reflow Profile FN9347 Rev.1.01 Jun.23.20 see TB493 Page 6 of 27 HIP2210, HIP2211 2.3 2. Specifications Recommended Operating Conditions Parameter (Note 5) Minimum Maximum Units +6 +18 V HI, LI, EN Inputs 0 VDD V PWM, VREF Inputs 0 +5.5 V +10 +100 kΩ VDD - 1 +18 V - +115 V The greater of [-10 or -(20 - VDD)] +100 V