HIP4083APZ

DATASHEET HIP4083 FN4223 Rev.3.00 October 2, 2015 80V, 300mA Three Phase High Side Driver The HIP4083 is a three phase high side N-channel MOSFET driver, specifically targeted for PWM motor control. Two HIP4083 may be used together for 3 phase full bridge applications (see application block diagram). Alternatively, the lower gates may be controlled directly from a buffered microprocessor output. Features Unlike other members of the HIP408x family, the HIP4083 has no built in turn-on delay. Each output (AHO, BHO, and CHO) will turn-on 65ns after its input is switched low. Likewise, each output will turn-off 60ns after its input is switched high. Very short and very long dead times are possible when two HIP4083 are used to drive a full bridge. This dead time is controlled by the input signal timing. • Drives 1000pF Load with Typical Rise Times of 35ns and Fall Times of 30ns The HIP4083 does not have a built in charge pump. Therefore, the bootstrap capacitors must be recharged on a periodic basis by initiating a short refresh pulse. In most bridge applications, this will happen automatically every time the lower FETs turn-on and the upper FETs turn-off. However, it is still possible to use the HIP4083 in applications that require the high side FETs to be on for extended periods of time. This can be easily accomplished by sending a short refresh pulse to the DIS pin. Applications The HIP4083 has reduced drive current compared to the HIP4086 making it ideal for low to moderate power applications. The HIP4083 is optimized for applications where size and cost are important. For high power applications driving large power FETs, the HIP4086 is recommended. Pinout HIP4083 (PDIP, SOIC) TOP VIEW AHI 1 16 CHB BHI 2 15 CHO CHI 3 14 CHS DIS 4 13 UVLO VSS 5 12 VDD AHB 6 11 BHB AHO 7 10 BHO AHS 8 9 BHS FN4223 Rev.3.00 October 2, 2015 • Independently Drives Three High Side N-Channel MOSFETs in Three Phase Bridge Configuration • Bootstrap Supply Max Voltage to 95VDC • Bias Supply Operation from 7V to 15V • CMOS/TTL Compatible Inputs • Programmable Undervoltage Protection • Pb-free Available • Brushless Motors • High Side Switches • AC Motor Drives • Switched Reluctance Motor Drives Ordering Information PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # HIP4083ABZ (Note) (No longer available, recommended replacement: HIP4083ABZ) -40 to 105 16 Ld SOIC (Pb-free) M16.15 HIP4083APZ (Note) -40 to 105 16 Ld PDIP (Pb-free) E16.3 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Page 1 of 10 HIP4083 Application Block Diagram 80V 12V AHI BHI AHO HIP4083 CHI MICROCONTROLLER (OPTIONAL) BHO CHO GND 12V AHO AHI BHI HIP4083 CHI BHO GND CHO GND Functional Block Diagram LEVEL SHIFTER AHI 1 BHI 2 LEVEL SHIFTER CHI 3 DIS 4 UVLO 13 EN VDD 12 FN4223 Rev.3.00 October 2, 2015 UNDERVOLTAGE DETECTOR UV 7 AHO 8 AHS 6 AHB 7 AHO 8 AHS 6 AHB 7 AHO 8 AHS DRIVER UV LEVEL SHIFTER AHB DRIVER UV LOGIC 6 DRIVER UV Page 2 of 10 HIP4083 TRUTH TABLE INPUT NOTE: OUTPUT AHI, BHI, CHI UV DIS AHO, BHO, CHO X 1 X 0 X X 1 0 1 0 0 0 0 0 0 1 X signifies that input can be either a “1” or “0”. Typical Application: Three Phase Bridge Driver with Programmable Dead Time CHIP SUPPLY CBYPASS OPTIONAL MICROPROCESSOR INPUTS CBS 1 AHI CHB 16 2 BHI CHO 15 3 CHI CHS 14 4 DIS UVLO 13 5 VSS VDD 12 6 AHB BHB 11 7 AHO BHO 10 8 AHS BHS 9 POWER BUS CBS CBS OC SENSE RCURRENT SENSE OPTIONAL MICROPROCESSOR INPUTS FN4223 Rev.3.00 October 2, 2015 1 AHI CHB 16 2 BHI CHO 15 3 CHI CHS 14 4 DIS UVLO 13 5 VSS 6 AHB VDD 12 3-PHASE LOAD BHB 11 7 AHO BHO 10 8 AHS BHS 9 Page 3 of 10 HIP4083 Typical Application: High Side Switch BOOT STRAP CAPACITOR 80V AND DIODE REQUIRED REFRESH 12V AHO DIS MICROPROCESSOR AHI HIP4083 BHO CHO BHI CHI GND LIGHT Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 6 11 16 AHB BHB CHB (xHB) Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full bridge applications. In this case, tie all three xHB pins to VDD and tie the xHS pins to the sources of the lower FETs. In full bridge applications, the lower FETs must be turned on first at start up to refresh the bootstrap capacitors. In high side switch applications, the load will keep xHS low and refresh should happen automatically at start up. 1 2 3 AHI BHI CHI (xHI) Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When xHI is low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). 5 VSS Chip ground. 13 UVLO Undervoltage setting. A resistor can be connected between this pin and VSS to program the under voltage set point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this pin is tied to VDD, the undervoltage set point is typically 6.2V. 4 DIS Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than VDD). 7 10 15 AHO BHO CHO (xHO) Gate connections. Connect to the gates of the power MOSFETs in each phase. 8 9 14 AHS BHS CHS (xHS) MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap capacitors to these pins. In high side switch applications, 2mA of current will flow out of these pins into the load when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down to at least 7V below VDD. For example, when VDD = 12V, xHS must be pulled down to 5V. Therefore, the minimum load necessary for proper refresh is given by the following equation: RMIN = 5V/2mA = 2.5k. So in this case, if the load has an impedance less than 5k, refresh will happen automatically at start up. 12 VDD Positive supply rail. Bypass this pin to VSS with a capacitor 1F. In applications where the bus voltage and chip VDD are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly simplifies the filtering requirements. FN4223 Rev.3.00 October 2, 2015 Page 4 of 10 HIP4083 Absolute Maximum Ratings TA = 25°C Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS . . . . . . . . . -6V (Transient) to 85V (-40°C to 150°C) Voltage on xHB . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Resistance (Typical, Note 1) JA (°C/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V to +15V Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS +VDD Operating Ambient Temperature Range . . . . . . . . . .-40°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS. Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, Gate Capacitance (CGATE) = 1000pF, RUV =  TJ = -40°C TO 150°C TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current xHI = 5V 0.5 1.5 2.25 0.25 2.3 mA VDD Operating Current f = 20kHz, 50% Duty Cycle 1.0 2.0 2.5 0.75 3.0 mA xHB On Quiescent Current xHI = 0V 65 100 240 45 250 A xHB Off Quiescent Current xHI = 5V 0.6 0.85 1.3 0.5 1.4 mA xHB Operating Current f = 20kHz, 50% Duty Cycle 0.6 0.85 1.2 0.5 1.3 mA VDD Rising Undervoltage Threshold RUV OPEN 6.2 7.0 8.0 6.1 8.1 V VDD Falling Undervoltage Threshold RUV OPEN 5.75 6.5 7.5 5.25 7.6 V Minimum Undervoltage Threshold RUV = VDD 5.0 6.2 6.9 4.5 7.0 V Low Level Input Voltage - - 1.0 - 0.8 V High Level Input Voltage 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV INPUT PINS: AHI, BHI, CHI AND DIS Low Level Input Current VIN = 0V -145 -100 -60 -150 -50 A High Level Input Current VIN = 5V -1 - +1 -10 +10 A GATE DRIVER OUTPUT PINS: AHO, BHO, AND CHO Average Turn-On Current VOUT 0V to 5V 100 240 400 50 500 mA Average Turn-Off Current VOUT VDD to 4V 150 300 450 100 550 mA FN4223 Rev.3.00 October 2, 2015 Page 5 of 10 HIP4083 Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF TJS = -40°C TO 150°C TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Turn-Off Propagation Delay (xHI - xHO) No Load - 60 80 90 ns Turn-On Propagation Delay (xHI - xHO) No Load - 65 90 100 ns Rise Time (10 - 90%) CGATE = 1000pF - 35 60 - 65 ns Fall Time (90 - 10%) CGATE = 1000pF - 30 50 - 55 ns Disable Turn-Off Propagation Delay No Load - 65 - - 100 ns Disable to Output Enable (DIS - xHO) No Load - 70 - - 100 ns Typical Performance Curves 4.5 200kHz VDD SUPPLY CURRENT (mA) VDD = 16V 1.8 VDD = 15V VDD = 12V 1.6 VDD = 10V 1.4 VDD = 8V VDD = 7V 1.2 1.0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 FIGURE 1. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE xHB SUPPLY OFF CURRENT (A) 950 (VXHB - VXHS) = 15V (VXHB - VXHS) = 14V (VXHB - VXHS) = 13V (VXHB - VXHS) = 12V 900 850 (VXHB - VXHS) = 10V 800 (VXHB - VXHS) = 8V 750 (VXHB - VXHS) = 7V 700 650 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 160 FIGURE 3. FLOATING SUPPLY OFF BIAS CURRENT FN4223 Rev.3.00 October 2, 2015 100kHz 4.0 50kHz 10kHz 3.5 20kHz 3.0 -60 -40 140 160 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 160 FIGURE 2. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY 120 xHB ON SUPPLY CURRENT (A) VDD SUPPLY CURRENT (mA) 2.0 110 100 90 (VXHB - VXHS) = 12V (VXHB - VXHS) = 15V (VXHB - VXHS) = 10V (VXHB - VXHS) = 8V 80 (VXHB - VXHS) = 7V 70 60 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 160 FIGURE 4. FLOATING SUPPLY ON BIAS CURRENT Page 6 of 10 HIP4083 Typical Performance Curves (Continued) 4 2.5 NO LOAD 200kHz xHB SUPPLY CURRENT (mA) xHB SUPPLY CURRENT (mA) CGATE = 1000pF 3 100kHz 2 50kHz 1 20kHz 200kHz 2.0 1.5 1.0 100kHz 50kHz 20kHz 0.5 10kHz 10kHz 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 0 -60 -40 160 FIGURE 5. FLOATING SUPPLY SWITCHING BIAS CURRENT 120 140 160 100 9 TRIP (50K, UVLO TO GND) 8 ENABLE (UVLO OPEN) 7 TRIP (UVLO OPEN) 6 PROPAGATION DELAY (ns) ENABLE (50K, UVLO TO GND) DISABLE TURN-OFF 80 ENABLE TURN-ON TURN-OFF 60 TURN-ON TRIP/ENABLE (OK, UVLO TO VDD) 5 -60 -40 -20 0 20 40 60 80 100 120 40 -60 140 160 -40 -20 JUNCTION TEMPERATURE (°C) FIGURE 7. UNDERVOLTAGE THRESHOLD 120 140 160 0.35 AVERAGE TURN-ON CURRENT (A) CGATE = 1000pF 40 TURN-ON TURN-OFF 30 20 -60 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) FIGURE 8. PROPAGATION DELAY 50 RISE AND FALL TIME (ns) 20 40 60 80 100 0 JUNCTION TEMPERATURE (°C) FIGURE 6. FLOATING SUPPLY SWITCHING BIAS CURRENT 10 UNDERVOLTAGE SHUTDOWN/ENABLE VOLTAGE (V) -20 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 FIGURE 9. RISE AND FALL TIME (10-90%) FN4223 Rev.3.00 October 2, 2015 140 160 0V TO 5V 15V 0.3 12V 0.25 10V 0.2 8V 0.15 7V 0.1 -60 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (°C) FIGURE 10. GATE DRIVER AVERAGE TURN-ON CURRENT Page 7 of 10 HIP4083 Typical Performance Curves (Continued) 50 15V 0.4 12V 0.3 10V VDD TO 4V xHS LEAKAGE CURRENT (A) AVERAGE TURN-OFF CURRENT (A) 0.5 8V 0.2 7V 0.1 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 160 FIGURE 11. GATE DRIVER AVERAGE TURN-OFF CURRENT 40 30 20 10 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 160 FIGURE 12. HIGH VOLTAGE LEAKAGE CURRENT Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 2, 2015 FN4223.3 CHANGE - Updated Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN4223 Rev.3.00 October 2, 2015 Page 8 of 10 HIP4083 Dual-In-Line Plastic Packages (PDIP) N E16.3 (JEDEC MS-001-BB ISSUE D) E1 INDEX AREA 1 2 3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B- SYMBOL -AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M C L eA A1 eC C A B S C eB MILLIMETERS MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 D1 0.005 - 0.13 - 5 19.68 5 E 0.300 0.325 7.62 8.25 6 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.150 2.93 3.81 4 N NOTES: 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 16 16 9 Rev. 0 12/93 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN4223 Rev.3.00 October 2, 2015 Page 9 of 10 HIP4083 HIP4083 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e  B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N  NOTES: MILLIMETERS 16 0° 16 8° 0° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4223 Rev.3.00 October 2, 2015 Page 10 of 10