HM62V16256CLTT-5SL

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Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. HM62V16256C Series 4 M SRAM (256-kword × 16-bit) ADE-203-1099G (Z) Rev. 4.0 Jul. 31, 2002 Description The Hitachi HM62V16256C Series is 4-Mbit static RAM organized 262,144-word × 16-bit. HM62V16256C Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII. Features • • • Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V Fast access time: 55 ns (max) Power dissipation:  Active: 5.0 mW/MHz (typ)(VCC = 2.5 V) : 6.0 mW/MHz (typ) (VCC = 3.0 V)  Standby: 2 µW (typ) (VCC = 2.5 V) : 2.4 µW (typ) (VCC = 3.0 V) Completely static memory.  No clock or timing strobe required Equal access and cycle times Common data input and output.  Three state output B attery backup operation.  2 chip selection for battery backup • • • • HM62V16256C Series Ordering Information Type No. HM62V16256CLTT-5 HM62V16256CLTT-5SL Access time 55 ns 55 ns Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB) 2 HM62V16256C Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 Pin Description Pin name A0 to A17 I/O0 to I/O15 CS1 CS2 WE OE LB UB VCC VSS Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Power supply Ground 3 HM62V16256C Series Block Diagram LSB V CC V SS • • • • • A12 A11 A10 A9 A8 A13 A14 A15 A16 A17 MSB A7 Row decoder Memory matrix 2,048 x 2,048 I/O0 Input data control I/O15 • • Column I/O Column decoder • • LSB A4 A3 A2 A1 A5 A6 A0 MSB • • CS2 CS1 LB UB WE OE Control logic 4 HM62V16256C Series Operation Table CS1 H × × L L L L L L L CS2 × L × H H H H H H H WE × × × H H H L L L H OE × × × L L L × × × H UB × × H L H L L H L × LB × × H L L H L L H × I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value –0.5 to + 4.6 –0.5* to V CC + 0.3* 1.0 –55 to +125 –20 to +85 1 2 Unit V V W °C °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage VCC = 2.2 V to 2.7 V VIH VCC = 2.7 V to 3.6 V VIH Input low voltage VCC = 2.2 V to 2.7 V VIL VCC = 2.7 V to 3.6 V VIL Ambient temperature range Note: Ta Min 2.2 0 2.0 2.0 –0.2 –0.3 –20 Typ 2.5/3.0 0 — — — — — Max 3.6 0 VCC + 0.3 VCC + 0.3 0.4 0.6 70 Unit V V V V V V °C 1 1 Note 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns. 5 HM62V16256C Series DC Characteristics Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | — — Typ* 1 — — Max 1 1 Unit µA µA Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL or LB = UB = VIH , VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/VIL, I I/O = 0 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ V CC – 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V CS2 = VIL 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V CS2 ≥ V CC – 0.2 V CS1 ≤ 0.2 V Operating current Average operating current I CC I CC1 — — 5 8 20 25 mA mA I CC2 — 2 5 mA Standby current Standby current I SB I SB1* 2 — — 0.1 0.5 0.3 20 mA µA I SB1*3 Output high voltage VCC =2.2 V to 2.7 V VOH VCC =2.7 V to 3.6 V VOH VCC =2.2 V to 3.6 V VOH Output low voltage VCC =2.2 V to 2.7 V VOL VCC =2.7 V to 3.6 V VOL VCC =2.2 V to 3.6 V VOL — 2.0 2.4 0.5 — — 10 — — — 0.4 0.4 0.2 µA V V V V V V I OH = –0.5 mA I OH = –1 mA I OH = –100 µA I OL = 0.5 mA I OL = 2 mA I OL = 100 µA VCC – 0.2— — — — — — — Notes: 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25° C and not guaranteed. 2. This characteristic is guaranteed only for L-version. 3. This characteristic is guaranteed only for L-SL version. 6 HM62V16256C Series Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min — — Typ — — Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. 7 HM62V16256C Series AC Characteristics (Ta = –20 to +70°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.) Test Conditions • • • • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.0 V (VCC = 2.2 V to 2.7 V) VIL = 0.4 V, VIH = 2.2 V (VCC = 2.7 V to 3.6 V) Input rise and fall time: 5 ns Input timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) Output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) Input timing reference levels: 1.4 V (VCC = 2.7 V to 3.6 V) Output timing reference levels: 1.4 V (VCC = 2.7 V to 3.6 V) Output load: See figures (Including scope and jig) VTM 1.4 V R1 Dout R1 = 3070 Ω 30pF R2 R2 = 3150 Ω VTM = 2.3 V Dout 50pF RL=500 Ω Output load (A) (VCC = 2.2 V to 2.7 V) Output load (B) (VCC = 2.7 V to 3.6 V) 8 HM62V16256C Series Read Cycle HM62V16256C -5 Parameter Read cycle time Address access time Chip select access time Symbol t RC t AA t ACS1 t ACS2 Output enable to output valid Output hold from address change LB, UB access time Chip select to output in low-Z t OE t OH t BA t CLZ1 t CLZ2 LB, UB enable to low-z Output enable to output in low-Z Chip deselect to output in high-Z t BLZ t OLZ t CHZ1 t CHZ2 LB, UB disable to high-Z Output disable to output in high-Z t BHZ t OHZ Min 55 — — — — 10 — 10 10 5 5 0 0 0 0 Max — 55 55 55 35 — 55 — — — — 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes 9 HM62V16256C Series Write Cycle HM62V16256C -5 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB, UB valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in High-Z Write to output in high-Z Symbol t WC t AW t CW t WP t BW t AS t WR t DW t DH t OW t OHZ t WHZ Min 55 50 50 40 50 0 0 25 0 5 0 0 Max — — — — — — — — — — 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 6 7 5 4 Notes Notes: 1. t CHZ, tOHZ , t WHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1 , a high CS2, a low WE and a low LB or a low UB . A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 10 HM62V16256C Series Timing Waveform Read Cycle t RC Address tAA tACS1 CS1 tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address CS2 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB, UB tBLZ*2, 3 tOE OE tOLZ*2, 3 Dout High impedance Valid data tOH tOHZ*1, 2, 3 11 HM62V16256C Series Write Cycle (1) (WE Clock) tWC Address Valid address tWR*7 tCW*5 CS1 tCW*5 CS2 tBW LB, UB tAW tWP*4 WE tAS*6 tDW Din tWHZ*1, 2 Valid data tDH tOW*2 High impedance Dout 12 HM62V16256C Series Write Cycle (2) (CS Clock, OE = VIH) tWC Address Valid address tAW tAS*6 CS1 tCW*5 CS2 tBW LB, UB tCW*5 tWR*7 tWP*4 WE tDW Din Valid data tDH High impedance Dout 13 HM62V16256C Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Address Valid address tAW tCW*5 CS1 tCW*5 CS2 tAS*6 LB, UB tBW tWR*7 tWP*4 WE tDW Din Valid data tDH High impedance Dout 14 HM62V16256C Series Low VCC Data Retention Characteristics (Ta = –20 to +70 °C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 4 — Max 3.6 Unit V Test conditions*3 Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V, CS1 ≤ 0.2 V VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V, CS1 ≥ V CC – 0.2 V or (3) LB = UB ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V, CS1 ≤ 0.2 V Data retention current I CCDR*1 — 0.5 20 µA I CCDR*2 Chip deselect to data retention time Operation recovery time t CDR tR — 0 t RC* 5 0.5 — — 10 — — µA ns ns See retention waveform Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = –20 to +40°C. 2. This characteristic is guaranteed only for L-SL version, 3 µA max. at Ta = –20 to +40°C. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1 , LB , UB , I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ V CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB , I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed. 5. t RC = read cycle time. 15 HM62V16256C Series Low V CC Data Retention Timing Waveform (1) (CS1 Controlled) Data retention mode tR t CDR V CC 2.2 V V DR 2.0 V CS1 0V CS1 ≥ VCC – 0.2 V Low V CC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR V CC 2.2 V CS2 V DR 0.4 V 0V 0 V < CS2 < 0.2 V Data retention mode tR Low V CC Data Retention Timing Waveform (3) (LB, UB Controlled) Data retention mode tR t CDR V CC 2.2 V V DR 2.0 V LB, UB 0V LB, UB ≥ VCC – 0.2 V 16 HM62V16256C Series Package Dimensions HM62V16256CLTT Series (TTP-44DB) As of January, 2002 18.41 18.81 Max 44 23 Unit: mm 1 *0.30 ± 0.10 0.25 ± 0.05 0.80 0.13 M 22 0.80 11.76 ± 0.20 0˚ – 5˚ *0.17 ± 0.05 0.125 ± 0.04 1.005 Max 10.16 1.20 Max 0.10 0.13 ± 0.05 0.50 ± 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC JEITA Mass (reference value) TTP-44DB — — 0.43 g 17 HM62V16256C Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: (408) 433-1990 Fax: (408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: (1628) 585000 Fax: (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strasse 3 D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: (89) 9 9180-0 Fax: (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : -6538-6533/6538-8577 Fax : -6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : -(2)-2718-3666 Fax : -(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : -2735-9218 Fax : -2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright C Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 6.0 18