HM64YGB36100

HM64YGB36100 Series 32M Synchronous Late Write Fast Static RAM (1-Mword × 36-bit) REJ03C0271-0100 (Previous ADE-203-1374 (Z) Rev. 0.0) Rev.1.00 Jun.27.2005 Description The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device. Features • • • • • • • • • • • • • 2.5 V ± 5% operation and 1.5 V (VDDQ) 32-Mbit density Synchronous register to register operation Internal self-timed late write Byte write control (4 byte write selects, one for each 9-bit) Optional ×18 configuration HSTL compatible I/O Programmable impedance output drivers Differential HSTL clock inputs Asynchronous G output control Asynchronous sleep mode FC-BGA 119pin package with SRAM JEDEC standard pinout Limited set of boundary scan JTAG IEEE 1149.1 compatible Ordering Information Type No. HM64YGB36100BP-33 Organization 1M × 36 Access time 1.6 ns Cycle time 3.3 ns Package 119-bump 1.27 mm 14 mm × 22 mm BGA PRBG0119DC-A (BP-119F) Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, G: Late Write SRAM, B: VDDQ = 1.5 V Rev.1.00 Jun 27, 2005 page 1 of 19 HM64YGB36100 Series Pin Arrangement 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc7 DQc5 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd5 DQd7 NC NC VDDQ 2 SA14 SA15 SA16 DQc8 DQc6 DQc4 DQc2 DQc0 VDD DQd0 DQd2 DQd4 DQd6 DQd8 SA10 NC TMS 3 SA13 SA12 SA11 VSS VSS VSS SWEc VSS VREF VSS SWEd VSS VSS VSS M1 SA18 TDI 4 NC SA20 VDD ZQ SS G NC NC VDD K K SWE SA17 SA19 VDD SA3 TCK 5 SA6 SA5 SA4 VSS VSS VSS SWEb VSS VREF VSS SWEa VSS VSS VSS M2 SA2 TDO 6 SA7 SA9 SA8 DQb8 DQb6 DQb4 DQb2 DQb0 VDD DQa0 DQa2 DQa4 DQa6 DQa8 SA1 NC NC 7 VDDQ NC NC DQb7 DQb5 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa5 DQa7 NC ZZ VDDQ (Top view) Block Diagram SA1 to SA20 Read add. reg. Write add. reg. SA1 to SA20 compare Match0 1 0 Memory array 1M × 36 0 1 59-N (x: a to d) SWEx 1st reg. SWEx 2nd reg. Byte write control Output reg. Din reg. 55 59K SS reg. SWE reg. Output enable / ZQ Impedance control DQxn (x: a to d, n: 0 to 8) Rev.1.00 Jun 27, 2005 page 2 of 19 HM64YGB36100 Series Pin Descriptions Name VDD VSS VDDQ VREF K K SS SWE SAn SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC I/O type Supply Supply Supply Supply Input Input Input Input Input Input Input Input Input I/O Input Input Input Input Output  Descriptions Core power supply Ground Output power supply Input reference, provides input reference voltage Clock input, active high Clock input, active low Synchronous chip select Synchronous write enable Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection Notes n: 1 to 20 x: a to d 1 x: a to d n: 0 to 8 M1 M2 Protocol Notes VSS VDD Synchronous register to register operation 2 Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or open, output buffer impedance will be maximum. 2. Mode control input pins M1 and M2 are set at power-up and will not change the states during the SRAM operates. This SRAM supports only single clock, pipelined read protocol. Other settings are not applicable. Mode control pin M2 can be set to VDDQ instead of VDD. Rev.1.00 Jun 27, 2005 page 3 of 19 HM64YGB36100 Series Truth Table ZZ H L SS SS × H G × × SWE SWE × × SWEa SWEa × × SWEb SWEb × × SWEc SWEc × × SWEd SWEd × × K × L-H K × H-L Operation Sleep mode Dead (not selected) Dead (dummy read) Read DQ (n) High-Z × DQ (n+1) High-Z High-Z L × H H × × × × × × High-Z × L L L H × × × × L-H H-L × L L × L L L L L L-H H-L L L × L H L L L L-H H-L L L × L L H L L L-H H-L L L × L L L H L L-H H-L L L × L L L L H L-H H-L L L L L L L L L L L L L L L L L × × × × × × × × L L L L L L L L H L L H H H H L H H L L H H L H L H H L H L H H L L H H L H H H L-H L-H L-H L-H L-H L-H L-H L-H H-L H-L H-L H-L H-L H-L H-L H-L Write a, b, c, d byte Write b, c, d byte Write a, c, d byte Write a, b, d byte Write a, b, c byte Write c, d byte Write a, d byte Write a, b byte Write b, c byte Write d byte Write c byte Write b byte Write a byte High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT (a, b, c, d) 0 to 8 DIN (a, b, c, d) 0 to 8 DIN (b, c, d) 0 to 8 DIN (a, c, d) 0 to 8 DIN (a, b, d) 0 to 8 DIN (a, b, c) 0 to 8 DIN (c, d) 0 to 8 DIN (a, d) 0 to 8 DIN (a, b) 0 to 8 DIN (b, c) 0 to 8 DIN (d) 0 to 8 DIN (c) 0 to 8 DIN (b) 0 to 8 DIN (a) 0 to 8 Notes: 1. H: VIH, L: VIL, ×: VIH or VIL 2. SWE, SS, SWEa to SWEd and SA are sampled at the rising edge of K clock. Rev.1.00 Jun 27, 2005 page 4 of 19 HM64YGB36100 Series Programmable Impedance Output Drivers Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 Ω typical. If the status of ZQ pin is open, output impedance is maximum value. Maximum impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance to be completely updated. Absolute Maximum Ratings Parameter Symbol Input voltage on any pin VIN V Core supply voltage VDD V Output supply voltage VDDQ V Operating temperature TOPR °C Storage temperature TSTG °C Output short-circuit current IOUT mA Latch up current ILI mA Package junction to top thermal resistance θJ-top °C/W 5 Package junction to board thermal resistance θJ-board °C/W 5 Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the instantaneous value of VDDQ. 5. See figure below. θJ-top θJ-board Rating −0.5 to VDDQ + 0.5 −0.5 to +3.13 −0.5 to +2.1 0 to +85 −55 to +125 25 200 6.5 12 Unit Notes 1, 4 1 1, 4 Thermocouple Thermo grease Teflon block Thermocouple SRAM Water Cold plate SRAM Water JEDEC/2S2P BGA Thermal board Cold plate JEDEC/2S2P Thermal board Water BGA Water Teflon block Thermo grease Rev.1.00 Jun 27, 2005 page 5 of 19 HM64YGB36100 Series Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. Recommended DC Operating Conditions (Ta = 0 to +85°C) Parameter Symbol Min Typ Max Power supply voltage: core VDD 2.38 2.50 2.63 Power supply voltage: I/O VDDQ 1.40 1.50 1.60 Input reference voltage: I/O VREF 0.60 0.75 0.90 Input high voltage VIH VREF + 0.10  VDDQ + 0.30 Input low voltage VIL −0.30  VREF − 0.10 Clock differential voltage VDIF 0.10  VDDQ + 0.30 Clock common mode voltage VCM 0.60  0.90 Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. Minimum differential input voltage required for differential input clock operation. 3. See figure below. 4. VREF = 0.75 V (typ). Unit V V V V V V V Notes 1 4 4 2, 3 3 Differential Voltage / Common Mode Voltage VDDQ VDIF VCM VSS Rev.1.00 Jun 27, 2005 page 6 of 19 HM64YGB36100 Series DC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%) Parameter Input leakage current Output leakage current Standby current VDD operating current, excluding output drivers Quiescent active power supply current Maximum power dissipation, including output drivers Symbol ILI ILO ISBZZ IDD IDD2 P Min       Max 2 5 150 550 200 2.3 Unit µA µA mA mA mA W Notes 1 2 3 4 5 6 Parameter Symbol Min Typ Max Unit Notes Output low voltage VOL VSS  VSS + 0.4 V 7 Output high voltage VOH VDDQ − 0.4  VDDQ V 8 ZQ pin connect resistance RQ  250  Ω Output “Low” current IOL (VDDQ/2) / {(RQ/5) − 15%} (VDDQ/2) / {(RQ/5) + 15%} mA 9, 11 Output “High” current IOH (VDDQ/2) / {(RQ/5) + 15%} (VDDQ/2) / {(RQ/5) − 15%} mA 10, 11 Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin) 2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z 3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is guaranteed at +75°C junction temperature. 4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle 5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz 6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer to determine electrical and package requirements for the SRAM device. 7. RQ = 250 Ω, IOL = 6.8 mA 8. RQ = 250 Ω, IOH = −6.8 mA 9. Measured at VOL = 1/2 VDDQ 10. Measured at VOH = 1/2 VDDQ 11. The total external capacitance of ZQ pin must be less than 7.5 pF. Rev.1.00 Jun 27, 2005 page 7 of 19 HM64YGB36100 Series AC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%) Single Differential Clock Register-Register Mode HM64YGB36100BP -33 Min Max        1.6   2.0  2.0 2.0  15.0 Parameter Symbol Unit Notes CK clock cycle time tKHKH 3.3 ns CK clock high width tKHKL 1.3 ns CK clock low width tKLKH 1.3 ns Address setup time tAVKH 0.3 ns Data setup time tDVKH 0.3 ns Address hold time tKHAX 0.6 ns Data hold time tKHDX 0.6 ns Clock high to output valid tKHQV  ns Clock high to output hold tKHQX 0.65 ns Clock high to output low-Z (SS control) tKHQX2 0.65 ns Clock high to output high-Z tKHQZ 0.65 ns Output enable low to output low-Z tGLQX 0.1 ns Output enable low to output valid tGLQV  ns Output enable high to output high-Z tGHQZ  ns Sleep mode recovery time tZZR 20.0 ns Sleep mode enable time tZZE  ns Notes: 1. See figure in ”AC Test Conditions”. 2. Parameters may be guaranteed by design, i.e., without tester guardband. 3. Transitions are measured ±50 mV of output high impedance from output low impedance. 4. Transitions are measured ±50 mV from steady state voltage. 5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation. 6. Minimum value is verified by design and tested without guardband. 2 2 1 1, 6 1, 4, 6 1, 3, 6 1, 4, 6 1, 4 1, 3 5 1, 3, 5 Rev.1.00 Jun 27, 2005 page 8 of 19 HM64YGB36100 Series Timing Waveforms Read Cycle-1 tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS SWE SWEx DQ tAVKH tKHAX tKHQX Q1 tKHQV Q2 Read Cycle-2 (SS Controlled) tKHKH K, K tAVKH SA A1 tAVKH A3 tKHAX tKHAX A4 tKHKL tKLKH SS tAVKH tKHAX SWE SWEx tKHQZ DQ Q0 Q1 tKHQX2 Q3 Rev.1.00 Jun 27, 2005 page 9 of 19 HM64YGB36100 Series Read Cycle-3 (G Controlled) tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX SWE SWEx G tGHQZ DQ Q0 Q1 tGLQV tGLQX Q3 Read operation During read cycle, the address is registered during the first rising clock edge, the internal array is read between this first edge and second edge, and data is captured in the output register. Rev.1.00 Jun 27, 2005 page 10 of 19 HM64YGB36100 Series Write Cycle tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX tKHAX SWE tAVKH SWEx G tDVKH DQ D0 D1 tKHDX D2 D3 Notes: ZZ = VIL, x: a to d Write operation During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address. Rev.1.00 Jun 27, 2005 page 11 of 19 HM64YGB36100 Series Read-Write Cycle READ tKHKH K, K tAVKH SA A1 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A6 A7 READ (G control) tKHKL tKLKH WRITE READ DEAD WRITE (SS control) SS tAVKH SWE tAVKH SWEx G DQ Q0 tKHQX tKHQV Q1 tGHQZ tDVKH tKHDX D3 tGLQX tGLQV Q4 tKHQZ Q6 Notes: ZZ = VIL, x: a to d ZZ Control tKHKH K, K tAVKH SA A1 tAVKH tAVKH tKHAX tKHAX tKHAX tKHKL tKLKH SS SWE SWEx ZZ Sleep active DQ Sleep off Q1 tZZR tZZE Sleep active Notes: G = VIL, x: a to d W hen ZZ is switching, clock input K must be at the same logic level for the reliable operation. Rev.1.00 Jun 27, 2005 page 12 of 19 HM64YGB36100 Series Input Capacitance (VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz) Parameter Symbol Min Max Unit Pin name Input capacitance CIN  4 pF SAn, SS, SWE, SWEx Clock input capacitance CCLK  5 pF K, K I/O capacitance CIO  5 pF DQxn Notes: 1. This parameter is sampled and not 100% tested. 2. Exclude G 3. Connect pins to GND, except VDD, VDDQ, and the measured pin. Notes 1, 3 1, 2, 3 1, 3 AC Test Conditions Parameter Symbol Input and output timing reference levels VREF Input signal amplitude VIL, VIH Input rise / fall time tr, tf Clock input timing reference level VDIF to clock VCM to clock Output loading conditions Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V. Conditions 0.75 0.25 to 1.25 0.5 (10% to 90%) Differential cross point 0.75 0.75 See figure below Unit V V ns V V Note Output Loading Conditions 16.7 Ω 16.7 Ω DQ 16.7 Ω 50 Ω 5 pF 50 Ω 5 pF 50 Ω 0.75 V 50 Ω 0.75 V 0.75 V Rev.1.00 Jun 27, 2005 page 13 of 19 HM64YGB36100 Series Boundary Scan Test Access Port Operations Overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1 compliance. The HM64YGB series contains a TAP controller. Instruction register, boundary scans register, bypass register and ID register. Test Access Port Pins Symbol I/O Name TCK Test clock TMS Test mode select TDI Test data in TDO Test data out Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected. To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V. TAP DC Operating Characteristics (Ta = 0 to +85°C) Parameter Boundary scan input high voltage Boundary scan input low voltage Boundary scan input leakage current Boundary scan output low voltage Boundary scan output high voltage Notes: 1. 0 ≤ VIN ≤ 3.6 V for all logic input pin 2. IOL = 2 mA at VDD = 2.5 V. 3. IOH = −2 mA at VDD = 2.5 V. Symbol VIH VIL ILI VOL VOH Min 1.4 V −0.3 V −10 µA  2.1 V Max 3.6 V 0.8 V +10 µA 0.2 V  Notes 1 2 3 Rev.1.00 Jun 27, 2005 page 14 of 19 HM64YGB36100 Series TAP AC Operating Characteristics (Ta = 0 to +85°C) Parameter Symbol Min Max Unit Test clock cycle time tTHTH 67  ns Test clock high pulse width tTHTL 30  ns Test clock low pulse width tTLTH 30  ns Test mode select setup tMVTH 10  ns Test mode select hold tTHMX 10  ns Capture setup tCS 10  ns Capture hold tCH 10  ns TDI valid to TCK high tDVTH 10  ns TCK high to TDI don’t care tTHDX 10  ns TCK low to TDO unknown tTLQX 0  ns TCK low to TDO valid tTLQV  20 ns Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. Note 1 1 TAP AC Test Conditions (VDD = 2.5 V) Temperature Input timing measurement reference level Input pulse levels Input rise/fall time Output timing measurement reference level Test load termination supply voltage (VT) Output load Boundary Scan AC Test Load VT DUT 50 Ω Z0 = 5 0 Ω TDO 0°C ≤ Ta ≤ +85°C 1.1 V 0 to 2.5 V 1.5 ns typical (10% to 90%) 1.25 V 1.25 V See figure below Rev.1.00 Jun 27, 2005 page 15 of 19 HM64YGB36100 Series TAP Controller Timing Diagram tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV TDO tCS tCH RAM ADDRESS tTLQX tTHTL tTLTH Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 70 bits Symbol IR [2:0] BP ID [31:0] BS [70:1] Note TAP Controller Instruction Set IR2 0 0 0 0 1 1 1 1 Note: IR1 IR0 Instruction Operation 0 0 SAMPLE-Z Tristate all data drivers and capture the pad value 0 1 IDCODE 1 0 SAMPLE-Z Tristate all data drivers and capture the pad value 1 1 BYPASS 0 0 SAMPLE 0 1 BYPASS 1 0 PRIVATE Do not use. They are reserved for vendor use only 1 1 BYPASS This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. Rev.1.00 Jun 27, 2005 page 16 of 19 HM64YGB36100 Series Boundary Scan Order (HM64YGB36100) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bump ID M2 SA19 SA3 SA1 SA2 ZZ DQa8 DQa7 DQa6 DQa5 DQa4 DQa2 DQa3 DQa0 DQa1 SWEa K K G SWEb DQb1 DQb0 DQb3 DQb2 DQb4 DQb5 DQb6 DQb7 DQb8 SA7 SA8 SA4 SA6 SA9 SA5 Signal name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Bit # 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4B 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R Bump ID SA12 SA15 SA13 SA11 SA16 SA14 DQc8 DQc7 DQc6 DQc5 DQc4 DQc2 DQc3 DQc0 DQc1 SWEc ZQ SS SA20 NC SWE SWEd DQd1 DQd0 DQd3 DQd2 DQd4 DQd5 DQd6 DQd7 DQd8 SA18 SA10 SA17 M1 Signal name Notes: 1. Bit#1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “Place Holder”. Place holder registers are internally connected to VSS. 3. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite logic levels for the reliable operation. 4. ZZ must remain VIL during boundary scan. 5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results. 6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results. Rev.1.00 Jun 27, 2005 page 17 of 19 HM64YGB36100 Series ID Register Revision number (31:28) 0000 Device density and configuration (27:18) 0100000100 Vendor definition (17:12) xxxxxx Vendor JEDEC code (11:1) 00000000111 Start bit (0) 1 Part HM64YGB36100 TAP Controller State Diagram 1 Test-logicreset 0 0 Run-test/ idle 1 SelectDR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 1 0 0 1 0 1 1 SelectIR-scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 1 0 1 Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high for at least five rising edges of TCK. Rev.1.00 Jun 27, 2005 page 18 of 19 HM64YGB36100 Series Package Dimensions HM64YGB36100BP Series (PRBG0119DC-A / Previous Code: BP-119F) JEITA Package Code P-BGA119-14x22-1.27 RENESAS Code PRBG0119DC-A Previous Code BP-119F MASS[Typ.] 1.0g D A B INDEX ×4 v y1 S S A y S e T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 e U A1 E Reference Symbol Dimension in Millimeters Min Nom 14.00 22.00 0.20 Max D E v w A A1 e b x y y1 SD SE ZD ZE φb 0.84 1.78 0.58 1.98 0.66 1.27 0.90 2.18 0.74 0.96 0.30 0.20 0.35 φ× M S A B φ0.15 M S Rev.1.00 Jun 27, 2005 page 19 of 19 Revision History HM64YGB36100 Series Data Sheet Description Summary Rev. 0.0 1.00 Date Dec. 5, 2002 Jun. 27, 2005 Page  Initial issue Change format issued by Renesas Technology Corp.  Ordering Information 1 Addition of Renesas package codes Change of 5 Programmable Impedance Output Drivers Package Dimensions 19 Addition of Renesas package codes Changed to Renesas formats Sales Strategic Planning Div. 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