ICL232CBE

DATASHEET ICL232 FN3020 Rev 8.00 October 15, 2014 +5V Powered, Dual RS-232 Transmitter/Receiver The ICL232 is a dual RS-232 transmitter/receiver interface circuit that meets all ElA RS-232C and V.28 specifications. It requires a single +5V power supply, and features two onboard charge pump voltage converters which generate +10V and -10V supplies from the 5V supply. Features The drivers feature true TTL/CMOS input compatibility, slew-rate-limited output, and 300Ω power-off source impedance. The receivers can handle up to +30V, and have a 3kΩ to 7kΩ input impedance. The receivers also have hysteresis to improve noise rejection. • Low power consumption • Meets all RS-232C and V.28 specifications • Requires only single +5V power supply • Onboard voltage doubler/inverter • 2 drivers - 9V output swing for +5V lnput - 300Ω power-off source impedance - Output current limiting - TTL/CMOS compatible - 30V/µs maximum slew rate Applications • Any system requiring RS-232 communications port - Computer - portable and mainframe - Peripheral - printers and terminals - Portable instrumentation - Modems • 2 Receivers - 30V input voltage range - 3kΩ to 7kΩ input impedance - 0.5V hysteresis to improve noise rejection • Dataloggers • All critical parameters are guaranteed over the entire commercial, industrial and military temperature ranges • Pb-free (RoHS compliant) +5V + 1.0µF 1 1µF + 3 4 1µF T1IN T2IN R1OUT R2OUT + 5 C1+ C1C2+ C2- 16 VCC 2 +5V TO 10V VOLTAGE INVERTER V+ +10V TO -10V VOLTAGE INVERTER 11 +5V 400kΩ T1 10 +5V 400kΩ T2 + V- 6 + 14 7 12 13 R1 5kΩ R2 5kΩ 9 1µF 8 1µF T1OUT T2OUT R1IN R2IN 15 FIGURE 1. FUNCTIONAL DIAGRAM FN3020 Rev 8.00 October 15, 2014 Page 1 of 8 ICL232 Pin Configuration ICL232 (16 LD SOIC) TOP VIEW C1+ 1 16 VCC V+ 2 15 GND C1- 3 14 T1OUT C2+ 4 13 R1IN C2- 5 12 R1OUT V- 6 11 T1IN T2OUT 7 10 T2IN R2IN 8 9 R2OUT Pin Descriptions PIN # PIN NAME 1 C1+ 2 V+ DESCRIPTION External capacitor “+” for internal voltage doubler. Internally generated +10V (typical) supply. 3 C1- External capacitor “-” for internal voltage doubler. 4 C2+ External capacitor “+” internal voltage inverter. 5 C2- External capacitor “-” internal voltage inverter. 6 V- 7 T2OUT RS-232 Transmitter 2 output 10V (typical). 8 R2IN RS-232 Receiver 2 input, with internal 5k pulldown resistor to GND. 9 R2out Receiver 2 TTL/CMOS output. 10 T2IN Transmitter 2 TTL/CMOS input, with internal 400k pullup resistor to VCC . 11 T1IN Transmitter 1 TTL/CMOS input, with internal 400k pullup resistor to VCC . 12 R1OUT Internally generated -10V (typical) supply. Receiver 1 TTL/CMOS output. 13 R1IN RS-232 Receiver 1 input, with internal 5k pulldown resistor to GND. 14 T1OUT RS-232 Transmitter 1 output 10V (typical). 15 GND Supply Ground 16 VCC Positive Power Supply +5V 10%. Ordering Information PART NUMBER (Notes 1, 2) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG DWG. # ICL232CBEZ 0 to +70 16 Ld SOIC M16.3 ICL232CBEZT (Note 3) 0 to +70 16 Ld SOIC M16.3 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see product information page for ICL232. For more information on MSL, please see tech brief TB363. 3. Please refer to TB347 for details on reel specifications. FN3020 Rev 8.00 October 15, 2014 Page 2 of 8 ICL232 Absolute Maximum Ratings Thermal Information VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND -0.3V) < VCC < 6V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VCC -0.3V) < V+ < 12V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -12V < V- < (GND +0.3V) Input Voltages T1IN , T2IN . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V- -0.3V) < VIN < (V+ +0.3V) R1IN , R2IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Output Voltages T1OUT , T2OUT. . . . . . . . . . . . . . . . . . . . . . (V- -0.3V) < VTXOUT < (V+ +0.3V) R1OUT , R2OUT . . . . . . . . . . . . . . . . . .(GND -0.3V) < VRXOUT < (VCC +0.3V) Short Circuit Duration T1OUT , T2OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous R1OUT , R2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Thermal Resistance (Typical) JA (°C/W) JC (°C/W) SOIC Package (Note 4) . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . .+300°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating Conditions Temperature Ranges ICL232C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications otherwise specified. Test Conditions: VCC = +5V 10%, TA = Operating Temperature Range. Test Circuit as in Figure 2. Unless PARAMETER TEST CONDITIONS Transmitter Output Voltage Swing, TOUT T1OUT and T2OUT Loaded with 3kΩ to Ground Power Supply Current, ICC Outputs Unloaded, TA = +25°C MIN TYP MAX UNITS 5 9 10 V - 5 10 mA TIN , Input Logic Low, VlL - - 0.8 V TIN , Input Logic High, VlH 2.0 - - V - 15 200 µA Logic Pullup Current, IP T1IN , T2IN = 0V RS-232 Input Voltage Range, VIN -30 - +30 V Receiver Input Impedance, RIN VIN = 3V 3.0 5.0 7.0 kΩ Receiver Input Low Threshold, VlN (H-L) VCC = 5V, TA = +25°C 0.8 1.2 - V Receiver Input High Threshold, VIN (L-H) VCC = 5V, TA = +25°C Receiver Input Hysteresis, VHYST - 1.7 2.4 V 0.2 0.5 1.0 V 0.4 V TTL/CMOS Receiver Output Voltage Low, VOL IOUT = 3.2mA - 0.1 TTL/CMOS Receiver Output Voltage High, VOH IOUT = -1.0mA 3.5 4.6 - V Propagation Delay, tPD RS-232 to TTL - 0.5 - µs Instantaneous Slew Rate, SR CL = 10pF, RL = 3kΩ, TA = +25°C (Notes 5, 6) - - 30 V/µs Transition Region Slew Rate, SRT RL = 3kΩ, CL = 2500pF Measured from +3V to -3V or -3V to +3V - 3 - V/µs Output Resistance, ROUT VCC = V+ = V- = 0V, VOUT = 2V 300 - - Ω RS-232 Output Short Circuit Current, ISC T1OUT or T2OUT Shorted to GND - 10 - mA NOTES: 5. Limit is not production tested. The maximum was established via characterization and/or design simulations. 6. See Figure 7 for definition. FN3020 Rev 8.00 October 15, 2014 Page 3 of 8 ICL232 Test Circuits 1µF C3 1µF C1 +4.5V TO +5.5V INPUT + + - 1 C1+ VCC 16 2 V+ GND 15 C1- T1OUT 14 4 C2+ R1IN 13 5 C2- R1OUT 12 6 V- T1IN 11 TTL/CMOS INPUT 7 T2OUT T2IN 10 TTL/CMOS INPUT 3 1µF + C2 - 3kΩ 1µF C4 T1 OUTPUT RS-232 ±30V INPUT TTL/CMOS OUTPUT - + 3kΩ T2 OUTPUT RS-232 ±30V INPUT 8 R2OUT R2IN C1+ VCC 16 2 V+ GND 15 3 C1- T1OUT 14 4 C2+ R1IN 13 5 C2- R1OUT 12 6 V- T1IN 11 7 T2OUT T2IN 10 8 R2IN 9 R2OUT ROUT = VIN/I VIN = 2V TTL/CMOS OUTPUT 9 1 T2OUT A T1OUT FIGURE 2. GENERAL TEST CIRCUIT FIGURE 3. POWER-OFF SOURCE RESISTANCE CONFIGURATION Typical Performance Curves 10 500 9 V- SUPPLY 450 TA = +25°C EXTERNAL SUPPLY LOAD 400 1kW BETWEEN V+ + GND OR V- + GND 350 TRANSMITTER OUTPUT OUTPUT VOLTAGE (|V|) V+, V- SUPPLY IMPEDANCES (Ω) 550 OPEN CIRCUIT 300 250 GUARANTEED OPERATING RANGE V+ SUPPLY 8 V+ (VCC = 4.5V) 7 6 3 4 5 5 3 6 TA = 25°C TRANSMITTER OUTPUTS OPEN CIRCUIT 0 1 2 3 INPUT SUPPLY VOLTAGE VCC (V) - S2 V+ = 2VCC GND S3 C1- + C1 S4 6 7 8 9 10 VOLTAGE INVERTER VCC + 5 FIGURE 5. V+, V- OUTPUT VOLTAGES vs LOAD CURRENT VOLTAGE DOUBLER S1 4 |ILOAD| (mA) FIGURE 4. V+, V- OUTPUT IMPEDANCES vs VCC C1+ V- (VCC = 5V) V- (VCC = 4.5V) 4 200 150 V+ (VCC = 5V) S5 C2+ GND + C3 VCC S6 GND S7 C2- + C2 S8 C4 V- = -(V+) RC OSCILLATOR FIGURE 6. DUAL CHARGE PUMP FN3020 Rev 8.00 October 15, 2014 Page 4 of 8 ICL232 Detailed Description V+ The ICL232 is a dual RS-232 transmitter/receiver powered by a single +5V power supply which meets all ElA RS232C specifications and features low power consumption. Figure 1 illustrates the major elements of the ICL232. The circuit is divided into three sections: a voltage doubler/inverter, dual transmitters, and dual receivers. VCC 400kΩ 300Ω TXIN TOUT GND < TXIN < VCC V- < VTOUT < V+ V- FIGURE 8. TRANSMITTER Voltage Converter Receivers An equivalent circuit of the dual charge pump is illustrated in Figure 6. The receiver inputs accept up to 30V while presenting the required 3kΩ to 7kΩ input impedance even it the power is off (VCC = 0V). The receivers have a typical input threshold of 1.3V which is within the 3V limits, known as the transition region, of the RS-232 specification. The receiver output is 0V to VCC . The output will be low whenever the input is greater than 2.4V and high whenever the input is floating or driven between +0.8V and -30V. The receivers feature 0.5V hysteresis to improve noise rejection. The voltage quadrupler contains two charge pumps which use two phases of an internally generated clock to generate +10V and -10V. The nominal clock frequency is 16kHz. During phase one of the clock, capacitor C1 is charged to VCC . During phase two, the voltage on C1 is added to VCC , producing a signal across C2 equal to twice VCC . At the same time, C3 is also charged to 2VCC , and then during phase one, it is inverted with respect to ground to produce a signal across C4 equal to -2VCC . The voltage converter accepts input voltages up to 5.5V. The output impedance of the doubler (V+) is approximately 200Ω, and the output impedance of the inverter (V-) is approximately 450Ω . Typical graphs are presented which show the voltage converters output vs input voltage and output voltages vs load characteristics. The test circuit (Figure 2) uses 1µF capacitors for C1 to C4, however, the value is not critical. Increasing the values of C1 and C2 will lower the output impedance of the voltage doubler and inverter, and increasing the values of the reservoir capacitors, C3 and C4, lowers the ripple on the V+ and V- supplies. T1IN, T2IN 90% 10% T1OUT, T2OUT tf Instantaneous Slew Rate (SR) VOH tr RXIN ROUT -30V < RXIN < +30V 5kΩ (0.8) (VOH - VOL) (0.8) (VOL - VOH) = or tr tf Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS-232 outputs. The input logic threshold is about 26% of VCC , or 1.3V for VCC = 5V. A logic 1 at the input results in a voltage of between -5V and V- at the output, and a logic 0 results in a voltage between +5V and (V+ - 0.6V). Each transmitter input has an internal 400kΩ pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RS-232C specification of 5V minimum with the worst case conditions of: both transmitters driving 3kΩ minimum load impedance, VCC = 4.5V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 30V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 300Ω with 2V applied to the outputs and VCC = 0V. GND < VROUT < VCC GND FIGURE 9. RECEIVER T1IN, T2IN OR R1IN, R2IN T1OUT, T2OUT OR R1OUT, R2OUT VOH VOL tPHL VOL FIGURE 7. SLEW RATE DEFINITION FN3020 Rev 8.00 October 15, 2014 VCC Average Propagation Delay = tPLH tPHL + tPLH 2 FIGURE 10. PROPAGATION DELAY DEFINITION Applications The ICL232 may be used for all RS-232 data terminal and communication links. It is particularly useful in applications where 12V power supplies are not available for conventional RS-232 interface circuits. The applications presented represent typical interface configurations. A simple duplex RS-232 port with CTS/RTS handshaking is illustrated in Figure 11. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) is generated by driving them through a 5kΩ resistor connected to V+. Page 5 of 8 ICL232 +5V C1 + 1µF C2 + 1µF TD 16 1 5kΩ 3 ICL232 4 6 5 T1 11 INPUTS RTS OUTPUTS 12 TTL/CMOS RD 9 + 14 T2 10 CTS - C3 + 1µF 5kΩ 2 7 13 R2 R1 15 8 In applications requiring four RS-232 inputs and outputs (Figure 12), note that each circuit requires two charge pump capacitors (C1 and C2) but can share common reservoir capacitors (C3 and C4). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. CTR (20) DATA TERMINAL READY DSRS (24) DATA SIGNALING RATE SELECT C4 1µF RS-232 INPUTS AND OUTPUTS TD (2) TRANSMIT DATA RTS (4) REQUEST TO SEND RD (3) RECEIVE DATA CTS (5) CLEAR TO SEND SIGNAL GROUND (7) FIGURE 11. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS HANDSHAKING 1 C1 + 1µF TD INPUTS OUTPUTS TTL/CMOS RTS RD 4 ICL232 3 T1 11 14 T2 10 CTS TD (2) TRANSMIT DATA 7 RTS (4) REQUEST TO SEND 13 12 9 + C2 - 1µF 5 R2 R1 RD (3) RECEIVE DATA 8 CTS (5) CLEAR TO SEND 15 6 - 2 C3 + + C4 V- V+ 2µF 6 2 - 2 µF 16 +5V RS-232 INPUTS AND OUTPUTS ICL232 C1 + 1µF DTR 1 4 3 5 10 INPUTS DSRS OUTPUTS 12 TTL/CMOS DCD R1 T1 11 9 14 T2 7 13 R2 R1 15 8 + C2 - 1µF DTR (20) DATA TERMINAL READY DSRS (24) DATA SIGNALING RATE SELECT DCD (8) DATA CARRIER DETECT R1 (22) RING INDICATOR SIGNAL GROUND (7) FIGURE 12. COMBINING TWO ICL232s FOR 4 PAIRS OF RS-232 INPUTS AND OUTPUTS FN3020 Rev 8.00 October 15, 2014 Page 6 of 8 ICL232 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 15, 2014 FN3020.8 Updated the Ordering Information table on page 2 by removing several obsolete products and added Notes 2 and 3. Removed “CERDIP” and “PDIP” from Pin Configuration on page 2. Removed “ICL232I” and “ICL232M” lines under “Operating Conditions” on page 3. Removed “CERDIP” and “PDIP” lines under “Thermal Information” on page 3. Removed “Ceramic Package” line under “Maxium Junction Temperature” on page 3. Updated datasheet with Intersil new standards throughout entire datasheet. Added Revision history and About Intersil verbiage. Added Package Outline Drawing on page 8. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2001-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN3020 Rev 8.00 October 15, 2014 Page 7 of 8 ICL232 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e  B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N  16 0° 16 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN3020 Rev 8.00 October 15, 2014 Page 8 of 8