Datasheet
ICL3221EM, ICL3221EF
±15kV ESD Protected, +3.3V, 1µA, 250kbps, RS-232 Transmitters/Receivers
The ICL3221EM and ICL3221EF devices are 3.3V
powered RS-232 transmitters/receivers that meet
ElA/TIA-232 and V.28/V.24 specifications.
Additionally, they provide ±15kV ESD protection
(IEC61000-4-2 Air Gap and Human Body Model) on
transmitter outputs and receiver inputs (RS-232 pins).
Efficient on-chip charge pumps, coupled with manual
and automatic powerdown functions, reduce the
standby supply current to a 1µA trickle. Small footprint
packaging, and the use of small, low value capacitors
ensure board space savings as well. Data rates
greater than 250kbps are ensured at worst case load
conditions. These devices are fully compatible with
3.3V-only systems.
The ICL3221EM and ICL3221EF feature an
automatic power-down function that powers down the
on-chip power-supply and driver circuits. Power-down
occurs when an attached peripheral device is shut off
or the RS-232 cable is removed, and conserves
system power automatically without changes to the
hardware or operating system. These devices power
up again when a valid RS-232 voltage is applied to
any receiver input.
Features
• ESD protection for RS-232 I/O pins to ±15kV
(IEC61000)
• RS-232 compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 specifications at
3V
• Latch-up free
• On-chip voltage converters require only four
external 0.1µF capacitors
• Manual and automatic powerdown features
• Receiver hysteresis for improved noise immunity
• Assured minimum data rate: 250kbps
• Power supply range : single +3.0V to +3.6V
• Low supply current in powerdown state: 1µA
• Pb-free (RoHS compliant)
Applications
• Any system requiring RS-232 communication ports
○ Battery powered, hand-held, and portable
equipment
Table 1 summarizes the features of the ICL3221EM
and ICL3221EF.
○ Modems, printers, and other peripherals
Related Literature
For a full list of related documents, visit our website:
• ICL3221EM, ICL3221EF device pages
+3.3V
C1
0.1µF
C2
0.1µF
T1IN
TTL/CMOS
Logic Levels
R1OUT
+
0.1µF
2
+
4
C1+
15
VCC
C15
C2+
+
6
C2-
V+
+ C3
0.1µF
V- 7
T1
11
3
13
9
8
C4
+ 0.1µF
T1OUT
R1IN
RS-232
Levels
5kΩ
R1
1 EN
FORCEOFF
12
FORCEON
GND
INVALID
16
10
VCC
To Power
Control Logic
14
Figure 1. Typical Operating Circuit
FN7552 Rev.2.00
May.29.19
Page 1 of 22
ICL3221EM, ICL3221EF
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
2.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
3.
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.
Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.1.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
5.
Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Charge Pump Abs Max Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Powerdown Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Software Controlled (Manual) Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
INVALID Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Receiver ENABLE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation Down to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmitter Outputs when Exiting Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interconnection with 3V and 5V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Compatible Replacements for 5V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
±15kV ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
5.4
Human Body Model (HBM) Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEC61000-4-2 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Air-Gap Discharge Test Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Discharge Test Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
6.
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FN7552 Rev.2.00
May.29.19
Page 2 of 22
ICL3221EM, ICL3221EF
1.
1. Overview
Overview
1.1
Ordering Information
Part Number
(Notes 2, 3)
Part Marking
Temp Range (°C)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant)
Pkg. Dwg. #
ICL3221EMVZ
3221 EMVZ
-55 to +125
-
16 Ld TSSOP
M16.173
ICL3221EMVZ-T
3221 EMVZ
-55 to +125
2.5k
16 Ld TSSOP
M16.173
ICL3221EFVZ
3221 EFVZ
-40 to +125
-
16 Ld TSSOP
M16.173
ICL3221EFVZ-T
3221 EFVZ
-40 to +125
2.5k
16 Ld TSSOP
M16.173
ICL3221EFVZ-T7A
3221 EFVZ
-40 to +125
250
16 Ld TSSOP
M16.173
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the ICL3221EM, ICL3221EF device pages. For more information about MSL, see TB363.
Table 1.
Summary of Features
Part
Number
Number
of Tx
Number
of Rx
Data Rate
(kbps)
Receiver
Enable Function?
Ready
Output?
Manual
Power-Down?
Automatic Power-Down
Function?
ICL3221EM
1
1
250
Yes
No
Yes
Yes
ICL3221EF
1
1
250
Yes
No
Yes
Yes
FN7552 Rev.2.00
May.29.19
Page 3 of 22
ICL3221EM, ICL3221EF
1.2
1. Overview
Pin Configuration
16 Ld TSSOP
Top View
EN 1
C1+ 2
15 VCC
V+ 3
14 GND
C1- 4
13 T1OUT
C2+ 5
12 FORCEON
C2- 6
11 T1IN
V- 7
R1IN 8
1.3
16 FORCEOFF
10 INVALID
9
R1OUT
Pin Descriptions
Pin
Pin
Number
EN
1
Function
Active low receiver enable control
C1+
2
External capacitor (voltage doubler) is connected to this lead.
V+
3
Internally generated positive transmitter supply (+5.5V).
C1-
4
External capacitor (voltage doubler) is connected to this lead.
C2+
5
External capacitor (voltage inverter) is connected to this lead.
C2-
6
External capacitor (voltage inverter) is connected to this lead.
V-
7
Internally generated negative transmitter supply (-5.5V).
R1IN
8
±15kV ESD protected, RS-232 compatible receiver inputs.
R1OUT
9
TTL/CMOS level receiver outputs.
INVALID
10
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
T1IN
11
TTL/CMOS compatible transmitter Inputs.
FORCEON
12
Active high input to override automatic powerdown circuitry thereby keeping transmitters active (FORCEOFF
must be high).
T1OUT
13
±15kV ESD protected, RS-232 level (nominally ±5.5V) transmitter outputs.
GND
14
Ground connection.
VCC
15
System power supply input (3.0V to 3.6V).
FORCEOFF
16
Active low to shut down transmitters and on-chip power supply that overrides any automatic circuitry and
FORCEON (see Table 5 on page 11).
FN7552 Rev.2.00
May.29.19
Page 4 of 22
ICL3221EM, ICL3221EF
2.
2. Specifications
Specifications
2.1
Absolute Maximum Ratings
Minimum
Maximum
Unit
VCC to Ground
Parameter
-0.3
6
V
V+ to Ground
-0.3
7
V
V- to Ground
+0.3
-7
V
14
V
6
V
±25
V
±13.2
V
VCC +0.3
V
V+ to VInput Voltages
TIN, FORCEOFF, FORCEON, EN
-0.3
RIN
Output Voltages
TOUT
ROUT, INVALID
-0.3
Short-Circuit Duration
Continuous
TOUT
(See “ESD Performance” on page 7)
ESD Rating
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical, Note 4)
θJA (°C/W)
16 Ld TSSOP Package
145
Note:
4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379.
Parameter
Minimum
Maximum Junction Temperature (Plastic Package)
Maximum Storage Temperature Range
-65
Pb-Free Reflow Profile
2.3
Maximum
Unit
+150
°C
+150
°C
see TB493
Recommended Operating Conditions
Parameter
Minimum
Maximum
Unit
+3.0
+3.6
V
ICL3221EM
-55
+125
°C
ICL3221EF
-40
+125
°C
Operating Voltage
Temperature Range
2.4
Electrical Specifications
Test conditions: VCC = 3.3V ±10%, C1 - C4 = 0.1µF; unless otherwise specified. Typicals at TA = +25°C. Boldface limits apply across the
operating temperature ranges, -55°C to +125°C (ICL3221EM) and -40°C to +125°C (ICL3221EF).
Parameter
Test Conditions
Temp
Min
(°C) (Note 6)
Typ
Max
(Note 6) Unit
DC Characteristics
Supply Current, Automatic
Power-Down
FN7552 Rev.2.00
May.29.19
All RIN Open, FORCEON = GND, FORCEOFF = VCC
Full
1.0
10
µA
Page 5 of 22
ICL3221EM, ICL3221EF
2. Specifications
Test conditions: VCC = 3.3V ±10%, C1 - C4 = 0.1µF; unless otherwise specified. Typicals at TA = +25°C. Boldface limits apply across the
operating temperature ranges, -55°C to +125°C (ICL3221EM) and -40°C to +125°C (ICL3221EF). (Continued)
Parameter
Test Conditions
Supply Current, Powerdown
FORCEOFF = GND
Supply Current, Automatic
Power-Down Disabled
All Outputs Unloaded,
FORCEON = FORCEOFF = VCC
VCC = 3.15V
Temp
Min
(°C) (Note 6)
Typ
Max
(Note 6) Unit
Full
1.0
10
µA
Full
0.3
1.8
mA
0.8
V
Logic and Transmitter Inputs and Receiver Outputs
Input Logic Threshold Low
TIN, FORCEON, FORCEOFF, EN
Input Logic Threshold High
TIN, FORCEON, FORCEOFF, EN
Input Leakage Current
TIN, FORCEON, FORCEOFF, EN
Full
±0.01
±10
µA
Output Leakage Current
FORCEOFF = GND or EN = VCC
Full
±0.05
±10
µA
Output Voltage Low
IOUT = 1.6mA
Full
-
0.4
V
Output Voltage High
IOUT = -1.0mA
Full
Full
VCC = 3.3V
Full
2.0
V
VCC - 0.6 VCC - 0.1
V
Automatic Powerdown (FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters
Power-up (see Figure 10)
Full
-2.7
2.7
V
Receiver Input Thresholds to
Disable Transmitters
Power-down (see Figure 10)
Full
-0.3
0.3
V
INVALID Output Voltage Low
IOUT = 1.6mA
Full
0.4
V
INVALID Output Voltage High
IOUT = -1.0mA
Full
VCC - 0.6
V
Receiver Threshold to
Transmitters Enabled Delay
(tWU)
25
100
µs
Receiver Positive or Negative
Threshold to INVALID High
Delay (tINVH)
25
1
µs
Receiver Positive or Negative
Threshold to INVALID Low
Delay (tINVL)
25
30
µs
Receiver Input
Input Voltage Range
25
-25
0.6
Input Threshold Low
VCC = 3.3V
25
Input Threshold High
VCC = 3.3V
25
1.2
25
1.5
Input Hysteresis
25
0.5
Input Resistance
25
3
5
V
V
2.4
V
V
7
kΩ
Transmitter Output
Output Voltage Swing
All transmitter outputs loaded with 3kΩ to ground
Full
±5.0
±5.4
V
Output Resistance
VCC = V+ = V- = 0V, transmitter output = ±2V
Full
300
10M
Ω
Output Short-Circuit Current
Full
VOUT = ±12V, VCC = 0V or 3V to 3.6V, automatic
power-down or FORCEOFF = GND
Full
Maximum Data Rate
RL = 3kΩ, CL = 1000pF, one transmitter switching
Full
Receiver Propagation Delay
Receiver input to receiver output,
CL = 150pF
tPHL
tPLH
Output Leakage Current
±35
±60
mA
±25
µA
Timing Characteristics
250
500
kbps
25
0.15
µs
25
0.15
µs
Receiver Output Enable Time
Normal operation
25
200
ns
Receiver Output Disable Time
Normal operation
25
200
ns
Transmitter Skew
tPHL to tPLH (Note 5)
25
100
1000
ns
Receiver Skew
tPHL to tPLH
25
50
1000
ns
FN7552 Rev.2.00
May.29.19
Page 6 of 22
ICL3221EM, ICL3221EF
2. Specifications
Test conditions: VCC = 3.3V ±10%, C1 - C4 = 0.1µF; unless otherwise specified. Typicals at TA = +25°C. Boldface limits apply across the
operating temperature ranges, -55°C to +125°C (ICL3221EM) and -40°C to +125°C (ICL3221EF). (Continued)
Parameter
Transition Region Slew Rate
Test Conditions
VCC = 3.3V,
RL = 3kΩ to 7kΩ,
Measured from 3V to
-3V or -3V to 3V
Temp
Min
(°C) (Note 6)
Typ
Max
(Note 6) Unit
CL = 150pF to 2500pF
25
4
30
V/µs
CL = 150pF to 1000pF
25
6
30
V/µs
ESD Performance
RS-232 Pins (TOUT, RIN)
All Other Pins
Human body model
25
±15
kV
IEC61000-4-2 contact discharge
25
±8
kV
IEC61000-4-2 air gap discharge
25
±15
kV
Human body model
25
±2
kV
Notes:
5. Transmitter skew is measured at the transmitter zero crossing points.
6. Parts are 100% tested at +25°C. Full temperature limits are established by bench and tester characterization.
FN7552 Rev.2.00
May.29.19
Page 7 of 22
ICL3221EM, ICL3221EF
3.
3. Typical Performance Curves
Typical Performance Curves
VCC = 3.3V, TA = +25°C.
25
VOUT+
4
20
2
Slew Rate (V/µs)
Transmitter Output Voltage (V)
6
1 Transmitter at 250kbps
1 or 2 Transmitters at 30kbps
0
-2
15
-SLEW
+SLEW
10
VOUT -
-4
-6
0
1000
2000
3000
4000
5000
5
0
1000
Load Capacitance (pF)
Figure 2. Transmitter Output Voltage vs Load
Capacitance
2000
3000
Load Capacitance (pF)
4000
5000
Figure 3. Slew Rate vs Load Capacitance
45
40
Supply Current (mA)
35
250kbps
30
25
20
120kbps
15
10
20kbps
5
0
0
1000
2000
3000
4000
5000
Load Capacitance (pF)
Figure 4. Supply Current vs Load Capacitance When Transmitting Data
FN7552 Rev.2.00
May.29.19
Page 8 of 22
ICL3221EM, ICL3221EF
4.
4. Application Information
Application Information
ICL3221EM and ICL3221EF interface ICs operate from a single +3V supply, ensure a 250kbps minimum data
rate, require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C
and V.28 specifications.
4.1
Charge Pump
The ICL3221EM and ICL3221EF use regulated on-chip dual charge pumps as voltage doublers, and voltage
inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V, which allows these devices to
maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient
on-chip power supplies require only four small, external 0.1µF capacitors for the voltage doubler and inverter
functions at VCC = 3.3V. See “Capacitor Selection” on page 14 and Table 6 on page 15 for capacitor
recommendations for other operating conditions. The charge pumps operate discontinuously (they turn off as
soon as the V+ and V- supplies are pumped up to the nominal values), and provides significant power savings.
4.1.1 Charge Pump Abs Max Ratings
These 3V to 5V RS-232 transceivers have been fully characterized for 3.0V to 3.6V operation, and at critical
points for 4.5V to 5.5V operation. Furthermore, load conditions were favorable using static logic states only.
The specified maximum values for V+ and V- are +7V and -7V, respectively. These limits apply for VCC values set
to 3.0V and 3.6V (see Table 2). For VCC values set to 4.5V and 5.5V, the maximum values for V+ and
V- can approach +9V and -7V, respectively (Table 3). The breakdown characteristics for V+ and V- were
measured with ±13V.
Table 2.
V+ and V- Values for VCC = 3.0V to 3.6V
C1(μF)
C2, C3, C4 (μF)
Load
T1IN
(Logic State)
0.1
0.1
Open
H
3kΩ // 1000pF
0.047
0.33
Open
3kΩ // 1000pF
1
1
Open
3kΩ // 1000pF
Table 3.
C1 (μF)
V+ (V)
V- (V)
VCC = 3.0V
VCC = 3.6V
VCC = 3.0V
VCC = 3.6V
5.80
6.56
-5.60
-5.88
L
5.80
6.56
-5.60
-5.88
2.4kbps
5.80
6.56
-5.60
-5.88
H
5.88
6.60
-5.56
-5.92
L
5.76
6.36
-5.56
-5.76
2.4kbps
6.00
6.64
-5.64
-5.96
H
5.68
6.00
-5.60
-5.60
L
5.68
6.00
-5.60
-5.60
2.4kbps
5.68
6.00
-5.60
-5.60
H
5.76
6.08
-5.64
-5.64
L
5.68
6.04
-5.60
-5.60
2.4kbps
5.84
6.16
-5.64
-5.72
H
5.88
6.24
-5.60
-5.60
L
5.88
6.28
-5.60
-5.64
2.4kbps
5.80
6.20
-5.60
-5.60
H
5.88
6.44
-5.64
-5.72
L
5.88
6.04
-5.64
-5.64
2.4kbps
5.92
6.40
-5.64
-5.64
V+ and V- Values for VCC = 4.5V to 5.5V
C2, C3, C4 (μF)
FN7552 Rev.2.00
May.29.19
Load
T1IN
(Logic State)
V+ (V)
VCC = 4.5V
V- (V)
VCC = 5.5V
VCC = 4.5V
VCC = 5.5V
Page 9 of 22
ICL3221EM, ICL3221EF
Table 3.
0.1
4. Application Information
V+ and V- Values for VCC = 4.5V to 5.5V (Continued)
0.1
Open
3kΩ // 1000pF
0.047
0.33
Open
3kΩ // 1000pF
1
1
Open
3kΩ // 1000pF
H
7.44
8.48
-6.16
-6.40
L
7.44
8.48
-6.16
-6.44
2.4kbps
7.44
8.48
-6.17
-6.44
H
7.76
8.88
-6.36
-6.72
L
7.08
8.00
-5.76
-5.76
2.4kbps
7.76
8.84
-6.40
-6.64
H
6.44
6.88
-5.80
-5.88
L
6.48
6.88
-5.84
-5.88
2.4kbps
6.44
6.88
-5.80
-5.88
H
6.64
7.28
-5.92
-6.04
L
6.24
6.60
-5.52
-5.52
2.4kbps
6.72
7.16
-5.92
-5.96
H
6.84
7.60
-5.76
-5.76
L
6.88
7.60
-5.76
-5.76
2.4kbps
6.92
7.56
-5.72
-5.76
H
7.28
8.16
-5.80
-5.92
L
6.44
6.84
-5.64
-6.84
2.4kbps
7.08
7.76
-5.80
-5.80
The resulting new maximum voltages at V+ and V- are listed in Table 4.
Table 4.
4.2
New Measured Withstanding Voltages
V+, V- to Ground
±13V
V+ to V-
20V
Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. These transmitters are coupled with the on-chip ±5.5V supplies and deliver true RS-232 levels
across a wide range of single supply system voltages.
The transmitter output disables and assumes a high impedance state when the device enters the powerdown
mode (see Table 5 on page 11). These outputs can be driven to ±12V when disabled.
All devices ensure a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one transmitter
operating at full speed. Under more typical conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one transmitter
easily operates at 900kbps.
Transmitter inputs float if left unconnected, and can cause ICC increases. Connect unused inputs to GND for best
performance.
4.3
Receivers
The ICL3221EM and ICL3221EF devices contain standard inverting receivers that three-state using the EN or
FORCEOFF control lines. The receivers convert RS-232 signals to CMOS output levels and accept inputs up to
±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 5 on page 11) even if the power is off
(VCC = 0V). The receivers’ Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease
errors due to slow input signal transitions.
The ICL3221EM’s and ICL3221EF’s inverting receivers are disabled only when EN is driven high (see Table 5).
Standard receivers driving powered down peripherals must be disabled to prevent current flow through the
peripheral’s protection diodes (see Figures 6 and 7 on page 12). When disabled, the receivers cannot be used for
wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 7.
FN7552 Rev.2.00
May.29.19
Page 10 of 22
ICL3221EM, ICL3221EF
4. Application Information
VCC
RXIN
-25V ≤ VRIN ≤ +25V
RXOUT
5kΩ
GND ≤ VROUT ≤ VCC
GND
Figure 5. Inverting Receiver Connections
4.4
Low Power Operation
These 3V devices require a nominal supply current of 0.3mA, during normal operation (not in powerdown mode),
which is considerably less than the 5mA to 11mA current required by comparable 5V RS-232 devices, allowing
you to reduce system power simply by switching to this new family.
4.5
Powerdown Functionality
The already low current requirement drops significantly when the device enters powerdown mode. In
power-down, supply current drops to 1µA, because the on-chip charge pump turns off (V+ collapses to VCC, Vcollapses to GND), and the transmitter outputs three-state. Inverting receiver outputs can disable in powerdown;
see Table 5 for details. This micro-power mode makes these devices ideal for battery powered and portable
applications.
4.5.1 Software Controlled (Manual) Powerdown
The ICL3221EM and ICL3221EF devices provide a pin that allows you to force the IC into the low power, standby
state. Driving this pin high enables normal operation, and driving it low forces the IC into its powerdown state.
Connect FORCEOFF to VCC if the powerdown function is not needed. Note: All the receiver outputs remain
enabled during shutdown (see Table 5). For the lowest power consumption during powerdown, the receivers
should also be disabled by driving the EN input high (see Figures 6 and 7).
Table 5.
Powerdown and Enable Logic Truth Table
RS-232 SIgnal
Present at
Receiver Input?
FORCEOFF
Input
FORCEON
Input
EN
Input
Transmitter
Outputs
Receiver
Outputs
INVALID
Output
L
Mode of Operation
ICL3221EM and ICL3221EF
No
H
H
L
Active
Active
No
H
H
H
Active
High-Z
L
Yes
H
L
L
Active
Active
H
Yes
H
L
H
Active
High-Z
H
No
H
L
L
High-Z
Active
L
Normal Operation
(Auto Powerdown Disabled)
Normal Operation
(Auto Powerdown Enabled)
Powerdown Due to Auto
Power-Down Logic
No
H
L
H
High-Z
High-Z
L
Yes
L
X
L
High-Z
Active
H
Manual Powerdown
Yes
L
X
H
High-Z
High-Z
H
Manual Powerdown with
Receiver Disabled
No
L
X
L
High-Z
Active
L
Manual Powerdown
No
L
X
H
High-Z
High-Z
L
Manual Powerdown with
Receiver Disabled
The ICL3221EM and ICL3221EF use a two pin approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high.
Under logic or software control, only the FORCEOFF input needs to be driven to switch between active and
powerdown modes. The FORCEON state is not critical because FORCEOFF overrides FORCEON. However, if
strictly manual control over powerdown is needed, you must strap FORCEON high to disable the automatic
powerdown circuitry.
FN7552 Rev.2.00
May.29.19
Page 11 of 22
ICL3221EM, ICL3221EF
4. Application Information
4.5.2 INVALID Output
The INVALID output always indicates whether a valid RS-232 signal is present at any of the receiver inputs (see
Table 5 on page 11), giving you a way to determine when the interface block should power down. If an interface
cable is disconnected and all the receiver inputs are floating (but pulled to GND by the internal receiver pull down
resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic
then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the
receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID
can also be used to indicate the DTR or RING INDICATOR signal as long as the other receiver inputs are floating
or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together
disables the automatic powerdown feature, and enables them to function as a manual SHUTDOWN (SHDN) input
(see Figure 8 on page 13).
VCC
VCC
Current
Flow
VCC
VOUT = VCC
Rx
Powered
Down
UART
Tx
SHDN = GND
GND
Old
RS-232 CHIP
Figure 6. Power Drain Through Powered Down Peripheral
VCC
Transition
Detector
To
Wake-Up
Logic
ICL324XE
VCC
R2OUTB
RX
Powered
Down
UART
VOUT = HI-Z
R2OUT
TX
R2IN
T1IN
T1OUT
FORCEOFF = GND
EN = VCC
Figure 7. Disabled Receivers Prevent Power Drain
FN7552 Rev.2.00
May.29.19
Page 12 of 22
ICL3221EM, ICL3221EF
4. Application Information
FORCEOFF
Power
Management
Logic
FORCEON
INVALID
ICL3221EM
ICL3221EF
I/O
UART
CPU
Figure 8. Connections for Manual Powerdown when No Valid Receiver Signals are Present
With any of the control schemes, the time required to exit power-down and resume transmission is only 100µs. A
mouse or other application may need more time to wake up from shutdown. If automatic power-down is being
used, the RS-232 device reenters powerdown if valid receiver levels are not reestablished within 30µs of the
ICL3221EM and ICL3221EF powering up. Figure 9 illustrates a circuit that prevents the ICL3221EM and
ICL3221EF from initiating automatic powerdown for 100ms after powering up. The delay gives the slow-to-wake
peripheral circuit time to reestablish valid RS-232 output levels.
Power
Management
Unit
Master Powerdown Line
0.1µF
FORCEOFF
1MΩ
FORCEON
ICL3221EM
ICL3221EF
Figure 9. Circuit to Prevent Auto Powerdown for 100ms After Forced Power-Up
4.5.3 Automatic Powerdown
Even greater power savings are available by using the ICL3221EM and ICL3221EF’s automatic powerdown
function. When no valid RS-232 voltages (see Figure 10) are sensed on any receiver input for 30µs, the
charge-pump and transmitters powerdown and reduce supply current to 1µA. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is
disconnected. The ICL3221EM and ICL3221EF power back up whenever they detect a valid RS-232 voltage level
on any receiver input, which provides additional system power savings without changes to the existing operating
system.
FN7552 Rev.2.00
May.29.19
Page 13 of 22
ICL3221EM, ICL3221EF
4. Application Information
2.7V
Valid RS-232 Level - ICL3221EM and ICL3221EF are Active
Indeterminate - Powerdown Can Occur
0.3V
Invalid Level - Powerdown Occurs
After 30µs
-0.3V
Indeterminate - Powerdown Can Occur
-2.7V
Valid RS-232 Level - ICL3221EM and ICL3221EF are Active
Figure 10. Definition of Valid RS-232 Receiver Levels
Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF input is high. Tying
FORCEON high disables automatic powerdown, but manual powerdown is always available using the overriding
FORCEOFF input. Table 5 on page 11 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an INVALID output signal that switches low to indicate that
invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 11). INVALID switches
high 1µs after detecting a valid RS-232 level on a receiver input. INVALID operates in all modes (forced or
automatic power-down, or forced on), so it is also useful for systems employing manual powerdown circuitry.
When automatic powerdown is used, INVALID = 0 indicates that the ICL3221EM and ICL3221EF are in
power-down mode.
The time to recover from automatic powerdown mode is typically 100µs.
Invalid
} Region
Receiver
Inputs
Transmitter
Outputs
INVALID
Output
VCC
0
tINVL
AUTOPWDN
tINVH
PWR UP
V+
VCC
0
V-
Figure 11. Automatic Powerdown and INVALID Timing Diagrams
4.6
Receiver ENABLE Control
The ICL3221EM and ICL3221EF also feature an EN input to control the receiver outputs. Driving EN high
disables all the inverting (standard) receiver outputs placing them in a high impedance state, which is useful to
eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a
powered down (VCC = GND) peripheral (see Figure 6 on page 12).
4.7
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages, see Table 6 on page 15
for capacitor values. Do not use values smaller than those listed in Table 6. Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can
be increased without increasing C1’s value; however, do not increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
FN7552 Rev.2.00
May.29.19
Page 14 of 22
ICL3221EM, ICL3221EF
4. Application Information
When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s Equivalent Series Resistance
(ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
Table 6.
4.8
Required Capacitor Values
VCC (V)
C1 (µF)
C2, C3, C4 (µF)
3.0 to 3.6
0.1
0.1
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
4.9
Operation Down to 2.7V
The ICL3221EM and ICL3221EF transmitter outputs meet RS-562 levels (±3.7V), at full data rate, with VCC as low
as 2.7V. RS-562 levels typically ensure interoperability with RS-232 devices.
4.10
Transmitter Outputs when Exiting Powerdown
Figure 12 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients.
Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note: The transmitters enable only when the
magnitude of the supplies exceed approximately 3V.
5V/Div
FORCEOFF
T1
2V/Div
T2
VCC = +3.3V
C1 - C4 = 0.1µF
Time (20µs/Div)
Figure 12. Transmitter Outputs When Exiting Powerdown
FN7552 Rev.2.00
May.29.19
Page 15 of 22
ICL3221EM, ICL3221EF
4.11
4. Application Information
High Data Rates
The ICL3221EM and ICL3221EF maintain the RS-232 ±5V minimum transmitter output voltages even at high data
rates. Figure 13 shows a transmitter loopback test circuit, and Figure 14 shows the loopback test result at
120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF at
120kbps. Figure 15 shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at
250kbps. The static transmitters were also loaded with an RS-232 receiver.
VCC
+
0.1µF
+
C1
C1+
C1-
+
C2
VCC
V+
ICL3221EM
ICL3221EF
+
C3
V-
C2+
C4
+
C2TIN
ROUT
EN
VCC
TOUT
1000pF
RIN
5k
FORCEOFF
Figure 13. Transmitter Loopback Test Circuit
5V/Div
5V/Div
T1IN
T1IN
T1OUT
T1OUT
R1OUT
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
VCC = +3.3V
C1 - C4 = 0.1µF
5µs/Div
2µs/Div
Figure 14. Loopback Test at 120kbps
4.12
Figure 15. Loopback Test at 250kbps
Interconnection with 3V and 5V Logic
The ICL3221EM and ICL3221EF directly interface with 5V CMOS and TTL logic families. With the ICL3221EM
and ICL3221EF at 3.3V, and the logic supply at 5V, AC, HC, and CD4000 outputs can drive ICL3221EM and
ICL3221EF inputs, but ICL3221EM and ICL3221EF outputs do not reach the minimum VIH for these logic families.
See Table 7 for more information.
Table 7.
Logic Family Compatibility with Various Supply Voltages
System Power-Supply Voltage (V)
VCC Supply Voltage (V)
3.3
3.3
FN7552 Rev.2.00
May.29.19
Compatibility
Compatible with all CMOS families.
Page 16 of 22
ICL3221EM, ICL3221EF
4.13
4. Application Information
Pin Compatible Replacements for 5V Devices
The ICL3221EM and ICL3221EF are pin compatible with existing 5V RS-232 transceivers (see the “Features”
section on page 1 for details), which coupled with the low ICC and wide operating supply range, make the
ICL3221EM and ICL3221EF potential lower power, higher performance drop-in replacements for existing 5V
applications. As long as the ±5V RS-232 output swings are acceptable, and transmitter input pull-up resistors are
not required, the ICL3221EM and ICL3221EF should work in most 5V applications.
When replacing a device in an existing 5V application, it is acceptable to terminate C3 to VCC as shown in Figure 1
on page 1. Terminate C3 to GND if possible, as slightly better performance results from this configuration.
FN7552 Rev.2.00
May.29.19
Page 17 of 22
ICL3221EM, ICL3221EF
5.
5. ±15kV ESD Protection
±15kV ESD Protection
All pins on the ICL3221EM and ICL3221EF devices include ESD protection structures, but the families
incorporate advanced structures that allow the RS-232 pins (transmitter outputs and receiver inputs) to survive
ESD events up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically
connect to an exposed port on the exterior of the finished product. Touching the port pins or connecting a cable
can cause an ESD event that might destroy unprotected ICs. The ESD structures protect the device whether or
not it is powered up, protect without allowing any latch-up mechanism to activate, and do not interfere with
RS-232 signals as large as ±25V.
5.1
Human Body Model (HBM) Testing
The Human Body Model (HBM) test method emulates the ESD event delivered to an IC during human handling.
The tester delivers the charge through a 1.5kΩ current limiting resistor so the test is less severe than the
IEC61000 test, which uses a 330Ω limiting resistor. The HBM method determines an IC’s ability to withstand the
ESD transients typically present during handling and manufacturing. Due to the random nature of these events,
each pin is tested with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD
events to ±15kV.
5.2
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most
likely to suffer an ESD event are those that are exposed to the outside world (the RS-232 pins in this case), and
the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin
combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that
is much more severe than the HBM test. The extra ESD protection built into this device’s RS-232 pins allows the
design of equipment meeting Level 4 criteria without the need for additional board level protection on the RS-232
port.
5.3
Air-Gap Discharge Test Method
For the air-gap discharge test method, a charged probe tip moves toward the IC pin until the voltage arcs to it.
The current waveform delivered to the IC pin depends on factors such as approach speed, humidity, and
temperature, so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap
discharges.
5.4
Contact Discharge Test Method
During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, and
eliminate the variables associated with the air-gap discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages higher than ±8kV. All “E” family devices survive ±8kV
contact discharges on the RS-232 pins.
FN7552 Rev.2.00
May.29.19
Page 18 of 22
ICL3221EM, ICL3221EF
6.
6. Die Characteristics
Die Characteristics
Substrate Potential (Powered Up)
GND
Transistor Count
286
Process
Si Gate CMOS
FN7552 Rev.2.00
May.29.19
Page 19 of 22
ICL3221EM, ICL3221EF
7.
7. Revision History
Revision History
Rev.
Date
2.00
May.29.19
Applied new formatting.
Update links throughout document.
Updated Ordering Information table by adding tape and reel parts and updating notes.
Added “Charge Pump Abs Max Ratings” on page 9.
Removed About Intersil section.
Updated disclaimer.
1.00
Oct.13.16
Updated datasheet with new standards.
In the first sentence on page 1 changed “3.0V” to “3.3V”.
Removed second Features bullet on page 1.
Removed PDAs, palmtops, notebooks, laptops, digital cameras, cellular/mobile phones application references
on page 1.
Added ICL3221EF information throughout datasheet.
Added Revision History and About Intersil sections.
Updated M16.173 package outline drawing to the most current revision, changes are as follows:
-Convert to new POD format by moving dimensions from table onto drawing and adding land pattern.
No
dimension changes
FN7552 Rev.2.00
May.29.19
Description
Page 20 of 22
ICL3221EM, ICL3221EF
8.
8. Package Outline Drawing
Package Outline Drawing
For the most recent package outline drawing, see M16.173.
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.65
0.09-0.20
END VIEW
TOP VIEW
H
1.00 REF
- 0.05
C
1.20 MAX
SEATING
PLANE
0.90 +0.15/-0.10
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
FN7552 Rev.2.00
May.29.19
Page 21 of 22
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