ICL7660CBAZ-T

DATASHEET ICL7660S, ICL7660A FN3179 Rev 7.00 January 23, 2013 Super Voltage Converters The ICL7660S and ICL7660A Super Voltage Converters are monolithic CMOS voltage conversion ICs that guarantee significant performance advantages over other similar devices. They are direct replacements for the industry standard ICL7660 offering an extended operating supply voltage range up to 12V, with lower supply current. A Frequency Boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in the “Electrical Specifications” section on page 3. Critical parameters are guaranteed over the entire commercial and industrial temperature ranges. The ICL7660S and ICL7660A perform supply voltage conversions from positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V. Only two non-critical external capacitors are needed, for the charge pump and charge reservoir functions. The ICL7660S and ICL7660A can be connected to function as a voltage doubler and will generate up to 22.8V with a 12V input. They can also be used as a voltage multipliers or voltage dividers. Each chip contains a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5.0V. This frequency can be lowered by the addition of an external capacitor to the “OSC” terminal, or the oscillator may be over-driven by an external clock. The “LV” terminal may be tied to GND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (3.5V to 12V), the LV pin is left floating to prevent device latchup. Features • Guaranteed Lower Max Supply Current for All Temperature Ranges • Wide Operating Voltage Range: 1.5V to 12V • 100% Tested at 3V • Boost Pin (Pin 1) for Higher Switching Frequency • Guaranteed Minimum Power Efficiency of 96% • Improved Minimum Open Circuit Voltage Conversion Efficiency of 99% • Improved SCR Latchup Protection • Simple Conversion of +5V Logic Supply to ±5V Supplies • Simple Voltage Multiplication VOUT = (-)nVIN • Easy to Use; Requires Only Two External Non-Critical Passive Components • Improved Direct Replacement for Industry Standard ICL7660 and Other Second Source Devices • Pb-Free Available (RoHS Compliant) Applications • Simple Conversion of +5V to ±5V Supplies • Voltage Multiplication VOUT = ±nVIN • Negative Supplies for Data Acquisition Systems and Instrumentation • RS232 Power Supplies • Supply Splitter, VOUT = ±VS In some applications, an external Schottky diode from VOUT to CAP- is needed to guarantee latchup free operation (see Do’s and Dont’s section on page 8). Pin Configurations ICL7660A (8 LD PDIP, SOIC) TOP VIEW ICL7660S (8 LD PDIP, SOIC) TOP VIEW BOOST 1 8 V+ CAP+ 2 7 OSC GND 3 6 CAP- 4 5 FN3179 Rev 7.00 January 23, 2013 NC 1 8 V+ CAP+ 2 7 OSC LV GND 3 6 LV VOUT CAP- 4 5 VOUT Page 1 of 13 ICL7660S, ICL7660A Ordering Information PART NUMBER (NOTE 3) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICL7660SCBA (Note 1) 7660 SCBA 0 to +70 8 Ld SOIC M8.15 ICL7660SCBAZ (Notes 1, 2) 7660 SCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15 ICL7660SCPA 7660S CPA 0 to +70 8 Ld PDIP E8.3 ICL7660SCPAZ (Note 2) 7660S CPAZ 0 to +70 8 Ld PDIP (Pb-free; Note 4) E8.3 ICL7660SIBA (Note 1) 7660 SIBA -40 to +85 8 Ld SOIC M8.15 ICL7660SIBAZ (Notes 1, 2) 7660 SIBAZ -40 to +85 8 Ld SOIC (Pb-free) M8.15 ICL7660SIPA 7660 SIPA -40 to +85 8 Ld PDIP E8.3 ICL7660SIPAZ (Note 2) 7660S IPAZ -40 to +85 8 Ld PDIP (Pb-free; Note 4) E8.3 ICL7660ACBA (Note 1) 7660ACBA 0 to 70 8 Ld SOIC (N) M8.15 ICL7660ACBAZA (Notes 1, 2) 7660ACBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15 ICL7660ACPA 7660ACPA 0 to 70 8 Ld PDIP E8.3 ICL7660ACPAZ (Note 2) 7660ACPAZ 8 Ld PDIP (Pb-free; Note 4) E8.3 ICL7660AIBA (Note 1) 7660AIBA -40 to 85 0 to 70 8 Ld SOIC (N) M8.15 ICL7660AIBAZA (Notes 1, 2) 7660AIBAZ -40 to 85 8 Ld SOIC (N) (Pb-free) M8.15 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ICL7660S, ICL7660A. For more information on MSL, please see Tech Brief TB363. 4. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications. FN3179 Rev 7.00 January 23, 2013 Page 2 of 13 ICL7660S, ICL7660A Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V LV and OSC Input Voltage (Note 5) V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V Current into LV (Note 5) V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA Output Short Duration VSUPPLY  5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Thermal Resistance (Typical, Notes 6, 7) JA (°C/W) Operating Conditions JC (°C/W) 8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . 110 59 8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . 160 48 Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications. Temperature Range ICL7660SI, ICL7660AI . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C ICL7660SC, ICL7660AC . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to “power up” of ICL7660S and ICL7660A. 6. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is taken at the package top center. 8. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications. Electrical Specifications PARAMETER Supply Current (Note 11) ICL7660S and ICL7660A, V+ = 5V, TA = +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit” on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified. MIN (Note 9) TYP MAX (Note 9) UNITS RL =  , +25°C - 80 160 µA 0°C < TA < +70°C - - 180 µA -40°C < TA < +85°C - - 180 µA -55°C < TA < +125°C - - 200 µA SYMBOL I+ TEST CONDITIONS Supply Voltage Range - High (Note 12) V+H RL = 10k, LV Open, TMIN < TA < TMAX 3.0 - 12 V Supply Voltage Range - Low V+L RL = 10k, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 V IOUT = 20mA - 60 100  IOUT = 20mA, 0°C < TA < +70°C - - 120  IOUT = 20mA, -25°C < TA < +85°C - - 120  IOUT = 20mA, -55°C < TA < +125°C - - 150  IOUT = 3mA, V+ = 2V, LV = GND, 0°C < TA < +70°C - - 250  IOUT = 3mA, V+ = 2V, LV = GND, -40°C < TA < +85°C - - 300  IOUT = 3mA, V+ = 2V, LV = GND, -55°C < TA < +125°C - - 400  COSC = 0, Pin 1 Open or GND 5 10 - kHz COSC = 0, Pin 1 = V+ - 35 - kHz RL = 5k 96 98 - % TMIN < TA < TMAX RL = 5k 95 97 - - RL =  99 99.9 - % Output Source Resistance Oscillator Frequency (Note 10) Power Efficiency Voltage Conversion Efficiency FN3179 Rev 7.00 January 23, 2013 ROUT fOSC PEFF VOUTEFF Page 3 of 13 ICL7660S, ICL7660A Electrical Specifications PARAMETER Oscillator Impedance ICL7660S and ICL7660A, V+ = 5V, TA = +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit” on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified. (Continued) MIN (Note 9) TYP MAX (Note 9) UNITS V+ = 2V - 1 - M V+ = 5V - 100 - k SYMBOL ZOSC TEST CONDITIONS ICL7660A, V+ = 3V, TA = 25°C, OSC = Free running, Test Circuit Figure 13, unless otherwise specified Supply Current (Note 13) Output Source Resistance Oscillator Frequency (Note 13) I+ ROUT fOSC V+ = 3V, RL =  , +25°C - 26 100 A 0°C < TA < +70°C - - 125 A -40°C < TA < +85°C - - 125 A V+ = 3V, IOUT = 10mA - 97 150  0°C < TA < +70°C - - 200  -40°C < TA < +85°C - - 200  V+ = 3V (same as 5V conditions) 5.0 8 - kHz 0°C < TA < +70°C 3.0 - - kHz -40°C < TA < +85°C 3.0 - - kHz NOTES: 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, on the order of 5pF. 11. The Intersil ICL7660S and ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in existing designs that incorporate an external diode with no degradation in overall circuit performance. 12. All significant improvements over the industry standard ICL7660 are highlighted. 13. Derate linearly above 50°C by 5.5mW/°C. FN3179 Rev 7.00 January 23, 2013 Page 4 of 13 ICL7660S, ICL7660A Functional Block Diagram 8 OSC LV 7 Q1 VOLTAGE LEVEL TRANSLATOR OSCILLATOR AND DIVIDE-BY2 COUNTER V+ 2 Q2 3 CAP+ GND 6 Q4 INTERNAL SUPPLY REGULATOR 4 5 Q3 3 CAPVOUT SUBSTRATE LOGIC NETWORK 3 3 Typical Performance Curves See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 12 OUTPUT SOURCE RESISTANCE (Ω) 250 SUPPLY VOLTAGE (V) 10 8 SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) 6 4 2 0 TA = +125°C 200 TA = +25°C 150 TA = -55°C 100 50 0 -55 -25 0 25 50 100 125 0 2 4 FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE POWER CONVERSION EFFICIENCY (%) OUTPUT SOURCE RESISTANCE (Ω) 300 250 IOUT = 3mA, IOUT = 20mA, V+ = 5V V+ = 2V 150 IOUT = 20mA, V+ = 5V 100 50 IOUT = 20mA, V+ = 12V 0 -50 -25 0 25 50 75 TEMPERATURE (°C) FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE FN3179 Rev 7.00 January 23, 2013 8 10 12 FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE 350 200 6 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 100 125 98 96 94 92 V+ = 5V TA = +25°C IOUT = 1mA 90 88 86 84 82 80 100 1k 10k 50k OSC FREQUENCY fOSC (Hz) FIGURE 4. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSCILLATOR FREQUENCY Page 5 of 13 ICL7660S, ICL7660A Typical Performance Curves See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued) 20 V+ = 5V TA = +25°C 9 OSCILLATOR FREQUENCY fOSC (kHz) 8 7 6 5 4 3 2 1 18 16 14 V+ = 10V 12 10 V+ = 5V 8 0 10 COSC (pF) 100 V+ = 5V OUTPUT VOLTAGE (V) 0 25 50 75 100 TA = +25°C -1 -2 -3 -4 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 V+ = 5V 20 10 TA = +25°C 10 0 0 -5 0 10 125 FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE POWER CONVERSION EFFICIENCY (%) 1 20 30 LOAD CURRENT (mA) 0 40 10 20 30 40 50 60 LOAD CURRENT (mA) FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT 2 100 V+ = 2V TA = +25°C 90 1 POWER CONVERSION EFFICIENCY (%) OUTPUT VOLTAGE (V) -25 TEMPERATURE (°C) FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSCILLATOR CAPACITANCE 0 -55 1k SUPPLY CURRENT (mA) 1 0 -1 80 16 70 14 60 12 50 10 40 8 30 0 0 1 2 3 4 5 6 7 8 9 LOAD CURRENT (mA) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FN3179 Rev 7.00 January 23, 2013 4 TA = +25°C 10 -2 6 V+ = 2V 20 0 1.5 3.0 4.5 6.0 2 7.5 9.0 SUPPLY CURRENT (mA) (NOTE 12) OSCILLATOR FREQUENCY fOSC (kHz) 10 0 LOAD CURRENT (mA) FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT Page 6 of 13 ICL7660S, ICL7660A Typical Performance Curves OUTPUT RESISTANCE (Ω) See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued) 400 V+ = 5V TA = +25°C I = 10mA C1 = C2 = 1mF C1 = C2 = 10mF 300 C1 = C2 = 100mF 200 100 0 100 1k 10k 100k OSCILLATOR FREQUENCY (Hz) FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY NOTE: 14. These curves include, in the supply current, that current fed directly into the load RL from the V+ (see Figure 12). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7660S and ICL7660A, goes to the negative side of the load. Ideally, VOUT 2VIN, IS  2IL, so VIN x IS  VOUT x IL. IS V+ V+ C1 + 10µF - IS V+ 1 8 2 7 IL 3 6 RL 4 5 ICL7660S 1 (+5V) - -VOUT C2 10µF 2 C1 + 10µF 8 ICL7660A 7 3 6 4 5 IL RL COSC (NOTE) -VOUT + (+5V) C2 10µF + NOTE: For large values of COSC (>1000pF), the values of C1 and C2 should be increased to 100µF. FIGURE 12. ICL7660S TEST CIRCUIT NOTE: For large values of COSC (>1000pF) the values of C1 and C2 should be increased to 100F. FIGURE 13. ICL7660A TEST CIRCUIT FN3179 Rev 7.00 January 23, 2013 Page 7 of 13 ICL7660S, ICL7660A Detailed Description The ICL7660S and ICL7660A contain all the necessary circuitry to complete a negative voltage converter, with the exception of two external capacitors, which may be inexpensive 10µF polarized electrolytic types. The mode of operation of the device may best be understood by considering Figure 14, which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V+, for the half cycle, when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle). During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 to C2 such that the voltage on C2 is exactly V+, assuming ideal switches and no load on C2. The ICL7660S and ICL7660A approach this ideal situation more closely than existing non-mechanical circuits. 8 S1 S2 2 C1 3 C2 S4 S3 4 5 VOUT = -VIN 7 FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER In the ICL7660S and ICL7660A, the four switches of Figure 14 are MOS power switches; S1 is a P-Channel device; and S2, S3 and S4 are N-Channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their “ON” resistances. In addition, at circuit startup, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latch-up. This problem is eliminated in the ICL7660S and ICL7660A by a logic network that senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. The voltage regulator portion of the ICL7660S and ICL7660A is an integral part of the anti-latchup circuitry; however, its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation, the “LV” pin should be connected to GND, thus disabling the regulator. For supply voltages greater than 3.5V, the LV terminal must be left open to ensure latchup-proof operation and to prevent device damage. FN3179 Rev 7.00 January 23, 2013 In theory, a voltage converter can approach 100% efficiency if certain conditions are met: 1. The drive circuitry consumes minimal power. 2. The output switches have extremely low ON resistance and virtually no offset. 3. The impedance of the pump and reservoir capacitors are negligible at the pump frequency. The ICL7660S and ICL7660A approach these conditions for negative voltage conversion if large values of C1 and C2 are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined as shown in Equation 1: 1 E = --- C 1  V 1 2 – V 2 2  2 VIN 3 Theoretical Power Efficiency Considerations (EQ. 1) where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (see Figure 14) compared to the value of RL, there will be a substantial difference in the voltages, V1 and V2. Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. Do’s and Don’ts 1. Do not exceed maximum supply voltages. 2. Do not connect LV terminal to GND for supply voltage greater than 3.5V. 3. Do not short circuit the output to V+ supply for supply voltages above 5.5V for extended periods; however, transient conditions including start-up are okay. 4. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7660S and ICL7660A, and the + terminal of C2 must be connected to GND. 5. If the voltage supply driving the ICL7660S and ICL7660A has a large source impedance (25 to 30), then a 2.2µF capacitor from pin 8 to ground may be required to limit the rate of rise of input voltage to less than 2V/µs. 6. If the input voltage is higher than 5V and it has a rise rate more than 2V/µs, an external Schottky diode from VOUT to CAP- is needed to prevent latchup (triggered by forward biasing Q4’s body diode) by keeping the output (pin 5) from going more positive than CAP- (pin 4). 7. User should ensure that the output (pin 5) does not go more positive than GND (pin 3). Device latch-up will occur under these conditions. To provide additional protection, a 1N914 or similar diode placed in parallel with C2 will prevent the device from latching up under these conditions, when the load on VOUT creates a path to pull up VOUT before the IC is active (anode pin 5, cathode pin 3). Page 8 of 13 ICL7660S, ICL7660A charge the capacitors every cycle. Equation 4 shows a typical application where fOSC = 10kHz and C = C1 = C2 = 10µF: Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL7660S and ICL7660A for generation of negative supply voltages. Figure 15 shows typical connections to provide a negative supply where a positive supply of +1.5V to +12V is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltage below 3.5V. V+ 1 10µF + - 2 3 8 ICL7660S ICL7660A 4 1 R 0  2x23 + --------------------------------------------------- + 4xESR C1 + ESR C2 3 –6 5  10  10  10 (EQ. 4) R 0  46 + 20 + 5  ESR C Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/fPUMP x C1 term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10. 7 Output Ripple 6 RO 5 10µF + VOUT = -V+ 15A. VOUT V+ + ESR also affects the ripple voltage seen at the output. The peak-to-peak output ripple voltage is given by Equation 5: 1 V RIPPLE   ----------------------------------------- + 2ESR C2  I OUT 2  f  PUMP  C 2 15B. FIGURE 15. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT (EQ. 5) A low ESR capacitor will result in a higher performance output. Paralleling Devices The output characteristics of the circuit in Figure 15 can be approximated by an ideal voltage source in series with a resistance as shown in Figure 15B. The voltage source has a value of -(V+). The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 14), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is shown in Equation 2: Any number of ICL7660S and ICL7660A voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices, while each device requires its own pump capacitor, C1. The resultant output resistance is approximated in Equation 6: R 0  2   R SW1 + R SW3 + ESR C1  + 2  R SW2 + R SW4 + ESR C1   The ICL7660S and ICL7660A may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined as shown in Equation 7: 1 -------------------------------- + ESR C2 f PUMP  C 1 f OSC f PUMP = -------------2 (EQ. 2)  R SWX = MOSFET Switch Resistance  Combining the four RSWX terms as RSW, we see in Equation 3 that: 1 R 0  2xR SW + -------------------------------- + 4xESR C1 + ESR C2 f PUMP  C 1 (EQ. 3) RSW, the total switch resistance, is a function of supply voltage and temperature (see the output source resistance graphs, Figures 2, 3, and 11), typically 23 at +25°C and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP x C1) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net increase in output impedance when C1 > 10µF and is not long enough to fully FN3179 Rev 7.00 January 23, 2013 R OUT  of ICL7660S  R OUT = --------------------------------------------------------n  number of devices  (EQ. 6) Cascading Devices V OUT = – n  V IN  (EQ. 7) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S and ICL7660A ROUT values. Changing the ICL7660S and ICL7660A Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to alter the oscillator frequency. This can be achieved simply by one of several methods. By connecting the Boost Pin (Pin 1) to V+, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increased by approximately 3.5 times. The result is a decrease in the output impedance and ripple. Page 9 of 13 ICL7660S, ICL7660A This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller capacitors, such as 0.1µF, can be used in conjunction with the Boost Pin to achieve similar output currents compared to the device free running with C1 = C2 = 10µF or 100µF. (see Figure 11). Increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in Figure 16. In order to prevent device latchup, a 1k resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k pull-up resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be one-half of the clock frequency. Output transitions occur on the positive going edge of the clock. V+ Positive Voltage Doubling The ICL7660S and ICL7660A may be employed to achieve positive voltage doubling using the circuit shown in Figure 18. In this application, the pump inverter switches of the ICL7660S and ICL7660A are used to charge C1 to a voltage level of V+ -VF, where V+ is the supply voltage and VF is the forward voltage on C1, plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. The source impedance of the output (VOUT) will depend on the output current, but for V+ = 5V and an output current of 10mA, it will be approximately 60. V+ 1 V+ 2 10µF + 1 8 2 7 ICL7660S ICL7660A 3 - 4 1kΩ CMOS GATE 6 3 4 8 ICL7660S ICL7660A 7 D1 6 D2 5 + + 5 VOUT - - - C1 VOUT = (2V+) - (2VF) C2 10µF + NOTE: D1 AND D2 CAN BE ANY SUITABLE DIODE. FIGURE 18. POSITIVE VOLTAGE DOUBLER FIGURE 16. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICL7660S and ICL7660A at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 17. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor by which the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC and V+) will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10µF to 100µF). V+ 1 2 C1 + - 3 4 Combined Negative Voltage Conversion and Positive Supply Doubling Figure 19 combines the functions shown in Figure 15 and Figure 18 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be suitable, for example, for generating +9V and -5V from an existing +5V supply. In this instance, capacitors C1 and C3 perform the pump and reservoir functions, respectively, for negative voltage generation, while capacitors C2 and C4 are pump and reservoir, respectively, for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher, due to the finite impedance of the common charge pump driver at pin 2 of the device. 8 ICL7660S ICL7660A COSC 7 6 5 + VOUT C2 FIGURE 17. LOWERING OSCILLATOR FREQUENCY FN3179 Rev 7.00 January 23, 2013 Page 10 of 13 ICL7660S, ICL7660A V+ 1 2 C1 + - 3 ICL7660S ICL7660A 4 7 RL1 VOUT = -VIN 8 D1 + 6 + VOUT = V+ - V2 C2 2 + 50µF D2 V+ + 1 C3 5 - 50µF - RL2 VOUT = (2V+) (VFD1) - (VFD2) 3 50µF + C - 4 + 8 ICL7660S ICL7660A 4 7 6 5 V- D3 FIGURE 20. SPLITTING A SUPPLY IN HALF FIGURE 19. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Regulated Negative Voltage Supply In some cases, the output impedance of the ICL7660S and ICL7660A can be a problem, particularly if the load current varies substantially. The circuit of Figure 21 can be used to overcome this by controlling the input voltage, via an ICL7611 low-power CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICL7660S’s and ICL7660A’s output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL7660S and ICL7660A, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provide an output impedance of less than 5 to a load of 10mA. Voltage Splitting The bidirectional characteristics can also be used to split a high supply in half, as shown in Figure 20. The combined load will be evenly shared between the two sides, and a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 15, +15V can be converted, via +7.5 and -7.5, to a nominal -15V, although with rather high series output resistance (250). Other Applications Further information on the operation and use of the ICL7660S and ICL7660A may be found in application note AN051, “Principles and Applications of the ICL7660 CMOS Voltage Converter”. 50k +8V 56k 50k 100k - +8V 100 10µF ICL7611 + 1 2 ICL8069 + 100µF + - 3 8 ICL7660S ICL7660A 4 800k 7 6 5 250k VOLTAGE ADJUST VOUT + 100µF FIGURE 21. REGULATING THE OUTPUT VOLTAGE FN3179 Rev 7.00 January 23, 2013 Page 11 of 13 ICL7660S, ICL7660A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 1999-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3179 Rev 7.00 January 23, 2013 Page 12 of 13 ICL7660S, ICL7660A Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN3179 Rev 7.00 January 23, 2013 Page 13 of 13