ICM7242IPA

DATASHEET ICM7242 FN2866 Rev 5.00 September 14, 2015 Long Range Fixed Timer The ICM7242 is a CMOS timer/counter circuit consisting of an RC oscillator followed by an 8-bit binary counter. It will replace the 2242 in most applications, with a significant reduction in the number of external components. Features Three outputs are provided. They are the oscillator output, and buffered outputs from the first and eighth counters. • Cascadable Ordering Information • Wide Supply Voltage Range . . . . . . . . . . . . . . . 2V to 16V PART NUMBER (See Note) ICM7242IPAZ 7242 IBAZ • Monostable or Astable Operation • Low Supply Current . . . . . . . . . . . . . . . . . . . . 115µA at 5V • Pb-Free Plus Anneal Available (RoHS Compliant) 8 Ld PDIP** E8.3 Pinout 0 to +70 8 Ld SOIC M8.15 -25 to +85 8 Ld SOIC M8.15 -25 to +85 ICM7242CBAZ* 7242 CBAZ (No longer available or supported) ICM7242IBAZ* (No longer available or supported) • Timing From Microseconds to Days PKG. DWG. # PART TEMP. MARKING RANGE (°C) 7242 IPAZ PACKAGE (RoHS Compliant) • Replaces the 2242 in Most Applications *Add “-T” suffix for tape and reel. ICM7242 (8 LD PDIP, SOIC) TOP VIEW VDD 1 8 TB I/O 2 OUT 2 7 RC 128/256 OUT 3 6 TRIGGER VSS 4 5 RESET **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 FN2866 Rev 5.00 September 14, 2015 Page 1 of 11 ICM7242 Functional Block Diagram R1 50k + + R R3 50k Q Q S Q Q CL Q S Q CL Q CL S Q S Q CL Q S Q Q S Q CL Q 1 4 8 5 VDD VSS TB I/O RESET FN2866 Rev 5.00 September 14, 2015 Q CL R S - 7 CL S - R2 86k RC Q Q CL S 6 Q 2 3 TRIGGER ÷2 OUT ÷128/256 OUTPUT Page 2 of 11 ICM7242 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage (Note 1) Terminals (Pins 5, 6, 7, 8). . . . . . . . . . (VSS -0.3V) to (VDD +0.3V) Continuous Output Current (Each Output). . . . . . . . . . . . . . . . 50mA Thermal Resistance (Typical, Note2) JA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICM7242I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C ICM7242C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device before its supply is established and, that in multiple supply systems, the supply to the ICM7242 be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, TA = +25°C, R = 10k, C = 0.1µF, VSS = 0V, Unless Otherwise Specified PARAMETER SYMBOL Guaranteed Supply Voltage VDD Supply Current IDD TEST CONDITIONS MIN TYP MAX UNITS 2 - 16 V Reset - 125 - µA Operating, R = 10k, C = 0.1µF - 340 800 µA Operating, R = 1M, C = 0.1µF - 220 600 µA TB Inhibited, RC Connected to VSS - 225 - µA - 5 - % Timing Accuracy RC Oscillator Frequency Temperature Drift f/t Independent of RC Components - 250 - ppm/°C Time Base Output Voltage VOTB ISOURCE = 100µA - 3.5 - V ISINK = 1.0mA - 0.40 - V Time Base Output Leakage Current ITBLK RC = Ground - - 25 µA Trigger Input Voltage VTRIG VDD = 5V - 1.6 2.0 V VDD = 15V - 3.5 4.5 V VDD = 5V - 1.3 2.0 V VDD = 15V - 2.7 4.0 V - 10 - µA - 1 - MHz 2 6 - MHz - 13 - MHz Reset Input Voltage Trigger/Reset Input Current Max Count Toggle Rate VRST ITRIG, IRST fT VDD = 2V VDD = 5V Counter/Divider Mode VDD = 15V 50% Duty Cycle Input with Peak to Peak Voltages Equal to VDD and VSS Output Saturation Voltage VSAT All Outputs Except TB Output VDD = 5V, IOUT = 3.2mA - 0.22 0.4 V Output Sourcing Current ISOURCE VDD = 5V Terminals 2 and 3, VOUT = 1V - 300 - µA 10 - - pF 1k - 22M  MIN Timing Capacitor (Note 3) CT Timing Resistor Range (Note 3) RT VDD = 2 - 16V NOTE: 3. For design only, not tested. FN2866 Rev 5.00 September 14, 2015 Page 3 of 11 ICM7242 Test Circuit VDD ÷21 (RC/2) OUTPUT ÷28 (RC/256) OUTPUT 1 8 2 7 3 6 4 5 RESET TIME BASE INPUT/OUTPUT C VDD R TRIGGER TIME BASE PERIOD = 1.0RC; 1s = 1M x 1µF NOTE: 4. 21 and 28 outputs are inverters and have active pullups. Application Information Operating Considerations Shorting the RC terminal or output terminals to VDD may exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages). There is a limitation of 50pF maximum loading on the TB I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount. For greatest accuracy, use timing component values shown in Figure 8. For highest frequency operation it will be desirable to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz. The timing capacitor should be connected between the RC pin and the positive supply rail, VDD , as shown in Figure 1. When system power is turned off, any charge remaining on the capacitor will be discharged to ground through a large internal diode between the RC node and VSS. Do NOT reference the timing capacitor to ground, since there is no high current path in this direction to safely discharge the capacitor when power is turned off. The discharge current from such a configuration could potentially damage the device. When driving the counter section from an external clock, the optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp triangular, sine wave, etc., it will be necessary to “square up” the waveform; this can be done by using two CMOS inverters in series, operating from the same supply voltage as the ICM7242. The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and long range timers; it makes a much better low frequency oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals. Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the FN2866 Rev 5.00 September 14, 2015 external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket for the 2242 having these resistors. The timing diagram for the ICM7242 is shown in Figure 1. Assuming that the device is in the RESET mode, which occurs on power up or after a positive signal on the RESET terminal (if TRIGGER is low), a positive edge on the trigger input signal will initiate normal operation. The discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. After 128 negative timebase edges, the 28 output returns to the high state. TRIGGER INPUT (TERMINAL 6) TIMEBASE INPUT (TERMINAL 8) ÷2 OUTPUT (TERMINAL 2) 128RC ÷128/256 OUTPUT (TERMINAL 3) (ASTABLE OR “FREE RUN” MODE) 128RC ÷128/256 OUTPUT (TERMINAL 3) (MONOSTABLE OR “ONE SHOT” MODE) 128RC FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS FOR THE ICM7242 (COMPARE WITH FIGURE 5) VDD fIN/2 OUTPUTS fIN/256 fIN 1 8 2 7 3 6 4 5 >3/4 (V+)