ICS3771G-18LFT

DATASHEET ICS3771-18 DTV, STB CLOCK SOURCE Description Features The ICS3771-18 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS3771-18 uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. • • • • • • • For audio sampling clocks generated from 27 MHz, use the ICS661. Integrated Phase-Lock Loop Low jitter, high accuracy outputs 3.3 V operation Packaged in 16-pin TSSOP RoHS 6 (green and lead free) compliant packaging Exact (0 ppm) multiplication ratios Pin compatible to CY24204-3 Please contact IDT if you have a requirement for an input and output frequency not included in this document. IDT can rapidly modify this product to meet special requirements. Block Diagram VDDL VDD 27 MHz CLKIN AVDD CLK1 PLL Clock Synthesis Output Multiplexer and Dividers FS1:0 2 CLK2 REFOUT1 REFOUT2 2 GND IDT™ / ICS™ DTV, STB CLOCK SOURCE GNDA OE 1 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Pin Assignment Output Clock Selection Table (MHz) OE FS1 FS0 CLK1/CLK2 REFOUT1/REFOUT2 0 OFF* 27 1 OFF* 27 1 0 OFF* 27 0 1 1 OFF* 27 1 0 0 27 27 1 0 1 27.027 27 1 1 0 74.250 27 1 1 1 74.17582418 27 CLKIN 1 16 NC VDD 2 15 OE 0 0 0 0 AVDD 3 14 FS1 0 GND NC 4 13 GNDA 5 12 CLK1 GND 6 11 VDDL REFOUT2 7 10 REFOUT1 8 9 FS0 *OFF = output is driven HIGH. CLK2 16-pin TSSOP Pin Descriptions Pin Numbe r Pin Name Pin Type 1 CLKIN Input Reference clock input. Connect to a 27 MHz external clock. 2 VDD Power Power supply. 3 AVDD Power 4 NC – 5 GNDA Power Pin Description Power supply. Connect to 3.3 V. No connect. Leave floating. Analog ground. 6 GND Power Connect to ground. 7 REFOUT Output Reference Clock output 2. See table above. 8 REFOUT Output Reference Clock output 1. See table above. 9 CLK2 Output Selectable Clock output 2. See table above. 10 FS0 Input Frequency select pin 0. Weak internal pull-up. See table above. 11 VDDL Power Power supply. Connect to 3.3 V. 12 CLK1 Output Selectable Clock output 1. See table above 13 GND Power Connect to ground. 14 FS1 Input Frequency select pin 1. Weak internal pull-up. See table above. 15 OE Output 16 NC – IDT™ / ICS™ DTV, STB CLOCK SOURCE Output Enable pin. Weak internal pull-up. See table above. No connect. Leave floating. 2 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Application Information Series Termination Resistor signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS3771-18. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Clock output traces should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS3771-18 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS3771-18 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI and obtain the best signal integrity, the 33Ω series termination resistor should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other IDT™ / ICS™ DTV, STB CLOCK SOURCE 3 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS3771-18. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +3.465 V 0 Power Supply Voltage (measured in respect to GND) +3.135 3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Supply Current Symbol Conditions Min. Typ. Max. Units IVDD AVDD / VDD current 25 mA IVDDL VDDL current (VDDL = 3.47 V) 20 mA Output High Current IOH VOH = VDD-0.5, VDD/VDD = 3.3 V 12 24 mA Output Low Current IOL VOL = 0.5, VDD/VDD = 3.3 V 12 24 mA Input High Voltage VIH CMOS levels, 70% of VDD 0.7 Input Low Voltage VIL CMOS levels, 30% of VDD VDD 0.3 VDD CLOAD 15 pF Input Capacitance CIN 7 pF Internal Pull-up Resistor RUP 150 kΩ Max. Load Capacitance IDT™ / ICS™ DTV, STB CLOCK SOURCE 100 4 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units 27 MHz Crystal Frequency Edge Rate Rise Time tOR 20% to 80%, 15 pF load 0.8 1.4 V/ns Edge Rate Fall Time tOF 80% to 20%, 15 pF load 0.8 1.4 V/ns Output Duty Cycle tOD Clock Jitter 45 CLK1, CLK2 50 55 120 % ps p-p PLL Lock Time 3 ms Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 ° C/W θJA 1 m/s air flow 70 ° C/W θJA 3 m/s air flow 68 ° C/W 37 ° C/W θJC Marking Diagram 16 9 3771G18L ###### YYWW 1 8 Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “LF” denotes Pb (lead) free, RoHS compliant package. 4. Bottom marking: country of origin if not USA. IDT™ / ICS™ DTV, STB CLOCK SOURCE 5 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 16 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 A Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A 1 c -C e b S E A T IN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 3771G-18 3771G-18 Tubes 16-pin TSSOP 0 to +70° C 3771G-18T 3771G-18 Tape and Reel 16-pin TSSOP 0 to +70° C 3771G-18LF 3771G18L Tubes 16-pin TSSOP 0 to +70° C 3771G-18LFT 3771G18L Tape and Reel 16-pin TSSOP 0 to +70° C Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ DTV, STB CLOCK SOURCE 6 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Revision History Rev. Originator Date A R. Willner 04/19/06 Production part number assigned. B R. Willner 11/13/07 Clock input support only. IDT™ / ICS™ DTV, STB CLOCK SOURCE Description of Change 7 ICS3771-18 REV B 111307 ICS3771-18 DTV, STB CLOCK SOURCE SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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