DATASHEET
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
Description
Features
The ICS570 is a high-performance Zero Delay Buffer (ZDB)
which integrates IDT’s proprietary analog/digital Phase
Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of IDT’s ClockBlocksTM
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage requirements.
The zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both output
clocks, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other output. The device
incorporates an all-chip power down/tri-state mode that
stops the internal PLL and puts both outputs into a high
impedance state.
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The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
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The ICS570 A and B versions were designed to improve
input to output jitter from the original ICS570M version, and
are recommended for all new designs.
8-pin SOIC package
Available in Pb (lead) free package
Pin-for-pin replacement and upgrade to ICS570M
Functional equivalent to AV9170 (not a pin-for-pin
replacement)
Low input to output skew of 300 ps max (>60 MHz
outputs)
Ability to choose between 14 different multipliers from
0.5x to 32x
Output clock frequency up to 170 MHz at 3.3 V
Can recover degraded input clock duty cycle
Output clock duty cycle of 45/55
Power Down and Tri-State Mode
Passes spread spectrum clock modulation
Full CMOS clock swings with 25 mA drive capability at
TTL levels
Advanced, low power CMOS process
ICS570B has an operating voltage of 3.3 V (±5%)
ICS570A has an operating voltage of 5.0 V (±5%)
Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
d ivid e
by N
Phase
D e te c to r,
C h a rg e
Pum p,
and Loop
F ilte r
VCO
C LK
/2
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K o r C L K /2 (se e ta b le o n p a g e 2 )
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
1
ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Assignment
S1
1
8
CLK/2
VDD
2
7
CLK
GND
3
6
S0
ICLK
4
5
FBIN
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
S1 S0
FBIN from
CLK
CLK
#1
0
0
0
M
M
M
1
1
1
#6
0
M
1
0
M
1
0
M
1
CLK/2
FBIN from
CLK/2
CLK
ICS570B (3.3 V)
ICS570A (5.0 V)
CLK/2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
pin #7 pin #8 pin #7 pin #8
Power Down and Tri-State
x3
x1.5
x6
x3
x4
x2
x8
x4
x8
x4
x16
x8
x6
x3
x12
x6
x10
x5
x20
x10
x1
/2
x2
x1
x16
x8
x32
x16
x2
x1
x4
x2
0 = connect directly to ground
3.75 to 28
2.75 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
11 to 85
1.5 to 5
5.5 to 37.5
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
1.5 to 5
2.5 to 37.5
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
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ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
2
3
4
5
6
7
8
S1
VDD
GND
ICLK
FBIN
S0
CLK
CLK/2
Input
Power
Power
Input
Input
Input
Output
Output
Pin Description
Select 1 for output clock. Connect to GND, VDD, or float per decoding
Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding
Clock output per table above.
Clock output per table above. Low skew divide by two of pin 7 clock.
External Components
The ICS570 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the part to minimize lead inductance. No external power supply filtering is required for this device. A 33Ω
series terminating resistor can be used next to each output pin.
Recommended Circuit
S1
CLK
VDD
CLK/2
ICLK
GND
S0
Input
CLK
FBIN
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
ICLK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
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ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the
CLK/2 could be a falling edge compared with ICLK. IDT recommends using CLK/2 feedback whenever possible.
This will synchronize the rising edges of all three clocks.
Clock Period Jitter Tables (ICS570A)
All jitter values are considered typical measured at 25° C with 27Ω termination resistor and 15 pF loads on both CLK
and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to
improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
Multiplier
CLK = 50M
P to P
1 sigma
Multiplier
CLK/2 = 25M
P to P
1 sigma
0
0
M
M
M
1
1
1
M
1
0
M
1
0
M
1
8.333
6.25
3.125
4.167
2.5
25
1.5625
12.5
6x
8x
16x
12x
20x
2x
32x
4x
±115
±115
±120
±120
±120
±120
±120
±120
80
80
80
90
80
70
80
80
3x
4x
8x
6x
10x
1x
16x
2x
±65
±60
±55
±60
±60
±55
±50
±55
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
Multiplier
CLK = 100M
P to P
1 sigma
Multiplier
CLK/2 = 50M
P to P
1 sigma
0
0
M
M
M
1
1
1
M
1
0
M
1
0
M
1
16.667
12.5
6.25
8.333
5
50
3.125
25
6x
8x
16x
12x
20x
2x
32x
4x
±135
±140
±140
±140
±135
±120
±135
±130
100
100
110
110
100
90
100
90
3x
4x
8x
6x
10x
1x
16x
2x
±55
±50
±55
±55
±50
±50
±55
±65
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
Multiplier
CLK = 150M
P to P
1 sigma
Multiplier
CLK/2 = 75M
P to P
1 sigma
0
0
M
M
M
M
1
0
M
1
25
18.375
9.375
12.5
7.5
6x
8x
16x
12x
20x
±160
±165
±170
±160
±160
120
120
120
120
120
3x
4x
8x
6x
10x
±55
±55
±50
±55
±55
20
20
20
20
20
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
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ICS570
REV K 073007
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
1
1
1
0
M
1
75
4.6875
37.5
2x
32x
4x
ZDB AND MULTIPLIER
±155
±165
±160
110
120
110
1x
16x
2x
±55
±55
±50
20
20
20
Clock Period Jitter Tables (ICS570B)
All jitter values are considered typical measured at 25° C with 27Ω termination resistor and 15 pF loads on both CLK
and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to
improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
Multiplier
CLK = 50M
P to P
1 sigma
Multiplier
CLK/2 = 25M
P to P
1 sigma
0
0
M
M
M
1
1
1
M
1
0
M
1
0
M
1
8.333
6.25
3.125
4.167
2.5
25
1.5625
12.5
6x
8x
16x
12x
20x
2x
32x
4x
±110
±125
±130
±120
±115
±130
±120
±120
80
90
90
90
90
50
90
60
3x
4x
8x
6x
10x
1x
16x
2x
±55
±50
±55
±55
±55
±55
±55
±55
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
Multiplier
CLK = 100M
P to P
1 sigma
Multiplier
CLK/2 = 50M
P to P
1 sigma
0
0
M
M
M
1
1
1
M
1
0
M
1
0
M
1
16.667
12.5
6.25
8.333
5
50
3.125
25
6x
8x
16x
12x
20x
2x
32x
4x
±100
±100
±110
±100
±105
±90
±95
±105
70
70
80
70
70
60
70
70
3x
4x
8x
6x
10x
1x
16x
2x
±45
±45
±45
±45
±40
±40
±45
±60
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
S
CLKIN
0
0
M
M
M
1
0
M
25
18.375
9.375
12.5
CLK = 150M
Multiplier
P to P
6x
8x
16x
12x
±115
±120
±130
±130
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
1 sigma
70
80
90
90
5
CLK/2 = 75M
Multiplier
P to P
3x
4x
8x
6x
1 sigma
±50
±50
±50
±45
20
20
20
20
ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
M
1
1
1
1
0
M
1
7.5
75
4.6875
37.5
20x
2x
32x
4x
ZDB AND MULTIPLIER
±130
±115
±130
±110
90
90
90
70
10x
1x
16x
2x
±45
±45
±50
±60
20
20
20
20
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS570. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial version
0 to +70° C
Ambient Operating Temperature, Industrial version
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Power Supply Voltage (measured in respect to GND)
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
6
Max.
Units
0
70
°C
-40
+85
°C
+3.45
V
+3.15
Typ.
+3.3
ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Operating Current
Symbol
VDD
IDD
Conditions
Min.
Typ.
Max.
Units
V
ICS570B,
ICS570M
3.15
3.45
ICS570A,
ICS570M
4.75
5.25
ICS570B,
ICS570M
VDD=3.3 V, 50M
input, S1:0 = 11
16
mA
ICS570A,
ICS570M
VDD=5.0 V, 50M
input, S1:0 = 11
25
mA
Input High Voltage
VIH
ICLK, FBIN
Input Low Voltage
VIL
ICLK, FBIN
Input High Voltage
VIH
S0, S1
Input Low Voltage
(mid-level)
VIM
S0, S1
Input Low Voltage
VIL
S0, S1
Output High Voltage (CMOS
High)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12mA
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
S0, S1
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
2
V
0.8
VDD-0.5
V
VDD/2
V
0.5
7
V
0.4
V
V
±100
mA
5
pF
ICS570
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ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Input Frequency, ICLK
FBIN from CLK/2
Output Clock Frequency
CLK
Output to Output Skew
ICS570B, ICS570M
Output to Output Skew
VDD=5 V, ICS570A
Input to Output Jitter
40 - 150 MHz
Min.
Typ.
Max. Units
See table on page 2
10
ICS570M
170
MHz
100
175
ps
100
200
ps
100-250
ps
600
ps
ICLK to FBIN,
CLK>30MHz, Note 1
-300
300
ps
ICLK to FBIN,
CLK30MHz, Note 1
-1
1
ns
Input Skew, ICS570A
ICLK to FBIN,
CLK