ICS671M-03ILFT

DATASHEET ICS671-03 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description Features The ICS671-03 is a low phase noise, high speed PLL based, 8 output, low skew zero delay buffer. Based on IDT’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin. • • • • • • • Packaged in 16 pin narrow (150 mil) SOIC • • • • • • 5 V tolerant FBIN and CLKIN pins Clock outputs from 10 to 133 MHz Zero input-output delay Eight low-skew (