PRELIMINARY
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS841S04I is a PLL-based clock generator
ICS
specifically designed for PCI_Express™Clock
HiPerClockS™ Generation applications. This device generates a
100MHz HCSL clock. The device offers a HCSL
(Host Clock Signal Level) clock output from a clock
input reference of 25MHz. The input reference may be derived
from an external source or by the addition of a 25MHz crystal to
the on-chip crystal oscillator. An external reference may be applied
to the XTAL_IN pin with the XTAL_OUT pin left floating.
• Four 0.7V current mode differential HCSL output pairs
• Crystal oscillator interface, 25MHz
• Output frequency: 100MHz
• RMS period jitter: 3ps (maximum)
• Output skew: 70ps (maximum)
• Cycle-to-cyle jitter: 35ps (maximum)
• I2C support with readback capabilities up to 400kHz
The device offers spread spectrum clock output for reduced EMI
applications. An I2C bus interface is used to enable or disable
spread spectrum operation as well as select either a down spread
value of -0.35% or -0.5%.
• Spread Spectrum for electromagnetic interference (EMI)
reduction
• 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
The ICS841S04I is available in both standard and lead-free
24-Lead TSSOP packages.
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
25MHz
XTAL_IN
OSC
PLL
Divider
Network
SRCT[1:4]
SRCC[1:4]
XTAL_OUT
SDATA Pullup
SCLK Pullup
I2C
Logic
IREF
SRCT3
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
VDD_SRC
VSS_SRC
IREF
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SRCC4
SRCT4
VDD_SRC
SDATA
SCLK
XTAL_OUT
XTAL_IN
VDD_REF
VSS_REF
nc
VDDA
VSSA
ICS841S04I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
5, 6
7, 8
3, 9, 11
Name
SRCT3, SRCC3
SRCT2, SRCC2
SRCT1, SRCC1
VSS_SRC
Type
Description
Output
Power
Ground for core and SRC outputs.
4, 10, 22
VDD_SRC
Power
12
IREF
Input
13
VSSA
Power
Power supply for core and SRC outputs.
A fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx
clock outputs.
Analog ground pin.
14
VDDA
Power
Power supply for PLL.
15
nc
Unused
16
VSS_REF
Power
17
VDD_REF
Power
18, 19
XTAL_IN, XTAL_OUT
Input
20
SCLK
Input
21
SDATA
Input/
Output
23, 24
SRCT4, SRCC4
Output
Differential output pair. HCSL interface levels.
No connect.
Ground for crystal interface
Power supply for crystal interface.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
SMBus compatible SCLK. This pin has an internal pullup resistor,
Pullup but is in high impedance in powerdown mode.
LVCMOS/LVTTL interface levels.
SMBus compatible SDATA. This pin has an internal pullup resistor,
Pullup but is in high impedance in powerdown mode.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
COUT
Output Pin Capacitance
LIN
Pin Inductance
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
Test Conditions
Minimum
Typical
Maximum
4
pF
51
3
2
Units
kΩ
5
pF
7
nH
ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
SERIAL DATA INTERFACE
DATA PROTOCOL
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as
described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
TABLE 3A. COMMAND CODE DEFINITION
BIT
7
6:5
4:0
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Chip select address, set to "00" to access device.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be
"00000".
TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL
BIT
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Star t
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
BIT
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
3
Description = Block Read
Star t
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat star t
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave / Acknowledges
Data Byte N from slave - 8 bits
Not Acknowledge
ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
TABLE 3C. BYTE READ AND BYTE WRITE PROTOCOL
BIT
1
2:8
9
10
11:18
19
20:27
28
29
Description = Byte Write
Star t
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Data byte - 8 bits
Acknowledge from slave
Stop
BIT
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Star t
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat star t
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
CONTROL REGISTERS
TABLE 4A. BYTE 0:CONTROL REGISTER 0
BIT
7
@Pup
0
Name
Reserved
6
1
SRC[T/C]4
5
1
SRC[T/C]3
4
1
SRC[T/C]2
3
1
SRC[T/C]1
2
1
0
1
0
0
Reserved
Reserved
Reserved
Description
Reserved
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
Reserved
Reserved
Reserved
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
TABLE 4B. BYTE 1:CONTROL REGISTER 1
BIT
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
@Pup
1
0
1
0
1
1
1
1
Name
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
TABLE 4C. BYTE 2:CONTROL REGISTER 2
Description
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
TABLE 4D. BYTE 3:CONTROL REGISTER 3
BIT
7
6
5
4
3
2
1
0
PRELIMINARY
BIT
@Pup
Name
7
1
SRCT/C
6
5
4
3
1
1
0
1
Reser ved
Reser ved
Reser ved
Reser ved
2
0
SRC
1
0
1
1
Reser ved
Reser ved
Description
Spread Spectrum Selection
0 = -0.35%,
1 = -0.50%
Reser ved
Reser ved
Reser ved
Reser ved
SRC Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
Reser ved
Reser ved
TABLE 4E. BYTE 4:CONTROL REGISTER 4
Description
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
BIT
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
1
Name
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Description
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
TABLE 4F. BYTE 5:CONTROL REGISTER 5
BIT
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Description
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
TABLE 4G. BYTE 6:CONTROL REGISTER 6
BIT
@Pup
Name
7
0
TEST_SEL
6
0
TEST_MODE
5
4
3
2
1
0
0
1
0
0
1
1
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Description
REF/N or Hi-Z Select
0 = Hi-Z,
1 = REF/N
TEST Clock Mode Entr y Control
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
Reser ved
TABLE 4H. BYTE 7:CONTROL REGISTER 7
BIT
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
1
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD_REF + 0.5 V
Outputs, VO
-0.5V to VDD_SRC + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 70°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD_REF
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Power Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
VDD_REF – 0.25
3.3
VDD_REF
V
3.135
3.3
3.465
V
8
mA
VDD_SRC
Core/SRC Supply Voltage
IDD_REF
Cr ystal Supply Current
IDD_SRC
Core/SRC Supply Current
160
mA
IDDA
Analog Supply Current
25
mA
Maximum
Units
V
1.0
V
5
µA
TABLE 5B. DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VIHSMBUS Input High Voltage
Test Conditions
SDATA, SCLK
VILSMBUS
Input Low Voltage
SDATA, SCLK
IIH
Input High Current
SDATA, SCLK
VDD = VIN = 3.465V
IIL
Input Low Current
SDATA, SCLK
VDD = 3.465V, VIN = 0V
IOH
Output Current
IOZ
High Impedance Leakage Current
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
Minimum Typical
2.2
-150
µA
14
-10
7
mA
10
µA
ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
TABLE 6. AC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
25
Units
fref
Frequency
sclk
SCLK Frequency
400
kHz
50
ppm
0
ppm
odc
XTAL
External
Reference
SRCT/SRCC Duty Cycle; NOTE 2, 7
tsk(o)
SRCT/C to SRCT/C Clock Skew; NOTE 2, 7
tPERIOD
Average Period; NOTE 3
Frequency Tolerance; NOTE 1
47
9.9970
MHz
53
%
70
ps
10.0533
ns
tjit(cc)
SRCT/C Cycle-to-Cycle Jitter ; NOTE 2, 7
35
ps
tjit(per)
Period Jitter, RMS; NOTE 2, 7
3
ps
700
ps
20
%
47.5
52.5
%
125
ps
800
mV
tR / tF
SRCT/SRCC Rise/Fall Time; NOTE 4
tRFM
Rise/Fall Time Matching; NOTE 5
tDC
XTAL_IN Duty Cycle; NOTE 6
175
ΔtR / tF
Rise/Fall Time Variation
VHIGH
Voltage High
520
VLOW
Voltage Low
-150
VCROSS
Absolute Crossing Voltage
250
ΔVCROSS
Total Variation of VCROSS over all edges
VOX
Output Crossover Voltage
VOVS
Maximum Overshoot Voltage
VUDS
Minimum Undershoot Voltage
@ 0.7V Swing
250
-0.3
mV
550
mV
140
mV
550
mV
VHIGH + 0.3
V
V
VRB
Ring Back Voltage
0.2
V
NOTE 1: With recommended cr ystal.
NOTE 2: Measured at crossing point VOX.
NOTE 3: Measured at crossing point VOX at 100MHz.
NOTE 4: Measured from VOL = 0.175V to VOH = 0.525V.
NOTE 5: Determined as a fraction of 2*(tR – tF) / (tR + tF).
NOTE 6: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within
specification.
NOTE 7: Measured using a 50Ω to GND termination.
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
3.3V±5%
100Ω
33Ω
Measurement
Point
SRCC1:4
VDDA
49.9Ω
2pF
100Ω
33Ω
GND
SRCT1:4
Measurement
Point
49.9Ω
➤
HCSL
➤
tcycle n
tcycle n+1
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
2pF
475Ω
➤
VDD_REF,
VDD_SRC
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
CYCLE-TO-CYCLE JITTER
VOH
nSRCx
VREF
SRCx
VOL
nSRCy
SRCy
tsk(o)
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
OUTPUT SKEW
PERIOD JITTER
SRCC1:4
80%
80%
SRCT1:4
VSW I N G
t PW
t
odc =
Clock
Outputs
PERIOD
t PW
20%
20%
tF
tR
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
HCSL OUTPUT RISE/FALL TIME
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ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS841S04I provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD_REF, VDD_SRC, and
VDDA should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a .01μF bypass capacitor should be connected
to each VDDA. The 10Ω resistor can also be replaced by a ferrite
bead.
3.3V
VDD_REF
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
USING THE ON-BOARD CRYSTAL OSCILLATOR
The crystal and optional trim capacitors should be located as
close to the ICS841S04I XTAL_IN and XTAL_OUT pins as possible
to avoid any board level parasitic.
The ICS841S04I features a fully integrated Pierce oscillator to
minimize system implementation costs. The ICS841S04I may be
operated with a 25MHz crystal and without additional components.
Recommended operation for the crystal should be of a parallel
resonant type and a load specification of CL = 18pF. See Table 7
for complete crystal specifications.
XT AL_IN
If more precise frequency control is desired, the addition of
capacitors from each of the XTAL_IN and XTAL_OUT pins to
ground may be used to trim the frequency as shown in Figure 2.
TBD
33pF
25MHz
TABLE 7. RECOMMENDED CRYSTAL SPECIFICATIONS
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Parallel Resonance
Shunt Capacitance (CL)
5-7pF
Load Capacitance (CO)
18pF
Equivalent Series Resistance (ESR)
20-50Ω
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
XTAL_OUT
TBD
18pF
FIGURE 2. CRYSTAL OSCILLATOR WITH TRIM CAPACITOR
10
ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
DIFFERENTIAL OUTPUT s
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
OUTPUT DRIVER CURRENT
The ICS841S04I outputs are HCSL current drive with the current being set with a resistor from I REF to ground. For a 50Ω
pc board trace, the drive current would typically be set with a
R REF of 475Ω which products an I REF of 2.32mA. The I REF is
multiplied by a current mirror to an output drive of 6*2.32mA
or 13.92mA. See Figure 3 for current mirror and output drive
details.
IREF
RREF
RL
RL
FIGURE 3. HCSL CURRENT MIRROR AND OUTPUT DRIVE
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
RECOMMENDED TERMINATION
Figure 4A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
0.7V Differential HCSL
Add-In Card
0.7V Differential HCSL
Clock Driver
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications
which require a point to point connection and contain the driver
and receiver on the same PCB. All traces should all be 50Ω
impedance.
0.7V Differential HCSL
Clock Driver
FIGURE 4B. RECOMMENDED TERMINATION
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS841S04I is: 1874
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ PCI EXPRESS™ CLOCK GENERATOR
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ICS841S04BGI REV. C MAY 23, 2007
ICS841S04I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS841S04BGI
ICS841S04BGI
24 Lead TSSOP
tube
-40°C to 85°C
ICS841S04BGIT
ICS841S04BGI
24 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS841S04BGILF
ICS841S04BGIL
24 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS841S04BGILFT
ICS841S04BGIL
24 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
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800 345 7015
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Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
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KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA