ICS8431-21
350MHZ, Low Jitter, Crystal Oscillator-to-3.3V
LVPECL Frequency Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON (JULY 26, 2014)
GENERAL DESCRIPTION
FEATURES
The ICS8431-21 is a general purpose clock frequency synthesizer for IA64/32 application. The VCO operates at a frequency
range of 250MHz to 700MHz providing an output frequency range
of 62.5MHz to 350MHz. The output frequency can be programmed
using the parallel interface, M0 through M8 to the configuration
logic, and the output divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0
and SSC_CTL1.
• Fully integrated PLL
Programmable features of the ICS8431-21 support four operational modes. The four modes are spread spectrum clocking
(SSC), non-spread spectrum clock and two test modes which are
controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers,
the ICS8431-21 can immediately change spread-spectrum operation without having to reset the device.
• Programmable PLL loop divider for generating a variety
of output frequencies
• Differential 3.3V LVPECL output
• Crystal oscillator interface
• Output frequency range: 62.5MHz to 350MHz
• Crystal input frequency range: 14MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for
environments requiring ultra low EMI
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
In SSC mode, the output clock is modulated in order to achieve a
reduction in EMI. In one of the PLL bypass test modes, the PLL is
disconnected as the source to the differential output allowing an
external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differential output to be
driven at a lower frequency throughout the system clock tree. In
the other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful for
characterizing the oscillator and internal dividers.
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V supply voltage
• 0°C to 85°C ambient operating temperature
• Replaces ICS8431-01 and ICS8431-11
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Use Replacement Part: 84314AY-02LF
BLOCK DIAGRAM
PIN ASSIGNMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VCC
XTAL_IN
OSC
XTAL_OUT
÷ 16
PLL
PHASE
DETECTOR
÷2
VCO
÷4
÷M
FOUT
nFOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VCC
XTAL_IN
XTAL_OUT
nc
nc
VCCA
VEE
MR
DIV_SEL
VCCO
FOUT
nFOUT
VEE
ICS8431-21
TEST_I/O
M0:M8
Configuration
Logic
nP_LOAD
SSC
Control
Logic
SSC_CTL0
SSC_CTL1
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
DIV_SEL
1
ICS8431AM-21 REV. B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8431-21 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
puts M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the M0:M8
inputs will not be seen by the M divider until the next LOW
transition on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
fxtal x
fVCO =
M
16
The M value and the required values of M0:M8 for programming
the VCO are shown in Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
16 x N
For the ICS8431-21, the output divider may be set to either ÷2
or ÷4 by the DIV_SEL pin. For an input of 16 MHz, valid
M values for which the PLL will achieve lock are defined as:
250 ≤ M ≤ 511.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to the LVPECL
output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-21 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using in-
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2, 3, 4,
5, 6, 7
8, 9
Name
Type
M0-M6
Input
Input
12, 15, 21
M7-M8
SSC CTL0,
SSC CTL1
VEE
13
TEST I/O
10, 11
Input
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL pins interface levels.
Pullup
Pullup
SCC control pins. LVTTL / LVCMOS interface levels.
14, 27
VCC
Power
Input /
Output
Power
Negative supply pins. Connect all VEE pins to board ground.
16, 17
nFOUT, FOUT
Output
Differential outputs for the synthesizer. 3.3V LVPECL interface levels.
18
VCCO
Power
19
DIV_SEL
Input
20
MR
Input
22
VCCA
Power
Output supply pin.
Determines the output divide value for FOUT.
Pulldown
LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output FOUT to go low and the inver ted output
Pulldown nFOUT to go high. When logic LOW, the internal dividers and the
outputs are enabled. Asser tion of MR does not effect loaded M and T
values. LVCMOS / LVTTL interface levels.
Analog supply pin.
23, 24
nc
XTAL_OUT,
XTAL_IN
Unused
Programmed as defined in Table 3A Function Table.
Core supply pin.
No connect.
Crystal oscillator interface. XTAL_IN is the input.
25, 26
Input
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0
28
nP_LOAD
Input
Pulldown
is loaded into M divider. LVTTL / LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Pin Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions
3
Minimum
Typical
Maximum
Units
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE
Inputs
SSC_CTL1 SSC_CTL0
Outputs
TEST_I/O
Source
SSC
FOUT, nFOUT
DIV_SEL0 DIV_SEL1
0
0
Internal
Disabled
fXTAL ÷ 32
fXTAL ÷ 64
0
1
PLL
Enabled
fXTAL x M
32
fXTAL x M
64
1
0
External
Disabled
Test Clk
Test Clk
fXTAL x M
32
NOTE 1: Used for in house debug and characterization.
1
1
PLL
fXTAL ÷ 16 PLL bypass; oscillator, M and N
÷M
dividers test mode. NOTE 1
Default SSC;
Hi-Z
Modulation Factor = ½ Percent
PLL Bypass Mode, NOTE 1;
Input
(1MHz≤ Test Clk ≤ 200MHz)
fXTAL x M
64
Disabled
Operational Modes
TEST_I/O
Hi-Z
No SSC Modulation
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Count
250
250
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
0
1
1
1
1
1
0
1
0
251
251
0
1
1
1
1
1
0
1
1
252
252
0
1
1
1
1
1
1
0
0
253
253
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
508
508
1
1
1
1
1
1
1
0
0
509
509
1
1
1
1
1
1
1
0
1
510
510
1
1
1
1
1
1
1
1
0
511
511
1
1
1
1
1
1
1
1
1
NOTE 1: Assumes a 16MHz cr ystal.
TABLE 3C. FUNCTION TABLE
Inputs
DIV_SEL
N Divider Value
Output Frequency (MHz)
Minimum
Maximum
0
2
12 5
350
1
4
62.5
175
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 46.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V CC
Core Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
155
mA
ICCA
Analog Supply Current
16
mA
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
150
µA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
VIH
Input
VIL
Input
IIH
Input
IIL
Input
Parameter
M0:M8, SSC_CTL0,
SSC_CTL1, MR,
High Voltage
DIV_SEL, TEST_I/O,
nP_LOAD
M0:M8, SSC_CTL0,
SSC_CTL1, MR,
Low Voltage
DIV_SEL, TEST_I/O,
nP_LOAD
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
High Current
M0:M6, DIV_SEL
nP_LOAD, MR
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
Low Current
M0:M6, DIV_SEL
nP_LOAD, MR
Test Conditions
Minimum
Typical
VCC = 3.465V, VIN = 0V
-150
µA
VCC = 3.465V, VIN = 0V
-5
µA
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Maximum
Units
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Output terminated with 50Ω to VCCO - 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
14
16
Equivalent Series Resistance (ESR)
Shunt Capacitance
3
25
MHz
40
Ω
7
pF
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
FOUT
Output Frequency
t j it(cc)
Cycle-to-Cycle Jitter; NOTE 1, 5
odc
Output Duty Cycle
tR / tF
Output Rise/Fall Time
Test Conditions
Typical
62.5
FOUT ≥ 100MHz
19
48
20% to 80%
200
29
Fxtal
Crystal Input Range; NOTE 2, 3
FM
SSC Modulation Frequency; NOTE 4
FOUT = 200MHz
FMF
SSC Modulation Factor; NOTE 4
FOUT = 200MHz
SSCred
Spectral Reduction; NOTE 4
FOUT = 200MHz
14
Power-up to Stable Clock Output
tSTABLE
See Figures in the Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: For XTAL input, refer to Application Note.
NOTE 4: Spread Spectrum clocking enabled.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
Minimum
6
50
16
0.4
7
Maximum
Units
350
MHz
30
ps
52
%
700
ps
25
MHz
33.33
KHz
0.6
%
10
dB
10
ms
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCA, VCCO
Qx
nFOUT
SCOPE
FOUT
➤
➤
LVPECL
➤
tcycle n
tcycle n+1
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
nQx
VEE
-1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
nFOUT
80%
80%
FOUT
VSW I N G
Clock
Outputs
t PW
20%
20%
tR
t
PERIOD
tF
odc =
t PW
x 100%
t PERIOD
OUTPUT RISE/FALL TIME
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
7
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-21 provides separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA, and VCCO should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, better power supply isolation is
required. Figure 1 illustrates how a 10Ω along with a 10μF and
a .01μF bypass capacitor should be connected to each VCCA
pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
SPREAD SPECTRUM
The ICS8431-21 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock frequency
(+0.0% / -0.5%). An example of the amount of down spread
relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 2B. The ratio of this width
to the fundamental frequency is typically 0.4%, and will not
exceed 0.6%. The resulting spectral reduction will be greater
than 7dB, as shown in Figure 2B. It is important to note the
ICS8431-21 7dB minimum spectral reduction is the componentspecific EMI reduction, and will not necessarily be the same as
the system EMI reduction.
Spread-spectrum clocking is a frequency modulation technique
for EMI reduction. When spread-spectrum is enabled, a 30kHz
triangle waveform is used with 0.5% down-spread (+0.0% / 0.5%) from the nominal 200MHz clock frequency. An example
of a triangle frequency modulation profile is shown in Figure
2A below. The ramp profile can be expressed as:
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
• Fm = Nominal Modulation Frequency (30kHz)
• δ = Modulation Factor (0.5% down spread)
➤
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < 1,
2fm
(1 - δ) fnom - 2 fm x δ x fnom x t when 1 < t < 1
2fm
fm
Δ − 10 dBm
Fnom
A
B
➤
(1 - δ) Fnom
δ = .4%
➤
➤
0.5/fm
1/fm
FIGURE 2A. TRIANGLE FREQUENCY MODULATION
FIGURE 2B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD -SPECTRUM OFF (B) SPREAD -S PECTRUM ON
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
The ICS8431-21 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF parallel
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
FIGURE 3. CRYSTAL INPUT INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
9
TO
XTAL INPUT INTERFACE
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
84Ω
FIGURE 5B. LVPECL OUTPUT TERMINATION
10
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 6B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected
component types and the density of the P.C. board.
The schematic of the ICS8431-21 layout example used in this
layout guideline is shown in Figure 6A. The ICS8431-21
recommended PCB board layout for this example is shown in
Logic Input Pin Examples
VCC=3.3V
Set Logic
Input to
'1'
VCC
SP=Spare, not installed
RU1
1K
VCC
C6
0.01uF
C8
VCC
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_IO
VCC
nP_LOAD
VCC
XTAL_IN
XTAL_OUT
NC
NC
VCCA
VEE
MR
DIV_SEL
VCCO
FOUT
nFOUT
VEE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RU2
SP
To Logic
Input
pins
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22pF
To Logic
Input
pins
RD1
SP
RD2
1K
X1
C7
22pF
VCC
R5
VCC
VCCA
VCC
C3
0.01uF
C4
10uF
10
R1
125
R3
125
Zo = 50 Ohm
+
Zo = 50 Ohm
C1
0.1uF
Set Logic
Input to
'0'
VCC
-
ICS8431-21
C2
0.1uF
R2
84
R4
84
FIGURE 6A. SCHEMATIC EXAMPLE
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
11
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
• The 50Ω output trace pair should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C6, as close as
possible to the power pins. If space allows, placment of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin generated by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R5, C3, and C4 should be placed as
close to the VCCA pin as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination scheme can also be used but is not shown in the
example.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL_OUT) and 26 (XTAL_IN). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
C8
GND
U1
ICS8431-21
VCC
Signals
C6
VIA
X1
C3
C4
R5
C7
C2
Zo=50 Ohm
C1
Zo=50 Ohm
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-21
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8431-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8431-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 30mW = 567.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.567W * 39.7°C/W = 107.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. THERMAL RESISTANCE θ JA FOR 28-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V
L
CCO_MAX
- VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
28 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8431-21 is: 4790
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
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350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - M SUFFIX
FOR
28 LEAD SOIC
TABLE 9. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUM
N
MAXIMUM
28
A
--
2.65
A1
0.10
--
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
17.70
18.40
E
7.40
7.60
e
H
1.27 BASIC
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
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350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS8431AM-21
ICS8431AM-21
28 Lead SOIC
Tube
0°C to 85°C
ICS8431AM-21T
ICS8431AM-21
28 Lead SOIC
1000 Tape & Reel
0°C to 85°C
ICS8431AM-21LF
ICS8431AM-21LF
28 Lead "Lead-Free" SOIC
Tube
0°C to 85°C
ICS8431AM-21LFT
ICS8431AM-21LF
28 Lead "Lead-Free" SOIC
1000 Tape & Reel
0°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8431AM-21 REV.B AUGUST 22, 2013
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350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
A
A
A
B
Table
T10
T10
Page
1
16
9
10
18
1
Description of Change
Features Section - added replacement bullet and Lead-Free bullet
Ordering Information Table - added Lead-Free par t number.
Added LVCMOS to XTAL Interface section.
Recommendations for Unused Input Pins section.
Ordering Information Table - added LF marking.
Updated format throughout the datasheet.
Not Recommended For New Designs
PDN# CQ-13-01, Product Discontinuation Notice - Last Time Buy Expires
(July 26, 2014)
IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
18
Date
4/27/05
5/30/07
6/21/13
8/22/13
ICS8431AM-21 REV.B AUGUST 22, 2013
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution.
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
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