ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
General Description
Features
The ICS853013 is a low skew, high performance
dual 1-to-3 Differential-to-2.5V/3.3V/5V LVPECL/
HiPerClockS™
ECL Fanout Buffer and a member of the
HiperclocksTM family of High Performance Clock
Solutions from IDT. The ICS853013 operates with a
positive or negative power supply at 2.5V, 3.3V, or 5V. Guaranteed
output and part-to-part skew characteristics make the ICS853013
ideal for those clock distribution applications demanding well
defined performance and repeatability.
•
•
•
Two differential LVPECL/ECL bank outputs
•
•
Output frequency: >2GHz (typical)
•
•
•
•
•
Output skew: 40ps (maximum)
•
ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
ICS
•
•
Block Diagram
Two differential LVPECL clock input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Translates any single-ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Part-to-part skew: 250ps (maximum)
Propagation delay: 5780ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V, VEE = 0V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
QA0
PCLKA Pulldown
Pullup/Pulldown
nPCLKA
nQA0
QA0
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
VCC
nQB0
QB0
nQA0
QA1
nQA1
QA2
nQA2
QB0
PCLKB Pulldown
nPCLKB
Pullup/Pulldown
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA1
nQA1
QA2
nQA2
VCC
QB2
nQB2
QB1
nQB1
VEE
nQB0
ICS853013
QB1
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
nQB1
QB2
nQB2
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
3, 8, 16
VCC
Power
Power supply pins.
4
PCLKA
Input
Pulldown
Non-inverting differential LVPECL clock input.
5
nPCLKA
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
6
PCLKB
Input
Pulldown
Non-inverting differential LVPECL clock input.
7
nPCLKB
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
9, 10
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
11
VEE
Power
Negative supply pin.
12, 13
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
14, 15
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
17, 18
nQA2, QA2
Output
Differential output pair. LVPECL interface levels.
19, 20
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN
Input Pulldown Resistor
75
kΩ
RVCC/2
Pullup/Pulldown Resistors
50
kΩ
Function Table
Table 3. Clock Input Function Table
Inputs
PCLKA or PCLKB
Outputs
nPCLKA or nPCLKB
QA0:Q2,
QB0:QB2
nQA0:nQA2,
nQB0:nQB2
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non-Inverting
1
0
HIGH
LOW
Differential to Differential
Non-Inverting
0
Biased; NOTE 1
LOW
HIGH
Single-Ended to Differential
Non-Inverting
1
Biased; NOTE 1
HIGH
LOW
Single-Ended to Differential
Non-Inverting
Biased; NOTE 1
0
HIGH
LOW
Single-Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single-Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, Wiring the Differential Input to Accept Single Ended Levels.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
5.5V (LVPECL mode, VEE = 0V)
Negative Supply Voltage, VEE
-5.5V (ECL mode, VCC = 0V)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5V
Inputs, VI (ECL mode)
0.5V to VEE – 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Operating Temperature Range, TA
-40°C to +85°C
Package Thermal Impedance, θJA
46.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 5.25V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Positive Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
3.3
5.25
V
60
mA
Table 4B. LVPECL DC Characteristics, VCC = 3.3V, VEE = 0V; TA = -40°C to 85°C
-40°C
Symbol Parameter
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.37
2.295
2.33
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage (Single-ended)
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage (Single-ended)
1.43
1.765
1.43
1.765
1.43
1.765
V
VPP
Peak-to-Peak Input Voltage
150
1200
150
1200
150
1200
V
VCMR
Input High Voltage Common Mode
Range; NOTE 2, 3
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input
High Current
PCLKA, PCLKB
nPCLKA, nPCLKB
200
µA
Input
Low Current
PCLKA, PCLKB
-10
-10
-10
µA
IIL
nPCLKA, nPCLKB
-200
-200
-200
µA
800
200
800
200
800
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
.Table 4C. LVPECL DC Characteristics, VCC = 2.5V, VEE = 0V; TA = -40°C to 85°C
-40°C
Symbol Parameter
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.495
1.53
1.565
V
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage (Single-ended)
1.275
1.56
1.275
1.56
1.275
-0.8
V
VIL
Input Low Voltage (Single-ended)
0.63
0.965
0.63
0.965
0.63
0.965
V
VPP
Peak-to-Peak Input Voltage
150
1200
150
1200
150
1200
V
VCMR
Input High Voltage Common Mode
Range; NOTE 2, 3
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input
High Current
PCLKA, PCLKB
nPCLKA, nPCLKB
200
µA
Input
Low Current
PCLKA, PCLKB
-10
-10
-10
µA
IIL
nPCLKA, nPCLKB
-200
-200
-200
µA
800
800
200
800
200
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
Table 4D. LVPECL DC Characteristics, VCC = 5V, VEE = 0V; TA = -40°C to 85°C
-40°C
Symbol Parameter
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.005
-0.97
-0.935
V
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.76
5
-1.67
V
VIH
Input High Voltage (Single-ended)
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
VIL
Input Low Voltage (Single-ended)
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
VPP
Peak-to-Peak Input Voltage
150
1200
150
1200
150
1200
V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3
VEE+1.2
0
VEE+1.2
0
VEE+1.2
0
V
IIH
Input
PCLKA, PCLKB
High Current nPCLKA, nPCLKB
200
µA
IIL
Input
Low Current
800
200
800
200
800
PCLKA, PCLKB
-10
-10
-10
µA
nPCLKA, nPCLKB
-200
-200
-200
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
4
ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Table 4E. ECL DC Characteristics, VCC = 0V, VEE = -5.25V to -2.375V; TA = -40°C to 85°C
-40°C
Symbol Parameter
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.005
-0.97
-0.935
V
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
VIH
Input High Voltage (Single-ended)
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
VIL
Input Low Voltage (Single-ended)
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
VPP
Peak-to-Peak Input Voltage
150
1200
150
1200
150
1200
V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3
VEE+1.2
0
VEE+1.2
0
VEE+1.2
0
V
IIH
Input
PCLKA, PCLKB
High Current nPCLKA, nPCLKB
200
µA
IIL
Input
Low Current
800
800
200
800
200
PCLKA, PCLKB
-10
-10
-10
µA
nPCLKA, nPCLKB
-200
-200
-200
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 0V, VEE = -5.25V to -2.375V or; VCC = 2.375V to 5.25V, VEE = 0V; TA = -40°C to 85°C
-40°C
Min
Max
Min
Parameter
fMAX
Output Frequency
tPLH
Propagation Delay; Low-to-High;
NOTE 1
300
410
510
330
425
520
360
465
570
ps
tPHL
Propagation Delay; High-to-Low;
NOTE 1
300
410
510
330
425
520
360
465
570
ps
tsk(o)
Output Skew; NOTE 2, 4
40
40
40
ps
tsk(odc)
Output Duty Cycle Skew
40
40
40
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250
250
250
ps
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jjitter Section
tR / tF
Output
Rise/Fall Time
>2
180
Max
Min
>2
0.03
120
Typ
80°C
Symbol
20% to 80%
Typ
25°C
120
180
Max
>2
0.03
250
Typ
GHz
0.03
250
120
180
Units
ps
250
ps
All parameters are measured at f ≤ 1GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
5
ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
Additive Phase Jitter @ 156.25MHz
= 0.03ps (typical)
-10
-20
-30
-40
-50
SSB Phase Noise dBc/Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Parameter Measurement Information
2V
VCC
VCC
Qx
SCOPE
nPCLKx
V
Cross Points
PP
V
CMR
PCLKx
LVPECL
nQx
VEE
VEE
-3.25V to -0.375V
LVPECL Output Load AC Test Circuit
nQx
Differential Input Level
nQx
Par t 1
Qx
Qx
nQy
nQy
Par t 2
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nPCLKx
80%
PCLKx
80%
VSW I N G
Clock
Outputs
20%
20%
tR
nQA[0:2],
nQB[0:2]
tF
QA[0:2],
QB[0:2]
tpLH
Output Rise/Fall Time
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
tpHL
Propagation Delay
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Parameter Measurement Information, continued
nPCLKx
PCLKx
nQA[0:2],
nQB[0:2]
QA[0:2],
QB[0:2]
tpLH
tpHL
tsk(odc) = tpLH - tpHL
Output Duty Cycle Skew
Application Information
Wiring the Differential Input to Accept Single-ended LVCMOS Levels
Figure 1 shows an example of the differential input that can be
wired to accept single-ended LVCMOS levels. The reference
voltage level VBB generated from the device is connected to the
negative input. The C1 capacitor should be located as close as
possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
PCLKx
V_REF
C1
0.1u
nPCLKx
R2
1K
Figure 1. Single-Ended LVCMOS Signal Driving Differential Input
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by the
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
Zo = 50Ω
R2
50
Zo = 50Ω
PCLK
R1
100
PCLK
Zo = 50Ω
nPCLK
Zo = 50Ω
nPCLK
HiPerClockS
PCLK/nPCLK
CML
HiPerClockS
PCLK/nPCLK
CML Built-In Pullup
Figure 2B. HiPerClockS PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
Figure 2A. HiPerClockS PCLK/nPCLK Input
Driven by an Open Collector CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
3.3V
R4
125
R3
84
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
C1
Zo = 50Ω
C2
R4
84
PCLK
PCLK
Zo = 50Ω
nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
R5
100 - 200
R6
100 - 200
R1
125
Figure 2D. HiPerClockS PCLK/nPCLKInput Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 2C. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
2.5V
3.3V
3.3V
2.5V
R3
120
HiPerClockS
PCLK/nPCLK
R2
125
3.3V
R4
120
R3
1k
Zo = 50Ω
R4
1k
C1
Zo = 60Ω
PCLK
PCLK
R5
100
Zo = 60Ω
R1
120
R2
120
nPCLK
Zo = 50Ω
nPCLK
SSTL
C2
LVDS
HiPerClockS
PCLK/nPCLK
R1
1k
HiPerClockS
PCLK/nPCLK
Figure 2F. HiPerClockS PCLK/nPCLK Input
Driven by a 3.3V LVDS Driver
Figure 2E. HiPerClockS PCLK/nPCLK Input
Driven by an SSTL Driver
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
R2
1k
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ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Recommendations for Unused Output Pins
Inputs:
Outputs:
PCLK/nPCLK INPUTS
LVPECL Outputs
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground. For applications
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
125Ω
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
Figure 3A. 3.3V LVPECL Output Termination
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
84Ω
Figure 3B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
ground level. The R3 in Figure 4B can be eliminated and the
termination is shown in Figure 4C.
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250
R3
250
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 4C. 2.5V LVPECL Driver Termination Example
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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Termination for 5V LVPECL Outputs
This section shows examples of 5V LVPECL output termination.
Figure 5A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
VCC – 2V = 3V at the receiver. Figure 5B shows Thevenin
equivalence of Figure 5A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
PECL
PECL
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
R1
50
PECL
R1
125
R2
50
PECL
R2
125
3V
Figure 5A. 5V LVPECL Driver Termination Example
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Figure 5B. 5V LVPECL Driver Termination Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853013.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW
•
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (3.8V, with all outputs switching) = 315mW + 185.64mW = 500.64mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.501W * 46.2°C/W = 108.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead SOIC Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V
(VCC_MAX – VOH_MAX) = 0.935V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead SOIC
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS853013 is: 226
Pin compatible with MC100LVEL13 and MC100EL13
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC
Table 8. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
2.65
A1
0.10
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
12.60
13.00
E
7.40
7.60
e
1.27 Basic
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
7°
Reference Document: JEDEC Publication 95, MS-013,
MS-119
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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Ordering Information
Table 9. Ordering Information
Part/Order Number
853013AM
853013AMT
853013AMLF
853013AMLFT
Marking
ICS853013AM
ICS853013AM
ICS853013AMLF
ICS853013AMLF
Package
20 Lead SOIC
20 Lead SOIC
“Lead-Free” 20 Lead SOIC
“Lead-Free” 20 Lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
1000 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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Revision History Sheet
Rev
A
B
Table
Page
T8
8
16
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free marking.
T4B
3
T4C
4
T4D
4
T4E
5
3.3V LVPECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
2.5V LVPECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
5V LVPECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
ECL DC Characteristics - changed IIH max. from 150µA to 200µA.
Changed IIL min. from -150µA to -200µA.
Updated LVPECL Clock Input Interface Section.
Added Termination for 5V LVPECL Outputs.
Power Considerations - updated Junction Temperature equation with worst
case thermal resistance of 46.2°C/W.
9
12
13
Description of Change
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
Date
17
10/19/05
2/7/08
ICS853013AM REV. B OCTOBER 24, 2008
ICS853013
LOW SKEW, DUAL,1-TO-3, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL FANOUT BUFFER
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