ICS8725AY-01LF

ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8725-01 is a highly versatile 1:5 Differential-to-HSTL clock generator and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8725-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • Five differential HSTL outputs ICS • Selectable differential CLKx, nCLKx input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Static phase offset: ±100ps • Cycle-to-cycle jitter: 25ps • Output skew: 25ps • 3.3V core, 1.8V output operating supply • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VDDO nQ4 Q4 Q3 nQ3 CLK_SEL GND Q2 nQ2 1 1 SEL3 32 31 30 29 28 27 26 25 0 0 PLL FB_IN nFB_IN Q1 nQ1 VDDA CLK1 nCLK1 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 VDD CLK0 nCLK0 Q0 nQ0 PLL_SEL PLL_SEL Q4 nQ4 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 SEL0 1 24 VDDO SEL1 2 23 Q3 CLK0 3 22 nQ3 nCLK0 4 21 Q2 CLK1 5 20 nQ2 nCLK1 6 19 Q1 CLK_SEL 7 18 nQ1 MR 8 17 VDDO ICS8725-01 9 10 11 12 13 14 15 16 VDDO Q0 nQ0 GND 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View SEL3 MR 8725AY-01 SEL2 SEL2 FB_IN SEL1 nFB_IN VDD SEL0 www.icst.com/products/hiperclocks.html 1 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number 1, 2, 12, 29 3 Name SEL0, SEL1, SEL2, SEL3 CL K 0 Type Input 4 nCLK0 Input 5 CLK1 Input Pulldown Non-inver ting differential clock input. 6 nCLK1 Input 7 CLK_SEL Input 8 MR Input 9, 32 VDD Power Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Core supply pins. 10 nFB_IN Input 11 FB_IN Input Input Description Determines output divider values in Table 3. Pulldown LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pullup Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". 13, 28 GND Power Power supply ground. 14, 15 16, 17, 24, 25 18, 19 nQ0, Q0 Output Differential output pair. HSTL interface levels. VDDO Power Output supply pins. nQ1, Q1 Output Differential output pair. HSTL interface levels. 20, 21 nQ2, Q2 Output Differential output pair. HSTL interface levels. 22, 23 nQ3, Q3 Output Differential output pair. HSTL interface levels. 26, 27 nQ4, Q4 Output Differential output pair. HSTL interface levels. 30 VDDA Power 31 PLL_SEL Input Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. Pullup NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8725AY-01 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR TABLE 3A. CONTROL INPUT FUNCTION TABLE SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 0 0 0 0 250 - 700 ÷1 0 0 0 1 125 - 350 ÷1 0 0 1 0 62.5 - 175 ÷1 0 0 1 1 31.25 - 87.5 ÷1 0 1 0 0 250 - 700 ÷2 0 1 0 1 125 - 350 ÷2 0 1 1 0 62.5 - 175 ÷2 Inputs 0 1 1 1 250 - 700 ÷4 1 0 0 0 125 - 350 ÷4 1 0 0 1 250 - 700 ÷8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. TABLE 3B. PLL BYPASS FUNCTION TABLE SEL3 SEL2 SEL1 SEL0 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 0 0 0 0 ÷4 0 0 0 1 ÷4 Inputs 8725AY-01 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷ 16 0 1 1 1 ÷ 16 1 0 0 0 ÷ 32 1 0 0 1 ÷ 64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 www.icst.com/products/hiperclocks.html 3 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3. 3 3.465 V VDDA Analog Supply Voltage 3.135 3. 3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 120 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current No Load 0 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Test Conditions Input High Current Input Low Current Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 VDD = VIN = 3.465V VDDO = 2V 150 µA PLL_SEL VDD = VIN = 3.465V VDDO = 2V 5 µA CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 VDD = 3.465V, VDDO = 2V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V, VDDO = 2V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Minimum VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 nCLK0, nCLK1, nFB_IN VDD = 3.465V, VIN = 0V -150 Input Low Current VPP Peak-to-Peak Input Voltage 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8725AY-01 www.icst.com/products/hiperclocks.html 4 Maximum Units 150 µA 5 CLK0, CLK1, FB_IN IIL Typical µA µA µA 1.3 V VDD - 0.85 V REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR TABLE 4D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum 1 Typical 1. 4 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage; NOTE 2 40 60 % VSWING Peak-to-Peak Output Voltage Swing 0.6 1.1 V Maximum Units 700 MHz 700 MHz NOTE 1: Outputs terminated with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions Minimum PLL_SEL = 1 31.25 Typical PLL_SEL = 0 TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum PLL_SEL = 0V ƒ≤ 700MHz PLL_SEL = 3.3V 3.4 3.9 Maximum Units 700 MHz 4.4 ns t(Ø) Static Phase Offset; NOTE 2, 5 100 ps t sk(o) Output Skew; NOTE 3, 5 25 ps t jit(cc) t jit(Ø) Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 25 ±50 ps ps tL PLL Lock Time 1 ms t R / tF Output Rise/Fall Time 700 ps 20% to 80% @ 50MHz -100 Typical 300 tPW Output Pulse Width tcycle/2 - 85 tcycle/2 tcycle/2 + 85 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across alll conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. 8725AY-01 www.icst.com/products/hiperclocks.html 5 ps REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 3.3V ± 5% 1.8V ± 0.2V VDD VDD, VDDA Qx SCOPE nCLK0, nCLK1 VDDO V HSTL GND V Cross Points PP CMR CLK0, CLK1 nQx GND 0V DIFFERENTIAL INPUT LEVEL nQx nQ0:nQ4 nQ Q0:Q4 ➤ nQy Qy tcycle n ➤ 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT ➤ tcycle n+1 ➤ t jit(cc) = tcycle n –tcycle n+1 tsk(o) 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT SKEW nCLK0, nCLK1 CLK0, CLK1 VOH nFB_IN VOH VOL 80% VOD Clock Outputs VOL FB_IN ➤ ➤ t(Ø) 80% 20% 20% tR tF tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter t(Ø) mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) PHASE JITTER AND OUTPUT RISE/FALL TIME STATIC PHASE OFFSET nCLK0, nCLK1 nQ0:nQ4 Q0:Q4 CLK0, CLK1 t PW t odc = nQ0:nQ4 PERIOD t PW Q0:Q4 x 100% tPD t PERIOD PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8725AY-01 www.icst.com/products/hiperclocks.html 6 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8725-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10Ω V DDA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8725AY-01 www.icst.com/products/hiperclocks.html 7 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. HSTL OUTPUT All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 8725AY-01 www.icst.com/products/hiperclocks.html 8 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR LAYOUT GUIDELINE depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board. The schematic of the ICS8725-01 layout example is shown in Figure 4A. The ICS8725-01 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will VDD SP = Space (i.e. not intstalled) R7 RU2 SP RU3 1K RU4 1K RU5 SP RU6 1K VDD VDDA RU7 SP 10 C11 0.01u CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 RD4 SP RD5 1K RD6 SP RD7 1K Zo = 50 Ohm + SEL3 RD3 SP (155.5 MHz) PLL_SEL RD2 1K C16 10u VDD - VDDO LVHSTL_input U1 3.3V (155.5 MHz) SEL0 SEL1 Zo = 50 Ohm CLK_SEL R8 50 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO 3.3V PECL Driver 1 2 3 4 5 6 7 8 R9 50 8725_01 R10 50 R4A 50 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO R4B 50 24 23 22 21 20 19 18 17 VDD=3.3V VDDO=1.8V 9 10 11 12 13 14 15 16 Zo = 50 Ohm VDD PLL_SEL VDDA SEL3 GND Q4 nQ4 VDDO 32 31 30 29 28 27 26 25 Zo = 50 Ohm SEL[3:0] = 0101, Divide by 2 SEL2 R2B 50 R2A 50 Bypass capacitors located near the power pins (U1-9) VDD C1 0.1uF (U1-32) C6 0.1uF (U1-16) VDDO (U1-17) C2 0.1uF C4 0.1uF (U1-24) C5 0.1uF (U1-25) C7 0.1uF FIGURE 4A. ICS8725-01 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE 8725AY-01 www.icst.com/products/hiperclocks.html 9 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR The following component footprints are used in this layout example: trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING • The differential 50Ω output traces should have same length. Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. GND R7 C16 C11 C7 VDDO C6 C5 VDD U1 Pin 1 VDDA VIA 50 Ohm Traces C4 C1 C2 FIGURE 4B. PCB BOARD LAYOUT FOR ICS8725-01 8725AY-01 www.icst.com/products/hiperclocks.html 10 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8725-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8725-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (120mA + 15mA) = 468mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 32.8mW = 164mW Total Power_MAX (3.465V, with all outputs switching) = 468mW + 164mW = 632mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.632W * 42.1°C/W = 96.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 7. Thermal Resistance θJA for 32-pin LQFP, Forced Convection θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8725AY-01 www.icst.com/products/hiperclocks.html 11 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50Ω FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MIN Pd_L = (V OL_MAX L -V DDO_MAX /R ) * (V L DDO_MAX ) OH_MIN -V ) OL_MAX Pd_H = (1V/50Ω) * (2V - 1V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8725AY-01 www.icst.com/products/hiperclocks.html 12 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8725-01 is: 2969 8725AY-01 www.icst.com/products/hiperclocks.html 13 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8725AY-01 www.icst.com/products/hiperclocks.html 14 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8725AY-01 ICS8725AY-01 32 Lead LQFP tray 0°C to 70°C ICS8725AY-01T ICS8725AY-01 32 Lead LQFP 1000 tape & reel 0°C to 70°C ICS8725AY-01LF ICS8725AY01L 32 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS8725AY-01LFT ICS8725AY01L 32 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8725AY-01 www.icst.com/products/hiperclocks.html 15 REV. B NOVEMBER 15, 2005 ICS8725-01 Integrated Circuit Systems, Inc. 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR REVISION HISTORY SHEET Rev A A Table 6 3A 6 1 A A T1 T2 B T4D B B 8725AY-01 T10 Page 1 5 3 5 2 8 2 2 4 7 8 5 1 15 8 11-12 Description of Change Updated Block Diagram. Changed PLL Reference Zero Delay to Static Phase Offset. Added note at bottom of the table. Added Note 6. Pin Description Table - revised MR description. Updated Output Rise/Fall Time Diagram. Format changes. Changed LVHSTL to HSTL throughout data sheet to conform with JEDEC terminology. Pin Description table - revised MR and VDD descriptions. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - updated Inputs ratings. Added Power Supply Filtering Techniques section. Added Differential Input Interface section. Updated format throughout data sheet. HSTL table - changed VOX minimum to 40% and maximum to 60%; added NOTE 2. Features Section - add Lead-Free bullet. Ordering Information Table - added Lead-Free package and note. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. www.icst.com/products/hiperclocks.html 16 Date 11/2/01 11/20/01 8/22/02 9/26/03 11/11/04 6/9/05 11/15/05 REV. B NOVEMBER 15, 2005