ICS873034AG

ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TOLVPECL CLOCK DIVIDER General Description Features The ICS873034 is a high-speed, differential-toLVPECL clock divider designed for highHiPerClockS™ performance telecommunication, computing and networking applications. High clock frequency capability and the differential design make the ICS873034 an ideal choice for performance clock distribution networks. The device frequency-divides the input clock by ÷2, ÷4 and ÷8. Each frequency-divided clock signal is output at a separate LVPECL output. The differential input pair can be driven by LVPECL, LVDS, CML and SSTL signals, single-ended input signals are supported by using the integrated bias voltage generator (VBB). The ICS873034 is optimized for 3.3V and 2.5V power supply voltages and the temperature range of -40 to +85°C. The device is available in space-saving 16-lead TSSOP and SOIC packages. • • • • ÷2, ÷4 and ÷8 clock frequency divider • VBB bias voltage generator supports single-ended LVPECL clock input signals • • • LVCMOS control inputs • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V ICS • • Block Diagram nEN Pulldown Three differential LVPECL output pairs One differential PCLK/nPCLK input pair PCLK/nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Maximum input frequency: 2.8GHz Translates any single-ended input signal to 3.3V LVPECL levels with bias resistor on nPCLK input -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Q0 nQ0 VCC Q1 nQ1 VCC Q2 nQ2 D Q LE PCLK Pulldown nPCLK Pullup/Pulldown ÷2 Q0 nQ0 R ÷4 Q1 nQ1 R VBB ÷8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC nEN nc PCLK nPCLK VBB MR VEE ICS873034 Q2 16-Lead SOIC, 300 Mil 7.5mm x 10.3mm x 2.3mm package body M Package Top View nQ2 R MR Pulldown 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 1 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Table 1. Pin Descriptions Number Name 1, 2 nQ0, Q0 Type Description Output Differential output pair. LVPECL interface levels. 3, 6, 16 VCC Power Power supply pins. 4, 5 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 7, 8 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 9 VEE Power Negative supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 10 MR Input 11 VBB Output Pulldown Bias voltage. Inverting differential clock input. Defaults to 0.66 * VCC when left open. LVPECL interface levels. 12 nPCLK Input Pullup/ Pulldown 13 PCLK Input Pulldown Non-inverting differential clock input. LVPECL interface levels. 14 nc Unused Pulldown Synchronizing clock enable. When LOW, clock outputs follow clock input. When HIGH, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL / LVCMOS interface levels. 15 nEN Input No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions RPULLDOWN Input Pulldown Resistor RPULLUP Input Pullup Resistor Minimum Typical Maximum Units 75 kΩ 37.5 kΩ Function Table Table 3. Truth Table Inputs PCLK nEN MR Function ↓ L L Divide ↑ H L Hold Q[0:2] X X H Reset Q[0:2] ↑ = Rising edge transition ↓ = Falling edge transition X = Don’t care IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 2 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 6V (LVPECL mode, VEE = 0V) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA VBB Sink/Source, IBB ±0.5mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA 16 Lead SOIC, Junction-to-Ambient 16 Lead TSSOP, Junction-to-Ambient 82°C/W (0 mps) 103°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER Test Conditions 3 Minimum Typical Maximum Units 2.375 3.3 3.8 V 52 mA ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Table 4B. DC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V; TA = -40°C to 85°C -40°C Symbol Parameter VOH 25°C 80°C Min Typ Max Min Typ Max Min Typ Max Units Output High Voltage; NOTE 1 VCC-1.145 VCC-1.020 VCC-0.895 VCC-1.145 VCC-1.020 VCC-0.895 VCC-1.145 VCC-1.020 VCC-0.895 V VOL Output Low Voltage; NOTE 1 VCC-1.945 VCC-1.700 VCC-1.600 VCC-1.945 VCC-1.700 VCC-1.600 VCC-1.945 VCC-1.700 VCC-1.600 V VIH Input High Voltage (Single-ended) 0.7VCC VCC + 0.3 0.7VCC VCC + 0.3 0.7VCC VCC + 0.3 V VIL Input Low Voltage (Single-ended) -0.3 0.3VCC -0.3 0.3VCC -0.3 0.3VCC V VBB Output Voltage Reference VCC - 1.44 VCC - 1.32 VCC - 1.44 VCC - 1.32 VCC - 1.44 VCC - 1.32 V VPP Peak-to-Peak Input Voltage; NOTE 2 0.15 VCMR Input High Voltage Common Mode Range; NOTE 2, 3 1.2 IIH Input PCLK/ High nPCLK, Current MR, nEN IIL PCLK, Input MR, nEN Low Current nPCLK 800 0.15 VCC 800 1.2 0.15 VCC 150 1.2 150 800 V VCC V 150 µA -10 -10 -10 µA -150 -150 -150 µA Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: VIL cannot be less than -0.3V. NOTE 3: Common mode voltage is defined as VIH. IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 4 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER AC Electrical Characteristics Table 5. AC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V; TA = -40°C to 85°C -40°C Typ 25°C Symbol Parameter Min Max fMAX Output Frequency 2.8 tPD Propagation Delay; NOTE 1 410 tsk(o) Output Skew; NOTE 2 tRR Set/Reset Recovery tS Setup Time nEN 400 tH Hold Time nEN 200 tR / tF Output Rise/Fall Time 20% to 80% odc Output Duty Cycle Min Typ 510 320 48 Max 2.8 610 440 170 Min Typ 540 640 480 320 240 110 52 48 180 Units GHz 580 680 ps 50 ps 500 ps 400 400 ps 200 200 ps 255 ps 52 % 50 500 Max 2.8 50 105 80°C 500 320 245 120 52 48 200 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions All parameters are measured at f ≤ 2.5GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Output skew at coincident rising edges. IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 5 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Parameter Measurement Information 2V VCC VCC Qx SCOPE nPCLK V Cross Points PP V CMR PCLK LVPECL nQx VEE VEE -0.375V to -1.8V LVPECL Output Load AC Test Circuit Differential Input Level nPCLK nQx PCLK Qx nQ[0:2] nQy Q[0:2] Qy tPD tsk(o) Propagation Delay Output Skew nQ[0:2] PCLK Q[0:2] nPCLK t PW t nEN t SET-UP t HOLD odc = PERIOD t PW x 100% t PERIOD Setup and Hold Time IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER Output Duty Cycle 6 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Parameter Measurement Information, continued nQ[0:2] 80% 80% VSW I N G Q[0:2] 20% 20% tR tF Output Rise/Fall Time Application Information Recommendations for Unused Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 7 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Wiring the Differential Input to Accept Single-ended LVCMOS Levels negative input. The C1 capacitor should be located as close as possible to the input pin. Figure 1A shows an example of the differential input that can be wired to accept single-ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the VCC R1 1K Single Ended Clock Input PCLK V_REF C1 0.1u nPCLK R2 1K Figure 1A. Single-Ended LVCMOS Signal Driving Differential Input Wiring the Differential Input to Accept Single-ended LVPECL Levels negative input. The C1 capacitor should be located as close as possible to the input pin. Figure 1B shows an example of the differential input that can be wired to accept single-ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the VCC C1 0.1uF CLK_IN PCLK VBB nPCLK Figure 1B. Single-Ended LVPECL Signal Driving Differential Input IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 8 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER LVPECL Clock Input Interface most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK/nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50Ω R2 50 Zo = 50Ω PCLK R1 100 PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK HiPerClockS PCLK/nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup Figure 2B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 R3 84 3.3V LVPECL Zo = 50Ω Zo = 50Ω C1 Zo = 50Ω C2 R4 84 PCLK PCLK Zo = 50Ω nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120 R4 120 3.3V 3.3V Zo = 60Ω Zo = 50Ω PCLK PCLK Zo = 60Ω R1 100 nPCLK SSTL R1 120 R2 120 HiPerClockS PCLK/nPCLK Zo = 50Ω LVDS HiPerClockS Figure 2F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver Figure 2E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER nPCLK 9 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω Figure 3A. 3.3V LVPECL Output Termination IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER FIN 50Ω 84Ω Figure 3B. 3.3V LVPECL Output Termination 10 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 11 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Application Schematic Example Figure 5 shows an example of ICS873034 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. For the LVPECL output drivers, only two terminations examples are shown in this schematic. More termination approaches are shown in the LVPECL Termination Application Note. 3.3V 3.3V R1 133 U1 9 10 11 12 13 14 15 16 3.3V Zo = 50 Ohm Zo = 50 Ohm LVPECL R9 50 R8 50 VEE MR VBB nCLK CLK nc nEN VCC nQ2 Q2 VCC nQ1 Q1 VCC nQ0 Q0 8 7 6 5 4 3 2 1 R3 133 Zo = 50 Ohm + Zo = 50 Ohm - R2 82.5 R4 82.5 ICS873034 R10 50 Zo = 50 Ohm + Zo = 50 Ohm - (U1-3) 3.3V C1 0.1uF (U1-6) C2 0.1uF (U1-16) R5 50 C3 0.1uF Optional Y-Termination R6 50 R7 50 Figure 5. ICS873034 Application Schematic Example IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 12 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Power Considerations This section provides information on power dissipation and junction temperature for the ICS873034. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873034 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 52mA = 197.6mW • Power (outputs)MAX = 32.58mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 32.58mW =97.74mW Total Power_MAX (3.8V, with all outputs switching) = 197.6mW + 97.74mW = 295.34mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 103°C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.295W * 103°C/W = 115.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance θJA for 16 Lead SOIC Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 82.0°C/W 75.6°C/W 72.0°C/W 0 1 2.5 103.0°C/W 97.6°C/W 93.8°C/W Table 6B. Thermal Resistance θJA for 16 Lead TSSOP Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 13 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX –0.895V (VCC_MAX – VOH_MAX) = 0.895V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.895V)/50Ω] * 0.895V = 19.78mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.58mW IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 14 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Reliability Information Table 7A. θJA vs. Air Flow Table for an 16 Lead SOIC θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 82.0°C/W 75.6°C/W 72.0°C/W 0 1 2.5 103.0°C/W 97.6°C/W 93.8°C/W Table 7B. θJA vs. Air Flow Table for an 16 Lead TSSOP Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS873034 is: 280 Pin compatible with MC100LVEP34 IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 15 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Package Outlines and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Package Outline - M Suffix for 16 Lead SOIC A2 Table 8B. Package Dimensions Table 8A. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 10.10 10.50 E 7.40 7.60 e 1.27 Basic H 10.0 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MS-013, MS-119 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 16 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Ordering Information Table 9. Ordering Information Part/Order Number 873034AM 873034AMT 873034AMLF 873034AMLFT 873034AG 873034AGT 873034AGLF 873034AGFT Marking 873034AM 873034AM 873034AMLF 873034AMLF 873034AG 873034AG 873034AGL 873034AGL Package 16 Lead SOIC 16 Lead SOIC “Lead-Free” 16 Lead SOIC “Lead-Free” 16 Lead SOIC 16 Lead TSSOP 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVPECL/ECL CLOCK DIVIDER 17 ICS873034AM REV. A OCTOBER 31, 2008 ICS873034 LOW SKEW, ÷2, ÷4, ÷8 DIFFERENTIAL-TO- LVPECL CLOCK DIVIDER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA