PCI EXPRESS™ Jitter Attenuator
ICS874003-04
DATA SHEET
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
General Description
Features
The ICS874003-04 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some PCI
Express systems, such as those found in desktop PCs, the PCI
ExpressTM clocks are generated from a low bandwidth, high phase
noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and from
the system board. The ICS874003-04 has a bandwidth of 6.8MHz.
The 6.8MHz provides a high bandwidth that can easily track
triangular spread profiles, while providing jitter attenuation.
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•
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Three differential LVDS output pairs
•
•
•
•
•
•
•
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Input frequency range: 98MHz to 128MHz
•
Use replacement part: 874003BG-05LF
The ICS874003-04 uses IDT’s 3rd Generation FemtoClock™ PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 20 Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
One differential clock input
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 98MHz to 320MHz
VCO range: 490MHz - 640MHz
Supports PCI-Express Spread-Spectrum Clocking
High PLL bandwidth allows for better input tracking
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
F_SEL[2:0] Function Table
Inputs
Outputs
QA1
VDDO
QA0
nQA0
MR
F_SEL0
nc
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
VDDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
F_SEL2
F_SEL1
F_SEL0
QA[0:1], nQA[0:1]
QB, nQB0
0
0
0
÷2
÷2
1
0
0
÷5
÷2
0
1
0
÷4
÷2
1
1
0
÷2
÷4
ICS874003-04
0
0
1
÷2
÷5
1
0
1
÷5
÷4
0
1
1
÷4
÷5
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
1
1
1
÷4
÷4
ICS874003AG-04 REVISION B JANUARY 28, 2014
1
VDDA
F_SEL1
VDD
CLK
OEA
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Block Diagram
OEA
Pullup
F_SEL2:0 Pulldown
3
QA0
÷5
÷4
÷2 (default)
nQA0
QA1
CLK Pulldown
nCLK Pullup
Phase
Detector
VCO
nQA1
490 - 640MHz
3
÷5
÷4
÷2 (default)
M = ÷5 (fixed)
QB0
nQB0
MR Pulldown
OEB
Pullup
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
Name
1, 20
QA1, nQA1
Output
Type
Description
Differential output pair. LVDS interface levels.
2, 19
VDDO
Power
Output supply pins.
3, 4
QA0, nQA0
Output
Differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
6,
9,
16
F_SEL0,
F_SEL1,
F_SEL2
Input
Pulldown
Frequency select pin for QAx, nQAx and QB0, nQB0 outputs. LVCMOS/LVTTL
interface levels.
7
nc
Unused
No connect.
8
VDDA
Power
Analog supply pin.
10
VDD
Power
Core supply pin.
11
OEA
Input
Pullup
12
CLK
Input
Pulldown
13
nCLK
Input
Pullup
14
GND
Power
15
OEB
Input
17, 18
nQB0, QB0
Output
Output enable pin for QA pins. When HIGH, the QAx, nQAx outputs are active.
When LOW, the QAx, nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Pullup
Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active.
When LOW, the QB0, nQB0 outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
Table 3. Output Enable Function Table
Inputs
Outputs
OEx
Qx[0:1], nQx[0:1]
0
Hi-Impedance
1
Enabled
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
86.7°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Positive Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.16
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
74
mA
IDDA
Analog Supply Current
16
mA
IDDO
Output Supply Current
76
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
OEA, OEB
VDD = VIN = 3.465V
5
µA
F_SEL0, F_SEL1,
F_SEL2, MR
VDD = VIN = 3.465V
150
µA
OEA, OEB
VDD = 3.465V, VIN = 0V
-150
µA
F_SEL0, F_SEL1,
F_SEL2, MR
VDD = 3.465V, VIN = 0V
-5
µA
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
IIH
Input High Current
IIL
Test Conditions
Minimum
Typical
Maximum
Units
CLK
VDD = VIN = 3.465V
150
µA
nCLK
VDD = VIN = 3.465V
5
µA
CLK
VDD = 3.465V,
VIN = 0V
-5
µA
nCLK
VDD = 3.465V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
275
375
485
mV
50
mV
1.50
V
50
mV
1.20
1.35
Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tjit(cc)
tsk(o)
Maximum
Units
320
MHz
Cycle-to-Cycle Jitter; NOTE 1
35
ps
Output Skew; NOTE 1, 2
135
ps
tsk(b)
Bank Skew; NOTE 1, 3
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
98
Bank A
20% to 80%
Typical
50
ps
215
550
ps
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information
VDD
nCLK
3.3V ±5%
VDD,
V
V
Cross Points
PP
VDDO
CMR
CLK
VDDA
GND
Differential Input Level
3.3V LVDS Output Load AC Test Circuit
nQA0
nQAx, nQB0
QA0
QAx, QB0
tcycle n
nQA1
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
QA1
tsk(b)
Cycle-to-Cycle Jitter
Bank Skew
nQx
nQAx, nQB0
Qx
QAx, QB0
nQy
Qy
Output Duty Cycle/Pulse Width/Period
Output Skew
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information, continued
nQAx, nQB0
80%
80%
VOD
QAx, QB0
20%
20%
tR
tF
Output Rise/Fall Time
Offset Voltage Setup
Differential Output Voltage Setup
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The ICS874003-04 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Differential Clock Input Interface
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. The differential signal must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
Differential
Input
LVPECL
R2
50Ω
R1
50Ω
R2
50Ω
R2
50Ω
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3A. HiPerClockS CLK/nCLK Input Driven by an IDT
Open Emitter HiPerClockS LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
120Ω
R4
120Ω
Zo = 60Ω
*R3
CLK
CLK
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
SSTL
Differential
Input
R1
120Ω
Differential
Input
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
ICS874003AG-04 REVISION B JANUARY 28, 2014
R2
120Ω
9
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential
transmission line environment, LVDS drivers require a matched load
termination of 100 across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Schematic Example
Figure 5 shows an example of ICS874003-04 application schematic.
In this example, the device is operated at VDD = 3.3V. The decoupling
capacitors should be located as close as possible to the power pin.
Two examples of LVDS terminations are shown in this schematic.
The input is driven either by a 3.3V LVPECL driver or a 3.3V
LVCMOS.
ICS874003-04
Figure 5. ICS874003-04 Schematic Example
ICS874003AG-04 REVISION B JANUARY 28, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS874003-04.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS74003-04 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (74mA + 16mA) = 311.85mW
•
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 76mA = 263.34mW
Total Power_MAX = 311.85mW + 263.34mW = 575.19mW
•
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.575W * 86.7°C/W = 119.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS874003AG-04 REVISION B JANUARY 28, 2014
0
1
2.5
86.7°C/W
82.4°C/W
80.2°C/W
12
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
86.7°C/W
82.4°C/W
80.2°C/W
Transistor Count
The transistor count for ICS874003-04 is: 1,416
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8 Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS874003AG-04 REVISION B JANUARY 28, 2014
13
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Revision History Sheet
Rev
B
Table
Page
Description of Change
Date
Product Discontinuation Notice - Last Time Buy Expires January 27, 2015, PDN# CQ-14-02
ICS874003AG-04 REVISION B JANUARY 28, 2014
14
1/28/14
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Ordering Information
Table 9. Ordering Information
Part/Order Number
874003AG-04
874003AG-04T
874003AG-04LF
874003AG-04LFT
Marking
ICS874003A04
ICS874003A04
ICS74003A04L
ICS74003A04L
Package
20 Lead TSSOP
20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
0C to 70C
0C to 70C
0C to 70C
0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS874003AG-04 REVISION B JANUARY 28, 2014
15
©2014 Integrated Device Technology, Inc.
ICS874003-04 Data Sheet
6024 Silver Creek Valley Road
San Jose, California 95138
PCI EXPRESS™ JITTER ATTENUATOR
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com
+480-763-2056
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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
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