ICS874S02BMI

874S02I 1:1 Differential-to-LVDS Zero Delay Clock Generator Description Features The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • • • • • • • • • • • • • Block Diagram One differential LVDS output pair and one differential feedback output pair One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL Input frequency range: 62.5MHz to 1GHz Output frequency range: 62.5MHz to 1GHz VCO range: 500MHz – 1GHz External feedback for "zero delay" clock regeneration with configurable frequencies Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Cycle-to-cycle jitter: 35ps (maximum) Static phase offset: ±100ps Full 3.3V supply mode -40°C to +85°C ambient operating temperature Available in lead-free packages Pin Assignment PLL_SEL Pullup 0 Q nQ 1 QFB nQFB ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 CLK Pulldown nCLK Pullup PLL FB_IN Pulldown nFB_IN Pullup Datasheet 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q nQ VDDO 874S02I 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR Pulldown ©2021 Renesas Electronics Corporation 1 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Table 1. Pin Descriptions Number Name 1 CLK Input Type Pulldown 2 nCLK Input Pullup Description Non-inverting differential clock input. Inverting differential clock input. 3 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Q and QFB to go low and the inverted outputs nQ and nQFB to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 4 nFB_IN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with “Zero Delay.” Connect to pin 8. 5 FB_IN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with “Zero Delay.” Connect to pin 9. 6, 15, 19, 20 SEL2, SEL3, SEL0, SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 7, 11 VDDO Power Output supply pins. 8, 9 nQFB, QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ, Q Output Differential clock output pair. LVDS interface levels. 16 VDDA Power Analog supply pin. 17 PLL_SEL Input 18 VDD Power Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. Core supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 50 k 50 k RPULLDOWN Input Pulldown Resistor ©2021 Renesas Electronics Corporation 2 Minimum Typical Maximum Units R31DS0061EU0101 July 6, 2021 874S02I Datasheet Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/nQ 0 0 0 0 500 - 1000 ÷1 0 0 0 1 250 - 500 ÷1 0 0 1 0 125 - 250 ÷1 0 0 1 1 62.5 - 125 ÷1 0 1 0 0 500 - 1000 ÷2 0 1 0 1 250 - 500 ÷2 0 1 1 0 125 - 250 ÷2 0 1 1 1 500 - 1000 ÷4 1 0 0 0 250 - 500 ÷4 1 0 0 1 500 - 1000 ÷8 1 0 1 0 250 - 500 x2 1 0 1 1 125 - 250 x2 1 1 0 0 62.5 - 125 x2 1 1 0 1 125 - 250 x4 1 1 1 0 62.5 - 125 x4 1 1 1 1 62.5 - 125 x8 *NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz. ©2021 Renesas Electronics Corporation 3 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q/nQ 0z 0 0 0 ÷4 0 0 0 1 ÷4 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷16 0 1 1 1 ÷16 1 0 0 0 ÷32 1 0 0 1 ÷64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 ©2021 Renesas Electronics Corporation 4 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 64.7°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.20 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 97 mA IDDA Analog Supply Current 20 mA IDDO Output Supply Current 40 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V MR, SEL[0:3] VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 10 µA MR, SEL[0:3] VDD = 3.465V, VIN = 0V -10 µA PLL_SEL VDD = 3.465V, VIN = 0V -150 µA ©2021 Renesas Electronics Corporation 5 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK, FB_IN VDD = VIN = 3.465V 150 µA nCLK, nFB_IN VDD = VIN = 3.465V 10 µA CLK, FB_IN VDD = 3.465V, VIN = 0V -10 µA nCLK, nFB_IN VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Minimum Typical Maximum Units 350 450 550 mV 50 mV 1.45 V 50 mV 1.20 1.33 Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter FIN Input Frequency CLK/nCLK Test Conditions Minimum PLL_SEL = 1 62.5 Typical PLL_SEL = 0 Maximum Units 1000 MHz 1000 MHz Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Parameter Symbol fOUT Output Frequency tsk(Ø) Static Phase Offset; NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions PLL_SEL = 1 20% to 80% Minimum Maximum Units 62.5 Typical 1000 MHz -100 100 ps 35 ps 1 ms 50 250 ps 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. ©2021 Renesas Electronics Corporation 6 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Parameter Measurement Information VDD nCLK VDD, 3.3V ±5% V V Cross Points PP VDDO VDDA CMR CLK GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nCLK VOH CLK VOL nFB_IN nQ, nQFB Q, QFB VOH FB_IN VOL tcycle n ➤ ➤ t(Ø) tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles tjit(Ø) = t(Ø) – t(Ø) mean = Phase Jitter t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges) Static Phase Offset Cycle-to-Cycle Jitter nQ, nQFB nQ, nQFB 80% 80% Q, QFB VOD Q, QFB 20% 20% tR tF Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time ©2021 Renesas Electronics Corporation 7 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup Application Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. ©2021 Renesas Electronics Corporation 8 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 874S02I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10 .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input ©2021 Renesas Electronics Corporation 9 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Differential Clock Input Interface component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver 3.3V 1.8V Zo = 50 CLK Zo = 50 nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50 R2 50 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120 R4 120 Zo = 60 CLK Zo = 60 nCLK SSTL R1 120 R2 120 Differential Input Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver ©2021 Renesas Electronics Corporation 10 R31DS0061EU0101 July 6, 2021 874S02I Datasheet 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50 3.3V LVDS Driver + R1 100 – 50 100 Differential Transmission Line Figure 4. Typical LVDS Driver Termination Schematic Example The schematic of the 874S02I layout example is shown in Figure 5A. The 874S02I recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types and the density of the P.C. board. 3.3V (155.52 MHz) U1 Zo = 50 Ohm Zo = 50 Ohm SEL2 VDDO 3.3V PECL Driv er R8 50 R9 50 R2 100 SP = Space (i.e. not intstalled) RU4 1K RU5 SP RU6 1K RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 RD3 SP RD4 SP CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND SEL1 SEL0 VDDI PLL_SEL VDDA SEL3 GND Q nQ VDDO 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 RD5 1K RD6 SP RD7 1K C1 0.1uF R7 C11 0.01u VDDO VDD 10 C16 10u ICS8745B-21 (77.76 MHz) R10 50 VDD RU3 1K 1 2 3 4 5 6 7 8 9 10 + Bypass capacitors located near the power pins (U1-7) VDDO C4 0.1uF R4 100 VDD=3.3V (U1-11) - LVDS_input VDDO=3.3V C2 0.1uF Zo = 100 Ohm Dif f erential SEL[3:0] = 0101, Divide by 2 Figure 5A. 874S02I LVDS Zero Delay Buffer Schematic Example The following component footprints are used in this layout ©2021 Renesas Electronics Corporation example. 11 R31DS0061EU0101 July 6, 2021 874S02I Datasheet trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • The 100 differential output traces should have the same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. U1 ICS8745B-21 GND VDDO C1 VDD C16 VDDA C11 VIA C4 R7 100 Ohm Differential Traces C2 Figure 5B. PCB Board Layout for 874S02I ©2021 Renesas Electronics Corporation 12 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 874S02I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 874S02I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • The maximum current at 85°C is as follows: IDD_MAX = 93mA IDDA_MAX = 19mA IDDO_MAX = 36mA • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (93mA + 19mA) = 388.08mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 36mA = 124.74mW Total Power_MAX = 388.08mW + 124.74mW = 512.82mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.513W * 64.7°C/W = 118.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 7. Thermal Resistance JA for 20 Lead SOIC, Forced Convection JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards ©2021 Renesas Electronics Corporation 0 200 500 64.7°C/W 56.7°C/W 53.5°C/W 13 R31DS0061EU0101 July 6, 2021 874S02I Datasheet Reliability Information Table 8. JA vs. Air Flow Table for a 20 Lead SOIC JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 64.7°C/W 56.7°C/W 53.5°C/W Transistor Count The transistor count for 874S02I is: 1358 Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website (see Ordering Information for POD links). The package information is the most current data available and is subject to change without revision of this document. Ordering Information Table 10. Ordering Information Part/Order Number 874S02BMILF 874S02BMILFT Marking ICS874S02BMILF ICS874S02BMILF Package Lead-Free, 20 Lead SOIC Lead-Free, 20 Lead SOIC Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C Revision History Revision Date July 6, 2021 January 26, 2016 Description of Change ▪ Updated pin descriptions for pins 8, 9 and 12, 13. ▪ Updated Package Outline Drawings section. ▪ ▪ ▪ ▪ Removed ICS from the part number where needed. General Description - Removed ICS Chip and HiPerClockS. Ordering Information - removed quantity from tape and reel. Updated data sheet header and footer. ©2021 Renesas Electronics Corporation 14 R31DS0061EU0101 July 6, 2021 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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